diff options
Diffstat (limited to 'binutils-2.25/gas/testsuite/gas/arm')
743 files changed, 33685 insertions, 0 deletions
diff --git a/binutils-2.25/gas/testsuite/gas/arm/abs12.d b/binutils-2.25/gas/testsuite/gas/arm/abs12.d new file mode 100644 index 00000000..d1ccf967 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/abs12.d @@ -0,0 +1,20 @@ +#objdump: -dr +#not-skip: *-vxworks + +.*: file format .* + +Disassembly of section \.text: + +00000000 <.*>: + 0: e5910000 ldr r0, \[r1\] + 0: R_ARM_ABS12 global + 4: e5910000 ldr r0, \[r1\] + 4: R_ARM_ABS12 global\+0xc + 8: e5910000 ldr r0, \[r1\] + 8: R_ARM_ABS12 global\+0x100000 + c: e5910000 ldr r0, \[r1\] + c: R_ARM_ABS12 \.text\+0x18 + 10: e5910000 ldr r0, \[r1\] + 10: R_ARM_ABS12 \.text\+0x24 + 14: e5910000 ldr r0, \[r1\] + 14: R_ARM_ABS12 \.text\+0x100018 diff --git a/binutils-2.25/gas/testsuite/gas/arm/abs12.s b/binutils-2.25/gas/testsuite/gas/arm/abs12.s new file mode 100644 index 00000000..9c2faa55 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/abs12.s @@ -0,0 +1,7 @@ + ldr r0,[r1,#global] + ldr r0,[r1,#global + 12] + ldr r0,[r1,#global + 0x100000] + ldr r0,[r1,#local] + ldr r0,[r1,#local + 12] + ldr r0,[r1,#local + 0x100000] +local: diff --git a/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.d b/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.d new file mode 100644 index 00000000..68657025 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.d @@ -0,0 +1,3 @@ +#name: Invalid Immediate field for flag-setting add,sub +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#error-output: addsw-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.l b/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.l new file mode 100644 index 00000000..fa62b95a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:5: Error: invalid constant \(496\) after fixup +[^:]*:6: Error: invalid constant \(496\) after fixup diff --git a/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.s b/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.s new file mode 100644 index 00000000..69013be8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/addsw-bad.s @@ -0,0 +1,6 @@ +.text +.thumb +.cpu cortex-a8 +.syntax unified +subs r4, r6, #0x496 +adds r4, r6, #0x496 diff --git a/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.d b/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.d new file mode 100644 index 00000000..46532f36 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.d @@ -0,0 +1,7 @@ +#name: bad Thumb2 Add{S} and Sub{S} instructions +#as: -march=armv7-a +#error-output: addthumb2err.l + +# Test some Thumb2 instructions: + +.*: +file format .*arm.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.l b/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.l new file mode 100644 index 00000000..c77d551c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:9: Error: shift value over 3 not allowed in thumb mode -- `add sp,sp,r0,LSL#4' +[^:]*:10: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,LSR#3' +[^:]*:11: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ASR#3' +[^:]*:12: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,ROR#3' +[^:]*:13: Error: only LSL shift allowed in thumb mode -- `add sp,sp,r0,RRX' +[^:]*:14: Error: shift value over 3 not allowed in thumb mode -- `adds sp,sp,r0,LSL#4' +[^:]*:15: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,LSR#3' +[^:]*:16: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ASR#3' +[^:]*:17: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,ROR#3' +[^:]*:18: Error: only LSL shift allowed in thumb mode -- `adds sp,sp,r0,RRX' +[^:]*:19: Error: shift value over 3 not allowed in thumb mode -- `sub sp,sp,r0,LSL#4' +[^:]*:20: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,LSR#3' +[^:]*:21: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ASR#3' +[^:]*:22: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,ROR#3' +[^:]*:23: Error: only LSL shift allowed in thumb mode -- `sub sp,sp,r0,RRX' +[^:]*:24: Error: shift value over 3 not allowed in thumb mode -- `subs sp,sp,r0,LSL#4' +[^:]*:25: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,LSR#3' +[^:]*:26: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ASR#3' +[^:]*:27: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,ROR#3' +[^:]*:28: Error: only LSL shift allowed in thumb mode -- `subs sp,sp,r0,RRX' diff --git a/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.s b/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.s new file mode 100644 index 00000000..139c1955 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/addthumb2err.s @@ -0,0 +1,28 @@ + .syntax unified + .text + .align 2 + .thumb + + # Test of invalid operands for ADD{S} and SUB{S} instructions + # in Thumb2 mode. The instruction form being testing + # involves having the first 2 operands be SP. + add sp, sp, r0, LSL #4 + add sp, sp, r0, LSR #3 + add sp, sp, r0, ASR #3 + add sp, sp, r0, ROR #3 + add sp, sp, r0, RRX + adds sp, sp, r0, LSL #4 + adds sp, sp, r0, LSR #3 + adds sp, sp, r0, ASR #3 + adds sp, sp, r0, ROR #3 + adds sp, sp, r0, RRX + sub sp, sp, r0, LSL #4 + sub sp, sp, r0, LSR #3 + sub sp, sp, r0, ASR #3 + sub sp, sp, r0, ROR #3 + sub sp, sp, r0, RRX + subs sp, sp, r0, LSL #4 + subs sp, sp, r0, LSR #3 + subs sp, sp, r0, ASR #3 + subs sp, sp, r0, ROR #3 + subs sp, sp, r0, RRX diff --git a/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.d b/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.d new file mode 100644 index 00000000..d8043dc7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.d @@ -0,0 +1,2 @@ +# name: Invalid use of ADR and ADRL +# error-output: adr-invalid.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.l b/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.l new file mode 100644 index 00000000..817646e9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: symbol var is in a different section +[^:]*:4: Error: undefined symbol undefinedvar used as an immediate value +[^:]*:5: Error: symbol var is in a different section +[^:]*:6: Error: undefined symbol undefinedvar used as an immediate value diff --git a/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.s b/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.s new file mode 100644 index 00000000..8ff38601 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adr-invalid.s @@ -0,0 +1,12 @@ + .text +start: + adr r0, var + adr r0, undefinedvar + adrl r1, var + adrl r1, undefinedvar + + .data + .globl var +var: + .word 0x00000000 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/adr.d b/binutils-2.25/gas/testsuite/gas/arm/adr.d new file mode 100644 index 00000000..ee74154c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adr.d @@ -0,0 +1,9 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ADR + +# Test the `ADR' pseudo-op + +.*: +file format .*arm.* + +Disassembly of section .text: +0+ <.*> 824ff203 subhi pc, pc, #805306368 ; 0x30000000 diff --git a/binutils-2.25/gas/testsuite/gas/arm/adr.s b/binutils-2.25/gas/testsuite/gas/arm/adr.s new file mode 100644 index 00000000..5d8ea2bd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adr.s @@ -0,0 +1,5 @@ + @ test ADR pseudo-op + .text + .global foo +foo: + adrhi pc, . - 0x2ffffff8 diff --git a/binutils-2.25/gas/testsuite/gas/arm/adrl.d b/binutils-2.25/gas/testsuite/gas/arm/adrl.d new file mode 100644 index 00000000..6276e8d2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adrl.d @@ -0,0 +1,27 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ADRL + +# Test the `ADRL' pseudo-op + +.*: +file format .*arm.* + +Disassembly of section .text: + ... +0+2000 <.*> e24f0008 sub r0, pc, #8 +0+2004 <.*> e2400c20 sub r0, r0, #32, 24 ; 0x2000 +0+2008 <.*> e28f0020 add r0, pc, #32 +0+200c <.*> e2800c20 add r0, r0, #32, 24 ; 0x2000 +0+2010 <.*> e24f0018 sub r0, pc, #24 +0+2014 <.*> e1a00000 nop ; \(mov r0, r0\) +0+2018 <.*> e28f0008 add r0, pc, #8 +0+201c <.*> e1a00000 nop ; \(mov r0, r0\) +0+2020 <.*> 028f0000 addeq r0, pc, #0 +0+2024 <.*> e1a00000 nop ; \(mov r0, r0\) +0+2028 <.*> e24f0030 sub r0, pc, #48 ; 0x30 +0+202c <.*> e2400c20 sub r0, r0, #32, 24 ; 0x2000 +0+2030 <.*> e28f0c21 add r0, pc, #8448 ; 0x2100 +0+2034 <.*> e1a00000 nop ; \(mov r0, r0\) + ... +0+4030 <.*> e28fec01 add lr, pc, #256 ; 0x100 + ... + ... diff --git a/binutils-2.25/gas/testsuite/gas/arm/adrl.s b/binutils-2.25/gas/testsuite/gas/arm/adrl.s new file mode 100644 index 00000000..5bb7456f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/adrl.s @@ -0,0 +1,24 @@ + @ test ADRL pseudo-op + .text + .global foo +foo: + .align 0 +1: + .space 8192 +2: + adrl r0, 1b + adrl r0, 1f + adrl r0, 2b + adrl r0, 2f + adrEQl r0, 2f +2: + adrl r0, foo + adrl r0, X + .space 8184 +1: + adral lr, X + .space 0x0104 + + .globl X; +X: + .p2align 5,0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/align.d b/binutils-2.25/gas/testsuite/gas/arm/align.d new file mode 100644 index 00000000..a15ed8c1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/align.d @@ -0,0 +1,26 @@ +# name: ARM V6t2 Alignment +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> bf00 nop +0+002 <[^>]*> 4611 mov r1, r2 +0+004 <[^>]*> f3af 8000 nop.w +0+008 <[^>]*> f3af 8000 nop.w +0+00c <[^>]*> f3af 8000 nop.w +0+010 <[^>]*> 4611 mov r1, r2 +0+012 <[^>]*> bf00 nop +0+014 <[^>]*> f3af 8000 nop.w +0+018 <[^>]*> e320f000 nop \{0\} +0+01c <[^>]*> e1a01002 mov r1, r2 +0+020 <[^>]*> e1a01002 mov r1, r2 +0+024 <[^>]*> e320f000 nop \{0\} +0+028 <[^>]*> e320f000 nop \{0\} +0+02c <[^>]*> e320f000 nop \{0\} +0+030 <[^>]*> e320f000 nop \{0\} +0+034 <[^>]*> e320f000 nop \{0\} +0+038 <[^>]*> e320f000 nop \{0\} +0+03c <[^>]*> e320f000 nop \{0\} diff --git a/binutils-2.25/gas/testsuite/gas/arm/align.s b/binutils-2.25/gas/testsuite/gas/arm/align.s new file mode 100644 index 00000000..7ed8fbb8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/align.s @@ -0,0 +1,18 @@ + .syntax unified + .thumb + .global foo +foo: + nop + mov r1,r2 + .p2align 4 + mov r1,r2 + .p2align 3 + + .arm + .global bar +bar: + nop + mov r1,r2 + .p2align 4 + mov r1,r2 + .p2align 5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/align64.d b/binutils-2.25/gas/testsuite/gas/arm/align64.d new file mode 100644 index 00000000..cee7442d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/align64.d @@ -0,0 +1,69 @@ +# name: 64 Bytes alignment test +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <foo> f04f 0001.*mov.w.*r0, #1 +00000004 <foo\+0x4> 46c0.*nop.* +00000006 <foo\+0x6> 46c0.*nop.* +00000008 <foo\+0x8> 46c0.*nop.* +0000000a <foo\+0xa> 46c0.*nop.* +0000000c <foo\+0xc> 46c0.*nop.* +0000000e <foo\+0xe> 46c0.*nop.* +00000010 <foo\+0x10> 46c0.*nop.* +00000012 <foo\+0x12> 46c0.*nop.* +00000014 <foo\+0x14> 46c0.*nop.* +00000016 <foo\+0x16> 46c0.*nop.* +00000018 <foo\+0x18> 46c0.*nop.* +0000001a <foo\+0x1a> 46c0.*nop.* +0000001c <foo\+0x1c> 46c0.*nop.* +0000001e <foo\+0x1e> 46c0.*nop.* +00000020 <foo\+0x20> 46c0.*nop.* +00000022 <foo\+0x22> 46c0.*nop.* +00000024 <foo\+0x24> 46c0.*nop.* +00000026 <foo\+0x26> 46c0.*nop.* +00000028 <foo\+0x28> 46c0.*nop.* +0000002a <foo\+0x2a> 46c0.*nop.* +0000002c <foo\+0x2c> 46c0.*nop.* +0000002e <foo\+0x2e> 46c0.*nop.* +00000030 <foo\+0x30> 46c0.*nop.* +00000032 <foo\+0x32> 46c0.*nop.* +00000034 <foo\+0x34> 46c0.*nop.* +00000036 <foo\+0x36> 46c0.*nop.* +00000038 <foo\+0x38> 46c0.*nop.* +0000003a <foo\+0x3a> 46c0.*nop.* +0000003c <foo\+0x3c> 46c0.*nop.* +0000003e <foo\+0x3e> 46c0.*nop.* +00000040 <foo\+0x40> f04f 0002.*mov.w.*r0, #2 +00000044 <foo2> e3a00003.*mov.*r0, #3 +00000048 <foo2\+0x4> e1a00000.*nop.* +0000004c <foo2\+0x8> e1a00000.*nop.* +00000050 <foo2\+0xc> e1a00000.*nop.* +00000054 <foo2\+0x10> e1a00000.*nop.* +00000058 <foo2\+0x14> e1a00000.*nop.* +0000005c <foo2\+0x18> e1a00000.*nop.* +00000060 <foo2\+0x1c> e1a00000.*nop.* +00000064 <foo2\+0x20> e1a00000.*nop.* +00000068 <foo2\+0x24> e1a00000.*nop.* +0000006c <foo2\+0x28> e1a00000.*nop.* +00000070 <foo2\+0x2c> e1a00000.*nop.* +00000074 <foo2\+0x30> e1a00000.*nop.* +00000078 <foo2\+0x34> e1a00000.*nop.* +0000007c <foo2\+0x38> e1a00000.*nop.* +00000080 <foo2\+0x3c> e3a00004.*mov.*r0, #4 +00000084 <foo2\+0x40> e1a00000.*nop.* +00000088 <foo2\+0x44> e1a00000.*nop.* +0000008c <foo2\+0x48> e1a00000.*nop.* +00000090 <foo2\+0x4c> e1a00000.*nop.* +00000094 <foo2\+0x50> e1a00000.*nop.* +00000098 <foo2\+0x54> e1a00000.*nop.* +0000009c <foo2\+0x58> e1a00000.*nop.* +000000a0 <foo2\+0x5c> e1a00000.*nop.* +000000a4 <foo2\+0x60> e1a00000.*nop.* +000000a8 <foo2\+0x64> e1a00000.*nop.* +000000ac <foo2\+0x68> e1a00000.*nop.* +000000b0 <foo2\+0x6c> e1a00000.*nop.* +000000b4 <foo2\+0x70> e1a00000.*nop.* +000000b8 <foo2\+0x74> e1a00000.*nop.* +000000bc <foo2\+0x78> e1a00000.*nop.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/align64.s b/binutils-2.25/gas/testsuite/gas/arm/align64.s new file mode 100644 index 00000000..17135616 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/align64.s @@ -0,0 +1,12 @@ +.syntax unified +.thumb +foo: + mov r0, #1 +.p2align 6,,63 + mov r0, #2 + +.arm +foo2: + mov r0, #3 +.p2align 6,,63 + mov r0, #4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/any-idiv.d b/binutils-2.25/gas/testsuite/gas/arm/any-idiv.d new file mode 100644 index 00000000..3b91c16c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/any-idiv.d @@ -0,0 +1,11 @@ +# name: attributes for 'any' CPU with Thumb integer divide +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v7 + Tag_THUMB_ISA_use: Thumb-2 + Tag_DIV_use: Allowed in v7-A with integer division extension diff --git a/binutils-2.25/gas/testsuite/gas/arm/any-idiv.s b/binutils-2.25/gas/testsuite/gas/arm/any-idiv.s new file mode 100644 index 00000000..bdbe9c4a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/any-idiv.s @@ -0,0 +1,4 @@ + .syntax unified + .text + .thumb + udiv r0, r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch4t-eabi.d b/binutils-2.25/gas/testsuite/gas/arm/arch4t-eabi.d new file mode 100644 index 00000000..ad2701d4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch4t-eabi.d @@ -0,0 +1,39 @@ +# name: ARM architecture 4t instructions (EABI) +# as: -march=armv4t +# objdump: -dr --prefix-addresses --show-raw-insn +# source: arch4t.s +# target: *-*-*eabi* *-*-symbianelf *-*-nacl* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e12fff10 ? bx r0 +.*: R_ARM_V4BX.* +0+04 <[^>]+> 012fff11 ? bxeq r1 +.*: R_ARM_V4BX.* +0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> +0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] +0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] +0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! +0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] +0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 +0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 +0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].* +0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* +0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* +0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] +0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 +0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 +0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 +0+44 <[^>]+> e124f005 ? msr CPSR_s, r5 +0+48 <[^>]+> e128f006 ? msr CPSR_f, r6 +0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7 +0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 +0+54 <[^>]+> e161f008 ? msr SPSR_c, r8 +0+58 <[^>]+> e162f009 ? msr SPSR_x, r9 +0+5c <[^>]+> e164f00a ? msr SPSR_s, sl +0+60 <[^>]+> e168f00b ? msr SPSR_f, fp +0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip +0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch4t.d b/binutils-2.25/gas/testsuite/gas/arm/arch4t.d new file mode 100644 index 00000000..a49ae0b1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch4t.d @@ -0,0 +1,38 @@ +# name: ARM architecture 4t instructions +# as: -march=armv4t +# objdump: -dr --prefix-addresses --show-raw-insn +# EABI targets have their own variant. +# not-target: *-*-*eabi* *-*-symbianelf *-*-nacl* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e12fff10 ? bx r0 +0+04 <[^>]+> 012fff11 ? bxeq r1 +0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> +0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] +0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] +0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! +0+18 <[^>]+> 011510d3 ? ldrsbeq r1, \[r5, -r3\] +0+1c <[^>]+> 109620b7 ? ldrhne r2, \[r6\], r7 +0+20 <[^>]+> 309720f8 ? ldrshcc r2, \[r7\], r8 +0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\].* +0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\].* +0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\].* +0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> +0+34 <[^>]+> 11c330b0 ? strhne r3, \[r3\] +0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 +0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 +0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 +0+44 <[^>]+> e124f005 ? msr CPSR_s, r5 +0+48 <[^>]+> e128f006 ? msr CPSR_f, r6 +0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7 +0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 +0+54 <[^>]+> e161f008 ? msr SPSR_c, r8 +0+58 <[^>]+> e162f009 ? msr SPSR_x, r9 +0+5c <[^>]+> e164f00a ? msr SPSR_s, sl +0+60 <[^>]+> e168f00b ? msr SPSR_f, fp +0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip +0+68 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+6c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch4t.s b/binutils-2.25/gas/testsuite/gas/arm/arch4t.s new file mode 100644 index 00000000..984829d8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch4t.s @@ -0,0 +1,38 @@ + .text + .align 0 +l: + bx r0 + bxeq r1 + +foo: + ldrh r3, foo + ldrsh r4, [r5] + ldrsb r4, [r1, r3] + ldrsh r1, [r4, r4]! + ldreqsb r1, [r5, -r3] + ldrneh r2, [r6], r7 + ldrccsh r2, [r7], +r8 + ldrsb r2, [r3, #255] + ldrsh r1, [r4, #-250] + ldrsb r1, [r5, #+240] + + strh r2, bar + strneh r3, [r3] + + msr CPSR_f, #2 + msr CPSR_c, r3 + msr CPSR_x, r4 + msr CPSR_s, r5 + msr CPSR_f, r6 + msr CPSR_all, r7 + + msr SPSR_f, #4 + msr SPSR_c, r8 + msr SPSR_x, r9 + msr SPSR_s, r10 + msr SPSR_f, r11 + msr SPSR_all, r12 +bar: + @ section padding for a.out's benefit + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch5tej.d b/binutils-2.25/gas/testsuite/gas/arm/arch5tej.d new file mode 100644 index 00000000..49d2cbbe --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch5tej.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM Architecture v5TEJ instructions +#as: -march=armv5tej + +# Test the ARM Architecture v5TEJ instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> e12fff20 ? bxj r0 +0+04 <[^>]*> e12fff21 ? bxj r1 +0+08 <[^>]*> e12fff2e ? bxj lr +0+0c <[^>]*> 012fff20 ? bxjeq r0 +0+10 <[^>]*> 412fff20 ? bxjmi r0 +0+14 <[^>]*> 512fff27 ? bxjpl r7 +0+18 <[^>]*> e1200070 ? bkpt 0x0000 +0+1c <[^>]*> e120007a ? bkpt 0x000a diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch5tej.s b/binutils-2.25/gas/testsuite/gas/arm/arch5tej.s new file mode 100644 index 00000000..4624b7e1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch5tej.s @@ -0,0 +1,12 @@ + .text + .align 0 +label: + bxj r0 + bxj r1 + bxj r14 + bxjeq r0 + bxjmi r0 + bxjpl r7 + + bkpt @ Support for a breakpoint without an argument + bkpt 10 @ is a feature added to GAS. diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch6zk.d b/binutils-2.25/gas/testsuite/gas/arm/arch6zk.d new file mode 100644 index 00000000..5ec8def0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch6zk.d @@ -0,0 +1,29 @@ +#name: ARM V6 instructions +#as: -march=armv6zk +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> f57ff01f ? clrex +0+004 <[^>]*> e1dc4f9f ? ldrexb r4, \[ip\] +0+008 <[^>]*> 11d4cf9f ? ldrexbne ip, \[r4\] +0+00c <[^>]*> e1bc4f9f ? ldrexd r4, \[ip\] +0+010 <[^>]*> 11b4cf9f ? ldrexdne ip, \[r4\] +0+014 <[^>]*> e1fc4f9f ? ldrexh r4, \[ip\] +0+018 <[^>]*> 11f4cf9f ? ldrexhne ip, \[r4\] +0+01c <[^>]*> e320f080 ? nop \{128\}.* +0+020 <[^>]*> 1320f07f ? nopne \{127\}.* +0+024 <[^>]*> e320f004 ? sev +0+028 <[^>]*> e1c74f9c ? strexb r4, ip, \[r7\] +0+02c <[^>]*> 11c8cf94 ? strexbne ip, r4, \[r8\] +0+030 <[^>]*> e1a74f9c ? strexd r4, ip, \[r7\] +0+034 <[^>]*> 11a8cf94 ? strexdne ip, r4, \[r8\] +0+038 <[^>]*> e1e74f9c ? strexh r4, ip, \[r7\] +0+03c <[^>]*> 11e8cf94 ? strexhne ip, r4, \[r8\] +0+040 <[^>]*> e320f002 ? wfe +0+044 <[^>]*> e320f003 ? wfi +0+048 <[^>]*> e320f001 ? yield +0+04c <[^>]*> e16ec371 ? smc 60465.* +0+050 <[^>]*> 11613c7e ? smcne 5070.* +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch6zk.s b/binutils-2.25/gas/testsuite/gas/arm/arch6zk.s new file mode 100644 index 00000000..19c2c652 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch6zk.s @@ -0,0 +1,30 @@ +.text +.align 0 + +label: + # ARMV6K instructions + clrex + ldrexb r4, [r12] + ldrexbne r12, [r4] + ldrexd r4, [r12] + ldrexdne r12, [r4] + ldrexh r4, [r12] + ldrexhne r12, [r4] + nop {128} + nopne {127} + sev + strexb r4, r12, [r7] + strexbne r12, r4, [r8] + strexd r4, r12, [r7] + strexdne r12, r4, [r8] + strexh r4, r12, [r7] + strexhne r12, r4, [r8] + wfe + wfi + yield + # ARMV6Z instructions + smc 0xec31 + smcne 0x13ce + + # Ensure output is 32-byte aligned as required for arm-aout. + .p2align 5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7.d b/binutils-2.25/gas/testsuite/gas/arm/arch7.d new file mode 100644 index 00000000..56ed09cf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7.d @@ -0,0 +1,81 @@ +#name: ARM V7 instructions +#as: -march=armv7r +#objdump: -dr --prefix-addresses --show-raw-insn +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> f6d6f008 pli \[r6, r8\] +0+004 <[^>]*> f6d9f007 pli \[r9, r7\] +0+008 <[^>]*> f6d0f101 pli \[r0, r1, lsl #2\] +0+00c <[^>]*> f4d5f000 pli \[r5\] +0+010 <[^>]*> f4d5ffff pli \[r5, #4095\].* +0+014 <[^>]*> f455ffff pli \[r5, #-4095\].* +0+018 <[^>]*> e320f0f0 dbg #0 +0+01c <[^>]*> e320f0ff dbg #15 +0+020 <[^>]*> f57ff05f dmb sy +0+024 <[^>]*> f57ff05f dmb sy +0+028 <[^>]*> f57ff04f dsb sy +0+02c <[^>]*> f57ff04f dsb sy +0+030 <[^>]*> f57ff047 dsb un +0+034 <[^>]*> f57ff04e dsb st +0+038 <[^>]*> f57ff046 dsb unst +0+03c <[^>]*> f57ff06f isb sy +0+040 <[^>]*> f57ff06f isb sy +0+044 <[^>]*> f916 f008 pli \[r6, r8\] +0+048 <[^>]*> f919 f007 pli \[r9, r7\] +0+04c <[^>]*> f910 f021 pli \[r0, r1, lsl #2\] +0+050 <[^>]*> f995 f000 pli \[r5\] +0+054 <[^>]*> f995 ffff pli \[r5, #4095\].* +0+058 <[^>]*> f915 fcff pli \[r5, #-255\] +0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0+0105f <[^>]*> +0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; f+ff065 <[^>]*> +0+064 <[^>]*> f3af 80f0 dbg #0 +0+068 <[^>]*> f3af 80ff dbg #15 +0+06c <[^>]*> f3bf 8f5f dmb sy +0+070 <[^>]*> f3bf 8f5f dmb sy +0+074 <[^>]*> f3bf 8f4f dsb sy +0+078 <[^>]*> f3bf 8f4f dsb sy +0+07c <[^>]*> f3bf 8f47 dsb un +0+080 <[^>]*> f3bf 8f4e dsb st +0+084 <[^>]*> f3bf 8f46 dsb unst +0+088 <[^>]*> f3bf 8f6f isb sy +0+08c <[^>]*> f3bf 8f6f isb sy +0+090 <[^>]*> fb99 f6fc sdiv r6, r9, ip +0+094 <[^>]*> fb96 f9f3 sdiv r9, r6, r3 +0+098 <[^>]*> fbb6 f9f3 udiv r9, r6, r3 +0+09c <[^>]*> fbb9 f6fc udiv r6, r9, ip +# V7M APSR has the same encoding as V7A CPSR_f +0+0a0 <[^>]*> f3ef 8000 mrs r0, (CPSR|APSR) +0+0a4 <[^>]*> f3ef 8001 mrs r0, IAPSR +0+0a8 <[^>]*> f3ef 8002 mrs r0, EAPSR +0+0ac <[^>]*> f3ef 8003 mrs r0, PSR +0+0b0 <[^>]*> f3ef 8005 mrs r0, IPSR +0+0b4 <[^>]*> f3ef 8006 mrs r0, EPSR +0+0b8 <[^>]*> f3ef 8007 mrs r0, IEPSR +0+0bc <[^>]*> f3ef 8008 mrs r0, MSP +0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP +0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK +0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI +0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX +0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK +0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL +0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0 +0+0dc <[^>]*> f380 8801 msr IAPSR, r0 +0+0e0 <[^>]*> f380 8802 msr EAPSR, r0 +0+0e4 <[^>]*> f380 8803 msr PSR, r0 +0+0e8 <[^>]*> f380 8805 msr IPSR, r0 +0+0ec <[^>]*> f380 8806 msr EPSR, r0 +0+0f0 <[^>]*> f380 8807 msr IEPSR, r0 +0+0f4 <[^>]*> f380 8808 msr MSP, r0 +0+0f8 <[^>]*> f380 8809 msr PSP, r0 +0+0fc <[^>]*> f380 8810 msr PRIMASK, r0 +0+100 <[^>]*> f380 8811 msr BASEPRI, r0 +0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0 +0+108 <[^>]*> f380 8813 msr FAULTMASK, r0 +0+10c <[^>]*> f380 8814 msr CONTROL, r0 +0+110 <[^>]*> f3ef 8003 mrs r0, PSR +0+114 <[^>]*> f380 8803 msr PSR, r0 +0+118 <[^>]*> df00 svc 0 +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7.s b/binutils-2.25/gas/testsuite/gas/arm/arch7.s new file mode 100644 index 00000000..7a732fec --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7.s @@ -0,0 +1,83 @@ + # ARMV7 instructions + .text + .arch armv7r +label1: + pli [r6, r8] + pli [r9, r7] + pli [r0, r1, lsl #2] + pli [r5] + pli [r5, #4095] + pli [r5, #-4095] + + dbg #0 + dbg #15 + dmb + dmb sy + dsb + dsb sy + dsb un + dsb st + dsb unst + isb + isb sy + .thumb + .thumb_func +label2: + pli [r6, r8] + pli [r9, r7] + pli [r0, r1, lsl #2] + pli [r5] + pli [r5, #4095] + pli [r5, #-255] + pli [pc, #4095] + pli [pc, #-4095] + + dbg #0 + dbg #15 + dmb + dmb sy + dsb + dsb sy + dsb un + dsb st + dsb unst + isb + isb sy + + sdiv r6, r9, r12 + sdiv r9, r6, r3 + udiv r9, r6, r3 + udiv r6, r9, r12 + .arch armv7m + mrs r0, apsr + mrs r0, iapsr + mrs r0, eapsr + mrs r0, psr + mrs r0, ipsr + mrs r0, epsr + mrs r0, iepsr + mrs r0, msp + mrs r0, psp + mrs r0, primask + mrs r0, basepri + mrs r0, basepri_max + mrs r0, faultmask + mrs r0, control + msr apsr_nzcvq, r0 + msr iapsr_nzcvq, r0 + msr eapsr_nzcvq, r0 + msr psr_nzcvq, r0 + msr ipsr, r0 + msr epsr, r0 + msr iepsr, r0 + msr msp, r0 + msr psp, r0 + msr primask, r0 + msr basepri, r0 + msr BASEPRI_MAX, r0 + msr faultmask, r0 + msr control, r0 + mrs r0, xpsr + msr xpsr_nzcvq, r0 + + svc 0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7a-mp.d b/binutils-2.25/gas/testsuite/gas/arm/arch7a-mp.d new file mode 100644 index 00000000..bf6c6da6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7a-mp.d @@ -0,0 +1,31 @@ +#name: ARM V7-A+MP instructions +#as: -march=armv7-a+mp +#objdump: -dr --prefix-addresses --show-raw-insn +#source: arch7ar-mp.s +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\] +0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\] +0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\] +0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff +0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfff +0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\] +0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\] +0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\] +0[0-9a-f]+ <[^>]+> f790f001 pldw \[r0, r1\] +0[0-9a-f]+ <[^>]+> f790f00e pldw \[r0, lr\] +0[0-9a-f]+ <[^>]+> f790f100 pldw \[r0, r0, lsl #2\] +0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\] +0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\] +0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\] +0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff +0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\] +0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\] +0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\] +0[0-9a-f]+ <[^>]+> f83e f000 pldw \[lr, r0\] +0[0-9a-f]+ <[^>]+> f830 f001 pldw \[r0, r1\] +0[0-9a-f]+ <[^>]+> f830 f00e pldw \[r0, lr\] +0[0-9a-f]+ <[^>]+> f830 f030 pldw \[r0, r0, lsl #3\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7ar-mp.s b/binutils-2.25/gas/testsuite/gas/arm/arch7ar-mp.s new file mode 100644 index 00000000..34f7278a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7ar-mp.s @@ -0,0 +1,33 @@ + @ Test MP Extension instructions + .text + +label1: + pldw [r0, #0] + pldw [r14, #0] + pldw [r1, #0] + pldw [r0, #4095] + pldw [r0, #-4095] + + pldw [r0, r0] + pldw [r1, r0] + pldw [r14, r0] + pldw [r0, r1] + pldw [r0, r14] + pldw [r0, r0, lsl #2] + + .thumb + .thumb_func +label2: + pldw [r0, #0] + pldw [r14, #0] + pldw [r1, #0] + pldw [r0, #4095] + pldw [r0, #-255] + + pldw [r0, r0] + pldw [r1, r0] + pldw [r14, r0] + pldw [r0, r1] + pldw [r0, r14] + pldw [r0, r0, lsl #3] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7em-bad.d b/binutils-2.25/gas/testsuite/gas/arm/arch7em-bad.d new file mode 100644 index 00000000..7cd11fc2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7em-bad.d @@ -0,0 +1,4 @@ +#name: Valid v7E-M, invalid v7-M +#as: -march=armv7-m +#source: arch7em.s +#error-output: arch7em-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7em-bad.l b/binutils-2.25/gas/testsuite/gas/arm/arch7em-bad.l new file mode 100644 index 00000000..1c478256 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7em-bad.l @@ -0,0 +1,132 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: selected processor does not support Thumb mode `pkhbt r0,r0,r0' +[^:]*:9: Error: selected processor does not support Thumb mode `pkhbt r9,r0,r0' +[^:]*:10: Error: selected processor does not support Thumb mode `pkhbt r0,r9,r0' +[^:]*:11: Error: selected processor does not support Thumb mode `pkhbt r0,r0,r9' +[^:]*:12: Error: selected processor does not support Thumb mode `pkhbt r0,r0,r0,lsl#0x14' +[^:]*:13: Error: selected processor does not support Thumb mode `pkhbt r0,r0,r0,lsl#3' +[^:]*:14: Error: selected processor does not support Thumb mode `pkhtb r1,r2,r3' +[^:]*:15: Error: selected processor does not support Thumb mode `pkhtb r1,r2,r3,asr#0x11' +[^:]*:18: Error: selected processor does not support Thumb mode `qadd r1,r2,r3' +[^:]*:19: Error: selected processor does not support Thumb mode `qadd16 r1,r2,r3' +[^:]*:20: Error: selected processor does not support Thumb mode `qadd8 r1,r2,r3' +[^:]*:21: Error: selected processor does not support Thumb mode `qasx r1,r2,r3' +[^:]*:22: Error: selected processor does not support Thumb mode `qaddsubx r1,r2,r3' +[^:]*:23: Error: selected processor does not support Thumb mode `qdadd r1,r2,r3' +[^:]*:24: Error: selected processor does not support Thumb mode `qdsub r1,r2,r3' +[^:]*:25: Error: selected processor does not support Thumb mode `qsub r1,r2,r3' +[^:]*:26: Error: selected processor does not support Thumb mode `qsub16 r1,r2,r3' +[^:]*:27: Error: selected processor does not support Thumb mode `qsub8 r1,r2,r3' +[^:]*:28: Error: selected processor does not support Thumb mode `qsax r1,r2,r3' +[^:]*:29: Error: selected processor does not support Thumb mode `qsubaddx r1,r2,r3' +[^:]*:30: Error: selected processor does not support Thumb mode `sadd16 r1,r2,r3' +[^:]*:31: Error: selected processor does not support Thumb mode `sadd8 r1,r2,r3' +[^:]*:32: Error: selected processor does not support Thumb mode `sasx r1,r2,r3' +[^:]*:33: Error: selected processor does not support Thumb mode `saddsubx r1,r2,r3' +[^:]*:34: Error: selected processor does not support Thumb mode `ssub16 r1,r2,r3' +[^:]*:35: Error: selected processor does not support Thumb mode `ssub8 r1,r2,r3' +[^:]*:36: Error: selected processor does not support Thumb mode `ssax r1,r2,r3' +[^:]*:37: Error: selected processor does not support Thumb mode `ssubaddx r1,r2,r3' +[^:]*:38: Error: selected processor does not support Thumb mode `shadd16 r1,r2,r3' +[^:]*:39: Error: selected processor does not support Thumb mode `shadd8 r1,r2,r3' +[^:]*:40: Error: selected processor does not support Thumb mode `shasx r1,r2,r3' +[^:]*:41: Error: selected processor does not support Thumb mode `shaddsubx r1,r2,r3' +[^:]*:42: Error: selected processor does not support Thumb mode `shsub16 r1,r2,r3' +[^:]*:43: Error: selected processor does not support Thumb mode `shsub8 r1,r2,r3' +[^:]*:44: Error: selected processor does not support Thumb mode `shsax r1,r2,r3' +[^:]*:45: Error: selected processor does not support Thumb mode `shsubaddx r1,r2,r3' +[^:]*:46: Error: selected processor does not support Thumb mode `uadd16 r1,r2,r3' +[^:]*:47: Error: selected processor does not support Thumb mode `uadd8 r1,r2,r3' +[^:]*:48: Error: selected processor does not support Thumb mode `uasx r1,r2,r3' +[^:]*:49: Error: selected processor does not support Thumb mode `uaddsubx r1,r2,r3' +[^:]*:50: Error: selected processor does not support Thumb mode `usub16 r1,r2,r3' +[^:]*:51: Error: selected processor does not support Thumb mode `usub8 r1,r2,r3' +[^:]*:52: Error: selected processor does not support Thumb mode `usax r1,r2,r3' +[^:]*:53: Error: selected processor does not support Thumb mode `usubaddx r1,r2,r3' +[^:]*:54: Error: selected processor does not support Thumb mode `uhadd16 r1,r2,r3' +[^:]*:55: Error: selected processor does not support Thumb mode `uhadd8 r1,r2,r3' +[^:]*:56: Error: selected processor does not support Thumb mode `uhasx r1,r2,r3' +[^:]*:57: Error: selected processor does not support Thumb mode `uhaddsubx r1,r2,r3' +[^:]*:58: Error: selected processor does not support Thumb mode `uhsub16 r1,r2,r3' +[^:]*:59: Error: selected processor does not support Thumb mode `uhsub8 r1,r2,r3' +[^:]*:60: Error: selected processor does not support Thumb mode `uhsax r1,r2,r3' +[^:]*:61: Error: selected processor does not support Thumb mode `uhsubaddx r1,r2,r3' +[^:]*:62: Error: selected processor does not support Thumb mode `uqadd16 r1,r2,r3' +[^:]*:63: Error: selected processor does not support Thumb mode `uqadd8 r1,r2,r3' +[^:]*:64: Error: selected processor does not support Thumb mode `uqasx r1,r2,r3' +[^:]*:65: Error: selected processor does not support Thumb mode `uqaddsubx r1,r2,r3' +[^:]*:66: Error: selected processor does not support Thumb mode `uqsub16 r1,r2,r3' +[^:]*:67: Error: selected processor does not support Thumb mode `uqsub8 r1,r2,r3' +[^:]*:68: Error: selected processor does not support Thumb mode `uqsax r1,r2,r3' +[^:]*:69: Error: selected processor does not support Thumb mode `uqsubaddx r1,r2,r3' +[^:]*:70: Error: selected processor does not support Thumb mode `sel r1,r2,r3' +[^:]*:73: Error: selected processor does not support Thumb mode `smlabb r0,r0,r0,r0' +[^:]*:74: Error: selected processor does not support Thumb mode `smlabb r9,r0,r0,r0' +[^:]*:75: Error: selected processor does not support Thumb mode `smlabb r0,r9,r0,r0' +[^:]*:76: Error: selected processor does not support Thumb mode `smlabb r0,r0,r9,r0' +[^:]*:77: Error: selected processor does not support Thumb mode `smlabb r0,r0,r0,r9' +[^:]*:79: Error: selected processor does not support Thumb mode `smlatb r0,r0,r0,r0' +[^:]*:80: Error: selected processor does not support Thumb mode `smlabt r0,r0,r0,r0' +[^:]*:81: Error: selected processor does not support Thumb mode `smlatt r0,r0,r0,r0' +[^:]*:82: Error: selected processor does not support Thumb mode `smlawb r0,r0,r0,r0' +[^:]*:83: Error: selected processor does not support Thumb mode `smlawt r0,r0,r0,r0' +[^:]*:84: Error: selected processor does not support Thumb mode `smlad r0,r0,r0,r0' +[^:]*:85: Error: selected processor does not support Thumb mode `smladx r0,r0,r0,r0' +[^:]*:86: Error: selected processor does not support Thumb mode `smlsd r0,r0,r0,r0' +[^:]*:87: Error: selected processor does not support Thumb mode `smlsdx r0,r0,r0,r0' +[^:]*:88: Error: selected processor does not support Thumb mode `smmla r0,r0,r0,r0' +[^:]*:89: Error: selected processor does not support Thumb mode `smmlar r0,r0,r0,r0' +[^:]*:90: Error: selected processor does not support Thumb mode `smmls r0,r0,r0,r0' +[^:]*:91: Error: selected processor does not support Thumb mode `smmlsr r0,r0,r0,r0' +[^:]*:92: Error: selected processor does not support Thumb mode `usada8 r0,r0,r0,r0' +[^:]*:95: Error: selected processor does not support Thumb mode `smlalbb r0,r0,r0,r0' +[^:]*:96: Error: selected processor does not support Thumb mode `smlalbb r9,r0,r0,r0' +[^:]*:97: Error: selected processor does not support Thumb mode `smlalbb r0,r9,r0,r0' +[^:]*:98: Error: selected processor does not support Thumb mode `smlalbb r0,r0,r9,r0' +[^:]*:99: Error: selected processor does not support Thumb mode `smlalbb r0,r0,r0,r9' +[^:]*:101: Error: selected processor does not support Thumb mode `smlaltb r0,r0,r0,r0' +[^:]*:102: Error: selected processor does not support Thumb mode `smlalbt r0,r0,r0,r0' +[^:]*:103: Error: selected processor does not support Thumb mode `smlaltt r0,r0,r0,r0' +[^:]*:104: Error: selected processor does not support Thumb mode `smlald r0,r0,r0,r0' +[^:]*:105: Error: selected processor does not support Thumb mode `smlaldx r0,r0,r0,r0' +[^:]*:106: Error: selected processor does not support Thumb mode `smlsld r0,r0,r0,r0' +[^:]*:107: Error: selected processor does not support Thumb mode `smlsldx r0,r0,r0,r0' +[^:]*:108: Error: selected processor does not support Thumb mode `umaal r0,r0,r0,r0' +[^:]*:111: Error: selected processor does not support Thumb mode `smulbb r0,r0,r0' +[^:]*:112: Error: selected processor does not support Thumb mode `smulbb r9,r0,r0' +[^:]*:113: Error: selected processor does not support Thumb mode `smulbb r0,r9,r0' +[^:]*:114: Error: selected processor does not support Thumb mode `smulbb r0,r0,r9' +[^:]*:116: Error: selected processor does not support Thumb mode `smultb r0,r0,r0' +[^:]*:117: Error: selected processor does not support Thumb mode `smulbt r0,r0,r0' +[^:]*:118: Error: selected processor does not support Thumb mode `smultt r0,r0,r0' +[^:]*:119: Error: selected processor does not support Thumb mode `smulwb r0,r0,r0' +[^:]*:120: Error: selected processor does not support Thumb mode `smulwt r0,r0,r0' +[^:]*:121: Error: selected processor does not support Thumb mode `smmul r0,r0,r0' +[^:]*:122: Error: selected processor does not support Thumb mode `smmulr r0,r0,r0' +[^:]*:123: Error: selected processor does not support Thumb mode `smuad r0,r0,r0' +[^:]*:124: Error: selected processor does not support Thumb mode `smuadx r0,r0,r0' +[^:]*:125: Error: selected processor does not support Thumb mode `smusd r0,r0,r0' +[^:]*:126: Error: selected processor does not support Thumb mode `smusdx r0,r0,r0' +[^:]*:127: Error: selected processor does not support Thumb mode `usad8 r0,r0,r0' +[^:]*:130: Error: selected processor does not support Thumb mode `ssat16 r0,#1,r0' +[^:]*:131: Error: selected processor does not support Thumb mode `ssat16 r9,#1,r0' +[^:]*:132: Error: selected processor does not support Thumb mode `ssat16 r0,#10,r0' +[^:]*:133: Error: selected processor does not support Thumb mode `ssat16 r0,#1,r9' +[^:]*:135: Error: selected processor does not support Thumb mode `usat16 r0,#0,r0' +[^:]*:136: Error: selected processor does not support Thumb mode `usat16 r9,#0,r0' +[^:]*:137: Error: selected processor does not support Thumb mode `usat16 r0,#9,r0' +[^:]*:138: Error: selected processor does not support Thumb mode `usat16 r0,#0,r9' +[^:]*:141: Error: selected processor does not support Thumb mode `sxtb16 r1,r2' +[^:]*:142: Error: selected processor does not support Thumb mode `sxtb16 r8,r9' +[^:]*:143: Error: selected processor does not support Thumb mode `uxtb16 r1,r2' +[^:]*:144: Error: selected processor does not support Thumb mode `uxtb16 r8,r9' +[^:]*:147: Error: selected processor does not support Thumb mode `sxtab r0,r0,r0' +[^:]*:148: Error: selected processor does not support Thumb mode `sxtab r0,r0,r0,ror#0' +[^:]*:149: Error: selected processor does not support Thumb mode `sxtab r9,r0,r0,ror#8' +[^:]*:150: Error: selected processor does not support Thumb mode `sxtab r0,r9,r0,ror#16' +[^:]*:151: Error: selected processor does not support Thumb mode `sxtab r0,r0,r9,ror#24' +[^:]*:153: Error: selected processor does not support Thumb mode `sxtab16 r1,r2,r3' +[^:]*:154: Error: selected processor does not support Thumb mode `sxtah r1,r2,r3' +[^:]*:155: Error: selected processor does not support Thumb mode `uxtab r1,r2,r3' +[^:]*:156: Error: selected processor does not support Thumb mode `uxtab16 r1,r2,r3' +[^:]*:157: Error: selected processor does not support Thumb mode `uxtah r1,r2,r3' diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7em.d b/binutils-2.25/gas/testsuite/gas/arm/arch7em.d new file mode 100644 index 00000000..cd1f9399 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7em.d @@ -0,0 +1,139 @@ +# name: 32-bit Thumb DSP instructions +# as: -march=armv7e-m +# objdump: -dr --prefix-addresses --show-raw-insn +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0 +0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0 +0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0 +0[0-9a-f]+ <[^>]+> eac0 0009 pkhbt r0, r0, r9 +0[0-9a-f]+ <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20 +0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3 +0[0-9a-f]+ <[^>]+> eac3 0102 pkhbt r1, r3, r2 +0[0-9a-f]+ <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17 +0[0-9a-f]+ <[^>]+> fa83 f182 qadd r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa83 f192 qdadd r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa83 f1b2 qdsub r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa83 f1a2 qsub r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f103 sadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f103 sadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f103 ssub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f103 ssub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f123 shadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f123 shadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f123 shsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f123 shsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f143 uadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f143 uadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f143 usub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f143 usub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f163 uhadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f163 uhadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f163 uhsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f163 uhsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f153 uqadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f153 uqadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f153 uqsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f153 uqsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f183 sel r1, r2, r3 +0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb19 0000 smlabb r0, r9, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0009 smlabb r0, r0, r9, r0 +0[0-9a-f]+ <[^>]+> fb10 9000 smlabb r0, r0, r0, r9 +0[0-9a-f]+ <[^>]+> fb10 0020 smlatb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0010 smlabt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0030 smlatt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 0000 smlawb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 0010 smlawt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 0000 smlad r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 0010 smladx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 0000 smlsd r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 0010 smlsdx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 0000 smmla r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 0010 smmlar r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb60 0000 smmls r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb60 0010 smmlsr r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb70 0000 usada8 r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0080 smlalbb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 9080 smlalbb r9, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0980 smlalbb r0, r9, r0, r0 +0[0-9a-f]+ <[^>]+> fbc9 0080 smlalbb r0, r0, r9, r0 +0[0-9a-f]+ <[^>]+> fbc0 0089 smlalbb r0, r0, r0, r9 +0[0-9a-f]+ <[^>]+> fbc0 00a0 smlaltb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0090 smlalbt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 00b0 smlaltt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 00c0 smlald r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 00d0 smlaldx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbd0 00c0 smlsld r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbd0 00d0 smlsldx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbe0 0060 umaal r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f000 smulbb r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f900 smulbb r9, r0, r0 +0[0-9a-f]+ <[^>]+> fb19 f000 smulbb r0, r9, r0 +0[0-9a-f]+ <[^>]+> fb10 f009 smulbb r0, r0, r9 +0[0-9a-f]+ <[^>]+> fb10 f020 smultb r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f010 smulbt r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f030 smultt r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 f000 smulwb r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 f010 smulwt r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 f000 smmul r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 f010 smmulr r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 f000 smuad r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 f010 smuadx r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0 +0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0 +0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0 +0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0 +0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9 +0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0 +0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0 +0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0 +0[0-9a-f]+ <[^>]+> f3a9 0000 usat16 r0, #0, r9 +0[0-9a-f]+ <[^>]+> fa2f f182 sxtb16 r1, r2 +0[0-9a-f]+ <[^>]+> fa2f f889 sxtb16 r8, r9 +0[0-9a-f]+ <[^>]+> fa3f f182 uxtb16 r1, r2 +0[0-9a-f]+ <[^>]+> fa3f f889 uxtb16 r8, r9 +0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa40 f990 sxtab r9, r0, r0, ror #8 +0[0-9a-f]+ <[^>]+> fa49 f0a0 sxtab r0, r9, r0, ror #16 +0[0-9a-f]+ <[^>]+> fa40 f0b9 sxtab r0, r0, r9, ror #24 +0[0-9a-f]+ <[^>]+> fa22 f183 sxtab16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa02 f183 sxtah r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7em.s b/binutils-2.25/gas/testsuite/gas/arm/arch7em.s new file mode 100644 index 00000000..7a3e4ab5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7em.s @@ -0,0 +1,157 @@ +# Instructions included in v7E-M architecture over v7-M. + + .text + .thumb + .syntax unified + +pkh: + pkhbt r0, r0, r0 + pkhbt r9, r0, r0 + pkhbt r0, r9, r0 + pkhbt r0, r0, r9 + pkhbt r0, r0, r0, lsl #0x14 + pkhbt r0, r0, r0, lsl #3 + pkhtb r1, r2, r3 + pkhtb r1, r2, r3, asr #0x11 + +qadd: + qadd r1, r2, r3 + qadd16 r1, r2, r3 + qadd8 r1, r2, r3 + qasx r1, r2, r3 + qaddsubx r1, r2, r3 + qdadd r1, r2, r3 + qdsub r1, r2, r3 + qsub r1, r2, r3 + qsub16 r1, r2, r3 + qsub8 r1, r2, r3 + qsax r1, r2, r3 + qsubaddx r1, r2, r3 + sadd16 r1, r2, r3 + sadd8 r1, r2, r3 + sasx r1, r2, r3 + saddsubx r1, r2, r3 + ssub16 r1, r2, r3 + ssub8 r1, r2, r3 + ssax r1, r2, r3 + ssubaddx r1, r2, r3 + shadd16 r1, r2, r3 + shadd8 r1, r2, r3 + shasx r1, r2, r3 + shaddsubx r1, r2, r3 + shsub16 r1, r2, r3 + shsub8 r1, r2, r3 + shsax r1, r2, r3 + shsubaddx r1, r2, r3 + uadd16 r1, r2, r3 + uadd8 r1, r2, r3 + uasx r1, r2, r3 + uaddsubx r1, r2, r3 + usub16 r1, r2, r3 + usub8 r1, r2, r3 + usax r1, r2, r3 + usubaddx r1, r2, r3 + uhadd16 r1, r2, r3 + uhadd8 r1, r2, r3 + uhasx r1, r2, r3 + uhaddsubx r1, r2, r3 + uhsub16 r1, r2, r3 + uhsub8 r1, r2, r3 + uhsax r1, r2, r3 + uhsubaddx r1, r2, r3 + uqadd16 r1, r2, r3 + uqadd8 r1, r2, r3 + uqasx r1, r2, r3 + uqaddsubx r1, r2, r3 + uqsub16 r1, r2, r3 + uqsub8 r1, r2, r3 + uqsax r1, r2, r3 + uqsubaddx r1, r2, r3 + sel r1, r2, r3 + +smla: + smlabb r0, r0, r0, r0 + smlabb r9, r0, r0, r0 + smlabb r0, r9, r0, r0 + smlabb r0, r0, r9, r0 + smlabb r0, r0, r0, r9 + + smlatb r0, r0, r0, r0 + smlabt r0, r0, r0, r0 + smlatt r0, r0, r0, r0 + smlawb r0, r0, r0, r0 + smlawt r0, r0, r0, r0 + smlad r0, r0, r0, r0 + smladx r0, r0, r0, r0 + smlsd r0, r0, r0, r0 + smlsdx r0, r0, r0, r0 + smmla r0, r0, r0, r0 + smmlar r0, r0, r0, r0 + smmls r0, r0, r0, r0 + smmlsr r0, r0, r0, r0 + usada8 r0, r0, r0, r0 + +smlal: + smlalbb r0, r0, r0, r0 + smlalbb r9, r0, r0, r0 + smlalbb r0, r9, r0, r0 + smlalbb r0, r0, r9, r0 + smlalbb r0, r0, r0, r9 + + smlaltb r0, r0, r0, r0 + smlalbt r0, r0, r0, r0 + smlaltt r0, r0, r0, r0 + smlald r0, r0, r0, r0 + smlaldx r0, r0, r0, r0 + smlsld r0, r0, r0, r0 + smlsldx r0, r0, r0, r0 + umaal r0, r0, r0, r0 + +smul: + smulbb r0, r0, r0 + smulbb r9, r0, r0 + smulbb r0, r9, r0 + smulbb r0, r0, r9 + + smultb r0, r0, r0 + smulbt r0, r0, r0 + smultt r0, r0, r0 + smulwb r0, r0, r0 + smulwt r0, r0, r0 + smmul r0, r0, r0 + smmulr r0, r0, r0 + smuad r0, r0, r0 + smuadx r0, r0, r0 + smusd r0, r0, r0 + smusdx r0, r0, r0 + usad8 r0, r0, r0 + +sat: + ssat16 r0, #1, r0 + ssat16 r9, #1, r0 + ssat16 r0, #10, r0 + ssat16 r0, #1, r9 + + usat16 r0, #0, r0 + usat16 r9, #0, r0 + usat16 r0, #9, r0 + usat16 r0, #0, r9 + +xt: + sxtb16 r1, r2 + sxtb16 r8, r9 + uxtb16 r1, r2 + uxtb16 r8, r9 + +xta: + sxtab r0, r0, r0 + sxtab r0, r0, r0, ror #0 + sxtab r9, r0, r0, ror #8 + sxtab r0, r9, r0, ror #16 + sxtab r0, r0, r9, ror #24 + + sxtab16 r1, r2, r3 + sxtah r1, r2, r3 + uxtab r1, r2, r3 + uxtab16 r1, r2, r3 + uxtah r1, r2, r3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.d b/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.d new file mode 100644 index 00000000..b7a3336c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.d @@ -0,0 +1,4 @@ +#name: Invalid V7M instructions +#as: -march=armv7m +#error-output: arch7m-bad.l + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.l b/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.l new file mode 100644 index 00000000..2b730098 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:5: Error: selected processor does not support 'A' form of this instruction -- `cpsie a' +[^:]*:6: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie i,#0x10' +[^:]*:7: Error: selected processor does not support Thumb mode `cps #0x10' + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.s b/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.s new file mode 100644 index 00000000..78ff8649 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7m-bad.s @@ -0,0 +1,7 @@ + .text + .thumb + .thumb_func +label: + cpsie a + cpsie i, #0x10 + cps #0x10 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arch7r-mp.d b/binutils-2.25/gas/testsuite/gas/arm/arch7r-mp.d new file mode 100644 index 00000000..8908c98c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arch7r-mp.d @@ -0,0 +1,30 @@ +#name: ARM V7-R+MP instructions +#as: -march=armv7-r+mp +#objdump: -dr --prefix-addresses --show-raw-insn +#source: arch7ar-mp.s + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f590f000 pldw \[r0\] +0[0-9a-f]+ <[^>]+> f59ef000 pldw \[lr\] +0[0-9a-f]+ <[^>]+> f591f000 pldw \[r1\] +0[0-9a-f]+ <[^>]+> f590ffff pldw \[r0, #4095\] ; 0xfff +0[0-9a-f]+ <[^>]+> f510ffff pldw \[r0, #-4095\] ; 0xfff +0[0-9a-f]+ <[^>]+> f790f000 pldw \[r0, r0\] +0[0-9a-f]+ <[^>]+> f791f000 pldw \[r1, r0\] +0[0-9a-f]+ <[^>]+> f79ef000 pldw \[lr, r0\] +0[0-9a-f]+ <[^>]+> f790f001 pldw \[r0, r1\] +0[0-9a-f]+ <[^>]+> f790f00e pldw \[r0, lr\] +0[0-9a-f]+ <[^>]+> f790f100 pldw \[r0, r0, lsl #2\] +0[0-9a-f]+ <[^>]+> f8b0 f000 pldw \[r0\] +0[0-9a-f]+ <[^>]+> f8be f000 pldw \[lr\] +0[0-9a-f]+ <[^>]+> f8b1 f000 pldw \[r1\] +0[0-9a-f]+ <[^>]+> f8b0 ffff pldw \[r0, #4095\] ; 0xfff +0[0-9a-f]+ <[^>]+> f830 fcff pldw \[r0, #-255\] +0[0-9a-f]+ <[^>]+> f830 f000 pldw \[r0, r0\] +0[0-9a-f]+ <[^>]+> f831 f000 pldw \[r1, r0\] +0[0-9a-f]+ <[^>]+> f83e f000 pldw \[lr, r0\] +0[0-9a-f]+ <[^>]+> f830 f001 pldw \[r0, r1\] +0[0-9a-f]+ <[^>]+> f830 f00e pldw \[r0, lr\] +0[0-9a-f]+ <[^>]+> f830 f030 pldw \[r0, r0, lsl #3\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6.d b/binutils-2.25/gas/testsuite/gas/arm/archv6.d new file mode 100644 index 00000000..bee9909f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6.d @@ -0,0 +1,225 @@ +#name: ARM V6 instructions +#as: -march=armv6j +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> f102000f ? cps #15 +0+004 <[^>]*> f10c00c0 ? cpsid if +0+008 <[^>]*> f10800c0 ? cpsie if +0+00c <[^>]*> e1942f9f ? ldrex r2, \[r4\] +0+010 <[^>]*> 11984f9f ? ldrexne r4, \[r8\] +0+014 <[^>]*> fc4570c3 ? mcrr2 0, 12, r7, r5, cr3 +0+018 <[^>]*> fc5570c3 ? mrrc2 0, 12, r7, r5, cr3 +0+01c <[^>]*> e6852018 ? pkhbt r2, r5, r8 +0+020 <[^>]*> e6852198 ? pkhbt r2, r5, r8, lsl #3 +0+024 <[^>]*> e6852198 ? pkhbt r2, r5, r8, lsl #3 +0+028 <[^>]*> 06852198 ? pkhbteq r2, r5, r8, lsl #3 +0+02c <[^>]*> e6882015 ? pkhbt r2, r8, r5 +0+030 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, asr #3 +0+034 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, asr #3 +0+038 <[^>]*> 068521d8 ? pkhtbeq r2, r5, r8, asr #3 +0+03c <[^>]*> e6242f17 ? qadd16 r2, r4, r7 +0+040 <[^>]*> 16242f17 ? qadd16ne r2, r4, r7 +0+044 <[^>]*> e6242f97 ? qadd8 r2, r4, r7 +0+048 <[^>]*> 16242f97 ? qadd8ne r2, r4, r7 +0+04c <[^>]*> e6242f37 ? qasx r2, r4, r7 +0+050 <[^>]*> 16242f37 ? qasxne r2, r4, r7 +0+054 <[^>]*> e6242f77 ? qsub16 r2, r4, r7 +0+058 <[^>]*> 16242f77 ? qsub16ne r2, r4, r7 +0+05c <[^>]*> e6242ff7 ? qsub8 r2, r4, r7 +0+060 <[^>]*> 16242ff7 ? qsub8ne r2, r4, r7 +0+064 <[^>]*> e6242f57 ? qsax r2, r4, r7 +0+068 <[^>]*> e6242f57 ? qsax r2, r4, r7 +0+06c <[^>]*> e6bf2f34 ? rev r2, r4 +0+070 <[^>]*> e6bf2fb4 ? rev16 r2, r4 +0+074 <[^>]*> 16bf3fb5 ? rev16ne r3, r5 +0+078 <[^>]*> 16bf3f35 ? revne r3, r5 +0+07c <[^>]*> e6ff2fb4 ? revsh r2, r4 +0+080 <[^>]*> 16ff3fb5 ? revshne r3, r5 +0+084 <[^>]*> f8120a00 ? rfeda r2 +0+088 <[^>]*> f8320a00 ? rfeda r2! +0+08c <[^>]*> f9120a00 ? rfedb r2 +0+090 <[^>]*> f9320a00 ? rfedb r2! +0+094 <[^>]*> f8920a00 ? rfeia r2 +0+098 <[^>]*> f8b20a00 ? rfeia r2! +0+09c <[^>]*> f9920a00 ? rfeib r2 +0+0a0 <[^>]*> f9b20a00 ? rfeib r2! +0+0a4 <[^>]*> f8920a00 ? rfeia r2 +0+0a8 <[^>]*> f8b20a00 ? rfeia r2! +0+0ac <[^>]*> e6142f17 ? sadd16 r2, r4, r7 +0+0b0 <[^>]*> 16142f17 ? sadd16ne r2, r4, r7 +0+0b4 <[^>]*> e6b42075 ? sxtah r2, r4, r5 +0+0b8 <[^>]*> e6b42475 ? sxtah r2, r4, r5, ror #8 +0+0bc <[^>]*> 16b42075 ? sxtahne r2, r4, r5 +0+0c0 <[^>]*> 16b42475 ? sxtahne r2, r4, r5, ror #8 +0+0c4 <[^>]*> e6142f97 ? sadd8 r2, r4, r7 +0+0c8 <[^>]*> 16142f97 ? sadd8ne r2, r4, r7 +0+0cc <[^>]*> e6842075 ? sxtab16 r2, r4, r5 +0+0d0 <[^>]*> e6842475 ? sxtab16 r2, r4, r5, ror #8 +0+0d4 <[^>]*> 16842075 ? sxtab16ne r2, r4, r5 +0+0d8 <[^>]*> 16842475 ? sxtab16ne r2, r4, r5, ror #8 +0+0dc <[^>]*> e6a42075 ? sxtab r2, r4, r5 +0+0e0 <[^>]*> e6a42475 ? sxtab r2, r4, r5, ror #8 +0+0e4 <[^>]*> 16a42075 ? sxtabne r2, r4, r5 +0+0e8 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ror #8 +0+0ec <[^>]*> e6142f37 ? sasx r2, r4, r7 +0+0f0 <[^>]*> 16142f37 ? sasxne r2, r4, r7 +0+0f4 <[^>]*> e6821fb3 ? sel r1, r2, r3 +0+0f8 <[^>]*> 16821fb3 ? selne r1, r2, r3 +0+0fc <[^>]*> f1010200 ? setend be +0+100 <[^>]*> f1010000 ? setend le +0+104 <[^>]*> e6342f17 ? shadd16 r2, r4, r7 +0+108 <[^>]*> 16342f17 ? shadd16ne r2, r4, r7 +0+10c <[^>]*> e6342f97 ? shadd8 r2, r4, r7 +0+110 <[^>]*> 16342f97 ? shadd8ne r2, r4, r7 +0+114 <[^>]*> e6342f37 ? shasx r2, r4, r7 +0+118 <[^>]*> 16342f37 ? shasxne r2, r4, r7 +0+11c <[^>]*> e6342f77 ? shsub16 r2, r4, r7 +0+120 <[^>]*> 16342f77 ? shsub16ne r2, r4, r7 +0+124 <[^>]*> e6342ff7 ? shsub8 r2, r4, r7 +0+128 <[^>]*> 16342ff7 ? shsub8ne r2, r4, r7 +0+12c <[^>]*> e6342f57 ? shsax r2, r4, r7 +0+130 <[^>]*> 16342f57 ? shsaxne r2, r4, r7 +0+134 <[^>]*> e7014312 ? smlad r1, r2, r3, r4 +0+138 <[^>]*> d7014312 ? smladle r1, r2, r3, r4 +0+13c <[^>]*> e7014332 ? smladx r1, r2, r3, r4 +0+140 <[^>]*> d7014332 ? smladxle r1, r2, r3, r4 +0+144 <[^>]*> e7421413 ? smlald r1, r2, r3, r4 +0+148 <[^>]*> d7421413 ? smlaldle r1, r2, r3, r4 +0+14c <[^>]*> e7421433 ? smlaldx r1, r2, r3, r4 +0+150 <[^>]*> d7421433 ? smlaldxle r1, r2, r3, r4 +0+154 <[^>]*> e7014352 ? smlsd r1, r2, r3, r4 +0+158 <[^>]*> d7014352 ? smlsdle r1, r2, r3, r4 +0+15c <[^>]*> e7014372 ? smlsdx r1, r2, r3, r4 +0+160 <[^>]*> d7014372 ? smlsdxle r1, r2, r3, r4 +0+164 <[^>]*> e7421453 ? smlsld r1, r2, r3, r4 +0+168 <[^>]*> d7421453 ? smlsldle r1, r2, r3, r4 +0+16c <[^>]*> e7421473 ? smlsldx r1, r2, r3, r4 +0+170 <[^>]*> d7421473 ? smlsldxle r1, r2, r3, r4 +0+174 <[^>]*> e7514312 ? smmla r1, r2, r3, r4 +0+178 <[^>]*> d7514312 ? smmlale r1, r2, r3, r4 +0+17c <[^>]*> e7514332 ? smmlar r1, r2, r3, r4 +0+180 <[^>]*> d7514332 ? smmlarle r1, r2, r3, r4 +0+184 <[^>]*> e75143d2 ? smmls r1, r2, r3, r4 +0+188 <[^>]*> d75143d2 ? smmlsle r1, r2, r3, r4 +0+18c <[^>]*> e75143f2 ? smmlsr r1, r2, r3, r4 +0+190 <[^>]*> d75143f2 ? smmlsrle r1, r2, r3, r4 +0+194 <[^>]*> e751f312 ? smmul r1, r2, r3 +0+198 <[^>]*> d751f312 ? smmulle r1, r2, r3 +0+19c <[^>]*> e751f332 ? smmulr r1, r2, r3 +0+1a0 <[^>]*> d751f332 ? smmulrle r1, r2, r3 +0+1a4 <[^>]*> e701f312 ? smuad r1, r2, r3 +0+1a8 <[^>]*> d701f312 ? smuadle r1, r2, r3 +0+1ac <[^>]*> e701f332 ? smuadx r1, r2, r3 +0+1b0 <[^>]*> d701f332 ? smuadxle r1, r2, r3 +0+1b4 <[^>]*> e701f352 ? smusd r1, r2, r3 +0+1b8 <[^>]*> d701f352 ? smusdle r1, r2, r3 +0+1bc <[^>]*> e701f372 ? smusdx r1, r2, r3 +0+1c0 <[^>]*> d701f372 ? smusdxle r1, r2, r3 +0+1c4 <[^>]*> f8cd0510 ? srsia sp, #16 +0+1c8 <[^>]*> f9ed0510 ? srsib sp!, #16 +0+1cc <[^>]*> e6a01012 ? ssat r1, #1, r2 +0+1d0 <[^>]*> e6a01152 ? ssat r1, #1, r2, asr #2 +0+1d4 <[^>]*> e6a01112 ? ssat r1, #1, r2, lsl #2 +0+1d8 <[^>]*> e6a01f31 ? ssat16 r1, #1, r1 +0+1dc <[^>]*> d6a01f31 ? ssat16le r1, #1, r1 +0+1e0 <[^>]*> e6142f77 ? ssub16 r2, r4, r7 +0+1e4 <[^>]*> 16142f77 ? ssub16ne r2, r4, r7 +0+1e8 <[^>]*> e6142ff7 ? ssub8 r2, r4, r7 +0+1ec <[^>]*> 16142ff7 ? ssub8ne r2, r4, r7 +0+1f0 <[^>]*> e6142f57 ? ssax r2, r4, r7 +0+1f4 <[^>]*> 16142f57 ? ssaxne r2, r4, r7 +0+1f8 <[^>]*> e1831f92 ? strex r1, r2, \[r3\] +0+1fc <[^>]*> 11831f92 ? strexne r1, r2, \[r3\] +0+200 <[^>]*> e6bf2075 ? sxth r2, r5 +0+204 <[^>]*> e6bf2475 ? sxth r2, r5, ror #8 +0+208 <[^>]*> 16bf2075 ? sxthne r2, r5 +0+20c <[^>]*> 16bf2475 ? sxthne r2, r5, ror #8 +0+210 <[^>]*> e68f2075 ? sxtb16 r2, r5 +0+214 <[^>]*> e68f2475 ? sxtb16 r2, r5, ror #8 +0+218 <[^>]*> 168f2075 ? sxtb16ne r2, r5 +0+21c <[^>]*> 168f2475 ? sxtb16ne r2, r5, ror #8 +0+220 <[^>]*> e6af2075 ? sxtb r2, r5 +0+224 <[^>]*> e6af2475 ? sxtb r2, r5, ror #8 +0+228 <[^>]*> 16af2075 ? sxtbne r2, r5 +0+22c <[^>]*> 16af2475 ? sxtbne r2, r5, ror #8 +0+230 <[^>]*> e6542f17 ? uadd16 r2, r4, r7 +0+234 <[^>]*> 16542f17 ? uadd16ne r2, r4, r7 +0+238 <[^>]*> e6f32075 ? uxtah r2, r3, r5 +0+23c <[^>]*> e6f32475 ? uxtah r2, r3, r5, ror #8 +0+240 <[^>]*> 16f32075 ? uxtahne r2, r3, r5 +0+244 <[^>]*> 16f32475 ? uxtahne r2, r3, r5, ror #8 +0+248 <[^>]*> e6542f97 ? uadd8 r2, r4, r7 +0+24c <[^>]*> 16542f97 ? uadd8ne r2, r4, r7 +0+250 <[^>]*> e6c32075 ? uxtab16 r2, r3, r5 +0+254 <[^>]*> e6c32475 ? uxtab16 r2, r3, r5, ror #8 +0+258 <[^>]*> 16c32075 ? uxtab16ne r2, r3, r5 +0+25c <[^>]*> 16c32475 ? uxtab16ne r2, r3, r5, ror #8 +0+260 <[^>]*> e6e32075 ? uxtab r2, r3, r5 +0+264 <[^>]*> e6e32475 ? uxtab r2, r3, r5, ror #8 +0+268 <[^>]*> 16e32075 ? uxtabne r2, r3, r5 +0+26c <[^>]*> 16e32475 ? uxtabne r2, r3, r5, ror #8 +0+270 <[^>]*> e6542f37 ? uasx r2, r4, r7 +0+274 <[^>]*> 16542f37 ? uasxne r2, r4, r7 +0+278 <[^>]*> e6742f17 ? uhadd16 r2, r4, r7 +0+27c <[^>]*> 16742f17 ? uhadd16ne r2, r4, r7 +0+280 <[^>]*> e6742f97 ? uhadd8 r2, r4, r7 +0+284 <[^>]*> 16742f97 ? uhadd8ne r2, r4, r7 +0+288 <[^>]*> e6742f37 ? uhasx r2, r4, r7 +0+28c <[^>]*> 16742f37 ? uhasxne r2, r4, r7 +0+290 <[^>]*> e6742f77 ? uhsub16 r2, r4, r7 +0+294 <[^>]*> 16742f77 ? uhsub16ne r2, r4, r7 +0+298 <[^>]*> e6742ff7 ? uhsub8 r2, r4, r7 +0+29c <[^>]*> 16742ff7 ? uhsub8ne r2, r4, r7 +0+2a0 <[^>]*> e6742f57 ? uhsax r2, r4, r7 +0+2a4 <[^>]*> 16742f57 ? uhsaxne r2, r4, r7 +0+2a8 <[^>]*> e0421493 ? umaal r1, r2, r3, r4 +0+2ac <[^>]*> d0421493 ? umaalle r1, r2, r3, r4 +0+2b0 <[^>]*> e6642f17 ? uqadd16 r2, r4, r7 +0+2b4 <[^>]*> 16642f17 ? uqadd16ne r2, r4, r7 +0+2b8 <[^>]*> e6642f97 ? uqadd8 r2, r4, r7 +0+2bc <[^>]*> 16642f97 ? uqadd8ne r2, r4, r7 +0+2c0 <[^>]*> e6642f37 ? uqasx r2, r4, r7 +0+2c4 <[^>]*> 16642f37 ? uqasxne r2, r4, r7 +0+2c8 <[^>]*> e6642f77 ? uqsub16 r2, r4, r7 +0+2cc <[^>]*> 16642f77 ? uqsub16ne r2, r4, r7 +0+2d0 <[^>]*> e6642ff7 ? uqsub8 r2, r4, r7 +0+2d4 <[^>]*> 16642ff7 ? uqsub8ne r2, r4, r7 +0+2d8 <[^>]*> e6642f57 ? uqsax r2, r4, r7 +0+2dc <[^>]*> 16642f57 ? uqsaxne r2, r4, r7 +0+2e0 <[^>]*> e781f312 ? usad8 r1, r2, r3 +0+2e4 <[^>]*> 1781f312 ? usad8ne r1, r2, r3 +0+2e8 <[^>]*> e7814312 ? usada8 r1, r2, r3, r4 +0+2ec <[^>]*> 17814312 ? usada8ne r1, r2, r3, r4 +0+2f0 <[^>]*> e6ef1012 ? usat r1, #15, r2 +0+2f4 <[^>]*> e6ef1252 ? usat r1, #15, r2, asr #4 +0+2f8 <[^>]*> e6ef1212 ? usat r1, #15, r2, lsl #4 +0+2fc <[^>]*> e6ef1f32 ? usat16 r1, #15, r2 +0+300 <[^>]*> d6ef1f32 ? usat16le r1, #15, r2 +0+304 <[^>]*> d6ef1012 ? usatle r1, #15, r2 +0+308 <[^>]*> d6ef1252 ? usatle r1, #15, r2, asr #4 +0+30c <[^>]*> d6ef1212 ? usatle r1, #15, r2, lsl #4 +0+310 <[^>]*> e6542f77 ? usub16 r2, r4, r7 +0+314 <[^>]*> 16542f77 ? usub16ne r2, r4, r7 +0+318 <[^>]*> e6542ff7 ? usub8 r2, r4, r7 +0+31c <[^>]*> 16542ff7 ? usub8ne r2, r4, r7 +0+320 <[^>]*> e6542f57 ? usax r2, r4, r7 +0+324 <[^>]*> 16542f57 ? usaxne r2, r4, r7 +0+328 <[^>]*> e6ff2075 ? uxth r2, r5 +0+32c <[^>]*> e6ff2475 ? uxth r2, r5, ror #8 +0+330 <[^>]*> 16ff2075 ? uxthne r2, r5 +0+334 <[^>]*> 16ff2475 ? uxthne r2, r5, ror #8 +0+338 <[^>]*> e6cf2075 ? uxtb16 r2, r5 +0+33c <[^>]*> e6cf2475 ? uxtb16 r2, r5, ror #8 +0+340 <[^>]*> 16cf2075 ? uxtb16ne r2, r5 +0+344 <[^>]*> 16cf2475 ? uxtb16ne r2, r5, ror #8 +0+348 <[^>]*> e6ef2075 ? uxtb r2, r5 +0+34c <[^>]*> e6ef2475 ? uxtb r2, r5, ror #8 +0+350 <[^>]*> 16ef2075 ? uxtbne r2, r5 +0+354 <[^>]*> 16ef2475 ? uxtbne r2, r5, ror #8 +0+358 <[^>]*> f10a00ca ? cpsie if,#10 +0+35c <[^>]*> f10a00d5 ? cpsie if,#21 +0+360 <[^>]*> f8cd0510 ? srsia sp, #16 +0+364 <[^>]*> f9ed0510 ? srsib sp!, #16 diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6.s b/binutils-2.25/gas/testsuite/gas/arm/archv6.s new file mode 100644 index 00000000..bc8ea72b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6.s @@ -0,0 +1,222 @@ +.text +.align 0 + +label: + cps #15 + cpsid if + cpsie if + ldrex r2, [r4] + ldrexne r4, [r8] + mcrr2 p0, 12, r7, r5, c3 + mrrc2 p0, 12, r7, r5, c3 + pkhbt r2, r5, r8 + pkhbt r2, r5, r8, LSL #3 + pkhbtal r2, r5, r8, LSL #3 + pkhbteq r2, r5, r8, LSL #3 + pkhtb r2, r5, r8 @ Equivalent to pkhbt r2, r8, r5. + pkhtb r2, r5, r8, ASR #3 + pkhtbal r2, r5, r8, ASR #3 + pkhtbeq r2, r5, r8, ASR #3 + qadd16 r2, r4, r7 + qadd16ne r2, r4, r7 + qadd8 r2, r4, r7 + qadd8ne r2, r4, r7 + qaddsubx r2, r4, r7 + qaddsubxne r2, r4, r7 + qsub16 r2, r4, r7 + qsub16ne r2, r4, r7 + qsub8 r2, r4, r7 + qsub8ne r2, r4, r7 + qsubaddx r2, r4, r7 + qsubaddx r2, r4, r7 + rev r2, r4 + rev16 r2, r4 + rev16ne r3, r5 + revne r3, r5 + revsh r2, r4 + revshne r3, r5 + rfeda r2 + rfefa r2! + rfedb r2 + rfeea r2! + rfeia r2 + rfefd r2! + rfeib r2 + rfeed r2! + rfe r2 + rfe r2! + sadd16 r2, r4, r7 + sadd16ne r2, r4, r7 + sxtah r2, r4, r5 + sxtah r2, r4, r5, ROR #8 + sxtahne r2, r4, r5 + sxtahne r2, r4, r5, ROR #8 + sadd8 r2, r4, r7 + sadd8ne r2, r4, r7 + sxtab16 r2, r4, r5 + sxtab16 r2, r4, r5, ROR #8 + sxtab16ne r2, r4, r5 + sxtab16ne r2, r4, r5, ROR #8 + sxtab r2, r4, r5 + sxtab r2, r4, r5, ROR #8 + sxtabne r2, r4, r5 + sxtabne r2, r4, r5, ROR #8 + saddsubx r2, r4, r7 + saddsubxne r2, r4, r7 + sel r1, r2, r3 + selne r1, r2, r3 + setend be + setend le + shadd16 r2, r4, r7 + shadd16ne r2, r4, r7 + shadd8 r2, r4, r7 + shadd8ne r2, r4, r7 + shaddsubx r2, r4, r7 + shaddsubxne r2, r4, r7 + shsub16 r2, r4, r7 + shsub16ne r2, r4, r7 + shsub8 r2, r4, r7 + shsub8ne r2, r4, r7 + shsubaddx r2, r4, r7 + shsubaddxne r2, r4, r7 + smlad r1,r2,r3,r4 + smladle r1,r2,r3,r4 + smladx r1,r2,r3,r4 + smladxle r1,r2,r3,r4 + smlald r1,r2,r3,r4 + smlaldle r1,r2,r3,r4 + smlaldx r1,r2,r3,r4 + smlaldxle r1,r2,r3,r4 + smlsd r1,r2,r3,r4 + smlsdle r1,r2,r3,r4 + smlsdx r1,r2,r3,r4 + smlsdxle r1,r2,r3,r4 + smlsld r1,r2,r3,r4 + smlsldle r1,r2,r3,r4 + smlsldx r1,r2,r3,r4 + smlsldxle r1,r2,r3,r4 + smmla r1,r2,r3,r4 + smmlale r1,r2,r3,r4 + smmlar r1,r2,r3,r4 + smmlarle r1,r2,r3,r4 + smmls r1,r2,r3,r4 + smmlsle r1,r2,r3,r4 + smmlsr r1,r2,r3,r4 + smmlsrle r1,r2,r3,r4 + smmul r1,r2,r3 + smmulle r1,r2,r3 + smmulr r1,r2,r3 + smmulrle r1,r2,r3 + smuad r1,r2,r3 + smuadle r1,r2,r3 + smuadx r1,r2,r3 + smuadxle r1,r2,r3 + smusd r1,r2,r3 + smusdle r1,r2,r3 + smusdx r1,r2,r3 + smusdxle r1,r2,r3 + srsia #16 + srsib #16! + ssat r1, #1, r2 + ssat r1, #1, r2, ASR #2 + ssat r1, #1, r2, LSL #2 + ssat16 r1, #1, r1 + ssat16le r1, #1, r1 + ssub16 r2, r4, r7 + ssub16ne r2, r4, r7 + ssub8 r2, r4, r7 + ssub8ne r2, r4, r7 + ssubaddx r2, r4, r7 + ssubaddxne r2, r4, r7 + strex r1, r2, [r3] + strexne r1, r2, [r3] + sxth r2, r5 + sxth r2, r5, ROR #8 + sxthne r2, r5 + sxthne r2, r5, ROR #8 + sxtb16 r2, r5 + sxtb16 r2, r5, ROR #8 + sxtb16ne r2, r5 + sxtb16ne r2, r5, ROR #8 + sxtb r2, r5 + sxtb r2, r5, ROR #8 + sxtbne r2, r5 + sxtbne r2, r5, ROR #8 + uadd16 r2, r4, r7 + uadd16ne r2, r4, r7 + uxtah r2, r3, r5 + uxtah r2, r3, r5, ROR #8 + uxtahne r2, r3, r5 + uxtahne r2, r3, r5, ROR #8 + uadd8 r2, r4, r7 + uadd8ne r2, r4, r7 + uxtab16 r2, r3, r5 + uxtab16 r2, r3, r5, ROR #8 + uxtab16ne r2, r3, r5 + uxtab16ne r2, r3, r5, ROR #8 + uxtab r2, r3, r5 + uxtab r2, r3, r5, ROR #8 + uxtabne r2, r3, r5 + uxtabne r2, r3, r5, ROR #8 + uaddsubx r2, r4, r7 + uaddsubxne r2, r4, r7 + uhadd16 r2, r4, r7 + uhadd16ne r2, r4, r7 + uhadd8 r2, r4, r7 + uhadd8ne r2, r4, r7 + uhaddsubx r2, r4, r7 + uhaddsubxne r2, r4, r7 + uhsub16 r2, r4, r7 + uhsub16ne r2, r4, r7 + uhsub8 r2, r4, r7 + uhsub8ne r2, r4, r7 + uhsubaddx r2, r4, r7 + uhsubaddxne r2, r4, r7 + umaal r1, r2, r3, r4 + umaalle r1, r2, r3, r4 + uqadd16 r2, r4, r7 + uqadd16ne r2, r4, r7 + uqadd8 r2, r4, r7 + uqadd8ne r2, r4, r7 + uqaddsubx r2, r4, r7 + uqaddsubxne r2, r4, r7 + uqsub16 r2, r4, r7 + uqsub16ne r2, r4, r7 + uqsub8 r2, r4, r7 + uqsub8ne r2, r4, r7 + uqsubaddx r2, r4, r7 + uqsubaddxne r2, r4, r7 + usad8 r1, r2, r3 + usad8ne r1, r2, r3 + usada8 r1, r2, r3, r4 + usada8ne r1, r2, r3, r4 + usat r1, #15, r2 + usat r1, #15, r2, ASR #4 + usat r1, #15, r2, LSL #4 + usat16 r1, #15, r2 + usat16le r1, #15, r2 + usatle r1, #15, r2 + usatle r1, #15, r2, ASR #4 + usatle r1, #15, r2, LSL #4 + usub16 r2, r4, r7 + usub16ne r2, r4, r7 + usub8 r2, r4, r7 + usub8ne r2, r4, r7 + usubaddx r2, r4, r7 + usubaddxne r2, r4, r7 + uxth r2, r5 + uxth r2, r5, ROR #8 + uxthne r2, r5 + uxthne r2, r5, ROR #8 + uxtb16 r2, r5 + uxtb16 r2, r5, ROR #8 + uxtb16ne r2, r5 + uxtb16ne r2, r5, ROR #8 + uxtb r2, r5 + uxtb r2, r5, ROR #8 + uxtbne r2, r5 + uxtbne r2, r5, ROR #8 + cpsie if, #10 + cpsie if, #21 + srsia sp, #16 + srsib sp!, #16 diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6m.d b/binutils-2.25/gas/testsuite/gas/arm/archv6m.d new file mode 100644 index 00000000..2ad48a76 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6m.d @@ -0,0 +1,18 @@ +# name: ARMv6-M +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f386 8800 msr (APSR|CPSR_f), r6 +0[0-9a-f]+ <[^>]+> f389 8806 msr EPSR, r9 +0[0-9a-f]+ <[^>]+> f3ef 8201 mrs r2, IAPSR +0[0-9a-f]+ <[^>]+> bf10 yield +0[0-9a-f]+ <[^>]+> bf20 wfe +0[0-9a-f]+ <[^>]+> bf30 wfi +0[0-9a-f]+ <[^>]+> bf40 sev +0[0-9a-f]+ <[^>]+> 4408 add r0, r1 +0[0-9a-f]+ <[^>]+> 46c0 nop.* +0[0-9a-f]+ <[^>]+> f3bf 8f5f dmb sy +0[0-9a-f]+ <[^>]+> f3bf 8f4f dsb sy +0[0-9a-f]+ <[^>]+> f3bf 8f6f isb sy diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6m.s b/binutils-2.25/gas/testsuite/gas/arm/archv6m.s new file mode 100644 index 00000000..137baccd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6m.s @@ -0,0 +1,20 @@ + .arch armv6-m + .syntax unified + .thumb + .text + .align 2 + .global foo +foo: + msr apsr_nzcvq,r6 + msr epsr,r9 + mrs r2, iapsr + yield + wfe + wfi + sev + add r0, r0, r1 + nop + dmb + dsb + isb + diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6s-m-bad.d b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m-bad.d new file mode 100644 index 00000000..d50d34f6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m-bad.d @@ -0,0 +1,4 @@ +#name: Valid v6S-M, invalid v6-M +#as: -march=armv6-m +#source: archv6s-m.s +#error-output: archv6s-m-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6s-m-bad.l b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m-bad.l new file mode 100644 index 00000000..e17420ba --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m-bad.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: SVC is not permitted on this architecture diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6s-m.d b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m.d new file mode 100644 index 00000000..dd7f12c3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m.d @@ -0,0 +1,9 @@ +#name: Valid v6S-M +#as: -march=armv6s-m +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> df00 svc 0 +0[0-9a-f]+ <[^>]+> 46c0 nop.+ diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6s-m.s b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m.s new file mode 100644 index 00000000..6cd56537 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6s-m.s @@ -0,0 +1,8 @@ + .syntax unified + .thumb + .text + .align 2 + .global foo +foo: + svc #0 + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.d b/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.d new file mode 100644 index 00000000..9b8e1b90 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.d @@ -0,0 +1,3 @@ +#name: Invalid V6T2 instructions +#as: -march=armv6t2 +#error-output: archv6t2-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.l b/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.l new file mode 100644 index 00000000..0f00db37 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.l @@ -0,0 +1,40 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: r15 not allowed here -- `bfc pc,#0,#1' +[^:]*:7: Error: r15 not allowed here -- `bfi pc,r0,#0,#1' +[^:]*:8: Error: r15 not allowed here -- `movw pc,#0' +[^:]*:9: Error: r15 not allowed here -- `movt pc,#0' +[^:]*:12: Error: immediate value out of range -- `bfc r0,#0,#0' +[^:]*:13: Error: immediate value out of range -- `bfc r0,#32,#0' +[^:]*:14: Error: immediate value out of range -- `bfc r0,#0,#33' +[^:]*:15: Error: immediate value out of range -- `bfc r0,#33,#1' +[^:]*:16: Error: immediate value out of range -- `bfc r0,#32,#1' +[^:]*:17: Error: bit-field extends past end of register -- `bfc r0,#28,#10' +[^:]*:19: Error: immediate value out of range -- `bfi r0,r1,#0,#0' +[^:]*:20: Error: immediate value out of range -- `bfi r0,r1,#32,#0' +[^:]*:21: Error: immediate value out of range -- `bfi r0,r1,#0,#33' +[^:]*:22: Error: immediate value out of range -- `bfi r0,r1,#33,#1' +[^:]*:23: Error: immediate value out of range -- `bfi r0,r1,#32,#1' +[^:]*:24: Error: bit-field extends past end of register -- `bfi r0,r1,#28,#10' +[^:]*:26: Error: immediate value out of range -- `sbfx r0,r1,#0,#0' +[^:]*:27: Error: immediate value out of range -- `sbfx r0,r1,#32,#0' +[^:]*:28: Error: immediate value out of range -- `sbfx r0,r1,#0,#33' +[^:]*:29: Error: immediate value out of range -- `sbfx r0,r1,#33,#1' +[^:]*:30: Error: immediate value out of range -- `sbfx r0,r1,#32,#1' +[^:]*:31: Error: bit-field extends past end of register -- `sbfx r0,r1,#28,#10' +[^:]*:33: Error: immediate value out of range -- `ubfx r0,r1,#0,#0' +[^:]*:34: Error: immediate value out of range -- `ubfx r0,r1,#32,#0' +[^:]*:35: Error: immediate value out of range -- `ubfx r0,r1,#0,#33' +[^:]*:36: Error: immediate value out of range -- `ubfx r0,r1,#33,#1' +[^:]*:37: Error: immediate value out of range -- `ubfx r0,r1,#32,#1' +[^:]*:38: Error: bit-field extends past end of register -- `ubfx r0,r1,#28,#10' +[^:]*:41: Error: immediate value out of range -- `bfi r0,#1,#2,#3' +[^:]*:44: Error: immediate value out of range -- `movt r0,#65537' +[^:]*:45: Error: immediate value out of range -- `movw r0,#65537' +[^:]*:46: Error: immediate value out of range -- `movt r0,#-1' +[^:]*:47: Error: immediate value out of range -- `movw r0,#-1' +[^:]*:50: Warning: destination register same as write-back base +[^:]*:51: Warning: destination register same as write-back base +[^:]*:52: Warning: destination register same as write-back base +[^:]*:53: Warning: source register same as write-back base +[^:]*:59: Error: instruction does not accept this addressing mode -- `ldrex r0,r2' +[^:]*:60: Error: instruction does not accept this addressing mode -- `strex r1,r0,r2' diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.s b/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.s new file mode 100644 index 00000000..af139727 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6t2-bad.s @@ -0,0 +1,61 @@ + @ We do not bother testing simple cases, e.g. immediates where + @ registers belong, trailing junk at end of line. + .text +x: + @ pc not allowed + bfc pc,#0,#1 + bfi pc,r0,#0,#1 + movw pc,#0 + movt pc,#0 + + @ bitfield range limits + bfc r0,#0,#0 + bfc r0,#32,#0 + bfc r0,#0,#33 + bfc r0,#33,#1 + bfc r0,#32,#1 + bfc r0,#28,#10 + + bfi r0,r1,#0,#0 + bfi r0,r1,#32,#0 + bfi r0,r1,#0,#33 + bfi r0,r1,#33,#1 + bfi r0,r1,#32,#1 + bfi r0,r1,#28,#10 + + sbfx r0,r1,#0,#0 + sbfx r0,r1,#32,#0 + sbfx r0,r1,#0,#33 + sbfx r0,r1,#33,#1 + sbfx r0,r1,#32,#1 + sbfx r0,r1,#28,#10 + + ubfx r0,r1,#0,#0 + ubfx r0,r1,#32,#0 + ubfx r0,r1,#0,#33 + ubfx r0,r1,#33,#1 + ubfx r0,r1,#32,#1 + ubfx r0,r1,#28,#10 + + @ bfi accepts only #0 in Rm position + bfi r0,#1,#2,#3 + + @ mov16 range limits + movt r0,#65537 + movw r0,#65537 + movt r0,#-1 + movw r0,#-1 + + @ ldsttv4 Rd == Rn (warning) + ldrht r0,[r0] + ldrsbt r0,[r0] + ldrsht r0,[r0] + strht r0,[r0] + + @ Bug reported by user. GAS used to issue an error message + @ "r15 not allowed here" for these two instructions because + @ it thought that the "r2" operand was a PC-relative branch + @ to a label called "r2". + ldrex r0, r2 + strex r1, r0, r2 +
\ No newline at end of file diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6t2.d b/binutils-2.25/gas/testsuite/gas/arm/archv6t2.d new file mode 100644 index 00000000..eb76a321 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6t2.d @@ -0,0 +1,63 @@ +#name: ARM V6T2 instructions +#as: -march=armv6t2 +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e7c00010 bfi r0, r0, #0, #1 +0+04 <[^>]+> 17c00010 bfine r0, r0, #0, #1 +0+08 <[^>]+> e7c09010 bfi r9, r0, #0, #1 +0+0c <[^>]+> e7c00019 bfi r0, r9, #0, #1 +0+10 <[^>]+> e7d10010 bfi r0, r0, #0, #18 +0+14 <[^>]+> e7d10890 bfi r0, r0, #17, #1 +0+18 <[^>]+> e7c0001f bfc r0, #0, #1 +0+1c <[^>]+> e7c0001f bfc r0, #0, #1 +0+20 <[^>]+> 17c0001f bfcne r0, #0, #1 +0+24 <[^>]+> e7c0901f bfc r9, #0, #1 +0+28 <[^>]+> e7d1001f bfc r0, #0, #18 +0+2c <[^>]+> e7d1089f bfc r0, #17, #1 +0+30 <[^>]+> e7a00050 sbfx r0, r0, #0, #1 +0+34 <[^>]+> 17a00050 sbfxne r0, r0, #0, #1 +0+38 <[^>]+> e7e00050 ubfx r0, r0, #0, #1 +0+3c <[^>]+> e7a09050 sbfx r9, r0, #0, #1 +0+40 <[^>]+> e7a00059 sbfx r0, r9, #0, #1 +0+44 <[^>]+> e7a008d0 sbfx r0, r0, #17, #1 +0+48 <[^>]+> e7b10050 sbfx r0, r0, #0, #18 +0+4c <[^>]+> e6ff0f30 rbit r0, r0 +0+50 <[^>]+> 16ff0f30 rbitne r0, r0 +0+54 <[^>]+> e6ff9f30 rbit r9, r0 +0+58 <[^>]+> e6ff0f39 rbit r0, r9 +0+5c <[^>]+> e0600090 mls r0, r0, r0, r0 +0+60 <[^>]+> 10600090 mlsne r0, r0, r0, r0 +0+64 <[^>]+> e0690090 mls r9, r0, r0, r0 +0+68 <[^>]+> e0600099 mls r0, r9, r0, r0 +0+6c <[^>]+> e0600990 mls r0, r0, r9, r0 +0+70 <[^>]+> e0609090 mls r0, r0, r0, r9 +0+74 <[^>]+> e3000000 movw r0, #0 +0+78 <[^>]+> e3400000 movt r0, #0 +0+7c <[^>]+> 13000000 movwne r0, #0 +0+80 <[^>]+> e3009000 movw r9, #0 +0+84 <[^>]+> e3000999 movw r0, #2457 ; 0x999 +0+88 <[^>]+> e3090000 movw r0, #36864 ; 0x9000 +0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\], #0 +0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\], #0 +0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\], #0 +0+98 <[^>]+> e0e900b0 strht r0, \[r9\], #0 +0+9c <[^>]+> 10f900b0 ldrhtne r0, \[r9\], #0 +0+a0 <[^>]+> e0b090b9 ldrht r9, \[r0\], r9 +0+a4 <[^>]+> e03090b9 ldrht r9, \[r0\], -r9 +0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153.* +0+ac <[^>]+> e07099b9 ldrht r9, \[r0\], #-153.* +0+b0 <[^>]+> 10b090b9 ldrhtne r9, \[r0\], r9 +0+b4 <[^>]+> 103090b9 ldrhtne r9, \[r0\], -r9 +0+b8 <[^>]+> 10f099b9 ldrhtne r9, \[r0\], #153 ; 0x99 +0+bc <[^>]+> 107099b9 ldrhtne r9, \[r0\], #-153 ; 0xffffff67 +0+c0 <[^>]+> e02100b2 strht r0, \[r1\], -r2 +0+c4 <[^>]+> 102100b2 strhtne r0, \[r1\], -r2 +0+c8 <[^>]+> e0a100b2 strht r0, \[r1\], r2 +0+cc <[^>]+> 10a100b2 strhtne r0, \[r1\], r2 +0+d0 <[^>]+> e0e100b2 strht r0, \[r1\], #2 +0+d4 <[^>]+> e06100b2 strht r0, \[r1\], #-2 +0+d8 <[^>]+> 10e100b2 strhtne r0, \[r1\], #2 +0+dc <[^>]+> 106100b2 strhtne r0, \[r1\], #-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/archv6t2.s b/binutils-2.25/gas/testsuite/gas/arm/archv6t2.s new file mode 100644 index 00000000..81ff5012 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/archv6t2.s @@ -0,0 +1,67 @@ + .text +x: + bfi r0, r0, #0, #1 + bfine r0, r0, #0, #1 + + bfi r9, r0, #0, #1 + bfi r0, r9, #0, #1 + bfi r0, r0, #0, #18 + bfi r0, r0, #17, #1 + + bfi r0, #0, #0, #1 + bfc r0, #0, #1 + bfcne r0, #0, #1 + bfc r9, #0, #1 + bfc r0, #0, #18 + bfc r0, #17, #1 + + sbfx r0, r0, #0, #1 + sbfxne r0, r0, #0, #1 + ubfx r0, r0, #0, #1 + sbfx r9, r0, #0, #1 + sbfx r0, r9, #0, #1 + sbfx r0, r0, #17, #1 + sbfx r0, r0, #0, #18 + + rbit r0, r0 + rbitne r0, r0 + rbit r9, r0 + rbit r0, r9 + + mls r0, r0, r0, r0 + mlsne r0, r0, r0, r0 + mls r9, r0, r0, r0 + mls r0, r9, r0, r0 + mls r0, r0, r9, r0 + mls r0, r0, r0, r9 + + movw r0, #0 + movt r0, #0 + movwne r0, #0 + movw r9, #0 + movw r0, #0x0999 + movw r0, #0x9000 + + @ for these, we must avoid write-back warnings + ldrht r0, [r9] + ldrsht r0, [r9] + ldrsbt r0, [r9] + strht r0, [r9] + ldrneht r0, [r9] + + ldrht r9, [r0], r9 + ldrht r9, [r0], -r9 + ldrht r9, [r0], #0x99 + ldrht r9, [r0], #-0x99 + ldrneht r9, [r0], r9 + ldrneht r9, [r0], -r9 + ldrneht r9, [r0], #0x99 + ldrneht r9, [r0], #-0x99 + strht r0, [r1], -r2 + strneht r0, [r1], -r2 + strht r0, [r1], r2 + strneht r0, [r1], r2 + strht r0, [r1], #2 + strht r0, [r1], #-2 + strneht r0, [r1], #2 + strneht r0, [r1], #-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.d b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.d new file mode 100644 index 00000000..c3d73941 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.d @@ -0,0 +1,4 @@ +#name: Invalid V7 ARM DIV instructions +#as: -march=armv7-a +#error-output: arm-idiv-bad.l + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.l b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.l new file mode 100644 index 00000000..6662cc7a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: selected processor does not support ARM mode `sdiv r0,r0,r0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.s b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.s new file mode 100644 index 00000000..45e846e7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv-bad.s @@ -0,0 +1,4 @@ + .text + .arm +label: + sdiv r0, r0, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-idiv.d b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv.d new file mode 100644 index 00000000..a886d025 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv.d @@ -0,0 +1,9 @@ +#name: ARM Integer division instructions +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> e735f819 udiv r5, r9, r8 +0+004 <[^>]*> e739f715 udiv r9, r5, r7 +0+008 <[^>]*> e710f010 sdiv r0, r0, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-idiv.s b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv.s new file mode 100644 index 00000000..626a67dd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-idiv.s @@ -0,0 +1,8 @@ +.arch armv7-a +.arch_extension idiv +.arm +udiv r5, r9, r8 +.cpu cortex-a15 +udiv r9, r5, r7 +.cpu cortex-r5 +sdiv r0, r0, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-2.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-2.d new file mode 100644 index 00000000..bff265dd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-2.d @@ -0,0 +1,15 @@ +#name: ARM IT automatic instruction generation 2 +#as: -mthumb -march=armv7a -mimplicit-it=always +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <.text> 3a40 subs r2, #64.* +00000002 <.text\+0x2> bfa1 itttt ge +00000004 <.text\+0x4> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr} +00000008 <.text\+0x8> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr} +0000000c <.text\+0xc> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr} +00000010 <.text\+0x10> e8a0 500a stmiage.w r0!, {r1, r3, ip, lr} +00000014 <.text\+0x14> dcf4 bgt.n 00000000 <.text> diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-2.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-2.s new file mode 100644 index 00000000..0026bc2a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-2.s @@ -0,0 +1,8 @@ +.syntax unified +2: subs r2, r2, #64 + @ IT generated automatically + stmge r0!, {r1, r3, ip, lr} @ 64 bytes at a time. + stmge r0!, {r1, r3, ip, lr} + stmge r0!, {r1, r3, ip, lr} + stmge r0!, {r1, r3, ip, lr} + bgt 2b @ This should not generate a new IT block diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-3.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-3.d new file mode 100644 index 00000000..c0398950 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-3.d @@ -0,0 +1,15 @@ +#name: ARM IT automatic instruction generation 3 +#as: -mthumb -march=armv7a -mimplicit-it=always +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text.one: +00000000 <.text.one> 2800 cmp r0, #0 +00000002 <.text.one\+0x2> bf08 it eq +00000004 <.text.one\+0x4> 3102 addeq r1, #2 + +Disassembly of section .text.two: +00000000 <.text.two> bf08 it eq +00000002 <.text.two\+0x2> 3103 addeq r1, #3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-3.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-3.s new file mode 100644 index 00000000..d82e3a9e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto-3.s @@ -0,0 +1,10 @@ + .syntax unified + .thumb + .section .text.one + cmp r0, #0 + addeq r1, #2 + .data + .word 33 + .section .text.two + addeq r1, #3 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto.d new file mode 100644 index 00000000..bfdd9d64 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto.d @@ -0,0 +1,81 @@ +#name: ARM IT automatic instruction generation +#as: -mthumb -march=armv7 -mimplicit-it=always +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <main> f000 f821 bl 00000046 <main\+0x46> +00000004 <main\+0x4> f000 f80c bl 00000020 <main\+0x20> +00000008 <main\+0x8> f000 f813 bl 00000032 <main\+0x32> +0000000c <main\+0xc> d142 bne.n 00000094 <main\+0x94> +0000000e <main\+0xe> bf18 it ne +00000010 <main\+0x10> 4487 addne pc, r0 +00000012 <main\+0x12> bf18 it ne +00000014 <main\+0x14> e8d0 f001 tbbne \[r0, r1\] +00000018 <main\+0x18> bf08 it eq +0000001a <main\+0x1a> e8d1 f010 tbheq \[r1, r0, lsl #1\] +0000001e <main\+0x1e> bf0a itet eq +00000020 <main\+0x20> 2002 moveq r0, #2 +00000022 <main\+0x22> 2003 movne r0, #3 +00000024 <main\+0x24> 2004 moveq r0, #4 +00000026 <main\+0x26> bf16 itet ne +00000028 <main\+0x28> 2002 movne r0, #2 +0000002a <main\+0x2a> 2003 moveq r0, #3 +0000002c <main\+0x2c> 2004 movne r0, #4 +0000002e <main\+0x2e> bf18 it ne +00000030 <main\+0x30> 2001 movne r0, #1 +00000032 <main\+0x32> bf0c ite eq +00000034 <main\+0x34> 2002 moveq r0, #2 +00000036 <main\+0x36> f8d1 f000 ldrne.w pc, \[r1\] +0000003a <main\+0x3a> bf18 it ne +0000003c <main\+0x3c> f000 f82a blne 00000094 <main\+0x94> +00000040 <main\+0x40> bfb8 it lt +00000042 <main\+0x42> f000 f828 bllt 00000096 <main\+0x96> +00000046 <main\+0x46> bf17 itett ne +00000048 <main\+0x48> 202d movne r0, #45.* +0000004a <main\+0x4a> 2005 moveq r0, #5 +0000004c <main\+0x4c> 2006 movne r0, #6 +0000004e <main\+0x4e> 4487 addne pc, r0 +00000050 <main\+0x50> bf0d iteet eq +00000052 <main\+0x52> 2007 moveq r0, #7 +00000054 <main\+0x54> 2008 movne r0, #8 +00000056 <main\+0x56> 2003 movne r0, #3 +00000058 <main\+0x58> 2004 moveq r0, #4 +0000005a <main\+0x5a> bf0b itete eq +0000005c <main\+0x5c> 2005 moveq r0, #5 +0000005e <main\+0x5e> 2006 movne r0, #6 +00000060 <main\+0x60> 2007 moveq r0, #7 +00000062 <main\+0x62> 2008 movne r0, #8 +00000064 <main\+0x64> bf0c ite eq +00000066 <main\+0x66> 2005 moveq r0, #5 +00000068 <main\+0x68> 2006 movne r0, #6 +0000006a <main\+0x6a> 4687 mov pc, r0 +0000006c <main\+0x6c> bf0b itete eq +0000006e <main\+0x6e> 2007 moveq r0, #7 +00000070 <main\+0x70> 2008 movne r0, #8 +00000072 <main\+0x72> 2005 moveq r0, #5 +00000074 <main\+0x74> 2006 movne r0, #6 +00000076 <main\+0x76> 4487 add pc, r0 +00000078 <main\+0x78> bf0c ite eq +0000007a <main\+0x7a> 2007 moveq r0, #7 +0000007c <main\+0x7c> 2008 movne r0, #8 +0000007e <main\+0x7e> bfcc ite gt +00000080 <main\+0x80> 2009 movgt r0, #9 +00000082 <main\+0x82> 200a movle r0, #10 +00000084 <main\+0x84> bf08 it eq +00000086 <main\+0x86> 200b moveq r0, #11 +00000088 <main\+0x88> bfd8 it le +0000008a <main\+0x8a> 200c movle r0, #12 +0000008c <main\+0x8c> bf18 it ne +0000008e <main\+0x8e> 200d movne r0, #13 +00000090 <main\+0x90> f... f... bl 0000000. <f.*> +00000094 <main\+0x94> bd10 pop {r4, pc} +00000096 <main\+0x96> f... f... bl 0000000. <f.*> +0000009a <main\+0x9a> bfb8 it lt +0000009c <main\+0x9c> 2000 movlt r0, #0 +0000009e <main\+0x9e> 4348 muls r0, r1 +000000a0 <main\+0xa0> bfb8 it lt +000000a2 <main\+0xa2> 2000 movlt r0, #0 +000000a4 <main\+0xa4> 4348 muls r0, r1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto.s new file mode 100644 index 00000000..b10a36ec --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-auto.s @@ -0,0 +1,110 @@ + .syntax unified + .arch armv7 + .thumb +main: + +@These branches are to see the labels in the generated file + bl .L888 + bl .L111 + bl .L777 + +@No IT block here: + bne .L4 + +@The following groups should be an IT block each. +@it ne + addne.n pc, r0 + +@it ne + tbbne [r0, r1] + +@it eq + tbheq [r1, r0] + +@The following group should be left as is: + itet eq +.L111: moveq r0, #2 + movne r0, #3 + moveq r0, #4 + +@Same, reverted condition: + itet ne + movne r0, #2 + moveq r0, #3 + movne r0, #4 + + +@Two groups shall be generated, due to the label: + movne r0, #1 +@ second group, the label should be at the IT insn +.L777: moveq r0, #2 + ldrne pc, [r1] + +@it ne + blne .L4 + +@it lt + bllt .L9 + +@itett ne +.L888: movne r0, #45 + moveq r0, #5 + movne r0, #6 + addne.n pc, r0 + +@iteet eq + moveq r0, #7 + movne r0, #8 + movne r0, #3 + moveq r0, #4 + +@itete eq + moveq r0, #5 + movne r0, #6 + moveq r0, #7 + movne r0, #8 + +@ite eq - this group finishes due to the mov.n pc, rn + moveq r0, #5 + movne r0, #6 + mov.n pc, r0 + +@itete eq + moveq r0, #7 + movne r0, #8 + moveq r0, #5 + movne r0, #6 + +@this shall not generate an IT block + add.n pc, r0 + +@ite eq - testing condition change (eq -> gt) + moveq r0, #7 + movne r0, #8 + +@ite gt (group shall finish due to another condition change) + movgt r0, #9 + movle r0, #10 + +@it eq + moveq r0, #11 + +@it le + movle r0, #12 + +@it ne + movne r0, #13 + + bl f +.L4: + pop {r4, pc} +.L9: + bl f + +@Only the movlt shall be enclosed in the IT block +movlt r0, #0 +muls r0, r0, r1 + +@Same here: +movlt r0, #0 +muls r0, r0, r1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.d new file mode 100644 index 00000000..2a644a3e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.d @@ -0,0 +1,4 @@ +#name: Test unclosed IT block validation. +#as: -march=armv7a +#skip: *-*-*aout* *-*-pe +#error-output: arm-it-bad-2.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.l b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.l new file mode 100644 index 00000000..3414ef7e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:9: Warning: section '.text' finished with an open IT block. +[^:]*:9: Warning: section 'second' finished with an open IT block. diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.s new file mode 100644 index 00000000..477975ec --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-2.s @@ -0,0 +1,9 @@ + .syntax unified + .text + cmp r0, #0 + itt eq + moveq r0, r1 +.section second + itt ne + movne r0, r1 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.d new file mode 100644 index 00000000..75e84b44 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.d @@ -0,0 +1,3 @@ +#name: Test automatic IT generation in Thumb-1 architectures. +#as: -mimplicit-it=always +#error-output: arm-it-bad-3.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.l b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.l new file mode 100644 index 00000000..7bb20d13 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: thumb conditional instruction should be in IT block -- `moveq r1,r8' +[^:]*:5: Error: thumb conditional instruction should be in IT block -- `movne r1,r9' diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.s new file mode 100644 index 00000000..5e4c21eb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad-3.s @@ -0,0 +1,6 @@ +.syntax unified +.arch armv6 +.thumb +moveq r1, r8 +movne r1, r9 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.d new file mode 100644 index 00000000..9b160cf6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.d @@ -0,0 +1,3 @@ +#name: Test IT block validation in ARM mode. +#as: -march=armv7a -mimplicit-it=never +#error-output: arm-it-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.l b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.l new file mode 100644 index 00000000..2ba52530 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: incorrect condition in IT block -- `moveq r0,r1' +[^:]*:10: Warning: conditional outside an IT block for Thumb. diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.s new file mode 100644 index 00000000..fe799389 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it-bad.s @@ -0,0 +1,10 @@ + .syntax unified + .text + .global x +x: + mov r0, r1 + cmp r0, #0 + it ne + moveq r0, r1 + bx lr + movgt r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it.d b/binutils-2.25/gas/testsuite/gas/arm/arm-it.d new file mode 100644 index 00000000..1abe0493 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it.d @@ -0,0 +1,9 @@ +#name: ARM IT instruction +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> 03a00000 ? moveq r0, #0 +0+004 <[^>]*> e1a0f00e ? mov pc, lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm-it.s b/binutils-2.25/gas/testsuite/gas/arm/arm-it.s new file mode 100644 index 00000000..f3c56e8c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm-it.s @@ -0,0 +1,8 @@ + # Check that IT is accepted in ARM mode on older architectures + .text + .syntax unified + .arch armv4 +label1: + it eq + moveq r0, #0 + mov pc, lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm.exp b/binutils-2.25/gas/testsuite/gas/arm/arm.exp new file mode 100644 index 00000000..2d6610b6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm.exp @@ -0,0 +1,24 @@ +# Copyright 2012 +# Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +# +# Some ARM tests +# + +if {[istarget arm*-*-*]} { + run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +} diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.d b/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.d new file mode 100644 index 00000000..29449b22 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.d @@ -0,0 +1,3 @@ +# name: ARM 3 errors +# as: -mcpu=arm3 +# error-output: arm3-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.l b/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.l new file mode 100644 index 00000000..d55a9b61 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.l @@ -0,0 +1,3 @@ +.*arm3-bad.s: Assembler messages: +.*arm3-bad.s:4: Error: Rn must not overlap other operands -- `swp r0,r1,\[r0\]' +.*arm3-bad.s:5: Error: Rn must not overlap other operands -- `swp r1,r0,\[r0\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.s b/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.s new file mode 100644 index 00000000..d3415a04 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm3-bad.s @@ -0,0 +1,7 @@ + .text + .align 0 +l: + swp r0, r1, [r0] + swp r1, r0, [r0] + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm3.d b/binutils-2.25/gas/testsuite/gas/arm/arm3.d new file mode 100644 index 00000000..c4a1001b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm3.d @@ -0,0 +1,11 @@ +# name: ARM 3 instructions +# as: -mcpu=arm3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\] +0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\] +0+8 <[^>]*> a1454091 ? swpbge r4, r1, \[r5\] +0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm3.s b/binutils-2.25/gas/testsuite/gas/arm/arm3.s new file mode 100644 index 00000000..b3fd794c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm3.s @@ -0,0 +1,7 @@ + .text + .align 0 +l: + swp r0, r1, [r8] + swpb r3, r3, [r2] + swpgeb r4, r1, [r5] + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm6.d b/binutils-2.25/gas/testsuite/gas/arm/arm6.d new file mode 100644 index 00000000..3fc0de81 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm6.d @@ -0,0 +1,19 @@ +# name: ARM 6 instructions +# as: -mcpu=arm6 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e10f8000 ? mrs r8, CPSR +0+04 <[^>]+> e14f2000 ? mrs r2, SPSR +0+08 <[^>]+> e129f001 ? msr CPSR_fc, r1 +0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000 +0+10 <[^>]+> e168f008 ? msr SPSR_f, r8 +0+14 <[^>]+> e169f009 ? msr SPSR_fc, r9 +0+18 <[^>]+> e10f8000 ? mrs r8, CPSR +0+1c <[^>]+> e14f2000 ? mrs r2, SPSR +0+20 <[^>]+> e129f001 ? msr CPSR_fc, r1 +0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000 +0+28 <[^>]+> e168f008 ? msr SPSR_f, r8 +0+2c <[^>]+> e169f009 ? msr SPSR_fc, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm6.s b/binutils-2.25/gas/testsuite/gas/arm/arm6.s new file mode 100644 index 00000000..1883ebad --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm6.s @@ -0,0 +1,18 @@ + .text + .align 0 +l: + mrs r8, cpsr + mrs r2, spsr + + msr cpsr, r1 + msrne cpsr_flg, #0xf0000000 + msr spsr_flg, r8 + msr spsr_all, r9 + + mrs r8, CPSR + mrs r2, SPSR + + msr CPSR, r1 + msrne CPSR_flg, #0xf0000000 + msr SPSR_flg, r8 + msr SPSR_all, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.d b/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.d new file mode 100644 index 00000000..45f900cc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.d @@ -0,0 +1,3 @@ +# name: ARM mode Thumb errors +# as: +# error-output: arm7-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.l b/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.l new file mode 100644 index 00000000..9892320f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.l @@ -0,0 +1,2 @@ +.*arm7-bad.s: Assembler messages: +.*arm7-bad.s:5: Error: selected processor does not support ARM mode `cbnz r0,.\+6' diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.s b/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.s new file mode 100644 index 00000000..8b37187e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7-bad.s @@ -0,0 +1,7 @@ + .text + .cpu cortex-a8 + .syntax unified + .arm + cbnz r0, .+6 + .thumb + cbnz r0, .+6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7dm.d b/binutils-2.25/gas/testsuite/gas/arm/arm7dm.d new file mode 100644 index 00000000..9411170d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7dm.d @@ -0,0 +1,19 @@ +# name: ARM 7DM instructions +# as: -mcpu=arm7dm +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e0c10392 ? smull r0, r1, r2, r3 +0+04 <[^>]+> e0810392 ? umull r0, r1, r2, r3 +0+08 <[^>]+> e0e10392 ? smlal r0, r1, r2, r3 +0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3 +0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4 +0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp +0+18 <[^>]+> 00b92994 ? umlalseq r2, r9, r4, r9 +0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr +0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 +0+24 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+28 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+2c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7dm.s b/binutils-2.25/gas/testsuite/gas/arm/arm7dm.s new file mode 100644 index 00000000..ee62e8c8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7dm.s @@ -0,0 +1,20 @@ + .text + .align 0 +l: + smull r0, r1, r2, r3 + umull r0, r1, r2, r3 + smlal r0, r1, r2, r3 + umlal r0, r1, r4, r3 + + smullne r0, r1, r3, r4 + smulls r1, r0, r9, r11 + umlaleqs r2, r9, r4, r9 + smlalge r14, r10, r8, r14 + + @ This used to be illegal, but rev 2 of the ARM ARM allows it. + msr CPSR_x, #0 + + @ padding for a.out's sake + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7t.d b/binutils-2.25/gas/testsuite/gas/arm/arm7t.d new file mode 100644 index 00000000..a16192bd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7t.d @@ -0,0 +1,70 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM arm7t +#as: -mcpu=arm7t -EL + +# Test the halfword and signextend memory transfers: + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1\] +0+04 <[^>]*> e1f100b0 ? ldrh r0, \[r1, #0\]! +0+08 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] +0+0c <[^>]*> e1b100b2 ? ldrh r0, \[r1, r2\]! +0+10 <[^>]*> e1d100bc ? ldrh r0, \[r1, #12\] +0+14 <[^>]*> e1f100bc ? ldrh r0, \[r1, #12\]! +0+18 <[^>]*> e15100bc ? ldrh r0, \[r1, #-12\] +0+1c <[^>]*> e09100b2 ? ldrh r0, \[r1\], r2 +0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 +0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] ; 0+e0 <[^>]*> +0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*> +0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\] +0+30 <[^>]*> e1e100b0 ? strh r0, \[r1, #0\]! +0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\] +0+38 <[^>]*> e1a100b2 ? strh r0, \[r1, r2\]! +0+3c <[^>]*> e1c100bc ? strh r0, \[r1, #12\] +0+40 <[^>]*> e1e100bc ? strh r0, \[r1, #12\]! +0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\] +0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2 +0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*> +0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\] +0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1, #0\]! +0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] +0+5c <[^>]*> e1b100d2 ? ldrsb r0, \[r1, r2\]! +0+60 <[^>]*> e1d100dc ? ldrsb r0, \[r1, #12\] +0+64 <[^>]*> e1f100dc ? ldrsb r0, \[r1, #12\]! +0+68 <[^>]*> e15100dc ? ldrsb r0, \[r1, #-12\] +0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2 +0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde +0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*> +0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\] +0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1, #0\]! +0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] +0+84 <[^>]*> e1b100f2 ? ldrsh r0, \[r1, r2\]! +0+88 <[^>]*> e1d100fc ? ldrsh r0, \[r1, #12\] +0+8c <[^>]*> e1f100fc ? ldrsh r0, \[r1, #12\]! +0+90 <[^>]*> e15100fc ? ldrsh r0, \[r1, #-12\] +0+94 <[^>]*> e09100f2 ? ldrsh r0, \[r1\], r2 +0+98 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 +0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] ; 0+e0 <[^>]*> +0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*> +0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] +0+a8 <[^>]*> 119100b2 ? ldrhne r0, \[r1, r2\] +0+ac <[^>]*> 819100b2 ? ldrhhi r0, \[r1, r2\] +0+b0 <[^>]*> b19100b2 ? ldrhlt r0, \[r1, r2\] +0+b4 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] +0+b8 <[^>]*> 119100f2 ? ldrshne r0, \[r1, r2\] +0+bc <[^>]*> 819100f2 ? ldrshhi r0, \[r1, r2\] +0+c0 <[^>]*> b19100f2 ? ldrshlt r0, \[r1, r2\] +0+c4 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] +0+c8 <[^>]*> 119100d2 ? ldrsbne r0, \[r1, r2\] +0+cc <[^>]*> 819100d2 ? ldrsbhi r0, \[r1, r2\] +0+d0 <[^>]*> b19100d2 ? ldrsblt r0, \[r1, r2\] +0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e0 <[^>]*> +0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e4 <[^>]*> +0+dc <[^>]*> 00000000 ? .* +[ ]*dc:.*fred +0+e0 <[^>]*> 0000c0de ? .* +0+e4 <[^>]*> 0000dead ? .* +0+e8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+ec <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/arm7t.s b/binutils-2.25/gas/testsuite/gas/arm/arm7t.s new file mode 100644 index 00000000..580c3f11 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/arm7t.s @@ -0,0 +1,81 @@ + .text + .align 0 + +loadhalfwords: + ldrh r0, [r1] + ldrh r0, [r1]! + ldrh r0, [r1, r2] + ldrh r0, [r1, r2]! + ldrh r0, [r1,#0x0C] + ldrh r0, [r1,#0x0C]! + ldrh r0, [r1,#-0x0C] + ldrh r0, [r1], r2 + ldrh r0, =0xFF00 + ldrh r0, =0xC0DE + ldrh r0, .L2 + +storehalfwords: + strh r0, [r1] + strh r0, [r1]! + strh r0, [r1, r2] + strh r0, [r1, r2]! + strh r0, [r1,#0x0C] + strh r0, [r1,#0x0C]! + strh r0, [r1,#-0x0C] + strh r0, [r1], r2 + strh r0, .L2 + +loadsignedbytes: + ldrsb r0, [r1] + ldrsb r0, [r1]! + ldrsb r0, [r1, r2] + ldrsb r0, [r1, r2]! + ldrsb r0, [r1,#0x0C] + ldrsb r0, [r1,#0x0C]! + ldrsb r0, [r1,#-0x0C] + ldrsb r0, [r1], r2 + ldrsb r0, =0xDE + ldrsb r0, .L2 + +loadsignedhalfwords: + ldrsh r0, [r1] + ldrsh r0, [r1]! + ldrsh r0, [r1, r2] + ldrsh r0, [r1, r2]! + ldrsh r0, [r1, #0x0C] + ldrsh r0, [r1, #0x0C]! + ldrsh r0, [r1, #-0x0C] + ldrsh r0, [r1], r2 + ldrsh r0, =0xFF00 + ldrsh r0, =0xC0DE + ldrsh r0, .L2 + +misc: + ldralh r0, [r1, r2] + ldrneh r0, [r1, r2] + ldrhih r0, [r1, r2] + ldrlth r0, [r1, r2] + + ldralsh r0, [r1, r2] + ldrnesh r0, [r1, r2] + ldrhish r0, [r1, r2] + ldrltsh r0, [r1, r2] + + ldralsb r0, [r1, r2] + ldrnesb r0, [r1, r2] + ldrhisb r0, [r1, r2] + ldrltsb r0, [r1, r2] + + ldrsh r0, =0xC0DE + ldrsh r0, =0xDEAD + + .align +.L2: + .word fred + + .ltorg + + # Add two nop instructions to ensure that the + # output is 32-byte aligned as required for arm-aout. + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.d b/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.d new file mode 100644 index 00000000..f6f1454b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.d @@ -0,0 +1,3 @@ +#name: ARM v1 errors +#as: -mcpu=arm7m +#error-output: armv1-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.l b/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.l new file mode 100644 index 00000000..22090d58 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.l @@ -0,0 +1,9 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: invalid pseudo operation -- `str r0,=0x00ff0000' +[^:]*:5: Error: bad expression -- `ldr r0,{r1}' +[^:]*:6: Error: bad instruction `cmpl r0,r0' +[^:]*:7: Error: selected processor does not support ARM mode `strh r0,\[r1\]' +[^:]*:8: Warning: writeback of base register is UNPREDICTABLE +[^:]*:9: Warning: writeback of base register when in register list is UNPREDICTABLE +[^:]*:10: Warning: writeback of base register is UNPREDICTABLE +[^:]*:12: Warning: if writeback register is in list, it must be the lowest reg in the list diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.s b/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.s new file mode 100644 index 00000000..7e5f6839 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv1-bad.s @@ -0,0 +1,12 @@ + .global entry + .text +entry: + str r0, =0x00ff0000 + ldr r0, {r1} + cmpl r0, r0 + strh r0, [r1] + ldmfa r4!, {r8, r9}^ + ldmfa r4!, {r4, r8, r9} + stmfa r4!, {r8, r9}^ + stmdb r4!, {r4, r8, r9} @ This is OK. + stmdb r8!, {r4, r8, r9} diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv1.d b/binutils-2.25/gas/testsuite/gas/arm/armv1.d new file mode 100644 index 00000000..7899df75 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv1.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM v1 instructions +#as: -mcpu=arm7t +#error-output: armv1.l + +# Test the ARM v1 instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> e0000000 ? and r0, r0, r0 +0+04 <[^>]*> e0100000 ? ands r0, r0, r0 +0+08 <[^>]*> e0200000 ? eor r0, r0, r0 +0+0c <[^>]*> e0300000 ? eors r0, r0, r0 +0+10 <[^>]*> e0400000 ? sub r0, r0, r0 +0+14 <[^>]*> e0500000 ? subs r0, r0, r0 +0+18 <[^>]*> e0600000 ? rsb r0, r0, r0 +0+1c <[^>]*> e0700000 ? rsbs r0, r0, r0 +0+20 <[^>]*> e0800000 ? add r0, r0, r0 +0+24 <[^>]*> e0900000 ? adds r0, r0, r0 +0+28 <[^>]*> e0a00000 ? adc r0, r0, r0 +0+2c <[^>]*> e0b00000 ? adcs r0, r0, r0 +0+30 <[^>]*> e0c00000 ? sbc r0, r0, r0 +0+34 <[^>]*> e0d00000 ? sbcs r0, r0, r0 +0+38 <[^>]*> e0e00000 ? rsc r0, r0, r0 +0+3c <[^>]*> e0f00000 ? rscs r0, r0, r0 +0+40 <[^>]*> e1800000 ? orr r0, r0, r0 +0+44 <[^>]*> e1900000 ? orrs r0, r0, r0 +0+48 <[^>]*> e1c00000 ? bic r0, r0, r0 +0+4c <[^>]*> e1d00000 ? bics r0, r0, r0 +0+50 <[^>]*> e1100000 ? tst r0, r0 +0+54 <[^>]*> e1100000 ? tst r0, r0 +0+58 <[^>]*> e110f000 ? tst r0, r0 +0+5c <[^>]*> e1300000 ? teq r0, r0 +0+60 <[^>]*> e1300000 ? teq r0, r0 +0+64 <[^>]*> e130f000 ? teq r0, r0 +0+68 <[^>]*> e1500000 ? cmp r0, r0 +0+6c <[^>]*> e1500000 ? cmp r0, r0 +0+70 <[^>]*> e150f000 ? cmp r0, r0 +0+74 <[^>]*> e1700000 ? cmn r0, r0 +0+78 <[^>]*> e1700000 ? cmn r0, r0 +0+7c <[^>]*> e170f000 ? cmn r0, r0 +0+80 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+84 <[^>]*> e1b00000 ? movs r0, r0 +0+88 <[^>]*> e1e00000 ? mvn r0, r0 +0+8c <[^>]*> e1f00000 ? mvns r0, r0 +0+90 <[^>]*> ef000000 ? (swi|svc) 0x00000000 +0+94 <[^>]*> e5900000 ? ldr r0, \[r0\] +0+98 <[^>]*> e5d00000 ? ldrb r0, \[r0\] +0+9c <[^>]*> e4b10000 ? ldrt r0, \[r1\] +0+a0 <[^>]*> e4f10000 ? ldrbt r0, \[r1\] +0+a4 <[^>]*> e5800000 ? str r0, \[r0\] +0+a8 <[^>]*> e5c00000 ? strb r0, \[r0\] +0+ac <[^>]*> e4a10000 ? strt r0, \[r1\] +0+b0 <[^>]*> e4e10000 ? strbt r0, \[r1\] +0+b4 <[^>]*> e8800001 ? stm r0, {r0} +0+b8 <[^>]*> e9800001 ? stmib r0, {r0} +0+bc <[^>]*> e8000001 ? stmda r0, {r0} +0+c0 <[^>]*> e9000001 ? stmdb r0, {r0} +0+c4 <[^>]*> e9000001 ? stmdb r0, {r0} +0+c8 <[^>]*> e9800001 ? stmib r0, {r0} +0+cc <[^>]*> e8800001 ? stm r0, {r0} +0+d0 <[^>]*> e8000001 ? stmda r0, {r0} +0+d4 <[^>]*> e8900001 ? ldm r0, {r0} +0+d8 <[^>]*> e9900001 ? ldmib r0, {r0} +0+dc <[^>]*> e8100001 ? ldmda r0, {r0} +0+e0 <[^>]*> e9100001 ? ldmdb r0, {r0} +0+e4 <[^>]*> e8900001 ? ldm r0, {r0} +0+e8 <[^>]*> e8100001 ? ldmda r0, {r0} +0+ec <[^>]*> e9100001 ? ldmdb r0, {r0} +0+f0 <[^>]*> e9900001 ? ldmib r0, {r0} +0+f4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+f8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) +0+fc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv1.l b/binutils-2.25/gas/testsuite/gas/arm/armv1.l new file mode 100644 index 00000000..369f9d4a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv1.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:26: Warning: s suffix on comparison instruction is deprecated +[^:]*:29: Warning: s suffix on comparison instruction is deprecated +[^:]*:32: Warning: s suffix on comparison instruction is deprecated +[^:]*:35: Warning: s suffix on comparison instruction is deprecated diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv1.s b/binutils-2.25/gas/testsuite/gas/arm/armv1.s new file mode 100644 index 00000000..bd83639d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv1.s @@ -0,0 +1,76 @@ + .global entry + .text +entry: + and r0, r0, r0 + ands r0, r0, r0 + eor r0, r0, r0 + eors r0, r0, r0 + sub r0, r0, r0 + subs r0, r0, r0 + rsb r0, r0, r0 + rsbs r0, r0, r0 + add r0, r0, r0 + adds r0, r0, r0 + adc r0, r0, r0 + adcs r0, r0, r0 + sbc r0, r0, r0 + sbcs r0, r0, r0 + rsc r0, r0, r0 + rscs r0, r0, r0 + orr r0, r0, r0 + orrs r0, r0, r0 + bic r0, r0, r0 + bics r0, r0, r0 + + tst r0, r0 + tsts r0, r0 + tstp r0, r0 + teq r0, r0 + teqs r0, r0 + teqp r0, r0 + cmp r0, r0 + cmps r0, r0 + cmpp r0, r0 + cmn r0, r0 + cmns r0, r0 + cmnp r0, r0 + + mov r0, r0 + movs r0, r0 + mvn r0, r0 + mvns r0, r0 + + swi #0 + + ldr r0, [r0, #-0] + ldrb r0, [r0, #-0] + ldrt r0, [r1] + ldrbt r0, [r1] + str r0, [r0, #-0] + strb r0, [r0, #-0] + strt r0, [r1] + strbt r0, [r1] + + stmia r0, {r0} + stmib r0, {r0} + stmda r0, {r0} + stmdb r0, {r0} + stmfd r0, {r0} + stmfa r0, {r0} + stmea r0, {r0} + stmed r0, {r0} + + ldmia r0, {r0} + ldmib r0, {r0} + ldmda r0, {r0} + ldmdb r0, {r0} + ldmfd r0, {r0} + ldmfa r0, {r0} + ldmea r0, {r0} + ldmed r0, {r0} + + # Add three nop instructions to ensure that the + # output is 32-byte aligned as required for arm-aout. + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv2-mp-bad.d b/binutils-2.25/gas/testsuite/gas/arm/armv2-mp-bad.d new file mode 100644 index 00000000..c43ba962 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv2-mp-bad.d @@ -0,0 +1,4 @@ +#name: ARM MP Extension errors +#source: blank.s +#as: -march=armv2+mp +#error-output: armv2-mp-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv2-mp-bad.l b/binutils-2.25/gas/testsuite/gas/arm/armv2-mp-bad.l new file mode 100644 index 00000000..eb971350 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv2-mp-bad.l @@ -0,0 +1,3 @@ +Assembler messages: +[^:]*: extension does not apply to the base architecture +[^:]*: unrecognized option -march=armv2\+mp diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv7-a+idiv.d b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+idiv.d new file mode 100644 index 00000000..ba8a2a1f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+idiv.d @@ -0,0 +1,10 @@ +#name: Valid v7-A+IDIV +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e730f211 udiv r0, r1, r2 +0[0-9a-f]+ <[^>]+> e710f211 sdiv r0, r1, r2 +0[0-9a-f]+ <[^>]+> fbb1 f0f2 udiv r0, r1, r2 +0[0-9a-f]+ <[^>]+> fb91 f0f2 sdiv r0, r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv7-a+idiv.s b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+idiv.s new file mode 100644 index 00000000..eaefde88 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+idiv.s @@ -0,0 +1,14 @@ + .syntax unified + .text + .arch armv7-a + .arch_extension idiv + +foo: + udiv r0, r1, r2 + sdiv r0, r1, r2 + + .thumb + .thumb_func +bar: + udiv r0, r1, r2 + sdiv r0, r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv7-a+virt.d b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+virt.d new file mode 100644 index 00000000..1e3224ce --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+virt.d @@ -0,0 +1,145 @@ +# name: ARMv7-a+virt Instructions +# as: -march=armv7-a+virt +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e1400070 hvc 0 +0[0-9a-f]+ <[^>]+> e14fff7f hvc 65535 ; 0xffff +0[0-9a-f]+ <[^>]+> e160006e eret +0[0-9a-f]+ <[^>]+> e1001200 mrs r1, R8_usr +0[0-9a-f]+ <[^>]+> e1011200 mrs r1, R9_usr +0[0-9a-f]+ <[^>]+> e1021200 mrs r1, R10_usr +0[0-9a-f]+ <[^>]+> e1031200 mrs r1, R11_usr +0[0-9a-f]+ <[^>]+> e1041200 mrs r1, R12_usr +0[0-9a-f]+ <[^>]+> e1051200 mrs r1, SP_usr +0[0-9a-f]+ <[^>]+> e1061200 mrs r1, LR_usr +0[0-9a-f]+ <[^>]+> e1081200 mrs r1, R8_fiq +0[0-9a-f]+ <[^>]+> e1091200 mrs r1, R9_fiq +0[0-9a-f]+ <[^>]+> e10a1200 mrs r1, R10_fiq +0[0-9a-f]+ <[^>]+> e10b1200 mrs r1, R11_fiq +0[0-9a-f]+ <[^>]+> e10c1200 mrs r1, R12_fiq +0[0-9a-f]+ <[^>]+> e10d1200 mrs r1, SP_fiq +0[0-9a-f]+ <[^>]+> e10e1200 mrs r1, LR_fiq +0[0-9a-f]+ <[^>]+> e14e1200 mrs r1, SPSR_fiq +0[0-9a-f]+ <[^>]+> e1011300 mrs r1, SP_irq +0[0-9a-f]+ <[^>]+> e1001300 mrs r1, LR_irq +0[0-9a-f]+ <[^>]+> e1401300 mrs r1, SPSR_irq +0[0-9a-f]+ <[^>]+> e1031300 mrs r1, SP_svc +0[0-9a-f]+ <[^>]+> e1021300 mrs r1, LR_svc +0[0-9a-f]+ <[^>]+> e1421300 mrs r1, SPSR_svc +0[0-9a-f]+ <[^>]+> e1051300 mrs r1, SP_abt +0[0-9a-f]+ <[^>]+> e1041300 mrs r1, LR_abt +0[0-9a-f]+ <[^>]+> e1441300 mrs r1, SPSR_abt +0[0-9a-f]+ <[^>]+> e1071300 mrs r1, SP_und +0[0-9a-f]+ <[^>]+> e1061300 mrs r1, LR_und +0[0-9a-f]+ <[^>]+> e1461300 mrs r1, SPSR_und +0[0-9a-f]+ <[^>]+> e10d1300 mrs r1, SP_mon +0[0-9a-f]+ <[^>]+> e10c1300 mrs r1, LR_mon +0[0-9a-f]+ <[^>]+> e14c1300 mrs r1, SPSR_mon +0[0-9a-f]+ <[^>]+> e10f1300 mrs r1, SP_hyp +0[0-9a-f]+ <[^>]+> e10e1300 mrs r1, ELR_hyp +0[0-9a-f]+ <[^>]+> e14e1300 mrs r1, SPSR_hyp +0[0-9a-f]+ <[^>]+> e120f201 msr R8_usr, r1 +0[0-9a-f]+ <[^>]+> e121f201 msr R9_usr, r1 +0[0-9a-f]+ <[^>]+> e122f201 msr R10_usr, r1 +0[0-9a-f]+ <[^>]+> e123f201 msr R11_usr, r1 +0[0-9a-f]+ <[^>]+> e124f201 msr R12_usr, r1 +0[0-9a-f]+ <[^>]+> e125f201 msr SP_usr, r1 +0[0-9a-f]+ <[^>]+> e126f201 msr LR_usr, r1 +0[0-9a-f]+ <[^>]+> e128f201 msr R8_fiq, r1 +0[0-9a-f]+ <[^>]+> e129f201 msr R9_fiq, r1 +0[0-9a-f]+ <[^>]+> e12af201 msr R10_fiq, r1 +0[0-9a-f]+ <[^>]+> e12bf201 msr R11_fiq, r1 +0[0-9a-f]+ <[^>]+> e12cf201 msr R12_fiq, r1 +0[0-9a-f]+ <[^>]+> e12df201 msr SP_fiq, r1 +0[0-9a-f]+ <[^>]+> e12ef201 msr LR_fiq, r1 +0[0-9a-f]+ <[^>]+> e16ef201 msr SPSR_fiq, r1 +0[0-9a-f]+ <[^>]+> e121f301 msr SP_irq, r1 +0[0-9a-f]+ <[^>]+> e120f301 msr LR_irq, r1 +0[0-9a-f]+ <[^>]+> e160f301 msr SPSR_irq, r1 +0[0-9a-f]+ <[^>]+> e123f301 msr SP_svc, r1 +0[0-9a-f]+ <[^>]+> e122f301 msr LR_svc, r1 +0[0-9a-f]+ <[^>]+> e162f301 msr SPSR_svc, r1 +0[0-9a-f]+ <[^>]+> e125f301 msr SP_abt, r1 +0[0-9a-f]+ <[^>]+> e124f301 msr LR_abt, r1 +0[0-9a-f]+ <[^>]+> e164f301 msr SPSR_abt, r1 +0[0-9a-f]+ <[^>]+> e127f301 msr SP_und, r1 +0[0-9a-f]+ <[^>]+> e126f301 msr LR_und, r1 +0[0-9a-f]+ <[^>]+> e166f301 msr SPSR_und, r1 +0[0-9a-f]+ <[^>]+> e12df301 msr SP_mon, r1 +0[0-9a-f]+ <[^>]+> e12cf301 msr LR_mon, r1 +0[0-9a-f]+ <[^>]+> e16cf301 msr SPSR_mon, r1 +0[0-9a-f]+ <[^>]+> e12ff301 msr SP_hyp, r1 +0[0-9a-f]+ <[^>]+> e12ef301 msr ELR_hyp, r1 +0[0-9a-f]+ <[^>]+> e16ef301 msr SPSR_hyp, r1 +0[0-9a-f]+ <[^>]+> f7e0 8000 hvc #0 +0[0-9a-f]+ <[^>]+> f7ef 8fff hvc #65535 ; 0xffff +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3e0 8120 mrs r1, R8_usr +0[0-9a-f]+ <[^>]+> f3e1 8120 mrs r1, R9_usr +0[0-9a-f]+ <[^>]+> f3e2 8120 mrs r1, R10_usr +0[0-9a-f]+ <[^>]+> f3e3 8120 mrs r1, R11_usr +0[0-9a-f]+ <[^>]+> f3e4 8120 mrs r1, R12_usr +0[0-9a-f]+ <[^>]+> f3e5 8120 mrs r1, SP_usr +0[0-9a-f]+ <[^>]+> f3e6 8120 mrs r1, LR_usr +0[0-9a-f]+ <[^>]+> f3e8 8120 mrs r1, R8_fiq +0[0-9a-f]+ <[^>]+> f3e9 8120 mrs r1, R9_fiq +0[0-9a-f]+ <[^>]+> f3ea 8120 mrs r1, R10_fiq +0[0-9a-f]+ <[^>]+> f3eb 8120 mrs r1, R11_fiq +0[0-9a-f]+ <[^>]+> f3ec 8120 mrs r1, R12_fiq +0[0-9a-f]+ <[^>]+> f3ed 8120 mrs r1, SP_fiq +0[0-9a-f]+ <[^>]+> f3ee 8120 mrs r1, LR_fiq +0[0-9a-f]+ <[^>]+> f3fe 8120 mrs r1, SPSR_fiq +0[0-9a-f]+ <[^>]+> f3e1 8130 mrs r1, SP_irq +0[0-9a-f]+ <[^>]+> f3e0 8130 mrs r1, LR_irq +0[0-9a-f]+ <[^>]+> f3f0 8130 mrs r1, SPSR_irq +0[0-9a-f]+ <[^>]+> f3e3 8130 mrs r1, SP_svc +0[0-9a-f]+ <[^>]+> f3e2 8130 mrs r1, LR_svc +0[0-9a-f]+ <[^>]+> f3f2 8130 mrs r1, SPSR_svc +0[0-9a-f]+ <[^>]+> f3e5 8130 mrs r1, SP_abt +0[0-9a-f]+ <[^>]+> f3e4 8130 mrs r1, LR_abt +0[0-9a-f]+ <[^>]+> f3f4 8130 mrs r1, SPSR_abt +0[0-9a-f]+ <[^>]+> f3e7 8130 mrs r1, SP_und +0[0-9a-f]+ <[^>]+> f3e6 8130 mrs r1, LR_und +0[0-9a-f]+ <[^>]+> f3f6 8130 mrs r1, SPSR_und +0[0-9a-f]+ <[^>]+> f3ed 8130 mrs r1, SP_mon +0[0-9a-f]+ <[^>]+> f3ec 8130 mrs r1, LR_mon +0[0-9a-f]+ <[^>]+> f3fc 8130 mrs r1, SPSR_mon +0[0-9a-f]+ <[^>]+> f3ef 8130 mrs r1, SP_hyp +0[0-9a-f]+ <[^>]+> f3ee 8130 mrs r1, ELR_hyp +0[0-9a-f]+ <[^>]+> f3fe 8130 mrs r1, SPSR_hyp +0[0-9a-f]+ <[^>]+> f381 8020 msr R8_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8120 msr R9_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8220 msr R10_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8320 msr R11_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8420 msr R12_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8520 msr SP_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8620 msr LR_usr, r1 +0[0-9a-f]+ <[^>]+> f381 8820 msr R8_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8920 msr R9_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8a20 msr R10_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8b20 msr R11_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8c20 msr R12_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8d20 msr SP_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8e20 msr LR_fiq, r1 +0[0-9a-f]+ <[^>]+> f391 8e20 msr SPSR_fiq, r1 +0[0-9a-f]+ <[^>]+> f381 8130 msr SP_irq, r1 +0[0-9a-f]+ <[^>]+> f381 8030 msr LR_irq, r1 +0[0-9a-f]+ <[^>]+> f391 8030 msr SPSR_irq, r1 +0[0-9a-f]+ <[^>]+> f381 8330 msr SP_svc, r1 +0[0-9a-f]+ <[^>]+> f381 8230 msr LR_svc, r1 +0[0-9a-f]+ <[^>]+> f391 8230 msr SPSR_svc, r1 +0[0-9a-f]+ <[^>]+> f381 8530 msr SP_abt, r1 +0[0-9a-f]+ <[^>]+> f381 8430 msr LR_abt, r1 +0[0-9a-f]+ <[^>]+> f391 8430 msr SPSR_abt, r1 +0[0-9a-f]+ <[^>]+> f381 8730 msr SP_und, r1 +0[0-9a-f]+ <[^>]+> f381 8630 msr LR_und, r1 +0[0-9a-f]+ <[^>]+> f391 8630 msr SPSR_und, r1 +0[0-9a-f]+ <[^>]+> f381 8d30 msr SP_mon, r1 +0[0-9a-f]+ <[^>]+> f381 8c30 msr LR_mon, r1 +0[0-9a-f]+ <[^>]+> f391 8c30 msr SPSR_mon, r1 +0[0-9a-f]+ <[^>]+> f381 8f30 msr SP_hyp, r1 +0[0-9a-f]+ <[^>]+> f381 8e30 msr ELR_hyp, r1 +0[0-9a-f]+ <[^>]+> f391 8e30 msr SPSR_hyp, r1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv7-a+virt.s b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+virt.s new file mode 100644 index 00000000..354b8bc0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv7-a+virt.s @@ -0,0 +1,146 @@ + .text + .syntax unified + .arm +foo: + hvc 0x0000 + hvc 0xffff + eret + mrs r1, R8_usr + mrs r1, R9_usr + mrs r1, R10_usr + mrs r1, R11_usr + mrs r1, R12_usr + mrs r1, SP_usr + mrs r1, LR_usr + mrs r1, R8_fiq + mrs r1, R9_fiq + mrs r1, R10_fiq + mrs r1, R11_fiq + mrs r1, R12_fiq + mrs r1, SP_fiq + mrs r1, LR_fiq + mrs r1, SPSR_fiq + mrs r1, SP_irq + mrs r1, LR_irq + mrs r1, SPSR_irq + mrs r1, SP_svc + mrs r1, LR_svc + mrs r1, SPSR_svc + mrs r1, SP_abt + mrs r1, LR_abt + mrs r1, SPSR_abt + mrs r1, SP_und + mrs r1, LR_und + mrs r1, SPSR_und + mrs r1, SP_mon + mrs r1, LR_mon + mrs r1, SPSR_mon + mrs r1, SP_hyp + mrs r1, ELR_hyp + mrs r1, SPSR_hyp + msr R8_usr, r1 + msr R9_usr, r1 + msr R10_usr, r1 + msr R11_usr, r1 + msr R12_usr, r1 + msr SP_usr, r1 + msr LR_usr, r1 + msr R8_fiq, r1 + msr R9_fiq, r1 + msr R10_fiq, r1 + msr R11_fiq, r1 + msr R12_fiq, r1 + msr SP_fiq, r1 + msr LR_fiq, r1 + msr SPSR_fiq, r1 + msr SP_irq, r1 + msr LR_irq, r1 + msr SPSR_irq, r1 + msr SP_svc, r1 + msr LR_svc, r1 + msr SPSR_svc, r1 + msr SP_abt, r1 + msr LR_abt, r1 + msr SPSR_abt, r1 + msr SP_und, r1 + msr LR_und, r1 + msr SPSR_und, r1 + msr SP_mon, r1 + msr LR_mon, r1 + msr SPSR_mon, r1 + msr SP_hyp, r1 + msr ELR_hyp, r1 + msr SPSR_hyp, r1 + + .thumb +bar: + hvc 0x0000 + hvc 0xffff + eret + mrs r1, R8_usr + mrs r1, R9_usr + mrs r1, R10_usr + mrs r1, R11_usr + mrs r1, R12_usr + mrs r1, SP_usr + mrs r1, LR_usr + mrs r1, R8_fiq + mrs r1, R9_fiq + mrs r1, R10_fiq + mrs r1, R11_fiq + mrs r1, R12_fiq + mrs r1, SP_fiq + mrs r1, LR_fiq + mrs r1, SPSR_fiq + mrs r1, SP_irq + mrs r1, LR_irq + mrs r1, SPSR_irq + mrs r1, SP_svc + mrs r1, LR_svc + mrs r1, SPSR_svc + mrs r1, SP_abt + mrs r1, LR_abt + mrs r1, SPSR_abt + mrs r1, SP_und + mrs r1, LR_und + mrs r1, SPSR_und + mrs r1, SP_mon + mrs r1, LR_mon + mrs r1, SPSR_mon + mrs r1, SP_hyp + mrs r1, ELR_hyp + mrs r1, SPSR_hyp + msr R8_usr, r1 + msr R9_usr, r1 + msr R10_usr, r1 + msr R11_usr, r1 + msr R12_usr, r1 + msr SP_usr, r1 + msr LR_usr, r1 + msr R8_fiq, r1 + msr R9_fiq, r1 + msr R10_fiq, r1 + msr R11_fiq, r1 + msr R12_fiq, r1 + msr SP_fiq, r1 + msr LR_fiq, r1 + msr SPSR_fiq, r1 + msr SP_irq, r1 + msr LR_irq, r1 + msr SPSR_irq, r1 + msr SP_svc, r1 + msr LR_svc, r1 + msr SPSR_svc, r1 + msr SP_abt, r1 + msr LR_abt, r1 + msr SPSR_abt, r1 + msr SP_und, r1 + msr LR_und, r1 + msr SPSR_und, r1 + msr SP_mon, r1 + msr LR_mon, r1 + msr SPSR_mon, r1 + msr SP_hyp, r1 + msr ELR_hyp, r1 + msr SPSR_hyp, r1 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a+crypto.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+crypto.d new file mode 100644 index 00000000..d5b2b4b3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+crypto.d @@ -0,0 +1,122 @@ +#name: Valid v8-a+cryptov1 +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2a00e00 vmull.p64 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2efeeaf vmull.p64 q15, d31, d31 +0[0-9a-f]+ <[^>]+> f3b00300 aese.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e30e aese.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f00320 aese.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e32e aese.8 q15, q15 +0[0-9a-f]+ <[^>]+> f3b00340 aesd.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e34e aesd.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f00360 aesd.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e36e aesd.8 q15, q15 +0[0-9a-f]+ <[^>]+> f3b00380 aesmc.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e38e aesmc.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f003a0 aesmc.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e3ae aesmc.8 q15, q15 +0[0-9a-f]+ <[^>]+> f3b003c0 aesimc.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b0e3ce aesimc.8 q7, q7 +0[0-9a-f]+ <[^>]+> f3f003e0 aesimc.8 q8, q8 +0[0-9a-f]+ <[^>]+> f3f0e3ee aesimc.8 q15, q15 +0[0-9a-f]+ <[^>]+> f2000c40 sha1c.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f20eec4e sha1c.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2400ce0 sha1c.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f24eecee sha1c.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f2100c40 sha1p.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f21eec4e sha1p.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2500ce0 sha1p.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f25eecee sha1p.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f2200c40 sha1m.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f22eec4e sha1m.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2600ce0 sha1m.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f26eecee sha1m.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f2300c40 sha1su0.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f23eec4e sha1su0.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f2700ce0 sha1su0.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f27eecee sha1su0.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3000c40 sha256h.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f30eec4e sha256h.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f3400ce0 sha256h.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f34eecee sha256h.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3100c40 sha256h2.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f31eec4e sha256h2.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f3500ce0 sha256h2.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f35eecee sha256h2.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3200c40 sha256su1.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f32eec4e sha256su1.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f3600ce0 sha256su1.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f36eecee sha256su1.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3b902c0 sha1h.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b9e2ce sha1h.32 q7, q7 +0[0-9a-f]+ <[^>]+> f3f902e0 sha1h.32 q8, q8 +0[0-9a-f]+ <[^>]+> f3f9e2ee sha1h.32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba0380 sha1su1.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bae38e sha1su1.32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fa03a0 sha1su1.32 q8, q8 +0[0-9a-f]+ <[^>]+> f3fae3ae sha1su1.32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba03c0 sha256su0.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bae3ce sha256su0.32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fa03e0 sha256su0.32 q8, q8 +0[0-9a-f]+ <[^>]+> f3fae3ee sha256su0.32 q15, q15 +0[0-9a-f]+ <[^>]+> efa0 0e00 vmull.p64 q0, d0, d0 +0[0-9a-f]+ <[^>]+> efef eeaf vmull.p64 q15, d31, d31 +0[0-9a-f]+ <[^>]+> ffb0 0300 aese.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e30e aese.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 0320 aese.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e32e aese.8 q15, q15 +0[0-9a-f]+ <[^>]+> ffb0 0340 aesd.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e34e aesd.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 0360 aesd.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e36e aesd.8 q15, q15 +0[0-9a-f]+ <[^>]+> ffb0 0380 aesmc.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e38e aesmc.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 03a0 aesmc.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e3ae aesmc.8 q15, q15 +0[0-9a-f]+ <[^>]+> ffb0 03c0 aesimc.8 q0, q0 +0[0-9a-f]+ <[^>]+> ffb0 e3ce aesimc.8 q7, q7 +0[0-9a-f]+ <[^>]+> fff0 03e0 aesimc.8 q8, q8 +0[0-9a-f]+ <[^>]+> fff0 e3ee aesimc.8 q15, q15 +0[0-9a-f]+ <[^>]+> ef00 0c40 sha1c.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef0e ec4e sha1c.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef40 0ce0 sha1c.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef4e ecee sha1c.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ef10 0c40 sha1p.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef1e ec4e sha1p.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef50 0ce0 sha1p.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef5e ecee sha1p.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ef20 0c40 sha1m.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef2e ec4e sha1m.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef60 0ce0 sha1m.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef6e ecee sha1m.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ef30 0c40 sha1su0.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ef3e ec4e sha1su0.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ef70 0ce0 sha1su0.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ef7e ecee sha1su0.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff00 0c40 sha256h.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff0e ec4e sha256h.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff40 0ce0 sha256h.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff4e ecee sha256h.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff10 0c40 sha256h2.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff1e ec4e sha256h2.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff50 0ce0 sha256h2.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff5e ecee sha256h2.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff20 0c40 sha256su1.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff2e ec4e sha256su1.32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff60 0ce0 sha256su1.32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff6e ecee sha256su1.32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ffb9 02c0 sha1h.32 q0, q0 +0[0-9a-f]+ <[^>]+> ffb9 e2ce sha1h.32 q7, q7 +0[0-9a-f]+ <[^>]+> fff9 02e0 sha1h.32 q8, q8 +0[0-9a-f]+ <[^>]+> fff9 e2ee sha1h.32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 0380 sha1su1.32 q0, q0 +0[0-9a-f]+ <[^>]+> ffba e38e sha1su1.32 q7, q7 +0[0-9a-f]+ <[^>]+> fffa 03a0 sha1su1.32 q8, q8 +0[0-9a-f]+ <[^>]+> fffa e3ae sha1su1.32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 03c0 sha256su0.32 q0, q0 +0[0-9a-f]+ <[^>]+> ffba e3ce sha256su0.32 q7, q7 +0[0-9a-f]+ <[^>]+> fffa 03e0 sha256su0.32 q8, q8 +0[0-9a-f]+ <[^>]+> fffa e3ee sha256su0.32 q15, q15 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a+crypto.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+crypto.s new file mode 100644 index 00000000..679f6045 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+crypto.s @@ -0,0 +1,123 @@ + .syntax unified + .arch armv8-a + .arch_extension crypto + + .arm + vmull.p64 q0, d0, d0 + vmull.p64 q15, d31, d31 + aese.8 q0, q0 + aese.8 q7, q7 + aese.8 q8, q8 + aese.8 q15, q15 + aesd.8 q0, q0 + aesd.8 q7, q7 + aesd.8 q8, q8 + aesd.8 q15, q15 + aesmc.8 q0, q0 + aesmc.8 q7, q7 + aesmc.8 q8, q8 + aesmc.8 q15, q15 + aesimc.8 q0, q0 + aesimc.8 q7, q7 + aesimc.8 q8, q8 + aesimc.8 q15, q15 + sha1c.32 q0, q0, q0 + sha1c.32 q7, q7, q7 + sha1c.32 q8, q8, q8 + sha1c.32 q15, q15, q15 + sha1p.32 q0, q0, q0 + sha1p.32 q7, q7, q7 + sha1p.32 q8, q8, q8 + sha1p.32 q15, q15, q15 + sha1m.32 q0, q0, q0 + sha1m.32 q7, q7, q7 + sha1m.32 q8, q8, q8 + sha1m.32 q15, q15, q15 + sha1su0.32 q0, q0, q0 + sha1su0.32 q7, q7, q7 + sha1su0.32 q8, q8, q8 + sha1su0.32 q15, q15, q15 + sha256h.32 q0, q0, q0 + sha256h.32 q7, q7, q7 + sha256h.32 q8, q8, q8 + sha256h.32 q15, q15, q15 + sha256h2.32 q0, q0, q0 + sha256h2.32 q7, q7, q7 + sha256h2.32 q8, q8, q8 + sha256h2.32 q15, q15, q15 + sha256su1.32 q0, q0, q0 + sha256su1.32 q7, q7, q7 + sha256su1.32 q8, q8, q8 + sha256su1.32 q15, q15, q15 + sha1h.32 q0, q0 + sha1h.32 q7, q7 + sha1h.32 q8, q8 + sha1h.32 q15, q15 + sha1su1.32 q0, q0 + sha1su1.32 q7, q7 + sha1su1.32 q8, q8 + sha1su1.32 q15, q15 + sha256su0.32 q0, q0 + sha256su0.32 q7, q7 + sha256su0.32 q8, q8 + sha256su0.32 q15, q15 + + .thumb + vmull.p64 q0, d0, d0 + vmull.p64 q15, d31, d31 + aese.8 q0, q0 + aese.8 q7, q7 + aese.8 q8, q8 + aese.8 q15, q15 + aesd.8 q0, q0 + aesd.8 q7, q7 + aesd.8 q8, q8 + aesd.8 q15, q15 + aesmc.8 q0, q0 + aesmc.8 q7, q7 + aesmc.8 q8, q8 + aesmc.8 q15, q15 + aesimc.8 q0, q0 + aesimc.8 q7, q7 + aesimc.8 q8, q8 + aesimc.8 q15, q15 + sha1c.32 q0, q0, q0 + sha1c.32 q7, q7, q7 + sha1c.32 q8, q8, q8 + sha1c.32 q15, q15, q15 + sha1p.32 q0, q0, q0 + sha1p.32 q7, q7, q7 + sha1p.32 q8, q8, q8 + sha1p.32 q15, q15, q15 + sha1m.32 q0, q0, q0 + sha1m.32 q7, q7, q7 + sha1m.32 q8, q8, q8 + sha1m.32 q15, q15, q15 + sha1su0.32 q0, q0, q0 + sha1su0.32 q7, q7, q7 + sha1su0.32 q8, q8, q8 + sha1su0.32 q15, q15, q15 + sha256h.32 q0, q0, q0 + sha256h.32 q7, q7, q7 + sha256h.32 q8, q8, q8 + sha256h.32 q15, q15, q15 + sha256h2.32 q0, q0, q0 + sha256h2.32 q7, q7, q7 + sha256h2.32 q8, q8, q8 + sha256h2.32 q15, q15, q15 + sha256su1.32 q0, q0, q0 + sha256su1.32 q7, q7, q7 + sha256su1.32 q8, q8, q8 + sha256su1.32 q15, q15, q15 + sha1h.32 q0, q0 + sha1h.32 q7, q7 + sha1h.32 q8, q8 + sha1h.32 q15, q15 + sha1su1.32 q0, q0 + sha1su1.32 q7, q7 + sha1su1.32 q8, q8 + sha1su1.32 q15, q15 + sha256su0.32 q0, q0 + sha256su0.32 q7, q7 + sha256su0.32 q8, q8 + sha256su0.32 q15, q15 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a+fp.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+fp.d new file mode 100644 index 00000000..d50a73bd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+fp.d @@ -0,0 +1,114 @@ +#name: Valid v8-a+fp +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> fe000a00 vseleq.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fe500aa0 vselvs.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe2ffa0f vselge.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fe7ffaaf vselgt.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe000b00 vseleq.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> febc0ac0 vcvta.s32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fefd0ae0 vcvtn.s32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> febefa4f vcvtp.u32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> fefffa6f vcvtm.u32.f32 s31, s31 +0[0-9a-f]+ <[^>]+> febc0b40 vcvta.u32.f64 s0, d0 +0[0-9a-f]+ <[^>]+> fefd0b60 vcvtn.u32.f64 s1, d16 +0[0-9a-f]+ <[^>]+> febefb4f vcvtp.u32.f64 s30, d15 +0[0-9a-f]+ <[^>]+> fefffb6f vcvtm.u32.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb60ac0 vrintz.f32 s0, s0 +0[0-9a-f]+ <[^>]+> eef70a60 vrintx.f32 s1, s1 +0[0-9a-f]+ <[^>]+> 0eb6fa4f vrintreq.f32 s30, s30 +0[0-9a-f]+ <[^>]+> feb80a40 vrinta.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fef90a60 vrintn.f32 s1, s1 +0[0-9a-f]+ <[^>]+> febafa4f vrintp.f32 s30, s30 +0[0-9a-f]+ <[^>]+> fefbfa6f vrintm.f32 s31, s31 +0[0-9a-f]+ <[^>]+> eeb60bc0 vrintz.f64 d0, d0 +0[0-9a-f]+ <[^>]+> eeb71b41 vrintx.f64 d1, d1 +0[0-9a-f]+ <[^>]+> 0ef6eb6e vrintreq.f64 d30, d30 +0[0-9a-f]+ <[^>]+> feb80b40 vrinta.f64 d0, d0 +0[0-9a-f]+ <[^>]+> feb91b41 vrintn.f64 d1, d1 +0[0-9a-f]+ <[^>]+> fefaeb6e vrintp.f64 d30, d30 +0[0-9a-f]+ <[^>]+> fefbfb6f vrintm.f64 d31, d31 +0[0-9a-f]+ <[^>]+> eeb30bc0 vcvtt.f16.f64 s0, d0 +0[0-9a-f]+ <[^>]+> eef30b60 vcvtb.f16.f64 s1, d16 +0[0-9a-f]+ <[^>]+> eeb3fbcf vcvtt.f16.f64 s30, d15 +0[0-9a-f]+ <[^>]+> eef3fb6f vcvtb.f16.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb20bc0 vcvtt.f64.f16 d0, s0 +0[0-9a-f]+ <[^>]+> eef20b60 vcvtb.f64.f16 d16, s1 +0[0-9a-f]+ <[^>]+> eeb2fbcf vcvtt.f64.f16 d15, s30 +0[0-9a-f]+ <[^>]+> eef2fb6f vcvtb.f64.f16 d31, s31 +0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fe7f faaf vselgt.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe00 0b00 vseleq.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0 +0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1 +0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30 +0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31 +0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16 +0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15 +0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31 +0[0-9a-f]+ <[^>]+> febc 0ac0 vcvta.s32.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fefd 0ae0 vcvtn.s32.f32 s1, s1 +0[0-9a-f]+ <[^>]+> febe fa4f vcvtp.u32.f32 s30, s30 +0[0-9a-f]+ <[^>]+> feff fa6f vcvtm.u32.f32 s31, s31 +0[0-9a-f]+ <[^>]+> febc 0b40 vcvta.u32.f64 s0, d0 +0[0-9a-f]+ <[^>]+> fefd 0b60 vcvtn.u32.f64 s1, d16 +0[0-9a-f]+ <[^>]+> febe fb4f vcvtp.u32.f64 s30, d15 +0[0-9a-f]+ <[^>]+> feff fb6f vcvtm.u32.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb6 0ac0 vrintz.f32 s0, s0 +0[0-9a-f]+ <[^>]+> eef7 0a60 vrintx.f32 s1, s1 +0[0-9a-f]+ <[^>]+> eeb6 fa4f vrintr.f32 s30, s30 +0[0-9a-f]+ <[^>]+> feb8 0a40 vrinta.f32 s0, s0 +0[0-9a-f]+ <[^>]+> fef9 0a60 vrintn.f32 s1, s1 +0[0-9a-f]+ <[^>]+> feba fa4f vrintp.f32 s30, s30 +0[0-9a-f]+ <[^>]+> fefb fa6f vrintm.f32 s31, s31 +0[0-9a-f]+ <[^>]+> eeb6 0bc0 vrintz.f64 d0, d0 +0[0-9a-f]+ <[^>]+> eeb7 1b41 vrintx.f64 d1, d1 +0[0-9a-f]+ <[^>]+> eef6 eb6e vrintr.f64 d30, d30 +0[0-9a-f]+ <[^>]+> feb8 0b40 vrinta.f64 d0, d0 +0[0-9a-f]+ <[^>]+> feb9 1b41 vrintn.f64 d1, d1 +0[0-9a-f]+ <[^>]+> fefa eb6e vrintp.f64 d30, d30 +0[0-9a-f]+ <[^>]+> fefb fb6f vrintm.f64 d31, d31 +0[0-9a-f]+ <[^>]+> eeb3 0bc0 vcvtt.f16.f64 s0, d0 +0[0-9a-f]+ <[^>]+> eef3 0b60 vcvtb.f16.f64 s1, d16 +0[0-9a-f]+ <[^>]+> eeb3 fbcf vcvtt.f16.f64 s30, d15 +0[0-9a-f]+ <[^>]+> eef3 fb6f vcvtb.f16.f64 s31, d31 +0[0-9a-f]+ <[^>]+> eeb2 0bc0 vcvtt.f64.f16 d0, s0 +0[0-9a-f]+ <[^>]+> eef2 0b60 vcvtb.f64.f16 d16, s1 +0[0-9a-f]+ <[^>]+> eeb2 fbcf vcvtt.f64.f16 d15, s30 +0[0-9a-f]+ <[^>]+> eef2 fb6f vcvtb.f64.f16 d31, s31 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a+fp.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+fp.s new file mode 100644 index 00000000..f7a54736 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+fp.s @@ -0,0 +1,116 @@ + .syntax unified + .text + .arch armv8-a + .arch_extension fp + + .arm + vseleq.f32 s0, s0, s0 + vselvs.f32 s1, s1, s1 + vselge.f32 s30, s30, s30 + vselgt.f32 s31, s31, s31 + vseleq.f64 d0, d0, d0 + vselvs.f64 d16, d16, d16 + vselge.f64 d15, d15, d15 + vselgt.f64 d31, d31, d31 + vmaxnm.f32 s0, s0, s0 + vmaxnm.f32 s1, s1, s1 + vmaxnm.f32 s30, s30, s30 + vmaxnm.f32 s31, s31, s31 + vmaxnm.f64 d0, d0, d0 + vmaxnm.f64 d16, d16, d16 + vmaxnm.f64 d15, d15, d15 + vmaxnm.f64 d31, d31, d31 + vminnm.f32 s0, s0, s0 + vminnm.f32 s1, s1, s1 + vminnm.f32 s30, s30, s30 + vminnm.f32 s31, s31, s31 + vminnm.f64 d0, d0, d0 + vminnm.f64 d16, d16, d16 + vminnm.f64 d15, d15, d15 + vminnm.f64 d31, d31, d31 + vcvta.s32.f32 s0, s0 + vcvtn.s32.f32 s1, s1 + vcvtp.u32.f32 s30, s30 + vcvtm.u32.f32 s31, s31 + vcvta.s32.f64 s0, d0 + vcvtn.s32.f64 s1, d16 + vcvtp.u32.f64 s30, d15 + vcvtm.u32.f64 s31, d31 + vrintz.f32 s0, s0 + vrintx.f32 s1, s1 + vrintreq.f32 s30, s30 + vrinta.f32 s0, s0 + vrintn.f32 s1, s1 + vrintp.f32 s30, s30 + vrintm.f32 s31, s31 + vrintz.f64 d0, d0 + vrintx.f64 d1, d1 + vrintreq.f64 d30, d30 + vrinta.f64 d0, d0 + vrintn.f64 d1, d1 + vrintp.f64 d30, d30 + vrintm.f64 d31, d31 + vcvtt.f16.f64 s0, d0 + vcvtb.f16.f64 s1, d16 + vcvtt.f16.f64 s30, d15 + vcvtb.f16.f64 s31, d31 + vcvtt.f64.f16 d0, s0 + vcvtb.f64.f16 d16, s1 + vcvtt.f64.f16 d15, s30 + vcvtb.f64.f16 d31, s31 + + .thumb + vseleq.f32 s0, s0, s0 + vselvs.f32 s1, s1, s1 + vselge.f32 s30, s30, s30 + vselgt.f32 s31, s31, s31 + vseleq.f64 d0, d0, d0 + vselvs.f64 d16, d16, d16 + vselge.f64 d15, d15, d15 + vselgt.f64 d31, d31, d31 + vmaxnm.f32 s0, s0, s0 + vmaxnm.f32 s1, s1, s1 + vmaxnm.f32 s30, s30, s30 + vmaxnm.f32 s31, s31, s31 + vmaxnm.f64 d0, d0, d0 + vmaxnm.f64 d16, d16, d16 + vmaxnm.f64 d15, d15, d15 + vmaxnm.f64 d31, d31, d31 + vminnm.f32 s0, s0, s0 + vminnm.f32 s1, s1, s1 + vminnm.f32 s30, s30, s30 + vminnm.f32 s31, s31, s31 + vminnm.f64 d0, d0, d0 + vminnm.f64 d16, d16, d16 + vminnm.f64 d15, d15, d15 + vminnm.f64 d31, d31, d31 + vcvta.s32.f32 s0, s0 + vcvtn.s32.f32 s1, s1 + vcvtp.u32.f32 s30, s30 + vcvtm.u32.f32 s31, s31 + vcvta.s32.f64 s0, d0 + vcvtn.s32.f64 s1, d16 + vcvtp.u32.f64 s30, d15 + vcvtm.u32.f64 s31, d31 + vrintz.f32 s0, s0 + vrintx.f32 s1, s1 + vrintr.f32 s30, s30 + vrinta.f32 s0, s0 + vrintn.f32 s1, s1 + vrintp.f32 s30, s30 + vrintm.f32 s31, s31 + vrintz.f64 d0, d0 + vrintx.f64 d1, d1 + vrintr.f64 d30, d30 + vrinta.f64 d0, d0 + vrintn.f64 d1, d1 + vrintp.f64 d30, d30 + vrintm.f64 d31, d31 + vcvtt.f16.f64 s0, d0 + vcvtb.f16.f64 s1, d16 + vcvtt.f16.f64 s30, d15 + vcvtb.f16.f64 s31, d31 + vcvtt.f64.f16 d0, s0 + vcvtb.f64.f16 d16, s1 + vcvtt.f64.f16 d15, s30 + vcvtb.f64.f16 d31, s31 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a+simd.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+simd.d new file mode 100644 index 00000000..49ef5b6a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+simd.d @@ -0,0 +1,78 @@ +#name: Valid v8-a+simdv3 +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> f32fff1f vminnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> f36fffbf vminnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> f3200f50 vminnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> f3bb0000 vcvta.s32.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3fb0120 vcvtn.s32.f32 d16, d16 +0[0-9a-f]+ <[^>]+> f3bbf28f vcvtp.u32.f32 d15, d15 +0[0-9a-f]+ <[^>]+> f3fbf3af vcvtm.u32.f32 d31, d31 +0[0-9a-f]+ <[^>]+> f3bb0040 vcvta.s32.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3fb0160 vcvtn.s32.f32 q8, q8 +0[0-9a-f]+ <[^>]+> f3bbe2ce vcvtp.u32.f32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fbe3ee vcvtm.u32.f32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba0500 vrinta.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3fa0420 vrintn.f32 d16, d16 +0[0-9a-f]+ <[^>]+> f3baf68f vrintm.f32 d15, d15 +0[0-9a-f]+ <[^>]+> f3faf7af vrintp.f32 d31, d31 +0[0-9a-f]+ <[^>]+> f3ba04af vrintx.f32 d0, d31 +0[0-9a-f]+ <[^>]+> f3fa058f vrintz.f32 d16, d15 +0[0-9a-f]+ <[^>]+> f3ba0540 vrinta.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3fa0460 vrintn.f32 q8, q8 +0[0-9a-f]+ <[^>]+> f3bae6ce vrintm.f32 q7, q7 +0[0-9a-f]+ <[^>]+> f3fae7ee vrintp.f32 q15, q15 +0[0-9a-f]+ <[^>]+> f3ba04ee vrintx.f32 q0, q15 +0[0-9a-f]+ <[^>]+> f3fa05ce vrintz.f32 q8, q7 +0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> ff4f ffbf vmaxnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> ff00 0f50 vmaxnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff40 0ff0 vmaxnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff0e ef5e vmaxnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff4e effe vmaxnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ff20 0f10 vminnm.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> ff60 0fb0 vminnm.f32 d16, d16, d16 +0[0-9a-f]+ <[^>]+> ff2f ff1f vminnm.f32 d15, d15, d15 +0[0-9a-f]+ <[^>]+> ff6f ffbf vminnm.f32 d31, d31, d31 +0[0-9a-f]+ <[^>]+> ff20 0f50 vminnm.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8 +0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7 +0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15 +0[0-9a-f]+ <[^>]+> ffbb 0000 vcvta.s32.f32 d0, d0 +0[0-9a-f]+ <[^>]+> fffb 0120 vcvtn.s32.f32 d16, d16 +0[0-9a-f]+ <[^>]+> ffbb f28f vcvtp.u32.f32 d15, d15 +0[0-9a-f]+ <[^>]+> fffb f3af vcvtm.u32.f32 d31, d31 +0[0-9a-f]+ <[^>]+> ffbb 0040 vcvta.s32.f32 q0, q0 +0[0-9a-f]+ <[^>]+> fffb 0160 vcvtn.s32.f32 q8, q8 +0[0-9a-f]+ <[^>]+> ffbb e2ce vcvtp.u32.f32 q7, q7 +0[0-9a-f]+ <[^>]+> fffb e3ee vcvtm.u32.f32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 0500 vrinta.f32 d0, d0 +0[0-9a-f]+ <[^>]+> fffa 0420 vrintn.f32 d16, d16 +0[0-9a-f]+ <[^>]+> ffba f68f vrintm.f32 d15, d15 +0[0-9a-f]+ <[^>]+> fffa f7af vrintp.f32 d31, d31 +0[0-9a-f]+ <[^>]+> ffba 04af vrintx.f32 d0, d31 +0[0-9a-f]+ <[^>]+> fffa 058f vrintz.f32 d16, d15 +0[0-9a-f]+ <[^>]+> ffba 0540 vrinta.f32 q0, q0 +0[0-9a-f]+ <[^>]+> fffa 0460 vrintn.f32 q8, q8 +0[0-9a-f]+ <[^>]+> ffba e6ce vrintm.f32 q7, q7 +0[0-9a-f]+ <[^>]+> fffa e7ee vrintp.f32 q15, q15 +0[0-9a-f]+ <[^>]+> ffba 04ee vrintx.f32 q0, q15 +0[0-9a-f]+ <[^>]+> fffa 05ce vrintz.f32 q8, q7 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a+simd.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+simd.s new file mode 100644 index 00000000..4d7bce7b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a+simd.s @@ -0,0 +1,79 @@ + .syntax unified + .arch armv8-a + .arch_extension simd + + .arm + vmaxnm.f32 d0, d0, d0 + vmaxnm.f32 d16, d16, d16 + vmaxnm.f32 d15, d15, d15 + vmaxnm.f32 d31, d31, d31 + vmaxnm.f32 q0, q0, q0 + vmaxnm.f32 q8, q8, q8 + vmaxnm.f32 q7, q7, q7 + vmaxnm.f32 q15, q15, q15 + vminnm.f32 d0, d0, d0 + vminnm.f32 d16, d16, d16 + vminnm.f32 d15, d15, d15 + vminnm.f32 d31, d31, d31 + vminnm.f32 q0, q0, q0 + vminnm.f32 q8, q8, q8 + vminnm.f32 q7, q7, q7 + vminnm.f32 q15, q15, q15 + vcvta.s32.f32 d0, d0 + vcvtn.s32.f32 d16, d16 + vcvtp.u32.f32 d15, d15 + vcvtm.u32.f32 d31, d31 + vcvta.s32.f32 q0, q0 + vcvtn.s32.f32 q8, q8 + vcvtp.u32.f32 q7, q7 + vcvtm.u32.f32 q15, q15 + vrinta.f32 d0, d0 + vrintn.f32 d16, d16 + vrintm.f32 d15, d15 + vrintp.f32 d31, d31 + vrintx.f32 d0, d31 + vrintz.f32 d16, d15 + vrinta.f32 q0, q0 + vrintn.f32 q8, q8 + vrintm.f32 q7, q7 + vrintp.f32 q15, q15 + vrintx.f32 q0, q15 + vrintz.f32 q8, q7 + + .thumb + vmaxnm.f32 d0, d0, d0 + vmaxnm.f32 d16, d16, d16 + vmaxnm.f32 d15, d15, d15 + vmaxnm.f32 d31, d31, d31 + vmaxnm.f32 q0, q0, q0 + vmaxnm.f32 q8, q8, q8 + vmaxnm.f32 q7, q7, q7 + vmaxnm.f32 q15, q15, q15 + vminnm.f32 d0, d0, d0 + vminnm.f32 d16, d16, d16 + vminnm.f32 d15, d15, d15 + vminnm.f32 d31, d31, d31 + vminnm.f32 q0, q0, q0 + vminnm.f32 q8, q8, q8 + vminnm.f32 q7, q7, q7 + vminnm.f32 q15, q15, q15 + vcvta.s32.f32 d0, d0 + vcvtn.s32.f32 d16, d16 + vcvtp.u32.f32 d15, d15 + vcvtm.u32.f32 d31, d31 + vcvta.s32.f32 q0, q0 + vcvtn.s32.f32 q8, q8 + vcvtp.u32.f32 q7, q7 + vcvtm.u32.f32 q15, q15 + vrinta.f32 d0, d0 + vrintn.f32 d16, d16 + vrintm.f32 d15, d15 + vrintp.f32 d31, d31 + vrintx.f32 d0, d31 + vrintz.f32 d16, d15 + vrinta.f32 q0, q0 + vrintn.f32 q8, q8 + vrintm.f32 q7, q7 + vrintp.f32 q15, q15 + vrintx.f32 q0, q15 + vrintz.f32 q8, q7 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.d new file mode 100644 index 00000000..94e130c6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.d @@ -0,0 +1,2 @@ +#name: Invalid v8-a +#error-output: armv8-a-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.l b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.l new file mode 100644 index 00000000..0d0751fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.l @@ -0,0 +1,96 @@ +.*: Assembler messages: +.*:7: Error: swp{b} use is obsoleted for ARMv8 and later +.*:10: Warning: This coprocessor register access is deprecated in ARMv8 +.*:11: Warning: This coprocessor register access is deprecated in ARMv8 +.*:12: Warning: This coprocessor register access is deprecated in ARMv8 +.*:13: Warning: This coprocessor register access is deprecated in ARMv8 +.*:14: Warning: This coprocessor register access is deprecated in ARMv8 +.*:17: Warning: setend use is deprecated for ARMv8 +.*:20: Warning: setend use is deprecated for ARMv8 +.*:24: Error: immediate value out of range -- `hlt 0x10000' +.*:25: Error: instruction cannot be conditional -- `hltne 0x1' +.*:29: Error: immediate value out of range -- `hlt 64' +.*:31: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions +.*:31: Error: instruction is always unconditional -- `hltne 0' +.*:35: Error: r15 not allowed here -- `stlb pc,\[r0\]' +.*:36: Error: r15 not allowed here -- `stlb r0,\[pc\]' +.*:37: Error: r15 not allowed here -- `stlh pc,\[r0\]' +.*:38: Error: r15 not allowed here -- `stlh r0,\[pc\]' +.*:39: Error: r15 not allowed here -- `stl pc,\[r0\]' +.*:40: Error: r15 not allowed here -- `stl r0,\[pc\]' +.*:41: Error: r15 not allowed here -- `stlexb r1,pc,\[r0\]' +.*:42: Error: r15 not allowed here -- `stlexb r1,r0,\[pc\]' +.*:43: Error: r15 not allowed here -- `stlexb pc,r0,\[r1\]' +.*:44: Error: registers may not be the same -- `stlexb r0,r0,\[r1\]' +.*:45: Error: registers may not be the same -- `stlexb r0,r1,\[r0\]' +.*:46: Error: r15 not allowed here -- `stlexh r1,pc,\[r0\]' +.*:47: Error: r15 not allowed here -- `stlexh r1,r0,\[pc\]' +.*:48: Error: r15 not allowed here -- `stlexh pc,r0,\[r1\]' +.*:49: Error: registers may not be the same -- `stlexh r0,r0,\[r1\]' +.*:50: Error: registers may not be the same -- `stlexh r0,r1,\[r0\]' +.*:51: Error: r15 not allowed here -- `stlex r1,pc,\[r0\]' +.*:52: Error: r15 not allowed here -- `stlex r1,r0,\[pc\]' +.*:53: Error: r15 not allowed here -- `stlex pc,r0,\[r1\]' +.*:54: Error: registers may not be the same -- `stlex r0,r0,\[r1\]' +.*:55: Error: registers may not be the same -- `stlex r0,r1,\[r0\]' +.*:56: Error: r14 not allowed here -- `stlexd r1,lr,\[r0\]' +.*:57: Error: r15 not allowed here -- `stlexd r1,r0,\[pc\]' +.*:58: Error: r15 not allowed here -- `stlexd pc,r0,\[r1\]' +.*:59: Error: registers may not be the same -- `stlexd r0,r0,\[r1\]' +.*:60: Error: registers may not be the same -- `stlexd r0,r2,\[r0\]' +.*:61: Error: even register required -- `stlexd r0,r1,\[r2\]' +.*:65: Error: r15 not allowed here -- `stlb pc,\[r0\]' +.*:66: Error: r15 not allowed here -- `stlb r0,\[pc\]' +.*:67: Error: r15 not allowed here -- `stlh pc,\[r0\]' +.*:68: Error: r15 not allowed here -- `stlh r0,\[pc\]' +.*:69: Error: r15 not allowed here -- `stl pc,\[r0\]' +.*:70: Error: r15 not allowed here -- `stl r0,\[pc\]' +.*:71: Error: r15 not allowed here -- `stlexb r1,pc,\[r0\]' +.*:72: Error: r15 not allowed here -- `stlexb r1,r0,\[pc\]' +.*:73: Error: r15 not allowed here -- `stlexb pc,r0,\[r1\]' +.*:74: Error: registers may not be the same -- `stlexb r0,r0,\[r1\]' +.*:75: Error: registers may not be the same -- `stlexb r0,r1,\[r0\]' +.*:76: Error: r15 not allowed here -- `stlexh r1,pc,\[r0\]' +.*:77: Error: r15 not allowed here -- `stlexh r1,r0,\[pc\]' +.*:78: Error: r15 not allowed here -- `stlexh pc,r0,\[r1\]' +.*:79: Error: registers may not be the same -- `stlexh r0,r0,\[r1\]' +.*:80: Error: registers may not be the same -- `stlexh r0,r1,\[r0\]' +.*:81: Error: r15 not allowed here -- `stlex r1,pc,\[r0\]' +.*:82: Error: r15 not allowed here -- `stlex r1,r0,\[pc\]' +.*:83: Error: r15 not allowed here -- `stlex pc,r0,\[r1\]' +.*:84: Error: registers may not be the same -- `stlex r0,r0,\[r1\]' +.*:85: Error: registers may not be the same -- `stlex r0,r1,\[r0\]' +.*:87: Error: r15 not allowed here -- `stlexd r1,r0,\[pc\]' +.*:88: Error: r15 not allowed here -- `stlexd pc,r0,\[r1\]' +.*:89: Error: registers may not be the same -- `stlexd r0,r0,\[r1\]' +.*:90: Error: registers may not be the same -- `stlexd r0,r2,\[r0\]' +.*:95: Error: r15 not allowed here -- `ldab pc,\[r0\]' +.*:96: Error: r15 not allowed here -- `ldab r0,\[pc\]' +.*:97: Error: r15 not allowed here -- `ldah pc,\[r0\]' +.*:98: Error: r15 not allowed here -- `ldah r0,\[pc\]' +.*:99: Error: r15 not allowed here -- `lda pc,\[r0\]' +.*:100: Error: r15 not allowed here -- `lda r0,\[pc\]' +.*:101: Error: r15 not allowed here -- `ldaexb pc,\[r0\]' +.*:102: Error: r15 not allowed here -- `ldaexb r0,\[pc\]' +.*:103: Error: r15 not allowed here -- `ldaexh pc,\[r0\]' +.*:104: Error: r15 not allowed here -- `ldaexh r0,\[pc\]' +.*:105: Error: r15 not allowed here -- `ldaex pc,\[r0\]' +.*:106: Error: r15 not allowed here -- `ldaex r0,\[pc\]' +.*:107: Error: r14 not allowed here -- `ldaexd lr,\[r0\]' +.*:108: Error: r15 not allowed here -- `ldaexd r0,\[pc\]' +.*:109: Error: even register required -- `ldaexd r1,\[r2\]' +.*:113: Error: r15 not allowed here -- `ldab pc,\[r0\]' +.*:114: Error: r15 not allowed here -- `ldab r0,\[pc\]' +.*:115: Error: r15 not allowed here -- `ldah pc,\[r0\]' +.*:116: Error: r15 not allowed here -- `ldah r0,\[pc\]' +.*:117: Error: r15 not allowed here -- `lda pc,\[r0\]' +.*:118: Error: r15 not allowed here -- `lda r0,\[pc\]' +.*:119: Error: r15 not allowed here -- `ldaexb pc,\[r0\]' +.*:120: Error: r15 not allowed here -- `ldaexb r0,\[pc\]' +.*:121: Error: r15 not allowed here -- `ldaexh pc,\[r0\]' +.*:122: Error: r15 not allowed here -- `ldaexh r0,\[pc\]' +.*:123: Error: r15 not allowed here -- `ldaex pc,\[r0\]' +.*:124: Error: r15 not allowed here -- `ldaex r0,\[pc\]' +.*:125: Error: r15 not allowed here -- `ldaexd r0,pc,\[r0\]' +.*:126: Error: r15 not allowed here -- `ldaexd pc,r0,\[r0\]' +.*:127: Error: r15 not allowed here -- `ldaexd r1,r0,\[pc\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.s new file mode 100644 index 00000000..90919e72 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-bad.s @@ -0,0 +1,127 @@ + .syntax unified + .text + .arch armv8-a + + // SWP + .arm + swp r0, r1, [r2] + + // deprecated MCRs + mcr p15, 0, r0, c7, c5, 4 + mcr p15, 0, r1, c7, c10, 4 + mcr p15, 0, r2, c7, c10, 5 + mrc p14, 6, r1, c0, c0, 0 + mrc p14, 6, r0, c1, c0, 0 + + // deprecated SETEND + setend be + + .thumb + setend le + + // HLT A32 + .arm + hlt 0x10000 + hltne 0x1 + + // HLT T32 + .thumb + hlt 64 + it ne + hltne 0 + + // STL A32 + .arm + stlb pc, [r0] + stlb r0, [pc] + stlh pc, [r0] + stlh r0, [pc] + stl pc, [r0] + stl r0, [pc] + stlexb r1, pc, [r0] + stlexb r1, r0, [pc] + stlexb pc, r0, [r1] + stlexb r0, r0, [r1] + stlexb r0, r1, [r0] + stlexh r1, pc, [r0] + stlexh r1, r0, [pc] + stlexh pc, r0, [r1] + stlexh r0, r0, [r1] + stlexh r0, r1, [r0] + stlex r1, pc, [r0] + stlex r1, r0, [pc] + stlex pc, r0, [r1] + stlex r0, r0, [r1] + stlex r0, r1, [r0] + stlexd r1, lr, [r0] + stlexd r1, r0, [pc] + stlexd pc, r0, [r1] + stlexd r0, r0, [r1] + stlexd r0, r2, [r0] + stlexd r0, r1, [r2] + + // STL T32 + .thumb + stlb pc, [r0] + stlb r0, [pc] + stlh pc, [r0] + stlh r0, [pc] + stl pc, [r0] + stl r0, [pc] + stlexb r1, pc, [r0] + stlexb r1, r0, [pc] + stlexb pc, r0, [r1] + stlexb r0, r0, [r1] + stlexb r0, r1, [r0] + stlexh r1, pc, [r0] + stlexh r1, r0, [pc] + stlexh pc, r0, [r1] + stlexh r0, r0, [r1] + stlexh r0, r1, [r0] + stlex r1, pc, [r0] + stlex r1, r0, [pc] + stlex pc, r0, [r1] + stlex r0, r0, [r1] + stlex r0, r1, [r0] + stlexd r1, lr, [r0] + stlexd r1, r0, [pc] + stlexd pc, r0, [r1] + stlexd r0, r0, [r1] + stlexd r0, r2, [r0] + stlexd r0, r1, [r2] + + // LDA A32 + .arm + ldab pc, [r0] + ldab r0, [pc] + ldah pc, [r0] + ldah r0, [pc] + lda pc, [r0] + lda r0, [pc] + ldaexb pc, [r0] + ldaexb r0, [pc] + ldaexh pc, [r0] + ldaexh r0, [pc] + ldaex pc, [r0] + ldaex r0, [pc] + ldaexd lr, [r0] + ldaexd r0, [pc] + ldaexd r1, [r2] + + // LDA T32 + .thumb + ldab pc, [r0] + ldab r0, [pc] + ldah pc, [r0] + ldah r0, [pc] + lda pc, [r0] + lda r0, [pc] + ldaexb pc, [r0] + ldaexb r0, [pc] + ldaexh pc, [r0] + ldaexh r0, [pc] + ldaex pc, [r0] + ldaex r0, [pc] + ldaexd r0, pc, [r0] + ldaexd pc, r0, [r0] + ldaexd r1, r0, [pc] diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier-arm.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier-arm.d new file mode 100644 index 00000000..1a245fa9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier-arm.d @@ -0,0 +1,24 @@ +#name: Valid v8-A barrier (ARM) +#as: -march=armv8-a +#source: armv8-a-barrier.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f57ff04d dsb ld +0[0-9a-f]+ <[^>]+> f57ff049 dsb ishld +0[0-9a-f]+ <[^>]+> f57ff045 dsb nshld +0[0-9a-f]+ <[^>]+> f57ff041 dsb oshld +0[0-9a-f]+ <[^>]+> f57ff05d dmb ld +0[0-9a-f]+ <[^>]+> f57ff059 dmb ishld +0[0-9a-f]+ <[^>]+> f57ff055 dmb nshld +0[0-9a-f]+ <[^>]+> f57ff051 dmb oshld +0[0-9a-f]+ <[^>]+> f57ff04d dsb ld +0[0-9a-f]+ <[^>]+> f57ff049 dsb ishld +0[0-9a-f]+ <[^>]+> f57ff045 dsb nshld +0[0-9a-f]+ <[^>]+> f57ff041 dsb oshld +0[0-9a-f]+ <[^>]+> f57ff05d dmb ld +0[0-9a-f]+ <[^>]+> f57ff059 dmb ishld +0[0-9a-f]+ <[^>]+> f57ff055 dmb nshld +0[0-9a-f]+ <[^>]+> f57ff051 dmb oshld diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d new file mode 100644 index 00000000..42dae156 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier-thumb.d @@ -0,0 +1,24 @@ +#name: Valid v8-A barrier (Thumb) +#as: -march=armv8-a -mthumb +#source: armv8-a-barrier.s +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3bf 8f4d dsb ld +0[0-9a-f]+ <[^>]+> f3bf 8f49 dsb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f45 dsb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f41 dsb oshld +0[0-9a-f]+ <[^>]+> f3bf 8f5d dmb ld +0[0-9a-f]+ <[^>]+> f3bf 8f59 dmb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f55 dmb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f51 dmb oshld +0[0-9a-f]+ <[^>]+> f3bf 8f4d dsb ld +0[0-9a-f]+ <[^>]+> f3bf 8f49 dsb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f45 dsb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f41 dsb oshld +0[0-9a-f]+ <[^>]+> f3bf 8f5d dmb ld +0[0-9a-f]+ <[^>]+> f3bf 8f59 dmb ishld +0[0-9a-f]+ <[^>]+> f3bf 8f55 dmb nshld +0[0-9a-f]+ <[^>]+> f3bf 8f51 dmb oshld diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier.s new file mode 100644 index 00000000..f7b71c0c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-barrier.s @@ -0,0 +1,18 @@ + .syntax unified + .text + dsb ld + dsb ishld + dsb nshld + dsb oshld + dmb ld + dmb ishld + dmb nshld + dmb oshld + dsb LD + dsb ISHLD + dsb NSHLD + dsb OSHLD + dmb LD + dmb ISHLD + dmb NSHLD + dmb OSHLD diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.d new file mode 100644 index 00000000..47894842 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.d @@ -0,0 +1,3 @@ +#name: Deprecated IT blocks (ARM v8) +#error-output: armv8-a-it-bad.l +#as: -mimplicit-it=always diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.l b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.l new file mode 100644 index 00000000..e3a5971f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.l @@ -0,0 +1,14 @@ +.*: Assembler messages: +.*:7: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8 +.*:15: Warning: IT blocks containing more than one conditional instruction are deprecated in ARMv8 +.*:20: Warning: IT blocks containing more than one conditional instruction are deprecated in ARMv8 +.*:30: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8 +.*:36: Warning: IT blocks containing more than one conditional instruction are deprecated in ARMv8 +.*:40: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +.*:43: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Miscellaneous 16-bit instructions +.*:49: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Literal loads +.*:52: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc +.*:55: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +.*:55: Error: r15 not allowed here -- `addeq r0,pc,pc' +.*:58: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +.*:58: Error: r15 not allowed here -- `addeq pc,r0,r0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.s new file mode 100644 index 00000000..42f2b86b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a-it-bad.s @@ -0,0 +1,58 @@ +.syntax unified +.arch armv8-a + +.thumb +@ Wide instruction in IT block is deprecated. +it eq +ldrdeq r0, [r1] + +@ This IT block is not deprecated. +it eq +moveq r2, r3 + +@ IT block of more than one instruction is deprecated. +itt eq +moveq r0, r1 +moveq r2, r3 + +@ Even for auto IT blocks +moveq r2, r3 +movne r2, r3 + +adds r0, r1 + +@ This automatic IT block is valid +moveq r2,r3 + +add r0, r1, r2 + +@ This one is too wide. +ldrdeq r0, [r1] + +add r0, r1, r2 + +@ Test automatic IT block generation at end of a file. +movne r0, r1 +moveq r1, r0 + +@ Test the various classes of 16-bit instructions that are deprecated. +it eq +svceq 0 + +it eq +uxtheq r0, r1 + +it eq +addeq r0, pc, #0 + +it eq +ldreq r0, [pc, #4] + +it eq +bxeq pc + +it eq +addeq r0, pc, pc + +it eq +addeq pc, r0, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a.d b/binutils-2.25/gas/testsuite/gas/arm/armv8-a.d new file mode 100644 index 00000000..60e50675 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a.d @@ -0,0 +1,102 @@ +#name: Valid v8-a +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e320f005 sevl +0[0-9a-f]+ <[^>]+> e1000070 hlt 0x0000 +0[0-9a-f]+ <[^>]+> e100007f hlt 0x000f +0[0-9a-f]+ <[^>]+> e10fff70 hlt 0xfff0 +0[0-9a-f]+ <[^>]+> e1c0fc90 stlb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1c1fc91 stlb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1cefc9e stlb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1e0fc90 stlh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1e1fc91 stlh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1eefc9e stlh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e180fc90 stl r0, \[r0\] +0[0-9a-f]+ <[^>]+> e181fc91 stl r1, \[r1\] +0[0-9a-f]+ <[^>]+> e18efc9e stl lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1ce0e91 stlexb r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e1c01e9e stlexb r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e1c1ee90 stlexb lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e1ee0e91 stlexh r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e1e01e9e stlexh r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e1e1ee90 stlexh lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e18e0e91 stlex r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e1801e9e stlex r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e181ee90 stlex lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e1ae0e92 stlexd r0, r2, r3, \[lr\] +0[0-9a-f]+ <[^>]+> e1a01e9c stlexd r1, ip, sp, \[r0\] +0[0-9a-f]+ <[^>]+> e1a1ee90 stlexd lr, r0, r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1d00c9f ldab r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1d11c9f ldab r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1deec9f ldab lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1f00c9f ldaexh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1f11c9f ldaexh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1feec9f ldaexh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1900c9f lda r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1911c9f lda r1, \[r1\] +0[0-9a-f]+ <[^>]+> e19eec9f lda lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1d00e9f ldaexb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1d11e9f ldaexb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1deee9f ldaexb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1f00e9f ldaexh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1f11e9f ldaexh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e1feee9f ldaexh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1900e9f ldaex r0, \[r0\] +0[0-9a-f]+ <[^>]+> e1911e9f ldaex r1, \[r1\] +0[0-9a-f]+ <[^>]+> e19eee9f ldaex lr, \[lr\] +0[0-9a-f]+ <[^>]+> e1b00e9f ldaexd r0, r1, \[r0\] +0[0-9a-f]+ <[^>]+> e1b12e9f ldaexd r2, r3, \[r1\] +0[0-9a-f]+ <[^>]+> e1bece9f ldaexd ip, sp, \[lr\] +0[0-9a-f]+ <[^>]+> bf50 sevl +0[0-9a-f]+ <[^>]+> bf50 sevl +0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w +0[0-9a-f]+ <[^>]+> f78f 8001 dcps1 +0[0-9a-f]+ <[^>]+> f78f 8002 dcps2 +0[0-9a-f]+ <[^>]+> f78f 8003 dcps3 +0[0-9a-f]+ <[^>]+> ba80 hlt 0x0000 +0[0-9a-f]+ <[^>]+> babf hlt 0x003f +0[0-9a-f]+ <[^>]+> e8c0 0f8f stlb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 1f8f stlb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce ef8f stlb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 0f9f stlh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 1f9f stlh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce ef9f stlh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 0faf stl r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 1faf stl r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce efaf stl lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8ce 1fc0 stlexb r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 efc1 stlexb r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 0fce stlexb lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce 1fd0 stlexh r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 efd1 stlexh r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 0fde stlexh lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce 1fe0 stlex r0, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 efe1 stlex r1, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 0fee stlex lr, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8ce 11f0 stlexd r0, r1, r1, \[lr\] +0[0-9a-f]+ <[^>]+> e8c0 eef1 stlexd r1, lr, lr, \[r0\] +0[0-9a-f]+ <[^>]+> e8c1 00fe stlexd lr, r0, r0, \[r1\] +0[0-9a-f]+ <[^>]+> e8d0 0f8f ldab r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1f8f ldab r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de ef8f ldab lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0f9f ldah r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1f9f ldah r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de ef9f ldah lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0faf lda r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1faf lda r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efaf lda lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0fcf ldaexb r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1fcf ldaexb r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efcf ldaexb lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0fdf ldaexh r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1fdf ldaexh r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efdf ldaexh lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 0fef ldaex r0, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1fef ldaex r1, \[r1\] +0[0-9a-f]+ <[^>]+> e8de efef ldaex lr, \[lr\] +0[0-9a-f]+ <[^>]+> e8d0 01ff ldaexd r0, r1, \[r0\] +0[0-9a-f]+ <[^>]+> e8d1 1eff ldaexd r1, lr, \[r1\] +0[0-9a-f]+ <[^>]+> e8de e0ff ldaexd lr, r0, \[lr\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/armv8-a.s b/binutils-2.25/gas/testsuite/gas/arm/armv8-a.s new file mode 100644 index 00000000..3217a8a5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/armv8-a.s @@ -0,0 +1,106 @@ + .syntax unified + .text + .arch armv8-a + + .arm +foo: + sevl + hlt 0x0 + hlt 0xf + hlt 0xfff0 + stlb r0, [r0] + stlb r1, [r1] + stlb r14, [r14] + stlh r0, [r0] + stlh r1, [r1] + stlh r14, [r14] + stl r0, [r0] + stl r1, [r1] + stl r14, [r14] + stlexb r0, r1, [r14] + stlexb r1, r14, [r0] + stlexb r14, r0, [r1] + stlexh r0, r1, [r14] + stlexh r1, r14, [r0] + stlexh r14, r0, [r1] + stlex r0, r1, [r14] + stlex r1, r14, [r0] + stlex r14, r0, [r1] + stlexd r0, r2, r3, [r14] + stlexd r1, r12, r13, [r0] + stlexd r14, r0, r1, [r1] + ldab r0, [r0] + ldab r1, [r1] + ldab r14, [r14] + ldah r0, [r0] + ldah r1, [r1] + ldah r14, [r14] + lda r0, [r0] + lda r1, [r1] + lda r14, [r14] + ldaexb r0, [r0] + ldaexb r1, [r1] + ldaexb r14, [r14] + ldaexh r0, [r0] + ldaexh r1, [r1] + ldaexh r14, [r14] + ldaex r0, [r0] + ldaex r1, [r1] + ldaex r14, [r14] + ldaexd r0, r1, [r0] + ldaexd r2, r3, [r1] + ldaexd r12, r13, [r14] + + .thumb + .thumb_func +bar: + sevl + sevl.n + sevl.w + dcps1 + dcps2 + dcps3 + hlt 0 + hlt 63 + stlb r0, [r0] + stlb r1, [r1] + stlb r14, [r14] + stlh r0, [r0] + stlh r1, [r1] + stlh r14, [r14] + stl r0, [r0] + stl r1, [r1] + stl r14, [r14] + stlexb r0, r1, [r14] + stlexb r1, r14, [r0] + stlexb r14, r0, [r1] + stlexh r0, r1, [r14] + stlexh r1, r14, [r0] + stlexh r14, r0, [r1] + stlex r0, r1, [r14] + stlex r1, r14, [r0] + stlex r14, r0, [r1] + stlexd r0, r1, r1, [r14] + stlexd r1, r14, r14, [r0] + stlexd r14, r0, r0, [r1] + ldab r0, [r0] + ldab r1, [r1] + ldab r14, [r14] + ldah r0, [r0] + ldah r1, [r1] + ldah r14, [r14] + lda r0, [r0] + lda r1, [r1] + lda r14, [r14] + ldaexb r0, [r0] + ldaexb r1, [r1] + ldaexb r14, [r14] + ldaexh r0, [r0] + ldaexh r1, [r1] + ldaexh r14, [r14] + ldaex r0, [r0] + ldaex r1, [r1] + ldaex r14, [r14] + ldaexd r0, r1, [r0] + ldaexd r1, r14, [r1] + ldaexd r14, r0, [r14] diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-any-armv4t.d b/binutils-2.25/gas/testsuite/gas/arm/attr-any-armv4t.d new file mode 100644 index 00000000..b578f886 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-any-armv4t.d @@ -0,0 +1,12 @@ +# name: attributes for 'any' cpu v4t ARM insn +# source: attr-any-armv4t.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-any-armv4t.s b/binutils-2.25/gas/testsuite/gas/arm/attr-any-armv4t.s new file mode 100644 index 00000000..290e531d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-any-armv4t.s @@ -0,0 +1 @@ + bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-any-thumbv6.d b/binutils-2.25/gas/testsuite/gas/arm/attr-any-thumbv6.d new file mode 100644 index 00000000..3887341b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-any-thumbv6.d @@ -0,0 +1,11 @@ +# name: attributes for 'any' cpu v6 thumb insn +# source: attr-any-thumbv6.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v6 + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-any-thumbv6.s b/binutils-2.25/gas/testsuite/gas/arm/attr-any-thumbv6.s new file mode 100644 index 00000000..ed019c89 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-any-thumbv6.s @@ -0,0 +1,2 @@ + .thumb + cpy r0, r1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-cpu-directive.d b/binutils-2.25/gas/testsuite/gas/arm/attr-cpu-directive.d new file mode 100644 index 00000000..56f33f5b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-cpu-directive.d @@ -0,0 +1,15 @@ +# name: EABI attributes from directives +# source: attr-cpu-directive.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "Cortex-A8" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-cpu-directive.s b/binutils-2.25/gas/testsuite/gas/arm/attr-cpu-directive.s new file mode 100644 index 00000000..ced1ff41 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-cpu-directive.s @@ -0,0 +1 @@ + .cpu cortex-a8 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-default.d b/binutils-2.25/gas/testsuite/gas/arm/attr-default.d new file mode 100644 index 00000000..635b3d92 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-default.d @@ -0,0 +1,11 @@ +# name: EABI attribute defaults +# source: blank.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-all.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-all.d new file mode 100644 index 00000000..e04d98c9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-all.d @@ -0,0 +1,16 @@ +# name: attributes for -march=all +# source: blank.s +# as: -march=all +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "all" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv1.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv1.d new file mode 100644 index 00000000..ac659774 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv1.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv1 +# source: blank.s +# as: -march=armv1 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "1" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2.d new file mode 100644 index 00000000..0b574efb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv2 +# source: blank.s +# as: -march=armv2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "2" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2a.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2a.d new file mode 100644 index 00000000..387e4a31 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2a.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv2a +# source: blank.s +# as: -march=armv2a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "2A" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2s.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2s.d new file mode 100644 index 00000000..3bd06e62 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv2s.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv2s +# source: blank.s +# as: -march=armv2s +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "2S" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv3.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv3.d new file mode 100644 index 00000000..13d5d183 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv3.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv3 +# source: blank.s +# as: -march=armv3 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "3" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv3m.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv3m.d new file mode 100644 index 00000000..4e243997 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv3m.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv3m +# source: blank.s +# as: -march=armv3m +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "3M" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4.d new file mode 100644 index 00000000..ab08cce2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv4 +# source: blank.s +# as: -march=armv4 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "4" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4t.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4t.d new file mode 100644 index 00000000..1aa0303b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4t.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv4t +# source: blank.s +# as: -march=armv4t +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "4T" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4txm.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4txm.d new file mode 100644 index 00000000..9047d585 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4txm.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv4txm +# source: blank.s +# as: -march=armv4txm +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "4TXM" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4xm.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4xm.d new file mode 100644 index 00000000..be8e22f6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv4xm.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv4xm +# source: blank.s +# as: -march=armv4xm +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "4XM" + Tag_CPU_arch: v4 + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5.d new file mode 100644 index 00000000..1faa9077 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv5 +# source: blank.s +# as: -march=armv5 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "5" + Tag_CPU_arch: v5T + Tag_ARM_ISA_use: Yes diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5t.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5t.d new file mode 100644 index 00000000..e0e528a4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5t.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv5t +# source: blank.s +# as: -march=armv5t +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "5T" + Tag_CPU_arch: v5T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5te.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5te.d new file mode 100644 index 00000000..7618f193 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5te.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv5te +# source: blank.s +# as: -march=armv5te +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "5TE" + Tag_CPU_arch: v5TE + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5tej.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5tej.d new file mode 100644 index 00000000..374bebd4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5tej.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv5tej +# source: blank.s +# as: -march=armv5tej +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "5TEJ" + Tag_CPU_arch: v5TEJ + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5texp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5texp.d new file mode 100644 index 00000000..d52396b7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5texp.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv5texp +# source: blank.s +# as: -march=armv5texp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "5TEXP" + Tag_CPU_arch: v5TE + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5txm.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5txm.d new file mode 100644 index 00000000..4af55ad2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv5txm.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv5txm +# source: blank.s +# as: -march=armv5txm +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "5TXM" + Tag_CPU_arch: v5T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6-m+os.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6-m+os.d new file mode 100644 index 00000000..e766cee4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6-m+os.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6-m+os +# source: blank.s +# as: -march=armv6-m+os +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6-M" + Tag_CPU_arch: v6S-M + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6-m.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6-m.d new file mode 100644 index 00000000..fc0f96fc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6-m.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6-m +# source: blank.s +# as: -march=armv6-m +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6-M" + Tag_CPU_arch: v6-M + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6.d new file mode 100644 index 00000000..369deeca --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6 +# source: blank.s +# as: -march=armv6 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6" + Tag_CPU_arch: v6 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6j.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6j.d new file mode 100644 index 00000000..0175f782 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6j.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6j +# source: blank.s +# as: -march=armv6j +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6J" + Tag_CPU_arch: v6 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6k+sec.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6k+sec.d new file mode 100644 index 00000000..083151f4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6k+sec.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv6k+sec +# source: blank.s +# as: -march=armv6k+sec +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6K" + Tag_CPU_arch: v6KZ + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6k.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6k.d new file mode 100644 index 00000000..9f6d48f3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6k.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6k +# source: blank.s +# as: -march=armv6k +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6K" + Tag_CPU_arch: v6K + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6kt2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6kt2.d new file mode 100644 index 00000000..c5abdacb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6kt2.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6kt2 +# source: blank.s +# as: -march=armv6kt2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6KT2" + Tag_CPU_arch: v6T2 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6s-m.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6s-m.d new file mode 100644 index 00000000..fc0f96fc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6s-m.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6-m +# source: blank.s +# as: -march=armv6-m +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6-M" + Tag_CPU_arch: v6-M + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6t2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6t2.d new file mode 100644 index 00000000..2b63a81f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6t2.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv6t2 +# source: blank.s +# as: -march=armv6t2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6T2" + Tag_CPU_arch: v6T2 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6z.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6z.d new file mode 100644 index 00000000..d1a48d80 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6z.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv6z +# source: blank.s +# as: -march=armv6z +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6Z" + Tag_CPU_arch: v6KZ + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zk.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zk.d new file mode 100644 index 00000000..c1f3722a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zk.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv6zk +# source: blank.s +# as: -march=armv6zk +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6ZK" + Tag_CPU_arch: v6KZ + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zkt2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zkt2.d new file mode 100644 index 00000000..c15de8b3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zkt2.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv6zkt2 +# source: blank.s +# as: -march=armv6zkt2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6ZKT2" + Tag_CPU_arch: v6T2 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zt2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zt2.d new file mode 100644 index 00000000..a21d01a0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv6zt2.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv6zt2 +# source: blank.s +# as: -march=armv6zt2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "6ZT2" + Tag_CPU_arch: v6T2 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d new file mode 100644 index 00000000..3a023c30 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d @@ -0,0 +1,15 @@ +# name: attributes for -march=armv7-a+idiv +# source: blank.s +# as: -march=armv7-a+idiv +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_DIV_use: Allowed in v7-A with integer division extension diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+mp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+mp.d new file mode 100644 index 00000000..b08b9d86 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+mp.d @@ -0,0 +1,15 @@ +# name: attributes for -march=armv7-a+mp +# source: blank.s +# as: -march=armv7-a+mp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d new file mode 100644 index 00000000..f1cf0144 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d @@ -0,0 +1,16 @@ +# name: attributes for -march=armv7-a+sec+virt +# source: blank.s +# as: -march=armv7-a+sec+virt +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_DIV_use: Allowed in v7-A with integer division extension + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+sec.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+sec.d new file mode 100644 index 00000000..69bb928d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+sec.d @@ -0,0 +1,15 @@ +# name: attributes for -march=armv7-a+sec +# source: blank.s +# as: -march=armv7-a+sec +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+virt.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+virt.d new file mode 100644 index 00000000..82f02420 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a+virt.d @@ -0,0 +1,16 @@ +# name: attributes for -march=armv7-a+virt +# source: blank.s +# as: -march=armv7-a+virt +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_DIV_use: Allowed in v7-A with integer division extension + Tag_Virtualization_use: Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a.d new file mode 100644 index 00000000..36267015 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-a.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv7-a +# source: blank.s +# as: -march=armv7-a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-m.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-m.d new file mode 100644 index 00000000..51d6a820 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-m.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv7-m +# source: blank.s +# as: -march=armv7-m +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-M" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-r+mp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-r+mp.d new file mode 100644 index 00000000..00618b35 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-r+mp.d @@ -0,0 +1,15 @@ +# name: attributes for -march=armv7-r+mp +# source: blank.s +# as: -march=armv7-r+mp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-R" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Realtime + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-r.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-r.d new file mode 100644 index 00000000..cf89007d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7-r.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv7-r +# source: blank.s +# as: -march=armv7-r +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7-R" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Realtime + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7.d new file mode 100644 index 00000000..d2252a15 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7.d @@ -0,0 +1,12 @@ +# name: attributes for -march=armv7 +# source: blank.s +# as: -march=armv7 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7" + Tag_CPU_arch: v7 + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7a.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7a.d new file mode 100644 index 00000000..db45e9e6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7a.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv7a +# source: blank.s +# as: -march=armv7a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7A" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7em.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7em.d new file mode 100644 index 00000000..f8e53500 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7em.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv7e-m +# source: blank.s +# as: -march=armv7e-m +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7E-M" + Tag_CPU_arch: v7E-M + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7m.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7m.d new file mode 100644 index 00000000..35c6b241 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7m.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv7m +# source: blank.s +# as: -march=armv7m +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7M" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7r.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7r.d new file mode 100644 index 00000000..33fbad6c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv7r.d @@ -0,0 +1,14 @@ +# name: attributes for -march=armv7r +# source: blank.s +# as: -march=armv7r +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "7R" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Realtime + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d new file mode 100644 index 00000000..776e4140 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+crypto.d @@ -0,0 +1,18 @@ +# name: attributes for -march=armv8-a+crypto +# source: blank.s +# as: -march=armv8-a+crypto +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_Advanced_SIMD_arch: NEON for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d new file mode 100644 index 00000000..a909f715 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+fp.d @@ -0,0 +1,17 @@ +# name: attributes for -march=armv8-a+fp +# source: blank.s +# as: -march=armv8-a+fp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d new file mode 100644 index 00000000..78838c32 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a+simd.d @@ -0,0 +1,18 @@ +# name: attributes for -march=armv8-a+simd +# source: blank.s +# as: -march=armv8-a+simd +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: FP for ARMv8 + Tag_Advanced_SIMD_arch: NEON for ARMv8 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a.d new file mode 100644 index 00000000..fb895969 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-armv8-a.d @@ -0,0 +1,16 @@ +# name: attributes for -march=armv8-a +# source: blank.s +# as: -march=armv8-a +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-A" + Tag_CPU_arch: v8 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-iwmmxt.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-iwmmxt.d new file mode 100644 index 00000000..879e7fcc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-iwmmxt.d @@ -0,0 +1,14 @@ +# name: attributes for -march=iwmmxt +# source: blank.s +# as: -march=iwmmxt +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "iwmmxt" + Tag_CPU_arch: v5TE + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_WMMX_arch: WMMXv1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-iwmmxt2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-iwmmxt2.d new file mode 100644 index 00000000..664bfac1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-iwmmxt2.d @@ -0,0 +1,14 @@ +# name: attributes for -march=iwmmxt2 +# source: blank.s +# as: -march=iwmmxt2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "iwmmxt2" + Tag_CPU_arch: v5TE + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_WMMX_arch: WMMXv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-march-xscale.d b/binutils-2.25/gas/testsuite/gas/arm/attr-march-xscale.d new file mode 100644 index 00000000..da4eaa91 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-march-xscale.d @@ -0,0 +1,13 @@ +# name: attributes for -march=xscale +# source: blank.s +# as: -march=xscale +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "xscale" + Tag_CPU_arch: v5TE + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mcpu.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mcpu.d new file mode 100644 index 00000000..bf1a4e83 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mcpu.d @@ -0,0 +1,17 @@ +# name: EABI attributes from command line +# source: blank.s +# as: -mcpu=cortex-a8 -mfpu=neon +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "Cortex-A8" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: VFPv3 + Tag_Advanced_SIMD_arch: NEONv1 + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1020e.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1020e.d new file mode 100644 index 00000000..c9467a1b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1020e.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=arm1020e +# source: blank.s +# as: -mfpu=arm1020e +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1020t.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1020t.d new file mode 100644 index 00000000..77125814 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1020t.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=arm1020t +# source: blank.s +# as: -mfpu=arm1020t +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1136jf-s.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1136jf-s.d new file mode 100644 index 00000000..7e32c61f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1136jf-s.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=arm1136jf-s +# source: blank.s +# as: -mfpu=arm1136jf-s +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1136jfs.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1136jfs.d new file mode 100644 index 00000000..3eff1e61 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm1136jfs.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=arm1136jfs +# source: blank.s +# as: -mfpu=arm1136jfs +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d new file mode 100644 index 00000000..8279d6f5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-arm7500fe.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=arm7500fe +# source: blank.s +# as: -mfpu=arm7500fe +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa.d new file mode 100644 index 00000000..498d46a2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=fpa +# source: blank.s +# as: -mfpu=fpa +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa10.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa10.d new file mode 100644 index 00000000..73b25f0e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa10.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=fpa10 +# source: blank.s +# as: -mfpu=fpa10 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa11.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa11.d new file mode 100644 index 00000000..4c655f24 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpa11.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=fpa11 +# source: blank.s +# as: -mfpu=fpa11 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe.d new file mode 100644 index 00000000..536acfb1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=fpe +# source: blank.s +# as: -mfpu=fpe +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe2.d new file mode 100644 index 00000000..29638ecf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe2.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=fpe2 +# source: blank.s +# as: -mfpu=fpe2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe3.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe3.d new file mode 100644 index 00000000..9f13b0fb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-fpe3.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=fpe3 +# source: blank.s +# as: -mfpu=fpe3 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-maverick.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-maverick.d new file mode 100644 index 00000000..433245e3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-maverick.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=maverick +# source: blank.s +# as: -mfpu=maverick +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d new file mode 100644 index 00000000..ab729454 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-neon-fp16.d @@ -0,0 +1,14 @@ +# name: attributes for -mfpu=neon-fp16 +# source: blank.s +# as: -mfpu=neon-fp16 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 + Tag_Advanced_SIMD_arch: NEONv1 + Tag_FP_HP_extension: Allowed diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-neon.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-neon.d new file mode 100644 index 00000000..1bc1054d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-neon.d @@ -0,0 +1,13 @@ +# name: attributes for -mfpu=neon +# source: blank.s +# as: -mfpu=neon +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 + Tag_Advanced_SIMD_arch: NEONv1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softfpa.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softfpa.d new file mode 100644 index 00000000..8eb432b4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softfpa.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=softfpa +# source: blank.s +# as: -mfpu=softfpa +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softvfp+vfp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softvfp+vfp.d new file mode 100644 index 00000000..92b7d418 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softvfp+vfp.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=softvfp+vfp +# source: blank.s +# as: -mfpu=softvfp+vfp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softvfp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softvfp.d new file mode 100644 index 00000000..edff4c38 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-softvfp.d @@ -0,0 +1,11 @@ +# name: attributes for -mfpu=softvfp +# source: blank.s +# as: -mfpu=softvfp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp.d new file mode 100644 index 00000000..3ba2be52 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfp +# source: blank.s +# as: -mfpu=vfp +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp10-r0.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp10-r0.d new file mode 100644 index 00000000..0c413e6c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp10-r0.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfp10-r0 +# source: blank.s +# as: -mfpu=vfp10-r0 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp10.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp10.d new file mode 100644 index 00000000..62e30026 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp10.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfp10 +# source: blank.s +# as: -mfpu=vfp10 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp3.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp3.d new file mode 100644 index 00000000..5b084028 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp3.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfp3 +# source: blank.s +# as: -mfpu=vfp3 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp9.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp9.d new file mode 100644 index 00000000..4ffa91d9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfp9.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfp9 +# source: blank.s +# as: -mfpu=vfp9 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv2.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv2.d new file mode 100644 index 00000000..c0a0a96d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv2.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfpv2 +# source: blank.s +# as: -mfpu=vfpv2 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv3-d16.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv3-d16.d new file mode 100644 index 00000000..5ed90d57 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv3-d16.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfpv3-d16 +# source: blank.s +# as: -mfpu=vfpv3-d16 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3-D16 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv3.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv3.d new file mode 100644 index 00000000..7b63286b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv3.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfpv3 +# source: blank.s +# as: -mfpu=vfpv3 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d new file mode 100644 index 00000000..a749d7b1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv4-d16.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfpv4-d16 +# source: blank.s +# as: -mfpu=vfpv4-d16 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4-D16 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d new file mode 100644 index 00000000..e00a3d93 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpv4.d @@ -0,0 +1,12 @@ +# name: attributes for -mfpu=vfpv4 +# source: blank.s +# as: -mfpu=vfpv4 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpxd.d b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpxd.d new file mode 100644 index 00000000..2b241715 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-mfpu-vfpxd.d @@ -0,0 +1,13 @@ +# name: attributes for -mfpu=vfpxd +# source: blank.s +# as: -mfpu=vfpxd +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv1 + Tag_ABI_HardFP_use: SP only diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-names.d b/binutils-2.25/gas/testsuite/gas/arm/attr-names.d new file mode 100644 index 00000000..56e4a7a3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-names.d @@ -0,0 +1,48 @@ +# name: EABI attribute names +# source: attr-names.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_conformance: "2.08" + Tag_nodefaults: True + Tag_CPU_raw_name: "random-cpu" + Tag_CPU_name: "cpu" + Tag_CPU_arch: v4 + Tag_CPU_arch_profile: Application or Realtime + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv1 + Tag_WMMX_arch: WMMXv1 + Tag_Advanced_SIMD_arch: NEONv1 + Tag_PCS_config: Bare platform + Tag_ABI_PCS_R9_use: SB + Tag_ABI_PCS_RW_data: PC-relative + Tag_ABI_PCS_RO_data: PC-relative + Tag_ABI_PCS_GOT_use: direct + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_rounding: Needed + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_user_exceptions: Needed + Tag_ABI_FP_number_model: Finite + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_HardFP_use: SP only + Tag_ABI_VFP_args: VFP registers + Tag_ABI_WMMX_args: WMMX registers + Tag_ABI_optimization_goals: Prefer Speed + Tag_ABI_FP_optimization_goals: Prefer Speed + Tag_compatibility: flag = 1, vendor = gnu + Tag_CPU_unaligned_access: v6 + Tag_FP_HP_extension: Allowed + Tag_ABI_FP_16bit_format: IEEE 754 + Tag_MPextension_use: Allowed + Tag_DIV_use: Not allowed + Tag_also_compatible_with: v6-M + Tag_T2EE_use: Allowed + Tag_Virtualization_use: TrustZone and Virtualization Extensions diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-names.s b/binutils-2.25/gas/testsuite/gas/arm/attr-names.s new file mode 100644 index 00000000..c43fb88f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-names.s @@ -0,0 +1,43 @@ +.eabi_attribute Tag_CPU_raw_name, "random-cpu" +.eabi_attribute Tag_CPU_name, "cpu" +.eabi_attribute Tag_CPU_arch, 1 +.eabi_attribute Tag_CPU_arch_profile, 'S' +.eabi_attribute Tag_ARM_ISA_use, 1 +.eabi_attribute Tag_THUMB_ISA_use, 1 +.eabi_attribute Tag_FP_arch, 1 +.eabi_attribute Tag_VFP_arch, 1 +.eabi_attribute Tag_WMMX_arch, 1 +.eabi_attribute Tag_Advanced_SIMD_arch, 1 +.eabi_attribute Tag_PCS_config, 1 +.eabi_attribute Tag_ABI_PCS_R9_use, 1 +.eabi_attribute Tag_ABI_PCS_RW_data, 1 +.eabi_attribute Tag_ABI_PCS_RO_data, 1 +.eabi_attribute Tag_ABI_PCS_GOT_use, 1 +.eabi_attribute Tag_ABI_PCS_wchar_t, 2 +.eabi_attribute Tag_ABI_FP_rounding, 1 +.eabi_attribute Tag_ABI_FP_denormal, 1 +.eabi_attribute Tag_ABI_FP_exceptions, 1 +.eabi_attribute Tag_ABI_FP_user_exceptions, 1 +.eabi_attribute Tag_ABI_FP_number_model, 1 +.eabi_attribute Tag_ABI_align_needed, 1 +.eabi_attribute Tag_ABI_align8_needed, 1 +.eabi_attribute Tag_ABI_align_preserved, 1 +.eabi_attribute Tag_ABI_align8_preserved, 1 +.eabi_attribute Tag_ABI_enum_size, 1 +.eabi_attribute Tag_ABI_HardFP_use, 1 +.eabi_attribute Tag_ABI_VFP_args, 1 +.eabi_attribute Tag_ABI_WMMX_args, 1 +.eabi_attribute Tag_ABI_optimization_goals, 1 +.eabi_attribute Tag_ABI_FP_optimization_goals, 1 +.eabi_attribute Tag_compatibility, 1, "gnu" +.eabi_attribute Tag_CPU_unaligned_access, 1 +.eabi_attribute Tag_FP_HP_extension, 1 +.eabi_attribute Tag_VFP_HP_extension, 1 +.eabi_attribute Tag_ABI_FP_16bit_format, 1 +.eabi_attribute Tag_MPextension_use, 1 +.eabi_attribute Tag_DIV_use, 1 +.eabi_attribute Tag_nodefaults, 0 +.eabi_attribute Tag_also_compatible_with, "\06\013" +.eabi_attribute Tag_conformance, "2.08" +.eabi_attribute Tag_T2EE_use, 1 +.eabi_attribute Tag_Virtualization_use, 3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-order.d b/binutils-2.25/gas/testsuite/gas/arm/attr-order.d new file mode 100644 index 00000000..56a192f0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-order.d @@ -0,0 +1,19 @@ +# name: EABI attribute ordering +# source: attr-order.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_conformance: "2.07" + Tag_nodefaults: True + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_unknown_63: "val" + Tag_also_compatible_with: v6-M + Tag_T2EE_use: Allowed + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-order.s b/binutils-2.25/gas/testsuite/gas/arm/attr-order.s new file mode 100644 index 00000000..10eb3a35 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-order.s @@ -0,0 +1,9 @@ +@ This test ensures that the following attributes +@ are emitted in the proper order. + .cpu arm7tdmi + .eabi_attribute 63, "val" + .eabi_attribute Tag_nodefaults, 0 + .eabi_attribute Tag_also_compatible_with, "\006\013" + .eabi_attribute Tag_T2EE_use, 1 + .eabi_attribute Tag_conformance, "2.07" + .eabi_attribute Tag_Virtualization_use, 1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-override-cpu-directive.d b/binutils-2.25/gas/testsuite/gas/arm/attr-override-cpu-directive.d new file mode 100644 index 00000000..a8705848 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-override-cpu-directive.d @@ -0,0 +1,12 @@ +# name: EABI attributes .eabi_attribute overrides .cpu +# source: attr-override-cpu-directive.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "custom name" + Tag_CPU_arch: v7 + Tag_THUMB_ISA_use: \?\?\? \(10\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-override-cpu-directive.s b/binutils-2.25/gas/testsuite/gas/arm/attr-override-cpu-directive.s new file mode 100644 index 00000000..21a28122 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-override-cpu-directive.s @@ -0,0 +1,5 @@ + .cpu arm7tdmi + .eabi_attribute Tag_CPU_name, "custom name" + .eabi_attribute Tag_CPU_arch, 10 + .eabi_attribute Tag_ARM_ISA_use, 0 + .eabi_attribute Tag_THUMB_ISA_use, 10 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-override-mcpu.d b/binutils-2.25/gas/testsuite/gas/arm/attr-override-mcpu.d new file mode 100644 index 00000000..316b88e0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-override-mcpu.d @@ -0,0 +1,13 @@ +# name: EABI attributes .cpu overrides -mcpu +# source: attr-override-mcpu.s +# as: -mcpu=cortex-a8 +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-override-mcpu.s b/binutils-2.25/gas/testsuite/gas/arm/attr-override-mcpu.s new file mode 100644 index 00000000..bc7a04c8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-override-mcpu.s @@ -0,0 +1,2 @@ + .cpu arm7tdmi + .fpu softfpa diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-syntax.d b/binutils-2.25/gas/testsuite/gas/arm/attr-syntax.d new file mode 100644 index 00000000..894b8293 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-syntax.d @@ -0,0 +1,4 @@ +#source: attr-syntax.s +#not-target: *-*-pe *-*-aout +#as: +#error: :1: Error: Attribute name not recognised: made_up_tag.*:3: Error: expected <tag> , <value>.*:5: Error: expected <tag> , <value> diff --git a/binutils-2.25/gas/testsuite/gas/arm/attr-syntax.s b/binutils-2.25/gas/testsuite/gas/arm/attr-syntax.s new file mode 100644 index 00000000..52c84503 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/attr-syntax.s @@ -0,0 +1,6 @@ +.eabi_attribute made_up_tag, 11 +.eabi_attribute 12, 3 +.eabi_attribute , 2 +.eabi_attribute Tag_CPU_name, "hi" +.eabi_attribute 10asdf, 3 +.eabi_attribute Tag_ABI_align8_needed, 1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/backslash-at.d b/binutils-2.25/gas/testsuite/gas/arm/backslash-at.d new file mode 100644 index 00000000..c87965f4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/backslash-at.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Backslash-at for ARM + +.*: file format .*arm.* + +Disassembly of section .text: +0+000 <.*>.*615c.* +0+002 <foo> e3a00000 mov r0, #0 +0+006 <foo\+0x4> e3a00000 mov r0, #0 +0+00a <foo\+0x8> e3a00000 mov r0, #0 +0+00e <foo\+0xc> e3a00001 mov r0, #1 +0+012 <foo\+0x10> e3a00001 mov r0, #1 +0+016 <foo\+0x14> e3a00001 mov r0, #1 +0+01a <foo\+0x18> e3a00002 mov r0, #2 +0+01e <foo\+0x1c> e3a00002 mov r0, #2 +0+022 <foo\+0x20> e3a00002 mov r0, #2 +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/backslash-at.s b/binutils-2.25/gas/testsuite/gas/arm/backslash-at.s new file mode 100644 index 00000000..4975aea6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/backslash-at.s @@ -0,0 +1,16 @@ +@ Check that \@ is not destroyed when assembling for the ARM. + +.macro bar + mov r0, #\@ + mov r0, #\@@comment + mov r0, #\@ @comment +.endm + +.byte '\\ +.byte '\a + +foo: + bar + bar + bar + diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier-bad-thumb.d b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad-thumb.d new file mode 100644 index 00000000..384b7ef8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad-thumb.d @@ -0,0 +1,5 @@ +#name: Bad barrier options (Thumb) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#source: barrier-bad.s +#as: -mthumb +#error-output: barrier-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.d b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.d new file mode 100644 index 00000000..6e19717f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.d @@ -0,0 +1,3 @@ +#name: Bad barrier options (ARM) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#error-output: barrier-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.l b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.l new file mode 100644 index 00000000..fc91fd22 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.l @@ -0,0 +1,11 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: invalid barrier type -- `isb st' +[^:]*:4: Error: invalid barrier type -- `isb ish' +[^:]*:5: Error: invalid barrier type -- `isb ishst' +[^:]*:6: Error: invalid barrier type -- `isb nsh' +[^:]*:7: Error: invalid barrier type -- `isb nshst' +[^:]*:8: Error: invalid barrier type -- `isb osh' +[^:]*:9: Error: invalid barrier type -- `isb oshst' +[^:]*:10: Error: immediate value out of range -- `isb #23' +[^:]*:11: Error: invalid barrier type -- `dsb xyz' +[^:]*:12: Error: immediate value out of range -- `dsb #34' diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.s b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.s new file mode 100644 index 00000000..fb7dfb8b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier-bad.s @@ -0,0 +1,12 @@ +.syntax unified +.arch armv7a +isb st +isb ish +isb ishst +isb nsh +isb nshst +isb osh +isb oshst +isb #23 +dsb xyz +dsb #34 diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier-thumb.d b/binutils-2.25/gas/testsuite/gas/arm/barrier-thumb.d new file mode 100644 index 00000000..59299469 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier-thumb.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Barrier Instruction Operands (Thumb) +#source: barrier.s +#as: -mcpu=cortex-a8 -mthumb +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd + +# Test Barrier Instruction Operands + +.*: *file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> f3bf 8f5f dmb (sy|#15) +00000004 <[^>]*> f3bf 8f5e dmb (st|#14) +00000008 <[^>]*> f3bf 8f5b dmb (sh|ish|#11) +0000000c <[^>]*> f3bf 8f5b dmb (sh|ish|#11) +00000010 <[^>]*> f3bf 8f5a dmb (ishst|shst|#10) +00000014 <[^>]*> f3bf 8f5a dmb (ishst|shst|#10) +00000018 <[^>]*> f3bf 8f57 dmb (un|nsh|#7) +0000001c <[^>]*> f3bf 8f57 dmb (un|nsh|#7) +00000020 <[^>]*> f3bf 8f56 dmb (unst|nshst|#6) +00000024 <[^>]*> f3bf 8f56 dmb (unst|nshst|#6) +00000028 <[^>]*> f3bf 8f53 dmb (osh|#3) +0000002c <[^>]*> f3bf 8f52 dmb (oshst|#2) +00000030 <[^>]*> f3bf 8f4f dsb (sy|#15) +00000034 <[^>]*> f3bf 8f4e dsb (st|#14) +00000038 <[^>]*> f3bf 8f4b dsb (sh|ish|#11) +0000003c <[^>]*> f3bf 8f4b dsb (sh|ish|#11) +00000040 <[^>]*> f3bf 8f4a dsb (ishst|ish|#10) +00000044 <[^>]*> f3bf 8f4a dsb (ishst|ish|#10) +00000048 <[^>]*> f3bf 8f47 dsb (un|nsh|#7) +0000004c <[^>]*> f3bf 8f47 dsb (un|nsh|#7) +00000050 <[^>]*> f3bf 8f46 dsb (nshst|unst|#6) +00000054 <[^>]*> f3bf 8f46 dsb (nshst|unst|#6) +00000058 <[^>]*> f3bf 8f43 dsb (osh|#3) +0000005c <[^>]*> f3bf 8f6f isb (sy|#15) +00000060 <[^>]*> f3bf 8f6f isb (sy|#15) +00000064 <[^>]*> f3bf 8f5f dmb (sy|#15) +00000068 <[^>]*> f3bf 8f5e dmb (st|#14) +0000006c <[^>]*> f3bf 8f5b dmb (sh|ish|#11) +00000070 <[^>]*> f3bf 8f5b dmb (sh|ish|#11) +00000074 <[^>]*> f3bf 8f5a dmb (ishst|shst|#10) +00000078 <[^>]*> f3bf 8f5a dmb (ishst|shst|#10) +0000007c <[^>]*> f3bf 8f57 dmb (un|nsh|#7) +00000080 <[^>]*> f3bf 8f57 dmb (un|nsh|#7) +00000084 <[^>]*> f3bf 8f56 dmb (unst|nshst|#6) +00000088 <[^>]*> f3bf 8f56 dmb (unst|nshst|#6) +0000008c <[^>]*> f3bf 8f53 dmb (osh|#3) +00000090 <[^>]*> f3bf 8f52 dmb (oshst|#2) +00000094 <[^>]*> f3bf 8f4f dsb (sy|#15) +00000098 <[^>]*> f3bf 8f4e dsb (st|#14) +0000009c <[^>]*> f3bf 8f4b dsb (sh|ish|#11) +000000a0 <[^>]*> f3bf 8f4b dsb (sh|ish|#11) +000000a4 <[^>]*> f3bf 8f4a dsb (ishst|ish|#10) +000000a8 <[^>]*> f3bf 8f4a dsb (ishst|ish|#10) +000000ac <[^>]*> f3bf 8f47 dsb (un|nsh|#7) +000000b0 <[^>]*> f3bf 8f47 dsb (un|nsh|#7) +000000b4 <[^>]*> f3bf 8f46 dsb (nshst|unst|#6) +000000b8 <[^>]*> f3bf 8f46 dsb (nshst|unst|#6) +000000bc <[^>]*> f3bf 8f43 dsb (osh|#3) +000000c0 <[^>]*> f3bf 8f6f isb (sy|#15) +000000c4 <[^>]*> f3bf 8f40 dsb #0 +000000c8 <[^>]*> f3bf 8f4f dsb (sy|#15) +000000cc <[^>]*> f3bf 8f50 dmb #0 +000000d0 <[^>]*> f3bf 8f5f dmb (sy|#15) +000000d4 <[^>]*> f3bf 8f60 isb #0 +000000d8 <[^>]*> f3bf 8f6e isb #14 +000000dc <[^>]*> f3bf 8f6b isb #11 +000000e0 <[^>]*> f3bf 8f6a isb #10 +000000e4 <[^>]*> f3bf 8f67 isb #7 +000000e8 <[^>]*> f3bf 8f66 isb #6 +000000ec <[^>]*> f3bf 8f63 isb #3 +000000f0 <[^>]*> f3bf 8f62 isb #2 +000000f4 <[^>]*> f3bf 8f6f isb (sy|#15) diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier.d b/binutils-2.25/gas/testsuite/gas/arm/barrier.d new file mode 100644 index 00000000..972a5111 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier.d @@ -0,0 +1,73 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Barrier Instruction Operands +#as: -mcpu=cortex-a8 +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd + +# Test Barrier Instruction Operands + +.*: *file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> f57ff05f dmb (sy|#15) +00000004 <[^>]*> f57ff05e dmb (st|#14) +00000008 <[^>]*> f57ff05b dmb (sh|ish|#11) +0000000c <[^>]*> f57ff05b dmb (sh|ish|#11) +00000010 <[^>]*> f57ff05a dmb (ishst|shst|#10) +00000014 <[^>]*> f57ff05a dmb (ishst|shst|#10) +00000018 <[^>]*> f57ff057 dmb (un|nsh|#7) +0000001c <[^>]*> f57ff057 dmb (un|nsh|#7) +00000020 <[^>]*> f57ff056 dmb (unst|nshst|#6) +00000024 <[^>]*> f57ff056 dmb (unst|nshst|#6) +00000028 <[^>]*> f57ff053 dmb (osh|#3) +0000002c <[^>]*> f57ff052 dmb (oshst|#2) +00000030 <[^>]*> f57ff04f dsb (sy|#15) +00000034 <[^>]*> f57ff04e dsb (st|#14) +00000038 <[^>]*> f57ff04b dsb (sh|ish|#11) +0000003c <[^>]*> f57ff04b dsb (sh|ish|#11) +00000040 <[^>]*> f57ff04a dsb (ishst|ish|#10) +00000044 <[^>]*> f57ff04a dsb (ishst|ish|#10) +00000048 <[^>]*> f57ff047 dsb (un|nsh|#7) +0000004c <[^>]*> f57ff047 dsb (un|nsh|#7) +00000050 <[^>]*> f57ff046 dsb (nshst|unst|#6) +00000054 <[^>]*> f57ff046 dsb (nshst|unst|#6) +00000058 <[^>]*> f57ff043 dsb (osh|#3) +0000005c <[^>]*> f57ff06f isb (sy|#15) +00000060 <[^>]*> f57ff06f isb (sy|#15) +00000064 <[^>]*> f57ff05f dmb (sy|#15) +00000068 <[^>]*> f57ff05e dmb (st|#14) +0000006c <[^>]*> f57ff05b dmb (sh|ish|#11) +00000070 <[^>]*> f57ff05b dmb (sh|ish|#11) +00000074 <[^>]*> f57ff05a dmb (ishst|shst|#10) +00000078 <[^>]*> f57ff05a dmb (ishst|shst|#10) +0000007c <[^>]*> f57ff057 dmb (un|nsh|#7) +00000080 <[^>]*> f57ff057 dmb (un|nsh|#7) +00000084 <[^>]*> f57ff056 dmb (unst|nshst|#6) +00000088 <[^>]*> f57ff056 dmb (unst|nshst|#6) +0000008c <[^>]*> f57ff053 dmb (osh|#3) +00000090 <[^>]*> f57ff052 dmb (oshst|#2) +00000094 <[^>]*> f57ff04f dsb (sy|#15) +00000098 <[^>]*> f57ff04e dsb (st|#14) +0000009c <[^>]*> f57ff04b dsb (sh|ish|#11) +000000a0 <[^>]*> f57ff04b dsb (sh|ish|#11) +000000a4 <[^>]*> f57ff04a dsb (ishst|ish|#10) +000000a8 <[^>]*> f57ff04a dsb (ishst|ish|#10) +000000ac <[^>]*> f57ff047 dsb (un|nsh|#7) +000000b0 <[^>]*> f57ff047 dsb (un|nsh|#7) +000000b4 <[^>]*> f57ff046 dsb (nshst|unst|#6) +000000b8 <[^>]*> f57ff046 dsb (nshst|unst|#6) +000000bc <[^>]*> f57ff043 dsb (osh|#3) +000000c0 <[^>]*> f57ff06f isb (sy|#15) +000000c4 <[^>]*> f57ff040 dsb #0 +000000c8 <[^>]*> f57ff04f dsb (sy|#15) +000000cc <[^>]*> f57ff050 dmb #0 +000000d0 <[^>]*> f57ff05f dmb (sy|#15) +000000d4 <[^>]*> f57ff060 isb #0 +000000d8 <[^>]*> f57ff06e isb #14 +000000dc <[^>]*> f57ff06b isb #11 +000000e0 <[^>]*> f57ff06a isb #10 +000000e4 <[^>]*> f57ff067 isb #7 +000000e8 <[^>]*> f57ff066 isb #6 +000000ec <[^>]*> f57ff063 isb #3 +000000f0 <[^>]*> f57ff062 isb #2 +000000f4 <[^>]*> f57ff06f isb (sy|#15) diff --git a/binutils-2.25/gas/testsuite/gas/arm/barrier.s b/binutils-2.25/gas/testsuite/gas/arm/barrier.s new file mode 100644 index 00000000..a4574e8a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/barrier.s @@ -0,0 +1,74 @@ +@ Test case to validate barrier instruction operands +.section .text +.syntax unified + @Tests to verify dsb, dmb and isb operand acceptance + dmb sy + dmb st + dmb ish + dmb sh + dmb ishst + dmb shst + dmb nsh + dmb un + dmb nshst + dmb unst + dmb osh + dmb oshst + dsb sy + dsb st + dsb ish + dsb sh + dsb ishst + dsb shst + dsb nsh + dsb un + dsb nshst + dsb unst + dsb osh + isb sy + isb + + @Sanity checks for operands in upper case + dmb SY + dmb ST + dmb ISH + dmb SH + dmb ISHST + dmb SHST + dmb NSH + dmb UN + dmb NSHST + dmb UNST + dmb OSH + dmb OSHST + dsb SY + dsb ST + dsb ISH + dsb SH + dsb ISHST + dsb SHST + dsb NSH + dsb UN + dsb NSHST + dsb UNST + dsb OSH + isb SY + + @Tests to verify immediate operands + dsb 0 + dsb #15 + + dmb 0 + dmb #15 + + isb 0 + isb #14 + isb #11 + isb #10 + isb #7 + isb #6 + isb #3 + isb #2 + + isb #15 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/bignum1.d b/binutils-2.25/gas/testsuite/gas/arm/bignum1.d new file mode 100644 index 00000000..cef2036c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bignum1.d @@ -0,0 +1,12 @@ +# name: bignums +# as: +# objdump: --full-contents +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Contents of section .data: + 0000 [08]0000000 000000[08]0 11111111 11111111 \.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\. +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/bignum1.s b/binutils-2.25/gas/testsuite/gas/arm/bignum1.s new file mode 100644 index 00000000..2b9d7364 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bignum1.s @@ -0,0 +1,3 @@ + .data + .8byte -9223372036854775808 + .8byte 1229782938247303441 diff --git a/binutils-2.25/gas/testsuite/gas/arm/bl-local-2.d b/binutils-2.25/gas/testsuite/gas/arm/bl-local-2.d new file mode 100644 index 00000000..da7a49b6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bl-local-2.d @@ -0,0 +1,21 @@ +#name: bl local conversion to blx +#objdump: -drw --prefix-addresses --show-raw-insn +#as: + + +.*: file format .* + + +Disassembly of section \.text: +0+00 <[^>]+> e12fff1e bx lr +0+04 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+06 <[^>]+> f7ff effc blx 0+ <myfunction> +0+0a <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0c <[^>]+> f7ff eff8 blx 0+ <myfunction> +0+10 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+12 <[^>]+> f7ff eff6 blx 0+ <myfunction> +0+16 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+18 <[^>]+> f7ff eff2 blx 0+ <myfunction> +0+1c <[^>]+> 4770 bx lr +0+1e <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+20 <[^>]+> fafffffd blx 0000001c <mythumbfunction> diff --git a/binutils-2.25/gas/testsuite/gas/arm/bl-local-2.s b/binutils-2.25/gas/testsuite/gas/arm/bl-local-2.s new file mode 100644 index 00000000..d79c5ed4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bl-local-2.s @@ -0,0 +1,41 @@ + .arch armv5te + + .text + .align 2 + .code 32 + .type myfunction, %function +myfunction: + bx r14 + + .text + .align 2 + .code 16 + .thumb_func + .global caller + .type caller, %function +caller: + nop + bl myfunction + nop + bl myfunction + nop + bl myfunction + nop + bl myfunction + + .text + .align 2 + .code 16 + .type mythumbfunction, %function + .thumb_func +mythumbfunction: + bx r14 + + .text + .align 2 + .code 32 + .global armcaller + .type armcaller, %function +armcaller: + bl mythumbfunction + diff --git a/binutils-2.25/gas/testsuite/gas/arm/bl-local-v4t.d b/binutils-2.25/gas/testsuite/gas/arm/bl-local-v4t.d new file mode 100644 index 00000000..959f6b2b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bl-local-v4t.d @@ -0,0 +1,19 @@ +#name: bl local instructions for v4t. +#objdump: -drw --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-elf +#as: +# stderr: blx-local-thumb.l + +.*: +file format .*arm.* +Disassembly of section .text: +0+00 <[^>]*> f7ff fffe bl 00+18 <[^>]*> 0: R_ARM_THM_CALL foo2 +0+04 <[^>]*> d004 beq.n 00+10 <[^>]*> +0+06 <[^>]*> e003 b.n 00+10 <[^>]*> +0+08 <[^>]*> f000 f808 bl 00+1c <[^>]*> +0+0c <[^>]*> f000 f802 bl 00+14 <[^>]*> +0+10 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+12 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+14 <[^>]*> 46c0 nop ; \(mov r8, r8\) + ... +0+18 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+1c <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/bl-local-v4t.s b/binutils-2.25/gas/testsuite/gas/arm/bl-local-v4t.s new file mode 100644 index 00000000..49353441 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bl-local-v4t.s @@ -0,0 +1,25 @@ + .text + .arch armv4t + .syntax unified + .thumb +one: + bl foo2 @ bl foo2 with reloc. + beq foo @ beq foo with reloc. + b foo @ branch foo with reloc. + bl fooundefarm + bl fooundefthumb + .thumb + .type foo, %function + .thumb_func +foo: + nop + nop +fooundefthumb: + nop + .type foo2, %function + .arm + .align 2 +foo2: + nop +fooundefarm: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/blank.s b/binutils-2.25/gas/testsuite/gas/arm/blank.s new file mode 100644 index 00000000..1d220541 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blank.s @@ -0,0 +1 @@ +@ this file left intentionally blank diff --git a/binutils-2.25/gas/testsuite/gas/arm/blx-bad.d b/binutils-2.25/gas/testsuite/gas/arm/blx-bad.d new file mode 100644 index 00000000..9e52d5b8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blx-bad.d @@ -0,0 +1,24 @@ +#objdump: -drw --show-raw-insn +#name: BLX encoding +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: file format .*arm.* + + +Disassembly of section .text: + +00000000 <ARM>: + 0: e1a00000 nop ; \(mov r0, r0\) + +00000004 <THUMB>: + 4: f7ff effc blx 0 <ARM> + 8: 46c0 nop ; \(mov r8, r8\) + a: f7ff effa blx 0 <ARM> + e: 46c0 nop ; \(mov r8, r8\) + 10: f7ff eff6 blx 0 <ARM> + 14: f7ff eff5 ; <UNDEFINED> instruction: 0xf7ffeff5 + 18: 46c0 nop ; \(mov r8, r8\) + 1a: f7ff eff1 ; <UNDEFINED> instruction: 0xf7ffeff1 + 1e: f7ff eff0 blx 0 <ARM> + 22: 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/blx-bad.s b/binutils-2.25/gas/testsuite/gas/arm/blx-bad.s new file mode 100644 index 00000000..cbc9c537 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blx-bad.s @@ -0,0 +1,16 @@ + .arm + .func ARM +ARM: nop + + .thumb + .thumb_func +THUMB: + blx ARM + nop + blx ARM + nop + .inst 0xf7ffeff6 + .inst 0xf7ffeff5 + nop + .inst 0xf7ffeff1 + .inst 0xf7ffeff0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/blx-local-thumb.l b/binutils-2.25/gas/testsuite/gas/arm/blx-local-thumb.l new file mode 100644 index 00000000..588674c1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blx-local-thumb.l @@ -0,0 +1,2 @@ +[^;]*: Assembler messages: +[^;]*:6: Warning: blx to Thumb func 'foo' from Thumb ISA state changed to bl
\ No newline at end of file diff --git a/binutils-2.25/gas/testsuite/gas/arm/blx-local.d b/binutils-2.25/gas/testsuite/gas/arm/blx-local.d new file mode 100644 index 00000000..2f9a90df --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blx-local.d @@ -0,0 +1,29 @@ +#name: Local BLX instructions +#objdump: -drw --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-elf +#as: +# stderr: blx-local.l +# Test assembler resolution of blx and bl instructions in ARM mode. +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> fa000006 blx 00000020 <foo> +0+04 <[^>]*> eb000007 bl 00000028 <foo2> +0+08 <[^>]*> fa000004 blx 00000020 <foo> +0+0c <[^>]*> eb000005 bl 00000028 <foo2> +0+10 <[^>]*> fa00000b blx 00000044 <fooundefarm> +0+14 <[^>]*> eb00000a bl 00000044 <fooundefarm> +0+18 <[^>]*> fa000001 blx 00000024 <fooundefthumb> +0+1c <[^>]*> eb000000 bl 00000024 <fooundefthumb> +0+20 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+22 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+24 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+26 <[^>]*> 46c0 nop ; \(mov r8, r8\) +0+28 <[^>]*> 0bfffffd bleq 00000024 <fooundefthumb> +0+2c <[^>]*> 0afffffc beq 00000024 <fooundefthumb> +0+30 <[^>]*> eafffffb b 00000024 <fooundefthumb> +0+34 <[^>]*> 0bfffffe bleq 00000020 <foo> 34: R_ARM_JUMP24 foo +0+38 <[^>]*> 0afffffe beq 00000020 <foo> 38: R_ARM_JUMP24 foo +0+3c <[^>]*> eafffffe b 00000020 <foo> 3c: R_ARM_JUMP24 foo +0+40 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+44 <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/blx-local.l b/binutils-2.25/gas/testsuite/gas/arm/blx-local.l new file mode 100644 index 00000000..fcca4646 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blx-local.l @@ -0,0 +1,3 @@ +[^;]*: Assembler messages: +[^;]*:9: Warning: blx to 'foo2' an ARM ISA state function changed to bl + diff --git a/binutils-2.25/gas/testsuite/gas/arm/blx-local.s b/binutils-2.25/gas/testsuite/gas/arm/blx-local.s new file mode 100644 index 00000000..ed587c9e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/blx-local.s @@ -0,0 +1,38 @@ +# objdump: -fdrw --prefix-addresses --show-raw-insn +# not-target: *-*-*aout* *-*-pe + + .text + .arch armv5t + .arm +one: + blx foo + blx foo2 + bl foo + bl foo2 + blx fooundefarm + bl fooundefarm + blx fooundefthumb + bl fooundefthumb + + .thumb + .type foo, %function + .thumb_func +foo: + nop + nop +fooundefthumb: + nop + + .align 2 + .type foo2, %function + .arm +foo2: + bleq fooundefthumb @no relocs + beq fooundefthumb @no relocs + b fooundefthumb @no relocs + bleq foo @ R_ARM_PCREL_JUMP + beq foo @ R_ARM_PCREL_JUMP + b foo @ R_ARM_PCREL_JUMP + nop +fooundefarm: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.d b/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.d new file mode 100644 index 00000000..6ba322e5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.d @@ -0,0 +1,89 @@ +#name: Inter-section branch relocations +#This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#as: -march=armv5t +#objdump: -rd +#stderr: branch-reloc.l + +# Test the generation of relocation for inter-section branches + +.*: +file format.*arm.* + + +Disassembly of section .text: + +00000000 <arm_glob_sym1-0x4>: + 0: e1a00000 nop ; \(mov r0, r0\) + +00000004 <arm_glob_sym1>: + 4: ebfffffe bl 46 <thumb_glob_sym1> + 4: R_ARM_CALL thumb_glob_sym1 + 8: ebfffffe bl 100 <thumb_glob_sym2> + 8: R_ARM_CALL thumb_glob_sym2 + c: fa00000c blx 44 <thumb_sym1> + 10: ebfffffe bl 4 <arm_glob_sym1> + 10: R_ARM_CALL arm_glob_sym1 + 14: ebfffffe bl 13c <arm_glob_sym2> + 14: R_ARM_CALL arm_glob_sym2 + 18: eb000007 bl 3c <arm_sym1> + 1c: fafffffe blx 46 <thumb_glob_sym1> + 1c: R_ARM_CALL thumb_glob_sym1 + 20: fafffffe blx 100 <thumb_glob_sym2> + 20: R_ARM_CALL thumb_glob_sym2 + 24: fa000006 blx 44 <thumb_sym1> + 28: fafffffe blx 4 <arm_glob_sym1> + 28: R_ARM_CALL arm_glob_sym1 + 2c: fafffffe blx 13c <arm_glob_sym2> + 2c: R_ARM_CALL arm_glob_sym2 + 30: eb000001 bl 3c <arm_sym1> + 34: e1a00000 nop ; \(mov r0, r0\) + 38: e12fff1e bx lr + +0000003c <arm_sym1>: + 3c: e1a00000 nop ; \(mov r0, r0\) + 40: e12fff1e bx lr + +00000044 <thumb_sym1>: + 44: 4770 bx lr + +00000046 <thumb_glob_sym1>: + 46: 4770 bx lr + +Disassembly of section foo: + +00000000 <thumb_glob_sym2-0x100>: + ... + +00000100 <thumb_glob_sym2>: + 100: f7ff fffe bl 4 <thumb_glob_sym2-0xfc> + 100: R_ARM_THM_CALL arm_glob_sym1 + 104: f7ff fffe bl 13c <arm_glob_sym2> + 104: R_ARM_THM_CALL arm_glob_sym2 + 108: f000 e816 blx 138 <arm_sym2> + 10c: f7ff fffe bl 46 <thumb_glob_sym2-0xba> + 10c: R_ARM_THM_CALL thumb_glob_sym1 + 110: f7ff fffe bl 100 <thumb_glob_sym2> + 110: R_ARM_THM_CALL thumb_glob_sym2 + 114: f000 f80e bl 134 <thumb_sym2> + 118: f7ff effe blx 4 <thumb_glob_sym2-0xfc> + 118: R_ARM_THM_CALL arm_glob_sym1 + 11c: f7ff effe blx 13c <arm_glob_sym2> + 11c: R_ARM_THM_CALL arm_glob_sym2 + 120: f000 e80a blx 138 <arm_sym2> + 124: f7ff effe blx 46 <thumb_glob_sym2-0xba> + 124: R_ARM_THM_CALL thumb_glob_sym1 + 128: f7ff effe blx 100 <thumb_glob_sym2> + 128: R_ARM_THM_CALL thumb_glob_sym2 + 12c: f000 f802 bl 134 <thumb_sym2> + 130: 46c0 nop ; \(mov r8, r8\) + 132: 4770 bx lr + +00000134 <thumb_sym2>: + 134: 46c0 nop ; \(mov r8, r8\) + 136: 4770 bx lr + +00000138 <arm_sym2>: + 138: e12fff1e bx lr + +0000013c <arm_glob_sym2>: + 13c: e12fff1e bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.l b/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.l new file mode 100644 index 00000000..293cfe01 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]*: Warning: blx to 'arm_sym1' an ARM ISA state function changed to bl +[^:]*:[0-9]*: Warning: blx to Thumb func 'thumb_sym2' from Thumb ISA state changed to bl
\ No newline at end of file diff --git a/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.s b/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.s new file mode 100644 index 00000000..b01146e2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/branch-reloc.s @@ -0,0 +1,87 @@ +@ Check that non-local branches with and without mode switching +@ produce the right relocations with appropriate in-place addends. + + .syntax unified + + .text + .arm + .global arm_glob_sym1 + .global arm_glob_sym2 + .global thumb_glob_sym1 + .global thumb_glob_sym2 + nop + .type arm_glob_sym1, %function +arm_glob_sym1: + bl thumb_glob_sym1 + bl thumb_glob_sym2 + bl thumb_sym1 + bl arm_glob_sym1 + bl arm_glob_sym2 + bl arm_sym1 + blx thumb_glob_sym1 + blx thumb_glob_sym2 + blx thumb_sym1 + blx arm_glob_sym1 + blx arm_glob_sym2 + blx arm_sym1 + nop + bx lr + + .type arm_sym1, %function +arm_sym1: + nop + bx lr + + .thumb + .thumb_func + .type thumb_sym1, %function +thumb_sym1: + bx lr + + .type thumb_glob_sym1, %function + .thumb_func + .thumb +thumb_glob_sym1: + bx lr + + .section foo,"ax" + +@ Add some space to avoid confusing objdump output: as we are +@ producing a relocatable file, objdump may match an address to +@ the wrong symbol (as symbols in different sections may have the same +@ address in the object file). + .space 0x100 + + .type thumb_glob_sym2, %function + .thumb_func + .thumb +thumb_glob_sym2: + bl arm_glob_sym1 + bl arm_glob_sym2 + bl arm_sym2 + bl thumb_glob_sym1 + bl thumb_glob_sym2 + bl thumb_sym2 + blx arm_glob_sym1 + blx arm_glob_sym2 + blx arm_sym2 + blx thumb_glob_sym1 + blx thumb_glob_sym2 + blx thumb_sym2 + nop + bx lr + + .type thumb_sym2, %function +thumb_sym2: + nop + bx lr + + .arm + .type arm_sym2, %function +arm_sym2: + bx lr + + .global arm_glob_sym2 + .type arm_glob_sym2, %function +arm_glob_sym2: + bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/bundle-lock.d b/binutils-2.25/gas/testsuite/gas/arm/bundle-lock.d new file mode 100644 index 00000000..d335833a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bundle-lock.d @@ -0,0 +1,247 @@ +#name: ARM .bundle_lock +#as: -march=armv7-a +#objdump: -drw + +.*: +file format .*arm.* + +Disassembly of section \.text: + +# This is testing the .bundle_lock feature, with 16-byte bundles. To keep +# this file simple, we just verify that every 16-byte boundary appears in +# the disassembly as either bkpt (what we use for padding to the chosen +# offset) or adds (what we use at the beginning of each bundle-locked +# sequence). + +0+0000 <arm_sequence_1_offset_0>: +#... + *0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *10:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *20:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *30:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *40:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *50:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *60:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *70:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *80:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *90:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *a0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *b0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *c0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *d0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *e0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *f0:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *100:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *110:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *120:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *130:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *140:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... + *150:\s+(e1200070\s+bkpt|e0900001\s+adds)\s+.+ +#... +0+160 <thumb_sequence_1_offset_0>: + *160:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *170:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *180:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *190:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *1a0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *1b0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *1c0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *1d0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *1e0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *1f0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *200:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *210:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *220:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *230:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *240:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *250:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *260:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *270:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *280:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *290:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *2a0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *2b0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *2c0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *2d0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *2e0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *2f0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *300:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *310:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *320:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *330:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *340:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *350:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *360:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *370:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *380:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *390:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *3a0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *3b0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *3c0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *3d0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *3e0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *3f0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *400:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *410:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *420:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *430:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *440:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *450:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *460:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *470:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *480:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *490:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *4a0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *4b0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *4c0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *4d0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *4e0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *4f0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *500:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *510:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *520:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *530:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *540:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *550:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *560:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *570:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *580:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *590:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *5a0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *5b0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *5c0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *5d0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *5e0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *5f0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *600:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *610:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *620:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *630:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *640:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *650:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *660:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *670:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *680:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *690:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *6a0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *6b0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *6c0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *6d0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *6e0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *6f0:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *700:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *710:\s+(be00\s+bkpt|1840\s+adds)\s+.+ +#... + *720:\s+e1200070\s+bkpt\s+.+ +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/bundle-lock.s b/binutils-2.25/gas/testsuite/gas/arm/bundle-lock.s new file mode 100644 index 00000000..b8fa38f6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bundle-lock.s @@ -0,0 +1,64 @@ + .syntax unified + .bundle_align_mode 4 + +# We use these macros to test each pattern at every offset from +# bundle alignment, i.e. [0,16) by 2 or 4. + + size_arm = 4 + size_thumb = 2 + +.macro offset_sequence which, size, offset + .p2align 4 +\which\()_sequence_\size\()_offset_\offset\(): + .rept \offset / size_\which + bkpt + .endr + test_sequence \size +.endm + +.macro test_offsets_arm size + .arm + offset_sequence arm, \size, 0 + offset_sequence arm, \size, 4 + offset_sequence arm, \size, 8 + offset_sequence arm, \size, 12 +.endm + +.macro test_offsets_thumb size + .thumb + offset_sequence thumb, \size, 0 + offset_sequence thumb, \size, 2 + offset_sequence thumb, \size, 4 + offset_sequence thumb, \size, 6 + offset_sequence thumb, \size, 8 + offset_sequence thumb, \size, 10 + offset_sequence thumb, \size, 12 + offset_sequence thumb, \size, 14 +.endm + +.macro test_sequence size + .bundle_lock + adds r0, r1 + .rept \size - 1 + subs r0, r1 + .endr + .bundle_unlock +.endm + + test_offsets_arm 1 + test_offsets_arm 2 + test_offsets_arm 3 + test_offsets_arm 4 + + test_offsets_thumb 1 + test_offsets_thumb 2 + test_offsets_thumb 3 + test_offsets_thumb 4 + test_offsets_thumb 5 + test_offsets_thumb 6 + test_offsets_thumb 7 + test_offsets_thumb 8 + + .arm +.p2align 4 + bkpt diff --git a/binutils-2.25/gas/testsuite/gas/arm/bundle.d b/binutils-2.25/gas/testsuite/gas/arm/bundle.d new file mode 100644 index 00000000..1c5e5a24 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bundle.d @@ -0,0 +1,96 @@ +#name: ARM .bundle_align_mode +#as: -march=armv7-a +#objdump: -drw + +.*: +file format .*arm.* + +Disassembly of section \.text: + +# This is testing the basic bundling features, with 16-byte bundles. +# To keep this file simple, we just verify that every 16-byte boundary +# appears in the disassembly as the start of an instruction. +0+0000 <test_arm_offset_0>: + *0:\s+[0-9a-f]{8}\s+[a-z].+ +#... + *10:\s+[0-9a-f]{8}\s+[a-z].+ +#... + *20:\s+[0-9a-f]{8}\s+[a-z].+ +#... + *30:\s+[0-9a-f]{8}\s+[a-z].+ +#... +0+0040 <test_thumb_2_offset_0>: +#... + *40:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *50:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *60:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *70:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *80:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *90:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *a0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *b0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *c0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *d0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *e0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *f0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *100:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *110:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *120:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *130:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *140:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *150:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *160:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *170:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *180:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *190:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *1a0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *1b0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *1c0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *1d0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *1e0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *1f0:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *200:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *210:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *220:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *230:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *240:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *250:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *260:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... + *270:\s+([0-9a-f]{4} ){1,2}\s+[a-z].+ +#... +[0-9a-f]+ <pad_for_far_target>: +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/bundle.s b/binutils-2.25/gas/testsuite/gas/arm/bundle.s new file mode 100644 index 00000000..9ec83375 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/bundle.s @@ -0,0 +1,74 @@ + .syntax unified + .bundle_align_mode 4 + +# We use these macros to test each pattern at every offset from +# bundle alignment, i.e. [0,16) by 2 or 4. + +.macro offset_insn insn_name, offset, size + .p2align 4 +\insn_name\()_offset_\offset\(): + .rept \offset / \size + bkpt + .endr + \insn_name +.endm + +.macro test_offsets_arm insn_name + .arm + offset_insn \insn_name, 0, 4 + offset_insn \insn_name, 4, 4 + offset_insn \insn_name, 8, 4 + offset_insn \insn_name, 12, 4 +.endm + +.macro test_offsets_thumb insn_name + .thumb + offset_insn \insn_name, 0, 2 + offset_insn \insn_name, 2, 2 + offset_insn \insn_name, 4, 2 + offset_insn \insn_name, 6, 2 + offset_insn \insn_name, 8, 2 + offset_insn \insn_name, 10, 2 + offset_insn \insn_name, 12, 2 + offset_insn \insn_name, 14, 2 +.endm + +.macro test_arm + add r0, r1 +.endm + +.macro test_thumb_2 + adds r0, r1 +.endm +.macro test_thumb_4 + adds r8, r9 +.endm + +test_offsets_arm test_arm +test_offsets_thumb test_thumb_2 +test_offsets_thumb test_thumb_4 + +# There are many relaxation cases for Thumb instructions. +# But we use as representative the simple branch cases. + +.macro test_thumb_b_2 + b 0f + bkpt 1 +0: bkpt 2 +.endm +.macro test_thumb_b_4 + b far_target +.endm + +test_offsets_thumb test_thumb_b_2 +test_offsets_thumb test_thumb_b_4 + +# This is to set up a branch target surely too far for a short branch. +pad_for_far_target: + .rept 1025 + bkpt 1 + .endr +far_target: + bkpt 2 +.p2align 4 + bkpt diff --git a/binutils-2.25/gas/testsuite/gas/arm/cmdline-bad-arch.d b/binutils-2.25/gas/testsuite/gas/arm/cmdline-bad-arch.d new file mode 100644 index 00000000..b414c6e7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/cmdline-bad-arch.d @@ -0,0 +1,4 @@ +# name: Bad -march command line +# as: -march=armv +# error: unknown architecture `armv' + diff --git a/binutils-2.25/gas/testsuite/gas/arm/cmdline-bad-cpu.d b/binutils-2.25/gas/testsuite/gas/arm/cmdline-bad-cpu.d new file mode 100644 index 00000000..8606b981 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/cmdline-bad-cpu.d @@ -0,0 +1,4 @@ +# name: Bad -mcpu command line +# as: -mcpu=cortex +# error: unknown cpu `cortex' + diff --git a/binutils-2.25/gas/testsuite/gas/arm/copro.d b/binutils-2.25/gas/testsuite/gas/arm/copro.d new file mode 100644 index 00000000..d007c811 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/copro.d @@ -0,0 +1,42 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM CoProcessor Instructions +#as: -march=armv5te -EL + +# Test the standard ARM co-processor instructions: + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> ee421103 dvfs f1, f2, f3 +0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5 +0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\] +0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] +0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.* +0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.* +0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] ; .* <foo> +0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\] +0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] +0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.* +0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.* +0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] ; .* <bar> +0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\} +0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\} +0+038 <[^>]*> ee215711 mcr 7, 1, r5, cr1, cr1, \{0\} +0+03c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\} +0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\} +0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\} +0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\} +0+04c <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\} +0+050 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\} +0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\} +0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\} +0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\} +0+060 <[^>]*> ecd88cff ldcl 12, cr8, \[r8\], \{255\}.* +0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}.* +0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4 +0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5 +0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15 +0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14 +0+078 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+07c <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+080 <[^>]*> aeb1f4f2 mrcge 4, 5, APSR_nzcv, cr1, cr2, \{7\} diff --git a/binutils-2.25/gas/testsuite/gas/arm/copro.s b/binutils-2.25/gas/testsuite/gas/arm/copro.s new file mode 100644 index 00000000..0ed0e054 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/copro.s @@ -0,0 +1,49 @@ +.text +.align 0 + cdp p1, 4, cr1, cr2, cr3 + cdpeq 4, 3, c1, c4, cr5, 5 + + ldc 5, cr9, [r3] + ldcl 1, cr14, [r1, #32] + ldcmi 0, cr0, [r2, #1020]! + ldcpll p7, c1, [r3], #64 + ldc p0, c8, foo +foo: + + stc 5, cr0, [r3] + stcl 3, cr15, [r0, #8] + stceq p4, cr12, [r2, #100]! + stccc p6, c8, [r4], #48 + stc p1, c7, bar +bar: + + mrc 2, 3, r5, c1, c2 + mrcge p4, 5, r15, cr1, cr2, 7 + + mcr p7, 1, r5, cr1, cr1 + mcrlt 5, 1, r8, cr2, cr9, 0 + + @ The following patterns test Addressing Mode 5 "Unindexed" + + ldc 3, c7, [r0], {0} + stc p14, c6, [r1], {1} + ldc2 5, c5, [r2], {2} + stc2 p6, c4, [r3], {3} + ldcl 7, c3, [r4], {4} + stcl p8, c2, [r5], {5} + ldc2l 9, c1, [r6], {6} + stc2l p10, c0, [r7], {7} + @ using '11' below results in an (invalid) Neon vldmia instruction. + ldcl 12, c8, [r8], {255} + stcl p12, c9, [r9], {254} + mrrc 13, 0, r7, r0, cr4 + mcrr p14, 0, r7, r0, cr5 + mrrc 15, 15, r7, r0, cr15 + mcrr p14, 15, r7, r0, cr14 + + # Extra instructions to allow for code alignment in arm-aout target. + nop + nop + + # UAL-syntax for MRC with APSR. Pre-UAL was PC + mrcge p4, 5, APSR_nzcv, cr1, cr2, 7 diff --git a/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.d b/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.d new file mode 100644 index 00000000..1a4b830e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.d @@ -0,0 +1,22 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Unpredictable ARMv8 CRC32 instructions. +#as: -march=armv8-a+crc +#stderr: crc32-bad.l +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + + +Disassembly of section .text: +0+0 <[^>]*> e101f042 crc32b pc, r1, r2 ; <UNPREDICTABLE> +0+4 <[^>]*> e12f0042 crc32h r0, pc, r2 ; <UNPREDICTABLE> +0+8 <[^>]*> e141004f crc32w r0, r1, pc ; <UNPREDICTABLE> +0+c <[^>]*> e10f0242 crc32cb r0, pc, r2 ; <UNPREDICTABLE> +0+10 <[^>]*> e121f242 crc32ch pc, r1, r2 ; <UNPREDICTABLE> +0+14 <[^>]*> e14f0242 crc32cw r0, pc, r2 ; <UNPREDICTABLE> +0+18 <[^>]*> fac1 fd82 crc32b sp, r1, r2 ; <UNPREDICTABLE> +0+1c <[^>]*> facf f092 crc32h r0, pc, r2 ; <UNPREDICTABLE> +0+20 <[^>]*> fac1 f0ad crc32w r0, r1, sp ; <UNPREDICTABLE> +0+24 <[^>]*> fadf f082 crc32cb r0, pc, r2 ; <UNPREDICTABLE> +0+28 <[^>]*> fad1 fd92 crc32ch sp, r1, r2 ; <UNPREDICTABLE> +0+2c <[^>]*> fadf f0a2 crc32cw r0, pc, r2 ; <UNPREDICTABLE> diff --git a/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.l b/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.l new file mode 100644 index 00000000..ea520aa9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.l @@ -0,0 +1,13 @@ +[^:]*: Assembler messages: +[^:]*:4: Warning: using r15 results in unpredictable behaviour +[^:]*.s:5: Warning: using r15 results in unpredictable behaviour +[^:]*.s:6: Warning: using r15 results in unpredictable behaviour +[^:]*.s:7: Warning: using r15 results in unpredictable behaviour +[^:]*.s:8: Warning: using r15 results in unpredictable behaviour +[^:]*.s:9: Warning: using r15 results in unpredictable behaviour +[^:]*.s:12: Warning: using r13 results in unpredictable behaviour +[^:]*.s:13: Warning: using r15 results in unpredictable behaviour +[^:]*.s:14: Warning: using r13 results in unpredictable behaviour +[^:]*.s:15: Warning: using r15 results in unpredictable behaviour +[^:]*.s:16: Warning: using r13 results in unpredictable behaviour +[^:]*.s:17: Warning: using r15 results in unpredictable behaviour diff --git a/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.s b/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.s new file mode 100644 index 00000000..4e497e3f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/crc32-bad.s @@ -0,0 +1,17 @@ +.section .text +.syntax unified +.arm +crc32b r15, r1, r2 +crc32h r0, r15, r2 +crc32w r0, r1, r15 +crc32cb r0, r15, r2 +crc32ch r15, r1, r2 +crc32cw r0, r15, r2 + +.thumb +crc32b r13, r1, r2 +crc32h r0, r15, r2 +crc32w r0, r1, r13 +crc32cb r0, r15, r2 +crc32ch r13, r1, r2 +crc32cw r0, r15, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/crc32.d b/binutils-2.25/gas/testsuite/gas/arm/crc32.d new file mode 100644 index 00000000..9e6c1c2f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/crc32.d @@ -0,0 +1,22 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARMv8 CRC32 instructions +#as: -march=armv8-a+crc +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: *file format .*arm.* + + +Disassembly of section .text: +0+0 <[^>]*> e1010042 crc32b r0, r1, r2 +0+4 <[^>]*> e1210042 crc32h r0, r1, r2 +0+8 <[^>]*> e1410042 crc32w r0, r1, r2 +0+c <[^>]*> e1010242 crc32cb r0, r1, r2 +0+10 <[^>]*> e1210242 crc32ch r0, r1, r2 +0+14 <[^>]*> e1410242 crc32cw r0, r1, r2 +0+18 <[^>]*> fac1 f082 crc32b r0, r1, r2 +0+1c <[^>]*> fac1 f092 crc32h r0, r1, r2 +0+20 <[^>]*> fac1 f0a2 crc32w r0, r1, r2 +0+24 <[^>]*> fad1 f082 crc32cb r0, r1, r2 +0+28 <[^>]*> fad1 f092 crc32ch r0, r1, r2 +0+2c <[^>]*> fad1 f0a2 crc32cw r0, r1, r2 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/crc32.s b/binutils-2.25/gas/testsuite/gas/arm/crc32.s new file mode 100644 index 00000000..63c1d686 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/crc32.s @@ -0,0 +1,17 @@ +.section .text +.syntax unified +.arm +crc32b r0, r1, r2 +crc32h r0, r1, r2 +crc32w r0, r1, r2 +crc32cb r0, r1, r2 +crc32ch r0, r1, r2 +crc32cw r0, r1, r2 + +.thumb +crc32b r0, r1, r2 +crc32h r0, r1, r2 +crc32w r0, r1, r2 +crc32cb r0, r1, r2 +crc32ch r0, r1, r2 +crc32cw r0, r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/depr-swp.d b/binutils-2.25/gas/testsuite/gas/arm/depr-swp.d new file mode 100644 index 00000000..40add70a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/depr-swp.d @@ -0,0 +1,3 @@ +#name: Deprecated swp{b} instructions +#source: depr-swp.s +#error-output: depr-swp.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/depr-swp.l b/binutils-2.25/gas/testsuite/gas/arm/depr-swp.l new file mode 100644 index 00000000..830f13ba --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/depr-swp.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +[^:]*:2: Warning: swp{b} use is obsoleted for ARMv8 and later +[^:]*:6: Warning: swp{b} use is deprecated for ARMv6 and ARMv7 +[^:]*:8: Warning: swp{b} use is deprecated for ARMv6 and ARMv7 diff --git a/binutils-2.25/gas/testsuite/gas/arm/depr-swp.s b/binutils-2.25/gas/testsuite/gas/arm/depr-swp.s new file mode 100644 index 00000000..ceb7d412 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/depr-swp.s @@ -0,0 +1,8 @@ +.syntax unified +swp r0, r1, [r2] +.arch armv4 +swp r0, r1, [r2] +.arch armv6 +swp r0, r1, [r2] +.arch armv7-a +swp r0, r1, [r2] diff --git a/binutils-2.25/gas/testsuite/gas/arm/dis-data.d b/binutils-2.25/gas/testsuite/gas/arm/dis-data.d new file mode 100644 index 00000000..40ca7709 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/dis-data.d @@ -0,0 +1,10 @@ +# name: Data disassembler test (no symbols) +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0x00000000 20010000 andcs r0, r1, r0 +0x00000004 000000f9 strdeq r0, \[r0\], -r9 +0x00000008 00004cd5 ldrdeq r4, \[r0\], -r5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/dis-data.s b/binutils-2.25/gas/testsuite/gas/arm/dis-data.s new file mode 100644 index 00000000..6b63a939 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/dis-data.s @@ -0,0 +1,5 @@ +.syntax unified +.word 0x20010000 +.word 0x000000f9 +.word 0x00004cd5 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/dis-data2.d b/binutils-2.25/gas/testsuite/gas/arm/dis-data2.d new file mode 100644 index 00000000..ef7bb81d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/dis-data2.d @@ -0,0 +1,10 @@ +# name: Data disassembler test (function symbol) +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +00000000 <main> 20010000 andcs r0, r1, r0 +00000004 <main\+0x4> 000000f9 strdeq r0, \[r0\], -r9 +00000008 <main\+0x8> 00004cd5 ldrdeq r4, \[r0\], -r5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/dis-data2.s b/binutils-2.25/gas/testsuite/gas/arm/dis-data2.s new file mode 100644 index 00000000..30eaa678 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/dis-data2.s @@ -0,0 +1,8 @@ +.syntax unified +.type main, %function +.globl main +main: +.word 0x20010000 +.word 0x000000f9 +.word 0x00004cd5 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/dis-data3.d b/binutils-2.25/gas/testsuite/gas/arm/dis-data3.d new file mode 100644 index 00000000..e33159b8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/dis-data3.d @@ -0,0 +1,11 @@ +# name: Data disassembler test (with mapping symbol) +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +00000000 <main> 20010000 .word 0x20010000 +00000004 <main\+0x4> 000000f9 .word 0x000000f9 +00000008 <main\+0x8> 00004cd5 .word 0x00004cd5 +0000000c <main\+0xc> e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/dis-data3.s b/binutils-2.25/gas/testsuite/gas/arm/dis-data3.s new file mode 100644 index 00000000..73da9b41 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/dis-data3.s @@ -0,0 +1,8 @@ +.syntax unified +.type main, %function +.globl main +main: +.word 0x20010000 +.word 0x000000f9 +.word 0x00004cd5 +nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/eabi_attr_1.d b/binutils-2.25/gas/testsuite/gas/arm/eabi_attr_1.d new file mode 100644 index 00000000..e3e3982d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/eabi_attr_1.d @@ -0,0 +1,14 @@ +# as: -meabi=4 +# readelf: -A +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM1136JF-S" + Tag_CPU_arch: v6 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_VFP_args: VFP registers + Tag_compatibility: flag = 3, vendor = GNU + Tag_unknown_128: 1234 \(0x4d2\) + Tag_unknown_129: "bar" diff --git a/binutils-2.25/gas/testsuite/gas/arm/eabi_attr_1.s b/binutils-2.25/gas/testsuite/gas/arm/eabi_attr_1.s new file mode 100644 index 00000000..3375acdb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/eabi_attr_1.s @@ -0,0 +1,9 @@ +.text +.cpu arm1136jf-s +foo: +bx lr +.eabi_attribute 32, 3, "GNU" +.eabi_attribute 28, 1 +.eabi_attribute 128, 1234 +.eabi_attribute 129, "bar" + diff --git a/binutils-2.25/gas/testsuite/gas/arm/el_segundo.d b/binutils-2.25/gas/testsuite/gas/arm/el_segundo.d new file mode 100644 index 00000000..6126060b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/el_segundo.d @@ -0,0 +1,34 @@ +# name: El Segundo instructions +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+00 <[^>]+> c1003281 smlabbgt r0, r1, r2, r3 +0+04 <[^>]+> e1003281 smlabb r0, r1, r2, r3 +0+08 <[^>]+> e10032a1 smlatb r0, r1, r2, r3 +0+0c <[^>]+> e10032c1 smlabt r0, r1, r2, r3 +0+10 <[^>]+> e10032e1 smlatt r0, r1, r2, r3 +0+14 <[^>]+> c1203281 smlawbgt r0, r1, r2, r3 +0+18 <[^>]+> e1203281 smlawb r0, r1, r2, r3 +0+1c <[^>]+> e12032c1 smlawt r0, r1, r2, r3 +0+20 <[^>]+> c1410382 smlalbbgt r0, r1, r2, r3 +0+24 <[^>]+> e1410382 smlalbb r0, r1, r2, r3 +0+28 <[^>]+> e14103a2 smlaltb r0, r1, r2, r3 +0+2c <[^>]+> e14103c2 smlalbt r0, r1, r2, r3 +0+30 <[^>]+> e14103e2 smlaltt r0, r1, r2, r3 +0+34 <[^>]+> c1600281 smulbbgt r0, r1, r2 +0+38 <[^>]+> e1600281 smulbb r0, r1, r2 +0+3c <[^>]+> e16002a1 smultb r0, r1, r2 +0+40 <[^>]+> e16002c1 smulbt r0, r1, r2 +0+44 <[^>]+> e16002e1 smultt r0, r1, r2 +0+48 <[^>]+> c12002a1 smulwbgt r0, r1, r2 +0+4c <[^>]+> e12002a1 smulwb r0, r1, r2 +0+50 <[^>]+> e12002e1 smulwt r0, r1, r2 +0+54 <[^>]+> c1020051 qaddgt r0, r1, r2 +0+58 <[^>]+> e1020051 qadd r0, r1, r2 +0+5c <[^>]+> e1420051 qdadd r0, r1, r2 +0+60 <[^>]+> e1220051 qsub r0, r1, r2 +0+64 <[^>]+> e1620051 qdsub r0, r1, r2 +0+68 <[^>]+> e1220051 qsub r0, r1, r2 +0+6c <[^>]+> e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/el_segundo.s b/binutils-2.25/gas/testsuite/gas/arm/el_segundo.s new file mode 100644 index 00000000..2111b5e7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/el_segundo.s @@ -0,0 +1,43 @@ +# el_segundo.s +# +# Tests that we generate the right code for v5e instructions. + .text + .global main + .align 0 +main: + smlabbgt r0,r1,r2,r3 + smlabb r0,r1,r2,r3 + smlatb r0,r1,r2,r3 + smlabt r0,r1,r2,r3 + smlatt r0,r1,r2,r3 + + smlawbgt r0,r1,r2,r3 + smlawb r0,r1,r2,r3 + smlawt r0,r1,r2,r3 + + smlalbbgt r0,r1,r2,r3 + smlalbb r0,r1,r2,r3 + smlaltb r0,r1,r2,r3 + smlalbt r0,r1,r2,r3 + smlaltt r0,r1,r2,r3 + + smulbbgt r0,r1,r2 + smulbb r0,r1,r2 + smultb r0,r1,r2 + smulbt r0,r1,r2 + smultt r0,r1,r2 + + smulwbgt r0,r1,r2 + smulwb r0,r1,r2 + smulwt r0,r1,r2 + + qaddgt r0,r1,r2 + qadd r0,r1,r2 + + qdadd r0,r1,r2 + qsub r0,r1,r2 + qdsub r0,r1,r2 + qsub r0,r1,r2 + + @ padding for a.out's sake + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/float.d b/binutils-2.25/gas/testsuite/gas/arm/float.d new file mode 100644 index 00000000..c0494309 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/float.d @@ -0,0 +1,131 @@ +# name: Core floating point instructions +# as: -mcpu=arm7tdmi -mfpu=fpa +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> ee088101 ? mvfe f0, f1 +0+004 <[^>]+> 0e08b105 ? mvfeqe f3, f5 +0+008 <[^>]+> 0e00c189 ? mvfeqd f4, #1\.0 +0+00c <[^>]+> ee00c107 ? mvfs f4, f7 +0+010 <[^>]+> ee008121 ? mvfsp f0, f1 +0+014 <[^>]+> ee00b1c4 ? mvfdm f3, f4 +0+018 <[^>]+> ee08f167 ? mvfez f7, f7 +0+01c <[^>]+> ee09010a ? adfe f0, f1, #2\.0 +0+020 <[^>]+> 0e0a110e ? adfeqe f1, f2, #0\.5 +0+024 <[^>]+> ee043145 ? adfsm f3, f4, f5 +0+028 <[^>]+> ee20018a ? sufd f0, f0, #2\.0 +0+02c <[^>]+> ee22110f ? sufs f1, f2, #10\.0 +0+030 <[^>]+> 1e2c3165 ? sufneez f3, f4, f5 +0+034 <[^>]+> ee311108 ? rsfs f1, f1, #0\.0 +0+038 <[^>]+> ee3031ad ? rsfdp f3, f0, #5\.0 +0+03c <[^>]+> de367180 ? rsfled f7, f6, f0 +0+040 <[^>]+> ee100180 ? mufd f0, f0, f0 +0+044 <[^>]+> ee1a116b ? mufez f1, f2, #3\.0 +0+048 <[^>]+> ee10010c ? mufs f0, f0, #4\.0 +0+04c <[^>]+> ee400189 ? dvfd f0, f0, #1\.0 +0+050 <[^>]+> ee49016f ? dvfez f0, f1, #10\.0 +0+054 <[^>]+> 4e443145 ? dvfmism f3, f4, f5 +0+058 <[^>]+> ee59010f ? rdfe f0, f1, #10\.0 +0+05c <[^>]+> ee573109 ? rdfs f3, f7, #1\.0 +0+060 <[^>]+> 3e5441a3 ? rdfccdp f4, f4, f3 +0+064 <[^>]+> ee620183 ? powd f0, f2, f3 +0+068 <[^>]+> ee63110f ? pows f1, f3, #10\.0 +0+06c <[^>]+> 2e6f4169 ? powcsez f4, f7, #1\.0 +0+070 <[^>]+> ee767107 ? rpws f7, f6, f7 +0+074 <[^>]+> 0e710182 ? rpweqd f0, f1, f2 +0+078 <[^>]+> ee7a2143 ? rpwem f2, f2, f3 +0+07c <[^>]+> ee82118b ? rmfd f1, f2, #3\.0 +0+080 <[^>]+> 6e843104 ? rmfvss f3, f4, f4 +0+084 <[^>]+> ee8f4120 ? rmfep f4, f7, f0 +0+088 <[^>]+> ee910102 ? fmls f0, f1, f2 +0+08c <[^>]+> 0e931105 ? fmleqs f1, f3, f5 +0+090 <[^>]+> 5e964160 ? fmlplsz f4, f6, f0 +0+094 <[^>]+> eea3110f ? fdvs f1, f3, #10\.0 +0+098 <[^>]+> eea10122 ? fdvsp f0, f1, f2 +0+09c <[^>]+> 2ea44144 ? fdvcssm f4, f4, f4 +0+0a0 <[^>]+> eeb11109 ? frds f1, f1, #1\.0 +0+0a4 <[^>]+> ceb12100 ? frdgts f2, f1, f0 +0+0a8 <[^>]+> ceb44165 ? frdgtsz f4, f4, f5 +0+0ac <[^>]+> eec10182 ? pold f0, f1, f2 +0+0b0 <[^>]+> eec6416b ? polsz f4, f6, #3\.0 +0+0b4 <[^>]+> 0ece5107 ? poleqe f5, f6, f7 +0+0b8 <[^>]+> ee108101 ? mnfs f0, f1 +0+0bc <[^>]+> ee10818b ? mnfd f0, #3\.0 +0+0c0 <[^>]+> ee18816c ? mnfez f0, #4\.0 +0+0c4 <[^>]+> 0e188165 ? mnfeqez f0, f5 +0+0c8 <[^>]+> ee108124 ? mnfsp f0, f4 +0+0cc <[^>]+> ee1091c7 ? mnfdm f1, f7 +0+0d0 <[^>]+> ee208181 ? absd f0, f1 +0+0d4 <[^>]+> ee20912b ? abssp f1, #3\.0 +0+0d8 <[^>]+> 0e28c105 ? abseqe f4, f5 +0+0dc <[^>]+> ee309102 ? rnds f1, f2 +0+0e0 <[^>]+> ee30b184 ? rndd f3, f4 +0+0e4 <[^>]+> 0e38e16c ? rndeqez f6, #4\.0 +0+0e8 <[^>]+> ee40d105 ? sqts f5, f5 +0+0ec <[^>]+> ee40e1a6 ? sqtdp f6, f6 +0+0f0 <[^>]+> 5e48f166 ? sqtplez f7, f6 +0+0f4 <[^>]+> ee50810f ? logs f0, #10\.0 +0+0f8 <[^>]+> ee58810f ? loge f0, #10\.0 +0+0fc <[^>]+> 1e5081e1 ? lognedz f0, f1 +0+100 <[^>]+> ee689102 ? lgne f1, f2 +0+104 <[^>]+> ee6091e3 ? lgndz f1, f3 +0+108 <[^>]+> 7e60b104 ? lgnvcs f3, f4 +0+10c <[^>]+> ee709103 ? exps f1, f3 +0+110 <[^>]+> ee78b14f ? expem f3, #10\.0 +0+114 <[^>]+> 5e70e187 ? exppld f6, f7 +0+118 <[^>]+> ee808181 ? sind f0, f1 +0+11c <[^>]+> ee809142 ? sinsm f1, f2 +0+120 <[^>]+> ce88c10d ? singte f4, #5\.0 +0+124 <[^>]+> ee909183 ? cosd f1, f3 +0+128 <[^>]+> ee98c145 ? cosem f4, f5 +0+12c <[^>]+> 1e90e1a1 ? cosnedp f6, f1 +0+130 <[^>]+> eea89105 ? tane f1, f5 +0+134 <[^>]+> eea0c167 ? tansz f4, f7 +0+138 <[^>]+> aea091ec ? tangedz f1, #4\.0 +0+13c <[^>]+> eeb8c105 ? asne f4, f5 +0+140 <[^>]+> eeb0e12e ? asnsp f6, #0\.5 +0+144 <[^>]+> 4eb0d1e5 ? asnmidz f5, f5 +0+148 <[^>]+> eec0d106 ? acss f5, f6 +0+14c <[^>]+> eec0e180 ? acsd f6, f0 +0+150 <[^>]+> 2ec8914e ? acscsem f1, #0\.5 +0+154 <[^>]+> eed88105 ? atne f0, f5 +0+158 <[^>]+> eed0916d ? atnsz f1, #5\.0 +0+15c <[^>]+> bed0b182 ? atnltd f3, f2 +0+160 <[^>]+> eee8d104 ? urde f5, f4 +0+164 <[^>]+> eef8e105 ? nrme f6, f5 +0+168 <[^>]+> 5ef0f1e5 ? nrmpldz f7, f5 +0+16c <[^>]+> ee008130 ? fltsp f0, r8 +0+170 <[^>]+> ee090110 ? flte f1, r0 +0+174 <[^>]+> 0e0571f0 ? flteqdz f5, r7 +0+178 <[^>]+> ee100111 ? fix r0, f1 +0+17c <[^>]+> ee101177 ? fixz r1, f7 +0+180 <[^>]+> 2e105155 ? fixcsm r5, f5 +0+184 <[^>]+> ee400110 ? wfc r0 +0+188 <[^>]+> ee201110 ? wfs r1 +0+18c <[^>]+> 0e302110 ? rfseq r2 +0+190 <[^>]+> ee504110 ? rfc r4 +0+194 <[^>]+> ee90f119 ? cmf f0, #1\.0 +0+198 <[^>]+> ee91f112 ? cmf f1, f2 +0+19c <[^>]+> 0e90f111 ? cmfeq f0, f1 +0+1a0 <[^>]+> eeb0f11b ? cnf f0, #3\.0 +0+1a4 <[^>]+> eeb1f11e ? cnf f1, #0\.5 +0+1a8 <[^>]+> 6eb3f114 ? cnfvs f3, f4 +0+1ac <[^>]+> eed0f111 ? cmfe f0, f1 +0+1b0 <[^>]+> 0ed1f112 ? cmfeeq f1, f2 +0+1b4 <[^>]+> 0ed3f11d ? cmfeeq f3, #5\.0 +0+1b8 <[^>]+> eef1f113 ? cnfe f1, f3 +0+1bc <[^>]+> 0ef3f114 ? cnfeeq f3, f4 +0+1c0 <[^>]+> 0ef4f117 ? cnfeeq f4, f7 +0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0 +0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\] +0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\] +0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\].* +0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]!.* +0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020.* +0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] ; .* <l\+.*> +0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12 +0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\].* +0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\].* +0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]!.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/float.s b/binutils-2.25/gas/testsuite/gas/arm/float.s new file mode 100644 index 00000000..437d298d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/float.s @@ -0,0 +1,163 @@ + .text + .align 0 +l: + mvfe f0, f1 + mvfeqe f3, f5 + mvfeqd f4, #1.0 + mvfs f4, f7 + mvfsp f0, f1 + mvfdm f3, f4 + mvfez f7, f7 + + adfe f0, f1, #2.0 + adfeqe f1, f2, #0.5 + adfsm f3, f4, f5 + + sufd f0, f0, #2.0 + sufs f1, f2, #10.0 + sufneez f3, f4, f5 + + rsfs f1, f1, #0.0 + rsfdp f3, f0, #5.0 + rsfled f7, f6, f0 + + mufd f0, f0, f0 + mufez f1, f2, #3.0 + mufals f0, f0, #4.0 + + dvfd f0, f0, #1.0000 + dvfez f0, f1, #10e0 + dvfmism f3, f4, f5 + + rdfe f0, f1, #1.0e1 + rdfs f3, f7, #0f1 + rdfccdp f4, f4, f3 + + powd f0, f2, f3 + pows f1, f3, #0e1e1 + powcsez f4, f7, #1 + + rpws f7, f6, f7 + rpweqd f0, f1, f2 + rpwem f2, f2, f3 + + rmfd f1, f2, #3 + rmfvss f3, f4, f4 + rmfep f4, f7, f0 + + fmls f0, f1, f2 + fmleqs f1, f3, f5 + fmlplsz f4, f6, f0 + + fdvs f1, f3, #10 + fdvsp f0, f1, f2 + fdvhssm f4, f4, f4 + + frds f1, f1, #1.0 + frdgts f2, f1, f0 + frdgtsz f4, f4, f5 + + pold f0, f1, f2 + polsz f4, f6, #3.0 + poleqe f5, f6, f7 + + mnfs f0, f1 + mnfd f0, #3.0 + mnfez f0, #4.0 + mnfeqez f0, f5 + mnfsp f0, f4 + mnfdm f1, f7 + + absd f0, f1 + abssp f1, #3.0 + abseqe f4, f5 + + rnds f1, f2 + rndd f3, f4 + rndeqez f6, #4.0 + + sqts f5, f5 + sqtdp f6, f6 + sqtplez f7, f6 + + logs f0, #10 + loge f0, #0f10 + lognedz f0, f1 + + lgne f1, f2 + lgndz f1, f3 + lgnvcs f3, f4 + + exps f1, f3 + expem f3, #10.0 + exppld f6, f7 + + sind f0, f1 + sinsm f1, f2 + singte f4, #5 + + cosd f1, f3 + cosem f4, f5 + cosnedp f6, f1 + + tane f1, f5 + tansz f4, f7 + tangedz f1, #4.0 + + asne f4, f5 + asnsp f6, #5e-1 + asnmidz f5, f5 + + acss f5, f6 + acsd f6, f0 + acshsem f1, #0.05e1 + + atne f0, f5 + atnsz f1, #5 + atnltd f3, f2 + + urde f5, f4 + nrme f6, f5 + nrmpldz f7, f5 + + fltsp f0, r8 + flte f1, r0 + flteqdz f5, r7 + + fix r0, f1 + fixz r1, f7 + fixcsm r5, f5 + + wfc r0 + wfs r1 + rfseq r2 + rfc r4 + + cmf f0, #1 + cmf f1, f2 + cmfeq f0, f1 + + cnf f0, #3 + cnf f1, #0.5 + cnfvs f3, f4 + + cmfe f0, f1 + cmfeeq f1, f2 + cmfeqe f3, #5.0 + + cnfe f1, f3 + cnfeeq f3, f4 + cnfeqe f4, f7 + cnfale f4, #5.0 + + lfm f0, 4, [r0] + lfm f0, 4, [r0, #0] + lfm f1, 4, [r1, #64] + sfm f2, 4, [r14, #1020]! + sfmeq f7, 3, [r8], #-1020 + + lfmfd f6, 2, [r15] + sfmea f7, 1, [r8]! + lfmeqea f5, 4, [r6] + sfmnefd f4, 3, [r2] + sfmnefd f4, 3, [r2]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/fp-save.d b/binutils-2.25/gas/testsuite/gas/arm/fp-save.d new file mode 100644 index 00000000..d32d9306 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fp-save.d @@ -0,0 +1,9 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: PR5712 - saving FP registers +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-riscix* +#as: -mfpu=fpa + +.*: *file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> ed2dc203[ ]+sfm[ ]+f4, 1, \[sp, #-12\]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/fp-save.s b/binutils-2.25/gas/testsuite/gas/arm/fp-save.s new file mode 100644 index 00000000..d0a572aa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fp-save.s @@ -0,0 +1,4 @@ + .fnstart
+ sfmfd f4, 1, [sp]!
+ .save f4, 1
+ .fnend
diff --git a/binutils-2.25/gas/testsuite/gas/arm/fpa-dyadic.d b/binutils-2.25/gas/testsuite/gas/arm/fpa-dyadic.d new file mode 100644 index 00000000..f603bbff --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fpa-dyadic.d @@ -0,0 +1,166 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: FPA Dyadic instructions +#as: -mfpu=fpa -mcpu=arm7m + +# Test FPA Dyadic instructions +# This test should work for both big and little-endian assembly. + +.*: *file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> ee000100 ? adfs f0, f0, f0 +0+004 <[^>]*> ee000120 ? adfsp f0, f0, f0 +0+008 <[^>]*> ee000140 ? adfsm f0, f0, f0 +0+00c <[^>]*> ee000160 ? adfsz f0, f0, f0 +0+010 <[^>]*> ee000180 ? adfd f0, f0, f0 +0+014 <[^>]*> ee0001a0 ? adfdp f0, f0, f0 +0+018 <[^>]*> ee0001c0 ? adfdm f0, f0, f0 +0+01c <[^>]*> ee0001e0 ? adfdz f0, f0, f0 +0+020 <[^>]*> ee080100 ? adfe f0, f0, f0 +0+024 <[^>]*> ee080120 ? adfep f0, f0, f0 +0+028 <[^>]*> ee080140 ? adfem f0, f0, f0 +0+02c <[^>]*> ee080160 ? adfez f0, f0, f0 +0+030 <[^>]*> ee200100 ? sufs f0, f0, f0 +0+034 <[^>]*> ee200120 ? sufsp f0, f0, f0 +0+038 <[^>]*> ee200140 ? sufsm f0, f0, f0 +0+03c <[^>]*> ee200160 ? sufsz f0, f0, f0 +0+040 <[^>]*> ee200180 ? sufd f0, f0, f0 +0+044 <[^>]*> ee2001a0 ? sufdp f0, f0, f0 +0+048 <[^>]*> ee2001c0 ? sufdm f0, f0, f0 +0+04c <[^>]*> ee2001e0 ? sufdz f0, f0, f0 +0+050 <[^>]*> ee280100 ? sufe f0, f0, f0 +0+054 <[^>]*> ee280120 ? sufep f0, f0, f0 +0+058 <[^>]*> ee280140 ? sufem f0, f0, f0 +0+05c <[^>]*> ee280160 ? sufez f0, f0, f0 +0+060 <[^>]*> ee300100 ? rsfs f0, f0, f0 +0+064 <[^>]*> ee300120 ? rsfsp f0, f0, f0 +0+068 <[^>]*> ee300140 ? rsfsm f0, f0, f0 +0+06c <[^>]*> ee300160 ? rsfsz f0, f0, f0 +0+070 <[^>]*> ee300180 ? rsfd f0, f0, f0 +0+074 <[^>]*> ee3001a0 ? rsfdp f0, f0, f0 +0+078 <[^>]*> ee3001c0 ? rsfdm f0, f0, f0 +0+07c <[^>]*> ee3001e0 ? rsfdz f0, f0, f0 +0+080 <[^>]*> ee380100 ? rsfe f0, f0, f0 +0+084 <[^>]*> ee380120 ? rsfep f0, f0, f0 +0+088 <[^>]*> ee380140 ? rsfem f0, f0, f0 +0+08c <[^>]*> ee380160 ? rsfez f0, f0, f0 +0+090 <[^>]*> ee100100 ? mufs f0, f0, f0 +0+094 <[^>]*> ee100120 ? mufsp f0, f0, f0 +0+098 <[^>]*> ee100140 ? mufsm f0, f0, f0 +0+09c <[^>]*> ee100160 ? mufsz f0, f0, f0 +0+0a0 <[^>]*> ee100180 ? mufd f0, f0, f0 +0+0a4 <[^>]*> ee1001a0 ? mufdp f0, f0, f0 +0+0a8 <[^>]*> ee1001c0 ? mufdm f0, f0, f0 +0+0ac <[^>]*> ee1001e0 ? mufdz f0, f0, f0 +0+0b0 <[^>]*> ee180100 ? mufe f0, f0, f0 +0+0b4 <[^>]*> ee180120 ? mufep f0, f0, f0 +0+0b8 <[^>]*> ee180140 ? mufem f0, f0, f0 +0+0bc <[^>]*> ee180160 ? mufez f0, f0, f0 +0+0c0 <[^>]*> ee400100 ? dvfs f0, f0, f0 +0+0c4 <[^>]*> ee400120 ? dvfsp f0, f0, f0 +0+0c8 <[^>]*> ee400140 ? dvfsm f0, f0, f0 +0+0cc <[^>]*> ee400160 ? dvfsz f0, f0, f0 +0+0d0 <[^>]*> ee400180 ? dvfd f0, f0, f0 +0+0d4 <[^>]*> ee4001a0 ? dvfdp f0, f0, f0 +0+0d8 <[^>]*> ee4001c0 ? dvfdm f0, f0, f0 +0+0dc <[^>]*> ee4001e0 ? dvfdz f0, f0, f0 +0+0e0 <[^>]*> ee480100 ? dvfe f0, f0, f0 +0+0e4 <[^>]*> ee480120 ? dvfep f0, f0, f0 +0+0e8 <[^>]*> ee480140 ? dvfem f0, f0, f0 +0+0ec <[^>]*> ee480160 ? dvfez f0, f0, f0 +0+0f0 <[^>]*> ee500100 ? rdfs f0, f0, f0 +0+0f4 <[^>]*> ee500120 ? rdfsp f0, f0, f0 +0+0f8 <[^>]*> ee500140 ? rdfsm f0, f0, f0 +0+0fc <[^>]*> ee500160 ? rdfsz f0, f0, f0 +0+100 <[^>]*> ee500180 ? rdfd f0, f0, f0 +0+104 <[^>]*> ee5001a0 ? rdfdp f0, f0, f0 +0+108 <[^>]*> ee5001c0 ? rdfdm f0, f0, f0 +0+10c <[^>]*> ee5001e0 ? rdfdz f0, f0, f0 +0+110 <[^>]*> ee580100 ? rdfe f0, f0, f0 +0+114 <[^>]*> ee580120 ? rdfep f0, f0, f0 +0+118 <[^>]*> ee580140 ? rdfem f0, f0, f0 +0+11c <[^>]*> ee580160 ? rdfez f0, f0, f0 +0+120 <[^>]*> ee600100 ? pows f0, f0, f0 +0+124 <[^>]*> ee600120 ? powsp f0, f0, f0 +0+128 <[^>]*> ee600140 ? powsm f0, f0, f0 +0+12c <[^>]*> ee600160 ? powsz f0, f0, f0 +0+130 <[^>]*> ee600180 ? powd f0, f0, f0 +0+134 <[^>]*> ee6001a0 ? powdp f0, f0, f0 +0+138 <[^>]*> ee6001c0 ? powdm f0, f0, f0 +0+13c <[^>]*> ee6001e0 ? powdz f0, f0, f0 +0+140 <[^>]*> ee680100 ? powe f0, f0, f0 +0+144 <[^>]*> ee680120 ? powep f0, f0, f0 +0+148 <[^>]*> ee680140 ? powem f0, f0, f0 +0+14c <[^>]*> ee680160 ? powez f0, f0, f0 +0+150 <[^>]*> ee700100 ? rpws f0, f0, f0 +0+154 <[^>]*> ee700120 ? rpwsp f0, f0, f0 +0+158 <[^>]*> ee700140 ? rpwsm f0, f0, f0 +0+15c <[^>]*> ee700160 ? rpwsz f0, f0, f0 +0+160 <[^>]*> ee700180 ? rpwd f0, f0, f0 +0+164 <[^>]*> ee7001a0 ? rpwdp f0, f0, f0 +0+168 <[^>]*> ee7001c0 ? rpwdm f0, f0, f0 +0+16c <[^>]*> ee7001e0 ? rpwdz f0, f0, f0 +0+170 <[^>]*> ee780100 ? rpwe f0, f0, f0 +0+174 <[^>]*> ee780120 ? rpwep f0, f0, f0 +0+178 <[^>]*> ee780140 ? rpwem f0, f0, f0 +0+17c <[^>]*> ee780160 ? rpwez f0, f0, f0 +0+180 <[^>]*> ee800100 ? rmfs f0, f0, f0 +0+184 <[^>]*> ee800120 ? rmfsp f0, f0, f0 +0+188 <[^>]*> ee800140 ? rmfsm f0, f0, f0 +0+18c <[^>]*> ee800160 ? rmfsz f0, f0, f0 +0+190 <[^>]*> ee800180 ? rmfd f0, f0, f0 +0+194 <[^>]*> ee8001a0 ? rmfdp f0, f0, f0 +0+198 <[^>]*> ee8001c0 ? rmfdm f0, f0, f0 +0+19c <[^>]*> ee8001e0 ? rmfdz f0, f0, f0 +0+1a0 <[^>]*> ee880100 ? rmfe f0, f0, f0 +0+1a4 <[^>]*> ee880120 ? rmfep f0, f0, f0 +0+1a8 <[^>]*> ee880140 ? rmfem f0, f0, f0 +0+1ac <[^>]*> ee880160 ? rmfez f0, f0, f0 +0+1b0 <[^>]*> ee900100 ? fmls f0, f0, f0 +0+1b4 <[^>]*> ee900120 ? fmlsp f0, f0, f0 +0+1b8 <[^>]*> ee900140 ? fmlsm f0, f0, f0 +0+1bc <[^>]*> ee900160 ? fmlsz f0, f0, f0 +0+1c0 <[^>]*> ee900180 ? fmld f0, f0, f0 +0+1c4 <[^>]*> ee9001a0 ? fmldp f0, f0, f0 +0+1c8 <[^>]*> ee9001c0 ? fmldm f0, f0, f0 +0+1cc <[^>]*> ee9001e0 ? fmldz f0, f0, f0 +0+1d0 <[^>]*> ee980100 ? fmle f0, f0, f0 +0+1d4 <[^>]*> ee980120 ? fmlep f0, f0, f0 +0+1d8 <[^>]*> ee980140 ? fmlem f0, f0, f0 +0+1dc <[^>]*> ee980160 ? fmlez f0, f0, f0 +0+1e0 <[^>]*> eea00100 ? fdvs f0, f0, f0 +0+1e4 <[^>]*> eea00120 ? fdvsp f0, f0, f0 +0+1e8 <[^>]*> eea00140 ? fdvsm f0, f0, f0 +0+1ec <[^>]*> eea00160 ? fdvsz f0, f0, f0 +0+1f0 <[^>]*> eea00180 ? fdvd f0, f0, f0 +0+1f4 <[^>]*> eea001a0 ? fdvdp f0, f0, f0 +0+1f8 <[^>]*> eea001c0 ? fdvdm f0, f0, f0 +0+1fc <[^>]*> eea001e0 ? fdvdz f0, f0, f0 +0+200 <[^>]*> eea80100 ? fdve f0, f0, f0 +0+204 <[^>]*> eea80120 ? fdvep f0, f0, f0 +0+208 <[^>]*> eea80140 ? fdvem f0, f0, f0 +0+20c <[^>]*> eea80160 ? fdvez f0, f0, f0 +0+210 <[^>]*> eeb00100 ? frds f0, f0, f0 +0+214 <[^>]*> eeb00120 ? frdsp f0, f0, f0 +0+218 <[^>]*> eeb00140 ? frdsm f0, f0, f0 +0+21c <[^>]*> eeb00160 ? frdsz f0, f0, f0 +0+220 <[^>]*> eeb00180 ? frdd f0, f0, f0 +0+224 <[^>]*> eeb001a0 ? frddp f0, f0, f0 +0+228 <[^>]*> eeb001c0 ? frddm f0, f0, f0 +0+22c <[^>]*> eeb001e0 ? frddz f0, f0, f0 +0+230 <[^>]*> eeb80100 ? frde f0, f0, f0 +0+234 <[^>]*> eeb80120 ? frdep f0, f0, f0 +0+238 <[^>]*> eeb80140 ? frdem f0, f0, f0 +0+23c <[^>]*> eeb80160 ? frdez f0, f0, f0 +0+240 <[^>]*> eec00100 ? pols f0, f0, f0 +0+244 <[^>]*> eec00120 ? polsp f0, f0, f0 +0+248 <[^>]*> eec00140 ? polsm f0, f0, f0 +0+24c <[^>]*> eec00160 ? polsz f0, f0, f0 +0+250 <[^>]*> eec00180 ? pold f0, f0, f0 +0+254 <[^>]*> eec001a0 ? poldp f0, f0, f0 +0+258 <[^>]*> eec001c0 ? poldm f0, f0, f0 +0+25c <[^>]*> eec001e0 ? poldz f0, f0, f0 +0+260 <[^>]*> eec80100 ? pole f0, f0, f0 +0+264 <[^>]*> eec80120 ? polep f0, f0, f0 +0+268 <[^>]*> eec80140 ? polem f0, f0, f0 +0+26c <[^>]*> eec80160 ? polez f0, f0, f0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/fpa-dyadic.s b/binutils-2.25/gas/testsuite/gas/arm/fpa-dyadic.s new file mode 100644 index 00000000..aebcd2b9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fpa-dyadic.s @@ -0,0 +1,172 @@ + .text + .globl F +F: + adfs f0, f0, f0 + adfsp f0, f0, f0 + adfsm f0, f0, f0 + adfsz f0, f0, f0 + adfd f0, f0, f0 + adfdp f0, f0, f0 + adfdm f0, f0, f0 + adfdz f0, f0, f0 + adfe f0, f0, f0 + adfep f0, f0, f0 + adfem f0, f0, f0 + adfez f0, f0, f0 + + sufs f0, f0, f0 + sufsp f0, f0, f0 + sufsm f0, f0, f0 + sufsz f0, f0, f0 + sufd f0, f0, f0 + sufdp f0, f0, f0 + sufdm f0, f0, f0 + sufdz f0, f0, f0 + sufe f0, f0, f0 + sufep f0, f0, f0 + sufem f0, f0, f0 + sufez f0, f0, f0 + + rsfs f0, f0, f0 + rsfsp f0, f0, f0 + rsfsm f0, f0, f0 + rsfsz f0, f0, f0 + rsfd f0, f0, f0 + rsfdp f0, f0, f0 + rsfdm f0, f0, f0 + rsfdz f0, f0, f0 + rsfe f0, f0, f0 + rsfep f0, f0, f0 + rsfem f0, f0, f0 + rsfez f0, f0, f0 + + mufs f0, f0, f0 + mufsp f0, f0, f0 + mufsm f0, f0, f0 + mufsz f0, f0, f0 + mufd f0, f0, f0 + mufdp f0, f0, f0 + mufdm f0, f0, f0 + mufdz f0, f0, f0 + mufe f0, f0, f0 + mufep f0, f0, f0 + mufem f0, f0, f0 + mufez f0, f0, f0 + + dvfs f0, f0, f0 + dvfsp f0, f0, f0 + dvfsm f0, f0, f0 + dvfsz f0, f0, f0 + dvfd f0, f0, f0 + dvfdp f0, f0, f0 + dvfdm f0, f0, f0 + dvfdz f0, f0, f0 + dvfe f0, f0, f0 + dvfep f0, f0, f0 + dvfem f0, f0, f0 + dvfez f0, f0, f0 + + rdfs f0, f0, f0 + rdfsp f0, f0, f0 + rdfsm f0, f0, f0 + rdfsz f0, f0, f0 + rdfd f0, f0, f0 + rdfdp f0, f0, f0 + rdfdm f0, f0, f0 + rdfdz f0, f0, f0 + rdfe f0, f0, f0 + rdfep f0, f0, f0 + rdfem f0, f0, f0 + rdfez f0, f0, f0 + + pows f0, f0, f0 + powsp f0, f0, f0 + powsm f0, f0, f0 + powsz f0, f0, f0 + powd f0, f0, f0 + powdp f0, f0, f0 + powdm f0, f0, f0 + powdz f0, f0, f0 + powe f0, f0, f0 + powep f0, f0, f0 + powem f0, f0, f0 + powez f0, f0, f0 + + rpws f0, f0, f0 + rpwsp f0, f0, f0 + rpwsm f0, f0, f0 + rpwsz f0, f0, f0 + rpwd f0, f0, f0 + rpwdp f0, f0, f0 + rpwdm f0, f0, f0 + rpwdz f0, f0, f0 + rpwe f0, f0, f0 + rpwep f0, f0, f0 + rpwem f0, f0, f0 + rpwez f0, f0, f0 + + rmfs f0, f0, f0 + rmfsp f0, f0, f0 + rmfsm f0, f0, f0 + rmfsz f0, f0, f0 + rmfd f0, f0, f0 + rmfdp f0, f0, f0 + rmfdm f0, f0, f0 + rmfdz f0, f0, f0 + rmfe f0, f0, f0 + rmfep f0, f0, f0 + rmfem f0, f0, f0 + rmfez f0, f0, f0 + + fmls f0, f0, f0 + fmlsp f0, f0, f0 + fmlsm f0, f0, f0 + fmlsz f0, f0, f0 + fmld f0, f0, f0 + fmldp f0, f0, f0 + fmldm f0, f0, f0 + fmldz f0, f0, f0 + fmle f0, f0, f0 + fmlep f0, f0, f0 + fmlem f0, f0, f0 + fmlez f0, f0, f0 + + fdvs f0, f0, f0 + fdvsp f0, f0, f0 + fdvsm f0, f0, f0 + fdvsz f0, f0, f0 + fdvd f0, f0, f0 + fdvdp f0, f0, f0 + fdvdm f0, f0, f0 + fdvdz f0, f0, f0 + fdve f0, f0, f0 + fdvep f0, f0, f0 + fdvem f0, f0, f0 + fdvez f0, f0, f0 + + frds f0, f0, f0 + frdsp f0, f0, f0 + frdsm f0, f0, f0 + frdsz f0, f0, f0 + frdd f0, f0, f0 + frddp f0, f0, f0 + frddm f0, f0, f0 + frddz f0, f0, f0 + frde f0, f0, f0 + frdep f0, f0, f0 + frdem f0, f0, f0 + frdez f0, f0, f0 + + pols f0, f0, f0 + polsp f0, f0, f0 + polsm f0, f0, f0 + polsz f0, f0, f0 + pold f0, f0, f0 + poldp f0, f0, f0 + poldm f0, f0, f0 + poldz f0, f0, f0 + pole f0, f0, f0 + polep f0, f0, f0 + polem f0, f0, f0 + polez f0, f0, f0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/fpa-mem.d b/binutils-2.25/gas/testsuite/gas/arm/fpa-mem.d new file mode 100644 index 00000000..4a638e1f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fpa-mem.d @@ -0,0 +1,34 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: FPA memory insructions +#as: -mfpu=fpa10 -mcpu=arm7m + +# Test FPA memory instructions +# This test should work for both big and little-endian assembly. + +.*: *file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> ed900100 ? ldfs f0, \[r0\] +0+04 <[^>]*> ec300101 ? ldfs f0, \[r0\], #-4 +0+08 <[^>]*> ed908100 ? ldfd f0, \[r0\] +0+0c <[^>]*> ec308101 ? ldfd f0, \[r0\], #-4 +0+10 <[^>]*> edd00100 ? ldfe f0, \[r0\] +0+14 <[^>]*> ec700101 ? ldfe f0, \[r0\], #-4 +0+18 <[^>]*> edd08100 ? ldfp f0, \[r0\] +0+1c <[^>]*> ec708101 ? ldfp f0, \[r0\], #-4 +0+20 <[^>]*> ed800100 ? stfs f0, \[r0\] +0+24 <[^>]*> ec200101 ? stfs f0, \[r0\], #-4 +0+28 <[^>]*> ed808100 ? stfd f0, \[r0\] +0+2c <[^>]*> ec208101 ? stfd f0, \[r0\], #-4 +0+30 <[^>]*> edc00100 ? stfe f0, \[r0\] +0+34 <[^>]*> ec600101 ? stfe f0, \[r0\], #-4 +0+38 <[^>]*> edc08100 ? stfp f0, \[r0\] +0+3c <[^>]*> ec608101 ? stfp f0, \[r0\], #-4 +0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] +0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] +0+48 <[^>]*> ed10020c ? lfm f0, 4, \[r0, #-48\].* +0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\] +0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, #-48\].* +0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\] +0+58 <[^>]*> 5d800100 ? stfpls f0, \[r0\] +0+5c <[^>]*> 5d800100 ? stfpls f0, \[r0\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/fpa-mem.s b/binutils-2.25/gas/testsuite/gas/arm/fpa-mem.s new file mode 100644 index 00000000..bcb4ae3a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fpa-mem.s @@ -0,0 +1,32 @@ + .text + .globl F +F: + ldfs f0, [r0] + ldfs f0, [r0], #-4 + ldfd f0, [r0] + ldfd f0, [r0], #-4 + ldfe f0, [r0] + ldfe f0, [r0], #-4 + ldfp f0, [r0] + ldfp f0, [r0], #-4 + + stfs f0, [r0] + stfs f0, [r0], #-4 + stfd f0, [r0] + stfd f0, [r0], #-4 + stfe f0, [r0] + stfe f0, [r0], #-4 + stfp f0, [r0] + stfp f0, [r0], #-4 + lfm f0, 4, [r0] + lfmfd f0, 4, [r0] + lfmea f0, 4, [r0] + sfm f0, 4, [r0] + sfmfd f0, 4, [r0] + sfmea f0, 4, [r0] + + # Test mnemonic that is ambiguous between infix and suffic + # condition codes + stfpls f0, [r0] + .syntax unified + stfpls f0, [r0] diff --git a/binutils-2.25/gas/testsuite/gas/arm/fpa-monadic.d b/binutils-2.25/gas/testsuite/gas/arm/fpa-monadic.d new file mode 100644 index 00000000..a688ee4b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fpa-monadic.d @@ -0,0 +1,202 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: FPA Monadic instructions +#as: -mfpu=fpa -mcpu=arm7m + +# Test FPA Monadic instructions +# This test should work for both big and little-endian assembly. + +.*: *file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> ee008100 ? mvfs f0, f0 +0+004 <[^>]*> ee008120 ? mvfsp f0, f0 +0+008 <[^>]*> ee008140 ? mvfsm f0, f0 +0+00c <[^>]*> ee008160 ? mvfsz f0, f0 +0+010 <[^>]*> ee008180 ? mvfd f0, f0 +0+014 <[^>]*> ee0081a0 ? mvfdp f0, f0 +0+018 <[^>]*> ee0081c0 ? mvfdm f0, f0 +0+01c <[^>]*> ee0081e0 ? mvfdz f0, f0 +0+020 <[^>]*> ee088100 ? mvfe f0, f0 +0+024 <[^>]*> ee088120 ? mvfep f0, f0 +0+028 <[^>]*> ee088140 ? mvfem f0, f0 +0+02c <[^>]*> ee088160 ? mvfez f0, f0 +0+030 <[^>]*> ee108100 ? mnfs f0, f0 +0+034 <[^>]*> ee108120 ? mnfsp f0, f0 +0+038 <[^>]*> ee108140 ? mnfsm f0, f0 +0+03c <[^>]*> ee108160 ? mnfsz f0, f0 +0+040 <[^>]*> ee108180 ? mnfd f0, f0 +0+044 <[^>]*> ee1081a0 ? mnfdp f0, f0 +0+048 <[^>]*> ee1081c0 ? mnfdm f0, f0 +0+04c <[^>]*> ee1081e0 ? mnfdz f0, f0 +0+050 <[^>]*> ee188100 ? mnfe f0, f0 +0+054 <[^>]*> ee188120 ? mnfep f0, f0 +0+058 <[^>]*> ee188140 ? mnfem f0, f0 +0+05c <[^>]*> ee188160 ? mnfez f0, f0 +0+060 <[^>]*> ee208100 ? abss f0, f0 +0+064 <[^>]*> ee208120 ? abssp f0, f0 +0+068 <[^>]*> ee208140 ? abssm f0, f0 +0+06c <[^>]*> ee208160 ? abssz f0, f0 +0+070 <[^>]*> ee208180 ? absd f0, f0 +0+074 <[^>]*> ee2081a0 ? absdp f0, f0 +0+078 <[^>]*> ee2081c0 ? absdm f0, f0 +0+07c <[^>]*> ee2081e0 ? absdz f0, f0 +0+080 <[^>]*> ee288100 ? abse f0, f0 +0+084 <[^>]*> ee288120 ? absep f0, f0 +0+088 <[^>]*> ee288140 ? absem f0, f0 +0+08c <[^>]*> ee288160 ? absez f0, f0 +0+090 <[^>]*> ee308100 ? rnds f0, f0 +0+094 <[^>]*> ee308120 ? rndsp f0, f0 +0+098 <[^>]*> ee308140 ? rndsm f0, f0 +0+09c <[^>]*> ee308160 ? rndsz f0, f0 +0+0a0 <[^>]*> ee308180 ? rndd f0, f0 +0+0a4 <[^>]*> ee3081a0 ? rnddp f0, f0 +0+0a8 <[^>]*> ee3081c0 ? rnddm f0, f0 +0+0ac <[^>]*> ee3081e0 ? rnddz f0, f0 +0+0b0 <[^>]*> ee388100 ? rnde f0, f0 +0+0b4 <[^>]*> ee388120 ? rndep f0, f0 +0+0b8 <[^>]*> ee388140 ? rndem f0, f0 +0+0bc <[^>]*> ee388160 ? rndez f0, f0 +0+0c0 <[^>]*> ee408100 ? sqts f0, f0 +0+0c4 <[^>]*> ee408120 ? sqtsp f0, f0 +0+0c8 <[^>]*> ee408140 ? sqtsm f0, f0 +0+0cc <[^>]*> ee408160 ? sqtsz f0, f0 +0+0d0 <[^>]*> ee408180 ? sqtd f0, f0 +0+0d4 <[^>]*> ee4081a0 ? sqtdp f0, f0 +0+0d8 <[^>]*> ee4081c0 ? sqtdm f0, f0 +0+0dc <[^>]*> ee4081e0 ? sqtdz f0, f0 +0+0e0 <[^>]*> ee488100 ? sqte f0, f0 +0+0e4 <[^>]*> ee488120 ? sqtep f0, f0 +0+0e8 <[^>]*> ee488140 ? sqtem f0, f0 +0+0ec <[^>]*> ee488160 ? sqtez f0, f0 +0+0f0 <[^>]*> ee508100 ? logs f0, f0 +0+0f4 <[^>]*> ee508120 ? logsp f0, f0 +0+0f8 <[^>]*> ee508140 ? logsm f0, f0 +0+0fc <[^>]*> ee508160 ? logsz f0, f0 +0+100 <[^>]*> ee508180 ? logd f0, f0 +0+104 <[^>]*> ee5081a0 ? logdp f0, f0 +0+108 <[^>]*> ee5081c0 ? logdm f0, f0 +0+10c <[^>]*> ee5081e0 ? logdz f0, f0 +0+110 <[^>]*> ee588100 ? loge f0, f0 +0+114 <[^>]*> ee588120 ? logep f0, f0 +0+118 <[^>]*> ee588140 ? logem f0, f0 +0+11c <[^>]*> ee588160 ? logez f0, f0 +0+120 <[^>]*> ee608100 ? lgns f0, f0 +0+124 <[^>]*> ee608120 ? lgnsp f0, f0 +0+128 <[^>]*> ee608140 ? lgnsm f0, f0 +0+12c <[^>]*> ee608160 ? lgnsz f0, f0 +0+130 <[^>]*> ee608180 ? lgnd f0, f0 +0+134 <[^>]*> ee6081a0 ? lgndp f0, f0 +0+138 <[^>]*> ee6081c0 ? lgndm f0, f0 +0+13c <[^>]*> ee6081e0 ? lgndz f0, f0 +0+140 <[^>]*> ee688100 ? lgne f0, f0 +0+144 <[^>]*> ee688120 ? lgnep f0, f0 +0+148 <[^>]*> ee688140 ? lgnem f0, f0 +0+14c <[^>]*> ee688160 ? lgnez f0, f0 +0+150 <[^>]*> ee708100 ? exps f0, f0 +0+154 <[^>]*> ee708120 ? expsp f0, f0 +0+158 <[^>]*> ee708140 ? expsm f0, f0 +0+15c <[^>]*> ee708160 ? expsz f0, f0 +0+160 <[^>]*> ee708180 ? expd f0, f0 +0+164 <[^>]*> ee7081a0 ? expdp f0, f0 +0+168 <[^>]*> ee7081c0 ? expdm f0, f0 +0+16c <[^>]*> ee7081e0 ? expdz f0, f0 +0+170 <[^>]*> ee788100 ? expe f0, f0 +0+174 <[^>]*> ee788120 ? expep f0, f0 +0+178 <[^>]*> ee788140 ? expem f0, f0 +0+17c <[^>]*> ee7081e0 ? expdz f0, f0 +0+180 <[^>]*> ee808100 ? sins f0, f0 +0+184 <[^>]*> ee808120 ? sinsp f0, f0 +0+188 <[^>]*> ee808140 ? sinsm f0, f0 +0+18c <[^>]*> ee808160 ? sinsz f0, f0 +0+190 <[^>]*> ee808180 ? sind f0, f0 +0+194 <[^>]*> ee8081a0 ? sindp f0, f0 +0+198 <[^>]*> ee8081c0 ? sindm f0, f0 +0+19c <[^>]*> ee8081e0 ? sindz f0, f0 +0+1a0 <[^>]*> ee888100 ? sine f0, f0 +0+1a4 <[^>]*> ee888120 ? sinep f0, f0 +0+1a8 <[^>]*> ee888140 ? sinem f0, f0 +0+1ac <[^>]*> ee888160 ? sinez f0, f0 +0+1b0 <[^>]*> ee908100 ? coss f0, f0 +0+1b4 <[^>]*> ee908120 ? cossp f0, f0 +0+1b8 <[^>]*> ee908140 ? cossm f0, f0 +0+1bc <[^>]*> ee908160 ? cossz f0, f0 +0+1c0 <[^>]*> ee908180 ? cosd f0, f0 +0+1c4 <[^>]*> ee9081a0 ? cosdp f0, f0 +0+1c8 <[^>]*> ee9081c0 ? cosdm f0, f0 +0+1cc <[^>]*> ee9081e0 ? cosdz f0, f0 +0+1d0 <[^>]*> ee988100 ? cose f0, f0 +0+1d4 <[^>]*> ee988120 ? cosep f0, f0 +0+1d8 <[^>]*> ee988140 ? cosem f0, f0 +0+1dc <[^>]*> ee988160 ? cosez f0, f0 +0+1e0 <[^>]*> eea08100 ? tans f0, f0 +0+1e4 <[^>]*> eea08120 ? tansp f0, f0 +0+1e8 <[^>]*> eea08140 ? tansm f0, f0 +0+1ec <[^>]*> eea08160 ? tansz f0, f0 +0+1f0 <[^>]*> eea08180 ? tand f0, f0 +0+1f4 <[^>]*> eea081a0 ? tandp f0, f0 +0+1f8 <[^>]*> eea081c0 ? tandm f0, f0 +0+1fc <[^>]*> eea081e0 ? tandz f0, f0 +0+200 <[^>]*> eea88100 ? tane f0, f0 +0+204 <[^>]*> eea88120 ? tanep f0, f0 +0+208 <[^>]*> eea88140 ? tanem f0, f0 +0+20c <[^>]*> eea88160 ? tanez f0, f0 +0+210 <[^>]*> eeb08100 ? asns f0, f0 +0+214 <[^>]*> eeb08120 ? asnsp f0, f0 +0+218 <[^>]*> eeb08140 ? asnsm f0, f0 +0+21c <[^>]*> eeb08160 ? asnsz f0, f0 +0+220 <[^>]*> eeb08180 ? asnd f0, f0 +0+224 <[^>]*> eeb081a0 ? asndp f0, f0 +0+228 <[^>]*> eeb081c0 ? asndm f0, f0 +0+22c <[^>]*> eeb081e0 ? asndz f0, f0 +0+230 <[^>]*> eeb88100 ? asne f0, f0 +0+234 <[^>]*> eeb88120 ? asnep f0, f0 +0+238 <[^>]*> eeb88140 ? asnem f0, f0 +0+23c <[^>]*> eeb88160 ? asnez f0, f0 +0+240 <[^>]*> eec08100 ? acss f0, f0 +0+244 <[^>]*> eec08120 ? acssp f0, f0 +0+248 <[^>]*> eec08140 ? acssm f0, f0 +0+24c <[^>]*> eec08160 ? acssz f0, f0 +0+250 <[^>]*> eec08180 ? acsd f0, f0 +0+254 <[^>]*> eec081a0 ? acsdp f0, f0 +0+258 <[^>]*> eec081c0 ? acsdm f0, f0 +0+25c <[^>]*> eec081e0 ? acsdz f0, f0 +0+260 <[^>]*> eec88100 ? acse f0, f0 +0+264 <[^>]*> eec88120 ? acsep f0, f0 +0+268 <[^>]*> eec88140 ? acsem f0, f0 +0+26c <[^>]*> eec88160 ? acsez f0, f0 +0+270 <[^>]*> eed08100 ? atns f0, f0 +0+274 <[^>]*> eed08120 ? atnsp f0, f0 +0+278 <[^>]*> eed08140 ? atnsm f0, f0 +0+27c <[^>]*> eed08160 ? atnsz f0, f0 +0+280 <[^>]*> eed08180 ? atnd f0, f0 +0+284 <[^>]*> eed081a0 ? atndp f0, f0 +0+288 <[^>]*> eed081c0 ? atndm f0, f0 +0+28c <[^>]*> eed081e0 ? atndz f0, f0 +0+290 <[^>]*> eed88100 ? atne f0, f0 +0+294 <[^>]*> eed88120 ? atnep f0, f0 +0+298 <[^>]*> eed88140 ? atnem f0, f0 +0+29c <[^>]*> eed88160 ? atnez f0, f0 +0+2a0 <[^>]*> eee08100 ? urds f0, f0 +0+2a4 <[^>]*> eee08120 ? urdsp f0, f0 +0+2a8 <[^>]*> eee08140 ? urdsm f0, f0 +0+2ac <[^>]*> eee08160 ? urdsz f0, f0 +0+2b0 <[^>]*> eee08180 ? urdd f0, f0 +0+2b4 <[^>]*> eee081a0 ? urddp f0, f0 +0+2b8 <[^>]*> eee081c0 ? urddm f0, f0 +0+2bc <[^>]*> eee081e0 ? urddz f0, f0 +0+2c0 <[^>]*> eee88100 ? urde f0, f0 +0+2c4 <[^>]*> eee88120 ? urdep f0, f0 +0+2c8 <[^>]*> eee88140 ? urdem f0, f0 +0+2cc <[^>]*> eee88160 ? urdez f0, f0 +0+2d0 <[^>]*> eef08100 ? nrms f0, f0 +0+2d4 <[^>]*> eef08120 ? nrmsp f0, f0 +0+2d8 <[^>]*> eef08140 ? nrmsm f0, f0 +0+2dc <[^>]*> eef08160 ? nrmsz f0, f0 +0+2e0 <[^>]*> eef08180 ? nrmd f0, f0 +0+2e4 <[^>]*> eef081a0 ? nrmdp f0, f0 +0+2e8 <[^>]*> eef081c0 ? nrmdm f0, f0 +0+2ec <[^>]*> eef081e0 ? nrmdz f0, f0 +0+2f0 <[^>]*> eef88100 ? nrme f0, f0 +0+2f4 <[^>]*> eef88120 ? nrmep f0, f0 +0+2f8 <[^>]*> eef88140 ? nrmem f0, f0 +0+2fc <[^>]*> eef88160 ? nrmez f0, f0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/fpa-monadic.s b/binutils-2.25/gas/testsuite/gas/arm/fpa-monadic.s new file mode 100644 index 00000000..2af03f4e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/fpa-monadic.s @@ -0,0 +1,210 @@ + .text + .globl F +F: + mvfs f0, f0 + mvfsp f0, f0 + mvfsm f0, f0 + mvfsz f0, f0 + mvfd f0, f0 + mvfdp f0, f0 + mvfdm f0, f0 + mvfdz f0, f0 + mvfe f0, f0 + mvfep f0, f0 + mvfem f0, f0 + mvfez f0, f0 + + mnfs f0, f0 + mnfsp f0, f0 + mnfsm f0, f0 + mnfsz f0, f0 + mnfd f0, f0 + mnfdp f0, f0 + mnfdm f0, f0 + mnfdz f0, f0 + mnfe f0, f0 + mnfep f0, f0 + mnfem f0, f0 + mnfez f0, f0 + + abss f0, f0 + abssp f0, f0 + abssm f0, f0 + abssz f0, f0 + absd f0, f0 + absdp f0, f0 + absdm f0, f0 + absdz f0, f0 + abse f0, f0 + absep f0, f0 + absem f0, f0 + absez f0, f0 + + rnds f0, f0 + rndsp f0, f0 + rndsm f0, f0 + rndsz f0, f0 + rndd f0, f0 + rnddp f0, f0 + rnddm f0, f0 + rnddz f0, f0 + rnde f0, f0 + rndep f0, f0 + rndem f0, f0 + rndez f0, f0 + + sqts f0, f0 + sqtsp f0, f0 + sqtsm f0, f0 + sqtsz f0, f0 + sqtd f0, f0 + sqtdp f0, f0 + sqtdm f0, f0 + sqtdz f0, f0 + sqte f0, f0 + sqtep f0, f0 + sqtem f0, f0 + sqtez f0, f0 + + logs f0, f0 + logsp f0, f0 + logsm f0, f0 + logsz f0, f0 + logd f0, f0 + logdp f0, f0 + logdm f0, f0 + logdz f0, f0 + loge f0, f0 + logep f0, f0 + logem f0, f0 + logez f0, f0 + + lgns f0, f0 + lgnsp f0, f0 + lgnsm f0, f0 + lgnsz f0, f0 + lgnd f0, f0 + lgndp f0, f0 + lgndm f0, f0 + lgndz f0, f0 + lgne f0, f0 + lgnep f0, f0 + lgnem f0, f0 + lgnez f0, f0 + + exps f0, f0 + expsp f0, f0 + expsm f0, f0 + expsz f0, f0 + expd f0, f0 + expdp f0, f0 + expdm f0, f0 + expdz f0, f0 + expe f0, f0 + expep f0, f0 + expem f0, f0 + expdz f0, f0 + + sins f0, f0 + sinsp f0, f0 + sinsm f0, f0 + sinsz f0, f0 + sind f0, f0 + sindp f0, f0 + sindm f0, f0 + sindz f0, f0 + sine f0, f0 + sinep f0, f0 + sinem f0, f0 + sinez f0, f0 + + coss f0, f0 + cossp f0, f0 + cossm f0, f0 + cossz f0, f0 + cosd f0, f0 + cosdp f0, f0 + cosdm f0, f0 + cosdz f0, f0 + cose f0, f0 + cosep f0, f0 + cosem f0, f0 + cosez f0, f0 + + tans f0, f0 + tansp f0, f0 + tansm f0, f0 + tansz f0, f0 + tand f0, f0 + tandp f0, f0 + tandm f0, f0 + tandz f0, f0 + tane f0, f0 + tanep f0, f0 + tanem f0, f0 + tanez f0, f0 + + asns f0, f0 + asnsp f0, f0 + asnsm f0, f0 + asnsz f0, f0 + asnd f0, f0 + asndp f0, f0 + asndm f0, f0 + asndz f0, f0 + asne f0, f0 + asnep f0, f0 + asnem f0, f0 + asnez f0, f0 + + acss f0, f0 + acssp f0, f0 + acssm f0, f0 + acssz f0, f0 + acsd f0, f0 + acsdp f0, f0 + acsdm f0, f0 + acsdz f0, f0 + acse f0, f0 + acsep f0, f0 + acsem f0, f0 + acsez f0, f0 + + atns f0, f0 + atnsp f0, f0 + atnsm f0, f0 + atnsz f0, f0 + atnd f0, f0 + atndp f0, f0 + atndm f0, f0 + atndz f0, f0 + atne f0, f0 + atnep f0, f0 + atnem f0, f0 + atnez f0, f0 + + urds f0, f0 + urdsp f0, f0 + urdsm f0, f0 + urdsz f0, f0 + urdd f0, f0 + urddp f0, f0 + urddm f0, f0 + urddz f0, f0 + urde f0, f0 + urdep f0, f0 + urdem f0, f0 + urdez f0, f0 + + nrms f0, f0 + nrmsp f0, f0 + nrmsm f0, f0 + nrmsz f0, f0 + nrmd f0, f0 + nrmdp f0, f0 + nrmdm f0, f0 + nrmdz f0, f0 + nrme f0, f0 + nrmep f0, f0 + nrmem f0, f0 + nrmez f0, f0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/got_prel.d b/binutils-2.25/gas/testsuite/gas/arm/got_prel.d new file mode 100644 index 00000000..8360fb96 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/got_prel.d @@ -0,0 +1,19 @@ +# name: R_ARM_GOT_PREL relocation +# source: got_prel.s +# as: -march=armv5te -meabi=5 +# readelf: -x 4 -r +# target: *-*-*eabi* *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl* + +Relocation section '.rel.text.foo' at offset 0x3f0 contains 1 entries: + Offset Info Type Sym.Value Sym. Name +00000010 00000c60 R_ARM_GOT_PREL 00000000 i + +Relocation section '.rel.ARM.exidx.text.foo' at offset 0x3f8 contains 2 entries: + Offset Info Type Sym.Value Sym. Name +00000000 0000042a R_ARM_PREL31 00000000 .text.foo +00000000 00000d00 R_ARM_NONE 00000000 __aeabi_unwind_cpp_pr0 + +Hex dump of section '.text.foo': + NOTE: This section has relocations against it, but these have NOT been applied to this dump. + 0x00000000 034b7b44 1b681a68 1860101c 7047c046 .K{D.h.h.`..pG.F + 0x00000010 0a000000 .... diff --git a/binutils-2.25/gas/testsuite/gas/arm/got_prel.s b/binutils-2.25/gas/testsuite/gas/arm/got_prel.s new file mode 100644 index 00000000..9628d472 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/got_prel.s @@ -0,0 +1,23 @@ + .code 16 + .text +.Ltext0: + .section .text.foo,"ax",%progbits + .align 2 + .global foo + .code 16 + .thumb_func + .type foo, %function +foo: + .fnstart + ldr r3, .L3 +.LPIC0: + add r3, pc + ldr r3, [r3] + ldr r2, [r3] + str r0, [r3] + mov r0, r2 + bx lr + .align 2 +.L3: + .word i(GOT_PREL) + (. - (.LPIC0+4)) + .fnend diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d new file mode 100644 index 00000000..bd469230 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (alu) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#error-output: group-reloc-alu-encoding-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l new file mode 100644 index 00000000..fe8827ce --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l @@ -0,0 +1,81 @@ +[^:]*: Assembler messages: +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:23: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:24: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:25: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:26: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:28: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:29: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:30: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable +[^:]*:31: Error: the offset 0x00011001 is not representable diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s new file mode 100644 index 00000000..bdde4ad4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s @@ -0,0 +1,35 @@ +@ Tests that should fail for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym + \offset) + \insn r0, r0, #:pc_g1:(\sym + \offset) + \insn r0, r0, #:pc_g2:(\sym + \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym + \offset) + \insn r0, r0, #:pc_g1_nc:(\sym + \offset) + + \insn r0, r0, #:sb_g0:(\sym + \offset) + \insn r0, r0, #:sb_g1:(\sym + \offset) + \insn r0, r0, #:sb_g2:(\sym + \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym + \offset) + \insn r0, r0, #:sb_g1_nc:(\sym + \offset) + + .endm + + alutest add f 0x11001 + alutest add localsym 0x11001 + alutest adds f 0x11001 + alutest adds localsym 0x11001 + + alutest add f "-0x11001" + alutest add localsym "-0x11001" + alutest adds f "-0x11001" + alutest adds localsym "-0x11001" + +localsym: + mov r0, #0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d new file mode 100644 index 00000000..808bc05f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (alu) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-alu-parsing-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l new file mode 100644 index 00000000..1c27ad02 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: shift expression expected -- `sub r0,r0,#:pc_g0:\(foo\)' +[^:]*:7: Error: shift expression expected -- `subs r0,r0,#:pc_g0:\(foo\)' +[^:]*:10: Error: unknown group relocation -- `add r0,r0,#:pc_g2_nc:\(foo\)' +[^:]*:11: Error: unknown group relocation -- `add r0,r0,#:sb_g2_nc:\(foo\)' diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s new file mode 100644 index 00000000..70a62ace --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s @@ -0,0 +1,12 @@ +@ Tests that should fail for ALU group relocations. + + .text + +@ Group relocs aren't allowed on SUB(S) instructions... + sub r0, r0, #:pc_g0:(foo) + subs r0, r0, #:pc_g0:(foo) + +@ Some nonexistent relocations: + add r0, r0, #:pc_g2_nc:(foo) + add r0, r0, #:sb_g2_nc:(foo) + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu.d new file mode 100644 index 00000000..327de740 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu.d @@ -0,0 +1,168 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#name: Group relocation tests (alu) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 10: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 14: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 18: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 1c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 20: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 24: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 28: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 2c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 30: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 34: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 38: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 3c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 40: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 44: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 48: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100 + 4c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 50: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 54: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 58: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 5c: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 60: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 64: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 68: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 6c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 70: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 74: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 78: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 7c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 80: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 84: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 88: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 8c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 90: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 94: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 98: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100 + 9c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + a8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ac: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b0: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b4: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + b8: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + bc: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c0: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c4: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + c8: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + cc: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d0: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d4: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + d8: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + dc: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e0: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e4: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + e8: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100 + ec: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f0: R_ARM_ALU_PC_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f4: R_ARM_ALU_PC_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + f8: R_ARM_ALU_PC_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + fc: R_ARM_ALU_PC_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 100: R_ARM_ALU_PC_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 104: R_ARM_ALU_SB_G0 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 108: R_ARM_ALU_SB_G1 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 10c: R_ARM_ALU_SB_G2 f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 110: R_ARM_ALU_SB_G0_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 114: R_ARM_ALU_SB_G1_NC f +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 118: R_ARM_ALU_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 11c: R_ARM_ALU_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 120: R_ARM_ALU_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 124: R_ARM_ALU_PC_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 128: R_ARM_ALU_PC_G1_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 12c: R_ARM_ALU_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 130: R_ARM_ALU_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 134: R_ARM_ALU_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 138: R_ARM_ALU_SB_G0_NC localsym +0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100 + 13c: R_ARM_ALU_SB_G1_NC localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu.s new file mode 100644 index 00000000..696f1dac --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-alu.s @@ -0,0 +1,39 @@ +@ Tests for ALU group relocations. + + .text + + .macro alutest insn sym offset + + \insn r0, r0, #:pc_g0:(\sym \offset) + \insn r0, r0, #:pc_g1:(\sym \offset) + +@ Try this one without the hash; it should still work. + \insn r0, r0, :pc_g2:(\sym \offset) + + \insn r0, r0, #:pc_g0_nc:(\sym \offset) + \insn r0, r0, #:pc_g1_nc:(\sym \offset) + + \insn r0, r0, #:sb_g0:(\sym \offset) + \insn r0, r0, #:sb_g1:(\sym \offset) + \insn r0, r0, #:sb_g2:(\sym \offset) + + \insn r0, r0, #:sb_g0_nc:(\sym \offset) + \insn r0, r0, #:sb_g1_nc:(\sym \offset) + + .endm + + alutest add f "+ 0x100" + alutest add localsym "+ 0x100" + alutest adds f "+ 0x100" + alutest adds localsym "+ 0x100" + +@ The following should cause the insns to be switched to SUB(S). + + alutest add f "- 0x100" + alutest add localsym "- 0x100" + alutest adds f "- 0x100" + alutest adds localsym "- 0x100" + +localsym: + mov r0, #0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d new file mode 100644 index 00000000..cdf0047d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldc) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#error-output: group-reloc-ldc-encoding-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l new file mode 100644 index 00000000..22e53a59 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l @@ -0,0 +1,721 @@ +[^:]*: Assembler messages: +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) +[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s new file mode 100644 index 00000000..5ab27c25 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s @@ -0,0 +1,169 @@ +@ LDC group relocation tests that are supposed to fail during encoding. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store cst + + \load 0, c0, [r0, #:pc_g0:(f + \cst)] + \load 0, c0, [r0, #:pc_g1:(f + \cst)] + \load 0, c0, [r0, #:pc_g2:(f + \cst)] + + \load 0, c0, [r0, #:sb_g0:(f + \cst)] + \load 0, c0, [r0, #:sb_g1:(f + \cst)] + \load 0, c0, [r0, #:sb_g2:(f + \cst)] + + \store 0, c0, [r0, #:pc_g0:(f + \cst)] + \store 0, c0, [r0, #:pc_g1:(f + \cst)] + \store 0, c0, [r0, #:pc_g2:(f + \cst)] + + \store 0, c0, [r0, #:sb_g0:(f + \cst)] + \store 0, c0, [r0, #:sb_g1:(f + \cst)] + \store 0, c0, [r0, #:sb_g2:(f + \cst)] + + \load 0, c0, [r0, #:pc_g0:(f - \cst)] + \load 0, c0, [r0, #:pc_g1:(f - \cst)] + \load 0, c0, [r0, #:pc_g2:(f - \cst)] + + \load 0, c0, [r0, #:sb_g0:(f - \cst)] + \load 0, c0, [r0, #:sb_g1:(f - \cst)] + \load 0, c0, [r0, #:sb_g2:(f - \cst)] + + \store 0, c0, [r0, #:pc_g0:(f - \cst)] + \store 0, c0, [r0, #:pc_g1:(f - \cst)] + \store 0, c0, [r0, #:pc_g2:(f - \cst)] + + \store 0, c0, [r0, #:sb_g0:(f - \cst)] + \store 0, c0, [r0, #:sb_g1:(f - \cst)] + \store 0, c0, [r0, #:sb_g2:(f - \cst)] + + .endm + + ldctest ldc stc 0x1 + ldctest ldcl stcl 0x1 + ldctest ldc2 stc2 0x1 + ldctest ldc2l stc2l 0x1 + + ldctest ldc stc 0x808 + ldctest ldcl stcl 0x808 + ldctest ldc2 stc2 0x808 + ldctest ldc2l stc2l 0x808 + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store cst + + \load f0, [r0, #:pc_g0:(f + \cst)] + \load f0, [r0, #:pc_g1:(f + \cst)] + \load f0, [r0, #:pc_g2:(f + \cst)] + + \load f0, [r0, #:sb_g0:(f + \cst)] + \load f0, [r0, #:sb_g1:(f + \cst)] + \load f0, [r0, #:sb_g2:(f + \cst)] + + \store f0, [r0, #:pc_g0:(f + \cst)] + \store f0, [r0, #:pc_g1:(f + \cst)] + \store f0, [r0, #:pc_g2:(f + \cst)] + + \store f0, [r0, #:sb_g0:(f + \cst)] + \store f0, [r0, #:sb_g1:(f + \cst)] + \store f0, [r0, #:sb_g2:(f + \cst)] + + \load f0, [r0, #:pc_g0:(f - \cst)] + \load f0, [r0, #:pc_g1:(f - \cst)] + \load f0, [r0, #:pc_g2:(f - \cst)] + + \load f0, [r0, #:sb_g0:(f - \cst)] + \load f0, [r0, #:sb_g1:(f - \cst)] + \load f0, [r0, #:sb_g2:(f - \cst)] + + \store f0, [r0, #:pc_g0:(f - \cst)] + \store f0, [r0, #:pc_g1:(f - \cst)] + \store f0, [r0, #:pc_g2:(f - \cst)] + + \store f0, [r0, #:sb_g0:(f - \cst)] + \store f0, [r0, #:sb_g1:(f - \cst)] + \store f0, [r0, #:sb_g2:(f - \cst)] + + .endm + + fpa_test ldfs stfs 0x1 + fpa_test ldfd stfd 0x1 + fpa_test ldfe stfe 0x1 + fpa_test ldfp stfp 0x1 + + fpa_test ldfs stfs 0x808 + fpa_test ldfd stfd 0x808 + fpa_test ldfe stfe 0x808 + fpa_test ldfp stfp 0x808 + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg cst + + \load \reg, [r0, #:pc_g0:(f + \cst)] + \load \reg, [r0, #:pc_g1:(f + \cst)] + \load \reg, [r0, #:pc_g2:(f + \cst)] + + \load \reg, [r0, #:sb_g0:(f + \cst)] + \load \reg, [r0, #:sb_g1:(f + \cst)] + \load \reg, [r0, #:sb_g2:(f + \cst)] + + \store \reg, [r0, #:pc_g0:(f + \cst)] + \store \reg, [r0, #:pc_g1:(f + \cst)] + \store \reg, [r0, #:pc_g2:(f + \cst)] + + \store \reg, [r0, #:sb_g0:(f + \cst)] + \store \reg, [r0, #:sb_g1:(f + \cst)] + \store \reg, [r0, #:sb_g2:(f + \cst)] + + \load \reg, [r0, #:pc_g0:(f - \cst)] + \load \reg, [r0, #:pc_g1:(f - \cst)] + \load \reg, [r0, #:pc_g2:(f - \cst)] + + \load \reg, [r0, #:sb_g0:(f - \cst)] + \load \reg, [r0, #:sb_g1:(f - \cst)] + \load \reg, [r0, #:sb_g2:(f - \cst)] + + \store \reg, [r0, #:pc_g0:(f - \cst)] + \store \reg, [r0, #:pc_g1:(f - \cst)] + \store \reg, [r0, #:pc_g2:(f - \cst)] + + \store \reg, [r0, #:sb_g0:(f - \cst)] + \store \reg, [r0, #:sb_g1:(f - \cst)] + \store \reg, [r0, #:sb_g2:(f - \cst)] + + .endm + + vfp_test flds fsts s0 0x1 + vfp_test flds fsts s0 0x808 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 0x1 + vfp_test fldd fstd d0 0x808 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 0x1 + vfp_test vldr vstr d0 0x808 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 0x1 + vfp_test cfldrd cfstrd mvd0 0x1 + vfp_test cfldr32 cfstr32 mvfx0 0x1 + vfp_test cfldr64 cfstr64 mvdx0 0x1 + + vfp_test cfldrs cfstrs mvf0 0x808 + vfp_test cfldrd cfstrd mvd0 0x808 + vfp_test cfldr32 cfstr32 mvfx0 0x808 + vfp_test cfldr64 cfstr64 mvdx0 0x808 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d new file mode 100644 index 00000000..09e32997 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldc) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldc-parsing-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l new file mode 100644 index 00000000..238d94db --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l @@ -0,0 +1,147 @@ +[^:]*: Assembler messages: +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]' +[^:]*:54: Error: too many positional arguments +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]' +[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]' +[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s new file mode 100644 index 00000000..a815f5de --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s @@ -0,0 +1,67 @@ +@ Tests for LDC group relocations that are meant to fail during parsing. + + .macro ldctest insn reg + + \insn 0, \reg, [r0, #:pc_g0_nc:(sym)] + \insn 0, \reg, [r0, #:pc_g1_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g0_nc:(sym)] + \insn 0, \reg, [r0, #:sb_g1_nc:(sym)] + + \insn 0, \reg, [r0, #:foo:(sym)] + + .endm + + .macro ldctest2 insn reg + + \insn \reg, [r0, #:pc_g0_nc:(sym)] + \insn \reg, [r0, #:pc_g1_nc:(sym)] + \insn \reg, [r0, #:sb_g0_nc:(sym)] + \insn \reg, [r0, #:sb_g1_nc:(sym)] + + \insn \reg, [r0, #:foo:(sym)] + + .endm + + ldctest ldc c0 + ldctest ldcl c0 + ldctest ldc2 c0 + ldctest ldc2l c0 + + ldctest stc c0 + ldctest stcl c0 + ldctest stc2 c0 + ldctest stc2l c0 + + .fpu fpa + + ldctest2 ldfs f0 + ldctest2 stfs f0 + ldctest2 ldfd f0 + ldctest2 stfd f0 + ldctest2 ldfe f0 + ldctest2 stfe f0 + ldctest2 ldfp f0 + ldctest2 stfp f0 + + .fpu vfp + + ldctest2 flds s0 + ldctest2 fsts s0 + + ldctest2 fldd d0 + ldctest2 fstd d0 + + ldctest2 vldr d0 FIXME + ldctest2 vstr d0 + + .cpu ep9312 + + ldctest2 cfldrs mvf0 + ldctest2 cfstrs mvf0 + ldctest2 cfldrd mvd0 + ldctest2 cfstrd mvd0 + ldctest2 cfldr32 mvfx0 + ldctest2 cfstr32 mvfx0 + ldctest2 cfldr64 mvdx0 + ldctest2 cfstr64 mvdx0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc.d new file mode 100644 index 00000000..5c6c5e0d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc.d @@ -0,0 +1,727 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#name: Group relocation tests (ldc) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].* + 0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].* + 4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].* + 8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].* + c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].* + 10: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\].* + 14: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\].* + 18: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\].* + 1c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\].* + 20: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\].* + 24: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\].* + 28: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\].* + 2c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].* + 30: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].* + 34: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].* + 38: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].* + 3c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].* + 40: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\].* + 44: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\].* + 48: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\].* + 4c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\].* + 50: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\].* + 54: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\].* + 58: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\].* + 5c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\].* + 60: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\].* + 64: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\].* + 68: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\].* + 6c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\].* + 70: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\].* + 74: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\].* + 78: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\].* + 7c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\].* + 80: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\].* + 84: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\].* + 88: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\].* + 8c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\].* + 90: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\].* + 94: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\].* + 98: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\].* + 9c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\].* + a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\].* + a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\].* + a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\].* + ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\].* + b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\].* + b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\].* + b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\].* + bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].* + c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].* + c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].* + c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].* + cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].* + d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\].* + d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\].* + d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\].* + dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\].* + e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\].* + e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\].* + e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\].* + ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].* + f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].* + f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].* + f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].* + fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].* + 100: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\].* + 104: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\].* + 108: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\].* + 10c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\].* + 110: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\].* + 114: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\].* + 118: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\].* + 11c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\].* + 120: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\].* + 124: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\].* + 128: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\].* + 12c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\].* + 130: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\].* + 134: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\].* + 138: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\].* + 13c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\].* + 140: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\].* + 144: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\].* + 148: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\].* + 14c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\].* + 150: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\].* + 154: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\].* + 158: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\].* + 15c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\].* + 160: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\].* + 164: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\].* + 168: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\].* + 16c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\].* + 170: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\].* + 174: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\].* + 178: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\].* + 17c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\].* + 180: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\].* + 184: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\].* + 188: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\].* + 18c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\].* + 190: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\].* + 194: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\].* + 198: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\].* + 19c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\].* + 1a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\].* + 1a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\].* + 1a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\].* + 1ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\].* + 1b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\].* + 1b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\].* + 1b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\].* + 1bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\].* + 1c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\].* + 1c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\].* + 1c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\].* + 1cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\].* + 1d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\].* + 1d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\].* + 1d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\].* + 1dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\].* + 1e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\].* + 1e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\].* + 1e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\].* + 1ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\].* + 1f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\].* + 1f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\].* + 1f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\].* + 1fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\].* + 200: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\].* + 204: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\].* + 208: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\].* + 20c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\].* + 210: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\].* + 214: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\].* + 218: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\].* + 21c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\].* + 220: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\].* + 224: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\].* + 228: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\].* + 22c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\].* + 230: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\].* + 234: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\].* + 238: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\].* + 23c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\].* + 240: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\].* + 244: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\].* + 248: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\].* + 24c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\].* + 250: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\].* + 254: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\].* + 258: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\].* + 25c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\].* + 260: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\].* + 264: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\].* + 268: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\].* + 26c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\].* + 270: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\].* + 274: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\].* + 278: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\].* + 27c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\].* + 280: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\].* + 284: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\].* + 288: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\].* + 28c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\].* + 290: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\].* + 294: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\].* + 298: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\].* + 29c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\].* + 2a0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\].* + 2a4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\].* + 2a8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\].* + 2ac: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\].* + 2b0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\].* + 2b4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\].* + 2b8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\].* + 2bc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\].* + 2c0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\].* + 2c4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\].* + 2c8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\].* + 2cc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\].* + 2d0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\].* + 2d4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\].* + 2d8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\].* + 2dc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\].* + 2e0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\].* + 2e4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\].* + 2e8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\].* + 2ec: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\].* + 2f0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\].* + 2f4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\].* + 2f8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\].* + 2fc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].* + 300: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].* + 304: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].* + 308: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].* + 30c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].* + 310: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900a85 (vldr|flds) s0, \[r0, #532\].* + 314: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 (vstr|fsts) s0, \[r0, #532\].* + 318: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 (vstr|fsts) s0, \[r0, #532\].* + 31c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 (vstr|fsts) s0, \[r0, #532\].* + 320: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800a85 (vstr|fsts) s0, \[r0, #532\].* + 324: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800a85 (vstr|fsts) s0, \[r0, #532\].* + 328: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800a85 (vstr|fsts) s0, \[r0, #532\].* + 32c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].* + 330: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].* + 334: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].* + 338: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].* + 33c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].* + 340: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100a85 (vldr|flds) s0, \[r0, #-532\].* + 344: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 (vstr|fsts) s0, \[r0, #-532\].* + 348: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 (vstr|fsts) s0, \[r0, #-532\].* + 34c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 (vstr|fsts) s0, \[r0, #-532\].* + 350: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000a85 (vstr|fsts) s0, \[r0, #-532\].* + 354: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000a85 (vstr|fsts) s0, \[r0, #-532\].* + 358: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000a85 (vstr|fsts) s0, \[r0, #-532\].* + 35c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 360: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 364: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 368: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 36c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 370: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 374: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 378: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 37c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 380: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 384: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 388: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 38c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 390: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 394: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 398: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 39c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 3a0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 3a4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 3a8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 3ac: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 3b0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 3b4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 3b8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 3bc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 3c0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 3c4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 3c8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 3cc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 3d0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\].* + 3d4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 3d8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 3dc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 3e0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 3e4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 3e8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\].* + 3ec: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 3f0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 3f4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 3f8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 3fc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 400: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\].* + 404: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 408: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 40c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 410: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 414: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 418: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\].* + 41c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].* + 420: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].* + 424: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].* + 428: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].* + 42c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].* + 430: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\].* + 434: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].* + 438: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].* + 43c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].* + 440: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].* + 444: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].* + 448: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\].* + 44c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].* + 450: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].* + 454: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].* + 458: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].* + 45c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].* + 460: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\].* + 464: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].* + 468: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].* + 46c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].* + 470: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].* + 474: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].* + 478: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\].* + 47c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].* + 480: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].* + 484: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].* + 488: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].* + 48c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].* + 490: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\].* + 494: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].* + 498: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].* + 49c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].* + 4a0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].* + 4a4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].* + 4a8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\].* + 4ac: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].* + 4b0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].* + 4b4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].* + 4b8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].* + 4bc: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].* + 4c0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\].* + 4c4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].* + 4c8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].* + 4cc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].* + 4d0: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].* + 4d4: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].* + 4d8: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\].* + 4dc: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].* + 4e0: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].* + 4e4: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].* + 4e8: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].* + 4ec: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].* + 4f0: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\].* + 4f4: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].* + 4f8: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].* + 4fc: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].* + 500: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].* + 504: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].* + 508: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\].* + 50c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].* + 510: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].* + 514: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].* + 518: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].* + 51c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].* + 520: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\].* + 524: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].* + 528: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].* + 52c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].* + 530: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].* + 534: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].* + 538: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\].* + 53c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].* + 540: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].* + 544: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].* + 548: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].* + 54c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].* + 550: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\].* + 554: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].* + 558: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].* + 55c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].* + 560: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].* + 564: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].* + 568: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\].* + 56c: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].* + 570: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].* + 574: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].* + 578: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].* + 57c: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].* + 580: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\].* + 584: R_ARM_LDC_SB_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].* + 588: R_ARM_LDC_PC_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].* + 58c: R_ARM_LDC_PC_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].* + 590: R_ARM_LDC_PC_G2 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].* + 594: R_ARM_LDC_SB_G0 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].* + 598: R_ARM_LDC_SB_G1 f +0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\].* + 59c: R_ARM_LDC_SB_G2 f diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc.s new file mode 100644 index 00000000..df27aaf5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldc.s @@ -0,0 +1,151 @@ +@ LDC group relocation tests. + + .text + +@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L + + .macro ldctest load store + + \load 0, c0, [r0, #:pc_g0:(f + 0x214)] + \load 0, c0, [r0, #:pc_g1:(f + 0x214)] + \load 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f + 0x214)] + \load 0, c0, [r0, #:sb_g1:(f + 0x214)] + \load 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f + 0x214)] + \store 0, c0, [r0, #:pc_g1:(f + 0x214)] + \store 0, c0, [r0, #:pc_g2:(f + 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f + 0x214)] + \store 0, c0, [r0, #:sb_g1:(f + 0x214)] + \store 0, c0, [r0, #:sb_g2:(f + 0x214)] + + \load 0, c0, [r0, #:pc_g0:(f - 0x214)] + \load 0, c0, [r0, #:pc_g1:(f - 0x214)] + \load 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \load 0, c0, [r0, #:sb_g0:(f - 0x214)] + \load 0, c0, [r0, #:sb_g1:(f - 0x214)] + \load 0, c0, [r0, #:sb_g2:(f - 0x214)] + + \store 0, c0, [r0, #:pc_g0:(f - 0x214)] + \store 0, c0, [r0, #:pc_g1:(f - 0x214)] + \store 0, c0, [r0, #:pc_g2:(f - 0x214)] + + \store 0, c0, [r0, #:sb_g0:(f - 0x214)] + \store 0, c0, [r0, #:sb_g1:(f - 0x214)] + \store 0, c0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + ldctest ldc stc + ldctest ldcl stcl + ldctest ldc2 stc2 + ldctest ldc2l stc2l + +@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP + + .fpu fpa + + .macro fpa_test load store + + \load f0, [r0, #:pc_g0:(f + 0x214)] + \load f0, [r0, #:pc_g1:(f + 0x214)] + \load f0, [r0, #:pc_g2:(f + 0x214)] + + \load f0, [r0, #:sb_g0:(f + 0x214)] + \load f0, [r0, #:sb_g1:(f + 0x214)] + \load f0, [r0, #:sb_g2:(f + 0x214)] + + \store f0, [r0, #:pc_g0:(f + 0x214)] + \store f0, [r0, #:pc_g1:(f + 0x214)] + \store f0, [r0, #:pc_g2:(f + 0x214)] + + \store f0, [r0, #:sb_g0:(f + 0x214)] + \store f0, [r0, #:sb_g1:(f + 0x214)] + \store f0, [r0, #:sb_g2:(f + 0x214)] + + \load f0, [r0, #:pc_g0:(f - 0x214)] + \load f0, [r0, #:pc_g1:(f - 0x214)] + \load f0, [r0, #:pc_g2:(f - 0x214)] + + \load f0, [r0, #:sb_g0:(f - 0x214)] + \load f0, [r0, #:sb_g1:(f - 0x214)] + \load f0, [r0, #:sb_g2:(f - 0x214)] + + \store f0, [r0, #:pc_g0:(f - 0x214)] + \store f0, [r0, #:pc_g1:(f - 0x214)] + \store f0, [r0, #:pc_g2:(f - 0x214)] + + \store f0, [r0, #:sb_g0:(f - 0x214)] + \store f0, [r0, #:sb_g1:(f - 0x214)] + \store f0, [r0, #:sb_g2:(f - 0x214)] + + .endm + + fpa_test ldfs stfs + fpa_test ldfd stfd + fpa_test ldfe stfe + fpa_test ldfp stfp + +@ FLDS/FSTS + + .fpu vfp + + .macro vfp_test load store reg + + \load \reg, [r0, #:pc_g0:(f + 0x214)] + \load \reg, [r0, #:pc_g1:(f + 0x214)] + \load \reg, [r0, #:pc_g2:(f + 0x214)] + + \load \reg, [r0, #:sb_g0:(f + 0x214)] + \load \reg, [r0, #:sb_g1:(f + 0x214)] + \load \reg, [r0, #:sb_g2:(f + 0x214)] + + \store \reg, [r0, #:pc_g0:(f + 0x214)] + \store \reg, [r0, #:pc_g1:(f + 0x214)] + \store \reg, [r0, #:pc_g2:(f + 0x214)] + + \store \reg, [r0, #:sb_g0:(f + 0x214)] + \store \reg, [r0, #:sb_g1:(f + 0x214)] + \store \reg, [r0, #:sb_g2:(f + 0x214)] + + \load \reg, [r0, #:pc_g0:(f - 0x214)] + \load \reg, [r0, #:pc_g1:(f - 0x214)] + \load \reg, [r0, #:pc_g2:(f - 0x214)] + + \load \reg, [r0, #:sb_g0:(f - 0x214)] + \load \reg, [r0, #:sb_g1:(f - 0x214)] + \load \reg, [r0, #:sb_g2:(f - 0x214)] + + \store \reg, [r0, #:pc_g0:(f - 0x214)] + \store \reg, [r0, #:pc_g1:(f - 0x214)] + \store \reg, [r0, #:pc_g2:(f - 0x214)] + + \store \reg, [r0, #:sb_g0:(f - 0x214)] + \store \reg, [r0, #:sb_g1:(f - 0x214)] + \store \reg, [r0, #:sb_g2:(f - 0x214)] + + .endm + + vfp_test flds fsts s0 + +@ FLDD/FSTD + + vfp_test fldd fstd d0 + +@ VLDR/VSTR + + vfp_test vldr vstr d0 + +@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64 + + .cpu ep9312 + + vfp_test cfldrs cfstrs mvf0 + vfp_test cfldrd cfstrd mvd0 + vfp_test cfldr32 cfstr32 mvfx0 + vfp_test cfldr64 cfstr64 mvdx0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d new file mode 100644 index 00000000..cfa0a0cc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldr) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#error-output: group-reloc-ldr-encoding-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l new file mode 100644 index 00000000..276a341d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l @@ -0,0 +1,97 @@ +[^:]*: Assembler messages: +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s new file mode 100644 index 00000000..3c528f19 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s @@ -0,0 +1,39 @@ +@ Tests that are supposed to fail during encoding +@ for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all fail. + + ldrtest ldr str f "+ 4096" + ldrtest ldrb strb f "+ 4096" + ldrtest ldr str f "- 4096" + ldrtest ldrb strb f "- 4096" + + ldrtest ldr str localsym "+ 4096" + ldrtest ldrb strb localsym "+ 4096" + ldrtest ldr str localsym "- 4096" + ldrtest ldrb strb localsym "- 4096" + +localsym: + mov r0, #0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d new file mode 100644 index 00000000..fa0941e8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldr) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldr-parsing-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l new file mode 100644 index 00000000..316a6a6c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:29: Error: unknown group relocation -- `ldr r0,\[r0,#:foo:\(f\)\]' +[^:]*:30: Error: unknown group relocation -- `str r0,\[r0,#:foo:\(f\)\]' +[^:]*:31: Error: unknown group relocation -- `ldrb r0,\[r0,#:foo:\(f\)\]' +[^:]*:32: Error: unknown group relocation -- `strb r0,\[r0,#:foo:\(f\)\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s new file mode 100644 index 00000000..c7d0ba75 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s @@ -0,0 +1,33 @@ +@ Tests that are supposed to fail during parsing of LDR group relocations. + + .text + +@ No NC variants exist for the LDR relocations. + + ldr r0, [r0, #:pc_g0_nc:(f)] + ldr r0, [r0, #:pc_g1_nc:(f)] + ldr r0, [r0, #:sb_g0_nc:(f)] + ldr r0, [r0, #:sb_g1_nc:(f)] + + str r0, [r0, #:pc_g0_nc:(f)] + str r0, [r0, #:pc_g1_nc:(f)] + str r0, [r0, #:sb_g0_nc:(f)] + str r0, [r0, #:sb_g1_nc:(f)] + + ldrb r0, [r0, #:pc_g0_nc:(f)] + ldrb r0, [r0, #:pc_g1_nc:(f)] + ldrb r0, [r0, #:sb_g0_nc:(f)] + ldrb r0, [r0, #:sb_g1_nc:(f)] + + strb r0, [r0, #:pc_g0_nc:(f)] + strb r0, [r0, #:pc_g1_nc:(f)] + strb r0, [r0, #:sb_g0_nc:(f)] + strb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + + ldr r0, [r0, #:foo:(f)] + str r0, [r0, #:foo:(f)] + ldrb r0, [r0, #:foo:(f)] + strb r0, [r0, #:foo:(f)] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr.d new file mode 100644 index 00000000..cd41b264 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr.d @@ -0,0 +1,200 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#name: Group relocation tests (ldr) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + 0: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + 4: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + 8: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + 10: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + 14: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + 18: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + 1c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + 20: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + 24: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + 28: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + 2c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 30: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 34: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 38: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 3c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 40: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 44: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 48: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 4c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 50: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 54: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 58: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 5c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 60: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 64: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 68: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 6c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 70: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 74: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 78: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 7c: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 80: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 84: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 88: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 8c: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 90: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 94: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 98: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 9c: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + a0: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + a4: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + a8: R_ARM_LDR_PC_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + ac: R_ARM_LDR_PC_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + b0: R_ARM_LDR_PC_G2 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + b4: R_ARM_LDR_SB_G0 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + b8: R_ARM_LDR_SB_G1 f +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + bc: R_ARM_LDR_SB_G2 f +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + c0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + c4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + c8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + cc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + d0: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\].* + d4: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + d8: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + dc: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + e0: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + e4: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + e8: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\].* + ec: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + f0: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + f4: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + f8: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + fc: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 100: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\].* + 104: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 108: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 10c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 110: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 114: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 118: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\].* + 11c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 120: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 124: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 128: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 12c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 130: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\].* + 134: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 138: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 13c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 140: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 144: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 148: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\].* + 14c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 150: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 154: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 158: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 15c: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 160: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\].* + 164: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + 168: R_ARM_LDR_PC_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + 16c: R_ARM_LDR_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + 170: R_ARM_LDR_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + 174: R_ARM_LDR_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + 178: R_ARM_LDR_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\].* + 17c: R_ARM_LDR_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr.s new file mode 100644 index 00000000..389042d7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldr.s @@ -0,0 +1,41 @@ +@ Tests for LDR group relocations. + + .text + + .macro ldrtest load store sym offset + + \load r0, [r0, #:pc_g0:(\sym \offset)] + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + \store r0, [r0, #:pc_g0:(\sym \offset)] + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend. +@ So these should all (just) work. + + ldrtest ldr str f "+ 4095" + ldrtest ldrb strb f "+ 4095" + ldrtest ldr str f "- 4095" + ldrtest ldrb strb f "- 4095" + +@ The same as the above, but for a local symbol. These should not be +@ resolved by the assembler but instead left to the linker. + + ldrtest ldr str localsym "+ 4095" + ldrtest ldrb strb localsym "+ 4095" + ldrtest ldr str localsym "- 4095" + ldrtest ldrb strb localsym "- 4095" + +localsym: + mov r0, #0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d new file mode 100644 index 00000000..0c0683a1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, encoding failures (ldrs) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#error-output: group-reloc-ldrs-encoding-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l new file mode 100644 index 00000000..2621002d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l @@ -0,0 +1,121 @@ +[^:]*: Assembler messages: +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) +[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s new file mode 100644 index 00000000..ac7a90f0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s @@ -0,0 +1,54 @@ +@ Tests that are meant to fail during encoding of LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) fail. + + ldrtest ldrd strd f "+ 256" + ldrtest ldrh strh f "+ 256" + ldrtest2 ldrsh f "+ 256" + ldrtest2 ldrsb f "+ 256" + + ldrtest ldrd strd f "- 256" + ldrtest ldrh strh f "- 256" + ldrtest2 ldrsh f "- 256" + ldrtest2 ldrsb f "- 256" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 256" + ldrtest ldrh strh localsym "+ 256" + ldrtest2 ldrsh localsym "+ 256" + ldrtest2 ldrsb localsym "+ 256" + + ldrtest ldrd strd localsym "- 256" + ldrtest ldrh strh localsym "- 256" + ldrtest2 ldrsh localsym "- 256" + ldrtest2 ldrsb localsym "- 256" + +localsym: + mov r0, #0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d new file mode 100644 index 00000000..cb46d846 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d @@ -0,0 +1,3 @@ +#name: Group relocation tests, parsing failures (ldrs) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: group-reloc-ldrs-parsing-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l new file mode 100644 index 00000000..b3d60351 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l @@ -0,0 +1,31 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:12: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:13: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:14: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:15: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:29: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:30: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:32: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g0_nc:\(f\)\]' +[^:]*:33: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g1_nc:\(f\)\]' +[^:]*:34: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g0_nc:\(f\)\]' +[^:]*:35: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g1_nc:\(f\)\]' +[^:]*:38: Error: unknown group relocation -- `ldrd r0,\[r0,#:foo:\(f\)\]' +[^:]*:39: Error: unknown group relocation -- `strd r0,\[r0,#:foo:\(f\)\]' +[^:]*:40: Error: unknown group relocation -- `ldrh r0,\[r0,#:foo:\(f\)\]' +[^:]*:41: Error: unknown group relocation -- `strh r0,\[r0,#:foo:\(f\)\]' +[^:]*:42: Error: unknown group relocation -- `ldrsh r0,\[r0,#:foo:\(f\)\]' +[^:]*:43: Error: unknown group relocation -- `ldrsb r0,\[r0,#:foo:\(f\)\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s new file mode 100644 index 00000000..16c1bea5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s @@ -0,0 +1,44 @@ +@ Tests that are supposed to fail during parsing of LDRS group relocations. + + .text + +@ No NC variants exist for the LDRS relocations. + + ldrd r0, [r0, #:pc_g0_nc:(f)] + ldrd r0, [r0, #:pc_g1_nc:(f)] + ldrd r0, [r0, #:sb_g0_nc:(f)] + ldrd r0, [r0, #:sb_g1_nc:(f)] + + strd r0, [r0, #:pc_g0_nc:(f)] + strd r0, [r0, #:pc_g1_nc:(f)] + strd r0, [r0, #:sb_g0_nc:(f)] + strd r0, [r0, #:sb_g1_nc:(f)] + + ldrh r0, [r0, #:pc_g0_nc:(f)] + ldrh r0, [r0, #:pc_g1_nc:(f)] + ldrh r0, [r0, #:sb_g0_nc:(f)] + ldrh r0, [r0, #:sb_g1_nc:(f)] + + strh r0, [r0, #:pc_g0_nc:(f)] + strh r0, [r0, #:pc_g1_nc:(f)] + strh r0, [r0, #:sb_g0_nc:(f)] + strh r0, [r0, #:sb_g1_nc:(f)] + + ldrsh r0, [r0, #:pc_g0_nc:(f)] + ldrsh r0, [r0, #:pc_g1_nc:(f)] + ldrsh r0, [r0, #:sb_g0_nc:(f)] + ldrsh r0, [r0, #:sb_g1_nc:(f)] + + ldrsb r0, [r0, #:pc_g0_nc:(f)] + ldrsb r0, [r0, #:pc_g1_nc:(f)] + ldrsb r0, [r0, #:sb_g0_nc:(f)] + ldrsb r0, [r0, #:sb_g1_nc:(f)] + +@ Instructions with a gibberish relocation code. + ldrd r0, [r0, #:foo:(f)] + strd r0, [r0, #:foo:(f)] + ldrh r0, [r0, #:foo:(f)] + strh r0, [r0, #:foo:(f)] + ldrsh r0, [r0, #:foo:(f)] + ldrsb r0, [r0, #:foo:(f)] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs.d b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs.d new file mode 100644 index 00000000..49b8f092 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs.d @@ -0,0 +1,248 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#name: Group relocation tests (ldrs) + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + 0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + 4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + 8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + 10: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 14: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 18: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 1c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 20: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 24: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 28: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 2c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 30: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 34: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 38: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 3c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 40: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 44: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 48: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 4c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 50: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 54: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 58: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 5c: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 60: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 64: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 68: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 6c: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 70: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 74: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 78: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 7c: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 80: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 84: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 88: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 8c: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 90: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 94: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 98: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 9c: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + a0: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + a4: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + a8: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + ac: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + b0: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + b4: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + b8: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + bc: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + c0: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + c4: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + c8: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + cc: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + d0: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + d4: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + d8: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + dc: R_ARM_LDRS_PC_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + e0: R_ARM_LDRS_PC_G2 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + e4: R_ARM_LDRS_SB_G0 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + e8: R_ARM_LDRS_SB_G1 f +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + ec: R_ARM_LDRS_SB_G2 f +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + f0: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + f4: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + f8: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + fc: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\] ; 0xff + 100: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 104: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 108: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 10c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 110: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\] ; 0xff + 114: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 118: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 11c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 120: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 124: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\] ; 0xff + 128: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 12c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 130: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 134: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 138: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\] ; 0xff + 13c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 140: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 144: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 148: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 14c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\] ; 0xff + 150: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 154: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 158: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 15c: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 160: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\] ; 0xff + 164: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 168: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 16c: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 170: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 174: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\] ; 0xffffff01 + 178: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 17c: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 180: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 184: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 188: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\] ; 0xffffff01 + 18c: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + 190: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + 194: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + 198: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + 19c: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\] ; 0xffffff01 + 1a0: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + 1a4: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + 1a8: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + 1ac: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + 1b0: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\] ; 0xffffff01 + 1b4: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + 1b8: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + 1bc: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + 1c0: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + 1c4: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\] ; 0xffffff01 + 1c8: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + 1cc: R_ARM_LDRS_PC_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + 1d0: R_ARM_LDRS_PC_G2 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + 1d4: R_ARM_LDRS_SB_G0 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + 1d8: R_ARM_LDRS_SB_G1 localsym +0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\] ; 0xffffff01 + 1dc: R_ARM_LDRS_SB_G2 localsym +0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs.s b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs.s new file mode 100644 index 00000000..fa74e7ea --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/group-reloc-ldrs.s @@ -0,0 +1,54 @@ +@ Tests for LDRS group relocations. + + .text + + .macro ldrtest2 load sym offset + + \load r0, [r0, #:pc_g1:(\sym \offset)] + \load r0, [r0, #:pc_g2:(\sym \offset)] + \load r0, [r0, #:sb_g0:(\sym \offset)] + \load r0, [r0, #:sb_g1:(\sym \offset)] + \load r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + + .macro ldrtest load store sym offset + + ldrtest2 \load \sym \offset + + \store r0, [r0, #:pc_g1:(\sym \offset)] + \store r0, [r0, #:pc_g2:(\sym \offset)] + \store r0, [r0, #:sb_g0:(\sym \offset)] + \store r0, [r0, #:sb_g1:(\sym \offset)] + \store r0, [r0, #:sb_g2:(\sym \offset)] + + .endm + +@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the +@ magnitude of the addend. So these should all (just) work. + + ldrtest ldrd strd f "+ 255" + ldrtest ldrh strh f "+ 255" + ldrtest2 ldrsh f "+ 255" + ldrtest2 ldrsb f "+ 255" + + ldrtest ldrd strd f "- 255" + ldrtest ldrh strh f "- 255" + ldrtest2 ldrsh f "- 255" + ldrtest2 ldrsb f "- 255" + +@ The same as the above, but for a local symbol. + + ldrtest ldrd strd localsym "+ 255" + ldrtest ldrh strh localsym "+ 255" + ldrtest2 ldrsh localsym "+ 255" + ldrtest2 ldrsb localsym "+ 255" + + ldrtest ldrd strd localsym "- 255" + ldrtest ldrh strh localsym "- 255" + ldrtest2 ldrsh localsym "- 255" + ldrtest2 ldrsb localsym "- 255" + +localsym: + mov r0, #0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/half-prec-neon.d b/binutils-2.25/gas/testsuite/gas/arm/half-prec-neon.d new file mode 100644 index 00000000..11b119e1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/half-prec-neon.d @@ -0,0 +1,9 @@ +# objdump: -dr --prefix-addresses --show-raw-insn +#name: Half-precision neon instructions +#as: -mfpu=neon-fp16 + +.*: +file format .*arm.* + +.* +0+0 <[^>]*> f3b60602 vcvt\.f16\.f32 d0, q1 +0+4 <[^>]*> f3b6a706 vcvt\.f32\.f16 q5, d6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/half-prec-neon.s b/binutils-2.25/gas/testsuite/gas/arm/half-prec-neon.s new file mode 100644 index 00000000..30cdb07b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/half-prec-neon.s @@ -0,0 +1,4 @@ + .text + + vcvt.f16.f32 d0, q1 + vcvt.f32.f16 q5, d6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/half-prec-psyntax.d b/binutils-2.25/gas/testsuite/gas/arm/half-prec-psyntax.d new file mode 100644 index 00000000..71e41747 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/half-prec-psyntax.d @@ -0,0 +1,13 @@ +# objdump: -dr --prefix-addresses --show-raw-insn +#name: Half-precision instructions (programmer's syntax) +#as: -mfpu=neon-fp16 + +.*: +file format .*arm.* + +.* +0+00 <[^>]*> f3b60602 vcvt\.f16\.f32 d0, q1 +0+04 <[^>]*> f3b6a706 vcvt\.f32\.f16 q5, d6 +0+08 <[^>]*> eeb21ae2 vcvtt\.f32\.f16 s2, s5 +0+0c <[^>]*> eeb21a62 vcvtb\.f32\.f16 s2, s5 +0+10 <[^>]*> eeb31ae2 vcvtt\.f16\.f32 s2, s5 +0+14 <[^>]*> eeb31a62 vcvtb\.f16\.f32 s2, s5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/half-prec-psyntax.s b/binutils-2.25/gas/testsuite/gas/arm/half-prec-psyntax.s new file mode 100644 index 00000000..85e52248 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/half-prec-psyntax.s @@ -0,0 +1,7 @@ + .text + vcvt d0.f16, q1.f32 + vcvt q5.f32, d6.f16 + vcvtt s2.f32, s5.f16 + vcvtb s2.f32, s5.f16 + vcvtt s2.f16, s5.f32 + vcvtb s2.f16, s5.f32 diff --git a/binutils-2.25/gas/testsuite/gas/arm/half-prec-vfpv3.d b/binutils-2.25/gas/testsuite/gas/arm/half-prec-vfpv3.d new file mode 100644 index 00000000..5bd9f306 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/half-prec-vfpv3.d @@ -0,0 +1,71 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: Half-precision vfpv3 instructions +#as: -mfpu=neon-fp16 + +.*: +file format .*arm.* + +.* +0+000 <[^>]*> eeb20ae0 vcvtt.f32.f16 s0, s1 +0+004 <[^>]*> 0eb21ae1 vcvtteq.f32.f16 s2, s3 +0+008 <[^>]*> 1eb21ae1 vcvttne.f32.f16 s2, s3 +0+00c <[^>]*> 2eb21ae1 vcvttcs.f32.f16 s2, s3 +0+010 <[^>]*> 3eb21ae1 vcvttcc.f32.f16 s2, s3 +0+014 <[^>]*> 4eb21ae1 vcvttmi.f32.f16 s2, s3 +0+018 <[^>]*> 5eb21ae1 vcvttpl.f32.f16 s2, s3 +0+01c <[^>]*> 6eb21ae1 vcvttvs.f32.f16 s2, s3 +0+020 <[^>]*> 7eb21ae1 vcvttvc.f32.f16 s2, s3 +0+024 <[^>]*> 8eb21ae1 vcvtthi.f32.f16 s2, s3 +0+028 <[^>]*> 9eb21ae1 vcvttls.f32.f16 s2, s3 +0+02c <[^>]*> aeb21ae1 vcvttge.f32.f16 s2, s3 +0+030 <[^>]*> beb21ae1 vcvttlt.f32.f16 s2, s3 +0+034 <[^>]*> ceb21ae1 vcvttgt.f32.f16 s2, s3 +0+038 <[^>]*> deb21ae1 vcvttle.f32.f16 s2, s3 +0+03c <[^>]*> eeb21ae1 vcvtt.f32.f16 s2, s3 +0+040 <[^>]*> eeb30ae0 vcvtt.f16.f32 s0, s1 +0+044 <[^>]*> 0eb31ae1 vcvtteq.f16.f32 s2, s3 +0+048 <[^>]*> 1eb31ae1 vcvttne.f16.f32 s2, s3 +0+04c <[^>]*> 2eb31ae1 vcvttcs.f16.f32 s2, s3 +0+050 <[^>]*> 3eb31ae1 vcvttcc.f16.f32 s2, s3 +0+054 <[^>]*> 4eb31ae1 vcvttmi.f16.f32 s2, s3 +0+058 <[^>]*> 5eb31ae1 vcvttpl.f16.f32 s2, s3 +0+05c <[^>]*> 6eb31ae1 vcvttvs.f16.f32 s2, s3 +0+060 <[^>]*> 7eb31ae1 vcvttvc.f16.f32 s2, s3 +0+064 <[^>]*> 8eb31ae1 vcvtthi.f16.f32 s2, s3 +0+068 <[^>]*> 9eb31ae1 vcvttls.f16.f32 s2, s3 +0+06c <[^>]*> aeb31ae1 vcvttge.f16.f32 s2, s3 +0+070 <[^>]*> beb31ae1 vcvttlt.f16.f32 s2, s3 +0+074 <[^>]*> ceb31ae1 vcvttgt.f16.f32 s2, s3 +0+078 <[^>]*> deb31ae1 vcvttle.f16.f32 s2, s3 +0+07c <[^>]*> eeb31ae1 vcvtt.f16.f32 s2, s3 +0+080 <[^>]*> eeb20a60 vcvtb.f32.f16 s0, s1 +0+084 <[^>]*> 0eb21a61 vcvtbeq.f32.f16 s2, s3 +0+088 <[^>]*> 1eb21a61 vcvtbne.f32.f16 s2, s3 +0+08c <[^>]*> 2eb21a61 vcvtbcs.f32.f16 s2, s3 +0+090 <[^>]*> 3eb21a61 vcvtbcc.f32.f16 s2, s3 +0+094 <[^>]*> 4eb21a61 vcvtbmi.f32.f16 s2, s3 +0+098 <[^>]*> 5eb21a61 vcvtbpl.f32.f16 s2, s3 +0+09c <[^>]*> 6eb21a61 vcvtbvs.f32.f16 s2, s3 +0+0a0 <[^>]*> 7eb21a61 vcvtbvc.f32.f16 s2, s3 +0+0a4 <[^>]*> 8eb21a61 vcvtbhi.f32.f16 s2, s3 +0+0a8 <[^>]*> 9eb21a61 vcvtbls.f32.f16 s2, s3 +0+0ac <[^>]*> aeb21a61 vcvtbge.f32.f16 s2, s3 +0+0b0 <[^>]*> beb21a61 vcvtblt.f32.f16 s2, s3 +0+0b4 <[^>]*> ceb21a61 vcvtbgt.f32.f16 s2, s3 +0+0b8 <[^>]*> deb21a61 vcvtble.f32.f16 s2, s3 +0+0bc <[^>]*> eeb21a61 vcvtb.f32.f16 s2, s3 +0+0c0 <[^>]*> eeb30a60 vcvtb.f16.f32 s0, s1 +0+0c4 <[^>]*> 0eb31a61 vcvtbeq.f16.f32 s2, s3 +0+0c8 <[^>]*> 1eb31a61 vcvtbne.f16.f32 s2, s3 +0+0cc <[^>]*> 2eb31a61 vcvtbcs.f16.f32 s2, s3 +0+0d0 <[^>]*> 3eb31a61 vcvtbcc.f16.f32 s2, s3 +0+0d4 <[^>]*> 4eb31a61 vcvtbmi.f16.f32 s2, s3 +0+0d8 <[^>]*> 5eb31a61 vcvtbpl.f16.f32 s2, s3 +0+0dc <[^>]*> 6eb31a61 vcvtbvs.f16.f32 s2, s3 +0+0e0 <[^>]*> 7eb31a61 vcvtbvc.f16.f32 s2, s3 +0+0e4 <[^>]*> 8eb31a61 vcvtbhi.f16.f32 s2, s3 +0+0e8 <[^>]*> 9eb31a61 vcvtbls.f16.f32 s2, s3 +0+0ec <[^>]*> aeb31a61 vcvtbge.f16.f32 s2, s3 +0+0f0 <[^>]*> beb31a61 vcvtblt.f16.f32 s2, s3 +0+0f4 <[^>]*> ceb31a61 vcvtbgt.f16.f32 s2, s3 +0+0f8 <[^>]*> deb31a61 vcvtble.f16.f32 s2, s3 +0+0fc <[^>]*> eeb31a61 vcvtb.f16.f32 s2, s3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/half-prec-vfpv3.s b/binutils-2.25/gas/testsuite/gas/arm/half-prec-vfpv3.s new file mode 100644 index 00000000..d658807c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/half-prec-vfpv3.s @@ -0,0 +1,68 @@ + .text + vcvtt.f32.f16 s0, s1 + vcvtteq.f32.f16 s2, s3 + vcvttne.f32.f16 s2, s3 + vcvttcs.f32.f16 s2, s3 + vcvttcc.f32.f16 s2, s3 + vcvttmi.f32.f16 s2, s3 + vcvttpl.f32.f16 s2, s3 + vcvttvs.f32.f16 s2, s3 + vcvttvc.f32.f16 s2, s3 + vcvtthi.f32.f16 s2, s3 + vcvttls.f32.f16 s2, s3 + vcvttge.f32.f16 s2, s3 + vcvttlt.f32.f16 s2, s3 + vcvttgt.f32.f16 s2, s3 + vcvttle.f32.f16 s2, s3 + vcvttal.f32.f16 s2, s3 + + vcvtt.f16.f32 s0, s1 + vcvtteq.f16.f32 s2, s3 + vcvttne.f16.f32 s2, s3 + vcvttcs.f16.f32 s2, s3 + vcvttcc.f16.f32 s2, s3 + vcvttmi.f16.f32 s2, s3 + vcvttpl.f16.f32 s2, s3 + vcvttvs.f16.f32 s2, s3 + vcvttvc.f16.f32 s2, s3 + vcvtthi.f16.f32 s2, s3 + vcvttls.f16.f32 s2, s3 + vcvttge.f16.f32 s2, s3 + vcvttlt.f16.f32 s2, s3 + vcvttgt.f16.f32 s2, s3 + vcvttle.f16.f32 s2, s3 + vcvttal.f16.f32 s2, s3 + + vcvtb.f32.f16 s0, s1 + vcvtbeq.f32.f16 s2, s3 + vcvtbne.f32.f16 s2, s3 + vcvtbcs.f32.f16 s2, s3 + vcvtbcc.f32.f16 s2, s3 + vcvtbmi.f32.f16 s2, s3 + vcvtbpl.f32.f16 s2, s3 + vcvtbvs.f32.f16 s2, s3 + vcvtbvc.f32.f16 s2, s3 + vcvtbhi.f32.f16 s2, s3 + vcvtbls.f32.f16 s2, s3 + vcvtbge.f32.f16 s2, s3 + vcvtblt.f32.f16 s2, s3 + vcvtbgt.f32.f16 s2, s3 + vcvtble.f32.f16 s2, s3 + vcvtbal.f32.f16 s2, s3 + + vcvtb.f16.f32 s0, s1 + vcvtbeq.f16.f32 s2, s3 + vcvtbne.f16.f32 s2, s3 + vcvtbcs.f16.f32 s2, s3 + vcvtbcc.f16.f32 s2, s3 + vcvtbmi.f16.f32 s2, s3 + vcvtbpl.f16.f32 s2, s3 + vcvtbvs.f16.f32 s2, s3 + vcvtbvc.f16.f32 s2, s3 + vcvtbhi.f16.f32 s2, s3 + vcvtbls.f16.f32 s2, s3 + vcvtbge.f16.f32 s2, s3 + vcvtblt.f16.f32 s2, s3 + vcvtbgt.f16.f32 s2, s3 + vcvtble.f16.f32 s2, s3 + vcvtbal.f16.f32 s2, s3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/immed.d b/binutils-2.25/gas/testsuite/gas/arm/immed.d new file mode 100644 index 00000000..42ca13bc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/immed.d @@ -0,0 +1,16 @@ +# name: immediate expressions +# as: +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+0000 <[^>]+> e3a00000 ? mov r0, #0 +0+0004 <[^>]+> e3e00003 ? mvn r0, #3 +0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+> +0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+> + \.\.\. +0+1010 <[^>]+> e3a00008 ? mov r0, #8 +0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+> +0+1018 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+101c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/immed.s b/binutils-2.25/gas/testsuite/gas/arm/immed.s new file mode 100644 index 00000000..400f628f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/immed.s @@ -0,0 +1,15 @@ +@ Tests for complex immediate expressions - none of these need +@ relocations + .text +bar: + mov r0, #0 + mov r0, #(. - bar - 8) + ldr r0, bar + ldr r0, [pc, # (bar - . -8)] + .space 4096 + mov r0, #(. - bar - 8) & 0xff + ldr r0, [pc, # (bar - . -8) & 0xff] + + @ section padding for a.out's benefit + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/immed2.d b/binutils-2.25/gas/testsuite/gas/arm/immed2.d new file mode 100644 index 00000000..49fa895b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/immed2.d @@ -0,0 +1,8 @@ +# name: modified immediate constants +# as: +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+0000 <[^>]+> b351029c ? cmplt r1, #156, 4 ; 0xc0000009 diff --git a/binutils-2.25/gas/testsuite/gas/arm/immed2.s b/binutils-2.25/gas/testsuite/gas/arm/immed2.s new file mode 100644 index 00000000..0365236c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/immed2.s @@ -0,0 +1,4 @@ +@ Tests for modified immediate constants with specified rotate + .text +bar: + cmplt r1, #0x9c, 4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.d b/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.d new file mode 100644 index 00000000..d3b492a1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.d @@ -0,0 +1,6 @@ +# Check that changing arm -> thumb state immediately +# after an invalid instruction does not cause an internal error. +#name: invalid instruction recovery test - ARM version +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: insn-error-a.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.l b/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.l new file mode 100644 index 00000000..ce9ca192 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: ARM register expected -- `movne r33,r9' diff --git a/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.s b/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.s new file mode 100644 index 00000000..9a8359d8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/insn-error-a.s @@ -0,0 +1,6 @@ +.syntax unified +.arch armv7a +.arm +movne r33,r9 +.thumb + diff --git a/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.d b/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.d new file mode 100644 index 00000000..01b3ad01 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.d @@ -0,0 +1,6 @@ +# Check that changing thumb -> arm state immediately +# after an invalid instruction does not cause an internal error. +#name: invalid instruction recovery test - Thumb version +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: insn-error-t.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.l b/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.l new file mode 100644 index 00000000..b3727e04 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: thumb conditional instruction should be in IT block -- `movne r1,r9' diff --git a/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.s b/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.s new file mode 100644 index 00000000..1d011384 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/insn-error-t.s @@ -0,0 +1,6 @@ +.syntax unified +.arch armv7a +.thumb +movne r1,r9 +.arm + diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.d b/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.d new file mode 100644 index 00000000..3c3c41ff --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.d @@ -0,0 +1,4 @@ +#name: .inst pseudo-opcode validations test +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: inst-po-2.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.l b/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.l new file mode 100644 index 00000000..677d3963 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.l @@ -0,0 +1,6 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: constant expression required +[^:]*:10: Error: width suffixes are invalid in ARM mode +[^:]*:11: Error: width suffixes are invalid in ARM mode +[^:]*:14: Error: cannot determine Thumb instruction size. Use .inst.n/.inst.w instead +[^:]*:15: Error: .inst.n operand too big. Use .inst.w instead diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.s b/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.s new file mode 100644 index 00000000..b66f1606 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po-2.s @@ -0,0 +1,16 @@ +.syntax unified +.arch armv7a +.arm +.L1: + +moveq r1, r9 +.inst .L1 + +.arm +.inst.w 1 +.inst.n 1 + +.thumb +.inst 0xf000 +.inst.n 1<<31 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po-3.d b/binutils-2.25/gas/testsuite/gas/arm/inst-po-3.d new file mode 100644 index 00000000..c6b09fb7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po-3.d @@ -0,0 +1,16 @@ +#name: .inst pseudo-opcode with automatic IT blocks test +#as: -mimplicit-it=always +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <.text> bf08 it eq +00000002 <.text\+0x2> 4649 moveq r1, r9 +00000004 <.text\+0x4> 4649 mov r1, r9 +00000006 <.text\+0x6> 4649 mov r1, r9 +00000008 <.text\+0x8> 00001234 .word 0x00001234 +0000000c <.text\+0xc> bf0c ite eq +0000000e <.text\+0xe> 4649 moveq r1, r9 +00000010 <.text\+0x10> 4649 movne r1, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po-3.s b/binutils-2.25/gas/testsuite/gas/arm/inst-po-3.s new file mode 100644 index 00000000..9fcefe9d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po-3.s @@ -0,0 +1,17 @@ +.syntax unified +.arch armv7a +.thumb + +@ it eq +@ mov r1, r9 +@ mov r1, r9 +moveq r1, r9 +.inst 0x4649 +.inst 0x4649 + +.word 0x1234 + +@ ite eq +@ moveq r1, r9 +@ movne r1, r9 +.inst 0xbf0b + 1, 0x4649, 0x4649 diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po-be.d b/binutils-2.25/gas/testsuite/gas/arm/inst-po-be.d new file mode 100644 index 00000000..2a6fb400 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po-be.d @@ -0,0 +1,22 @@ +#name: .inst pseudo-opcode test 1 - big endian version +#as: -mbig-endian +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#source: inst-po.s + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <.text> 11a01009 movne r1, r9 +00000004 <.text\+0x4> bf0c ite eq +00000006 <.text\+0x6> 4649 moveq r1, r9 +00000008 <.text\+0x8> 4649 movne r1, r9 +0000000a <.text\+0xa> 0000 .short 0x0000 +0000000c <.text\+0xc> 1234 .short 0x1234 +0000000e <.text\+0xe> bf0c ite eq +00000010 <.text\+0x10> 4649 moveq r1, r9 +00000012 <.text\+0x12> 4649 movne r1, r9 +00000014 <.text\+0x14> 4649 mov r1, r9 +00000016 <.text\+0x16> ea4f 0109 mov.w r1, r9 +0000001a <.text\+0x1a> ea4f 0109 mov.w r1, r9 +0000001e <.text\+0x1e> bf00 nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po.d b/binutils-2.25/gas/testsuite/gas/arm/inst-po.d new file mode 100644 index 00000000..be912c87 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po.d @@ -0,0 +1,20 @@ +#name: .inst pseudo-opcode test 1 +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <.text> 11a01009 movne r1, r9 +00000004 <.text\+0x4> bf0c ite eq +00000006 <.text\+0x6> 4649 moveq r1, r9 +00000008 <.text\+0x8> 4649 movne r1, r9 +0000000a <.text\+0xa> 1234 .short 0x1234 +0000000c <.text\+0xc> 0000 .short 0x0000 +0000000e <.text\+0xe> bf0c ite eq +00000010 <.text\+0x10> 4649 moveq r1, r9 +00000012 <.text\+0x12> 4649 movne r1, r9 +00000014 <.text\+0x14> 4649 mov r1, r9 +00000016 <.text\+0x16> ea4f 0109 mov.w r1, r9 +0000001a <.text\+0x1a> ea4f 0109 mov.w r1, r9 +0000001e <.text\+0x1e> bf00 nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst-po.s b/binutils-2.25/gas/testsuite/gas/arm/inst-po.s new file mode 100644 index 00000000..2d6d1dde --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst-po.s @@ -0,0 +1,27 @@ +.syntax unified +.arch armv7a +.arm +@ movne r1,r9 +.inst 0x11a01009 + +.thumb + +@ ite eq +@ moveq r1, r9 +@ movne r1, r9 +.inst 0xbf0b + 1, 0x4649 +.inst 0x4649 + +.word 0x1234 + +@ ite eq +@ moveq r1, r9 +@ movne r1, r9 +.inst.n 0xbf0b + 1, 0x4649, 0x4649 + +.inst.n 0x4649 + +@ mov.w r1, r9 +@ mov.w r1, r9 +.inst 0xea4f0109 +.inst.w 0xea4f0109 diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst.d b/binutils-2.25/gas/testsuite/gas/arm/inst.d new file mode 100644 index 00000000..e298c5fe --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst.d @@ -0,0 +1,204 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM basic instructions +#as: -mcpu=arm7m -EL +# WinCE has its own version of this test. +#skip: *-wince-* + +# Test the standard ARM instructions: + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> e3a00000 ? mov r0, #0 +0+004 <[^>]*> e1a01002 ? mov r1, r2 +0+008 <[^>]*> e1a03184 ? lsl r3, r4, #3 +0+00c <[^>]*> e1a05736 ? lsr r5, r6, r7 +0+010 <[^>]*> e1a08a59 ? asr r8, r9, sl +0+014 <[^>]*> e1a0bd1c ? lsl fp, ip, sp +0+018 <[^>]*> e1a0e06f ? rrx lr, pc +0+01c <[^>]*> e1a01002 ? mov r1, r2 +0+020 <[^>]*> 01a02003 ? moveq r2, r3 +0+024 <[^>]*> 11a04005 ? movne r4, r5 +0+028 <[^>]*> b1a06007 ? movlt r6, r7 +0+02c <[^>]*> a1a08009 ? movge r8, r9 +0+030 <[^>]*> d1a0a00b ? movle sl, fp +0+034 <[^>]*> c1a0c00d ? movgt ip, sp +0+038 <[^>]*> 31a01002 ? movcc r1, r2 +0+03c <[^>]*> 21a01003 ? movcs r1, r3 +0+040 <[^>]*> 41a03006 ? movmi r3, r6 +0+044 <[^>]*> 51a07009 ? movpl r7, r9 +0+048 <[^>]*> 61a01008 ? movvs r1, r8 +0+04c <[^>]*> 71a09fa1 ? lsrvc r9, r1, #31 +0+050 <[^>]*> 81a0800f ? movhi r8, pc +0+054 <[^>]*> 91a0f00e ? movls pc, lr +0+058 <[^>]*> 21a09008 ? movcs r9, r8 +0+05c <[^>]*> 31a01003 ? movcc r1, r3 +0+060 <[^>]*> e1b00008 ? movs r0, r8 +0+064 <[^>]*> 31b00007 ? movscc r0, r7 +0+068 <[^>]*> e281000a ? add r0, r1, #10 +0+06c <[^>]*> e0832004 ? add r2, r3, r4 +0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 +0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1 +0+078 <[^>]*> e201000a ? and r0, r1, #10 +0+07c <[^>]*> e0032004 ? and r2, r3, r4 +0+080 <[^>]*> e0065287 ? and r5, r6, r7, lsl #5 +0+084 <[^>]*> e0021113 ? and r1, r2, r3, lsl r1 +0+088 <[^>]*> e221000a ? eor r0, r1, #10 +0+08c <[^>]*> e0232004 ? eor r2, r3, r4 +0+090 <[^>]*> e0265287 ? eor r5, r6, r7, lsl #5 +0+094 <[^>]*> e0221113 ? eor r1, r2, r3, lsl r1 +0+098 <[^>]*> e241000a ? sub r0, r1, #10 +0+09c <[^>]*> e0432004 ? sub r2, r3, r4 +0+0a0 <[^>]*> e0465287 ? sub r5, r6, r7, lsl #5 +0+0a4 <[^>]*> e0421113 ? sub r1, r2, r3, lsl r1 +0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 +0+0ac <[^>]*> e0a32004 ? adc r2, r3, r4 +0+0b0 <[^>]*> e0a65287 ? adc r5, r6, r7, lsl #5 +0+0b4 <[^>]*> e0a21113 ? adc r1, r2, r3, lsl r1 +0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 +0+0bc <[^>]*> e0c32004 ? sbc r2, r3, r4 +0+0c0 <[^>]*> e0c65287 ? sbc r5, r6, r7, lsl #5 +0+0c4 <[^>]*> e0c21113 ? sbc r1, r2, r3, lsl r1 +0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 +0+0cc <[^>]*> e0632004 ? rsb r2, r3, r4 +0+0d0 <[^>]*> e0665287 ? rsb r5, r6, r7, lsl #5 +0+0d4 <[^>]*> e0621113 ? rsb r1, r2, r3, lsl r1 +0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 +0+0dc <[^>]*> e0e32004 ? rsc r2, r3, r4 +0+0e0 <[^>]*> e0e65287 ? rsc r5, r6, r7, lsl #5 +0+0e4 <[^>]*> e0e21113 ? rsc r1, r2, r3, lsl r1 +0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 +0+0ec <[^>]*> e1832004 ? orr r2, r3, r4 +0+0f0 <[^>]*> e1865287 ? orr r5, r6, r7, lsl #5 +0+0f4 <[^>]*> e1821113 ? orr r1, r2, r3, lsl r1 +0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 +0+0fc <[^>]*> e1c32004 ? bic r2, r3, r4 +0+100 <[^>]*> e1c65287 ? bic r5, r6, r7, lsl #5 +0+104 <[^>]*> e1c21113 ? bic r1, r2, r3, lsl r1 +0+108 <[^>]*> e3e0000a ? mvn r0, #10 +0+10c <[^>]*> e1e02004 ? mvn r2, r4 +0+110 <[^>]*> e1e05287 ? mvn r5, r7, lsl #5 +0+114 <[^>]*> e1e01113 ? mvn r1, r3, lsl r1 +0+118 <[^>]*> e310000a ? tst r0, #10 +0+11c <[^>]*> e1120004 ? tst r2, r4 +0+120 <[^>]*> e1150287 ? tst r5, r7, lsl #5 +0+124 <[^>]*> e1110113 ? tst r1, r3, lsl r1 +0+128 <[^>]*> e330000a ? teq r0, #10 +0+12c <[^>]*> e1320004 ? teq r2, r4 +0+130 <[^>]*> e1350287 ? teq r5, r7, lsl #5 +0+134 <[^>]*> e1310113 ? teq r1, r3, lsl r1 +0+138 <[^>]*> e350000a ? cmp r0, #10 +0+13c <[^>]*> e1520004 ? cmp r2, r4 +0+140 <[^>]*> e1550287 ? cmp r5, r7, lsl #5 +0+144 <[^>]*> e1510113 ? cmp r1, r3, lsl r1 +0+148 <[^>]*> e370000a ? cmn r0, #10 +0+14c <[^>]*> e1720004 ? cmn r2, r4 +0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 +0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 +0+158 <[^>]*> e330f00a ? teq r0, #10 +0+15c <[^>]*> e132f004 ? teq r2, r4 +0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 +0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 +0+168 <[^>]*> e370f00a ? cmn r0, #10 +0+16c <[^>]*> e172f004 ? cmn r2, r4 +0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 +0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 +0+178 <[^>]*> e350f00a ? cmp r0, #10 +0+17c <[^>]*> e152f004 ? cmp r2, r4 +0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 +0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 +0+188 <[^>]*> e310f00a ? tst r0, #10 +0+18c <[^>]*> e112f004 ? tst r2, r4 +0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 +0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 +0+198 <[^>]*> e0000291 ? mul r0, r1, r2 +0+19c <[^>]*> e0110392 ? muls r1, r2, r3 +0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 +0+1a4 <[^>]*> 90190798 ? mulsls r9, r8, r7 +0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp +0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip +0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp +0+1b4 <[^>]*> a034e391 ? mlasge r4, r1, r3, lr +0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] +0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] +0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! +0+1c4 <[^>]*> e5922020 ? ldr r2, \[r2, #32\] +0+1c8 <[^>]*> e7932424 ? ldr r2, \[r3, r4, lsr #8\] +0+1cc <[^>]*> 07b54484 ? ldreq r4, \[r5, r4, lsl #9\]! +0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6 +0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3 +0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 +0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> +0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] +0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\], #0 +0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] +0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] +0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! +0+1f4 <[^>]*> e5822020 ? str r2, \[r2, #32\] +0+1f8 <[^>]*> e7832424 ? str r2, \[r3, r4, lsr #8\] +0+1fc <[^>]*> 07a54484 ? streq r4, \[r5, r4, lsl #9\]! +0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6 +0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3 +0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8 +0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> +0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] +0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\], #0 +0+218 <[^>]*> e8900002 ? ldm r0, {r1} +0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5} +0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ +0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} +0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} +0+22c <[^>]*> e89201f8 ? ldm r2, {r3, r4, r5, r6, r7, r8} +0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} +0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ +0+238 <[^>]*> e8800002 ? stm r0, {r1} +0+23c <[^>]*> 09820038 ? stmibeq r2, {r3, r4, r5} +0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ +0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} +0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} +0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} +0+250 <[^>]*> e8830003 ? stm r3, {r0, r1} +0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ +0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 +0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 +0+260 <[^>]*> eb...... ? bl 0[0123456789abcdef]+ <[^>]*> +[ ]*260:.*_wombat.* +0+264 <[^>]*> 5b...... ? blpl 0[0123456789abcdef]+ <[^>]*> +[ ]*264:.*ARM.*hohum.* +0+268 <[^>]*> ea...... ? b 0[0123456789abcdef]+ <[^>]*> +[ ]*268:.*_wibble.* +0+26c <[^>]*> da...... ? ble 0[0123456789abcdef]+ <[^>]*> +[ ]*26c:.*testerfunc.* +0+270 <[^>]*> e1a01102 ? lsl r1, r2, #2 +0+274 <[^>]*> e1a01002 ? mov r1, r2 +0+278 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+27c <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+280 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+284 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+288 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+28c <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+290 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+294 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+298 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+29c <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2a0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2a4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2a8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ac <[^>]*> e1a01062 ? rrx r1, r2 +0+2b0 <[^>]*> e1a01102 ? lsl r1, r2, #2 +0+2b4 <[^>]*> e1a01002 ? mov r1, r2 +0+2b8 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+2bc <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+2c0 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+2c4 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+2c8 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+2cc <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+2d0 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+2d4 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+2d8 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+2dc <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2e0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2e4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2e8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ec <[^>]*> e1a01062 ? rrx r1, r2 +0+2f0 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/inst.s b/binutils-2.25/gas/testsuite/gas/arm/inst.s new file mode 100644 index 00000000..432f19a4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/inst.s @@ -0,0 +1,223 @@ +@ Test file for ARM/GAS -- basic instructions + +.text +.align + mov r0, #0 + mov r1, r2 + mov r3, r4, lsl #3 + mov r5, r6, lsr r7 + mov r8, r9, asr r10 + mov r11, r12, asl r13 + mov r14, r15, rrx + moval a2, a3 + moveq a3, a4 + movne v1, v2 + movlt v3, v4 + movge v5, v6 + movle v7, v8 + movgt ip, sp + movcc r1, r2 + movcs r1, r3 + movmi r3, r6 + movpl wr, sb + movvs r1, r8 + movvc SB, r1, lsr #31 + movhi r8, pc + movls PC, lr + movhs r9, r8 + movul r1, r3 + movs r0, r8 + movuls r0, WR + + add r0, r1, #10 + add r2, r3, r4 + add r5, r6, r7, asl #5 + add r1, r2, r3, lsl r1 + + and r0, r1, #10 + and r2, r3, r4 + and r5, r6, r7, asl #5 + and r1, r2, r3, lsl r1 + + eor r0, r1, #10 + eor r2, r3, r4 + eor r5, r6, r7, asl #5 + eor r1, r2, r3, lsl r1 + + sub r0, r1, #10 + sub r2, r3, r4 + sub r5, r6, r7, asl #5 + sub r1, r2, r3, lsl r1 + + adc r0, r1, #10 + adc r2, r3, r4 + adc r5, r6, r7, asl #5 + adc r1, r2, r3, lsl r1 + + sbc r0, r1, #10 + sbc r2, r3, r4 + sbc r5, r6, r7, asl #5 + sbc r1, r2, r3, lsl r1 + + rsb r0, r1, #10 + rsb r2, r3, r4 + rsb r5, r6, r7, asl #5 + rsb r1, r2, r3, lsl r1 + + rsc r0, r1, #10 + rsc r2, r3, r4 + rsc r5, r6, r7, asl #5 + rsc r1, r2, r3, lsl r1 + + orr r0, r1, #10 + orr r2, r3, r4 + orr r5, r6, r7, asl #5 + orr r1, r2, r3, lsl r1 + + bic r0, r1, #10 + bic r2, r3, r4 + bic r5, r6, r7, asl #5 + bic r1, r2, r3, lsl r1 + + mvn r0, #10 + mvn r2, r4 + mvn r5, r7, asl #5 + mvn r1, r3, lsl r1 + + tst r0, #10 + tst r2, r4 + tst r5, r7, asl #5 + tst r1, r3, lsl r1 + + teq r0, #10 + teq r2, r4 + teq r5, r7, asl #5 + teq r1, r3, lsl r1 + + cmp r0, #10 + cmp r2, r4 + cmp r5, r7, asl #5 + cmp r1, r3, lsl r1 + + cmn r0, #10 + cmn r2, r4 + cmn r5, r7, asl #5 + cmn r1, r3, lsl r1 + + teqp r0, #10 + teqp r2, r4 + teqp r5, r7, asl #5 + teqp r1, r3, lsl r1 + + cmnp r0, #10 + cmnp r2, r4 + cmnp r5, r7, asl #5 + cmnp r1, r3, lsl r1 + + cmpp r0, #10 + cmpp r2, r4 + cmpp r5, r7, asl #5 + cmpp r1, r3, lsl r1 + + tstp r0, #10 + tstp r2, r4 + tstp r5, r7, asl #5 + tstp r1, r3, lsl r1 + + mul r0, r1, r2 + muls r1, r2, r3 + mulne r0, r1, r0 + mullss r9, r8, r7 + + mla r1, r9, sl, fp + mlas r3, r4, r9, IP + mlalt r9, r8, r7, SP + mlages r4, r1, r3, LR + + ldr r0, [r1] + ldr r1, [r1, r2] + ldr r2, [r3, r4]! + ldr r2, [r2, #32] + ldr r2, [r3, r4, lsr #8] + ldreq r4, [r5, r4, asl #9]! + ldrne r4, [r5], #6 + ldrt r1, [r2], r3 + ldr r2, [r4], r5, lsr #8 +foo: + ldr r0, foo + ldrb r3, [r4] + ldrnebt r5, [r8] + + str r0, [r1] + str r1, [r1, r2] + str r3, [r4, r3]! + str r2, [r2, #32] + str r2, [r3, r4, lsr #8] + streq r4, [r5, r4, asl #9]! + strne r4, [r5], #6 + str r1, [r2], r3 + strt r2, [r4], r5, lsr #8 + str r1, bar +bar: + stralb r1, [r7] + strbt r2, [r0] + + ldmia r0, {r1} + ldmeqib r2, {r3, r4, r5} + ldmalda r3, {r0-r15}^ + ldmdb FP!, {r0-r8, SL} + ldmed r1, {r0, r1, r2}|0xf0 + ldmfd r2, {r3, r4}+{r5, r6, r7, r8} + ldmea r3, 3 + ldmfa r4, {r8, r9}^ + + stmia r0, {r1} + stmeqib r2, {r3, r4, r5} + stmalda r3, {r0-r15}^ + stmdb r11!, {r0-r8, r10} + stmed r1, {r0, r1, r2} + stmfd r2, {r3, r4} + stmea r3, 3 + stmfa r4, {r8, r9}^ + + swi 0x123456 + swihs 0x33 + + bl _wombat + blpl hohum + b _wibble + ble testerfunc + + mov r1, r2, lsl #2 + mov r1, r2, lsl #0 + mov r1, r2, lsl #31 + mov r1, r2, lsl r3 + mov r1, r2, lsr #2 + mov r1, r2, lsr #31 + mov r1, r2, lsr #32 + mov r1, r2, lsr r3 + mov r1, r2, asr #2 + mov r1, r2, asr #31 + mov r1, r2, asr #32 + mov r1, r2, asr r3 + mov r1, r2, ror #2 + mov r1, r2, ror #31 + mov r1, r2, ror r3 + mov r1, r2, rrx + mov r1, r2, LSL #2 + mov r1, r2, LSL #0 + mov r1, r2, LSL #31 + mov r1, r2, LSL r3 + mov r1, r2, LSR #2 + mov r1, r2, LSR #31 + mov r1, r2, LSR #32 + mov r1, r2, LSR r3 + mov r1, r2, ASR #2 + mov r1, r2, ASR #31 + mov r1, r2, ASR #32 + mov r1, r2, ASR r3 + mov r1, r2, ROR #2 + mov r1, r2, ROR #31 + mov r1, r2, ROR r3 + mov r1, r2, RRX + ldralt r1, [r2], r3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/itblock.s b/binutils-2.25/gas/testsuite/gas/arm/itblock.s new file mode 100644 index 00000000..0fb3c198 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/itblock.s @@ -0,0 +1,21 @@ +# All-true IT block macro. + + .macro itblock num cond="" + .if x\cond != x + .if \num == 4 + itttt \cond + .else + .if \num == 3 + ittt \cond + .else + .if \num == 2 + itt \cond + .else + .if \num == 1 + .it \cond + .endif + .endif + .endif + .endif + .endif + .endm diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.d b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.d new file mode 100644 index 00000000..6b44634c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.d @@ -0,0 +1,3 @@ +#name: iWMMXt errors +#as: -mcpu=iwmmxt +#error-output: iwmmxt-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.l b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.l new file mode 100644 index 00000000..d030a6da --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.l @@ -0,0 +1,12 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: instruction cannot be conditional -- `wldrwgt wcgr0,\[r1\]' +[^:]*:2: Error: iWMMXt data register expected -- `wldrb wcgr0,\[r1\]' +[^:]*:3: Error: iWMMXt data register expected -- `wldrh wcgr0,\[r1\]' +[^:]*:4: Error: iWMMXt data register expected -- `wldrd wcgr0,\[r1\]' +[^:]*:5: Error: instruction cannot be conditional -- `wstrwgt wcgr0,\[r1\]' +[^:]*:6: Error: iWMMXt data register expected -- `wstrb wcgr0,\[r1\]' +[^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]' +[^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]' +[^:]*:9: Error: iWMMXt control register expected -- `tmcr wibble,r1' +[^:]*:10: Error: iWMMXt data or control register expected -- `wldrw wibble,\[r1\]' +[^:]*:11: Error: iWMMXt data or control register expected -- `wstrw wibble,\[r1\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.s b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.s new file mode 100644 index 00000000..98fc2393 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad.s @@ -0,0 +1,11 @@ + wldrwgt wcgr0,[r1] + wldrb wcgr0,[r1] + wldrh wcgr0,[r1] + wldrd wcgr0,[r1] + wstrwgt wcgr0,[r1] + wstrb wcgr0,[r1] + wstrh wcgr0,[r1] + wstrd wcgr0,[r1] + tmcr wibble,r1 + wldrw wibble,[r1] + wstrw wibble,[r1] diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.d b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.d new file mode 100644 index 00000000..c8587a4c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.d @@ -0,0 +1,3 @@ +#name: iWMMXt CoProcessor offset errors +#as: -mcpu=iwmmxt +#error-output: iwmmxt-bad2.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.l b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.l new file mode 100644 index 00000000..1a43ebcd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.l @@ -0,0 +1,7 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: co-processor offset out of range +[^:]*:2: Error: co-processor offset out of range +[^:]*:3: Error: co-processor offset out of range +[^:]*:4: Error: co-processor offset out of range +[^:]*:5: Error: co-processor offset out of range +[^:]*:6: Error: co-processor offset out of range diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.s b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.s new file mode 100644 index 00000000..dc559a89 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-bad2.s @@ -0,0 +1,6 @@ + wldrd wr1, [r0, #3] + wstrd wr1, [r0, #0x400] + wstrb wr1, [r0, #0x100] + wstrh wr1, [r0, #0x100] + wldrb wr1, [r0, #-0x100] + wldrh wr1, [r0, #-0x100] diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d new file mode 100644 index 00000000..c17a1d85 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-wldsttbh.d @@ -0,0 +1,11 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions version 1 +#as: -mcpu=xscale+iwmmxt -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <iwmmxt> ecb11000[ ]+wldrb[ ]+wr1, \[r1\] +0+004 <[^>]*> ecf11000[ ]+wldrh[ ]+wr1, \[r1\] +0+008 <[^>]*> eca11000[ ]+wstrb[ ]+wr1, \[r1\] +0+00c <[^>]*> ece11000[ ]+wstrh[ ]+wr1, \[r1\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s new file mode 100644 index 00000000..fd58c105 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt-wldsttbh.s @@ -0,0 +1,8 @@ + .text + .global iwmmxt +iwmmxt: + + wldrb wr1, [r1], #0 + wldrh wr1, [r1], #0 + wstrb wr1, [r1], #0 + wstrh wr1, [r1], #0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt.d b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt.d new file mode 100644 index 00000000..1739ebb4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt.d @@ -0,0 +1,171 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions +#as: -mcpu=xscale+iwmmxt -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <iwmmxt> ee13f130[ ]+tandcb[ ]+pc +0+04 <[^>]*> de53f130[ ]+tandchle[ ]+pc +0+08 <[^>]*> ae93f130[ ]+tandcwge[ ]+pc +0+0c <[^>]*> be401010[ ]+tbcstblt[ ]+wr0, r1 +0+10 <[^>]*> ee412050[ ]+tbcsth[ ]+wr1, r2 +0+14 <[^>]*> ce423090[ ]+tbcstwgt[ ]+wr2, r3 +0+18 <[^>]*> ee13f177[ ]+textrcb[ ]+pc, #7 +0+1c <[^>]*> 0e53f172[ ]+textrcheq[ ]+pc, #2 +0+20 <[^>]*> ee93f170[ ]+textrcw[ ]+pc, #0 +0+24 <[^>]*> ee13e076[ ]+textrmub[ ]+lr, wr3, #6 +0+28 <[^>]*> 1e14d07d[ ]+textrmsbne[ ]+sp, wr4, #5 +0+2c <[^>]*> ee55c072[ ]+textrmuh[ ]+ip, wr5, #2 +0+30 <[^>]*> ee56b078[ ]+textrmsh[ ]+fp, wr6, #0 +0+34 <[^>]*> 2e97a071[ ]+textrmuwcs[ ]+sl, wr7, #1 +0+38 <[^>]*> 2e989078[ ]+textrmswcs[ ]+r9, wr8, #0 +0+3c <[^>]*> ee698014[ ]+tinsrb[ ]+wr9, r8, #4 +0+40 <[^>]*> 3e6a7050[ ]+tinsrhcc[ ]+wr10, r7, #0 +0+44 <[^>]*> ee6b6091[ ]+tinsrw[ ]+wr11, r6, #1 +0+48 <[^>]*> 3e005110[ ]+tmcrcc[ ]+wcid, r5 +0+4c <[^>]*> ec47600c[ ]+tmcrr[ ]+wr12, r6, r7 +0+50 <[^>]*> 3e2041b5[ ]+tmiacc[ ]+wr13, r5, r4 +0+54 <[^>]*> 4e2821d3[ ]+tmiaphmi[ ]+wr14, r3, r2 +0+58 <[^>]*> ee2c11f0[ ]+tmiabb[ ]+wr15, r0, r1 +0+5c <[^>]*> 5e2d31b2[ ]+tmiabtpl[ ]+wr13, r2, r3 +0+60 <[^>]*> 6e2d5034[ ]+tmiabtvs[ ]+wr1, r4, r5 +0+64 <[^>]*> 7e2f7056[ ]+tmiattvc[ ]+wr2, r6, r7 +0+68 <[^>]*> ee138030[ ]+tmovmskb[ ]+r8, wr3 +0+6c <[^>]*> 8e549030[ ]+tmovmskhhi[ ]+r9, wr4 +0+70 <[^>]*> 9e95a030[ ]+tmovmskwls[ ]+sl, wr5 +0+74 <[^>]*> ee11b110[ ]+tmrc[ ]+fp, wcon +0+78 <[^>]*> ac5dc006[ ]+tmrrcge[ ]+ip, sp, wr6 +0+7c <[^>]*> ee13f150[ ]+torcb[ ]+pc +0+80 <[^>]*> be53f150[ ]+torchlt[ ]+pc +0+84 <[^>]*> ee93f150[ ]+torcw[ ]+pc +0+88 <[^>]*> ee0871c0[ ]+waccb[ ]+wr7, wr8 +0+8c <[^>]*> be4a91c0[ ]+wacchlt[ ]+wr9, wr10 +0+90 <[^>]*> ce8cb1c0[ ]+waccwgt[ ]+wr11, wr12 +0+94 <[^>]*> de0ed18f[ ]+waddble[ ]+wr13, wr14, wr15 +0+98 <[^>]*> ee120184[ ]+waddbus[ ]+wr0, wr2, wr4 +0+9c <[^>]*> ee38618a[ ]+waddbss[ ]+wr6, wr8, wr10 +0+a0 <[^>]*> ee4ec18f[ ]+waddh[ ]+wr12, wr14, wr15 +0+a4 <[^>]*> de5cd18b[ ]+waddhusle[ ]+wr13, wr12, wr11 +0+a8 <[^>]*> 0e79a188[ ]+waddhsseq[ ]+wr10, wr9, wr8 +0+ac <[^>]*> 1e867185[ ]+waddwne[ ]+wr7, wr6, wr5 +0+b0 <[^>]*> ee934182[ ]+waddwus[ ]+wr4, wr3, wr2 +0+b4 <[^>]*> 2eb0118f[ ]+waddwsscs[ ]+wr1, wr0, wr15 +0+b8 <[^>]*> ee553027[ ]+waligni[ ]+wr3, wr5, wr7, #5 +0+bc <[^>]*> 2e8b902d[ ]+walignr0cs[ ]+wr9, wr11, wr13 +0+c0 <[^>]*> ee967025[ ]+walignr1[ ]+wr7, wr6, wr5 +0+c4 <[^>]*> 3ea42028[ ]+walignr2cc[ ]+wr2, wr4, wr8 +0+c8 <[^>]*> 3eb95021[ ]+walignr3cc[ ]+wr5, wr9, wr1 +0+cc <[^>]*> ee283001[ ]+wand[ ]+wr3, wr8, wr1 +0+d0 <[^>]*> ee323006[ ]+wandn[ ]+wr3, wr2, wr6 +0+d4 <[^>]*> ee887009[ ]+wavg2b[ ]+wr7, wr8, wr9 +0+d8 <[^>]*> decba00c[ ]+wavg2hle[ ]+wr10, wr11, wr12 +0+dc <[^>]*> ae9ed00f[ ]+wavg2brge[ ]+wr13, wr14, wr15 +0+e0 <[^>]*> eed1000c[ ]+wavg2hr[ ]+wr0, wr1, wr12 +0+e4 <[^>]*> ee04d065[ ]+wcmpeqb[ ]+wr13, wr4, wr5 +0+e8 <[^>]*> 0e474060[ ]+wcmpeqheq[ ]+wr4, wr7, wr0 +0+ec <[^>]*> be896068[ ]+wcmpeqwlt[ ]+wr6, wr9, wr8 +0+f0 <[^>]*> 3e121063[ ]+wcmpgtubcc[ ]+wr1, wr2, wr3 +0+f4 <[^>]*> ee354066[ ]+wcmpgtsb[ ]+wr4, wr5, wr6 +0+f8 <[^>]*> 3e587069[ ]+wcmpgtuhcc[ ]+wr7, wr8, wr9 +0+fc <[^>]*> ee7ba06d[ ]+wcmpgtsh[ ]+wr10, wr11, wr13 +0+100 <[^>]*> ee942063[ ]+wcmpgtuw[ ]+wr2, wr4, wr3 +0+104 <[^>]*> 8eb65063[ ]+wcmpgtswhi[ ]+wr5, wr6, wr3 +0+108 <[^>]*> ed901024[ ]+wldrb[ ]+wr1, \[r0, #36\] +0+10c <[^>]*> 0df12018[ ]+wldrheq[ ]+wr2, \[r1, #24\]! +0+110 <[^>]*> 1cb23104[ ]+wldrwne[ ]+wr3, \[r2\], #16 +0+114 <[^>]*> 6d534153[ ]+wldrdvs[ ]+wr4, \[r3, #-332\].* +0+118 <[^>]*> fdb12105[ ]+wldrw[ ]+wcssf, \[r1, #20\]! +0+11c <[^>]*> ee474109[ ]+wmacu[ ]+wr4, wr7, wr9 +0+120 <[^>]*> 2e6a810e[ ]+wmacscs[ ]+wr8, wr10, wr14 +0+124 <[^>]*> ee5cf10b[ ]+wmacuz[ ]+wr15, wr12, wr11 +0+128 <[^>]*> ee78310a[ ]+wmacsz[ ]+wr3, wr8, wr10 +0+12c <[^>]*> ee8bc107[ ]+wmaddu[ ]+wr12, wr11, wr7 +0+130 <[^>]*> cea3510f[ ]+wmaddsgt[ ]+wr5, wr3, wr15 +0+134 <[^>]*> 2e043165[ ]+wmaxubcs[ ]+wr3, wr4, wr5 +0+138 <[^>]*> ee243165[ ]+wmaxsb[ ]+wr3, wr4, wr5 +0+13c <[^>]*> 5e443165[ ]+wmaxuhpl[ ]+wr3, wr4, wr5 +0+140 <[^>]*> 4e643165[ ]+wmaxshmi[ ]+wr3, wr4, wr5 +0+144 <[^>]*> ae843165[ ]+wmaxuwge[ ]+wr3, wr4, wr5 +0+148 <[^>]*> dea43165[ ]+wmaxswle[ ]+wr3, wr4, wr5 +0+14c <[^>]*> 3e1c416a[ ]+wminubcc[ ]+wr4, wr12, wr10 +0+150 <[^>]*> ee3c416a[ ]+wminsb[ ]+wr4, wr12, wr10 +0+154 <[^>]*> 7e5c416a[ ]+wminuhvc[ ]+wr4, wr12, wr10 +0+158 <[^>]*> ee7c416a[ ]+wminsh[ ]+wr4, wr12, wr10 +0+15c <[^>]*> ee9c416a[ ]+wminuw[ ]+wr4, wr12, wr10 +0+160 <[^>]*> 3ebc416a[ ]+wminswcc[ ]+wr4, wr12, wr10 +0+164 <[^>]*> 0e043004[ ]+woreq[ ]+wr3, wr4, wr4 +0+168 <[^>]*> ee112108[ ]+wmulum[ ]+wr2, wr1, wr8 +0+16c <[^>]*> ee312108[ ]+wmulsm[ ]+wr2, wr1, wr8 +0+170 <[^>]*> ee012108[ ]+wmulul[ ]+wr2, wr1, wr8 +0+174 <[^>]*> de212108[ ]+wmulslle[ ]+wr2, wr1, wr8 +0+178 <[^>]*> 0e08b00e[ ]+woreq[ ]+wr11, wr8, wr14 +0+17c <[^>]*> 0e510083[ ]+wpackhuseq[ ]+wr0, wr1, wr3 +0+180 <[^>]*> ee910083[ ]+wpackwus[ ]+wr0, wr1, wr3 +0+184 <[^>]*> eed10083[ ]+wpackdus[ ]+wr0, wr1, wr3 +0+188 <[^>]*> 8e710083[ ]+wpackhsshi[ ]+wr0, wr1, wr3 +0+18c <[^>]*> eeb10083[ ]+wpackwss[ ]+wr0, wr1, wr3 +0+190 <[^>]*> 0ef10083[ ]+wpackdsseq[ ]+wr0, wr1, wr3 +0+194 <[^>]*> ee754046[ ]+wrorh[ ]+wr4, wr5, wr6 +0+198 <[^>]*> 4eb54046[ ]+wrorwmi[ ]+wr4, wr5, wr6 +0+19c <[^>]*> eef54046[ ]+wrord[ ]+wr4, wr5, wr6 +0+1a0 <[^>]*> ee7a9148[ ]+wrorhg[ ]+wr9, wr10, wcgr0 +0+1a4 <[^>]*> aeba9149[ ]+wrorwgge[ ]+wr9, wr10, wcgr1 +0+1a8 <[^>]*> eefa914a[ ]+wrordg[ ]+wr9, wr10, wcgr2 +0+1ac <[^>]*> ee00212a[ ]+wsadb[ ]+wr2, wr0, wr10 +0+1b0 <[^>]*> ee40212a[ ]+wsadh[ ]+wr2, wr0, wr10 +0+1b4 <[^>]*> ee10212a[ ]+wsadbz[ ]+wr2, wr0, wr10 +0+1b8 <[^>]*> de50212a[ ]+wsadhzle[ ]+wr2, wr0, wr10 +0+1bc <[^>]*> 0ef941eb[ ]+wshufheq[ ]+wr4, wr9, #251 +0+1c0 <[^>]*> ee592044[ ]+wsllh[ ]+wr2, wr9, wr4 +0+1c4 <[^>]*> ee992044[ ]+wsllw[ ]+wr2, wr9, wr4 +0+1c8 <[^>]*> 0ed92044[ ]+wslldeq[ ]+wr2, wr9, wr4 +0+1cc <[^>]*> 0e59214b[ ]+wsllhgeq[ ]+wr2, wr9, wcgr3 +0+1d0 <[^>]*> 7e99214a[ ]+wsllwgvc[ ]+wr2, wr9, wcgr2 +0+1d4 <[^>]*> eed92149[ ]+wslldg[ ]+wr2, wr9, wcgr1 +0+1d8 <[^>]*> ee451047[ ]+wsrah[ ]+wr1, wr5, wr7 +0+1dc <[^>]*> ee851047[ ]+wsraw[ ]+wr1, wr5, wr7 +0+1e0 <[^>]*> 0ec51047[ ]+wsradeq[ ]+wr1, wr5, wr7 +0+1e4 <[^>]*> ee45114b[ ]+wsrahg[ ]+wr1, wr5, wcgr3 +0+1e8 <[^>]*> 4e851148[ ]+wsrawgmi[ ]+wr1, wr5, wcgr0 +0+1ec <[^>]*> eec51149[ ]+wsradg[ ]+wr1, wr5, wcgr1 +0+1f0 <[^>]*> ee651047[ ]+wsrlh[ ]+wr1, wr5, wr7 +0+1f4 <[^>]*> eea51047[ ]+wsrlw[ ]+wr1, wr5, wr7 +0+1f8 <[^>]*> 0ee51047[ ]+wsrldeq[ ]+wr1, wr5, wr7 +0+1fc <[^>]*> ee65114b[ ]+wsrlhg[ ]+wr1, wr5, wcgr3 +0+200 <[^>]*> 4ea51148[ ]+wsrlwgmi[ ]+wr1, wr5, wcgr0 +0+204 <[^>]*> eee51149[ ]+wsrldg[ ]+wr1, wr5, wcgr1 +0+208 <[^>]*> ed8110ff[ ]+wstrb[ ]+wr1, \[r1, #255\] +0+20c <[^>]*> ed6110ff[ ]+wstrh[ ]+wr1, \[r1, #-255\]! +0+210 <[^>]*> eca11101[ ]+wstrw[ ]+wr1, \[r1\], #4 +0+214 <[^>]*> edc111ff[ ]+wstrd[ ]+wr1, \[r1, #1020\].* +0+218 <[^>]*> fca1314b[ ]+wstrw[ ]+wcasf, \[r1\], #300.* +0+21c <[^>]*> 3e1311ae[ ]+wsubbuscc[ ]+wr1, wr3, wr14 +0+220 <[^>]*> ee5311ae[ ]+wsubhus[ ]+wr1, wr3, wr14 +0+224 <[^>]*> 3e9311ae[ ]+wsubwuscc[ ]+wr1, wr3, wr14 +0+228 <[^>]*> 3e3311ae[ ]+wsubbsscc[ ]+wr1, wr3, wr14 +0+22c <[^>]*> 3e7311ae[ ]+wsubhsscc[ ]+wr1, wr3, wr14 +0+230 <[^>]*> eeb311ae[ ]+wsubwss[ ]+wr1, wr3, wr14 +0+234 <[^>]*> ee0630c0[ ]+wunpckehub[ ]+wr3, wr6 +0+238 <[^>]*> 4e4630c0[ ]+wunpckehuhmi[ ]+wr3, wr6 +0+23c <[^>]*> ee8630c0[ ]+wunpckehuw[ ]+wr3, wr6 +0+240 <[^>]*> ee2630c0[ ]+wunpckehsb[ ]+wr3, wr6 +0+244 <[^>]*> ee6630c0[ ]+wunpckehsh[ ]+wr3, wr6 +0+248 <[^>]*> 0ea630c0[ ]+wunpckehsweq[ ]+wr3, wr6 +0+24c <[^>]*> ee1c50ca[ ]+wunpckihb[ ]+wr5, wr12, wr10 +0+250 <[^>]*> 8e5c50ca[ ]+wunpckihhhi[ ]+wr5, wr12, wr10 +0+254 <[^>]*> ee9c50ca[ ]+wunpckihw[ ]+wr5, wr12, wr10 +0+258 <[^>]*> ee0530e0[ ]+wunpckelub[ ]+wr3, wr5 +0+25c <[^>]*> 1e4530e0[ ]+wunpckeluhne[ ]+wr3, wr5 +0+260 <[^>]*> ee8530e0[ ]+wunpckeluw[ ]+wr3, wr5 +0+264 <[^>]*> ce2530e0[ ]+wunpckelsbgt[ ]+wr3, wr5 +0+268 <[^>]*> ee6530e0[ ]+wunpckelsh[ ]+wr3, wr5 +0+26c <[^>]*> eea530e0[ ]+wunpckelsw[ ]+wr3, wr5 +0+270 <[^>]*> ee1540ea[ ]+wunpckilb[ ]+wr4, wr5, wr10 +0+274 <[^>]*> ee5540ea[ ]+wunpckilh[ ]+wr4, wr5, wr10 +0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10 +0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5 +0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7 +0+284 <[^>]*> ee080110[ ]+tmcr[ ]+wcgr0, r0 +0+288 <[^>]*> ee1a1110[ ]+tmrc[ ]+r1, wcgr2 +0+28c <[^>]*> e1a00000[ ]+nop[ ]+; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt.s b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt.s new file mode 100644 index 00000000..42bbb7ab --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt.s @@ -0,0 +1,210 @@ + .text + .global iwmmxt +iwmmxt: + + tandcb r15 + TANDCHLE r15 + TANDCWge r15 + + TBCSTBlt wr0, r1 + tbcsth wr1, r2 + TBCSTWGT wr2, r3 + + textrcb r15, #7 + textrcheq r15, #2 + TEXTRCW r15, #0 + + TEXTRMUB r14, wr3, #6 + textrmsbne r13, wr4, #5 + textrmUH r12, wr5, #2 + textrmSh r11, wr6, #0 + TEXTRMUWcs r10, wr7, #1 + textrmswhs r9, wr8, #0 + + TINSRB wr9, r8, #4 + tinsrhcc wr10, r7, #0 + tinsrw wr11, r6, #1 + + tmcrul wcid, r5 + TMCRR wr12, r6, r7 + tmialo wr13, r5, r4 + tmiaphMI wr14, r3, r2 + + TMIAbb wr15, r0, r1 + TMIAbTpl wr13, r2, r3 + tmiaBtvs wr1, r4, r5 + tmiaTTvc wr2, r6, r7 + + tmovmskB r8, wr3 + TMOVMSKHhi r9, wr4 + tmovmskwls r10, wr5 + + tmrc r11, wcon + TMRRCge r12, r13, wr6 + + torcb r15 + torchlt r15 + TORCW r15 + + waccb wr7, wr8 + WACCHlt wr9, wr10 + WACCWGT wr11, wr12 + + waddble wr13, wr14, wr15 + waddBUS wr0, wr2, wr4 + waddbssal wr6, wr8, wr10 + waddH wr12, wr14, wr15 + WADDHUSLE wr13, wr12, wr11 + WADDHSSeq wr10, wr9, wr8 + WADDWne wr7, wr6, wr5 + waddwus wr4, wr3, wr2 + waddwsscs wr1, wr0, wr15 + + waligni wr3, wr5, wr7, #5 + WALIGNR0hs wr9, wr11, wr13 + walignr1 wr7, wr6, wr5 + walignr2cc wr2, wr4, wr8 + WALIGNR3ul wr5, wr9, wr1 + + wand wr3, wr8, wr1 + wandn wr3, wr2, wr6 + + wavg2b wr7, wr8, wr9 + wavg2hle wr10, wr11, wr12 + wavg2brge wr13, wr14, wr15 + wavg2hr wr0, wr1, wr12 + + wcmpeqb wr13, wr4, wr5 + wcmpeqheq wr4, wr7, wr0 + wcmpeqWlt wr6, wr9, wr8 + + wcmpgtUbul wr1, wr2, wr3 + wcmpgtsb wr4, wr5, wr6 + wcmpgtuhcc wr7, wr8, wr9 + wcmpgtsh wr10, wr11, wr13 + wcmpgtuw wr2, wr4, wr3 + wcmpgtswhi wr5, wr6, wr3 + + wldrb wr1, [r0, #36] + wldrheq wr2, [r1, #24]! + wldrwne wr3, [r2], #16 + wldrdvs wr4, [r3, #-332] + wldrw wcssf, [r1, #20]! + + wmacu wr4, wr7, wr9 + wmacscs wr8, wr10, wr14 + wmacuzal wr15, wr12, wr11 + wmacsz wr3, wr8, wr10 + + wmaddu wr12, wr11, wr7 + wmaddsgt wr5, wr3, wr15 + + wmaxubhs wr3, wr4, wr5 + wmaxsb wr3, wr4, wr5 + wmaxuhpl wr3, wr4, wr5 + wmaxshmi wr3, wr4, wr5 + wmaxuwge wr3, wr4, wr5 + wmaxswle wr3, wr4, wr5 + + wminubul wr4, wr12, wr10 + wminsb wr4, wr12, wr10 + wminuhvc wr4, wr12, wr10 + wminsh wr4, wr12, wr10 + wminuw wr4, wr12, wr10 + wminswcc wr4, wr12, wr10 + + wmoveq wr3, wr4 + + wmulum wr2, wr1, wr8 + wmulsm wr2, wr1, wr8 + wmulul wr2, wr1, wr8 + wmulslle wr2, wr1, wr8 + + woreq wr11, wr8, wr14 + + wpackhuseq wr0, wr1, wr3 + wpackwus wr0, wr1, wr3 + wpackdusal wr0, wr1, wr3 + wpackhsshi wr0, wr1, wr3 + wpackwss wr0, wr1, wr3 + wpackdsseq wr0, wr1, wr3 + + wrorh wr4, wr5, wr6 + wrorwmi wr4, wr5, wr6 + wrord wr4, wr5, wr6 + wrorhg wr9, wr10, wcgr0 + wrorwgge wr9, wr10, wcgr1 + wrordg wr9, wr10, wcgr2 + + wsadb wr2, wr0, wr10 + wsadhal wr2, wr0, wr10 + wsadbz wr2, wr0, wr10 + wsadhzle wr2, wr0, wr10 + + wshufheq wr4, wr9, #251 + + wsllh wr2, wr9, wr4 + wsllw wr2, wr9, wr4 + wslldeq wr2, wr9, wr4 + wsllhgeq wr2, wr9, wcgr3 + wsllwgvc wr2, wr9, wcgr2 + wslldg wr2, wr9, wcgr1 + + wsrah wr1, wr5, wr7 + wsraw wr1, wr5, wr7 + wsradeq wr1, wr5, wr7 + wsrahg wr1, wr5, wcgr3 + wsrawgmi wr1, wr5, wcgr0 + wsradg wr1, wr5, wcgr1 + + wsrlh wr1, wr5, wr7 + wsrlw wr1, wr5, wr7 + wsrldeq wr1, wr5, wr7 + wsrlhg wr1, wr5, wcgr3 + wsrlwgmi wr1, wr5, wcgr0 + wsrldg wr1, wr5, wcgr1 + + wstrb wr1, [r1, #0xFF] + wstrh wr1, [r1, #-0xFF]! + wstrw wr1, [r1], #4 + wstrd wr1, [r1, #0x3FC] + wstrw wcasf, [r1], #300 + + wsubbusul wr1, wr3, wr14 + wsubhus wr1, wr3, wr14 + wsubwusul wr1, wr3, wr14 + wsubbssul wr1, wr3, wr14 + wsubhssul wr1, wr3, wr14 + wsubwss wr1, wr3, wr14 + + wunpckehub wr3, wr6 + wunpckehuhmi wr3, wr6 + wunpckehuw wr3, wr6 + wunpckehsb wr3, wr6 + wunpckehsh wr3, wr6 + wunpckehsweq wr3, wr6 + + wunpckihb wr5, wr12, wr10 + wunpckihhhi wr5, wr12, wr10 + wunpckihw wr5, wr12, wr10 + + wunpckelub wr3, wr5 + wunpckeluhne wr3, wr5 + wunpckeluw wr3, wr5 + wunpckelsbgt wr3, wr5 + wunpckelsh wr3, wr5 + wunpckelsw wr3, wr5 + + wunpckilb wr4, wr5, wr10 + wunpckilh wr4, wr5, wr10 + wunpckilweq wr4, wr5, wr10 + + wxorne wr3, wr4, wr5 + + wzeroge wr7 + + tmcr wcgr0, r0 + tmrc r1, wcgr2 + + @ a.out-required section size padding + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt2.d b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt2.d new file mode 100644 index 00000000..2388f059 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt2.d @@ -0,0 +1,123 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt +#name: Intel(r) Wireless MMX(tm) technology instructions version 2 +#as: -mcpu=xscale+iwmmxt+iwmmxt2 -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <iwmmxt2> ee654186[ ]+waddhc[ ]+wr4, wr5, wr6 +0+004 <[^>]*> eea87189[ ]+waddwc[ ]+wr7, wr8, wr9 +0+008 <[^>]*> ce954106[ ]+wmadduxgt[ ]+wr4, wr5, wr6 +0+00c <[^>]*> 0ec87109[ ]+wmadduneq[ ]+wr7, wr8, wr9 +0+010 <[^>]*> 1eb54106[ ]+wmaddsxne[ ]+wr4, wr5, wr6 +0+014 <[^>]*> aee87109[ ]+wmaddsnge[ ]+wr7, wr8, wr9 +0+018 <[^>]*> eed21103[ ]+wmulumr[ ]+wr1, wr2, wr3 +0+01c <[^>]*> eef21103[ ]+wmulsmr[ ]+wr1, wr2, wr3 +0+020 <[^>]*> ce12f190[ ]+torvscbgt[ ]+pc +0+024 <[^>]*> 1e52f190[ ]+torvschne[ ]+pc +0+028 <[^>]*> 0e92f190[ ]+torvscweq[ ]+pc +0+02c <[^>]*> ee2211c0[ ]+wabsb[ ]+wr1, wr2 +0+030 <[^>]*> ee6431c0[ ]+wabsh[ ]+wr3, wr4 +0+034 <[^>]*> eea651c0[ ]+wabsw[ ]+wr5, wr6 +0+038 <[^>]*> ce2211c0[ ]+wabsbgt[ ]+wr1, wr2 +0+03c <[^>]*> ee1211c3[ ]+wabsdiffb[ ]+wr1, wr2, wr3 +0+040 <[^>]*> ee5541c6[ ]+wabsdiffh[ ]+wr4, wr5, wr6 +0+044 <[^>]*> ee9871c9[ ]+wabsdiffw[ ]+wr7, wr8, wr9 +0+048 <[^>]*> ce1211c3[ ]+wabsdiffbgt[ ]+wr1, wr2, wr3 +0+04c <[^>]*> ee6211a3[ ]+waddbhusm[ ]+wr1, wr2, wr3 +0+050 <[^>]*> ee2541a6[ ]+waddbhusl[ ]+wr4, wr5, wr6 +0+054 <[^>]*> ce6211a3[ ]+waddbhusmgt[ ]+wr1, wr2, wr3 +0+058 <[^>]*> ce2541a6[ ]+waddbhuslgt[ ]+wr4, wr5, wr6 +0+05c <[^>]*> eea211a3[ ]+waddsubhx[ ]+wr1, wr2, wr3 +0+060 <[^>]*> bea541a6[ ]+waddsubhxlt[ ]+wr4, wr5, wr6 +0+064 <[^>]*> 0ea211a3[ ]+waddsubhxeq[ ]+wr1, wr2, wr3 +0+068 <[^>]*> cea541a6[ ]+waddsubhxgt[ ]+wr4, wr5, wr6 +0+06c <[^>]*> ee421003[ ]+wavg4[ ]+wr1, wr2, wr3 +0+070 <[^>]*> ce454006[ ]+wavg4gt[ ]+wr4, wr5, wr6 +0+074 <[^>]*> ee521003[ ]+wavg4r[ ]+wr1, wr2, wr3 +0+078 <[^>]*> ce554006[ ]+wavg4rgt[ ]+wr4, wr5, wr6 +0+07c <[^>]*> fc711102[ ]+wldrd[ ]+wr1, \[r1\], -r2 +0+080 <[^>]*> fc712132[ ]+wldrd[ ]+wr2, \[r1\], -r2, lsl #3 +0+084 <[^>]*> fcf13102[ ]+wldrd[ ]+wr3, \[r1\], \+r2 +0+088 <[^>]*> fcf14142[ ]+wldrd[ ]+wr4, \[r1\], \+r2, lsl #4 +0+08c <[^>]*> fd515102[ ]+wldrd[ ]+wr5, \[r1, -r2\] +0+090 <[^>]*> fd516132[ ]+wldrd[ ]+wr6, \[r1, -r2, lsl #3\] +0+094 <[^>]*> fdd17102[ ]+wldrd[ ]+wr7, \[r1, \+r2\] +0+098 <[^>]*> fdd18142[ ]+wldrd[ ]+wr8, \[r1, \+r2, lsl #4\] +0+09c <[^>]*> fd719102[ ]+wldrd[ ]+wr9, \[r1, -r2\]! +0+0a0 <[^>]*> fd71a132[ ]+wldrd[ ]+wr10, \[r1, -r2, lsl #3\]! +0+0a4 <[^>]*> fdf1b102[ ]+wldrd[ ]+wr11, \[r1, \+r2\]! +0+0a8 <[^>]*> fdf1c142[ ]+wldrd[ ]+wr12, \[r1, \+r2, lsl #4\]! +0+0ac <[^>]*> ee821083[ ]+wmerge[ ]+wr1, wr2, wr3, #4 +0+0b0 <[^>]*> ce821083[ ]+wmergegt[ ]+wr1, wr2, wr3, #4 +0+0b4 <[^>]*> 0e3210a3[ ]+wmiatteq[ ]+wr1, wr2, wr3 +0+0b8 <[^>]*> ce2210a3[ ]+wmiatbgt[ ]+wr1, wr2, wr3 +0+0bc <[^>]*> 1e1210a3[ ]+wmiabtne[ ]+wr1, wr2, wr3 +0+0c0 <[^>]*> ce0210a3[ ]+wmiabbgt[ ]+wr1, wr2, wr3 +0+0c4 <[^>]*> 0e7210a3[ ]+wmiattneq[ ]+wr1, wr2, wr3 +0+0c8 <[^>]*> 1e6210a3[ ]+wmiatbnne[ ]+wr1, wr2, wr3 +0+0cc <[^>]*> ce5210a3[ ]+wmiabtngt[ ]+wr1, wr2, wr3 +0+0d0 <[^>]*> 0e4210a3[ ]+wmiabbneq[ ]+wr1, wr2, wr3 +0+0d4 <[^>]*> 0eb21123[ ]+wmiawtteq[ ]+wr1, wr2, wr3 +0+0d8 <[^>]*> cea21123[ ]+wmiawtbgt[ ]+wr1, wr2, wr3 +0+0dc <[^>]*> 1e921123[ ]+wmiawbtne[ ]+wr1, wr2, wr3 +0+0e0 <[^>]*> ce821123[ ]+wmiawbbgt[ ]+wr1, wr2, wr3 +0+0e4 <[^>]*> 1ef21123[ ]+wmiawttnne[ ]+wr1, wr2, wr3 +0+0e8 <[^>]*> cee21123[ ]+wmiawtbngt[ ]+wr1, wr2, wr3 +0+0ec <[^>]*> 0ed21123[ ]+wmiawbtneq[ ]+wr1, wr2, wr3 +0+0f0 <[^>]*> 1ec21123[ ]+wmiawbbnne[ ]+wr1, wr2, wr3 +0+0f4 <[^>]*> 0ed210c3[ ]+wmulwumeq[ ]+wr1, wr2, wr3 +0+0f8 <[^>]*> cec210c3[ ]+wmulwumrgt[ ]+wr1, wr2, wr3 +0+0fc <[^>]*> 1ef210c3[ ]+wmulwsmne[ ]+wr1, wr2, wr3 +0+100 <[^>]*> 0ee210c3[ ]+wmulwsmreq[ ]+wr1, wr2, wr3 +0+104 <[^>]*> ceb210c3[ ]+wmulwlgt[ ]+wr1, wr2, wr3 +0+108 <[^>]*> aeb210c3[ ]+wmulwlge[ ]+wr1, wr2, wr3 +0+10c <[^>]*> 1eb210a3[ ]+wqmiattne[ ]+wr1, wr2, wr3 +0+110 <[^>]*> 0ef210a3[ ]+wqmiattneq[ ]+wr1, wr2, wr3 +0+114 <[^>]*> cea210a3[ ]+wqmiatbgt[ ]+wr1, wr2, wr3 +0+118 <[^>]*> aee210a3[ ]+wqmiatbnge[ ]+wr1, wr2, wr3 +0+11c <[^>]*> 1e9210a3[ ]+wqmiabtne[ ]+wr1, wr2, wr3 +0+120 <[^>]*> 0ed210a3[ ]+wqmiabtneq[ ]+wr1, wr2, wr3 +0+124 <[^>]*> ce8210a3[ ]+wqmiabbgt[ ]+wr1, wr2, wr3 +0+128 <[^>]*> 1ec210a3[ ]+wqmiabbnne[ ]+wr1, wr2, wr3 +0+12c <[^>]*> ce121083[ ]+wqmulmgt[ ]+wr1, wr2, wr3 +0+130 <[^>]*> 0e321083[ ]+wqmulmreq[ ]+wr1, wr2, wr3 +0+134 <[^>]*> cec210e3[ ]+wqmulwmgt[ ]+wr1, wr2, wr3 +0+138 <[^>]*> 0ee210e3[ ]+wqmulwmreq[ ]+wr1, wr2, wr3 +0+13c <[^>]*> fc611102[ ]+wstrd[ ]+wr1, \[r1\], -r2 +0+140 <[^>]*> fc612132[ ]+wstrd[ ]+wr2, \[r1\], -r2, lsl #3 +0+144 <[^>]*> fce13102[ ]+wstrd[ ]+wr3, \[r1\], \+r2 +0+148 <[^>]*> fce14142[ ]+wstrd[ ]+wr4, \[r1\], \+r2, lsl #4 +0+14c <[^>]*> fd415102[ ]+wstrd[ ]+wr5, \[r1, -r2\] +0+150 <[^>]*> fd416132[ ]+wstrd[ ]+wr6, \[r1, -r2, lsl #3\] +0+154 <[^>]*> fdc17102[ ]+wstrd[ ]+wr7, \[r1, \+r2\] +0+158 <[^>]*> fdc18142[ ]+wstrd[ ]+wr8, \[r1, \+r2, lsl #4\] +0+15c <[^>]*> fd619102[ ]+wstrd[ ]+wr9, \[r1, -r2\]! +0+160 <[^>]*> fd61a132[ ]+wstrd[ ]+wr10, \[r1, -r2, lsl #3\]! +0+164 <[^>]*> fde1b102[ ]+wstrd[ ]+wr11, \[r1, \+r2\]! +0+168 <[^>]*> fde1c142[ ]+wstrd[ ]+wr12, \[r1, \+r2, lsl #4\]! +0+16c <[^>]*> ced211c3[ ]+wsubaddhxgt[ ]+wr1, wr2, wr3 +0+170 <[^>]*> fe721140[ ]+wrorh[ ]+wr1, wr2, #16 +0+174 <[^>]*> feb21040[ ]+wrorw[ ]+wr1, wr2, #32 +0+178 <[^>]*> ee021002[ ]+wor[ ]+wr1, wr2, wr2 +0+17c <[^>]*> fe721145[ ]+wrorh[ ]+wr1, wr2, #21 +0+180 <[^>]*> feb2104d[ ]+wrorw[ ]+wr1, wr2, #13 +0+184 <[^>]*> fef2104e[ ]+wrord[ ]+wr1, wr2, #14 +0+188 <[^>]*> fe721140[ ]+wrorh[ ]+wr1, wr2, #16 +0+18c <[^>]*> feb21040[ ]+wrorw[ ]+wr1, wr2, #32 +0+190 <[^>]*> ee021002[ ]+wor[ ]+wr1, wr2, wr2 +0+194 <[^>]*> fe59204b[ ]+wsllh[ ]+wr2, wr9, #11 +0+198 <[^>]*> fe95304d[ ]+wsllw[ ]+wr3, wr5, #13 +0+19c <[^>]*> fed8304f[ ]+wslld[ ]+wr3, wr8, #15 +0+1a0 <[^>]*> fe721140[ ]+wrorh[ ]+wr1, wr2, #16 +0+1a4 <[^>]*> feb21040[ ]+wrorw[ ]+wr1, wr2, #32 +0+1a8 <[^>]*> ee021002[ ]+wor[ ]+wr1, wr2, wr2 +0+1ac <[^>]*> fe49204c[ ]+wsrah[ ]+wr2, wr9, #12 +0+1b0 <[^>]*> fe85304e[ ]+wsraw[ ]+wr3, wr5, #14 +0+1b4 <[^>]*> fec83140[ ]+wsrad[ ]+wr3, wr8, #16 +0+1b8 <[^>]*> fe721140[ ]+wrorh[ ]+wr1, wr2, #16 +0+1bc <[^>]*> feb21040[ ]+wrorw[ ]+wr1, wr2, #32 +0+1c0 <[^>]*> ee021002[ ]+wor[ ]+wr1, wr2, wr2 +0+1c4 <[^>]*> fe69204c[ ]+wsrlh[ ]+wr2, wr9, #12 +0+1c8 <[^>]*> fea5304e[ ]+wsrlw[ ]+wr3, wr5, #14 +0+1cc <[^>]*> fee83140[ ]+wsrld[ ]+wr3, wr8, #16 diff --git a/binutils-2.25/gas/testsuite/gas/arm/iwmmxt2.s b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt2.s new file mode 100644 index 00000000..801166d3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/iwmmxt2.s @@ -0,0 +1,142 @@ + .text + .global iwmmxt2 +iwmmxt2: + + waddhc wr4, wr5, wr6 + waddwc wr7, wr8, wr9 + + wmadduxgt wr4, wr5, wr6 + wmadduneq wr7, wr8, wr9 + wmaddsxne wr4, wr5, wr6 + wmaddsnge wr7, wr8, wr9 + + wmulumr wr1, wr2, wr3 + wmulsmr wr1, wr2, wr3 + + torvscbgt r15 + torvschne r15 + torvscweq r15 + + wabsb wr1, wr2 + wabsh wr3, wr4 + wabsw wr5, wr6 + wabsbgt wr1, wr2 + + wabsdiffb wr1, wr2, wr3 + wabsdiffh wr4, wr5, wr6 + wabsdiffw wr7, wr8, wr9 + wabsdiffbgt wr1, wr2, wr3 + + waddbhusm wr1, wr2, wr3 + waddbhusl wr4, wr5, wr6 + waddbhusmgt wr1, wr2, wr3 + waddbhuslgt wr4, wr5, wr6 + + waddsubhx wr1, wr2, wr3 + waddsubhxlt wr4, wr5, wr6 + waddsubhxeq wr1, wr2, wr3 + waddsubhxgt wr4, wr5, wr6 + + wavg4 wr1, wr2, wr3 + wavg4gt wr4, wr5, wr6 + wavg4r wr1, wr2, wr3 + wavg4rgt wr4, wr5, wr6 + + wldrd wr1, [r1], -r2 + wldrd wr2, [r1], -r2,lsl #3 + wldrd wr3, [r1], +r2 + wldrd wr4, [r1], +r2,lsl #4 + wldrd wr5, [r1, -r2] + wldrd wr6, [r1, -r2,lsl #3] + wldrd wr7, [r1, +r2] + wldrd wr8, [r1, +r2,lsl #4] + wldrd wr9, [r1, -r2]! + wldrd wr10, [r1, -r2,lsl #3]! + wldrd wr11, [r1, +r2]! + wldrd wr12, [r1, +r2,lsl #4]! + + wmerge wr1, wr2, wr3, #4 + wmergegt wr1, wr2, wr3, #4 + + wmiatteq wr1, wr2, wr3 + wmiatbgt wr1, wr2, wr3 + wmiabtne wr1, wr2, wr3 + wmiabbgt wr1, wr2, wr3 + wmiattneq wr1, wr2, wr3 + wmiatbnne wr1, wr2, wr3 + wmiabtngt wr1, wr2, wr3 + wmiabbneq wr1, wr2, wr3 + + wmiawtteq wr1, wr2, wr3 + wmiawtbgt wr1, wr2, wr3 + wmiawbtne wr1, wr2, wr3 + wmiawbbgt wr1, wr2, wr3 + wmiawttnne wr1, wr2, wr3 + wmiawtbngt wr1, wr2, wr3 + wmiawbtneq wr1, wr2, wr3 + wmiawbbnne wr1, wr2, wr3 + + wmulwumeq wr1, wr2, wr3 + wmulwumrgt wr1, wr2, wr3 + wmulwsmne wr1, wr2, wr3 + wmulwsmreq wr1, wr2, wr3 + wmulwlgt wr1, wr2, wr3 + wmulwlge wr1, wr2, wr3 + + wqmiattne wr1, wr2, wr3 + wqmiattneq wr1, wr2, wr3 + wqmiatbgt wr1, wr2, wr3 + wqmiatbnge wr1, wr2, wr3 + wqmiabtne wr1, wr2, wr3 + wqmiabtneq wr1, wr2, wr3 + wqmiabbgt wr1, wr2, wr3 + wqmiabbnne wr1, wr2, wr3 + + wqmulmgt wr1, wr2, wr3 + wqmulmreq wr1, wr2, wr3 + + wqmulwmgt wr1, wr2, wr3 + wqmulwmreq wr1, wr2, wr3 + + wstrd wr1, [r1], -r2 + wstrd wr2, [r1], -r2,lsl #3 + wstrd wr3, [r1], +r2 + wstrd wr4, [r1], +r2,lsl #4 + wstrd wr5, [r1, -r2] + wstrd wr6, [r1, -r2,lsl #3] + wstrd wr7, [r1, +r2] + wstrd wr8, [r1, +r2,lsl #4] + wstrd wr9, [r1, -r2]! + wstrd wr10, [r1, -r2,lsl #3]! + wstrd wr11, [r1, +r2]! + wstrd wr12, [r1, +r2,lsl #4]! + + wsubaddhxgt wr1, wr2, wr3 + + wrorh wr1, wr2, #0 + wrorw wr1, wr2, #0 + wrord wr1, wr2, #0 + wrorh wr1, wr2, #21 + wrorw wr1, wr2, #13 + wrord wr1, wr2, #14 + + wsllh wr1, wr2, #0 + wsllw wr1, wr2, #0 + wslld wr1, wr2, #0 + wsllh wr2, wr9, #11 + wsllw wr3, wr5, #13 + wslld wr3, wr8, #15 + + wsrah wr1, wr2, #0 + wsraw wr1, wr2, #0 + wsrad wr1, wr2, #0 + wsrah wr2, wr9, #12 + wsraw wr3, wr5, #14 + wsrad wr3, wr8, #16 + + wsrlh wr1, wr2, #0 + wsrlw wr1, wr2, #0 + wsrld wr1, wr2, #0 + wsrlh wr2, wr9, #12 + wsrlw wr3, wr5, #14 + wsrld wr3, wr8, #16 diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.d new file mode 100644 index 00000000..c1f89b40 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (cortex m3) +# as: -mcpu=cortex-m3 +# source: ld-sp-warn.s +# error-output: ld-sp-warn-cortex-m3.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.l new file mode 100644 index 00000000..48ac57fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m3.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.d new file mode 100644 index 00000000..0ae6d98e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (cortex m4) +# as: -mcpu=cortex-m4 +# source: ld-sp-warn.s +# error-output: ld-sp-warn-cortex-m4.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.l new file mode 100644 index 00000000..48ac57fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-cortex-m4.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7.d new file mode 100644 index 00000000..4d3b0a5b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (v7) +# as: -march=armv7 +# source: ld-sp-warn.s +# error-output: ld-sp-warn-v7.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7.l new file mode 100644 index 00000000..48ac57fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7a.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7a.d new file mode 100644 index 00000000..2f7dc8dc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7a.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (v7a) +# as: -march=armv7-a +# source: ld-sp-warn.s +# error-output: ld-sp-warn-v7a.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7a.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7a.l new file mode 100644 index 00000000..40f0999e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7a.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7e-m.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7e-m.l new file mode 100644 index 00000000..48ac57fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7e-m.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7em.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7em.d new file mode 100644 index 00000000..d69368e2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7em.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (v7em) +# as: -march=armv7e-m +# source: ld-sp-warn.s +# error-output: ld-sp-warn-v7e-m.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7m.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7m.d new file mode 100644 index 00000000..f2683577 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7m.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (v7m) +# as: -march=armv7m +# source: ld-sp-warn.s +# error-output: ld-sp-warn-v7m.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7m.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7m.l new file mode 100644 index 00000000..48ac57fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7m.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7r.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7r.d new file mode 100644 index 00000000..59a5db4f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7r.d @@ -0,0 +1,4 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP (v7r) +# as: -march=armv7-r +# source: ld-sp-warn.s +# error-output: ld-sp-warn-v7r.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7r.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7r.l new file mode 100644 index 00000000..40f0999e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn-v7r.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.d b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.d new file mode 100644 index 00000000..dcbbdd26 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.d @@ -0,0 +1,3 @@ +# name: Erratum 752419: Warn Loads with writebacks to SP +# source: ld-sp-warn.s +# error-output: ld-sp-warn.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.l b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.l new file mode 100644 index 00000000..48ac57fa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled. +[^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!' +[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.s b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.s new file mode 100644 index 00000000..87e3e953 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ld-sp-warn.s @@ -0,0 +1,8 @@ +.syntax unified +.thumb +ldr sp, [r0, #16]! +ldr sp, [r1], #8 +ldr sp, [r0, #16] +ldr r1, [r0, #16] +ldr r1, [r0, r1]! +ldrsb sp, [r2, #16]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldconst.d b/binutils-2.25/gas/testsuite/gas/arm/ldconst.d new file mode 100644 index 00000000..3d063785 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldconst.d @@ -0,0 +1,27 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM ldr with immediate constant +#as: -mcpu=arm7m -EL + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> e3a00000 ? mov r0, #0 +0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 ; 0xff000000 +0+08 <[^>]*> e3e00000 ? mvn r0, #0 +0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+10 <[^>]*> +0+10 <[^>]*> 0fff0000 ? .* +0+14 <[^>]*> e3a0e000 ? mov lr, #0 +0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 ; 0xff0000 +0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 ; 0xff0000 +0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] ; 0+24 <[^>]*> +0+24 <[^>]*> 00fff000 ? .* +0+28 <[^>]*> 03a00000 ? moveq r0, #0 +0+2c <[^>]*> 03a00cff ? moveq r0, #65280 ; 0xff00 +0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 ; 0xff00 +0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] ; 0+38 <[^>]*> +0+38 <[^>]*> 000fff00 ? .* +0+3c <[^>]*> 43a0b000 ? movmi fp, #0 +0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 ; 0xff +0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff +0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*> +0+4c <[^>]*> 0000fff0 ? .* diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldconst.s b/binutils-2.25/gas/testsuite/gas/arm/ldconst.s new file mode 100644 index 00000000..1b6aca90 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldconst.s @@ -0,0 +1,28 @@ +@ Test file for ARM/GAS -- ldr reg, =... expressions. + +.text +.align +foo: + ldr r0, =0 + ldr r0, =0xff000000 + ldr r0, =-1 + ldr r0, =0x0fff0000 + .pool + + ldr r14, =0 + ldr r14, =0x00ff0000 + ldr r14, =0xff00ffff + ldr r14, =0x00fff000 + .pool + + ldreq r0, =0 + ldreq r0, =0x0000ff00 + ldreq r0, =0xffff00ff + ldreq r0, =0x000fff00 + .pool + + ldrmi r11, =0 + ldrmi r11, =0x000000ff + ldrmi r11, =0xffffff00 + ldrmi r11, =0x0000fff0 + .pool diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.d b/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.d new file mode 100644 index 00000000..f11df796 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.d @@ -0,0 +1,3 @@ +# name: Reject ld<cc>sb instructions +# as: -march=armv7-a +# error-output: ldgesb-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.l b/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.l new file mode 100644 index 00000000..71beeeb0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*Error: bad instruction `ldgesb r1,\[r11,#4\]' +.*Warning: section '.text' finished with an open IT block. diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.s b/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.s new file mode 100644 index 00000000..d40b6f8e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldgesb-bad.s @@ -0,0 +1,7 @@ +.syntax unified +.arch armv7-a +.thumb + .global foo +foo: + it ge + ldgesb r1, [r11, #4] diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.d b/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.d new file mode 100644 index 00000000..e7c93c31 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.d @@ -0,0 +1,3 @@ +# name: Reject ld<cc>sh instructions +# as: -march=armv7-a +# error-output: ldgesh-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.l b/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.l new file mode 100644 index 00000000..9cb9d4bc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*Error: bad instruction `ldgesh r1,\[r11,#4\]' +.*Warning: section '.text' finished with an open IT block. diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.s b/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.s new file mode 100644 index 00000000..c51fa3df --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldgesh-bad.s @@ -0,0 +1,7 @@ +.syntax unified +.arch armv7-a +.thumb + .global foo +foo: + it ge + ldgesh r1, [r11, #4] diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.d b/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.d new file mode 100644 index 00000000..82a17180 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.d @@ -0,0 +1,3 @@ +# name: Unpredictable operations - ldr - arm +# error-output: ldr-bad.l + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.l b/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.l new file mode 100644 index 00000000..554b4a33 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.l @@ -0,0 +1,12 @@ +[^:]*: Assembler messages: +[^:]*:5: Warning: destination register same as write-back base +[^:]*:9: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]' +[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7' +[^:]*:15: Warning: destination register same as write-back base +[^:]*:16: Error: cannot use register index with PC-relative addressing -- `ldr r2,\[r15,r2\]!' +[^:]*:19: Error: cannot use register index with PC-relative addressing -- `ldr r1,\[r1,r15\]' +[^:]*:22: Warning: source register same as write-back base +[^:]*:23: Error: cannot use register index with PC-relative addressing -- `str r1,\[r15,#10\]!' +[^:]*:26: Warning: source register same as write-back base +[^:]*:27: Error: cannot use register index with PC-relative addressing -- `str r1,\[r15,r2\]!' + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.s b/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.s new file mode 100644 index 00000000..2d452b6b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-bad.s @@ -0,0 +1,28 @@ +.syntax unified + +.arm + @wback && (n == t) + ldr r1, [r1, #5]! + + @rt == r15 && rn == r15 + @ && bits<0..1> (immediate) != 00 + ldr r15, [r15, #5] + + @rt == r15 && bits<0..1> (immediate) != 00 + ldr r15, .-0xab7 + + @wback && (n == t || n == 15) + ldr r1, [r1, r2]! + ldr r2, [r15, r2]! + + @rm == 15 + ldr r1, [r1, r15] + + @wback && (n == t || n == 15) + str r1, [r1, #10]! + str r1, [r15, #10]! + + @wback && (n == t || n == 15) + str r1, [r1, r2]! + str r1, [r15, r2]! + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-global.d b/binutils-2.25/gas/testsuite/gas/arm/ldr-global.d new file mode 100644 index 00000000..3528d4ef --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-global.d @@ -0,0 +1,14 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: PC-relative LDR from global + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]*> e59f0010 ? ldr r0, \[pc, #16\] ; 0+18 <[^>]*> +0+04 <[^>]*> e1df00fc ? ldrsh r0, \[pc, #12\] ; 0+18 <[^>]*> +0+08 <[^>]*> ed9f0a02 ? vldr s0, \[pc, #8\] ; 0+18 <[^>]*> +0+0c <[^>]*> 4802 ? ldr r0, \[pc, #8\] ; \(0+18 <[^>]*>\) +0+0e <[^>]*> 4802 ? ldr r0, \[pc, #8\] ; \(0+18 <[^>]*>\) +0+10 <[^>]*> ed9f 0a01 ? vldr s0, \[pc, #4\] ; 0+18 <[^>]*> +0+14 <[^>]*> f8df 0000 ? ldr\.w r0, \[pc\] ; 0+18 <[^>]*> +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-global.s b/binutils-2.25/gas/testsuite/gas/arm/ldr-global.s new file mode 100644 index 00000000..ef3960c5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-global.s @@ -0,0 +1,22 @@ +@ Test pc-relative loads from global objects defined in the same text segment. +@ See tc-arm.c:arm_force_relocation. +.arch armv7-a +.fpu vfp +.syntax unified +.text +foo_arm: + ldr r0, bar + ldrsh r0, bar + vldr s0, bar +.thumb +foo_thumb: + ldr r0, bar + ldr.n r0, bar + vldr s0, bar + ldr.w r0, bar + +.align 2 +.globl bar +bar: + .word 42 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.d b/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.d new file mode 100644 index 00000000..0c28a85c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.d @@ -0,0 +1,3 @@ +# name: Unpredictable operations - ldr - thumb +# error-output: ldr-t-bad.l + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.l b/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.l new file mode 100644 index 00000000..95f420aa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.l @@ -0,0 +1,16 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: registers may not be the same -- `ldr r1,\[r1,#5\]!' +[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]' +[^:]*:16: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,#4\]' +[^:]*:25: Error: branch must be last instruction in IT block -- `ldrge r15,.0x4' +[^:]*:30: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7' +[^:]*:36: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,r1\]' +[^:]*:41: Error: r13 not allowed here -- `ldr r1,\[r2,r13\]' +[^:]*:42: Error: r15 not allowed here -- `ldr r2,\[r2,r15\]' +[^:]*:47: Error: r15 not allowed here -- `str r15,\[r1,#10\]' +[^:]*:48: Error: cannot use register index with PC-relative addressing -- `str r1,\[r15,#10\]' +[^:]*:51: Error: registers may not be the same -- `str r1,\[r1,#10\]!' +[^:]*:56: Error: r15 not allowed here -- `str r15,\[r1,r2\]' +[^:]*:57: Error: r13 not allowed here -- `str r1,\[r2,r13\]' +[^:]*:58: Error: r15 not allowed here -- `str r1,\[r2,r15\]' +[^:]*:61: Error: Instruction does not support =N addresses -- `ldrt r0,=0x0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.s b/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.s new file mode 100644 index 00000000..a1e22bd7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-t-bad.s @@ -0,0 +1,61 @@ +.syntax unified +.arch armv7-a +.thumb + + @ldr-immediate + + @wback && (n == t) + ldr r1, [r1, #5]! + + @rt == r15 && rn == r15 + @ && bits<0..1> (immediate) != 00 + ldr r15, [r15, #5] + + @inITBlock && rt == 15 && !lastInITBlock + ittt ge + ldrge r15, [r15, #4] + nopge + nopge + + @ldr-literal + + + @inITBlock && rt == 15 && !lastInITBlock + ittt ge + ldrge r15, .0x4 + nopge + nopge + + @rt == r15 && bits<0..1> (immediate) != 00 + ldr r15, .-0xab7 + + @ldr-register + + @inITBlock && rt == 15 && !lastInITBlock + ittt ge + ldrge r15, [r15, r1] + nopge + nopge + + @rm == 13 || rm == 15 + ldr r1, [r2, r13] + ldr r2, [r2, r15] + + @str-immediate + + @rt == 15 || rn == 15 + str r15, [r1, #10] + str r1, [r15, #10] + + @wback && (n == t) + str r1, [r1, #10]! + + @str-register + + @rt == 15 || rm == 13 || rm == 15 + str r15, [r1, r2] + str r1, [r2, r13] + str r1, [r2, r15] + + @ PR 14260 + ldrt r0, =0x0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-t.d b/binutils-2.25/gas/testsuite/gas/arm/ldr-t.d new file mode 100644 index 00000000..ddcd6127 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-t.d @@ -0,0 +1,37 @@ +# name: ldr - thumb +#objdump: -dr --prefix-address --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section [^>]+: +0+00 <[^>]+> f8d1 1005 ldr.w r1, \[r1, #5\] +0+04 <[^>]+> f852 1f05 ldr.w r1, \[r2, #5\]! +0+08 <[^>]+> f8df 1005 ldr.w r1, \[pc, #5\] ; 0+11 <[^>]+0x11> +0+0c <[^>]+> f8d1 f005 ldr.w pc, \[r1, #5\] +0+10 <[^>]+> f8df f004 ldr.w pc, \[pc, #4\] ; 0+18 <[^>]+0x18> +0+14 <[^>]+> bfa2 ittt ge +0+16 <[^>]+> 4901 ldrge r1, \[pc, #4\] ; \(0+1c <[^>]+0x1c>\) +0+18 <[^>]+> bf00 nopge +0+1a <[^>]+> bf00 nopge +0+1c <[^>]+> bfa8 it ge +0+1e <[^>]+> f8df f004 ldrge.w pc, \[pc, #4\] ; 0+24 <[^>]+0x24> +0+22 <[^>]+> bfa2 ittt ge +0+24 <[^>]+> f85f 1ab8 ldrge.w r1, \[pc, #-2744\] ; fffff570 <[^>]+> +0+28 <[^>]+> bf00 nopge +0+2a <[^>]+> bf00 nopge +0+2c <[^>]+> bfa8 it ge +0+2e <[^>]+> f85f fab6 ldrge.w pc, \[pc, #-2742\] ; fffff57a <[^>]+> +0+32 <[^>]+> f85f 1ab9 ldr.w r1, \[pc, #-2745\] ; fffff57b <[^>]+> +0+36 <[^>]+> f85f fab6 ldr.w pc, \[pc, #-2742\] ; fffff582 <[^>]+> +0+3a <[^>]+> bfa2 ittt ge +0+3c <[^>]+> 5851 ldrge r1, \[r2, r1\] +0+3e <[^>]+> bf00 nopge +0+40 <[^>]+> bf00 nopge +0+42 <[^>]+> bfa8 it ge +0+44 <[^>]+> f852 f001 ldrge.w pc, \[r2, r1\] +0+48 <[^>]+> 58d1 ldr r1, \[r2, r3\] +0+4a <[^>]+> f8c2 100a str.w r1, \[r2, #10\] +0+4e <[^>]+> f8c1 100a str.w r1, \[r1, #10\] +0+52 <[^>]+> f842 1f0a str.w r1, \[r2, #10\]! +0+56 <[^>]+> 50d1 str r1, \[r2, r3\] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr-t.s b/binutils-2.25/gas/testsuite/gas/arm/ldr-t.s new file mode 100644 index 00000000..4aaecdf6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr-t.s @@ -0,0 +1,84 @@ +.syntax unified +.arch armv7-a +.thumb + .global foo +foo: + @ldr-immediate + + @!wback && (n == t) + ldr r1, [r1, #5] + + @wback && !(n == t) + ldr r1, [r2, #5]! + + @!(rt == r15) && rn == r15 + @ && bits<0..1> (immediate) != 00 + ldr r1, [r15, #5] + + @rt == r15 && !(rn == r15) + @ && bits<0..1> (immediate) != 00 + ldr r15, [r1, #5] + + @rt == r15 && rn == r15 + @ && bits<0..1> (immediate) == 00 + ldr r15, [r15, #4] + + @inITBlock && !(rt == 15) && !lastInITBlock + ittt ge + ldrge r1, [r15, #4] + nopge + nopge + + @inITBlock && rt == 15 && lastInITBlock + it ge + ldrge r15, [r15, #4] + + @ldr-literal + + @inITBlock && !(rt == 15) && !lastInITBlock + ittt ge + ldrge r1, .-0xab4 + nopge + nopge + + @inITBlock && (rt == 15) && lastInITBlock + it ge + ldrge r15, .-0xab4 + + @!(rt == r15) && bits<0..1> (immediate) != 00 + ldr r1, .-0xab7 + + @rt == r15 && bits<0..1> (immediate) == 00 + ldr r15, .-0xab4 + + @ldr-register + + @inITBlock && !(rt == 15) && !lastInITBlock + ittt ge + ldrge r1, [r2, r1] + nopge + nopge + + @inITBlock && (rt == 15) && lastInITBlock + it ge + ldrge r15, [r2, r1] + + @!(rm == 13 || rm == 15) + ldr r1, [r2, r3] + + @str-immediate + + @!(rt == 15 || rn == 15) + str r1, [r2, #10] + + @!wback && (n == t) + str r1, [r1, #10] + + @wback && !(n == t) + str r1, [r2, #10]! + + @str-register + + @!(rt == 15 || rm == 13 || rm == 15) + str r1, [r2, r3] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr.d b/binutils-2.25/gas/testsuite/gas/arm/ldr.d new file mode 100644 index 00000000..6e959dee --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr.d @@ -0,0 +1,24 @@ +# name: ldr - arm +#objdump: -dr --prefix-address --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+00 <[^>]+> e5911005 ldr r1, \[r1, #5\] +0+04 <[^>]+> e5b21005 ldr r1, \[r2, #5\]! +0+08 <[^>]+> e59f1005 ldr r1, \[pc, #5\] ; 0+15 <[^>]+0x15> +0+0c <[^>]+> e591f005 ldr pc, \[r1, #5\] +0+10 <[^>]+> e59ff004 ldr pc, \[pc, #4\] ; 0+1c <[^>]+0x1c> +0+14 <[^>]+> e51ffabc ldr pc, \[pc, #-2748\] ; fffff560 <[^>]+> +0+18 <[^>]+> e51f1abf ldr r1, \[pc, #-2751\] ; fffff561 <[^>]+> +0+1c <[^>]+> e7911002 ldr r1, \[r1, r2\] +0+20 <[^>]+> e79f2002 ldr r2, \[pc, r2\] +0+24 <[^>]+> e7b21003 ldr r1, \[r2, r3\]! +0+28 <[^>]+> e791100c ldr r1, \[r1, ip\] +0+2c <[^>]+> e581100a str r1, \[r1, #10\] +0+30 <[^>]+> e58f100a str r1, \[pc, #10\] ; 0+42 <[^>]+0x42> +0+34 <[^>]+> e5a2100a str r1, \[r2, #10\]! +0+38 <[^>]+> e7811002 str r1, \[r1, r2\] +0+3c <[^>]+> e78f1002 str r1, \[pc, r2\] +0+40 <[^>]+> e7a21003 str r1, \[r2, r3\]! + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldr.s b/binutils-2.25/gas/testsuite/gas/arm/ldr.s new file mode 100644 index 00000000..f09d1b0c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldr.s @@ -0,0 +1,62 @@ +.syntax unified + +.arm + + @ldr-immediate + + @!wback && (n == t) + ldr r1, [r1, #5] + + @wback && !(n == t) + ldr r1, [r2, #5]! + + @ !(rt == r15) && (rn == r15) + @ && bits<0..1> (immediate) != 00 + ldr r1, [r15, #5] + + @ (rt == r15) && !(rn == r15) + @ && bits<0..1> (immediate) != 00 + ldr r15, [r1, #5] + + @ ((rt == r15) && ((rn == r15) + @ && (bits<0..1> (immediate) == 00))) + ldr r15, [r15, #4] + + @ldr-literal + + @rt == r15 && (bits<0..1> (immediate) == 00) + ldr r15, .-0xab4 + + @(!rt == r15) && bits<0..1> (immediate) != 00 + ldr r1, .-0xab7 + + @ldr-register + + @!wback && (n == t || n == 15) + ldr r1, [r1, r2] + ldr r2, [r15, r2] + + @wback && !(n == t || n == 15) + ldr r1, [r2, r3]! + + @rm != 15 + ldr r1, [r1, r12] + + @str-immediate + + @!wback && (n == t || n == 15) + str r1, [r1, #10] + str r1, [r15, #10] + + @wback && !(n == t || n == 15) + str r1, [r2, #10]! + + @str-register + + @!wback && (n == t || n == 15) + str r1, [r1, r2] + str r1, [r15, r2] + + @wback && !(n == t || n == 15) + str r1, [r2, r3]! + diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.d b/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.d new file mode 100644 index 00000000..10561b82 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.d @@ -0,0 +1,2 @@ +# name: Unpredictable LDRD and STRD instructions. - ARM +# error-output: ldrd-unpredictable.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.l b/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.l new file mode 100644 index 00000000..32717145 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.l @@ -0,0 +1,7 @@ +[^:]*: Assembler messages: +[^:]*:6: Warning: index register overlaps transfer register +[^:]*:7: Warning: index register overlaps transfer register +[^:]*:8: Warning: source register same as write-back base +[^:]*:9: Warning: base register written back, and overlaps second transfer register +[^:]*:13: Warning: source register same as write-back base +[^:]*:14: Warning: base register written back, and overlaps second transfer register diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.s b/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.s new file mode 100644 index 00000000..9bc20750 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldrd-unpredictable.s @@ -0,0 +1,14 @@ +.syntax unified
+
+.arm
+
+@ LDRD
+ldrd r0,r1,[r0,r1] @ unpredictable
+ldrd r0,r1,[r1,r0] @ ditto
+ldrd r0,r1,[r0,r2]! @ ditto
+ldrd r0,r1,[r1,r2]! @ ditto
+
+@ STRD
+
+strd r0,r1,[r0,r2]! @ ditto
+strd r0,r1,[r1,r2]! @ ditto
diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.d b/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.d new file mode 100644 index 00000000..2c674aa1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.d @@ -0,0 +1,2 @@ +# name: Accept lds<cc>sb mnemonics +# error-output: ldsgeb.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.l b/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.l new file mode 100644 index 00000000..bcc175b5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: conditional infixes are deprecated in unified syntax diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.s b/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.s new file mode 100644 index 00000000..15587bda --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldsgeb.s @@ -0,0 +1,7 @@ +.syntax unified +.arch armv7-a +.thumb + .global foo +foo: + it ge + ldsgeb r1, [r11, #4] diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.d b/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.d new file mode 100644 index 00000000..293d761c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.d @@ -0,0 +1,2 @@ +# name: Accept lds<cc>sh mnemonics +# error-output: ldsgeh.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.l b/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.l new file mode 100644 index 00000000..bcc175b5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: conditional infixes are deprecated in unified syntax diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.s b/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.s new file mode 100644 index 00000000..b33b32b3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldsgeh.s @@ -0,0 +1,7 @@ +.syntax unified +.arch armv7-a +.thumb + .global foo +foo: + it ge + ldsgeh r1, [r11, #4] diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldst-offset0.d b/binutils-2.25/gas/testsuite/gas/arm/ldst-offset0.d new file mode 100644 index 00000000..5c1f88b3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldst-offset0.d @@ -0,0 +1,51 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM load/store with 0 offset +#as: + +# Test the standard ARM instructions: + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> e5121000 ldr r1, \[r2, #-0\] +0+004 <[^>]*> e5121000 ldr r1, \[r2, #-0\] +0+008 <[^>]*> e5921000 ldr r1, \[r2\] +0+00c <[^>]*> e5921000 ldr r1, \[r2\] +0+010 <[^>]*> e5321000 ldr r1, \[r2, #-0\]! +0+014 <[^>]*> e5321000 ldr r1, \[r2, #-0\]! +0+018 <[^>]*> e5b21000 ldr r1, \[r2, #0\]! +0+01c <[^>]*> e5b21000 ldr r1, \[r2, #0\]! +0+020 <[^>]*> e4121000 ldr r1, \[r2\], #-0 +0+024 <[^>]*> e4121000 ldr r1, \[r2\], #-0 +0+028 <[^>]*> e4921000 ldr r1, \[r2\], #0 +0+02c <[^>]*> e4921000 ldr r1, \[r2\], #0 +0+030 <[^>]*> e5b21000 ldr r1, \[r2, #0\]! +0+034 <[^>]*> e5921000 ldr r1, \[r2\] +0+038 <[^>]*> e4f21000 ldrbt r1, \[r2\], #0 +0+03c <[^>]*> e4721000 ldrbt r1, \[r2\], #-0 +0+040 <[^>]*> e4f21000 ldrbt r1, \[r2\], #0 +0+044 <[^>]*> 5d565300 ldclpl 3, cr5, \[r6, #-0\] +0+048 <[^>]*> 5dd65300 ldclpl 3, cr5, \[r6\] +0+04c <[^>]*> e5021000 str r1, \[r2, #-0\] +0+050 <[^>]*> e5021000 str r1, \[r2, #-0\] +0+054 <[^>]*> e5821000 str r1, \[r2\] +0+058 <[^>]*> e5821000 str r1, \[r2\] +0+05c <[^>]*> e5221000 str r1, \[r2, #-0\]! +0+060 <[^>]*> e5221000 str r1, \[r2, #-0\]! +0+064 <[^>]*> e5a21000 str r1, \[r2, #0\]! +0+068 <[^>]*> e5a21000 str r1, \[r2, #0\]! +0+06c <[^>]*> e4021000 str r1, \[r2\], #-0 +0+070 <[^>]*> e4021000 str r1, \[r2\], #-0 +0+074 <[^>]*> e4821000 str r1, \[r2\], #0 +0+078 <[^>]*> e4821000 str r1, \[r2\], #0 +0+07c <[^>]*> e5a21000 str r1, \[r2, #0\]! +0+080 <[^>]*> e5821000 str r1, \[r2\] +0+084 <[^>]*> e4e21000 strbt r1, \[r2\], #0 +0+088 <[^>]*> e4621000 strbt r1, \[r2\], #-0 +0+08c <[^>]*> e4e21000 strbt r1, \[r2\], #0 +0+090 <[^>]*> 5d465300 stclpl 3, cr5, \[r6, #-0\] +0+094 <[^>]*> 5dc65300 stclpl 3, cr5, \[r6\] +0+098 <[^>]*> e59f0004 ldr r0, \[pc, #4\] ; .* +0+09c <[^>]*> e59f0000 ldr r0, \[pc\] ; .* +0+0a0 <[^>]*> e51f0004 ldr r0, \[pc, #-4\] ; .* +0+0a4 <[^>]*> 00000000 .word 0x00000000 diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldst-offset0.s b/binutils-2.25/gas/testsuite/gas/arm/ldst-offset0.s new file mode 100644 index 00000000..9b0900f6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldst-offset0.s @@ -0,0 +1,66 @@ +@ Test file for ARM load/store instructions with 0 offset + + .text + .syntax unified + ldr r1, [r2, #-0] + ldr r1, [r2, #-1+1] + + ldr r1, [r2, #1-1] + ldr r1, [r2, #0] + + ldr r1, [r2, #-0]! + ldr r1, [r2, #-1+1]! + + ldr r1, [r2, #1-1]! + ldr r1, [r2, #0]! + + ldr r1, [r2], #-0 + ldr r1, [r2], #-1+1 + + ldr r1, [r2], #1-1 + ldr r1, [r2], #0 + + ldr r1, [r2]! + ldr r1, [r2] + + ldrbt r1, [r2], #0 + ldrbt r1, [r2], #-0 + + ldrbt r1, [r2] + + ldclpl p3, c5, [r6, #-0] + ldclpl p3, c5, [r6, #0] + + str r1, [r2, #-0] + str r1, [r2, #-1+1] + + str r1, [r2, #1-1] + str r1, [r2, #0] + + str r1, [r2, #-0]! + str r1, [r2, #-1+1]! + + str r1, [r2, #1-1]! + str r1, [r2, #0]! + + str r1, [r2], #-0 + str r1, [r2], #-1+1 + + str r1, [r2], #1-1 + str r1, [r2], #0 + + str r1, [r2]! + str r1, [r2] + + strbt r1, [r2], #0 + strbt r1, [r2], #-0 + + strbt r1, [r2] + + stclpl p3, c5, [r6, #-0] + stclpl p3, c5, [r6, #0] + + ldr r0,1f + ldr r0,1f + ldr r0,1f +1: .word 0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldst-pc.d b/binutils-2.25/gas/testsuite/gas/arm/ldst-pc.d new file mode 100644 index 00000000..7a745c54 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldst-pc.d @@ -0,0 +1,25 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM load/store with pc base register +#as: -mno-warn-deprecated + +# Test the standard ARM instructions: + +.*: +file format .*arm.* + +Disassembly of section .text: +(0[0-9a-f]+) <[^>]+> e51f1008 ldr r1, \[pc, #-8\] ; \1 <[^>]*> +0[0-9a-f]+ <[^>]+> e79f1002 ldr r1, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e7df1002 ldrb r1, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e18f00d2 ldrd r0, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e19f10b2 ldrh r1, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e19f10d2 ldrsb r1, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e19f10f2 ldrsh r1, \[pc, r2\] +(0[0-9a-f]+) <[^>]+> f55ff008 pld \[pc, #-8\] ; \1 <[^>]*> +0[0-9a-f]+ <[^>]+> f7dff001 pld \[pc, r1\] +(0[0-9a-f]+) <[^>]+> f45ff008 pli \[pc, #-8\] ; \1 <[^>]*> +0[0-9a-f]+ <[^>]+> f6dff001 pli \[pc, r1\] +0[0-9a-f]+ <[^>]+> e58f1004 str r1, \[pc, #4\] ; 0+038 <[^>]*> +0[0-9a-f]+ <[^>]+> e78f1002 str r1, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e7cf1002 strb r1, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e18f00f2 strd r0, \[pc, r2\] +0[0-9a-f]+ <[^>]+> e18f10b2 strh r1, \[pc, r2\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/ldst-pc.s b/binutils-2.25/gas/testsuite/gas/arm/ldst-pc.s new file mode 100644 index 00000000..2d96e3b2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/ldst-pc.s @@ -0,0 +1,24 @@ +@ Test file for ARM load/store instructions with pc as the base register + + .text + .syntax unified + .align 2 + ldr r1, [pc, #-8] + ldr r1, [pc, r2] + ldrb r1, [pc, r2] + ldrd r0, r1, [pc, r2] + ldrh r1, [pc, r2] + ldrsb r1, [pc, r2] + ldrsh r1, [pc, r2] + + pld [pc, #-8] + pld [pc, r1] + + pli [pc, #-8] + pli [pc, r1] + + str r1, [pc, #4] + str r1, [pc, r2] + strb r1, [pc, r2] + strd r0, r1, [pc, r2] + strh r1, [pc, r2] diff --git a/binutils-2.25/gas/testsuite/gas/arm/le-fpconst.d b/binutils-2.25/gas/testsuite/gas/arm/le-fpconst.d new file mode 100644 index 00000000..846da89f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/le-fpconst.d @@ -0,0 +1,11 @@ +#objdump: -s --section=.text +#as: -EL +#name: arm little-endian fpconst +# Not all arm targets are bi-endian, so only run this test on ones +# we know that are. FIXME We should probably also key off armeb/armel. +#target: *-*-pe + +.*: +file format .*arm.* + +Contents of section .text: + 0000 cdcc8c3f 00000000 9999f13f 9a999999 .* diff --git a/binutils-2.25/gas/testsuite/gas/arm/le-fpconst.s b/binutils-2.25/gas/testsuite/gas/arm/le-fpconst.s new file mode 100644 index 00000000..8a3c3d70 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/le-fpconst.s @@ -0,0 +1,8 @@ +# Test fp constants. +# These need ARM specific support because 8 byte fp constants in little +# endian mode are represented abnormally. + + .text + .float 1.1 + .float 0 + .double 1.1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_function.d b/binutils-2.25/gas/testsuite/gas/arm/local_function.d new file mode 100644 index 00000000..2532f739 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_function.d @@ -0,0 +1,10 @@ +#objdump: -r +#name: Relocations agains local function symbols +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks + +.*: file format.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000000 R_ARM_(CALL|PC24) bar diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_function.s b/binutils-2.25/gas/testsuite/gas/arm/local_function.s new file mode 100644 index 00000000..1d98a374 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_function.s @@ -0,0 +1,10 @@ + .text + .type foo, %function +foo: + bl bar + + .section .text.bar + nop + .type bar, %function +bar: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_label_coff.d b/binutils-2.25/gas/testsuite/gas/arm/local_label_coff.d new file mode 100644 index 00000000..5e45ac8c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_label_coff.d @@ -0,0 +1,11 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (COFF) +# This test is only valid on COFF based targets, except Windows CE. +# There are ELF and Windows CE versions of this test. +#not-skip: *-unknown-pe *-epoc-pe *-*-*coff + +# Check if relocations against local symbols are converted to +# relocations against section symbols. +0+0 b .bss +0+0 d .data +0+0 t .text diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_label_coff.s b/binutils-2.25/gas/testsuite/gas/arm/local_label_coff.s new file mode 100644 index 00000000..985f568a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_label_coff.s @@ -0,0 +1,3 @@ + .text +Lused_label: + .word Lused_label diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_label_elf.d b/binutils-2.25/gas/testsuite/gas/arm/local_label_elf.d new file mode 100644 index 00000000..d4a8c8ea --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_label_elf.d @@ -0,0 +1,9 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (ELF) +# This test is only valid on ELF targets. +# There are COFF and Windows CE versions of this test. +#skip: *-*-*coff *-*-pe *-wince-* *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# Check if relocations against local symbols are converted to +# relocations against section symbols. + diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_label_elf.s b/binutils-2.25/gas/testsuite/gas/arm/local_label_elf.s new file mode 100644 index 00000000..e9f5467d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_label_elf.s @@ -0,0 +1,3 @@ + .text +.Lused_label: + .word .Lused_label diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_label_wince.d b/binutils-2.25/gas/testsuite/gas/arm/local_label_wince.d new file mode 100644 index 00000000..97fc58ae --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_label_wince.d @@ -0,0 +1,11 @@ +#nm: -n +#name: ARM local label relocs to section symbol relocs (WinCE) +# This test is only valid on Windows CE. +# There are ELF and COFF versions of this test. +#not-skip: *-*-wince *-wince-* + +# Check if relocations against local symbols are converted to +# relocations against section symbols. +0+0 b .bss +0+0 d .data +0+0 t .text diff --git a/binutils-2.25/gas/testsuite/gas/arm/local_label_wince.s b/binutils-2.25/gas/testsuite/gas/arm/local_label_wince.s new file mode 100644 index 00000000..e9f5467d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/local_label_wince.s @@ -0,0 +1,3 @@ + .text +.Lused_label: + .word .Lused_label diff --git a/binutils-2.25/gas/testsuite/gas/arm/macro-pld.d b/binutils-2.25/gas/testsuite/gas/arm/macro-pld.d new file mode 100644 index 00000000..e3a78435 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/macro-pld.d @@ -0,0 +1,9 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +\s*0:\s+f5d0f000\s+pld\s+\[r0\] +\s*4:\s+e52d0004\s+push\s+{r0}\s*.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/macro-pld.s b/binutils-2.25/gas/testsuite/gas/arm/macro-pld.s new file mode 100644 index 00000000..f2a436b8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/macro-pld.s @@ -0,0 +1,5 @@ +.macro foo arg, rest:vararg + \rest +.endm + foo r0, pld [r0] + foo r0, push {r0} diff --git a/binutils-2.25/gas/testsuite/gas/arm/macro-vld1.d b/binutils-2.25/gas/testsuite/gas/arm/macro-vld1.d new file mode 100644 index 00000000..b4f67215 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/macro-vld1.d @@ -0,0 +1,9 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +\s*0:\s+f420070f\s+vld1.8\s+{d0},\s*\[r0\] +\s*4:\s+f420070f\s+vld1.8\s+{d0},\s*\[r0\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/macro-vld1.s b/binutils-2.25/gas/testsuite/gas/arm/macro-vld1.s new file mode 100644 index 00000000..614724b8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/macro-vld1.s @@ -0,0 +1,10 @@ + .fpu neon + .macro sfi_breg basereg, insn, operands:vararg + .macro _sfi_breg_doit B + \insn \operands + .endm + _sfi_breg_doit \basereg + .purgem _sfi_breg_doit + .endm + sfi_breg r0, vld1.8 {d0}, [\B] + sfi_breg r0, vld1.8 { d0 }, [\B] diff --git a/binutils-2.25/gas/testsuite/gas/arm/macro1.d b/binutils-2.25/gas/testsuite/gas/arm/macro1.d new file mode 100644 index 00000000..1e28877f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/macro1.d @@ -0,0 +1,12 @@ +# name: Macro scrubbing +# as: +# objdump: -dr --prefix-addresses --show-raw-insn + +[^:]+: +file format .*arm.* + +Disassembly of section .text: + +0+0 <[^>]*> e8bd8030 ? pop {r4, r5, pc} +0+4 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/macro1.s b/binutils-2.25/gas/testsuite/gas/arm/macro1.s new file mode 100644 index 00000000..e2880e7b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/macro1.s @@ -0,0 +1,12 @@ + @ Test that macro expansions are properly scrubbed. + .macro popret regs + ldmia sp!, {\regs, pc} + .endm + .text +l: + popret "r4, r5" + + @ section padding for a.out's sake + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapdir.d b/binutils-2.25/gas/testsuite/gas/arm/mapdir.d new file mode 100644 index 00000000..a8538440 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapdir.d @@ -0,0 +1,35 @@ +#as: -EL -I$srcdir/$subdir +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .arm/.thumb +# This test is only valid on EABI based ports. +#target: *-*-*eabi* *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl* +#source: mapdir.s + + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l d .fini_array 00000000 .fini_array +0+00 l .fini_array 00000000 \$d +0+00 l O .fini_array 00000000 __do_global_dtors_aux_fini_array_entry +0+00 l d .code 00000000 .code +0+00 l .code 00000000 \$a +0+00 l d .tcode 00000000 .tcode +0+00 l .tcode 00000000 \$t +0+00 l d .ARM.attributes 00000000 .ARM.attributes +0+00 \*UND\* 00000000 __do_global_dtors_aux + + + +Disassembly of section .code: + +00000000 <.code>: + 0: e1a00000 nop ; \(mov r0, r0\) + +Disassembly of section .tcode: + +00000000 <.tcode>: + 0: 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapdir.s b/binutils-2.25/gas/testsuite/gas/arm/mapdir.s new file mode 100644 index 00000000..ff071791 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapdir.s @@ -0,0 +1,23 @@ +# Test that .arm / .thumb do not cause mapping symbols to be +# generated. This could lead to duplicate mapping symbols at +# the same address. + + .section .fini_array + .thumb + .align 2 + .type __do_global_dtors_aux_fini_array_entry, %object +__do_global_dtors_aux_fini_array_entry: + .word __do_global_dtors_aux + + .section .code,"ax",%progbits + .thumb + .arm + nop + +# .bss should not automatically emit $d. + .bss + +# Make sure that mapping symbols are placed in the correct section. + .thumb + .section .tcode,"ax",%progbits + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapmisc.d b/binutils-2.25/gas/testsuite/gas/arm/mapmisc.d new file mode 100644 index 00000000..f5b70390 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapmisc.d @@ -0,0 +1,97 @@ +#as: -EL -I$srcdir/$subdir -mfpu=neon +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for miscellaneous directives +# This test is only valid on EABI based ports. +#target: *-*-*eabi* *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl* +#source: mapmisc.s + + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$d +0+08 l .text 00000000 \$a +0+0c l .text 00000000 \$d +0+10 l .text 00000000 \$a +0+14 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+20 l .text 00000000 \$a +0+24 l .text 00000000 \$d +0+28 l .text 00000000 \$a +0+2c l .text 00000000 \$d +0+34 l .text 00000000 \$a +0+38 l .text 00000000 \$d +0+48 l .text 00000000 \$a +0+4c l .text 00000000 \$d +0+50 l .text 00000000 \$a +0+54 l .text 00000000 \$d +0+58 l .text 00000000 \$a +0+5c l .text 00000000 \$d +0+64 l .text 00000000 \$a +0+68 l .text 00000000 \$d +0+70 l .text 00000000 \$a +0+74 l .text 00000000 \$d +0+84 l .text 00000000 \$a +0+88 l .text 00000000 \$d +0+8c l .text 00000000 \$a +0+90 l .text 00000000 \$d +0+94 l .text 00000000 \$a +0+98 l .text 00000000 \$d +0+9c l .text 00000000 \$a +0+a0 l .text 00000000 \$d +0+a4 l .text 00000000 \$a +0+a8 l .text 00000000 \$a +0+00 l d .ARM.attributes 00000000 .ARM.attributes + + + +Disassembly of section .text: + +00000000 <foo>: + 0: e1a00000 nop ; \(mov r0, r0\) + 4: 64636261 .word 0x64636261 + 8: e1a00000 nop ; \(mov r0, r0\) + c: 00636261 .word 0x00636261 + 10: e1a00000 nop ; \(mov r0, r0\) + 14: 00676665 .word 0x00676665 + 18: e1a00000 nop ; \(mov r0, r0\) + 1c: 006a6968 .word 0x006a6968 + 20: e1a00000 nop ; \(mov r0, r0\) + 24: 0000006b .word 0x0000006b + 28: e1a00000 nop ; \(mov r0, r0\) + 2c: 0000006c .word 0x0000006c + 30: 00000000 .word 0x00000000 + 34: e1a00000 nop ; \(mov r0, r0\) + 38: 0000006d .word 0x0000006d + ... + 48: e1a00000 nop ; \(mov r0, r0\) + 4c: 3fc00000 .word 0x3fc00000 + 50: e1a00000 nop ; \(mov r0, r0\) + 54: 40200000 .word 0x40200000 + 58: e1a00000 nop ; \(mov r0, r0\) + 5c: 00000000 .word 0x00000000 + 60: 400c0000 .word 0x400c0000 + 64: e1a00000 nop ; \(mov r0, r0\) + 68: 00000000 .word 0x00000000 + 6c: 40120000 .word 0x40120000 + 70: e1a00000 nop ; \(mov r0, r0\) + 74: 00000004 .word 0x00000004 + 78: 00000004 .word 0x00000004 + 7c: 00000004 .word 0x00000004 + 80: 00000004 .word 0x00000004 + 84: e1a00000 nop ; \(mov r0, r0\) + 88: 00000000 .word 0x00000000 + 8c: e1a00000 nop ; \(mov r0, r0\) + 90: 00000000 .word 0x00000000 + 94: e1a00000 nop ; \(mov r0, r0\) + 98: 00000000 .word 0x00000000 + 9c: e1a00000 nop ; \(mov r0, r0\) + a0: 7778797a .word 0x7778797a + a4: e1a00000 nop ; \(mov r0, r0\) + a8: e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapmisc.dat b/binutils-2.25/gas/testsuite/gas/arm/mapmisc.dat new file mode 100644 index 00000000..450730be --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapmisc.dat @@ -0,0 +1 @@ +zyxw
\ No newline at end of file diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapmisc.s b/binutils-2.25/gas/testsuite/gas/arm/mapmisc.s new file mode 100644 index 00000000..1625515f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapmisc.s @@ -0,0 +1,40 @@ + .text + .type foo, %function +foo: + .align 2 + .fill 0, 0, 0 + nop + .ascii "abcd" + nop + .asciz "abc" + nop + .string "efg" + nop + .string8 "hij" + nop + .string16 "k" + nop + .string32 "l" + nop + .string64 "m" + nop + .float 0e1.5 + nop + .single 0e2.5 + nop + .double 0e3.5 + nop + .dcb.d 1, 4.5 + nop + .fill 4, 4, 4 + nop + .space 4 + nop + .skip 4 + nop + .zero 4 + nop + .incbin "mapmisc.dat" + nop + .fill 0, 0, 0 + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping.d b/binutils-2.25/gas/testsuite/gas/arm/mapping.d new file mode 100644 index 00000000..c4819d28 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping.d @@ -0,0 +1,21 @@ +#objdump: --syms --special-syms +#name: ARM Mapping Symbols +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# Test the generation of ARM ELF Mapping Symbols + +.*: +file format.*arm.* + +SYMBOL TABLE: +0+00 l d .text 0+0 (|.text) +0+00 l d .data 0+0 (|.data) +0+00 l d .bss 0+0 (|.bss) +0+00 l .text 0+0 \$a +0+08 l .text 0+0 \$t +0+00 l d foo 0+0 (|foo) +0+00 l foo 0+0 \$t +#Maybe section symbol for .ARM.attributes +#... +0+00 g .text 0+0 mapping +0+08 g F .text 0+0 thumb_mapping diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping.s b/binutils-2.25/gas/testsuite/gas/arm/mapping.s new file mode 100644 index 00000000..c9cee8d4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping.s @@ -0,0 +1,19 @@ + .text + .arm + .global mapping +mapping: + nop + bl mapping + + .global thumb_mapping + .thumb_func +thumb_mapping: + .thumb + nop + bl thumb_mapping + + .data + .word 0x123456 + + .section foo,"ax" + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping2.d b/binutils-2.25/gas/testsuite/gas/arm/mapping2.d new file mode 100644 index 00000000..42b300d1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping2.d @@ -0,0 +1,19 @@ +#objdump: --syms --special-syms +#name: ARM Mapping Symbols Test 2 +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format.*arm.* + +SYMBOL TABLE: +00000000 l d .text 00000000 .text +00000000 l d .data 00000000 .data +00000000 l d .bss 00000000 .bss +00000000 l .text 00000000 \$t +00000002 l .text 00000000 foo +00000000 l d .note 00000000 .note +00000000 l d .comment 00000000 .comment +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 g F .text 00000008 main + + diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping2.s b/binutils-2.25/gas/testsuite/gas/arm/mapping2.s new file mode 100644 index 00000000..2629c55e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping2.s @@ -0,0 +1,20 @@ + .syntax unified + .arch armv7-a + .fpu softvfp + .version "dfg" + .thumb + .text + .align 2 + .global main + .thumb + .thumb_func + .type main, %function +main: + push {r4, lr} +foo: + pop {r4, lr} + bx lr + .size main, .-main + .ident "" + + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping3.d b/binutils-2.25/gas/testsuite/gas/arm/mapping3.d new file mode 100644 index 00000000..2c70a724 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping3.d @@ -0,0 +1,16 @@ +#objdump: --syms --special-syms +#name: ARM Mapping Symbols Test 3 +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format.*arm.* + +SYMBOL TABLE: +00000000 l d .text 00000000 .text +00000000 l d .data 00000000 .data +00000000 l d .bss 00000000 .bss +00000000 l .text 00000000 \$d +00000004 l .text 00000000 \$a +00000000 l d .ARM.attributes 00000000 .ARM.attributes + + diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping3.s b/binutils-2.25/gas/testsuite/gas/arm/mapping3.s new file mode 100644 index 00000000..9ee9bb42 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping3.s @@ -0,0 +1,5 @@ + .syntax unified + .arch armv7-a +.text +.word 0 + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping4.d b/binutils-2.25/gas/testsuite/gas/arm/mapping4.d new file mode 100644 index 00000000..2d82a1a0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping4.d @@ -0,0 +1,15 @@ +#objdump: --syms --special-syms +#name: ARM Mapping Symbols Test 4 +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format.*arm.* + +SYMBOL TABLE: +00000000 l d .text 00000000 .text +00000000 l d .data 00000000 .data +00000000 l d .bss 00000000 .bss +00000000 l .text 00000000 \$a +00000000 l d .ARM.attributes 00000000 .ARM.attributes + + diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapping4.s b/binutils-2.25/gas/testsuite/gas/arm/mapping4.s new file mode 100644 index 00000000..8a24a4a9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapping4.s @@ -0,0 +1,7 @@ + .text + nop + .data + .word 0 + .text + nop + diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapsecs.d b/binutils-2.25/gas/testsuite/gas/arm/mapsecs.d new file mode 100644 index 00000000..b2a0e602 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapsecs.d @@ -0,0 +1,45 @@ +#as: -EL +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols with multiple sections +# This test is only valid on EABI based ports. +#target: *-*-*eabi* *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl* +#source: mapsecs.s + + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l d .text.f1 00000000 .text.f1 +0+00 l F .text.f1 00000000 f1 +0+00 l .text.f1 00000000 \$a +0+08 l .text.f1 00000000 f1a +0+00 l d .text.f2 00000000 .text.f2 +0+00 l F .text.f2 00000000 f2 +0+00 l .text.f2 00000000 \$a +0+04 l .text.f2 00000000 \$d +0+08 l .text.f2 00000000 f2a +0+08 l .text.f2 00000000 \$a +0+00 l d .ARM.attributes 00000000 .ARM.attributes + + + +Disassembly of section .text.f1: + +00000000 <f1>: + 0: e1a00000 nop ; \(mov r0, r0\) + 4: e1a00000 nop ; \(mov r0, r0\) + +00000008 <f1a>: + 8: e1a00000 nop ; \(mov r0, r0\) + +Disassembly of section .text.f2: + +00000000 <f2>: + 0: e1a00000 nop ; \(mov r0, r0\) + 4: 00000001 .word 0x00000001 + +00000008 <f2a>: + 8: e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapsecs.s b/binutils-2.25/gas/testsuite/gas/arm/mapsecs.s new file mode 100644 index 00000000..005c339f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapsecs.s @@ -0,0 +1,15 @@ + .text + .section .text.f1,"ax",%progbits + .type f1, %function +f1: + nop + nop +f1a: + nop + .section .text.f2,"ax",%progbits + .type f2, %function +f2: + nop + .word 1 +f2a: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapshort-eabi.d b/binutils-2.25/gas/testsuite/gas/arm/mapshort-eabi.d new file mode 100644 index 00000000..fd6cf91f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapshort-eabi.d @@ -0,0 +1,44 @@ +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .short (EABI version) +# This test is only valid on EABI based ports. +#target: *-*-*eabi* *-*-symbianelf *-*-linux-* *-*-elf *-*-nacl* +#source: mapshort.s + +# Test the generation and use of ARM ELF Mapping Symbols + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$t +0+08 l .text 00000000 \$d +0+12 l .text 00000000 \$t +0+16 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+1f l .text 00000000 bar +0+00 l .data 00000000 wibble +0+00 l d .ARM.attributes 00000000 .ARM.attributes + + +Disassembly of section .text: + +0+00 <foo>: + 0: e1a00000 nop ; \(mov r0, r0\) + 4: 46c0 nop ; \(mov r8, r8\) + 6: 46c0 nop ; \(mov r8, r8\) + 8: 00000002 .word 0x00000002 + c: 00010001 .word 0x00010001 + 10: 0003 .short 0x0003 + 12: 46c0 nop ; \(mov r8, r8\) + 14: 46c0 nop ; \(mov r8, r8\) + 16: 0001 .short 0x0001 + 18: ebfffff8 bl 0 <foo> + 1c: 0008 .short 0x0008 + 1e: 09 .byte 0x09 +0+1f <bar>: + 1f: 0a .byte 0x0a diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapshort-elf.d b/binutils-2.25/gas/testsuite/gas/arm/mapshort-elf.d new file mode 100644 index 00000000..866cdd24 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapshort-elf.d @@ -0,0 +1,44 @@ +#objdump: --syms --special-syms -d +#name: ARM Mapping Symbols for .short (ELF version) +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-*eabi* *-*-syymbianelf *-*-linux-* *-*-vxworks *-*-elf *-*-nacl* +#source: mapshort.s + +# Test the generation and use of ARM ELF Mapping Symbols + +.*: +file format .*arm.* + +SYMBOL TABLE: +0+00 l d .text 00000000 .text +0+00 l d .data 00000000 .data +0+00 l d .bss 00000000 .bss +0+00 l F .text 00000000 foo +0+00 l .text 00000000 \$a +0+04 l .text 00000000 \$t +0+08 l .text 00000000 \$d +0+12 l .text 00000000 \$t +0+16 l .text 00000000 \$d +0+18 l .text 00000000 \$a +0+1c l .text 00000000 \$d +0+1f l .text 00000000 bar +0+00 l .data 00000000 wibble +0+00 l .data 00000000 \$d +# The ELF based port does not generate a .ARM.attributes symbol + +Disassembly of section .text: + +0+00 <foo>: + 0: e1a00000 nop ; \(mov r0, r0\) + 4: 46c0 nop ; \(mov r8, r8\) + 6: 46c0 nop ; \(mov r8, r8\) + 8: 00000002 .word 0x00000002 + c: 00010001 .word 0x00010001 + 10: 0003 .short 0x0003 + 12: 46c0 nop ; \(mov r8, r8\) + 14: 46c0 nop ; \(mov r8, r8\) + 16: 0001 .short 0x0001 + 18: ebfffff8 bl 0 <foo> + 1c: 0008 .short 0x0008 + 1e: 09 .byte 0x09 +0+1f <bar>: + 1f: 0a .byte 0x0a diff --git a/binutils-2.25/gas/testsuite/gas/arm/mapshort.s b/binutils-2.25/gas/testsuite/gas/arm/mapshort.s new file mode 100644 index 00000000..741cb825 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mapshort.s @@ -0,0 +1,24 @@ + .text + .type foo, %function +foo: + .code 32 + nop + .code 16 + nop + nop + .long 2 + .short 1 + .short 1 + .short 3 + nop + nop + .short 1 + .code 32 + bl foo + .short 8 + .byte 9 +bar: + .byte 10 + .data +wibble: + .word 0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/maverick.c b/binutils-2.25/gas/testsuite/gas/arm/maverick.c new file mode 100644 index 00000000..09ad8cbb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/maverick.c @@ -0,0 +1,534 @@ +/* Copyright (C) 2000, 2003, 2004, 2005, 2007 Free Software Foundation + Contributed by Alexandre Oliva <aoliva@cygnus.com> + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* Generator of tests for Maverick. + + See the following file for usage and documentation. */ +#include "../all/test-gen.c" + +/* These are the ARM registers. Some of them have canonical names + other than r##, so we'll use both in the asm input, but only the + canonical names in the expected disassembler output. */ +char *arm_regs[] = + { + /* Canonical names. */ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", + /* Alternate names, i.e., those that can be used in the assembler, + * but that will never be emitted by the disassembler. */ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" + }; + +/* The various types of registers: ARM's registers, Maverick's + f/d/fx/dx registers, Maverick's accumulators and Maverick's + status register. */ +#define armreg(shift) \ + reg_r (arm_regs, shift, 0xf, mk_get_bits (5u)) +#define mvreg(prefix, shift) \ + reg_p ("mv" prefix, shift, mk_get_bits (4u)) +#define acreg(shift) \ + reg_p ("mvax", shift, mk_get_bits (2u)) +#define dspsc \ + literal ("dspsc"), tick_random + +/* This outputs the condition flag that may follow each ARM insn. + Since the condition 15 is invalid, we use it to check that the + assembler recognizes the absence of a condition as `al'. However, + the disassembler won't ever output `al', so, if we emit it in the + assembler, expect the condition to be omitted in the disassembler + output. */ + +int +arm_cond (func_arg * arg, insn_data * data) +#define arm_cond { arm_cond } +{ + static const char conds[16][3] = + { + "eq", "ne", "cs", "cc", + "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", + "gt", "le", "al", "" + }; + unsigned val = get_bits (4u); + + data->as_in = data->dis_out = strdup (conds[val]); + if (val == 14) + data->dis_out = strdup (""); + data->bits = (val == 15 ? 14 : val) << 28; + return 0; +} + +/* The sign of an offset is actually used to determined whether the + absolute value of the offset should be added or subtracted, so we + must adjust negative values so that they do not overflow: -1024 is + not valid, but -0 is distinct from +0. */ +int +off8s (func_arg * arg, insn_data * data) +#define off8s { off8s } +{ + int val; + char value[9]; + + /* Zero values are problematical. + The assembler performs translations on the addressing modes + for these values, meaning that we cannot just recreate the + disassembler string in the LDST macro without knowing what + value had been generated in off8s. */ + do + { + val = get_bits (9s); + } + while (val == -1 || val == 0); + + val <<= 2; + if (val < 0) + { + val = -4 - val; + sprintf (value, ", #-%i", val); + data->dis_out = strdup (value); + sprintf (value, ", #-%i", val); + data->as_in = strdup (value); + data->bits = val >> 2; + } + else + { + sprintf (value, ", #%i", val); + data->as_in = data->dis_out = strdup (value); + data->bits = (val >> 2) | (1 << 23); + } + + return 0; +} + +/* This function generates a 7-bit signed constant, emitted as + follows: the 4 least-significant bits are stored in the 4 + least-significant bits of the word; the 3 most-significant bits are + stored in bits 7:5, i.e., bit 4 is skipped. */ +int +imm7 (func_arg *arg, insn_data *data) +#define imm7 { imm7 } +{ + int val = get_bits (7s); + char value[6]; + + data->bits = (val & 0x0f) | (2 * (val & 0x70)); + sprintf (value, "#%i", val); + data->as_in = data->dis_out = strdup (value); + return 0; +} + +/* Convenience wrapper to define_insn, that prefixes every insn with + `cf' (so, if you specify command-line arguments, remember that `cf' + must *not* be part of the string), and post-fixes a condition code. + insname and insnvar specify the main insn name and a variant; + they're just concatenated, and insnvar is often empty. word is the + bit pattern that defines the insn, properly shifted, and funcs is a + sequence of funcs that define the operands and the syntax of the + insn. */ +#define mv_insn(insname, insnvar, word, funcs...) \ + define_insn (insname ## insnvar, \ + literal ("cf"), \ + insn_bits (insname, word), \ + arm_cond, \ + tab, \ + ## funcs) + +/* Define a single LDC/STC variant. op is the main insn opcode; ld + stands for load (it should be 0 on stores), dword selects 64-bit + operations, pre should be enabled for pre-increment, and wb, for + write-back. sep1, sep2 and sep3 are syntactical elements ([]!) + that the assembler will use to enable pre and wb. It would + probably have been cleaner to couple the syntactical elements with + the pre/wb bits directly, but it would have required the definition + of more functions. */ +#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \ + mv_insn (insname, insnvar, \ + (12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \ + mvreg (regname, 12), comma, \ + lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \ + tick_random) + +/* Define all variants of an LDR or STR instruction, namely, + pre-indexed without write-back, pre-indexed with write-back and + post-indexed. */ +#define LDSTall(insname, op, ld, dword, regname) \ + LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \ + LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \ + LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing) + +/* Produce the insn identifiers of all LDST variants of a given insn. + To be used in the initialization of an insn group array. */ +#define insns_LDSTall(insname) \ + insn (insname ## _p), insn (insname ## _pw), insn (insname) + +/* Define a CDP variant that uses two registers, at offsets 12 and 16. + The two opcodes and the co-processor number identify the CDP + insn. */ +#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \ + mv_insn (insname##var, , \ + (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \ + mvreg (reg1name, 12), comma, mvreg (reg2name, 16)) + +/* Define a 32-bit integer CDP instruction with two operands. */ +#define CDP2fx(insname, opcode1, opcode2) \ + CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx") + +/* Define a 64-bit integer CDP instruction with two operands. */ +#define CDP2dx(insname, opcode1, opcode2) \ + CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx") + +/* Define a float CDP instruction with two operands. */ +#define CDP2f(insname, opcode1, opcode2) \ + CDP2 (insname, s, 4, opcode1, opcode2, "f", "f") + +/* Define a double CDP instruction with two operands. */ +#define CDP2d(insname, opcode1, opcode2) \ + CDP2 (insname, d, 4, opcode1, opcode2, "d", "d") + +/* Define a CDP instruction with two register operands and one 7-bit + signed immediate generated with imm7. */ +#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \ + mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \ + mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \ + tick_random) + +/* Produce the insn identifiers of CDP floating-point or integer insn + pairs (i.e., it appends the suffixes for 32-bit and 64-bit + insns. */ +#define CDPfp_insns(insname) \ + insn (insname ## s), insn (insname ## d) +#define CDPx_insns(insname) \ + insn (insname ## 32), insn (insname ## 64) + +/* Define a CDP instruction with 3 operands, at offsets 12, 16, 0. */ +#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \ + mv_insn (insname##var, , \ + (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \ + mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \ + mvreg (reg3name, 0), tick_random) + +/* Define a 32-bit integer CDP instruction with three operands. */ +#define CDP3fx(insname, opcode1, opcode2) \ + CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx") + +/* Define a 64-bit integer CDP instruction with three operands. */ +#define CDP3dx(insname, opcode1, opcode2) \ + CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx") + +/* Define a float CDP instruction with three operands. */ +#define CDP3f(insname, opcode1, opcode2) \ + CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f") + +/* Define a double CDP instruction with three operands. */ +#define CDP3d(insname, opcode1, opcode2) \ + CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d") + +/* Define a CDP instruction with four operands, at offsets 5, 12, 16 + * and 0. Used only for ACC instructions. */ +#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \ + mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \ + acreg (5), comma, reg2spec, comma, \ + mvreg (reg3name, 16), comma, mvreg (reg4name, 0)) + +/* Define a CDP4 instruction with one accumulator operands. */ +#define CDP41A(insname, opcode1) \ + CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx") + +/* Define a CDP4 instruction with two accumulator operands. */ +#define CDP42A(insname, opcode1) \ + CDP4 (insname, opcode1, acreg (12), "fx", "fx") + +/* Define a MCR or MRC instruction with two register operands. */ +#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \ + mv_insn (insname, , \ + ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \ + ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \ + reg1spec, comma, reg2spec) + +/* Define a move from a DSP register to an ARM register. */ +#define MVDSPARM(insname, cpnum, opcode2, regDSPname) \ + MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \ + mvreg (regDSPname, 16), armreg (12)) + +/* Define a move from an ARM register to a DSP register. */ +#define MVARMDSP(insname, cpnum, opcode2, regDSPname) \ + MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \ + armreg (12), mvreg (regDSPname, 16)) + +/* Move between coprocessor registers. A two operand CDP insn. */ +#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \ + mv_insn (insname, , \ + ((14 << 24) | ((opcode1) << 20) | \ + (4 << 8) | ((opcode2) << 5)), \ + reg1spec, comma, reg2spec) + +/* Define a move from a DSP register to a DSP accumulator. */ +#define MVDSPACC(insname, opcode2, regDSPname) \ + MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16)) + +/* Define a move from a DSP accumulator to a DSP register. */ +#define MVACCDSP(insname, opcode2, regDSPname) \ + MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16)) + +/* Define move insns between a float DSP register and an ARM + register. */ +#define MVf(nameAD, nameDA, opcode2) \ + MVDSPARM (nameAD, 4, opcode2, "f"); \ + MVARMDSP (nameDA, 4, opcode2, "f") + +/* Define move insns between a double DSP register and an ARM + register. */ +#define MVd(nameAD, nameDA, opcode2) \ + MVDSPARM (nameAD, 4, opcode2, "d"); \ + MVARMDSP (nameDA, 4, opcode2, "d") + +/* Define move insns between a 32-bit integer DSP register and an ARM + register. */ +#define MVfx(nameAD, nameDA, opcode2) \ + MVDSPARM (nameAD, 5, opcode2, "fx"); \ + MVARMDSP (nameDA, 5, opcode2, "fx") + +/* Define move insns between a 64-bit integer DSP register and an ARM + register. */ +#define MVdx(nameAD, nameDA, opcode2) \ + MVDSPARM (nameAD, 5, opcode2, "dx"); \ + MVARMDSP (nameDA, 5, opcode2, "dx") + +/* Define move insns between a 32-bit DSP register and a DSP + accumulator. */ +#define MVfxa(nameFA, nameAF, opcode2) \ + MVDSPACC (nameFA, opcode2, "fx"); \ + MVACCDSP (nameAF, opcode2, "fx") + +/* Define move insns between a 64-bit DSP register and a DSP + accumulator. */ +#define MVdxa(nameDA, nameAD, opcode2) \ + MVDSPACC (nameDA, opcode2, "dx"); \ + MVACCDSP (nameAD, opcode2, "dx") + +/* Produce the insn identifiers for a pair of mv insns. */ +#define insns_MV(name1, name2) \ + insn (mv ## name1), insn (mv ## name2) + +/* Define a MCR or MRC instruction with three register operands. */ +#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \ + mv_insn (insname, , \ + ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \ + ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \ + reg1spec, comma, reg2spec, comma, reg3spec, \ + tick_random) + +/* Define all load_store insns. */ +LDSTall (ldrs, 4, 1, 0, "f"); +LDSTall (ldrd, 4, 1, 1, "d"); +LDSTall (ldr32, 5, 1, 0, "fx"); +LDSTall (ldr64, 5, 1, 1, "dx"); +LDSTall (strs, 4, 0, 0, "f"); +LDSTall (strd, 4, 0, 1, "d"); +LDSTall (str32, 5, 0, 0, "fx"); +LDSTall (str64, 5, 0, 1, "dx"); + +/* Create the load_store insn group. */ +func *load_store_insns[] = + { + insns_LDSTall (ldrs), insns_LDSTall (ldrd), + insns_LDSTall (ldr32), insns_LDSTall (ldr64), + insns_LDSTall (strs), insns_LDSTall (strd), + insns_LDSTall (str32), insns_LDSTall (str64), + 0 + }; + +/* Define all move insns. */ +MVf (sr, rs, 2); +MVd (dlr, rdl, 0); +MVd (dhr, rdh, 1); +MVdx (64lr, r64l, 0); +MVdx (64hr, r64h, 1); +MVfxa (al32, 32al, 2); +MVfxa (am32, 32am, 3); +MVfxa (ah32, 32ah, 4); +MVfxa (a32, 32a, 5); +MVdxa (a64, 64a, 6); +MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12)); +MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc); +CDP2 (cpys, , 4, 0, 0, "f", "f"); +CDP2 (cpyd, , 4, 0, 1, "d", "d"); + +/* Create the move insns group. */ +func * move_insns[] = + { + insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh), + insns_MV (64lr, r64l), insns_MV (64hr, r64h), + insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah), + insns_MV (a32, 32a), insns_MV (a64, 64a), + insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd), + 0 + }; + +/* Define all conversion insns. */ +CDP2 (cvtsd, , 4, 0, 3, "d", "f"); +CDP2 (cvtds, , 4, 0, 2, "f", "d"); +CDP2 (cvt32s, , 4, 0, 4, "f", "fx"); +CDP2 (cvt32d, , 4, 0, 5, "d", "fx"); +CDP2 (cvt64s, , 4, 0, 6, "f", "dx"); +CDP2 (cvt64d, , 4, 0, 7, "d", "dx"); +CDP2 (cvts32, , 5, 1, 4, "fx", "f"); +CDP2 (cvtd32, , 5, 1, 5, "fx", "d"); +CDP2 (truncs32, , 5, 1, 6, "fx", "f"); +CDP2 (truncd32, , 5, 1, 7, "fx", "d"); + +/* Create the conv insns group. */ +func * conv_insns[] = + { + insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d), + insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32), + insn (truncs32), insn (truncd32), + 0 + }; + +/* Define all shift insns. */ +MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12)); +MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12)); +CDP2_imm7 (sh32, 5, 0, "fx", "fx"); +CDP2_imm7 (sh64, 5, 2, "dx", "dx"); + +/* Create the shift insns group. */ +func *shift_insns[] = + { + insn (rshl32), insn (rshl64), + insn (sh32), insn (sh64), + 0 + }; + +/* Define all comparison insns. */ +MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0)); +MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0)); +MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0)); +MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0)); + +/* Create the comp insns group. */ +func *comp_insns[] = + { + insn (cmps), insn (cmpd), + insn (cmp32), insn (cmp64), + 0 + }; + +/* Define all floating-point arithmetic insns. */ +CDP2f (abs, 3, 0); +CDP2d (abs, 3, 1); +CDP2f (neg, 3, 2); +CDP2d (neg, 3, 3); +CDP3f (add, 3, 4); +CDP3d (add, 3, 5); +CDP3f (sub, 3, 6); +CDP3d (sub, 3, 7); +CDP3f (mul, 1, 0); +CDP3d (mul, 1, 1); + +/* Create the fp-arith insns group. */ +func *fp_arith_insns[] = + { + CDPfp_insns (abs), CDPfp_insns (neg), + CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul), + 0 + }; + +/* Define all integer arithmetic insns. */ +CDP2fx (abs, 3, 0); +CDP2dx (abs, 3, 1); +CDP2fx (neg, 3, 2); +CDP2dx (neg, 3, 3); +CDP3fx (add, 3, 4); +CDP3dx (add, 3, 5); +CDP3fx (sub, 3, 6); +CDP3dx (sub, 3, 7); +CDP3fx (mul, 1, 0); +CDP3dx (mul, 1, 1); +CDP3fx (mac, 1, 2); +CDP3fx (msc, 1, 3); + +/* Create the int-arith insns group. */ +func * int_arith_insns[] = + { + CDPx_insns (abs), CDPx_insns (neg), + CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul), + insn (mac32), insn (msc32), + 0 + }; + +/* Define all accumulator arithmetic insns. */ +CDP41A (madd32, 0); +CDP41A (msub32, 1); +CDP42A (madda32, 2); +CDP42A (msuba32, 3); + +/* Create the acc-arith insns group. */ +func * acc_arith_insns[] = + { + insn (madd32), insn (msub32), + insn (madda32), insn (msuba32), + 0 + }; + +/* Create the set of all groups. */ +group_t groups[] = + { + { "load_store", load_store_insns }, + { "move", move_insns }, + { "conv", conv_insns }, + { "shift", shift_insns }, + { "comp", comp_insns }, + { "fp_arith", fp_arith_insns }, + { "int_arith", int_arith_insns }, + { "acc_arith", acc_arith_insns }, + { 0 } + }; + +int +main (int argc, char *argv[]) +{ + FILE *as_in = stdout, *dis_out = stderr; + + /* Check whether we're filtering insns. */ + if (argc > 1) + skip_list = argv + 1; + + /* Output assembler header. */ + fputs ("\t.text\n" + "\t.align\n", + as_in); + /* Output comments for the testsuite-driver and the initial + disassembler output. */ + fputs ("#objdump: -dr --prefix-address --show-raw-insn\n" + "#name: Maverick\n" + "#as: -mcpu=ep9312\n" + "\n" + "# Test the instructions of the Cirrus Maverick floating point co-processor\n" + "\n" + ".*: +file format.*arm.*\n" + "\n" + "Disassembly of section .text:\n", + dis_out); + + /* Now emit all (selected) insns. */ + output_groups (groups, as_in, dis_out); + + exit (0); +} diff --git a/binutils-2.25/gas/testsuite/gas/arm/maverick.d b/binutils-2.25/gas/testsuite/gas/arm/maverick.d new file mode 100644 index 00000000..4addfac4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/maverick.d @@ -0,0 +1,477 @@ +#objdump: -dr --prefix-address --show-raw-insn +#name: Maverick +#as: -mcpu=ep9312 + +# Test the instructions of the Cirrus Maverick floating point co-processor + +.*: +file format.*arm.* + +Disassembly of section .text: +# load_store: +0*0 <load_store> 0d ?9d ?54 ?ff ? * cfldrseq mvf5, ?\[sp, #1020\].* +0*4 <load_store\+0x4> 4d ?9b ?e4 ?49 ? * cfldrsmi mvf14, ?\[fp, #292\].* +0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[ip, #-956\].* +0*c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[sl, #-1020\].* +0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, #-156\].* +0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9, #416\]!.* +0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0, #-1020\]!.* +0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1, #-156\]!.* +0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9, #416\]!.* +0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? * cfldrsvs mvf11, ?\[r0, #-1020\]!.* +0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1\], #-156.* +0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9\], #416.* +0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0\], #-1020.* +0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1\], #-156.* +0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9\], #416.* +0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\].* +0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\].* +0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\].* +0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\].* +0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, #-156\].* +0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9, #416\]!.* +0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]!.* +0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]!.* +0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]!.* +0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]!.* +0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1\], #-156.* +0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9\], #416.* +0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0\], #-1020.* +0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1\], #-156.* +0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9\], #416.* +0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\].* +0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\].* +0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\].* +0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\].* +0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, #-156\].* +0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9, #416\]!.* +0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]!.* +0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]!.* +0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]!.* +0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]!.* +0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1\], #-156.* +0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9\], #416.* +0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0\], #-1020.* +0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1\], #-156.* +0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9\], #416.* +0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\].* +0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\].* +0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\].* +0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\].* +0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, #-156\].* +0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9, #416\]!.* +0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]!.* +0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]!.* +0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]!.* +0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]!.* +0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1\], #-156.* +0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9\], #416.* +0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0\], #-1020.* +0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1\], #-156.* +0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9\], #416.* +0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\].* +0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\].* +0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\].* +0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\].* +0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, #-156\].* +0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9, #416\]!.* +0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]!.* +0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]!.* +0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]!.* +0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]!.* +0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1\], #-156.* +0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9\], #416.* +0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0\], #-1020.* +0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1\], #-156.* +0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9\], #416.* +0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\].* +0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\].* +0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\].* +0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\].* +0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, #-156\].* +0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9, #416\]!.* +0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]!.* +0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]!.* +0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]!.* +0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]!.* +0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1\], #-156.* +0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9\], #416.* +0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0\], #-1020.* +0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1\], #-156.* +0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9\], #416.* +0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\].* +0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\].* +0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\].* +0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\].* +0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1, #-156\].* +0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9, #416\]!.* +0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]!.* +0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]!.* +0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]!.* +0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]!.* +0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], #-156.* +0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9\], #416.* +0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0\], #-1020.* +0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1\], #-156.* +0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9\], #416.* +0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\].* +0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\].* +0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\].* +0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\].* +0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1, #-156\].* +0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9, #416\]!.* +0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]!.* +0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]!.* +0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]!.* +0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]!.* +0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], #-156.* +0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9\], #416.* +0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0\], #-1020.* +0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1\], #-156.* +0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9\], #416.* +# move: +0*1e0 <move> 2e ?09 ?04 ?50 ? * cfmvsrcs mvf9, ?r0 +0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? * cfmvsrpl mvf15, ?r7 +0*1e8 <move\+0x8> 9e ?04 ?14 ?50 ? * cfmvsrls mvf4, ?r1 +0*1ec <move\+0xc> 3e ?08 ?24 ?50 ? * cfmvsrcc mvf8, ?r2 +0*1f0 <move\+0x10> 7e ?02 ?c4 ?50 ? * cfmvsrvc mvf2, ?ip +0*1f4 <move\+0x14> ce ?1b ?94 ?50 ? * cfmvrsgt r9, ?mvf11 +0*1f8 <move\+0x18> 0e ?15 ?a4 ?50 ? * cfmvrseq sl, ?mvf5 +0*1fc <move\+0x1c> ee ?1c ?44 ?50 ? * cfmvrs r4, ?mvf12 +0*200 <move\+0x20> ae ?18 ?b4 ?50 ? * cfmvrsge fp, ?mvf8 +0*204 <move\+0x24> ee ?16 ?54 ?50 ? * cfmvrs r5, ?mvf6 +0*208 <move\+0x28> be ?04 ?94 ?10 ? * cfmvdlrlt mvd4, ?r9 +0*20c <move\+0x2c> 9e ?00 ?a4 ?10 ? * cfmvdlrls mvd0, ?sl +0*210 <move\+0x30> ee ?0a ?44 ?10 ? * cfmvdlr mvd10, ?r4 +0*214 <move\+0x34> 4e ?0e ?b4 ?10 ? * cfmvdlrmi mvd14, ?fp +0*218 <move\+0x38> 8e ?0d ?54 ?10 ? * cfmvdlrhi mvd13, ?r5 +0*21c <move\+0x3c> 2e ?1c ?c4 ?10 ? * cfmvrdlcs ip, ?mvd12 +0*220 <move\+0x40> 6e ?10 ?34 ?10 ? * cfmvrdlvs r3, ?mvd0 +0*224 <move\+0x44> 7e ?1e ?d4 ?10 ? * cfmvrdlvc sp, ?mvd14 +0*228 <move\+0x48> 3e ?1a ?e4 ?10 ? * cfmvrdlcc lr, ?mvd10 +0*22c <move\+0x4c> 1e ?1f ?84 ?10 ? * cfmvrdlne r8, ?mvd15 +0*230 <move\+0x50> de ?06 ?c4 ?30 ? * cfmvdhrle mvd6, ?ip +0*234 <move\+0x54> 4e ?02 ?34 ?30 ? * cfmvdhrmi mvd2, ?r3 +0*238 <move\+0x58> 0e ?05 ?d4 ?30 ? * cfmvdhreq mvd5, ?sp +0*23c <move\+0x5c> ae ?09 ?e4 ?30 ? * cfmvdhrge mvd9, ?lr +0*240 <move\+0x60> ee ?03 ?84 ?30 ? * cfmvdhr mvd3, ?r8 +0*244 <move\+0x64> de ?12 ?54 ?30 ? * cfmvrdhle r5, ?mvd2 +0*248 <move\+0x68> 1e ?16 ?64 ?30 ? * cfmvrdhne r6, ?mvd6 +0*24c <move\+0x6c> be ?17 ?04 ?30 ? * cfmvrdhlt r0, ?mvd7 +0*250 <move\+0x70> 5e ?13 ?74 ?30 ? * cfmvrdhpl r7, ?mvd3 +0*254 <move\+0x74> ce ?11 ?14 ?30 ? * cfmvrdhgt r1, ?mvd1 +0*258 <move\+0x78> 8e ?0f ?55 ?10 ? * cfmv64lrhi mvdx15, ?r5 +0*25c <move\+0x7c> 6e ?0b ?65 ?10 ? * cfmv64lrvs mvdx11, ?r6 +0*260 <move\+0x80> 2e ?09 ?05 ?10 ? * cfmv64lrcs mvdx9, ?r0 +0*264 <move\+0x84> 5e ?0f ?75 ?10 ? * cfmv64lrpl mvdx15, ?r7 +0*268 <move\+0x88> 9e ?04 ?15 ?10 ? * cfmv64lrls mvdx4, ?r1 +0*26c <move\+0x8c> 3e ?1d ?85 ?10 ? * cfmvr64lcc r8, ?mvdx13 +0*270 <move\+0x90> 7e ?11 ?f5 ?10 ? * cfmvr64lvc pc, ?mvdx1 +0*274 <move\+0x94> ce ?1b ?95 ?10 ? * cfmvr64lgt r9, ?mvdx11 +0*278 <move\+0x98> 0e ?15 ?a5 ?10 ? * cfmvr64leq sl, ?mvdx5 +0*27c <move\+0x9c> ee ?1c ?45 ?10 ? * cfmvr64l r4, ?mvdx12 +0*280 <move\+0xa0> ae ?01 ?85 ?30 ? * cfmv64hrge mvdx1, ?r8 +0*284 <move\+0xa4> ee ?0d ?f5 ?30 ? * cfmv64hr mvdx13, ?pc +0*288 <move\+0xa8> be ?04 ?95 ?30 ? * cfmv64hrlt mvdx4, ?r9 +0*28c <move\+0xac> 9e ?00 ?a5 ?30 ? * cfmv64hrls mvdx0, ?sl +0*290 <move\+0xb0> ee ?0a ?45 ?30 ? * cfmv64hr mvdx10, ?r4 +0*294 <move\+0xb4> 4e ?13 ?15 ?30 ? * cfmvr64hmi r1, ?mvdx3 +0*298 <move\+0xb8> 8e ?17 ?25 ?30 ? * cfmvr64hhi r2, ?mvdx7 +0*29c <move\+0xbc> 2e ?1c ?c5 ?30 ? * cfmvr64hcs ip, ?mvdx12 +0*2a0 <move\+0xc0> 6e ?10 ?35 ?30 ? * cfmvr64hvs r3, ?mvdx0 +0*2a4 <move\+0xc4> 7e ?1e ?d5 ?30 ? * cfmvr64hvc sp, ?mvdx14 +0*2a8 <move\+0xc8> 3e ?2a ?04 ?40 ? * cfmval32cc mvax0, ?mvfx10 +0*2ac <move\+0xcc> 1e ?2f ?14 ?40 ? * cfmval32ne mvax1, ?mvfx15 +0*2b0 <move\+0xd0> de ?2b ?04 ?40 ? * cfmval32le mvax0, ?mvfx11 +0*2b4 <move\+0xd4> 4e ?29 ?04 ?40 ? * cfmval32mi mvax0, ?mvfx9 +0*2b8 <move\+0xd8> 0e ?2f ?14 ?40 ? * cfmval32eq mvax1, ?mvfx15 +0*2bc <move\+0xdc> ae ?10 ?94 ?40 ? * cfmv32alge mvfx9, ?mvax0 +0*2c0 <move\+0xe0> ee ?11 ?34 ?40 ? * cfmv32al mvfx3, ?mvax1 +0*2c4 <move\+0xe4> de ?10 ?74 ?40 ? * cfmv32alle mvfx7, ?mvax0 +0*2c8 <move\+0xe8> 1e ?10 ?c4 ?40 ? * cfmv32alne mvfx12, ?mvax0 +0*2cc <move\+0xec> be ?11 ?04 ?40 ? * cfmv32allt mvfx0, ?mvax1 +0*2d0 <move\+0xf0> 5e ?23 ?24 ?60 ? * cfmvam32pl mvax2, ?mvfx3 +0*2d4 <move\+0xf4> ce ?21 ?14 ?60 ? * cfmvam32gt mvax1, ?mvfx1 +0*2d8 <move\+0xf8> 8e ?2d ?34 ?60 ? * cfmvam32hi mvax3, ?mvfx13 +0*2dc <move\+0xfc> 6e ?24 ?34 ?60 ? * cfmvam32vs mvax3, ?mvfx4 +0*2e0 <move\+0x100> 2e ?20 ?14 ?60 ? * cfmvam32cs mvax1, ?mvfx0 +0*2e4 <move\+0x104> 5e ?12 ?f4 ?60 ? * cfmv32ampl mvfx15, ?mvax2 +0*2e8 <move\+0x108> 9e ?11 ?44 ?60 ? * cfmv32amls mvfx4, ?mvax1 +0*2ec <move\+0x10c> 3e ?13 ?84 ?60 ? * cfmv32amcc mvfx8, ?mvax3 +0*2f0 <move\+0x110> 7e ?13 ?24 ?60 ? * cfmv32amvc mvfx2, ?mvax3 +0*2f4 <move\+0x114> ce ?11 ?64 ?60 ? * cfmv32amgt mvfx6, ?mvax1 +0*2f8 <move\+0x118> 0e ?25 ?14 ?80 ? * cfmvah32eq mvax1, ?mvfx5 +0*2fc <move\+0x11c> ee ?2c ?24 ?80 ? * cfmvah32 mvax2, ?mvfx12 +0*300 <move\+0x120> ae ?28 ?34 ?80 ? * cfmvah32ge mvax3, ?mvfx8 +0*304 <move\+0x124> ee ?26 ?24 ?80 ? * cfmvah32 mvax2, ?mvfx6 +0*308 <move\+0x128> be ?22 ?24 ?80 ? * cfmvah32lt mvax2, ?mvfx2 +0*30c <move\+0x12c> 9e ?11 ?04 ?80 ? * cfmv32ahls mvfx0, ?mvax1 +0*310 <move\+0x130> ee ?12 ?a4 ?80 ? * cfmv32ah mvfx10, ?mvax2 +0*314 <move\+0x134> 4e ?13 ?e4 ?80 ? * cfmv32ahmi mvfx14, ?mvax3 +0*318 <move\+0x138> 8e ?12 ?d4 ?80 ? * cfmv32ahhi mvfx13, ?mvax2 +0*31c <move\+0x13c> 2e ?12 ?14 ?80 ? * cfmv32ahcs mvfx1, ?mvax2 +0*320 <move\+0x140> 6e ?20 ?14 ?a0 ? * cfmva32vs mvax1, ?mvfx0 +0*324 <move\+0x144> 7e ?2e ?34 ?a0 ? * cfmva32vc mvax3, ?mvfx14 +0*328 <move\+0x148> 3e ?2a ?04 ?a0 ? * cfmva32cc mvax0, ?mvfx10 +0*32c <move\+0x14c> 1e ?2f ?14 ?a0 ? * cfmva32ne mvax1, ?mvfx15 +0*330 <move\+0x150> de ?2b ?04 ?a0 ? * cfmva32le mvax0, ?mvfx11 +0*334 <move\+0x154> 4e ?11 ?24 ?a0 ? * cfmv32ami mvfx2, ?mvax1 +0*338 <move\+0x158> 0e ?13 ?54 ?a0 ? * cfmv32aeq mvfx5, ?mvax3 +0*33c <move\+0x15c> ae ?10 ?94 ?a0 ? * cfmv32age mvfx9, ?mvax0 +0*340 <move\+0x160> ee ?11 ?34 ?a0 ? * cfmv32a mvfx3, ?mvax1 +0*344 <move\+0x164> de ?10 ?74 ?a0 ? * cfmv32ale mvfx7, ?mvax0 +0*348 <move\+0x168> 1e ?26 ?24 ?c0 ? * cfmva64ne mvax2, ?mvdx6 +0*34c <move\+0x16c> be ?27 ?04 ?c0 ? * cfmva64lt mvax0, ?mvdx7 +0*350 <move\+0x170> 5e ?23 ?24 ?c0 ? * cfmva64pl mvax2, ?mvdx3 +0*354 <move\+0x174> ce ?21 ?14 ?c0 ? * cfmva64gt mvax1, ?mvdx1 +0*358 <move\+0x178> 8e ?2d ?34 ?c0 ? * cfmva64hi mvax3, ?mvdx13 +0*35c <move\+0x17c> 6e ?12 ?b4 ?c0 ? * cfmv64avs mvdx11, ?mvax2 +0*360 <move\+0x180> 2e ?10 ?94 ?c0 ? * cfmv64acs mvdx9, ?mvax0 +0*364 <move\+0x184> 5e ?12 ?f4 ?c0 ? * cfmv64apl mvdx15, ?mvax2 +0*368 <move\+0x188> 9e ?11 ?44 ?c0 ? * cfmv64als mvdx4, ?mvax1 +0*36c <move\+0x18c> 3e ?13 ?84 ?c0 ? * cfmv64acc mvdx8, ?mvax3 +0*370 <move\+0x190> 7e ?20 ?14 ?e0 ? * cfmvsc32vc dspsc, ?mvdx1 +0*374 <move\+0x194> ce ?20 ?b4 ?e0 ? * cfmvsc32gt dspsc, ?mvdx11 +0*378 <move\+0x198> 0e ?20 ?54 ?e0 ? * cfmvsc32eq dspsc, ?mvdx5 +0*37c <move\+0x19c> ee ?20 ?c4 ?e0 ? * cfmvsc32 dspsc, ?mvdx12 +0*380 <move\+0x1a0> ae ?20 ?84 ?e0 ? * cfmvsc32ge dspsc, ?mvdx8 +0*384 <move\+0x1a4> ee ?10 ?d4 ?e0 ? * cfmv32sc mvdx13, ?dspsc +0*388 <move\+0x1a8> be ?10 ?44 ?e0 ? * cfmv32sclt mvdx4, ?dspsc +0*38c <move\+0x1ac> 9e ?10 ?04 ?e0 ? * cfmv32scls mvdx0, ?dspsc +0*390 <move\+0x1b0> ee ?10 ?a4 ?e0 ? * cfmv32sc mvdx10, ?dspsc +0*394 <move\+0x1b4> 4e ?10 ?e4 ?e0 ? * cfmv32scmi mvdx14, ?dspsc +0*398 <move\+0x1b8> 8e ?07 ?d4 ?00 ? * cfcpyshi mvf13, ?mvf7 +0*39c <move\+0x1bc> 2e ?0c ?14 ?00 ? * cfcpyscs mvf1, ?mvf12 +0*3a0 <move\+0x1c0> 6e ?00 ?b4 ?00 ? * cfcpysvs mvf11, ?mvf0 +0*3a4 <move\+0x1c4> 7e ?0e ?54 ?00 ? * cfcpysvc mvf5, ?mvf14 +0*3a8 <move\+0x1c8> 3e ?0a ?c4 ?00 ? * cfcpyscc mvf12, ?mvf10 +0*3ac <move\+0x1cc> 1e ?0f ?84 ?20 ? * cfcpydne mvd8, ?mvd15 +0*3b0 <move\+0x1d0> de ?0b ?64 ?20 ? * cfcpydle mvd6, ?mvd11 +0*3b4 <move\+0x1d4> 4e ?09 ?24 ?20 ? * cfcpydmi mvd2, ?mvd9 +0*3b8 <move\+0x1d8> 0e ?0f ?54 ?20 ? * cfcpydeq mvd5, ?mvd15 +0*3bc <move\+0x1dc> ae ?04 ?94 ?20 ? * cfcpydge mvd9, ?mvd4 +# conv: +0*3c0 <conv> ee ?08 ?34 ?60 ? * cfcvtsd mvd3, ?mvf8 +0*3c4 <conv\+0x4> de ?02 ?74 ?60 ? * cfcvtsdle mvd7, ?mvf2 +0*3c8 <conv\+0x8> 1e ?06 ?c4 ?60 ? * cfcvtsdne mvd12, ?mvf6 +0*3cc <conv\+0xc> be ?07 ?04 ?60 ? * cfcvtsdlt mvd0, ?mvf7 +0*3d0 <conv\+0x10> 5e ?03 ?e4 ?60 ? * cfcvtsdpl mvd14, ?mvf3 +0*3d4 <conv\+0x14> ce ?01 ?a4 ?40 ? * cfcvtdsgt mvf10, ?mvd1 +0*3d8 <conv\+0x18> 8e ?0d ?f4 ?40 ? * cfcvtdshi mvf15, ?mvd13 +0*3dc <conv\+0x1c> 6e ?04 ?b4 ?40 ? * cfcvtdsvs mvf11, ?mvd4 +0*3e0 <conv\+0x20> 2e ?00 ?94 ?40 ? * cfcvtdscs mvf9, ?mvd0 +0*3e4 <conv\+0x24> 5e ?0a ?f4 ?40 ? * cfcvtdspl mvf15, ?mvd10 +0*3e8 <conv\+0x28> 9e ?0e ?44 ?80 ? * cfcvt32sls mvf4, ?mvfx14 +0*3ec <conv\+0x2c> 3e ?0d ?84 ?80 ? * cfcvt32scc mvf8, ?mvfx13 +0*3f0 <conv\+0x30> 7e ?01 ?24 ?80 ? * cfcvt32svc mvf2, ?mvfx1 +0*3f4 <conv\+0x34> ce ?0b ?64 ?80 ? * cfcvt32sgt mvf6, ?mvfx11 +0*3f8 <conv\+0x38> 0e ?05 ?74 ?80 ? * cfcvt32seq mvf7, ?mvfx5 +0*3fc <conv\+0x3c> ee ?0c ?34 ?a0 ? * cfcvt32d mvd3, ?mvfx12 +0*400 <conv\+0x40> ae ?08 ?14 ?a0 ? * cfcvt32dge mvd1, ?mvfx8 +0*404 <conv\+0x44> ee ?06 ?d4 ?a0 ? * cfcvt32d mvd13, ?mvfx6 +0*408 <conv\+0x48> be ?02 ?44 ?a0 ? * cfcvt32dlt mvd4, ?mvfx2 +0*40c <conv\+0x4c> 9e ?05 ?04 ?a0 ? * cfcvt32dls mvd0, ?mvfx5 +0*410 <conv\+0x50> ee ?09 ?a4 ?c0 ? * cfcvt64s mvf10, ?mvdx9 +0*414 <conv\+0x54> 4e ?03 ?e4 ?c0 ? * cfcvt64smi mvf14, ?mvdx3 +0*418 <conv\+0x58> 8e ?07 ?d4 ?c0 ? * cfcvt64shi mvf13, ?mvdx7 +0*41c <conv\+0x5c> 2e ?0c ?14 ?c0 ? * cfcvt64scs mvf1, ?mvdx12 +0*420 <conv\+0x60> 6e ?00 ?b4 ?c0 ? * cfcvt64svs mvf11, ?mvdx0 +0*424 <conv\+0x64> 7e ?0e ?54 ?e0 ? * cfcvt64dvc mvd5, ?mvdx14 +0*428 <conv\+0x68> 3e ?0a ?c4 ?e0 ? * cfcvt64dcc mvd12, ?mvdx10 +0*42c <conv\+0x6c> 1e ?0f ?84 ?e0 ? * cfcvt64dne mvd8, ?mvdx15 +0*430 <conv\+0x70> de ?0b ?64 ?e0 ? * cfcvt64dle mvd6, ?mvdx11 +0*434 <conv\+0x74> 4e ?09 ?24 ?e0 ? * cfcvt64dmi mvd2, ?mvdx9 +0*438 <conv\+0x78> 0e ?1f ?55 ?80 ? * cfcvts32eq mvfx5, ?mvf15 +0*43c <conv\+0x7c> ae ?14 ?95 ?80 ? * cfcvts32ge mvfx9, ?mvf4 +0*440 <conv\+0x80> ee ?18 ?35 ?80 ? * cfcvts32 mvfx3, ?mvf8 +0*444 <conv\+0x84> de ?12 ?75 ?80 ? * cfcvts32le mvfx7, ?mvf2 +0*448 <conv\+0x88> 1e ?16 ?c5 ?80 ? * cfcvts32ne mvfx12, ?mvf6 +0*44c <conv\+0x8c> be ?17 ?05 ?a0 ? * cfcvtd32lt mvfx0, ?mvd7 +0*450 <conv\+0x90> 5e ?13 ?e5 ?a0 ? * cfcvtd32pl mvfx14, ?mvd3 +0*454 <conv\+0x94> ce ?11 ?a5 ?a0 ? * cfcvtd32gt mvfx10, ?mvd1 +0*458 <conv\+0x98> 8e ?1d ?f5 ?a0 ? * cfcvtd32hi mvfx15, ?mvd13 +0*45c <conv\+0x9c> 6e ?14 ?b5 ?a0 ? * cfcvtd32vs mvfx11, ?mvd4 +0*460 <conv\+0xa0> 2e ?10 ?95 ?c0 ? * cftruncs32cs mvfx9, ?mvf0 +0*464 <conv\+0xa4> 5e ?1a ?f5 ?c0 ? * cftruncs32pl mvfx15, ?mvf10 +0*468 <conv\+0xa8> 9e ?1e ?45 ?c0 ? * cftruncs32ls mvfx4, ?mvf14 +0*46c <conv\+0xac> 3e ?1d ?85 ?c0 ? * cftruncs32cc mvfx8, ?mvf13 +0*470 <conv\+0xb0> 7e ?11 ?25 ?c0 ? * cftruncs32vc mvfx2, ?mvf1 +0*474 <conv\+0xb4> ce ?1b ?65 ?e0 ? * cftruncd32gt mvfx6, ?mvd11 +0*478 <conv\+0xb8> 0e ?15 ?75 ?e0 ? * cftruncd32eq mvfx7, ?mvd5 +0*47c <conv\+0xbc> ee ?1c ?35 ?e0 ? * cftruncd32 mvfx3, ?mvd12 +0*480 <conv\+0xc0> ae ?18 ?15 ?e0 ? * cftruncd32ge mvfx1, ?mvd8 +0*484 <conv\+0xc4> ee ?16 ?d5 ?e0 ? * cftruncd32 mvfx13, ?mvd6 +# shift: +0*488 <shift> be ?04 ?35 ?52 ? * cfrshl32lt mvfx4, ?mvfx2, ?r3 +0*48c <shift\+0x4> 5e ?0f ?45 ?5a ? * cfrshl32pl mvfx15, ?mvfx10, ?r4 +0*490 <shift\+0x8> ee ?03 ?25 ?58 ? * cfrshl32 mvfx3, ?mvfx8, ?r2 +0*494 <shift\+0xc> 2e ?01 ?95 ?5c ? * cfrshl32cs mvfx1, ?mvfx12, ?r9 +0*498 <shift\+0x10> 0e ?07 ?75 ?55 ? * cfrshl32eq mvfx7, ?mvfx5, ?r7 +0*49c <shift\+0x14> ce ?0a ?85 ?71 ? * cfrshl64gt mvdx10, ?mvdx1, ?r8 +0*4a0 <shift\+0x18> de ?06 ?65 ?7b ? * cfrshl64le mvdx6, ?mvdx11, ?r6 +0*4a4 <shift\+0x1c> 9e ?00 ?d5 ?75 ? * cfrshl64ls mvdx0, ?mvdx5, ?sp +0*4a8 <shift\+0x20> 9e ?04 ?b5 ?7e ? * cfrshl64ls mvdx4, ?mvdx14, ?fp +0*4ac <shift\+0x24> de ?07 ?c5 ?72 ? * cfrshl64le mvdx7, ?mvdx2, ?ip +0*4b0 <shift\+0x28> 6e ?00 ?b5 ?ef ? * cfsh32vs mvfx11, ?mvfx0, ?#-1 +0*4b4 <shift\+0x2c> ee ?0c ?35 ?28 ? * cfsh32 mvfx3, ?mvfx12, ?#24 +0*4b8 <shift\+0x30> 8e ?0d ?f5 ?41 ? * cfsh32hi mvfx15, ?mvfx13, ?#33.* +0*4bc <shift\+0x34> 4e ?09 ?25 ?00 ? * cfsh32mi mvfx2, ?mvfx9, ?#0 +0*4c0 <shift\+0x38> ee ?09 ?a5 ?40 ? * cfsh32 mvfx10, ?mvfx9, ?#32 +0*4c4 <shift\+0x3c> 3e ?2d ?85 ?c1 ? * cfsh64cc mvdx8, ?mvdx13, ?#-31.* +0*4c8 <shift\+0x40> 1e ?26 ?c5 ?01 ? * cfsh64ne mvdx12, ?mvdx6, ?#1 +0*4cc <shift\+0x44> 7e ?2e ?55 ?c0 ? * cfsh64vc mvdx5, ?mvdx14, ?#-32.* +0*4d0 <shift\+0x48> ae ?28 ?15 ?c5 ? * cfsh64ge mvdx1, ?mvdx8, ?#-27.* +0*4d4 <shift\+0x4c> 6e ?24 ?b5 ?eb ? * cfsh64vs mvdx11, ?mvdx4, ?#-5 +# comp: +0*4d8 <comp> 0e ?1f ?a4 ?9a ? * cfcmpseq sl, ?mvf15, ?mvf10 +0*4dc <comp\+0x4> 4e ?13 ?14 ?98 ? * cfcmpsmi r1, ?mvf3, ?mvf8 +0*4e0 <comp\+0x8> 7e ?11 ?f4 ?9c ? * cfcmpsvc pc, ?mvf1, ?mvf12 +0*4e4 <comp\+0xc> be ?17 ?04 ?95 ? * cfcmpslt r0, ?mvf7, ?mvf5 +0*4e8 <comp\+0x10> 3e ?1a ?e4 ?91 ? * cfcmpscc lr, ?mvf10, ?mvf1 +0*4ec <comp\+0x14> ee ?16 ?54 ?bb ? * cfcmpd r5, ?mvd6, ?mvd11 +0*4f0 <comp\+0x18> 2e ?10 ?34 ?b5 ? * cfcmpdcs r3, ?mvd0, ?mvd5 +0*4f4 <comp\+0x1c> ae ?14 ?44 ?be ? * cfcmpdge r4, ?mvd4, ?mvd14 +0*4f8 <comp\+0x20> 8e ?17 ?24 ?b2 ? * cfcmpdhi r2, ?mvd7, ?mvd2 +0*4fc <comp\+0x24> ce ?1b ?94 ?b0 ? * cfcmpdgt r9, ?mvd11, ?mvd0 +0*500 <comp\+0x28> 5e ?13 ?75 ?9c ? * cfcmp32pl r7, ?mvfx3, ?mvfx12 +0*504 <comp\+0x2c> 1e ?1f ?85 ?9d ? * cfcmp32ne r8, ?mvfx15, ?mvfx13 +0*508 <comp\+0x30> be ?12 ?65 ?99 ? * cfcmp32lt r6, ?mvfx2, ?mvfx9 +0*50c <comp\+0x34> 5e ?1a ?d5 ?99 ? * cfcmp32pl sp, ?mvfx10, ?mvfx9 +0*510 <comp\+0x38> ee ?18 ?b5 ?9d ? * cfcmp32 fp, ?mvfx8, ?mvfx13 +0*514 <comp\+0x3c> 2e ?1c ?c5 ?b6 ? * cfcmp64cs ip, ?mvdx12, ?mvdx6 +0*518 <comp\+0x40> 0e ?15 ?a5 ?be ? * cfcmp64eq sl, ?mvdx5, ?mvdx14 +0*51c <comp\+0x44> ce ?11 ?15 ?b8 ? * cfcmp64gt r1, ?mvdx1, ?mvdx8 +0*520 <comp\+0x48> de ?1b ?f5 ?b4 ? * cfcmp64le pc, ?mvdx11, ?mvdx4 +0*524 <comp\+0x4c> 9e ?15 ?05 ?bf ? * cfcmp64ls r0, ?mvdx5, ?mvdx15 +# fp_arith: +0*528 <fp_arith> 9e ?3e ?44 ?00 ? * cfabssls mvf4, ?mvf14 +0*52c <fp_arith\+0x4> 3e ?3d ?84 ?00 ? * cfabsscc mvf8, ?mvf13 +0*530 <fp_arith\+0x8> 7e ?31 ?24 ?00 ? * cfabssvc mvf2, ?mvf1 +0*534 <fp_arith\+0xc> ce ?3b ?64 ?00 ? * cfabssgt mvf6, ?mvf11 +0*538 <fp_arith\+0x10> 0e ?35 ?74 ?00 ? * cfabsseq mvf7, ?mvf5 +0*53c <fp_arith\+0x14> ee ?3c ?34 ?20 ? * cfabsd mvd3, ?mvd12 +0*540 <fp_arith\+0x18> ae ?38 ?14 ?20 ? * cfabsdge mvd1, ?mvd8 +0*544 <fp_arith\+0x1c> ee ?36 ?d4 ?20 ? * cfabsd mvd13, ?mvd6 +0*548 <fp_arith\+0x20> be ?32 ?44 ?20 ? * cfabsdlt mvd4, ?mvd2 +0*54c <fp_arith\+0x24> 9e ?35 ?04 ?20 ? * cfabsdls mvd0, ?mvd5 +0*550 <fp_arith\+0x28> ee ?39 ?a4 ?40 ? * cfnegs mvf10, ?mvf9 +0*554 <fp_arith\+0x2c> 4e ?33 ?e4 ?40 ? * cfnegsmi mvf14, ?mvf3 +0*558 <fp_arith\+0x30> 8e ?37 ?d4 ?40 ? * cfnegshi mvf13, ?mvf7 +0*55c <fp_arith\+0x34> 2e ?3c ?14 ?40 ? * cfnegscs mvf1, ?mvf12 +0*560 <fp_arith\+0x38> 6e ?30 ?b4 ?40 ? * cfnegsvs mvf11, ?mvf0 +0*564 <fp_arith\+0x3c> 7e ?3e ?54 ?60 ? * cfnegdvc mvd5, ?mvd14 +0*568 <fp_arith\+0x40> 3e ?3a ?c4 ?60 ? * cfnegdcc mvd12, ?mvd10 +0*56c <fp_arith\+0x44> 1e ?3f ?84 ?60 ? * cfnegdne mvd8, ?mvd15 +0*570 <fp_arith\+0x48> de ?3b ?64 ?60 ? * cfnegdle mvd6, ?mvd11 +0*574 <fp_arith\+0x4c> 4e ?39 ?24 ?60 ? * cfnegdmi mvd2, ?mvd9 +0*578 <fp_arith\+0x50> 0e ?3f ?54 ?8a ? * cfaddseq mvf5, ?mvf15, ?mvf10 +0*57c <fp_arith\+0x54> 4e ?33 ?e4 ?88 ? * cfaddsmi mvf14, ?mvf3, ?mvf8 +0*580 <fp_arith\+0x58> 7e ?31 ?24 ?8c ? * cfaddsvc mvf2, ?mvf1, ?mvf12 +0*584 <fp_arith\+0x5c> be ?37 ?04 ?85 ? * cfaddslt mvf0, ?mvf7, ?mvf5 +0*588 <fp_arith\+0x60> 3e ?3a ?c4 ?81 ? * cfaddscc mvf12, ?mvf10, ?mvf1 +0*58c <fp_arith\+0x64> ee ?36 ?d4 ?ab ? * cfaddd mvd13, ?mvd6, ?mvd11 +0*590 <fp_arith\+0x68> 2e ?30 ?94 ?a5 ? * cfadddcs mvd9, ?mvd0, ?mvd5 +0*594 <fp_arith\+0x6c> ae ?34 ?94 ?ae ? * cfadddge mvd9, ?mvd4, ?mvd14 +0*598 <fp_arith\+0x70> 8e ?37 ?d4 ?a2 ? * cfadddhi mvd13, ?mvd7, ?mvd2 +0*59c <fp_arith\+0x74> ce ?3b ?64 ?a0 ? * cfadddgt mvd6, ?mvd11, ?mvd0 +0*5a0 <fp_arith\+0x78> 5e ?33 ?e4 ?cc ? * cfsubspl mvf14, ?mvf3, ?mvf12 +0*5a4 <fp_arith\+0x7c> 1e ?3f ?84 ?cd ? * cfsubsne mvf8, ?mvf15, ?mvf13 +0*5a8 <fp_arith\+0x80> be ?32 ?44 ?c9 ? * cfsubslt mvf4, ?mvf2, ?mvf9 +0*5ac <fp_arith\+0x84> 5e ?3a ?f4 ?c9 ? * cfsubspl mvf15, ?mvf10, ?mvf9 +0*5b0 <fp_arith\+0x88> ee ?38 ?34 ?cd ? * cfsubs mvf3, ?mvf8, ?mvf13 +0*5b4 <fp_arith\+0x8c> 2e ?3c ?14 ?e6 ? * cfsubdcs mvd1, ?mvd12, ?mvd6 +0*5b8 <fp_arith\+0x90> 0e ?35 ?74 ?ee ? * cfsubdeq mvd7, ?mvd5, ?mvd14 +0*5bc <fp_arith\+0x94> ce ?31 ?a4 ?e8 ? * cfsubdgt mvd10, ?mvd1, ?mvd8 +0*5c0 <fp_arith\+0x98> de ?3b ?64 ?e4 ? * cfsubdle mvd6, ?mvd11, ?mvd4 +0*5c4 <fp_arith\+0x9c> 9e ?35 ?04 ?ef ? * cfsubdls mvd0, ?mvd5, ?mvd15 +0*5c8 <fp_arith\+0xa0> 9e ?1e ?44 ?03 ? * cfmulsls mvf4, ?mvf14, ?mvf3 +0*5cc <fp_arith\+0xa4> de ?12 ?74 ?01 ? * cfmulsle mvf7, ?mvf2, ?mvf1 +0*5d0 <fp_arith\+0xa8> 6e ?10 ?b4 ?07 ? * cfmulsvs mvf11, ?mvf0, ?mvf7 +0*5d4 <fp_arith\+0xac> ee ?1c ?34 ?0a ? * cfmuls mvf3, ?mvf12, ?mvf10 +0*5d8 <fp_arith\+0xb0> 8e ?1d ?f4 ?06 ? * cfmulshi mvf15, ?mvf13, ?mvf6 +0*5dc <fp_arith\+0xb4> 4e ?19 ?24 ?20 ? * cfmuldmi mvd2, ?mvd9, ?mvd0 +0*5e0 <fp_arith\+0xb8> ee ?19 ?a4 ?24 ? * cfmuld mvd10, ?mvd9, ?mvd4 +0*5e4 <fp_arith\+0xbc> 3e ?1d ?84 ?27 ? * cfmuldcc mvd8, ?mvd13, ?mvd7 +0*5e8 <fp_arith\+0xc0> 1e ?16 ?c4 ?2b ? * cfmuldne mvd12, ?mvd6, ?mvd11 +0*5ec <fp_arith\+0xc4> 7e ?1e ?54 ?23 ? * cfmuldvc mvd5, ?mvd14, ?mvd3 +# int_arith: +0*5f0 <int_arith> ae ?38 ?15 ?00 ? * cfabs32ge mvfx1, ?mvfx8 +0*5f4 <int_arith\+0x4> ee ?36 ?d5 ?00 ? * cfabs32 mvfx13, ?mvfx6 +0*5f8 <int_arith\+0x8> be ?32 ?45 ?00 ? * cfabs32lt mvfx4, ?mvfx2 +0*5fc <int_arith\+0xc> 9e ?35 ?05 ?00 ? * cfabs32ls mvfx0, ?mvfx5 +0*600 <int_arith\+0x10> ee ?39 ?a5 ?00 ? * cfabs32 mvfx10, ?mvfx9 +0*604 <int_arith\+0x14> 4e ?33 ?e5 ?20 ? * cfabs64mi mvdx14, ?mvdx3 +0*608 <int_arith\+0x18> 8e ?37 ?d5 ?20 ? * cfabs64hi mvdx13, ?mvdx7 +0*60c <int_arith\+0x1c> 2e ?3c ?15 ?20 ? * cfabs64cs mvdx1, ?mvdx12 +0*610 <int_arith\+0x20> 6e ?30 ?b5 ?20 ? * cfabs64vs mvdx11, ?mvdx0 +0*614 <int_arith\+0x24> 7e ?3e ?55 ?20 ? * cfabs64vc mvdx5, ?mvdx14 +0*618 <int_arith\+0x28> 3e ?3a ?c5 ?40 ? * cfneg32cc mvfx12, ?mvfx10 +0*61c <int_arith\+0x2c> 1e ?3f ?85 ?40 ? * cfneg32ne mvfx8, ?mvfx15 +0*620 <int_arith\+0x30> de ?3b ?65 ?40 ? * cfneg32le mvfx6, ?mvfx11 +0*624 <int_arith\+0x34> 4e ?39 ?25 ?40 ? * cfneg32mi mvfx2, ?mvfx9 +0*628 <int_arith\+0x38> 0e ?3f ?55 ?40 ? * cfneg32eq mvfx5, ?mvfx15 +0*62c <int_arith\+0x3c> ae ?34 ?95 ?60 ? * cfneg64ge mvdx9, ?mvdx4 +0*630 <int_arith\+0x40> ee ?38 ?35 ?60 ? * cfneg64 mvdx3, ?mvdx8 +0*634 <int_arith\+0x44> de ?32 ?75 ?60 ? * cfneg64le mvdx7, ?mvdx2 +0*638 <int_arith\+0x48> 1e ?36 ?c5 ?60 ? * cfneg64ne mvdx12, ?mvdx6 +0*63c <int_arith\+0x4c> be ?37 ?05 ?60 ? * cfneg64lt mvdx0, ?mvdx7 +0*640 <int_arith\+0x50> 5e ?33 ?e5 ?8c ? * cfadd32pl mvfx14, ?mvfx3, ?mvfx12 +0*644 <int_arith\+0x54> 1e ?3f ?85 ?8d ? * cfadd32ne mvfx8, ?mvfx15, ?mvfx13 +0*648 <int_arith\+0x58> be ?32 ?45 ?89 ? * cfadd32lt mvfx4, ?mvfx2, ?mvfx9 +0*64c <int_arith\+0x5c> 5e ?3a ?f5 ?89 ? * cfadd32pl mvfx15, ?mvfx10, ?mvfx9 +0*650 <int_arith\+0x60> ee ?38 ?35 ?8d ? * cfadd32 mvfx3, ?mvfx8, ?mvfx13 +0*654 <int_arith\+0x64> 2e ?3c ?15 ?a6 ? * cfadd64cs mvdx1, ?mvdx12, ?mvdx6 +0*658 <int_arith\+0x68> 0e ?35 ?75 ?ae ? * cfadd64eq mvdx7, ?mvdx5, ?mvdx14 +0*65c <int_arith\+0x6c> ce ?31 ?a5 ?a8 ? * cfadd64gt mvdx10, ?mvdx1, ?mvdx8 +0*660 <int_arith\+0x70> de ?3b ?65 ?a4 ? * cfadd64le mvdx6, ?mvdx11, ?mvdx4 +0*664 <int_arith\+0x74> 9e ?35 ?05 ?af ? * cfadd64ls mvdx0, ?mvdx5, ?mvdx15 +0*668 <int_arith\+0x78> 9e ?3e ?45 ?c3 ? * cfsub32ls mvfx4, ?mvfx14, ?mvfx3 +0*66c <int_arith\+0x7c> de ?32 ?75 ?c1 ? * cfsub32le mvfx7, ?mvfx2, ?mvfx1 +0*670 <int_arith\+0x80> 6e ?30 ?b5 ?c7 ? * cfsub32vs mvfx11, ?mvfx0, ?mvfx7 +0*674 <int_arith\+0x84> ee ?3c ?35 ?ca ? * cfsub32 mvfx3, ?mvfx12, ?mvfx10 +0*678 <int_arith\+0x88> 8e ?3d ?f5 ?c6 ? * cfsub32hi mvfx15, ?mvfx13, ?mvfx6 +0*67c <int_arith\+0x8c> 4e ?39 ?25 ?e0 ? * cfsub64mi mvdx2, ?mvdx9, ?mvdx0 +0*680 <int_arith\+0x90> ee ?39 ?a5 ?e4 ? * cfsub64 mvdx10, ?mvdx9, ?mvdx4 +0*684 <int_arith\+0x94> 3e ?3d ?85 ?e7 ? * cfsub64cc mvdx8, ?mvdx13, ?mvdx7 +0*688 <int_arith\+0x98> 1e ?36 ?c5 ?eb ? * cfsub64ne mvdx12, ?mvdx6, ?mvdx11 +0*68c <int_arith\+0x9c> 7e ?3e ?55 ?e3 ? * cfsub64vc mvdx5, ?mvdx14, ?mvdx3 +0*690 <int_arith\+0xa0> ae ?18 ?15 ?0f ? * cfmul32ge mvfx1, ?mvfx8, ?mvfx15 +0*694 <int_arith\+0xa4> 6e ?14 ?b5 ?02 ? * cfmul32vs mvfx11, ?mvfx4, ?mvfx2 +0*698 <int_arith\+0xa8> 0e ?1f ?55 ?0a ? * cfmul32eq mvfx5, ?mvfx15, ?mvfx10 +0*69c <int_arith\+0xac> 4e ?13 ?e5 ?08 ? * cfmul32mi mvfx14, ?mvfx3, ?mvfx8 +0*6a0 <int_arith\+0xb0> 7e ?11 ?25 ?0c ? * cfmul32vc mvfx2, ?mvfx1, ?mvfx12 +0*6a4 <int_arith\+0xb4> be ?17 ?05 ?25 ? * cfmul64lt mvdx0, ?mvdx7, ?mvdx5 +0*6a8 <int_arith\+0xb8> 3e ?1a ?c5 ?21 ? * cfmul64cc mvdx12, ?mvdx10, ?mvdx1 +0*6ac <int_arith\+0xbc> ee ?16 ?d5 ?2b ? * cfmul64 mvdx13, ?mvdx6, ?mvdx11 +0*6b0 <int_arith\+0xc0> 2e ?10 ?95 ?25 ? * cfmul64cs mvdx9, ?mvdx0, ?mvdx5 +0*6b4 <int_arith\+0xc4> ae ?14 ?95 ?2e ? * cfmul64ge mvdx9, ?mvdx4, ?mvdx14 +0*6b8 <int_arith\+0xc8> 8e ?17 ?d5 ?42 ? * cfmac32hi mvfx13, ?mvfx7, ?mvfx2 +0*6bc <int_arith\+0xcc> ce ?1b ?65 ?40 ? * cfmac32gt mvfx6, ?mvfx11, ?mvfx0 +0*6c0 <int_arith\+0xd0> 5e ?13 ?e5 ?4c ? * cfmac32pl mvfx14, ?mvfx3, ?mvfx12 +0*6c4 <int_arith\+0xd4> 1e ?1f ?85 ?4d ? * cfmac32ne mvfx8, ?mvfx15, ?mvfx13 +0*6c8 <int_arith\+0xd8> be ?12 ?45 ?49 ? * cfmac32lt mvfx4, ?mvfx2, ?mvfx9 +0*6cc <int_arith\+0xdc> 5e ?1a ?f5 ?69 ? * cfmsc32pl mvfx15, ?mvfx10, ?mvfx9 +0*6d0 <int_arith\+0xe0> ee ?18 ?35 ?6d ? * cfmsc32 mvfx3, ?mvfx8, ?mvfx13 +0*6d4 <int_arith\+0xe4> 2e ?1c ?15 ?66 ? * cfmsc32cs mvfx1, ?mvfx12, ?mvfx6 +0*6d8 <int_arith\+0xe8> 0e ?15 ?75 ?6e ? * cfmsc32eq mvfx7, ?mvfx5, ?mvfx14 +0*6dc <int_arith\+0xec> ce ?11 ?a5 ?68 ? * cfmsc32gt mvfx10, ?mvfx1, ?mvfx8 +# acc_arith: +0*6e0 <acc_arith> de ?04 ?b6 ?02 ? * cfmadd32le mvax0, ?mvfx11, ?mvfx4, ?mvfx2 +0*6e4 <acc_arith\+0x4> 9e ?0f ?56 ?0a ? * cfmadd32ls mvax0, ?mvfx5, ?mvfx15, ?mvfx10 +0*6e8 <acc_arith\+0x8> 9e ?03 ?e6 ?08 ? * cfmadd32ls mvax0, ?mvfx14, ?mvfx3, ?mvfx8 +0*6ec <acc_arith\+0xc> de ?01 ?26 ?4c ? * cfmadd32le mvax2, ?mvfx2, ?mvfx1, ?mvfx12 +0*6f0 <acc_arith\+0x10> 6e ?07 ?06 ?25 ? * cfmadd32vs mvax1, ?mvfx0, ?mvfx7, ?mvfx5 +0*6f4 <acc_arith\+0x14> ee ?1a ?c6 ?41 ? * cfmsub32 mvax2, ?mvfx12, ?mvfx10, ?mvfx1 +0*6f8 <acc_arith\+0x18> 8e ?16 ?d6 ?6b ? * cfmsub32hi mvax3, ?mvfx13, ?mvfx6, ?mvfx11 +0*6fc <acc_arith\+0x1c> 4e ?10 ?96 ?05 ? * cfmsub32mi mvax0, ?mvfx9, ?mvfx0, ?mvfx5 +0*700 <acc_arith\+0x20> ee ?14 ?96 ?4e ? * cfmsub32 mvax2, ?mvfx9, ?mvfx4, ?mvfx14 +0*704 <acc_arith\+0x24> 3e ?17 ?d6 ?22 ? * cfmsub32cc mvax1, ?mvfx13, ?mvfx7, ?mvfx2 +0*708 <acc_arith\+0x28> 1e ?2b ?06 ?40 ? * cfmadda32ne mvax2, ?mvax0, ?mvfx11, ?mvfx0 +0*70c <acc_arith\+0x2c> 7e ?23 ?26 ?6c ? * cfmadda32vc mvax3, ?mvax2, ?mvfx3, ?mvfx12 +0*710 <acc_arith\+0x30> ae ?2f ?16 ?6d ? * cfmadda32ge mvax3, ?mvax1, ?mvfx15, ?mvfx13 +0*714 <acc_arith\+0x34> 6e ?22 ?26 ?69 ? * cfmadda32vs mvax3, ?mvax2, ?mvfx2, ?mvfx9 +0*718 <acc_arith\+0x38> 0e ?2a ?36 ?29 ? * cfmadda32eq mvax1, ?mvax3, ?mvfx10, ?mvfx9 +0*71c <acc_arith\+0x3c> 4e ?38 ?36 ?2d ? * cfmsuba32mi mvax1, ?mvax3, ?mvfx8, ?mvfx13 +0*720 <acc_arith\+0x40> 7e ?3c ?36 ?06 ? * cfmsuba32vc mvax0, ?mvax3, ?mvfx12, ?mvfx6 +0*724 <acc_arith\+0x44> be ?35 ?16 ?0e ? * cfmsuba32lt mvax0, ?mvax1, ?mvfx5, ?mvfx14 +0*728 <acc_arith\+0x48> 3e ?31 ?16 ?08 ? * cfmsuba32cc mvax0, ?mvax1, ?mvfx1, ?mvfx8 +0*72c <acc_arith\+0x4c> ee ?3b ?06 ?44 ? * cfmsuba32 mvax2, ?mvax0, ?mvfx11, ?mvfx4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/maverick.s b/binutils-2.25/gas/testsuite/gas/arm/maverick.s new file mode 100644 index 00000000..e32d36b6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/maverick.s @@ -0,0 +1,470 @@ + .text + .align +load_store: + cfldrseq mvf5, [sp, #1020] + cfldrsmi mvf14, [r11, #292] + cfldrsvc mvf2, [r12, #-956] + cfldrslt mvf0, [sl, #-1020] + cfldrscc mvf12, [r1, #-156] + cfldrs mvf13, [r9, #416]! + cfldrscs mvf9, [r0, #-1020]! + cfldrsls mvf4, [r1, #-156]! + cfldrsle mvf7, [r9, #416]! + cfldrsvs mvf11, [r0, #-1020]! + cfldrscc mvf12, [r1], #-156 + cfldrs mvf13, [r9], #416 + cfldrscs mvf9, [r0], #-1020 + cfldrsls mvf4, [r1], #-156 + cfldrsle mvf7, [r9], #416 + cfldrdvs mvd11, [r0, #-1020] + cfldrdcc mvd12, [r1, #-156] + cfldrd mvd13, [r9, #416] + cfldrdcs mvd9, [r0, #-1020] + cfldrdls mvd4, [r1, #-156] + cfldrdle mvd7, [r9, #416]! + cfldrdvs mvd11, [r0, #-1020]! + cfldrdcc mvd12, [r1, #-156]! + cfldrd mvd13, [r9, #416]! + cfldrdcs mvd9, [r0, #-1020]! + cfldrdls mvd4, [r1], #-156 + cfldrdle mvd7, [r9], #416 + cfldrdvs mvd11, [r0], #-1020 + cfldrdcc mvd12, [r1], #-156 + cfldrd mvd13, [r9], #416 + cfldr32cs mvfx9, [r0, #-1020] + cfldr32ls mvfx4, [r1, #-156] + cfldr32le mvfx7, [r9, #416] + cfldr32vs mvfx11, [r0, #-1020] + cfldr32cc mvfx12, [r1, #-156] + cfldr32 mvfx13, [r9, #416]! + cfldr32cs mvfx9, [r0, #-1020]! + cfldr32ls mvfx4, [r1, #-156]! + cfldr32le mvfx7, [r9, #416]! + cfldr32vs mvfx11, [r0, #-1020]! + cfldr32cc mvfx12, [r1], #-156 + cfldr32 mvfx13, [r9], #416 + cfldr32cs mvfx9, [r0], #-1020 + cfldr32ls mvfx4, [r1], #-156 + cfldr32le mvfx7, [r9], #416 + cfldr64vs mvdx11, [r0, #-1020] + cfldr64cc mvdx12, [r1, #-156] + cfldr64 mvdx13, [r9, #416] + cfldr64cs mvdx9, [r0, #-1020] + cfldr64ls mvdx4, [r1, #-156] + cfldr64le mvdx7, [r9, #416]! + cfldr64vs mvdx11, [r0, #-1020]! + cfldr64cc mvdx12, [r1, #-156]! + cfldr64 mvdx13, [r9, #416]! + cfldr64cs mvdx9, [r0, #-1020]! + cfldr64ls mvdx4, [r1], #-156 + cfldr64le mvdx7, [r9], #416 + cfldr64vs mvdx11, [r0], #-1020 + cfldr64cc mvdx12, [r1], #-156 + cfldr64 mvdx13, [r9], #416 + cfstrscs mvf9, [r0, #-1020] + cfstrsls mvf4, [r1, #-156] + cfstrsle mvf7, [r9, #416] + cfstrsvs mvf11, [r0, #-1020] + cfstrscc mvf12, [r1, #-156] + cfstrs mvf13, [r9, #416]! + cfstrscs mvf9, [r0, #-1020]! + cfstrsls mvf4, [r1, #-156]! + cfstrsle mvf7, [r9, #416]! + cfstrsvs mvf11, [r0, #-1020]! + cfstrscc mvf12, [r1], #-156 + cfstrs mvf13, [r9], #416 + cfstrscs mvf9, [r0], #-1020 + cfstrsls mvf4, [r1], #-156 + cfstrsle mvf7, [r9], #416 + cfstrdvs mvd11, [r0, #-1020] + cfstrdcc mvd12, [r1, #-156] + cfstrd mvd13, [r9, #416] + cfstrdcs mvd9, [r0, #-1020] + cfstrdls mvd4, [r1, #-156] + cfstrdle mvd7, [r9, #416]! + cfstrdvs mvd11, [r0, #-1020]! + cfstrdcc mvd12, [r1, #-156]! + cfstrd mvd13, [r9, #416]! + cfstrdcs mvd9, [r0, #-1020]! + cfstrdls mvd4, [r1], #-156 + cfstrdle mvd7, [r9], #416 + cfstrdvs mvd11, [r0], #-1020 + cfstrdcc mvd12, [r1], #-156 + cfstrd mvd13, [r9], #416 + cfstr32cs mvfx9, [r0, #-1020] + cfstr32ls mvfx4, [r1, #-156] + cfstr32le mvfx7, [r9, #416] + cfstr32vs mvfx11, [r0, #-1020] + cfstr32cc mvfx12, [r1, #-156] + cfstr32 mvfx13, [r9, #416]! + cfstr32cs mvfx9, [r0, #-1020]! + cfstr32ls mvfx4, [r1, #-156]! + cfstr32le mvfx7, [r9, #416]! + cfstr32vs mvfx11, [r0, #-1020]! + cfstr32cc mvfx12, [r1], #-156 + cfstr32 mvfx13, [r9], #416 + cfstr32cs mvfx9, [r0], #-1020 + cfstr32ls mvfx4, [r1], #-156 + cfstr32le mvfx7, [r9], #416 + cfstr64vs mvdx11, [r0, #-1020] + cfstr64cc mvdx12, [r1, #-156] + cfstr64 mvdx13, [r9, #416] + cfstr64cs mvdx9, [r0, #-1020] + cfstr64ls mvdx4, [r1, #-156] + cfstr64le mvdx7, [r9, #416]! + cfstr64vs mvdx11, [r0, #-1020]! + cfstr64cc mvdx12, [r1, #-156]! + cfstr64 mvdx13, [r9, #416]! + cfstr64cs mvdx9, [r0, #-1020]! + cfstr64ls mvdx4, [r1], #-156 + cfstr64le mvdx7, [r9], #416 + cfstr64vs mvdx11, [r0], #-1020 + cfstr64cc mvdx12, [r1], #-156 + cfstr64 mvdx13, [r9], #416 +move: + cfmvsrcs mvf9, r0 + cfmvsrpl mvf15, r7 + cfmvsrls mvf4, r1 + cfmvsrcc mvf8, r2 + cfmvsrvc mvf2, r12 + cfmvrsgt r9, mvf11 + cfmvrseq sl, mvf5 + cfmvrsal r4, mvf12 + cfmvrsge fp, mvf8 + cfmvrs r5, mvf6 + cfmvdlrlt mvd4, r9 + cfmvdlrls mvd0, r10 + cfmvdlr mvd10, r4 + cfmvdlrmi mvd14, r11 + cfmvdlrhi mvd13, r5 + cfmvrdlcs r12, mvd12 + cfmvrdlvs r3, mvd0 + cfmvrdlvc r13, mvd14 + cfmvrdlcc r14, mvd10 + cfmvrdlne r8, mvd15 + cfmvdhrle mvd6, ip + cfmvdhrmi mvd2, r3 + cfmvdhreq mvd5, sp + cfmvdhrge mvd9, lr + cfmvdhral mvd3, r8 + cfmvrdhle r5, mvd2 + cfmvrdhne r6, mvd6 + cfmvrdhlt r0, mvd7 + cfmvrdhpl r7, mvd3 + cfmvrdhgt r1, mvd1 + cfmv64lrhi mvdx15, r5 + cfmv64lrvs mvdx11, r6 + cfmv64lrcs mvdx9, r0 + cfmv64lrpl mvdx15, r7 + cfmv64lrls mvdx4, r1 + cfmvr64lcc r8, mvdx13 + cfmvr64lvc pc, mvdx1 + cfmvr64lgt r9, mvdx11 + cfmvr64leq sl, mvdx5 + cfmvr64lal r4, mvdx12 + cfmv64hrge mvdx1, r8 + cfmv64hr mvdx13, r15 + cfmv64hrlt mvdx4, r9 + cfmv64hrls mvdx0, r10 + cfmv64hr mvdx10, r4 + cfmvr64hmi r1, mvdx3 + cfmvr64hhi r2, mvdx7 + cfmvr64hcs r12, mvdx12 + cfmvr64hvs r3, mvdx0 + cfmvr64hvc r13, mvdx14 + cfmval32cc mvax0, mvfx10 + cfmval32ne mvax1, mvfx15 + cfmval32le mvax0, mvfx11 + cfmval32mi mvax0, mvfx9 + cfmval32eq mvax1, mvfx15 + cfmv32alge mvfx9, mvax0 + cfmv32alal mvfx3, mvax1 + cfmv32alle mvfx7, mvax0 + cfmv32alne mvfx12, mvax0 + cfmv32allt mvfx0, mvax1 + cfmvam32pl mvax2, mvfx3 + cfmvam32gt mvax1, mvfx1 + cfmvam32hi mvax3, mvfx13 + cfmvam32vs mvax3, mvfx4 + cfmvam32cs mvax1, mvfx0 + cfmv32ampl mvfx15, mvax2 + cfmv32amls mvfx4, mvax1 + cfmv32amcc mvfx8, mvax3 + cfmv32amvc mvfx2, mvax3 + cfmv32amgt mvfx6, mvax1 + cfmvah32eq mvax1, mvfx5 + cfmvah32al mvax2, mvfx12 + cfmvah32ge mvax3, mvfx8 + cfmvah32 mvax2, mvfx6 + cfmvah32lt mvax2, mvfx2 + cfmv32ahls mvfx0, mvax1 + cfmv32ah mvfx10, mvax2 + cfmv32ahmi mvfx14, mvax3 + cfmv32ahhi mvfx13, mvax2 + cfmv32ahcs mvfx1, mvax2 + cfmva32vs mvax1, mvfx0 + cfmva32vc mvax3, mvfx14 + cfmva32cc mvax0, mvfx10 + cfmva32ne mvax1, mvfx15 + cfmva32le mvax0, mvfx11 + cfmv32ami mvfx2, mvax1 + cfmv32aeq mvfx5, mvax3 + cfmv32age mvfx9, mvax0 + cfmv32aal mvfx3, mvax1 + cfmv32ale mvfx7, mvax0 + cfmva64ne mvax2, mvdx6 + cfmva64lt mvax0, mvdx7 + cfmva64pl mvax2, mvdx3 + cfmva64gt mvax1, mvdx1 + cfmva64hi mvax3, mvdx13 + cfmv64avs mvdx11, mvax2 + cfmv64acs mvdx9, mvax0 + cfmv64apl mvdx15, mvax2 + cfmv64als mvdx4, mvax1 + cfmv64acc mvdx8, mvax3 + cfmvsc32vc dspsc, mvdx1 + cfmvsc32gt dspsc, mvdx11 + cfmvsc32eq dspsc, mvdx5 + cfmvsc32al dspsc, mvdx12 + cfmvsc32ge dspsc, mvdx8 + cfmv32sc mvdx13, dspsc + cfmv32sclt mvdx4, dspsc + cfmv32scls mvdx0, dspsc + cfmv32sc mvdx10, dspsc + cfmv32scmi mvdx14, dspsc + cfcpyshi mvf13, mvf7 + cfcpyscs mvf1, mvf12 + cfcpysvs mvf11, mvf0 + cfcpysvc mvf5, mvf14 + cfcpyscc mvf12, mvf10 + cfcpydne mvd8, mvd15 + cfcpydle mvd6, mvd11 + cfcpydmi mvd2, mvd9 + cfcpydeq mvd5, mvd15 + cfcpydge mvd9, mvd4 +conv: + cfcvtsdal mvd3, mvf8 + cfcvtsdle mvd7, mvf2 + cfcvtsdne mvd12, mvf6 + cfcvtsdlt mvd0, mvf7 + cfcvtsdpl mvd14, mvf3 + cfcvtdsgt mvf10, mvd1 + cfcvtdshi mvf15, mvd13 + cfcvtdsvs mvf11, mvd4 + cfcvtdscs mvf9, mvd0 + cfcvtdspl mvf15, mvd10 + cfcvt32sls mvf4, mvfx14 + cfcvt32scc mvf8, mvfx13 + cfcvt32svc mvf2, mvfx1 + cfcvt32sgt mvf6, mvfx11 + cfcvt32seq mvf7, mvfx5 + cfcvt32dal mvd3, mvfx12 + cfcvt32dge mvd1, mvfx8 + cfcvt32d mvd13, mvfx6 + cfcvt32dlt mvd4, mvfx2 + cfcvt32dls mvd0, mvfx5 + cfcvt64s mvf10, mvdx9 + cfcvt64smi mvf14, mvdx3 + cfcvt64shi mvf13, mvdx7 + cfcvt64scs mvf1, mvdx12 + cfcvt64svs mvf11, mvdx0 + cfcvt64dvc mvd5, mvdx14 + cfcvt64dcc mvd12, mvdx10 + cfcvt64dne mvd8, mvdx15 + cfcvt64dle mvd6, mvdx11 + cfcvt64dmi mvd2, mvdx9 + cfcvts32eq mvfx5, mvf15 + cfcvts32ge mvfx9, mvf4 + cfcvts32al mvfx3, mvf8 + cfcvts32le mvfx7, mvf2 + cfcvts32ne mvfx12, mvf6 + cfcvtd32lt mvfx0, mvd7 + cfcvtd32pl mvfx14, mvd3 + cfcvtd32gt mvfx10, mvd1 + cfcvtd32hi mvfx15, mvd13 + cfcvtd32vs mvfx11, mvd4 + cftruncs32cs mvfx9, mvf0 + cftruncs32pl mvfx15, mvf10 + cftruncs32ls mvfx4, mvf14 + cftruncs32cc mvfx8, mvf13 + cftruncs32vc mvfx2, mvf1 + cftruncd32gt mvfx6, mvd11 + cftruncd32eq mvfx7, mvd5 + cftruncd32al mvfx3, mvd12 + cftruncd32ge mvfx1, mvd8 + cftruncd32 mvfx13, mvd6 +shift: + cfrshl32lt mvfx4, mvfx2, r3 + cfrshl32pl mvfx15, mvfx10, r4 + cfrshl32al mvfx3, mvfx8, r2 + cfrshl32cs mvfx1, mvfx12, r9 + cfrshl32eq mvfx7, mvfx5, r7 + cfrshl64gt mvdx10, mvdx1, r8 + cfrshl64le mvdx6, mvdx11, r6 + cfrshl64ls mvdx0, mvdx5, sp + cfrshl64ls mvdx4, mvdx14, r11 + cfrshl64le mvdx7, mvdx2, r12 + cfsh32vs mvfx11, mvfx0, #-1 + cfsh32al mvfx3, mvfx12, #24 + cfsh32hi mvfx15, mvfx13, #33 + cfsh32mi mvfx2, mvfx9, #0 + cfsh32 mvfx10, mvfx9, #32 + cfsh64cc mvdx8, mvdx13, #-31 + cfsh64ne mvdx12, mvdx6, #1 + cfsh64vc mvdx5, mvdx14, #-32 + cfsh64ge mvdx1, mvdx8, #-27 + cfsh64vs mvdx11, mvdx4, #-5 +comp: + cfcmpseq r10, mvf15, mvf10 + cfcmpsmi r1, mvf3, mvf8 + cfcmpsvc pc, mvf1, mvf12 + cfcmpslt r0, mvf7, mvf5 + cfcmpscc r14, mvf10, mvf1 + cfcmpd r5, mvd6, mvd11 + cfcmpdcs r3, mvd0, mvd5 + cfcmpdge r4, mvd4, mvd14 + cfcmpdhi r2, mvd7, mvd2 + cfcmpdgt r9, mvd11, mvd0 + cfcmp32pl r7, mvfx3, mvfx12 + cfcmp32ne r8, mvfx15, mvfx13 + cfcmp32lt r6, mvfx2, mvfx9 + cfcmp32pl sp, mvfx10, mvfx9 + cfcmp32al r11, mvfx8, mvfx13 + cfcmp64cs r12, mvdx12, mvdx6 + cfcmp64eq sl, mvdx5, mvdx14 + cfcmp64gt r1, mvdx1, mvdx8 + cfcmp64le r15, mvdx11, mvdx4 + cfcmp64ls r0, mvdx5, mvdx15 +fp_arith: + cfabssls mvf4, mvf14 + cfabsscc mvf8, mvf13 + cfabssvc mvf2, mvf1 + cfabssgt mvf6, mvf11 + cfabsseq mvf7, mvf5 + cfabsdal mvd3, mvd12 + cfabsdge mvd1, mvd8 + cfabsd mvd13, mvd6 + cfabsdlt mvd4, mvd2 + cfabsdls mvd0, mvd5 + cfnegs mvf10, mvf9 + cfnegsmi mvf14, mvf3 + cfnegshi mvf13, mvf7 + cfnegscs mvf1, mvf12 + cfnegsvs mvf11, mvf0 + cfnegdvc mvd5, mvd14 + cfnegdcc mvd12, mvd10 + cfnegdne mvd8, mvd15 + cfnegdle mvd6, mvd11 + cfnegdmi mvd2, mvd9 + cfaddseq mvf5, mvf15, mvf10 + cfaddsmi mvf14, mvf3, mvf8 + cfaddsvc mvf2, mvf1, mvf12 + cfaddslt mvf0, mvf7, mvf5 + cfaddscc mvf12, mvf10, mvf1 + cfaddd mvd13, mvd6, mvd11 + cfadddcs mvd9, mvd0, mvd5 + cfadddge mvd9, mvd4, mvd14 + cfadddhi mvd13, mvd7, mvd2 + cfadddgt mvd6, mvd11, mvd0 + cfsubspl mvf14, mvf3, mvf12 + cfsubsne mvf8, mvf15, mvf13 + cfsubslt mvf4, mvf2, mvf9 + cfsubspl mvf15, mvf10, mvf9 + cfsubsal mvf3, mvf8, mvf13 + cfsubdcs mvd1, mvd12, mvd6 + cfsubdeq mvd7, mvd5, mvd14 + cfsubdgt mvd10, mvd1, mvd8 + cfsubdle mvd6, mvd11, mvd4 + cfsubdls mvd0, mvd5, mvd15 + cfmulsls mvf4, mvf14, mvf3 + cfmulsle mvf7, mvf2, mvf1 + cfmulsvs mvf11, mvf0, mvf7 + cfmulsal mvf3, mvf12, mvf10 + cfmulshi mvf15, mvf13, mvf6 + cfmuldmi mvd2, mvd9, mvd0 + cfmuld mvd10, mvd9, mvd4 + cfmuldcc mvd8, mvd13, mvd7 + cfmuldne mvd12, mvd6, mvd11 + cfmuldvc mvd5, mvd14, mvd3 +int_arith: + cfabs32ge mvfx1, mvfx8 + cfabs32 mvfx13, mvfx6 + cfabs32lt mvfx4, mvfx2 + cfabs32ls mvfx0, mvfx5 + cfabs32 mvfx10, mvfx9 + cfabs64mi mvdx14, mvdx3 + cfabs64hi mvdx13, mvdx7 + cfabs64cs mvdx1, mvdx12 + cfabs64vs mvdx11, mvdx0 + cfabs64vc mvdx5, mvdx14 + cfneg32cc mvfx12, mvfx10 + cfneg32ne mvfx8, mvfx15 + cfneg32le mvfx6, mvfx11 + cfneg32mi mvfx2, mvfx9 + cfneg32eq mvfx5, mvfx15 + cfneg64ge mvdx9, mvdx4 + cfneg64al mvdx3, mvdx8 + cfneg64le mvdx7, mvdx2 + cfneg64ne mvdx12, mvdx6 + cfneg64lt mvdx0, mvdx7 + cfadd32pl mvfx14, mvfx3, mvfx12 + cfadd32ne mvfx8, mvfx15, mvfx13 + cfadd32lt mvfx4, mvfx2, mvfx9 + cfadd32pl mvfx15, mvfx10, mvfx9 + cfadd32al mvfx3, mvfx8, mvfx13 + cfadd64cs mvdx1, mvdx12, mvdx6 + cfadd64eq mvdx7, mvdx5, mvdx14 + cfadd64gt mvdx10, mvdx1, mvdx8 + cfadd64le mvdx6, mvdx11, mvdx4 + cfadd64ls mvdx0, mvdx5, mvdx15 + cfsub32ls mvfx4, mvfx14, mvfx3 + cfsub32le mvfx7, mvfx2, mvfx1 + cfsub32vs mvfx11, mvfx0, mvfx7 + cfsub32al mvfx3, mvfx12, mvfx10 + cfsub32hi mvfx15, mvfx13, mvfx6 + cfsub64mi mvdx2, mvdx9, mvdx0 + cfsub64 mvdx10, mvdx9, mvdx4 + cfsub64cc mvdx8, mvdx13, mvdx7 + cfsub64ne mvdx12, mvdx6, mvdx11 + cfsub64vc mvdx5, mvdx14, mvdx3 + cfmul32ge mvfx1, mvfx8, mvfx15 + cfmul32vs mvfx11, mvfx4, mvfx2 + cfmul32eq mvfx5, mvfx15, mvfx10 + cfmul32mi mvfx14, mvfx3, mvfx8 + cfmul32vc mvfx2, mvfx1, mvfx12 + cfmul64lt mvdx0, mvdx7, mvdx5 + cfmul64cc mvdx12, mvdx10, mvdx1 + cfmul64 mvdx13, mvdx6, mvdx11 + cfmul64cs mvdx9, mvdx0, mvdx5 + cfmul64ge mvdx9, mvdx4, mvdx14 + cfmac32hi mvfx13, mvfx7, mvfx2 + cfmac32gt mvfx6, mvfx11, mvfx0 + cfmac32pl mvfx14, mvfx3, mvfx12 + cfmac32ne mvfx8, mvfx15, mvfx13 + cfmac32lt mvfx4, mvfx2, mvfx9 + cfmsc32pl mvfx15, mvfx10, mvfx9 + cfmsc32al mvfx3, mvfx8, mvfx13 + cfmsc32cs mvfx1, mvfx12, mvfx6 + cfmsc32eq mvfx7, mvfx5, mvfx14 + cfmsc32gt mvfx10, mvfx1, mvfx8 +acc_arith: + cfmadd32le mvax0, mvfx11, mvfx4, mvfx2 + cfmadd32ls mvax0, mvfx5, mvfx15, mvfx10 + cfmadd32ls mvax0, mvfx14, mvfx3, mvfx8 + cfmadd32le mvax2, mvfx2, mvfx1, mvfx12 + cfmadd32vs mvax1, mvfx0, mvfx7, mvfx5 + cfmsub32al mvax2, mvfx12, mvfx10, mvfx1 + cfmsub32hi mvax3, mvfx13, mvfx6, mvfx11 + cfmsub32mi mvax0, mvfx9, mvfx0, mvfx5 + cfmsub32 mvax2, mvfx9, mvfx4, mvfx14 + cfmsub32cc mvax1, mvfx13, mvfx7, mvfx2 + cfmadda32ne mvax2, mvax0, mvfx11, mvfx0 + cfmadda32vc mvax3, mvax2, mvfx3, mvfx12 + cfmadda32ge mvax3, mvax1, mvfx15, mvfx13 + cfmadda32vs mvax3, mvax2, mvfx2, mvfx9 + cfmadda32eq mvax1, mvax3, mvfx10, mvfx9 + cfmsuba32mi mvax1, mvax3, mvfx8, mvfx13 + cfmsuba32vc mvax0, mvax3, mvfx12, mvfx6 + cfmsuba32lt mvax0, mvax1, mvfx5, mvfx14 + cfmsuba32cc mvax0, mvax1, mvfx1, mvfx8 + cfmsuba32 mvax2, mvax0, mvfx11, mvfx4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/missing.d b/binutils-2.25/gas/testsuite/gas/arm/missing.d new file mode 100644 index 00000000..6a0cbf2d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/missing.d @@ -0,0 +1,3 @@ +#name: missing operands +#as: -march=armv5 +#error-output: missing.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/missing.l b/binutils-2.25/gas/testsuite/gas/arm/missing.l new file mode 100644 index 00000000..d6e59658 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/missing.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: missing expression -- `bl' +[^:]*:2: Error: missing expression -- `blx' diff --git a/binutils-2.25/gas/testsuite/gas/arm/missing.s b/binutils-2.25/gas/testsuite/gas/arm/missing.s new file mode 100644 index 00000000..c3e29357 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/missing.s @@ -0,0 +1,2 @@ + bl + blx diff --git a/binutils-2.25/gas/testsuite/gas/arm/mov-highregs-any.d b/binutils-2.25/gas/testsuite/gas/arm/mov-highregs-any.d new file mode 100644 index 00000000..a6be0065 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mov-highregs-any.d @@ -0,0 +1,8 @@ +# name: MOV highregs +# readelf: -A +# target: *-*-*eabi* *-*-nacl* +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v4T + Tag_THUMB_ISA_use: Thumb-1 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/mov-highregs-any.s b/binutils-2.25/gas/testsuite/gas/arm/mov-highregs-any.s new file mode 100644 index 00000000..9e9e5873 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mov-highregs-any.s @@ -0,0 +1,3 @@ + .syntax unified + .thumb + mov r8, r8 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mov-lowregs-any.d b/binutils-2.25/gas/testsuite/gas/arm/mov-lowregs-any.d new file mode 100644 index 00000000..7e29e134 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mov-lowregs-any.d @@ -0,0 +1,7 @@ +# name: MOV lowregs +# readelf: -A +# target: *-*-*eabi* *-*-nacl* +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v6 + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mov-lowregs-any.s b/binutils-2.25/gas/testsuite/gas/arm/mov-lowregs-any.s new file mode 100644 index 00000000..12619eff --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mov-lowregs-any.s @@ -0,0 +1,3 @@ + .syntax unified + .thumb + mov r0, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/movw-local.d b/binutils-2.25/gas/testsuite/gas/arm/movw-local.d new file mode 100644 index 00000000..af9562e4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/movw-local.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#name: MOVW/MOVT relocations against local symbols + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e3000000 movw r0, #0 + 0: R_ARM_MOVW_ABS_NC bar +0[0-9a-f]+ <[^>]+> e3400000 movt r0, #0 + 4: R_ARM_MOVT_ABS bar +0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 + 8: R_ARM_THM_MOVW_ABS_NC bar +0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 + c: R_ARM_THM_MOVT_ABS bar +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/movw-local.s b/binutils-2.25/gas/testsuite/gas/arm/movw-local.s new file mode 100644 index 00000000..fa923c91 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/movw-local.s @@ -0,0 +1,13 @@ +.arch armv7-a +.text +.syntax unified +foo: +movw r0, #:lower16: bar +movt r0, #:upper16: bar +.thumb +movw r0, #:lower16: bar +movt r0, #:upper16: bar + +.space 0x10000 + +bar: diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v6.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v6.d new file mode 100644 index 00000000..0afafad1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v6.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MRS/MSR test, architecture v6, ARM mode + +.*: file format .* + + +Disassembly of section .text: +0+00 <[^>]*> e10f4000 mrs r4, CPSR +0+04 <[^>]*> e10f5000 mrs r5, CPSR +0+08 <[^>]*> e14f6000 mrs r6, SPSR +0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000 +0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000 +0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000 +0+18 <[^>]*> e128f004 msr CPSR_f, r4 +0+1c <[^>]*> e128f005 msr CPSR_f, r5 +0+20 <[^>]*> e169f006 msr SPSR_fc, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v6.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v6.s new file mode 100644 index 00000000..c52abd91 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v6.s @@ -0,0 +1,13 @@ + .arch armv6 + .text + .arm + + mrs r4, apsr + mrs r5, cpsr + mrs r6, spsr + msr apsr_nzcvq, #0x40000000 + msr cpsr_f, #0x20000000 + msr spsr, #0x10000000 + msr apsr_nzcvq, r4 + msr cpsr_f, r5 + msr spsr, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d new file mode 100644 index 00000000..e4cf35e1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.d @@ -0,0 +1,2 @@ +# name: MRS/MSR negative test, architecture v7-A, ARM mode +# error-output: mrs-msr-arm-v7-a-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l new file mode 100644 index 00000000..222198f0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +[^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq' +[^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,iapsr' +[^:]*:7: Error: selected processor does not support requested special purpose register -- `msr iapsr,r4' +[^:]*:8: writing to APSR without specifying a bitmask is deprecated diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s new file mode 100644 index 00000000..e76af9fb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a-bad.s @@ -0,0 +1,8 @@ + .arch armv7-a + .text + .arm + + mrs r4, apsr_nzcvq + mrs r5, iapsr + msr iapsr, r4 + msr apsr, r5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d new file mode 100644 index 00000000..62d93492 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MRS/MSR test, architecture v7-A, ARM mode + +.*: file format .* + + +Disassembly of section .text: +0+00 <[^>]*> e10f4000 mrs r4, CPSR +0+04 <[^>]*> e10f5000 mrs r5, CPSR +0+08 <[^>]*> e14f6000 mrs r6, SPSR +0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000 +0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000 +0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000 +0+18 <[^>]*> e128f004 msr CPSR_f, r4 +0+1c <[^>]*> e128f005 msr CPSR_f, r5 +0+20 <[^>]*> e169f006 msr SPSR_fc, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s new file mode 100644 index 00000000..c9ecada8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-arm-v7-a.s @@ -0,0 +1,13 @@ + .arch armv7-a + .text + .arm + + mrs r4, apsr + mrs r5, cpsr + mrs r6, spsr + msr apsr_nzcvqg, #0x40000000 + msr cpsr_f, #0x20000000 + msr spsr, #0x10000000 + msr apsr_nzcvq, r4 + msr cpsr_f, r5 + msr spsr, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d new file mode 100644 index 00000000..232e2373 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d @@ -0,0 +1,15 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MRS/MSR test, architecture v6t2, Thumb mode +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: file format .* + + +Disassembly of section .text: +0+00 <[^>]*> f3ef 8400 mrs r4, CPSR +0+04 <[^>]*> f3ef 8500 mrs r5, CPSR +0+08 <[^>]*> f3ff 8600 mrs r6, SPSR +0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4 +0+10 <[^>]*> f385 8800 msr CPSR_f, r5 +0+14 <[^>]*> f396 8900 msr SPSR_fc, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s new file mode 100644 index 00000000..2d041c5a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.s @@ -0,0 +1,10 @@ + .arch armv6t2 + .text + .thumb + + mrs r4, apsr + mrs r5, cpsr + mrs r6, spsr + msr apsr_nzcvqg, r4 + msr cpsr_f, r5 + msr spsr, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d new file mode 100644 index 00000000..eef7f030 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.d @@ -0,0 +1,2 @@ +# name: MRS/MSR negative test, architecture v7-M, Thumb mode +# error-output: mrs-msr-thumb-v7-m-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l new file mode 100644 index 00000000..e9770b6d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.l @@ -0,0 +1,10 @@ +[^:]*: Assembler messages: +[^:]*:5: Error: selected processor does not support requested special purpose register -- `mrs r4,cpsr' +[^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,spsr' +[^:]*:7: Error: selected processor does not support DSP extension -- `msr apsr_nzcvqg,r4' +[^:]*:8: Error: selected processor does not support DSP extension -- `msr iapsr_nzcvqg,r5' +[^:]*:9: Error: bad bitmask specified after APSR -- `msr xpsr_nncvq,r6' +[^:]*:10: Error: bad bitmask specified after APSR -- `msr xpsr_nzcv,r7' +[^:]*:11: Error: selected processor does not support requested special purpose register -- `msr cpsr_f,r7' +[^:]*:12: Error: selected processor does not support requested special purpose register -- `msr spsr,r8' +[^:]*:13: Error: syntax error -- `msr primask_nzcvq,r9' diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s new file mode 100644 index 00000000..da61015c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m-bad.s @@ -0,0 +1,13 @@ + .arch armv7-m + .text + .thumb + + mrs r4, cpsr + mrs r5, spsr + msr apsr_nzcvqg, r4 + msr iapsr_nzcvqg, r5 + msr xpsr_nncvq, r6 + msr xpsr_nzcv, r7 + msr cpsr_f, r7 + msr spsr, r8 + msr primask_nzcvq, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d new file mode 100644 index 00000000..594ab43c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MRS/MSR test, architecture v7-M, Thumb mode +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: file format .* + + +Disassembly of section .text: +0+00 <[^>]*> f3ef 8400 mrs r4, CPSR +0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR +0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK +0+0c <[^>]*> f383 8803 msr PSR, r3 +0+10 <[^>]*> f384 8800 msr CPSR_f, r4 +0+14 <[^>]*> f385 8801 msr IAPSR, r5 +0+18 <[^>]*> f386 8810 msr PRIMASK, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s new file mode 100644 index 00000000..54cf7230 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.s @@ -0,0 +1,11 @@ + .arch armv7-m + .text + .thumb + + mrs r4, apsr + mrs r5, eapsr + mrs r6, primask + msr xpsr_nzcvq, r3 + msr apsr_nzcvq, r4 + msr iapsr_nzcvq, r5 + msr primask, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d new file mode 100644 index 00000000..a1595ca7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d @@ -0,0 +1,15 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MRS/MSR test, architecture v7e-M, Thumb mode +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: file format .* + + +Disassembly of section .text: +0+00 <[^>]*> f3ef 8400 mrs r4, CPSR +0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR +0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK +0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4 +0+10 <[^>]*> f385 8401 msr IAPSR, r5 +0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s new file mode 100644 index 00000000..e9e85883 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s @@ -0,0 +1,10 @@ + .arch armv7e-m + .text + .thumb + + mrs r4, apsr + mrs r5, eapsr + mrs r6, primask + msr apsr_nzcvqg, r4 + msr iapsr_g, r5 + msr basepri_max, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-imm-bad.d b/binutils-2.25/gas/testsuite/gas/arm/msr-imm-bad.d new file mode 100644 index 00000000..ae1faa7a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-imm-bad.d @@ -0,0 +1,5 @@ +# name: Cannot use MSR with immediates in thumb mode. +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +# error-output: msr-imm-bad.l +# source: msr-imm.s +# as: -march=armv7-a -mthumb diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-imm-bad.l b/binutils-2.25/gas/testsuite/gas/arm/msr-imm-bad.l new file mode 100644 index 00000000..78d958bf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-imm-bad.l @@ -0,0 +1,135 @@ +[^:]*: Assembler messages: +[^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004' +[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004' +[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004' +[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004' +[^:]*:15: Error: Thumb encoding does not support an immediate here -- `msr CPSR,#0xc0000004' +[^:]*:16: Error: Thumb encoding does not support an immediate here -- `msr CPSR_s,#0xc0000004' +[^:]*:17: Error: Thumb encoding does not support an immediate here -- `msr CPSR_f,#0xc0000004' +[^:]*:18: Error: Thumb encoding does not support an immediate here -- `msr CPSR_c,#0xc0000004' +[^:]*:19: Error: Thumb encoding does not support an immediate here -- `msr CPSR_x,#0xc0000004' +[^:]*:22: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fs,#0xc0000004' +[^:]*:23: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fx,#0xc0000004' +[^:]*:24: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fc,#0xc0000004' +[^:]*:25: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sf,#0xc0000004' +[^:]*:26: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sx,#0xc0000004' +[^:]*:27: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sc,#0xc0000004' +[^:]*:28: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xf,#0xc0000004' +[^:]*:29: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xs,#0xc0000004' +[^:]*:30: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xc,#0xc0000004' +[^:]*:31: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cf,#0xc0000004' +[^:]*:32: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cs,#0xc0000004' +[^:]*:33: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cx,#0xc0000004' +[^:]*:34: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fsx,#0xc0000004' +[^:]*:35: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fsc,#0xc0000004' +[^:]*:36: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxs,#0xc0000004' +[^:]*:37: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxc,#0xc0000004' +[^:]*:38: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcs,#0xc0000004' +[^:]*:39: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcx,#0xc0000004' +[^:]*:40: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfx,#0xc0000004' +[^:]*:41: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfc,#0xc0000004' +[^:]*:42: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxf,#0xc0000004' +[^:]*:43: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxc,#0xc0000004' +[^:]*:44: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scf,#0xc0000004' +[^:]*:45: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scx,#0xc0000004' +[^:]*:46: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfs,#0xc0000004' +[^:]*:47: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfc,#0xc0000004' +[^:]*:48: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xsf,#0xc0000004' +[^:]*:49: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xsc,#0xc0000004' +[^:]*:50: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcf,#0xc0000004' +[^:]*:51: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcs,#0xc0000004' +[^:]*:52: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfs,#0xc0000004' +[^:]*:53: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfx,#0xc0000004' +[^:]*:54: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csf,#0xc0000004' +[^:]*:55: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csx,#0xc0000004' +[^:]*:56: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxf,#0xc0000004' +[^:]*:57: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxs,#0xc0000004' +[^:]*:58: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fsxc,#0xc0000004' +[^:]*:59: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fscx,#0xc0000004' +[^:]*:60: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxsc,#0xc0000004' +[^:]*:61: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fxcs,#0xc0000004' +[^:]*:62: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcsx,#0xc0000004' +[^:]*:63: Error: Thumb encoding does not support an immediate here -- `msr CPSR_fcxs,#0xc0000004' +[^:]*:64: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfxc,#0xc0000004' +[^:]*:65: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sfcx,#0xc0000004' +[^:]*:66: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxfc,#0xc0000004' +[^:]*:67: Error: Thumb encoding does not support an immediate here -- `msr CPSR_sxcf,#0xc0000004' +[^:]*:68: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scfx,#0xc0000004' +[^:]*:69: Error: Thumb encoding does not support an immediate here -- `msr CPSR_scxf,#0xc0000004' +[^:]*:70: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfsc,#0xc0000004' +[^:]*:71: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xfcs,#0xc0000004' +[^:]*:72: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xsfc,#0xc0000004' +[^:]*:73: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xscf,#0xc0000004' +[^:]*:74: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcfs,#0xc0000004' +[^:]*:75: Error: Thumb encoding does not support an immediate here -- `msr CPSR_xcsf,#0xc0000004' +[^:]*:76: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfsx,#0xc0000004' +[^:]*:77: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cfxs,#0xc0000004' +[^:]*:78: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csfx,#0xc0000004' +[^:]*:79: Error: Thumb encoding does not support an immediate here -- `msr CPSR_csxf,#0xc0000004' +[^:]*:80: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxfs,#0xc0000004' +[^:]*:81: Error: Thumb encoding does not support an immediate here -- `msr CPSR_cxsf,#0xc0000004' +[^:]*:85: Error: Thumb encoding does not support an immediate here -- `msr SPSR,#0xc0000004' +[^:]*:86: Error: Thumb encoding does not support an immediate here -- `msr SPSR_s,#0xc0000004' +[^:]*:87: Error: Thumb encoding does not support an immediate here -- `msr SPSR_f,#0xc0000004' +[^:]*:88: Error: Thumb encoding does not support an immediate here -- `msr SPSR_c,#0xc0000004' +[^:]*:89: Error: Thumb encoding does not support an immediate here -- `msr SPSR_x,#0xc0000004' +[^:]*:92: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fs,#0xc0000004' +[^:]*:93: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fx,#0xc0000004' +[^:]*:94: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fc,#0xc0000004' +[^:]*:95: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sf,#0xc0000004' +[^:]*:96: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sx,#0xc0000004' +[^:]*:97: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sc,#0xc0000004' +[^:]*:98: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xf,#0xc0000004' +[^:]*:99: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xs,#0xc0000004' +[^:]*:100: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xc,#0xc0000004' +[^:]*:101: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cf,#0xc0000004' +[^:]*:102: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cs,#0xc0000004' +[^:]*:103: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cx,#0xc0000004' +[^:]*:104: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fsx,#0xc0000004' +[^:]*:105: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fsc,#0xc0000004' +[^:]*:106: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxs,#0xc0000004' +[^:]*:107: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxc,#0xc0000004' +[^:]*:108: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcs,#0xc0000004' +[^:]*:109: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcx,#0xc0000004' +[^:]*:110: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfx,#0xc0000004' +[^:]*:111: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfc,#0xc0000004' +[^:]*:112: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxf,#0xc0000004' +[^:]*:113: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxc,#0xc0000004' +[^:]*:114: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scf,#0xc0000004' +[^:]*:115: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scx,#0xc0000004' +[^:]*:116: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfs,#0xc0000004' +[^:]*:117: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfc,#0xc0000004' +[^:]*:118: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xsf,#0xc0000004' +[^:]*:119: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xsc,#0xc0000004' +[^:]*:120: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcf,#0xc0000004' +[^:]*:121: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcs,#0xc0000004' +[^:]*:122: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfs,#0xc0000004' +[^:]*:123: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfx,#0xc0000004' +[^:]*:124: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csf,#0xc0000004' +[^:]*:125: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csx,#0xc0000004' +[^:]*:126: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxf,#0xc0000004' +[^:]*:127: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxs,#0xc0000004' +[^:]*:128: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fsxc,#0xc0000004' +[^:]*:129: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fscx,#0xc0000004' +[^:]*:130: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxsc,#0xc0000004' +[^:]*:131: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fxcs,#0xc0000004' +[^:]*:132: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcsx,#0xc0000004' +[^:]*:133: Error: Thumb encoding does not support an immediate here -- `msr SPSR_fcxs,#0xc0000004' +[^:]*:134: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfxc,#0xc0000004' +[^:]*:135: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sfcx,#0xc0000004' +[^:]*:136: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxfc,#0xc0000004' +[^:]*:137: Error: Thumb encoding does not support an immediate here -- `msr SPSR_sxcf,#0xc0000004' +[^:]*:138: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scfx,#0xc0000004' +[^:]*:139: Error: Thumb encoding does not support an immediate here -- `msr SPSR_scxf,#0xc0000004' +[^:]*:140: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfsc,#0xc0000004' +[^:]*:141: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xfcs,#0xc0000004' +[^:]*:142: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xsfc,#0xc0000004' +[^:]*:143: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xscf,#0xc0000004' +[^:]*:144: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcfs,#0xc0000004' +[^:]*:145: Error: Thumb encoding does not support an immediate here -- `msr SPSR_xcsf,#0xc0000004' +[^:]*:146: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfsx,#0xc0000004' +[^:]*:147: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cfxs,#0xc0000004' +[^:]*:148: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csfx,#0xc0000004' +[^:]*:149: Error: Thumb encoding does not support an immediate here -- `msr SPSR_csxf,#0xc0000004' +[^:]*:150: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxfs,#0xc0000004' +[^:]*:151: Error: Thumb encoding does not support an immediate here -- `msr SPSR_cxsf,#0xc0000004' diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-imm.d b/binutils-2.25/gas/testsuite/gas/arm/msr-imm.d new file mode 100644 index 00000000..729720d6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-imm.d @@ -0,0 +1,141 @@ +# name: MSR immediate operands +# as: -march=armv7-a +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004 +00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004 +00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004 +0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004 +00000010 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +00000014 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004 +00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004 +0000001c <[^>]*> e321f113 msr CPSR_c, #-1073741820 ; 0xc0000004 +00000020 <[^>]*> e322f113 msr CPSR_x, #-1073741820 ; 0xc0000004 +00000024 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004 +00000028 <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004 +0000002c <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +00000030 <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004 +00000034 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004 +00000038 <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004 +0000003c <[^>]*> e32af113 msr CPSR_fx, #-1073741820 ; 0xc0000004 +00000040 <[^>]*> e326f113 msr CPSR_sx, #-1073741820 ; 0xc0000004 +00000044 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004 +00000048 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004 +0000004c <[^>]*> e325f113 msr CPSR_sc, #-1073741820 ; 0xc0000004 +00000050 <[^>]*> e323f113 msr CPSR_xc, #-1073741820 ; 0xc0000004 +00000054 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000058 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +0000005c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000060 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +00000064 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +00000068 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +0000006c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000070 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +00000074 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000078 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +0000007c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +00000080 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +00000084 <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000088 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +0000008c <[^>]*> e32ef113 msr CPSR_fsx, #-1073741820 ; 0xc0000004 +00000090 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +00000094 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +00000098 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +0000009c <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +000000a0 <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +000000a4 <[^>]*> e32df113 msr CPSR_fsc, #-1073741820 ; 0xc0000004 +000000a8 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +000000ac <[^>]*> e32bf113 msr CPSR_fxc, #-1073741820 ; 0xc0000004 +000000b0 <[^>]*> e327f113 msr CPSR_sxc, #-1073741820 ; 0xc0000004 +000000b4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000b8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000bc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000c0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000c4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000c8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000cc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000d0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000d4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000d8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000dc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000e0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000e4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000e8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000ec <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000f0 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000f4 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000f8 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +000000fc <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000100 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000104 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000108 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +0000010c <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000110 <[^>]*> e32ff113 msr CPSR_fsxc, #-1073741820 ; 0xc0000004 +00000114 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004 +00000118 <[^>]*> e364f113 msr SPSR_s, #-1073741820 ; 0xc0000004 +0000011c <[^>]*> e368f113 msr SPSR_f, #-1073741820 ; 0xc0000004 +00000120 <[^>]*> e361f113 msr SPSR_c, #-1073741820 ; 0xc0000004 +00000124 <[^>]*> e362f113 msr SPSR_x, #-1073741820 ; 0xc0000004 +00000128 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004 +0000012c <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004 +00000130 <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004 +00000134 <[^>]*> e36cf113 msr SPSR_fs, #-1073741820 ; 0xc0000004 +00000138 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004 +0000013c <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004 +00000140 <[^>]*> e36af113 msr SPSR_fx, #-1073741820 ; 0xc0000004 +00000144 <[^>]*> e366f113 msr SPSR_sx, #-1073741820 ; 0xc0000004 +00000148 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004 +0000014c <[^>]*> e369f113 msr SPSR_fc, #-1073741820 ; 0xc0000004 +00000150 <[^>]*> e365f113 msr SPSR_sc, #-1073741820 ; 0xc0000004 +00000154 <[^>]*> e363f113 msr SPSR_xc, #-1073741820 ; 0xc0000004 +00000158 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +0000015c <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +00000160 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +00000164 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +00000168 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +0000016c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +00000170 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +00000174 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +00000178 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +0000017c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +00000180 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +00000184 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +00000188 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +0000018c <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +00000190 <[^>]*> e36ef113 msr SPSR_fsx, #-1073741820 ; 0xc0000004 +00000194 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +00000198 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +0000019c <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +000001a0 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +000001a4 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +000001a8 <[^>]*> e36df113 msr SPSR_fsc, #-1073741820 ; 0xc0000004 +000001ac <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +000001b0 <[^>]*> e36bf113 msr SPSR_fxc, #-1073741820 ; 0xc0000004 +000001b4 <[^>]*> e367f113 msr SPSR_sxc, #-1073741820 ; 0xc0000004 +000001b8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001bc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001c0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001c4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001c8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001cc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001d0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001d4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001d8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001dc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001e0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001e4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001e8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001ec <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001f0 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001f4 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001f8 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +000001fc <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000200 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000204 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000208 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +0000020c <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000210 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 +00000214 <[^>]*> e36ff113 msr SPSR_fsxc, #-1073741820 ; 0xc0000004 diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-imm.s b/binutils-2.25/gas/testsuite/gas/arm/msr-imm.s new file mode 100644 index 00000000..3fd963e8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-imm.s @@ -0,0 +1,153 @@ +@ Check MSR and MRS instruction operand syntax. +@ Also check for MSR/MRS acceptance in ARM/THUMB modes. + +.section .text +.syntax unified + + @ Write to Special Register from Immediate + @ Write to application status register + msr APSR_nzcvq,#0xc0000004 + msr APSR_g,#0xc0000004 + msr APSR_nzcvq,#0xc0000004 + msr APSR_nzcvqg,#0xc0000004 + + @ Write to CPSR flags + msr CPSR,#0xc0000004 + msr CPSR_s,#0xc0000004 + msr CPSR_f,#0xc0000004 + msr CPSR_c,#0xc0000004 + msr CPSR_x,#0xc0000004 + + @ Write to CPSR flag combos + msr CPSR_fs, #0xc0000004 + msr CPSR_fx, #0xc0000004 + msr CPSR_fc, #0xc0000004 + msr CPSR_sf, #0xc0000004 + msr CPSR_sx, #0xc0000004 + msr CPSR_sc, #0xc0000004 + msr CPSR_xf, #0xc0000004 + msr CPSR_xs, #0xc0000004 + msr CPSR_xc, #0xc0000004 + msr CPSR_cf, #0xc0000004 + msr CPSR_cs, #0xc0000004 + msr CPSR_cx, #0xc0000004 + msr CPSR_fsx, #0xc0000004 + msr CPSR_fsc, #0xc0000004 + msr CPSR_fxs, #0xc0000004 + msr CPSR_fxc, #0xc0000004 + msr CPSR_fcs, #0xc0000004 + msr CPSR_fcx, #0xc0000004 + msr CPSR_sfx, #0xc0000004 + msr CPSR_sfc, #0xc0000004 + msr CPSR_sxf, #0xc0000004 + msr CPSR_sxc, #0xc0000004 + msr CPSR_scf, #0xc0000004 + msr CPSR_scx, #0xc0000004 + msr CPSR_xfs, #0xc0000004 + msr CPSR_xfc, #0xc0000004 + msr CPSR_xsf, #0xc0000004 + msr CPSR_xsc, #0xc0000004 + msr CPSR_xcf, #0xc0000004 + msr CPSR_xcs, #0xc0000004 + msr CPSR_cfs, #0xc0000004 + msr CPSR_cfx, #0xc0000004 + msr CPSR_csf, #0xc0000004 + msr CPSR_csx, #0xc0000004 + msr CPSR_cxf, #0xc0000004 + msr CPSR_cxs, #0xc0000004 + msr CPSR_fsxc, #0xc0000004 + msr CPSR_fscx, #0xc0000004 + msr CPSR_fxsc, #0xc0000004 + msr CPSR_fxcs, #0xc0000004 + msr CPSR_fcsx, #0xc0000004 + msr CPSR_fcxs, #0xc0000004 + msr CPSR_sfxc, #0xc0000004 + msr CPSR_sfcx, #0xc0000004 + msr CPSR_sxfc, #0xc0000004 + msr CPSR_sxcf, #0xc0000004 + msr CPSR_scfx, #0xc0000004 + msr CPSR_scxf, #0xc0000004 + msr CPSR_xfsc, #0xc0000004 + msr CPSR_xfcs, #0xc0000004 + msr CPSR_xsfc, #0xc0000004 + msr CPSR_xscf, #0xc0000004 + msr CPSR_xcfs, #0xc0000004 + msr CPSR_xcsf, #0xc0000004 + msr CPSR_cfsx, #0xc0000004 + msr CPSR_cfxs, #0xc0000004 + msr CPSR_csfx, #0xc0000004 + msr CPSR_csxf, #0xc0000004 + msr CPSR_cxfs, #0xc0000004 + msr CPSR_cxsf, #0xc0000004 + + @ Write to Saved status register + @ Write to SPSR flags + msr SPSR, #0xc0000004 + msr SPSR_s, #0xc0000004 + msr SPSR_f, #0xc0000004 + msr SPSR_c, #0xc0000004 + msr SPSR_x, #0xc0000004 + + @Write to SPSR flag combos + msr SPSR_fs, #0xc0000004 + msr SPSR_fx, #0xc0000004 + msr SPSR_fc, #0xc0000004 + msr SPSR_sf, #0xc0000004 + msr SPSR_sx, #0xc0000004 + msr SPSR_sc, #0xc0000004 + msr SPSR_xf, #0xc0000004 + msr SPSR_xs, #0xc0000004 + msr SPSR_xc, #0xc0000004 + msr SPSR_cf, #0xc0000004 + msr SPSR_cs, #0xc0000004 + msr SPSR_cx, #0xc0000004 + msr SPSR_fsx, #0xc0000004 + msr SPSR_fsc, #0xc0000004 + msr SPSR_fxs, #0xc0000004 + msr SPSR_fxc, #0xc0000004 + msr SPSR_fcs, #0xc0000004 + msr SPSR_fcx, #0xc0000004 + msr SPSR_sfx, #0xc0000004 + msr SPSR_sfc, #0xc0000004 + msr SPSR_sxf, #0xc0000004 + msr SPSR_sxc, #0xc0000004 + msr SPSR_scf, #0xc0000004 + msr SPSR_scx, #0xc0000004 + msr SPSR_xfs, #0xc0000004 + msr SPSR_xfc, #0xc0000004 + msr SPSR_xsf, #0xc0000004 + msr SPSR_xsc, #0xc0000004 + msr SPSR_xcf, #0xc0000004 + msr SPSR_xcs, #0xc0000004 + msr SPSR_cfs, #0xc0000004 + msr SPSR_cfx, #0xc0000004 + msr SPSR_csf, #0xc0000004 + msr SPSR_csx, #0xc0000004 + msr SPSR_cxf, #0xc0000004 + msr SPSR_cxs, #0xc0000004 + msr SPSR_fsxc, #0xc0000004 + msr SPSR_fscx, #0xc0000004 + msr SPSR_fxsc, #0xc0000004 + msr SPSR_fxcs, #0xc0000004 + msr SPSR_fcsx, #0xc0000004 + msr SPSR_fcxs, #0xc0000004 + msr SPSR_sfxc, #0xc0000004 + msr SPSR_sfcx, #0xc0000004 + msr SPSR_sxfc, #0xc0000004 + msr SPSR_sxcf, #0xc0000004 + msr SPSR_scfx, #0xc0000004 + msr SPSR_scxf, #0xc0000004 + msr SPSR_xfsc, #0xc0000004 + msr SPSR_xfcs, #0xc0000004 + msr SPSR_xsfc, #0xc0000004 + msr SPSR_xscf, #0xc0000004 + msr SPSR_xcfs, #0xc0000004 + msr SPSR_xcsf, #0xc0000004 + msr SPSR_cfsx, #0xc0000004 + msr SPSR_cfxs, #0xc0000004 + msr SPSR_csfx, #0xc0000004 + msr SPSR_csxf, #0xc0000004 + msr SPSR_cxfs, #0xc0000004 + msr SPSR_cxsf, #0xc0000004 + + diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-reg-bad.d b/binutils-2.25/gas/testsuite/gas/arm/msr-reg-bad.d new file mode 100644 index 00000000..468bb613 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-reg-bad.d @@ -0,0 +1,5 @@ +# name: Cannot use flag-variant of PSR on v7m and v6m. +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +# error-output: msr-reg-bad.l +# source: msr-reg.s +# as: -march=armv7-m diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-reg-bad.l b/binutils-2.25/gas/testsuite/gas/arm/msr-reg-bad.l new file mode 100644 index 00000000..585d418f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-reg-bad.l @@ -0,0 +1,134 @@ +[^:]*: Assembler messages: +[^:]*:8: writing to APSR without specifying a bitmask is deprecated +[^:]*:9: Error: selected processor does not support DSP extension -- `msr APSR_g,r9' +[^:]*:11: Error: selected processor does not support DSP extension -- `msr APSR_nzcvqg,r9' +[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9' +[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9' +[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9' +[^:]*:17: Error: selected processor does not support requested special purpose register -- `msr CPSR_c,r9' +[^:]*:18: Error: selected processor does not support requested special purpose register -- `msr CPSR_x,r9' +[^:]*:21: Error: selected processor does not support requested special purpose register -- `msr CPSR_fs,r9' +[^:]*:22: Error: selected processor does not support requested special purpose register -- `msr CPSR_fx,r9' +[^:]*:23: Error: selected processor does not support requested special purpose register -- `msr CPSR_fc,r9' +[^:]*:24: Error: selected processor does not support requested special purpose register -- `msr CPSR_sf,r9' +[^:]*:25: Error: selected processor does not support requested special purpose register -- `msr CPSR_sx,r9' +[^:]*:26: Error: selected processor does not support requested special purpose register -- `msr CPSR_sc,r9' +[^:]*:27: Error: selected processor does not support requested special purpose register -- `msr CPSR_xf,r9' +[^:]*:28: Error: selected processor does not support requested special purpose register -- `msr CPSR_xs,r9' +[^:]*:29: Error: selected processor does not support requested special purpose register -- `msr CPSR_xc,r9' +[^:]*:30: Error: selected processor does not support requested special purpose register -- `msr CPSR_cf,r9' +[^:]*:31: Error: selected processor does not support requested special purpose register -- `msr CPSR_cs,r9' +[^:]*:32: Error: selected processor does not support requested special purpose register -- `msr CPSR_cx,r9' +[^:]*:33: Error: selected processor does not support requested special purpose register -- `msr CPSR_fsx,r9' +[^:]*:34: Error: selected processor does not support requested special purpose register -- `msr CPSR_fsc,r9' +[^:]*:35: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxs,r9' +[^:]*:36: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxc,r9' +[^:]*:37: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcs,r9' +[^:]*:38: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcx,r9' +[^:]*:39: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfx,r9' +[^:]*:40: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfc,r9' +[^:]*:41: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxf,r9' +[^:]*:42: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxc,r9' +[^:]*:43: Error: selected processor does not support requested special purpose register -- `msr CPSR_scf,r9' +[^:]*:44: Error: selected processor does not support requested special purpose register -- `msr CPSR_scx,r9' +[^:]*:45: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfs,r9' +[^:]*:46: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfc,r9' +[^:]*:47: Error: selected processor does not support requested special purpose register -- `msr CPSR_xsf,r9' +[^:]*:48: Error: selected processor does not support requested special purpose register -- `msr CPSR_xsc,r9' +[^:]*:49: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcf,r9' +[^:]*:50: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcs,r9' +[^:]*:51: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfs,r9' +[^:]*:52: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfx,r9' +[^:]*:53: Error: selected processor does not support requested special purpose register -- `msr CPSR_csf,r9' +[^:]*:54: Error: selected processor does not support requested special purpose register -- `msr CPSR_csx,r9' +[^:]*:55: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxf,r9' +[^:]*:56: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxs,r9' +[^:]*:57: Error: selected processor does not support requested special purpose register -- `msr CPSR_fsxc,r9' +[^:]*:58: Error: selected processor does not support requested special purpose register -- `msr CPSR_fscx,r9' +[^:]*:59: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxsc,r9' +[^:]*:60: Error: selected processor does not support requested special purpose register -- `msr CPSR_fxcs,r9' +[^:]*:61: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcsx,r9' +[^:]*:62: Error: selected processor does not support requested special purpose register -- `msr CPSR_fcxs,r9' +[^:]*:63: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfxc,r9' +[^:]*:64: Error: selected processor does not support requested special purpose register -- `msr CPSR_sfcx,r9' +[^:]*:65: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxfc,r9' +[^:]*:66: Error: selected processor does not support requested special purpose register -- `msr CPSR_sxcf,r9' +[^:]*:67: Error: selected processor does not support requested special purpose register -- `msr CPSR_scfx,r9' +[^:]*:68: Error: selected processor does not support requested special purpose register -- `msr CPSR_scxf,r9' +[^:]*:69: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfsc,r9' +[^:]*:70: Error: selected processor does not support requested special purpose register -- `msr CPSR_xfcs,r9' +[^:]*:71: Error: selected processor does not support requested special purpose register -- `msr CPSR_xsfc,r9' +[^:]*:72: Error: selected processor does not support requested special purpose register -- `msr CPSR_xscf,r9' +[^:]*:73: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcfs,r9' +[^:]*:74: Error: selected processor does not support requested special purpose register -- `msr CPSR_xcsf,r9' +[^:]*:75: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfsx,r9' +[^:]*:76: Error: selected processor does not support requested special purpose register -- `msr CPSR_cfxs,r9' +[^:]*:77: Error: selected processor does not support requested special purpose register -- `msr CPSR_csfx,r9' +[^:]*:78: Error: selected processor does not support requested special purpose register -- `msr CPSR_csxf,r9' +[^:]*:79: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxfs,r9' +[^:]*:80: Error: selected processor does not support requested special purpose register -- `msr CPSR_cxsf,r9' +[^:]*:83: Error: selected processor does not support requested special purpose register -- `msr SPSR,r9' +[^:]*:84: Error: selected processor does not support requested special purpose register -- `msr SPSR_s,r9' +[^:]*:85: Error: selected processor does not support requested special purpose register -- `msr SPSR_f,r9' +[^:]*:86: Error: selected processor does not support requested special purpose register -- `msr SPSR_c,r9' +[^:]*:87: Error: selected processor does not support requested special purpose register -- `msr SPSR_x,r9' +[^:]*:90: Error: selected processor does not support requested special purpose register -- `msr SPSR_fs,r9' +[^:]*:91: Error: selected processor does not support requested special purpose register -- `msr SPSR_fx,r9' +[^:]*:92: Error: selected processor does not support requested special purpose register -- `msr SPSR_fc,r9' +[^:]*:93: Error: selected processor does not support requested special purpose register -- `msr SPSR_sf,r9' +[^:]*:94: Error: selected processor does not support requested special purpose register -- `msr SPSR_sx,r9' +[^:]*:95: Error: selected processor does not support requested special purpose register -- `msr SPSR_sc,r9' +[^:]*:96: Error: selected processor does not support requested special purpose register -- `msr SPSR_xf,r9' +[^:]*:97: Error: selected processor does not support requested special purpose register -- `msr SPSR_xs,r9' +[^:]*:98: Error: selected processor does not support requested special purpose register -- `msr SPSR_xc,r9' +[^:]*:99: Error: selected processor does not support requested special purpose register -- `msr SPSR_cf,r9' +[^:]*:100: Error: selected processor does not support requested special purpose register -- `msr SPSR_cs,r9' +[^:]*:101: Error: selected processor does not support requested special purpose register -- `msr SPSR_cx,r9' +[^:]*:102: Error: selected processor does not support requested special purpose register -- `msr SPSR_fsx,r9' +[^:]*:103: Error: selected processor does not support requested special purpose register -- `msr SPSR_fsc,r9' +[^:]*:104: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxs,r9' +[^:]*:105: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxc,r9' +[^:]*:106: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcs,r9' +[^:]*:107: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcx,r9' +[^:]*:108: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfx,r9' +[^:]*:109: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfc,r9' +[^:]*:110: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxf,r9' +[^:]*:111: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxc,r9' +[^:]*:112: Error: selected processor does not support requested special purpose register -- `msr SPSR_scf,r9' +[^:]*:113: Error: selected processor does not support requested special purpose register -- `msr SPSR_scx,r9' +[^:]*:114: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfs,r9' +[^:]*:115: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfc,r9' +[^:]*:116: Error: selected processor does not support requested special purpose register -- `msr SPSR_xsf,r9' +[^:]*:117: Error: selected processor does not support requested special purpose register -- `msr SPSR_xsc,r9' +[^:]*:118: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcf,r9' +[^:]*:119: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcs,r9' +[^:]*:120: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfs,r9' +[^:]*:121: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfx,r9' +[^:]*:122: Error: selected processor does not support requested special purpose register -- `msr SPSR_csf,r9' +[^:]*:123: Error: selected processor does not support requested special purpose register -- `msr SPSR_csx,r9' +[^:]*:124: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxf,r9' +[^:]*:125: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxs,r9' +[^:]*:126: Error: selected processor does not support requested special purpose register -- `msr SPSR_fsxc,r9' +[^:]*:127: Error: selected processor does not support requested special purpose register -- `msr SPSR_fscx,r9' +[^:]*:128: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxsc,r9' +[^:]*:129: Error: selected processor does not support requested special purpose register -- `msr SPSR_fxcs,r9' +[^:]*:130: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcsx,r9' +[^:]*:131: Error: selected processor does not support requested special purpose register -- `msr SPSR_fcxs,r9' +[^:]*:132: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfxc,r9' +[^:]*:133: Error: selected processor does not support requested special purpose register -- `msr SPSR_sfcx,r9' +[^:]*:134: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxfc,r9' +[^:]*:135: Error: selected processor does not support requested special purpose register -- `msr SPSR_sxcf,r9' +[^:]*:136: Error: selected processor does not support requested special purpose register -- `msr SPSR_scfx,r9' +[^:]*:137: Error: selected processor does not support requested special purpose register -- `msr SPSR_scxf,r9' +[^:]*:138: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfsc,r9' +[^:]*:139: Error: selected processor does not support requested special purpose register -- `msr SPSR_xfcs,r9' +[^:]*:140: Error: selected processor does not support requested special purpose register -- `msr SPSR_xsfc,r9' +[^:]*:141: Error: selected processor does not support requested special purpose register -- `msr SPSR_xscf,r9' +[^:]*:142: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcfs,r9' +[^:]*:143: Error: selected processor does not support requested special purpose register -- `msr SPSR_xcsf,r9' +[^:]*:144: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfsx,r9' +[^:]*:145: Error: selected processor does not support requested special purpose register -- `msr SPSR_cfxs,r9' +[^:]*:146: Error: selected processor does not support requested special purpose register -- `msr SPSR_csfx,r9' +[^:]*:147: Error: selected processor does not support requested special purpose register -- `msr SPSR_csxf,r9' +[^:]*:148: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxfs,r9' +[^:]*:149: Error: selected processor does not support requested special purpose register -- `msr SPSR_cxsf,r9' diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-reg-thumb.d b/binutils-2.25/gas/testsuite/gas/arm/msr-reg-thumb.d new file mode 100644 index 00000000..39b12750 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-reg-thumb.d @@ -0,0 +1,144 @@ +# name: MSR register operands in thumb mode +# as: -march=armv7-a -mthumb +# source: msr-reg.s +# objdump: -dr --prefix-addresses --show-raw-insn +# warning: writing to APSR without specifying a bitmask is deprecated +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> f389 8800 msr CPSR_f, r9 +00000004 <[^>]*> f389 8400 msr CPSR_s, r9 +00000008 <[^>]*> f389 8800 msr CPSR_f, r9 +0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9 +00000010 <[^>]*> f389 8900 msr CPSR_fc, r9 +00000014 <[^>]*> f389 8400 msr CPSR_s, r9 +00000018 <[^>]*> f389 8800 msr CPSR_f, r9 +0000001c <[^>]*> f389 8100 msr CPSR_c, r9 +00000020 <[^>]*> f389 8200 msr CPSR_x, r9 +00000024 <[^>]*> f389 8c00 msr CPSR_fs, r9 +00000028 <[^>]*> f389 8a00 msr CPSR_fx, r9 +0000002c <[^>]*> f389 8900 msr CPSR_fc, r9 +00000030 <[^>]*> f389 8c00 msr CPSR_fs, r9 +00000034 <[^>]*> f389 8600 msr CPSR_sx, r9 +00000038 <[^>]*> f389 8500 msr CPSR_sc, r9 +0000003c <[^>]*> f389 8a00 msr CPSR_fx, r9 +00000040 <[^>]*> f389 8600 msr CPSR_sx, r9 +00000044 <[^>]*> f389 8300 msr CPSR_xc, r9 +00000048 <[^>]*> f389 8900 msr CPSR_fc, r9 +0000004c <[^>]*> f389 8500 msr CPSR_sc, r9 +00000050 <[^>]*> f389 8300 msr CPSR_xc, r9 +00000054 <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000058 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +0000005c <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000060 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +00000064 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +00000068 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +0000006c <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000070 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +00000074 <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000078 <[^>]*> f389 8700 msr CPSR_sxc, r9 +0000007c <[^>]*> f389 8d00 msr CPSR_fsc, r9 +00000080 <[^>]*> f389 8700 msr CPSR_sxc, r9 +00000084 <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000088 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +0000008c <[^>]*> f389 8e00 msr CPSR_fsx, r9 +00000090 <[^>]*> f389 8700 msr CPSR_sxc, r9 +00000094 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +00000098 <[^>]*> f389 8700 msr CPSR_sxc, r9 +0000009c <[^>]*> f389 8d00 msr CPSR_fsc, r9 +000000a0 <[^>]*> f389 8b00 msr CPSR_fxc, r9 +000000a4 <[^>]*> f389 8d00 msr CPSR_fsc, r9 +000000a8 <[^>]*> f389 8700 msr CPSR_sxc, r9 +000000ac <[^>]*> f389 8b00 msr CPSR_fxc, r9 +000000b0 <[^>]*> f389 8700 msr CPSR_sxc, r9 +000000b4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000b8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000bc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000c0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000c4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000c8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000cc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000d0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000d4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000d8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000dc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000e0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000e4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000e8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000ec <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000f0 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000f4 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000f8 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +000000fc <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000100 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000104 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000108 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +0000010c <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000110 <[^>]*> f389 8f00 msr CPSR_fsxc, r9 +00000114 <[^>]*> f399 8900 msr SPSR_fc, r9 +00000118 <[^>]*> f399 8400 msr SPSR_s, r9 +0000011c <[^>]*> f399 8800 msr SPSR_f, r9 +00000120 <[^>]*> f399 8100 msr SPSR_c, r9 +00000124 <[^>]*> f399 8200 msr SPSR_x, r9 +00000128 <[^>]*> f399 8c00 msr SPSR_fs, r9 +0000012c <[^>]*> f399 8a00 msr SPSR_fx, r9 +00000130 <[^>]*> f399 8900 msr SPSR_fc, r9 +00000134 <[^>]*> f399 8c00 msr SPSR_fs, r9 +00000138 <[^>]*> f399 8600 msr SPSR_sx, r9 +0000013c <[^>]*> f399 8500 msr SPSR_sc, r9 +00000140 <[^>]*> f399 8a00 msr SPSR_fx, r9 +00000144 <[^>]*> f399 8600 msr SPSR_sx, r9 +00000148 <[^>]*> f399 8300 msr SPSR_xc, r9 +0000014c <[^>]*> f399 8900 msr SPSR_fc, r9 +00000150 <[^>]*> f399 8500 msr SPSR_sc, r9 +00000154 <[^>]*> f399 8300 msr SPSR_xc, r9 +00000158 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +0000015c <[^>]*> f399 8d00 msr SPSR_fsc, r9 +00000160 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +00000164 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +00000168 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +0000016c <[^>]*> f399 8b00 msr SPSR_fxc, r9 +00000170 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +00000174 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +00000178 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +0000017c <[^>]*> f399 8700 msr SPSR_sxc, r9 +00000180 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +00000184 <[^>]*> f399 8700 msr SPSR_sxc, r9 +00000188 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +0000018c <[^>]*> f399 8b00 msr SPSR_fxc, r9 +00000190 <[^>]*> f399 8e00 msr SPSR_fsx, r9 +00000194 <[^>]*> f399 8700 msr SPSR_sxc, r9 +00000198 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +0000019c <[^>]*> f399 8700 msr SPSR_sxc, r9 +000001a0 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +000001a4 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +000001a8 <[^>]*> f399 8d00 msr SPSR_fsc, r9 +000001ac <[^>]*> f399 8700 msr SPSR_sxc, r9 +000001b0 <[^>]*> f399 8b00 msr SPSR_fxc, r9 +000001b4 <[^>]*> f399 8700 msr SPSR_sxc, r9 +000001b8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001bc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001c0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001c4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001c8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001cc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001d0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001d4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001d8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001dc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001e0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001e4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001e8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001ec <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001f0 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001f4 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001f8 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +000001fc <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000200 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000204 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000208 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +0000020c <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000210 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 +00000214 <[^>]*> f399 8f00 msr SPSR_fsxc, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-reg.d b/binutils-2.25/gas/testsuite/gas/arm/msr-reg.d new file mode 100644 index 00000000..3603f9c7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-reg.d @@ -0,0 +1,142 @@ +# name: MSR register operands +# as: -march=armv7-a +# objdump: -dr --prefix-addresses --show-raw-insn +# warning: writing to APSR without specifying a bitmask is deprecated + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <[^>]*> e128f009 msr CPSR_f, r9 +00000004 <[^>]*> e124f009 msr CPSR_s, r9 +00000008 <[^>]*> e128f009 msr CPSR_f, r9 +0000000c <[^>]*> e12cf009 msr CPSR_fs, r9 +00000010 <[^>]*> e129f009 msr CPSR_fc, r9 +00000014 <[^>]*> e124f009 msr CPSR_s, r9 +00000018 <[^>]*> e128f009 msr CPSR_f, r9 +0000001c <[^>]*> e121f009 msr CPSR_c, r9 +00000020 <[^>]*> e122f009 msr CPSR_x, r9 +00000024 <[^>]*> e12cf009 msr CPSR_fs, r9 +00000028 <[^>]*> e12af009 msr CPSR_fx, r9 +0000002c <[^>]*> e129f009 msr CPSR_fc, r9 +00000030 <[^>]*> e12cf009 msr CPSR_fs, r9 +00000034 <[^>]*> e126f009 msr CPSR_sx, r9 +00000038 <[^>]*> e125f009 msr CPSR_sc, r9 +0000003c <[^>]*> e12af009 msr CPSR_fx, r9 +00000040 <[^>]*> e126f009 msr CPSR_sx, r9 +00000044 <[^>]*> e123f009 msr CPSR_xc, r9 +00000048 <[^>]*> e129f009 msr CPSR_fc, r9 +0000004c <[^>]*> e125f009 msr CPSR_sc, r9 +00000050 <[^>]*> e123f009 msr CPSR_xc, r9 +00000054 <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000058 <[^>]*> e12df009 msr CPSR_fsc, r9 +0000005c <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000060 <[^>]*> e12bf009 msr CPSR_fxc, r9 +00000064 <[^>]*> e12df009 msr CPSR_fsc, r9 +00000068 <[^>]*> e12bf009 msr CPSR_fxc, r9 +0000006c <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000070 <[^>]*> e12df009 msr CPSR_fsc, r9 +00000074 <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000078 <[^>]*> e127f009 msr CPSR_sxc, r9 +0000007c <[^>]*> e12df009 msr CPSR_fsc, r9 +00000080 <[^>]*> e127f009 msr CPSR_sxc, r9 +00000084 <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000088 <[^>]*> e12bf009 msr CPSR_fxc, r9 +0000008c <[^>]*> e12ef009 msr CPSR_fsx, r9 +00000090 <[^>]*> e127f009 msr CPSR_sxc, r9 +00000094 <[^>]*> e12bf009 msr CPSR_fxc, r9 +00000098 <[^>]*> e127f009 msr CPSR_sxc, r9 +0000009c <[^>]*> e12df009 msr CPSR_fsc, r9 +000000a0 <[^>]*> e12bf009 msr CPSR_fxc, r9 +000000a4 <[^>]*> e12df009 msr CPSR_fsc, r9 +000000a8 <[^>]*> e127f009 msr CPSR_sxc, r9 +000000ac <[^>]*> e12bf009 msr CPSR_fxc, r9 +000000b0 <[^>]*> e127f009 msr CPSR_sxc, r9 +000000b4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000b8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000bc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000c0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000c4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000c8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000cc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000d0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000d4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000d8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000dc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000e0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000e4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000e8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000ec <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000f0 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000f4 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000f8 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +000000fc <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000100 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000104 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000108 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +0000010c <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000110 <[^>]*> e12ff009 msr CPSR_fsxc, r9 +00000114 <[^>]*> e169f009 msr SPSR_fc, r9 +00000118 <[^>]*> e164f009 msr SPSR_s, r9 +0000011c <[^>]*> e168f009 msr SPSR_f, r9 +00000120 <[^>]*> e161f009 msr SPSR_c, r9 +00000124 <[^>]*> e162f009 msr SPSR_x, r9 +00000128 <[^>]*> e16cf009 msr SPSR_fs, r9 +0000012c <[^>]*> e16af009 msr SPSR_fx, r9 +00000130 <[^>]*> e169f009 msr SPSR_fc, r9 +00000134 <[^>]*> e16cf009 msr SPSR_fs, r9 +00000138 <[^>]*> e166f009 msr SPSR_sx, r9 +0000013c <[^>]*> e165f009 msr SPSR_sc, r9 +00000140 <[^>]*> e16af009 msr SPSR_fx, r9 +00000144 <[^>]*> e166f009 msr SPSR_sx, r9 +00000148 <[^>]*> e163f009 msr SPSR_xc, r9 +0000014c <[^>]*> e169f009 msr SPSR_fc, r9 +00000150 <[^>]*> e165f009 msr SPSR_sc, r9 +00000154 <[^>]*> e163f009 msr SPSR_xc, r9 +00000158 <[^>]*> e16ef009 msr SPSR_fsx, r9 +0000015c <[^>]*> e16df009 msr SPSR_fsc, r9 +00000160 <[^>]*> e16ef009 msr SPSR_fsx, r9 +00000164 <[^>]*> e16bf009 msr SPSR_fxc, r9 +00000168 <[^>]*> e16df009 msr SPSR_fsc, r9 +0000016c <[^>]*> e16bf009 msr SPSR_fxc, r9 +00000170 <[^>]*> e16ef009 msr SPSR_fsx, r9 +00000174 <[^>]*> e16df009 msr SPSR_fsc, r9 +00000178 <[^>]*> e16ef009 msr SPSR_fsx, r9 +0000017c <[^>]*> e167f009 msr SPSR_sxc, r9 +00000180 <[^>]*> e16df009 msr SPSR_fsc, r9 +00000184 <[^>]*> e167f009 msr SPSR_sxc, r9 +00000188 <[^>]*> e16ef009 msr SPSR_fsx, r9 +0000018c <[^>]*> e16bf009 msr SPSR_fxc, r9 +00000190 <[^>]*> e16ef009 msr SPSR_fsx, r9 +00000194 <[^>]*> e167f009 msr SPSR_sxc, r9 +00000198 <[^>]*> e16bf009 msr SPSR_fxc, r9 +0000019c <[^>]*> e167f009 msr SPSR_sxc, r9 +000001a0 <[^>]*> e16df009 msr SPSR_fsc, r9 +000001a4 <[^>]*> e16bf009 msr SPSR_fxc, r9 +000001a8 <[^>]*> e16df009 msr SPSR_fsc, r9 +000001ac <[^>]*> e167f009 msr SPSR_sxc, r9 +000001b0 <[^>]*> e16bf009 msr SPSR_fxc, r9 +000001b4 <[^>]*> e167f009 msr SPSR_sxc, r9 +000001b8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001bc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001c0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001c4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001c8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001cc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001d0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001d4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001d8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001dc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001e0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001e4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001e8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001ec <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001f0 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001f4 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001f8 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +000001fc <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000200 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000204 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000208 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +0000020c <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000210 <[^>]*> e16ff009 msr SPSR_fsxc, r9 +00000214 <[^>]*> e16ff009 msr SPSR_fsxc, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/msr-reg.s b/binutils-2.25/gas/testsuite/gas/arm/msr-reg.s new file mode 100644 index 00000000..4f79b0e1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/msr-reg.s @@ -0,0 +1,149 @@ +@ Check MSR and MRS instruction operand syntax. +@ Also check for MSR/MRS acceptance in ARM/THUMB modes. + +.section .text +.syntax unified + + @ Write to Special Register from register + msr APSR,r9 @ deprecated usage. + msr APSR_g,r9 + msr APSR_nzcvq,r9 + msr APSR_nzcvqg,r9 + + @ Write to CPSR flags + msr CPSR,r9 + msr CPSR_s,r9 + msr CPSR_f,r9 + msr CPSR_c,r9 + msr CPSR_x,r9 + + @ Write to CPSR flag combos + msr CPSR_fs, r9 + msr CPSR_fx, r9 + msr CPSR_fc, r9 + msr CPSR_sf, r9 + msr CPSR_sx, r9 + msr CPSR_sc, r9 + msr CPSR_xf, r9 + msr CPSR_xs, r9 + msr CPSR_xc, r9 + msr CPSR_cf, r9 + msr CPSR_cs, r9 + msr CPSR_cx, r9 + msr CPSR_fsx, r9 + msr CPSR_fsc, r9 + msr CPSR_fxs, r9 + msr CPSR_fxc, r9 + msr CPSR_fcs, r9 + msr CPSR_fcx, r9 + msr CPSR_sfx, r9 + msr CPSR_sfc, r9 + msr CPSR_sxf, r9 + msr CPSR_sxc, r9 + msr CPSR_scf, r9 + msr CPSR_scx, r9 + msr CPSR_xfs, r9 + msr CPSR_xfc, r9 + msr CPSR_xsf, r9 + msr CPSR_xsc, r9 + msr CPSR_xcf, r9 + msr CPSR_xcs, r9 + msr CPSR_cfs, r9 + msr CPSR_cfx, r9 + msr CPSR_csf, r9 + msr CPSR_csx, r9 + msr CPSR_cxf, r9 + msr CPSR_cxs, r9 + msr CPSR_fsxc, r9 + msr CPSR_fscx, r9 + msr CPSR_fxsc, r9 + msr CPSR_fxcs, r9 + msr CPSR_fcsx, r9 + msr CPSR_fcxs, r9 + msr CPSR_sfxc, r9 + msr CPSR_sfcx, r9 + msr CPSR_sxfc, r9 + msr CPSR_sxcf, r9 + msr CPSR_scfx, r9 + msr CPSR_scxf, r9 + msr CPSR_xfsc, r9 + msr CPSR_xfcs, r9 + msr CPSR_xsfc, r9 + msr CPSR_xscf, r9 + msr CPSR_xcfs, r9 + msr CPSR_xcsf, r9 + msr CPSR_cfsx, r9 + msr CPSR_cfxs, r9 + msr CPSR_csfx, r9 + msr CPSR_csxf, r9 + msr CPSR_cxfs, r9 + msr CPSR_cxsf, r9 + + @ Write to SPSR flags + msr SPSR,r9 + msr SPSR_s,r9 + msr SPSR_f,r9 + msr SPSR_c,r9 + msr SPSR_x,r9 + + @ Write to Saved status register + msr SPSR_fs, r9 + msr SPSR_fx, r9 + msr SPSR_fc, r9 + msr SPSR_sf, r9 + msr SPSR_sx, r9 + msr SPSR_sc, r9 + msr SPSR_xf, r9 + msr SPSR_xs, r9 + msr SPSR_xc, r9 + msr SPSR_cf, r9 + msr SPSR_cs, r9 + msr SPSR_cx, r9 + msr SPSR_fsx, r9 + msr SPSR_fsc, r9 + msr SPSR_fxs, r9 + msr SPSR_fxc, r9 + msr SPSR_fcs, r9 + msr SPSR_fcx, r9 + msr SPSR_sfx, r9 + msr SPSR_sfc, r9 + msr SPSR_sxf, r9 + msr SPSR_sxc, r9 + msr SPSR_scf, r9 + msr SPSR_scx, r9 + msr SPSR_xfs, r9 + msr SPSR_xfc, r9 + msr SPSR_xsf, r9 + msr SPSR_xsc, r9 + msr SPSR_xcf, r9 + msr SPSR_xcs, r9 + msr SPSR_cfs, r9 + msr SPSR_cfx, r9 + msr SPSR_csf, r9 + msr SPSR_csx, r9 + msr SPSR_cxf, r9 + msr SPSR_cxs, r9 + msr SPSR_fsxc, r9 + msr SPSR_fscx, r9 + msr SPSR_fxsc, r9 + msr SPSR_fxcs, r9 + msr SPSR_fcsx, r9 + msr SPSR_fcxs, r9 + msr SPSR_sfxc, r9 + msr SPSR_sfcx, r9 + msr SPSR_sxfc, r9 + msr SPSR_sxcf, r9 + msr SPSR_scfx, r9 + msr SPSR_scxf, r9 + msr SPSR_xfsc, r9 + msr SPSR_xfcs, r9 + msr SPSR_xsfc, r9 + msr SPSR_xscf, r9 + msr SPSR_xcfs, r9 + msr SPSR_xcsf, r9 + msr SPSR_cfsx, r9 + msr SPSR_cfxs, r9 + msr SPSR_csfx, r9 + msr SPSR_csxf, r9 + msr SPSR_cxfs, r9 + msr SPSR_cxsf, r9 diff --git a/binutils-2.25/gas/testsuite/gas/arm/mul-overlap-v6.d b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap-v6.d new file mode 100644 index 00000000..ff42190a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap-v6.d @@ -0,0 +1,10 @@ +# name: Overlapping multiplication operands for ARMv6 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> e0000090 mul r0, r0, r0 +0[0-9a-f]+ <[^>]+> e0202190 mla r0, r0, r1, r2 +0[0-9a-f]+ <[^>]+> e0602190 mls r0, r0, r1, r2 +0[0-9a-f]+ <[^>]+> e12fff1e bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/mul-overlap-v6.s b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap-v6.s new file mode 100644 index 00000000..f35c124a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap-v6.s @@ -0,0 +1,9 @@ + .arch armv6t2 + .text + .align 2 + .global foo +foo: + mul r0, r0, r0 + mla r0, r0, r1, r2 + mls r0, r0, r1, r2 + bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.d b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.d new file mode 100644 index 00000000..53406e3f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.d @@ -0,0 +1,2 @@ +# name: Overlapping multiplication operands without architecture specification +# error-output: mul-overlap.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.l b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.l new file mode 100644 index 00000000..cd0ae674 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +[^:]*:5: Rd and Rm should be different in mul +[^:]*:6: Rd and Rm should be different in mla +[^:]*:8: rdhi, rdlo and rm must all be different diff --git a/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.s b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.s new file mode 100644 index 00000000..b35fb512 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/mul-overlap.s @@ -0,0 +1,10 @@ + .text + .align 2 + .global foo +foo: + mul r0, r0, r0 + mla r0, r0, r1, r2 + mls r0, r0, r1, r2 + umull r0, r1, r0, r1 + smlalbb r0, r1, r0, r1 + bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.d b/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.d new file mode 100644 index 00000000..3e27426d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.d @@ -0,0 +1,3 @@ +# name: Bad operand in Advanced SIMD Neon instructions +# as: -mfpu=neon +# error-output: neon-addressing-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.l b/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.l new file mode 100644 index 00000000..38e18013 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.l @@ -0,0 +1,27 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: r15 not allowed here -- `vld1.8 {d0},1f' +[^:]*:5: Error: r15 not allowed here -- `vld1.8 {D0},R0' +[^:]*:6: Error: r15 not allowed here -- `vld1.8 {Q1},R0' +[^:]*:7: Error: r15 not allowed here -- `vld1.8 {D0},\[PC\]' +[^:]*:8: Error: r15 not allowed here -- `vld1.8 {D0},\[PC,#0\]' +[^:]*:9: Error: r15 not allowed here -- `vst1.8 {D0},R0' +[^:]*:10: Error: r15 not allowed here -- `vst1.8 {Q1},R0' +[^:]*:11: Error: r15 not allowed here -- `vst1.8 {D0},\[PC\]' +[^:]*:12: Error: r15 not allowed here -- `vst1.8 {D0},\[PC,#0\]' +[^:]*:13: Error: only loads support such operands -- `vst1.8 {D0\[\].* +[^:]*:14: Error: only loads support such operands -- `vst2.8 {D0\[\].* +[^:]*:15: Error: only loads support such operands -- `vst3.16 {D0\[\].* +[^:]*:16: Error: only loads support such operands -- `vst4.32 {D0\[\].* +[^:]*:17: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,#8\]' +[^:]*:18: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,#8\]!' +[^:]*:19: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,R1\]' +[^:]*:20: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,R1\]!' +[^:]*:22: Error: r15 not allowed here -- `vld1.8 {d0},2f' +[^:]*:24: Error: r15 not allowed here -- `vld1.8 {D0},R0' +[^:]*:25: Error: r15 not allowed here -- `vld1.8 {Q1},R0' +[^:]*:26: Error: r15 not allowed here -- `vld1.8 {D0},\[PC\]' +[^:]*:27: Error: r15 not allowed here -- `vld1.8 {D0},\[PC,#0\]' +[^:]*:28: Error: r15 not allowed here -- `vst1.8 {D0},R0' +[^:]*:29: Error: r15 not allowed here -- `vst1.8 {Q1},R0' +[^:]*:30: Error: r15 not allowed here -- `vst1.8 {D0},\[PC\]' +[^:]*:31: Error: r15 not allowed here -- `vst1.8 {D0},\[PC,#0\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.s b/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.s new file mode 100644 index 00000000..6f7e7691 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-addressing-bad.s @@ -0,0 +1,31 @@ +.syntax unified + +VLD1.8 {d0}, 1f +1: +VLD1.8 {D0}, R0 +VLD1.8 {Q1}, R0 +VLD1.8 {D0}, [PC] +VLD1.8 {D0}, [PC, #0] +VST1.8 {D0}, R0 +VST1.8 {Q1}, R0 +VST1.8 {D0}, [PC] +VST1.8 {D0}, [PC, #0] +VST1.8 {D0[]}, [R0] +VST2.8 {D0[], D2[]}, [R0] +VST3.16 {D0[], D1[], D2[]}, [R0] +VST4.32 {D0[], D1[], D2[], D3[]}, [R0] +VLD1.8 {Q0}, [R0, #8] +VLD1.8 {Q0}, [R0, #8]! +VLD1.8 {Q0}, [R0, R1] +VLD1.8 {Q0}, [R0, R1]! +.thumb +VLD1.8 {d0}, 2f +2: +VLD1.8 {D0}, R0 +VLD1.8 {Q1}, R0 +VLD1.8 {D0}, [PC] +VLD1.8 {D0}, [PC, #0] +VST1.8 {D0}, R0 +VST1.8 {Q1}, R0 +VST1.8 {D0}, [PC] +VST1.8 {D0}, [PC, #0] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad-inc.s b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad-inc.s new file mode 100644 index 00000000..2f56773d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad-inc.s @@ -0,0 +1,57 @@ +# Check for illegal conditional Neon instructions in ARM mode. The instructions +# which overlap with VFP are the tricky cases, so test those. + .include "itblock.s" + .syntax unified + .arch armv7-a + .fpu neon + .text +func: + itblock 4 eq + vmoveq q0,q1 + vmoveq d0,d1 + vmoveq.i32 q0,#0 + vmoveq.i32 d0,#0 + @ Following four *can* be conditional. + itblock 4 eq + vmoveq.32 d0[1], r2 + vmoveq d0,r1,r2 + vmoveq.32 r2,d1[0] + vmoveq r0,r1,d2 + + .macro dyadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1,d2 + \op\eq\f32 q0,q1,q2 + .endm + + dyadic_eq vmul + dyadic_eq vmla + dyadic_eq vmls + dyadic_eq vadd + dyadic_eq vsub + + .macro monadic_eq op eq="eq" f32=".f32" + itblock 2 eq + \op\eq\f32 d0,d1 + \op\eq\f32 q0,q1 + .endm + + monadic_eq vabs + monadic_eq vneg + + .macro cvt to from dot="." + itblock 2 eq + vcvteq\dot\to\dot\from d0,d1 + vcvteq\dot\to\dot\from q0,q1 + .endm + + cvt s32 f32 + cvt u32 f32 + cvt f32 s32 + cvt f32 u32 + + itblock 4 eq + vdupeq.32 d0,r1 + vdupeq.32 q0,r1 + vdupeq.32 d0,d1[0] + vdupeq.32 q0,d1[1] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.d b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.d new file mode 100644 index 00000000..105ba4d7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.d @@ -0,0 +1,3 @@ +# name: Illegal conditions in Neon instructions, ARM mode +# as: -mfpu=neon -I$srcdir/$subdir +# error-output: neon-cond-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.l b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.l new file mode 100644 index 00000000..a79f79d6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.l @@ -0,0 +1,29 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: instruction cannot be conditional -- `vmoveq q0,q1' +[^:]*:11: Error: instruction cannot be conditional -- `vmoveq d0,d1' +[^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0' +[^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 d0,d1,d2' +[^:]*:27: Error: instruction cannot be conditional -- `vmuleq\.f32 q0,q1,q2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 d0,d1,d2' +[^:]*:28: Error: instruction cannot be conditional -- `vmlaeq\.f32 q0,q1,q2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 d0,d1,d2' +[^:]*:29: Error: instruction cannot be conditional -- `vmlseq\.f32 q0,q1,q2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 d0,d1,d2' +[^:]*:30: Error: instruction cannot be conditional -- `vaddeq\.f32 q0,q1,q2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 d0,d1,d2' +[^:]*:31: Error: instruction cannot be conditional -- `vsubeq\.f32 q0,q1,q2' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 d0,d1' +[^:]*:39: Error: instruction cannot be conditional -- `vabseq\.f32 q0,q1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 d0,d1' +[^:]*:40: Error: instruction cannot be conditional -- `vnegeq\.f32 q0,q1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 d0,d1' +[^:]*:48: Error: instruction cannot be conditional -- `vcvteq\.s32\.f32 q0,q1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 d0,d1' +[^:]*:49: Error: instruction cannot be conditional -- `vcvteq\.u32\.f32 q0,q1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 d0,d1' +[^:]*:50: Error: instruction cannot be conditional -- `vcvteq\.f32\.s32 q0,q1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 d0,d1' +[^:]*:51: Error: instruction cannot be conditional -- `vcvteq\.f32\.u32 q0,q1' +[^:]*:56: Error: instruction cannot be conditional -- `vdupeq\.32 d0,d1\[0\]' +[^:]*:57: Error: instruction cannot be conditional -- `vdupeq\.32 q0,d1\[1\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.s b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.s new file mode 100644 index 00000000..16afd863 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad.s @@ -0,0 +1,2 @@ + .arm + .include "neon-cond-bad-inc.s" diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad_t2.d b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad_t2.d new file mode 100644 index 00000000..517caa75 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad_t2.d @@ -0,0 +1,55 @@ +# name: Conditions in Neon instructions, Thumb mode (illegal in ARM). +# as: -mfpu=neon -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ef22 0152 vorreq q0, q1, q1 +0[0-9a-f]+ <[^>]+> ef21 0111 vorreq d0, d1, d1 +0[0-9a-f]+ <[^>]+> ef80 0050 vmoveq\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> ef80 0010 vmoveq\.i32 d0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee20 2b10 vmoveq\.32 d0\[1\], r2 +0[0-9a-f]+ <[^>]+> ec42 1b10 vmoveq d0, r1, r2 +0[0-9a-f]+ <[^>]+> ee11 2b10 vmoveq\.32 r2, d1\[0\] +0[0-9a-f]+ <[^>]+> ec51 0b12 vmoveq r0, r1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ff01 0d12 vmuleq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ff02 0d54 vmuleq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d12 vmlaeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d54 vmlaeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d12 vmlseq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d54 vmlseq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef01 0d02 vaddeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef02 0d44 vaddeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ef21 0d02 vsubeq\.f32 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ef22 0d44 vsubeq\.f32 q0, q1, q2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0701 vabseq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 0742 vabseq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffb9 0781 vnegeq\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffb9 07c2 vnegeq\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0701 vcvteq\.s32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0742 vcvteq\.s32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0781 vcvteq\.u32\.f32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 07c2 vcvteq\.u32\.f32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0601 vcvteq\.f32\.s32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 0642 vcvteq\.f32\.s32 q0, q1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ffbb 0681 vcvteq\.f32\.u32 d0, d1 +0[0-9a-f]+ <[^>]+> ffbb 06c2 vcvteq\.f32\.u32 q0, q1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee80 1b10 vdupeq\.32 d0, r1 +0[0-9a-f]+ <[^>]+> eea0 1b10 vdupeq\.32 q0, r1 +0[0-9a-f]+ <[^>]+> ffb4 0c01 vdupeq\.32 d0, d1\[0\] +0[0-9a-f]+ <[^>]+> ffbc 0c41 vdupeq\.32 q0, d1\[1\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad_t2.s b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad_t2.s new file mode 100644 index 00000000..2655d11a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond-bad_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "neon-cond-bad-inc.s" diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond.d b/binutils-2.25/gas/testsuite/gas/arm/neon-cond.d new file mode 100644 index 00000000..0b7d8ede --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond.d @@ -0,0 +1,14 @@ +# name: Conditional Neon instructions +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> 0d943b00 vldreq d3, \[r4\] +0[0-9a-f]+ <[^>]+> be035b70 vmovlt\.16 d3\[1\], r5 +0[0-9a-f]+ <[^>]+> ac474b13 vmovge d3, r4, r7 +0[0-9a-f]+ <[^>]+> 3c543b3e vmovcc r3, r4, d30 +0[0-9a-f]+ <[^>]+> 1e223b10 vmovne\.32 d2\[1\], r3 +0[0-9a-f]+ <[^>]+> 2c521b13 vmovcs r1, r2, d3 +0[0-9a-f]+ <[^>]+> 3c421b14 vmovcc d4, r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cond.s b/binutils-2.25/gas/testsuite/gas/arm/neon-cond.s new file mode 100644 index 00000000..8f62575a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cond.s @@ -0,0 +1,13 @@ +@ test conditional compilation + + .arm + .text + .syntax unified + + vldreq.32 d3,[r4] + vmovlt.16 d3[1], r5 + vmovge d3, r4, r7 + vmovcc r3, r4, d30 + vmovne.32 d2[1],r3 + vmovcs r1,r2,d3 + vmovcc d4,r1,r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-const.d b/binutils-2.25/gas/testsuite/gas/arm/neon-const.d new file mode 100644 index 00000000..6c46930b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-const.d @@ -0,0 +1,266 @@ +# name: Neon floating-point constants +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2800050 vmov\.i32 q0, #0 ; 0x00000000 +0[0-9a-f]+ <[^>]+> f2800f50 vmov\.f32 q0, #2 ; 0x40000000 +0[0-9a-f]+ <[^>]+> f2810f50 vmov\.f32 q0, #4 ; 0x40800000 +0[0-9a-f]+ <[^>]+> f2820f50 vmov\.f32 q0, #8 ; 0x41000000 +0[0-9a-f]+ <[^>]+> f2830f50 vmov\.f32 q0, #16 ; 0x41800000 +0[0-9a-f]+ <[^>]+> f2840f50 vmov\.f32 q0, #0\.125 ; 0x3e000000 +0[0-9a-f]+ <[^>]+> f2850f50 vmov\.f32 q0, #0\.25 ; 0x3e800000 +0[0-9a-f]+ <[^>]+> f2860f50 vmov\.f32 q0, #0\.5 ; 0x3f000000 +0[0-9a-f]+ <[^>]+> f2870f50 vmov\.f32 q0, #1 ; 0x3f800000 +0[0-9a-f]+ <[^>]+> f2800f51 vmov\.f32 q0, #2\.125 ; 0x40080000 +0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f2820f51 vmov\.f32 q0, #8\.5 ; 0x41080000 +0[0-9a-f]+ <[^>]+> f2830f51 vmov\.f32 q0, #17 ; 0x41880000 +0[0-9a-f]+ <[^>]+> f2840f51 vmov\.f32 q0, #0\.1328125 ; 0x3e080000 +0[0-9a-f]+ <[^>]+> f2850f51 vmov\.f32 q0, #0\.265625 ; 0x3e880000 +0[0-9a-f]+ <[^>]+> f2860f51 vmov\.f32 q0, #0\.53125 ; 0x3f080000 +0[0-9a-f]+ <[^>]+> f2870f51 vmov\.f32 q0, #1\.0625 ; 0x3f880000 +0[0-9a-f]+ <[^>]+> f2800f52 vmov\.f32 q0, #2\.25 ; 0x40100000 +0[0-9a-f]+ <[^>]+> f2810f52 vmov\.f32 q0, #4\.5 ; 0x40900000 +0[0-9a-f]+ <[^>]+> f2820f52 vmov\.f32 q0, #9 ; 0x41100000 +0[0-9a-f]+ <[^>]+> f2830f52 vmov\.f32 q0, #18 ; 0x41900000 +0[0-9a-f]+ <[^>]+> f2840f52 vmov\.f32 q0, #0\.140625 ; 0x3e100000 +0[0-9a-f]+ <[^>]+> f2850f52 vmov\.f32 q0, #0\.28125 ; 0x3e900000 +0[0-9a-f]+ <[^>]+> f2860f52 vmov\.f32 q0, #0\.5625 ; 0x3f100000 +0[0-9a-f]+ <[^>]+> f2870f52 vmov\.f32 q0, #1\.125 ; 0x3f900000 +0[0-9a-f]+ <[^>]+> f2800f53 vmov\.f32 q0, #2\.375 ; 0x40180000 +0[0-9a-f]+ <[^>]+> f2810f53 vmov\.f32 q0, #4\.75 ; 0x40980000 +0[0-9a-f]+ <[^>]+> f2820f53 vmov\.f32 q0, #9\.5 ; 0x41180000 +0[0-9a-f]+ <[^>]+> f2830f53 vmov\.f32 q0, #19 ; 0x41980000 +0[0-9a-f]+ <[^>]+> f2840f53 vmov\.f32 q0, #0\.1484375 ; 0x3e180000 +0[0-9a-f]+ <[^>]+> f2850f53 vmov\.f32 q0, #0\.296875 ; 0x3e980000 +0[0-9a-f]+ <[^>]+> f2860f53 vmov\.f32 q0, #0\.59375 ; 0x3f180000 +0[0-9a-f]+ <[^>]+> f2870f53 vmov\.f32 q0, #1\.1875 ; 0x3f980000 +0[0-9a-f]+ <[^>]+> f2800f54 vmov\.f32 q0, #2\.5 ; 0x40200000 +0[0-9a-f]+ <[^>]+> f2810f54 vmov\.f32 q0, #5 ; 0x40a00000 +0[0-9a-f]+ <[^>]+> f2820f54 vmov\.f32 q0, #10 ; 0x41200000 +0[0-9a-f]+ <[^>]+> f2830f54 vmov\.f32 q0, #20 ; 0x41a00000 +0[0-9a-f]+ <[^>]+> f2840f54 vmov\.f32 q0, #0\.15625 ; 0x3e200000 +0[0-9a-f]+ <[^>]+> f2850f54 vmov\.f32 q0, #0\.3125 ; 0x3ea00000 +0[0-9a-f]+ <[^>]+> f2860f54 vmov\.f32 q0, #0\.625 ; 0x3f200000 +0[0-9a-f]+ <[^>]+> f2870f54 vmov\.f32 q0, #1\.25 ; 0x3fa00000 +0[0-9a-f]+ <[^>]+> f2800f55 vmov\.f32 q0, #2\.625 ; 0x40280000 +0[0-9a-f]+ <[^>]+> f2810f55 vmov\.f32 q0, #5\.25 ; 0x40a80000 +0[0-9a-f]+ <[^>]+> f2820f55 vmov\.f32 q0, #10\.5 ; 0x41280000 +0[0-9a-f]+ <[^>]+> f2830f55 vmov\.f32 q0, #21 ; 0x41a80000 +0[0-9a-f]+ <[^>]+> f2840f55 vmov\.f32 q0, #0\.1640625 ; 0x3e280000 +0[0-9a-f]+ <[^>]+> f2850f55 vmov\.f32 q0, #0\.328125 ; 0x3ea80000 +0[0-9a-f]+ <[^>]+> f2860f55 vmov\.f32 q0, #0\.65625 ; 0x3f280000 +0[0-9a-f]+ <[^>]+> f2870f55 vmov\.f32 q0, #1\.3125 ; 0x3fa80000 +0[0-9a-f]+ <[^>]+> f2800f56 vmov\.f32 q0, #2\.75 ; 0x40300000 +0[0-9a-f]+ <[^>]+> f2810f56 vmov\.f32 q0, #5\.5 ; 0x40b00000 +0[0-9a-f]+ <[^>]+> f2820f56 vmov\.f32 q0, #11 ; 0x41300000 +0[0-9a-f]+ <[^>]+> f2830f56 vmov\.f32 q0, #22 ; 0x41b00000 +0[0-9a-f]+ <[^>]+> f2840f56 vmov\.f32 q0, #0\.171875 ; 0x3e300000 +0[0-9a-f]+ <[^>]+> f2850f56 vmov\.f32 q0, #0\.34375 ; 0x3eb00000 +0[0-9a-f]+ <[^>]+> f2860f56 vmov\.f32 q0, #0\.6875 ; 0x3f300000 +0[0-9a-f]+ <[^>]+> f2870f56 vmov\.f32 q0, #1\.375 ; 0x3fb00000 +0[0-9a-f]+ <[^>]+> f2800f57 vmov\.f32 q0, #2\.875 ; 0x40380000 +0[0-9a-f]+ <[^>]+> f2810f57 vmov\.f32 q0, #5\.75 ; 0x40b80000 +0[0-9a-f]+ <[^>]+> f2820f57 vmov\.f32 q0, #11\.5 ; 0x41380000 +0[0-9a-f]+ <[^>]+> f2830f57 vmov\.f32 q0, #23 ; 0x41b80000 +0[0-9a-f]+ <[^>]+> f2840f57 vmov\.f32 q0, #0\.1796875 ; 0x3e380000 +0[0-9a-f]+ <[^>]+> f2850f57 vmov\.f32 q0, #0\.359375 ; 0x3eb80000 +0[0-9a-f]+ <[^>]+> f2860f57 vmov\.f32 q0, #0\.71875 ; 0x3f380000 +0[0-9a-f]+ <[^>]+> f2870f57 vmov\.f32 q0, #1\.4375 ; 0x3fb80000 +0[0-9a-f]+ <[^>]+> f2800f58 vmov\.f32 q0, #3 ; 0x40400000 +0[0-9a-f]+ <[^>]+> f2810f58 vmov\.f32 q0, #6 ; 0x40c00000 +0[0-9a-f]+ <[^>]+> f2820f58 vmov\.f32 q0, #12 ; 0x41400000 +0[0-9a-f]+ <[^>]+> f2830f58 vmov\.f32 q0, #24 ; 0x41c00000 +0[0-9a-f]+ <[^>]+> f2840f58 vmov\.f32 q0, #0\.1875 ; 0x3e400000 +0[0-9a-f]+ <[^>]+> f2850f58 vmov\.f32 q0, #0\.375 ; 0x3ec00000 +0[0-9a-f]+ <[^>]+> f2860f58 vmov\.f32 q0, #0\.75 ; 0x3f400000 +0[0-9a-f]+ <[^>]+> f2870f58 vmov\.f32 q0, #1\.5 ; 0x3fc00000 +0[0-9a-f]+ <[^>]+> f2800f59 vmov\.f32 q0, #3\.125 ; 0x40480000 +0[0-9a-f]+ <[^>]+> f2810f59 vmov\.f32 q0, #6\.25 ; 0x40c80000 +0[0-9a-f]+ <[^>]+> f2820f59 vmov\.f32 q0, #12\.5 ; 0x41480000 +0[0-9a-f]+ <[^>]+> f2830f59 vmov\.f32 q0, #25 ; 0x41c80000 +0[0-9a-f]+ <[^>]+> f2840f59 vmov\.f32 q0, #0\.1953125 ; 0x3e480000 +0[0-9a-f]+ <[^>]+> f2850f59 vmov\.f32 q0, #0\.390625 ; 0x3ec80000 +0[0-9a-f]+ <[^>]+> f2860f59 vmov\.f32 q0, #0\.78125 ; 0x3f480000 +0[0-9a-f]+ <[^>]+> f2870f59 vmov\.f32 q0, #1\.5625 ; 0x3fc80000 +0[0-9a-f]+ <[^>]+> f2800f5a vmov\.f32 q0, #3\.25 ; 0x40500000 +0[0-9a-f]+ <[^>]+> f2810f5a vmov\.f32 q0, #6\.5 ; 0x40d00000 +0[0-9a-f]+ <[^>]+> f2820f5a vmov\.f32 q0, #13 ; 0x41500000 +0[0-9a-f]+ <[^>]+> f2830f5a vmov\.f32 q0, #26 ; 0x41d00000 +0[0-9a-f]+ <[^>]+> f2840f5a vmov\.f32 q0, #0\.203125 ; 0x3e500000 +0[0-9a-f]+ <[^>]+> f2850f5a vmov\.f32 q0, #0\.40625 ; 0x3ed00000 +0[0-9a-f]+ <[^>]+> f2860f5a vmov\.f32 q0, #0\.8125 ; 0x3f500000 +0[0-9a-f]+ <[^>]+> f2870f5a vmov\.f32 q0, #1\.625 ; 0x3fd00000 +0[0-9a-f]+ <[^>]+> f2800f5b vmov\.f32 q0, #3\.375 ; 0x40580000 +0[0-9a-f]+ <[^>]+> f2810f5b vmov\.f32 q0, #6\.75 ; 0x40d80000 +0[0-9a-f]+ <[^>]+> f2820f5b vmov\.f32 q0, #13\.5 ; 0x41580000 +0[0-9a-f]+ <[^>]+> f2830f5b vmov\.f32 q0, #27 ; 0x41d80000 +0[0-9a-f]+ <[^>]+> f2840f5b vmov\.f32 q0, #0\.2109375 ; 0x3e580000 +0[0-9a-f]+ <[^>]+> f2850f5b vmov\.f32 q0, #0\.421875 ; 0x3ed80000 +0[0-9a-f]+ <[^>]+> f2860f5b vmov\.f32 q0, #0\.84375 ; 0x3f580000 +0[0-9a-f]+ <[^>]+> f2870f5b vmov\.f32 q0, #1\.6875 ; 0x3fd80000 +0[0-9a-f]+ <[^>]+> f2800f5c vmov\.f32 q0, #3\.5 ; 0x40600000 +0[0-9a-f]+ <[^>]+> f2810f5c vmov\.f32 q0, #7 ; 0x40e00000 +0[0-9a-f]+ <[^>]+> f2820f5c vmov\.f32 q0, #14 ; 0x41600000 +0[0-9a-f]+ <[^>]+> f2830f5c vmov\.f32 q0, #28 ; 0x41e00000 +0[0-9a-f]+ <[^>]+> f2840f5c vmov\.f32 q0, #0\.21875 ; 0x3e600000 +0[0-9a-f]+ <[^>]+> f2850f5c vmov\.f32 q0, #0\.4375 ; 0x3ee00000 +0[0-9a-f]+ <[^>]+> f2860f5c vmov\.f32 q0, #0\.875 ; 0x3f600000 +0[0-9a-f]+ <[^>]+> f2870f5c vmov\.f32 q0, #1\.75 ; 0x3fe00000 +0[0-9a-f]+ <[^>]+> f2800f5d vmov\.f32 q0, #3\.625 ; 0x40680000 +0[0-9a-f]+ <[^>]+> f2810f5d vmov\.f32 q0, #7\.25 ; 0x40e80000 +0[0-9a-f]+ <[^>]+> f2820f5d vmov\.f32 q0, #14\.5 ; 0x41680000 +0[0-9a-f]+ <[^>]+> f2830f5d vmov\.f32 q0, #29 ; 0x41e80000 +0[0-9a-f]+ <[^>]+> f2840f5d vmov\.f32 q0, #0\.2265625 ; 0x3e680000 +0[0-9a-f]+ <[^>]+> f2850f5d vmov\.f32 q0, #0\.453125 ; 0x3ee80000 +0[0-9a-f]+ <[^>]+> f2860f5d vmov\.f32 q0, #0\.90625 ; 0x3f680000 +0[0-9a-f]+ <[^>]+> f2870f5d vmov\.f32 q0, #1\.8125 ; 0x3fe80000 +0[0-9a-f]+ <[^>]+> f2800f5e vmov\.f32 q0, #3\.75 ; 0x40700000 +0[0-9a-f]+ <[^>]+> f2810f5e vmov\.f32 q0, #7\.5 ; 0x40f00000 +0[0-9a-f]+ <[^>]+> f2820f5e vmov\.f32 q0, #15 ; 0x41700000 +0[0-9a-f]+ <[^>]+> f2830f5e vmov\.f32 q0, #30 ; 0x41f00000 +0[0-9a-f]+ <[^>]+> f2840f5e vmov\.f32 q0, #0\.234375 ; 0x3e700000 +0[0-9a-f]+ <[^>]+> f2850f5e vmov\.f32 q0, #0\.46875 ; 0x3ef00000 +0[0-9a-f]+ <[^>]+> f2860f5e vmov\.f32 q0, #0\.9375 ; 0x3f700000 +0[0-9a-f]+ <[^>]+> f2870f5e vmov\.f32 q0, #1\.875 ; 0x3ff00000 +0[0-9a-f]+ <[^>]+> f2800f5f vmov\.f32 q0, #3\.875 ; 0x40780000 +0[0-9a-f]+ <[^>]+> f2810f5f vmov\.f32 q0, #7\.75 ; 0x40f80000 +0[0-9a-f]+ <[^>]+> f2820f5f vmov\.f32 q0, #15\.5 ; 0x41780000 +0[0-9a-f]+ <[^>]+> f2830f5f vmov\.f32 q0, #31 ; 0x41f80000 +0[0-9a-f]+ <[^>]+> f2840f5f vmov\.f32 q0, #0\.2421875 ; 0x3e780000 +0[0-9a-f]+ <[^>]+> f2850f5f vmov\.f32 q0, #0\.484375 ; 0x3ef80000 +0[0-9a-f]+ <[^>]+> f2860f5f vmov\.f32 q0, #0\.96875 ; 0x3f780000 +0[0-9a-f]+ <[^>]+> f2870f5f vmov\.f32 q0, #1\.9375 ; 0x3ff80000 +0[0-9a-f]+ <[^>]+> f3800650 vmov\.i32 q0, #-2147483648 ; 0x80000000 +0[0-9a-f]+ <[^>]+> f3800f50 vmov\.f32 q0, #-2 ; 0xc0000000 +0[0-9a-f]+ <[^>]+> f3810f50 vmov\.f32 q0, #-4 ; 0xc0800000 +0[0-9a-f]+ <[^>]+> f3820f50 vmov\.f32 q0, #-8 ; 0xc1000000 +0[0-9a-f]+ <[^>]+> f3830f50 vmov\.f32 q0, #-16 ; 0xc1800000 +0[0-9a-f]+ <[^>]+> f3840f50 vmov\.f32 q0, #-0\.125 ; 0xbe000000 +0[0-9a-f]+ <[^>]+> f3850f50 vmov\.f32 q0, #-0\.25 ; 0xbe800000 +0[0-9a-f]+ <[^>]+> f3860f50 vmov\.f32 q0, #-0\.5 ; 0xbf000000 +0[0-9a-f]+ <[^>]+> f3870f50 vmov\.f32 q0, #-1 ; 0xbf800000 +0[0-9a-f]+ <[^>]+> f3800f51 vmov\.f32 q0, #-2\.125 ; 0xc0080000 +0[0-9a-f]+ <[^>]+> f3810f51 vmov\.f32 q0, #-4\.25 ; 0xc0880000 +0[0-9a-f]+ <[^>]+> f3820f51 vmov\.f32 q0, #-8\.5 ; 0xc1080000 +0[0-9a-f]+ <[^>]+> f3830f51 vmov\.f32 q0, #-17 ; 0xc1880000 +0[0-9a-f]+ <[^>]+> f3840f51 vmov\.f32 q0, #-0\.1328125 ; 0xbe080000 +0[0-9a-f]+ <[^>]+> f3850f51 vmov\.f32 q0, #-0\.265625 ; 0xbe880000 +0[0-9a-f]+ <[^>]+> f3860f51 vmov\.f32 q0, #-0\.53125 ; 0xbf080000 +0[0-9a-f]+ <[^>]+> f3870f51 vmov\.f32 q0, #-1\.0625 ; 0xbf880000 +0[0-9a-f]+ <[^>]+> f3800f52 vmov\.f32 q0, #-2\.25 ; 0xc0100000 +0[0-9a-f]+ <[^>]+> f3810f52 vmov\.f32 q0, #-4\.5 ; 0xc0900000 +0[0-9a-f]+ <[^>]+> f3820f52 vmov\.f32 q0, #-9 ; 0xc1100000 +0[0-9a-f]+ <[^>]+> f3830f52 vmov\.f32 q0, #-18 ; 0xc1900000 +0[0-9a-f]+ <[^>]+> f3840f52 vmov\.f32 q0, #-0\.140625 ; 0xbe100000 +0[0-9a-f]+ <[^>]+> f3850f52 vmov\.f32 q0, #-0\.28125 ; 0xbe900000 +0[0-9a-f]+ <[^>]+> f3860f52 vmov\.f32 q0, #-0\.5625 ; 0xbf100000 +0[0-9a-f]+ <[^>]+> f3870f52 vmov\.f32 q0, #-1\.125 ; 0xbf900000 +0[0-9a-f]+ <[^>]+> f3800f53 vmov\.f32 q0, #-2\.375 ; 0xc0180000 +0[0-9a-f]+ <[^>]+> f3810f53 vmov\.f32 q0, #-4\.75 ; 0xc0980000 +0[0-9a-f]+ <[^>]+> f3820f53 vmov\.f32 q0, #-9\.5 ; 0xc1180000 +0[0-9a-f]+ <[^>]+> f3830f53 vmov\.f32 q0, #-19 ; 0xc1980000 +0[0-9a-f]+ <[^>]+> f3840f53 vmov\.f32 q0, #-0\.1484375 ; 0xbe180000 +0[0-9a-f]+ <[^>]+> f3850f53 vmov\.f32 q0, #-0\.296875 ; 0xbe980000 +0[0-9a-f]+ <[^>]+> f3860f53 vmov\.f32 q0, #-0\.59375 ; 0xbf180000 +0[0-9a-f]+ <[^>]+> f3870f53 vmov\.f32 q0, #-1\.1875 ; 0xbf980000 +0[0-9a-f]+ <[^>]+> f3800f54 vmov\.f32 q0, #-2\.5 ; 0xc0200000 +0[0-9a-f]+ <[^>]+> f3810f54 vmov\.f32 q0, #-5 ; 0xc0a00000 +0[0-9a-f]+ <[^>]+> f3820f54 vmov\.f32 q0, #-10 ; 0xc1200000 +0[0-9a-f]+ <[^>]+> f3830f54 vmov\.f32 q0, #-20 ; 0xc1a00000 +0[0-9a-f]+ <[^>]+> f3840f54 vmov\.f32 q0, #-0\.15625 ; 0xbe200000 +0[0-9a-f]+ <[^>]+> f3850f54 vmov\.f32 q0, #-0\.3125 ; 0xbea00000 +0[0-9a-f]+ <[^>]+> f3860f54 vmov\.f32 q0, #-0\.625 ; 0xbf200000 +0[0-9a-f]+ <[^>]+> f3870f54 vmov\.f32 q0, #-1\.25 ; 0xbfa00000 +0[0-9a-f]+ <[^>]+> f3800f55 vmov\.f32 q0, #-2\.625 ; 0xc0280000 +0[0-9a-f]+ <[^>]+> f3810f55 vmov\.f32 q0, #-5\.25 ; 0xc0a80000 +0[0-9a-f]+ <[^>]+> f3820f55 vmov\.f32 q0, #-10\.5 ; 0xc1280000 +0[0-9a-f]+ <[^>]+> f3830f55 vmov\.f32 q0, #-21 ; 0xc1a80000 +0[0-9a-f]+ <[^>]+> f3840f55 vmov\.f32 q0, #-0\.1640625 ; 0xbe280000 +0[0-9a-f]+ <[^>]+> f3850f55 vmov\.f32 q0, #-0\.328125 ; 0xbea80000 +0[0-9a-f]+ <[^>]+> f3860f55 vmov\.f32 q0, #-0\.65625 ; 0xbf280000 +0[0-9a-f]+ <[^>]+> f3870f55 vmov\.f32 q0, #-1\.3125 ; 0xbfa80000 +0[0-9a-f]+ <[^>]+> f3800f56 vmov\.f32 q0, #-2\.75 ; 0xc0300000 +0[0-9a-f]+ <[^>]+> f3810f56 vmov\.f32 q0, #-5\.5 ; 0xc0b00000 +0[0-9a-f]+ <[^>]+> f3820f56 vmov\.f32 q0, #-11 ; 0xc1300000 +0[0-9a-f]+ <[^>]+> f3830f56 vmov\.f32 q0, #-22 ; 0xc1b00000 +0[0-9a-f]+ <[^>]+> f3840f56 vmov\.f32 q0, #-0\.171875 ; 0xbe300000 +0[0-9a-f]+ <[^>]+> f3850f56 vmov\.f32 q0, #-0\.34375 ; 0xbeb00000 +0[0-9a-f]+ <[^>]+> f3860f56 vmov\.f32 q0, #-0\.6875 ; 0xbf300000 +0[0-9a-f]+ <[^>]+> f3870f56 vmov\.f32 q0, #-1\.375 ; 0xbfb00000 +0[0-9a-f]+ <[^>]+> f3800f57 vmov\.f32 q0, #-2\.875 ; 0xc0380000 +0[0-9a-f]+ <[^>]+> f3810f57 vmov\.f32 q0, #-5\.75 ; 0xc0b80000 +0[0-9a-f]+ <[^>]+> f3820f57 vmov\.f32 q0, #-11\.5 ; 0xc1380000 +0[0-9a-f]+ <[^>]+> f3830f57 vmov\.f32 q0, #-23 ; 0xc1b80000 +0[0-9a-f]+ <[^>]+> f3840f57 vmov\.f32 q0, #-0\.1796875 ; 0xbe380000 +0[0-9a-f]+ <[^>]+> f3850f57 vmov\.f32 q0, #-0\.359375 ; 0xbeb80000 +0[0-9a-f]+ <[^>]+> f3860f57 vmov\.f32 q0, #-0\.71875 ; 0xbf380000 +0[0-9a-f]+ <[^>]+> f3870f57 vmov\.f32 q0, #-1\.4375 ; 0xbfb80000 +0[0-9a-f]+ <[^>]+> f3800f58 vmov\.f32 q0, #-3 ; 0xc0400000 +0[0-9a-f]+ <[^>]+> f3810f58 vmov\.f32 q0, #-6 ; 0xc0c00000 +0[0-9a-f]+ <[^>]+> f3820f58 vmov\.f32 q0, #-12 ; 0xc1400000 +0[0-9a-f]+ <[^>]+> f3830f58 vmov\.f32 q0, #-24 ; 0xc1c00000 +0[0-9a-f]+ <[^>]+> f3840f58 vmov\.f32 q0, #-0\.1875 ; 0xbe400000 +0[0-9a-f]+ <[^>]+> f3850f58 vmov\.f32 q0, #-0\.375 ; 0xbec00000 +0[0-9a-f]+ <[^>]+> f3860f58 vmov\.f32 q0, #-0\.75 ; 0xbf400000 +0[0-9a-f]+ <[^>]+> f3870f58 vmov\.f32 q0, #-1\.5 ; 0xbfc00000 +0[0-9a-f]+ <[^>]+> f3800f59 vmov\.f32 q0, #-3\.125 ; 0xc0480000 +0[0-9a-f]+ <[^>]+> f3810f59 vmov\.f32 q0, #-6\.25 ; 0xc0c80000 +0[0-9a-f]+ <[^>]+> f3820f59 vmov\.f32 q0, #-12\.5 ; 0xc1480000 +0[0-9a-f]+ <[^>]+> f3830f59 vmov\.f32 q0, #-25 ; 0xc1c80000 +0[0-9a-f]+ <[^>]+> f3840f59 vmov\.f32 q0, #-0\.1953125 ; 0xbe480000 +0[0-9a-f]+ <[^>]+> f3850f59 vmov\.f32 q0, #-0\.390625 ; 0xbec80000 +0[0-9a-f]+ <[^>]+> f3860f59 vmov\.f32 q0, #-0\.78125 ; 0xbf480000 +0[0-9a-f]+ <[^>]+> f3870f59 vmov\.f32 q0, #-1\.5625 ; 0xbfc80000 +0[0-9a-f]+ <[^>]+> f3800f5a vmov\.f32 q0, #-3\.25 ; 0xc0500000 +0[0-9a-f]+ <[^>]+> f3810f5a vmov\.f32 q0, #-6\.5 ; 0xc0d00000 +0[0-9a-f]+ <[^>]+> f3820f5a vmov\.f32 q0, #-13 ; 0xc1500000 +0[0-9a-f]+ <[^>]+> f3830f5a vmov\.f32 q0, #-26 ; 0xc1d00000 +0[0-9a-f]+ <[^>]+> f3840f5a vmov\.f32 q0, #-0\.203125 ; 0xbe500000 +0[0-9a-f]+ <[^>]+> f3850f5a vmov\.f32 q0, #-0\.40625 ; 0xbed00000 +0[0-9a-f]+ <[^>]+> f3860f5a vmov\.f32 q0, #-0\.8125 ; 0xbf500000 +0[0-9a-f]+ <[^>]+> f3870f5a vmov\.f32 q0, #-1\.625 ; 0xbfd00000 +0[0-9a-f]+ <[^>]+> f3800f5b vmov\.f32 q0, #-3\.375 ; 0xc0580000 +0[0-9a-f]+ <[^>]+> f3810f5b vmov\.f32 q0, #-6\.75 ; 0xc0d80000 +0[0-9a-f]+ <[^>]+> f3820f5b vmov\.f32 q0, #-13\.5 ; 0xc1580000 +0[0-9a-f]+ <[^>]+> f3830f5b vmov\.f32 q0, #-27 ; 0xc1d80000 +0[0-9a-f]+ <[^>]+> f3840f5b vmov\.f32 q0, #-0\.2109375 ; 0xbe580000 +0[0-9a-f]+ <[^>]+> f3850f5b vmov\.f32 q0, #-0\.421875 ; 0xbed80000 +0[0-9a-f]+ <[^>]+> f3860f5b vmov\.f32 q0, #-0\.84375 ; 0xbf580000 +0[0-9a-f]+ <[^>]+> f3870f5b vmov\.f32 q0, #-1\.6875 ; 0xbfd80000 +0[0-9a-f]+ <[^>]+> f3800f5c vmov\.f32 q0, #-3\.5 ; 0xc0600000 +0[0-9a-f]+ <[^>]+> f3810f5c vmov\.f32 q0, #-7 ; 0xc0e00000 +0[0-9a-f]+ <[^>]+> f3820f5c vmov\.f32 q0, #-14 ; 0xc1600000 +0[0-9a-f]+ <[^>]+> f3830f5c vmov\.f32 q0, #-28 ; 0xc1e00000 +0[0-9a-f]+ <[^>]+> f3840f5c vmov\.f32 q0, #-0\.21875 ; 0xbe600000 +0[0-9a-f]+ <[^>]+> f3850f5c vmov\.f32 q0, #-0\.4375 ; 0xbee00000 +0[0-9a-f]+ <[^>]+> f3860f5c vmov\.f32 q0, #-0\.875 ; 0xbf600000 +0[0-9a-f]+ <[^>]+> f3870f5c vmov\.f32 q0, #-1\.75 ; 0xbfe00000 +0[0-9a-f]+ <[^>]+> f3800f5d vmov\.f32 q0, #-3\.625 ; 0xc0680000 +0[0-9a-f]+ <[^>]+> f3810f5d vmov\.f32 q0, #-7\.25 ; 0xc0e80000 +0[0-9a-f]+ <[^>]+> f3820f5d vmov\.f32 q0, #-14\.5 ; 0xc1680000 +0[0-9a-f]+ <[^>]+> f3830f5d vmov\.f32 q0, #-29 ; 0xc1e80000 +0[0-9a-f]+ <[^>]+> f3840f5d vmov\.f32 q0, #-0\.2265625 ; 0xbe680000 +0[0-9a-f]+ <[^>]+> f3850f5d vmov\.f32 q0, #-0\.453125 ; 0xbee80000 +0[0-9a-f]+ <[^>]+> f3860f5d vmov\.f32 q0, #-0\.90625 ; 0xbf680000 +0[0-9a-f]+ <[^>]+> f3870f5d vmov\.f32 q0, #-1\.8125 ; 0xbfe80000 +0[0-9a-f]+ <[^>]+> f3800f5e vmov\.f32 q0, #-3\.75 ; 0xc0700000 +0[0-9a-f]+ <[^>]+> f3810f5e vmov\.f32 q0, #-7\.5 ; 0xc0f00000 +0[0-9a-f]+ <[^>]+> f3820f5e vmov\.f32 q0, #-15 ; 0xc1700000 +0[0-9a-f]+ <[^>]+> f3830f5e vmov\.f32 q0, #-30 ; 0xc1f00000 +0[0-9a-f]+ <[^>]+> f3840f5e vmov\.f32 q0, #-0\.234375 ; 0xbe700000 +0[0-9a-f]+ <[^>]+> f3850f5e vmov\.f32 q0, #-0\.46875 ; 0xbef00000 +0[0-9a-f]+ <[^>]+> f3860f5e vmov\.f32 q0, #-0\.9375 ; 0xbf700000 +0[0-9a-f]+ <[^>]+> f3870f5e vmov\.f32 q0, #-1\.875 ; 0xbff00000 +0[0-9a-f]+ <[^>]+> f3800f5f vmov\.f32 q0, #-3\.875 ; 0xc0780000 +0[0-9a-f]+ <[^>]+> f3810f5f vmov\.f32 q0, #-7\.75 ; 0xc0f80000 +0[0-9a-f]+ <[^>]+> f3820f5f vmov\.f32 q0, #-15\.5 ; 0xc1780000 +0[0-9a-f]+ <[^>]+> f3830f5f vmov\.f32 q0, #-31 ; 0xc1f80000 +0[0-9a-f]+ <[^>]+> f3840f5f vmov\.f32 q0, #-0\.2421875 ; 0xbe780000 +0[0-9a-f]+ <[^>]+> f3850f5f vmov\.f32 q0, #-0\.484375 ; 0xbef80000 +0[0-9a-f]+ <[^>]+> f3860f5f vmov\.f32 q0, #-0\.96875 ; 0xbf780000 +0[0-9a-f]+ <[^>]+> f3870f5f vmov\.f32 q0, #-1\.9375 ; 0xbff80000 +0[0-9a-f]+ <[^>]+> f3879e3f vmov\.i64 d9, #0xffffffffffffffff diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-const.s b/binutils-2.25/gas/testsuite/gas/arm/neon-const.s new file mode 100644 index 00000000..aaaf1441 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-const.s @@ -0,0 +1,299 @@ +@ test floating-point constant parsing. + + .arm + .text + .syntax unified + + vmov.f32 q0, 0.0 + + vmov.f32 q0, 2.0 + vmov.f32 q0, 4.0 + vmov.f32 q0, 8.0 + vmov.f32 q0, 16.0 + vmov.f32 q0, 0.125 + vmov.f32 q0, 0.25 + vmov.f32 q0, 0.5 + vmov.f32 q0, 1.0 + + vmov.f32 q0, 2.125 + vmov.f32 q0, 4.25 + vmov.f32 q0, 8.5 + vmov.f32 q0, 17.0 + vmov.f32 q0, 0.1328125 + vmov.f32 q0, 0.265625 + vmov.f32 q0, 0.53125 + vmov.f32 q0, 1.0625 + + vmov.f32 q0, 2.25 + vmov.f32 q0, 4.5 + vmov.f32 q0, 9.0 + vmov.f32 q0, 18.0 + vmov.f32 q0, 0.140625 + vmov.f32 q0, 0.28125 + vmov.f32 q0, 0.5625 + vmov.f32 q0, 1.125 + + vmov.f32 q0, 2.375 + vmov.f32 q0, 4.75 + vmov.f32 q0, 9.5 + vmov.f32 q0, 19.0 + vmov.f32 q0, 0.1484375 + vmov.f32 q0, 0.296875 + vmov.f32 q0, 0.59375 + vmov.f32 q0, 1.1875 + + vmov.f32 q0, 2.5 + vmov.f32 q0, 5.0 + vmov.f32 q0, 10.0 + vmov.f32 q0, 20.0 + vmov.f32 q0, 0.15625 + vmov.f32 q0, 0.3125 + vmov.f32 q0, 0.625 + vmov.f32 q0, 1.25 + + vmov.f32 q0, 2.625 + vmov.f32 q0, 5.25 + vmov.f32 q0, 10.5 + vmov.f32 q0, 21.0 + vmov.f32 q0, 0.1640625 + vmov.f32 q0, 0.328125 + vmov.f32 q0, 0.65625 + vmov.f32 q0, 1.3125 + + vmov.f32 q0, 2.75 + vmov.f32 q0, 5.5 + vmov.f32 q0, 11.0 + vmov.f32 q0, 22.0 + vmov.f32 q0, 0.171875 + vmov.f32 q0, 0.34375 + vmov.f32 q0, 0.6875 + vmov.f32 q0, 1.375 + + vmov.f32 q0, 2.875 + vmov.f32 q0, 5.75 + vmov.f32 q0, 11.5 + vmov.f32 q0, 23.0 + vmov.f32 q0, 0.1796875 + vmov.f32 q0, 0.359375 + vmov.f32 q0, 0.71875 + vmov.f32 q0, 1.4375 + + vmov.f32 q0, 3.0 + vmov.f32 q0, 6.0 + vmov.f32 q0, 12.0 + vmov.f32 q0, 24.0 + vmov.f32 q0, 0.1875 + vmov.f32 q0, 0.375 + vmov.f32 q0, 0.75 + vmov.f32 q0, 1.5 + + vmov.f32 q0, 3.125 + vmov.f32 q0, 6.25 + vmov.f32 q0, 12.5 + vmov.f32 q0, 25.0 + vmov.f32 q0, 0.1953125 + vmov.f32 q0, 0.390625 + vmov.f32 q0, 0.78125 + vmov.f32 q0, 1.5625 + + vmov.f32 q0, 3.25 + vmov.f32 q0, 6.5 + vmov.f32 q0, 13.0 + vmov.f32 q0, 26.0 + vmov.f32 q0, 0.203125 + vmov.f32 q0, 0.40625 + vmov.f32 q0, 0.8125 + vmov.f32 q0, 1.625 + + vmov.f32 q0, 3.375 + vmov.f32 q0, 6.75 + vmov.f32 q0, 13.5 + vmov.f32 q0, 27.0 + vmov.f32 q0, 0.2109375 + vmov.f32 q0, 0.421875 + vmov.f32 q0, 0.84375 + vmov.f32 q0, 1.6875 + + vmov.f32 q0, 3.5 + vmov.f32 q0, 7.0 + vmov.f32 q0, 14.0 + vmov.f32 q0, 28.0 + vmov.f32 q0, 0.21875 + vmov.f32 q0, 0.4375 + vmov.f32 q0, 0.875 + vmov.f32 q0, 1.75 + + vmov.f32 q0, 3.625 + vmov.f32 q0, 7.25 + vmov.f32 q0, 14.5 + vmov.f32 q0, 29.0 + vmov.f32 q0, 0.2265625 + vmov.f32 q0, 0.453125 + vmov.f32 q0, 0.90625 + vmov.f32 q0, 1.8125 + + vmov.f32 q0, 3.75 + vmov.f32 q0, 7.5 + vmov.f32 q0, 15.0 + vmov.f32 q0, 30.0 + vmov.f32 q0, 0.234375 + vmov.f32 q0, 0.46875 + vmov.f32 q0, 0.9375 + vmov.f32 q0, 1.875 + + vmov.f32 q0, 3.875 + vmov.f32 q0, 7.75 + vmov.f32 q0, 15.5 + vmov.f32 q0, 31.0 + vmov.f32 q0, 0.2421875 + vmov.f32 q0, 0.484375 + vmov.f32 q0, 0.96875 + vmov.f32 q0, 1.9375 + + vmov.f32 q0, -0.0 + + vmov.f32 q0, -2.0 + vmov.f32 q0, -4.0 + vmov.f32 q0, -8.0 + vmov.f32 q0, -16.0 + vmov.f32 q0, -0.125 + vmov.f32 q0, -0.25 + vmov.f32 q0, -0.5 + vmov.f32 q0, -1.0 + + vmov.f32 q0, -2.125 + vmov.f32 q0, -4.25 + vmov.f32 q0, -8.5 + vmov.f32 q0, -17.0 + vmov.f32 q0, -0.1328125 + vmov.f32 q0, -0.265625 + vmov.f32 q0, -0.53125 + vmov.f32 q0, -1.0625 + + vmov.f32 q0, -2.25 + vmov.f32 q0, -4.5 + vmov.f32 q0, -9.0 + vmov.f32 q0, -18.0 + vmov.f32 q0, -0.140625 + vmov.f32 q0, -0.28125 + vmov.f32 q0, -0.5625 + vmov.f32 q0, -1.125 + + vmov.f32 q0, -2.375 + vmov.f32 q0, -4.75 + vmov.f32 q0, -9.5 + vmov.f32 q0, -19.0 + vmov.f32 q0, -0.1484375 + vmov.f32 q0, -0.296875 + vmov.f32 q0, -0.59375 + vmov.f32 q0, -1.1875 + + vmov.f32 q0, -2.5 + vmov.f32 q0, -5.0 + vmov.f32 q0, -10.0 + vmov.f32 q0, -20.0 + vmov.f32 q0, -0.15625 + vmov.f32 q0, -0.3125 + vmov.f32 q0, -0.625 + vmov.f32 q0, -1.25 + + vmov.f32 q0, -2.625 + vmov.f32 q0, -5.25 + vmov.f32 q0, -10.5 + vmov.f32 q0, -21.0 + vmov.f32 q0, -0.1640625 + vmov.f32 q0, -0.328125 + vmov.f32 q0, -0.65625 + vmov.f32 q0, -1.3125 + + vmov.f32 q0, -2.75 + vmov.f32 q0, -5.5 + vmov.f32 q0, -11.0 + vmov.f32 q0, -22.0 + vmov.f32 q0, -0.171875 + vmov.f32 q0, -0.34375 + vmov.f32 q0, -0.6875 + vmov.f32 q0, -1.375 + + vmov.f32 q0, -2.875 + vmov.f32 q0, -5.75 + vmov.f32 q0, -11.5 + vmov.f32 q0, -23.0 + vmov.f32 q0, -0.1796875 + vmov.f32 q0, -0.359375 + vmov.f32 q0, -0.71875 + vmov.f32 q0, -1.4375 + + vmov.f32 q0, -3.0 + vmov.f32 q0, -6.0 + vmov.f32 q0, -12.0 + vmov.f32 q0, -24.0 + vmov.f32 q0, -0.1875 + vmov.f32 q0, -0.375 + vmov.f32 q0, -0.75 + vmov.f32 q0, -1.5 + + vmov.f32 q0, -3.125 + vmov.f32 q0, -6.25 + vmov.f32 q0, -12.5 + vmov.f32 q0, -25.0 + vmov.f32 q0, -0.1953125 + vmov.f32 q0, -0.390625 + vmov.f32 q0, -0.78125 + vmov.f32 q0, -1.5625 + + vmov.f32 q0, -3.25 + vmov.f32 q0, -6.5 + vmov.f32 q0, -13.0 + vmov.f32 q0, -26.0 + vmov.f32 q0, -0.203125 + vmov.f32 q0, -0.40625 + vmov.f32 q0, -0.8125 + vmov.f32 q0, -1.625 + + vmov.f32 q0, -3.375 + vmov.f32 q0, -6.75 + vmov.f32 q0, -13.5 + vmov.f32 q0, -27.0 + vmov.f32 q0, -0.2109375 + vmov.f32 q0, -0.421875 + vmov.f32 q0, -0.84375 + vmov.f32 q0, -1.6875 + + vmov.f32 q0, -3.5 + vmov.f32 q0, -7.0 + vmov.f32 q0, -14.0 + vmov.f32 q0, -28.0 + vmov.f32 q0, -0.21875 + vmov.f32 q0, -0.4375 + vmov.f32 q0, -0.875 + vmov.f32 q0, -1.75 + + vmov.f32 q0, -3.625 + vmov.f32 q0, -7.25 + vmov.f32 q0, -14.5 + vmov.f32 q0, -29.0 + vmov.f32 q0, -0.2265625 + vmov.f32 q0, -0.453125 + vmov.f32 q0, -0.90625 + vmov.f32 q0, -1.8125 + + vmov.f32 q0, -3.75 + vmov.f32 q0, -7.5 + vmov.f32 q0, -15.0 + vmov.f32 q0, -30.0 + vmov.f32 q0, -0.234375 + vmov.f32 q0, -0.46875 + vmov.f32 q0, -0.9375 + vmov.f32 q0, -1.875 + + vmov.f32 q0, -3.875 + vmov.f32 q0, -7.75 + vmov.f32 q0, -15.5 + vmov.f32 q0, -31.0 + vmov.f32 q0, -0.2421875 + vmov.f32 q0, -0.484375 + vmov.f32 q0, -0.96875 + vmov.f32 q0, -1.9375 + + vmov.i64 d9, #0xffffffffffffffff diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cov.d b/binutils-2.25/gas/testsuite/gas/arm/neon-cov.d new file mode 100644 index 00000000..3d7a4885 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cov.d @@ -0,0 +1,1522 @@ +# name: Neon instruction coverage +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f2000750 vaba\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000750 vaba\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000710 vaba\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100750 vaba\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100750 vaba\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100710 vaba\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200750 vaba\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200750 vaba\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200710 vaba\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000750 vaba\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000750 vaba\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000710 vaba\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100750 vaba\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100710 vaba\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200750 vaba\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200750 vaba\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200710 vaba\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000040 vhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000040 vhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000000 vhadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100040 vhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100040 vhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100000 vhadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200040 vhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200040 vhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200000 vhadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000040 vhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000040 vhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000000 vhadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100040 vhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100000 vhadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200040 vhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200040 vhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200000 vhadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000140 vrhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000140 vrhadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000100 vrhadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100140 vrhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100140 vrhadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100100 vrhadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200140 vrhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200140 vrhadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200100 vrhadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000140 vrhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000140 vrhadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000100 vrhadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100140 vrhadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100100 vrhadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200140 vrhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200140 vrhadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200100 vrhadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000240 vhsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000240 vhsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000200 vhsub\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100240 vhsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100240 vhsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100200 vhsub\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200240 vhsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200240 vhsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200200 vhsub\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000240 vhsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000240 vhsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000200 vhsub\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100240 vhsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100200 vhsub\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200240 vhsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200240 vhsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200200 vhsub\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000050 vqadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000050 vqadd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000010 vqadd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100050 vqadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100050 vqadd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100010 vqadd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200050 vqadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200050 vqadd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200010 vqadd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300050 vqadd\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300050 vqadd\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300010 vqadd\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000050 vqadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000050 vqadd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000010 vqadd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100050 vqadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100050 vqadd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100010 vqadd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200050 vqadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200050 vqadd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200010 vqadd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300050 vqadd\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300050 vqadd\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300010 vqadd\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000250 vqsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000250 vqsub\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000210 vqsub\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100250 vqsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100250 vqsub\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100210 vqsub\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200250 vqsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200250 vqsub\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200210 vqsub\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300250 vqsub\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300250 vqsub\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300210 vqsub\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000250 vqsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000250 vqsub\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000210 vqsub\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100250 vqsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100250 vqsub\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100210 vqsub\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200250 vqsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200250 vqsub\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200210 vqsub\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300250 vqsub\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300250 vqsub\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300210 vqsub\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000540 vrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000540 vrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000500 vrshl\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100540 vrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100540 vrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100500 vrshl\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200540 vrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200540 vrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200500 vrshl\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300540 vrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300540 vrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300500 vrshl\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000540 vrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000540 vrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000500 vrshl\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100540 vrshl\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100540 vrshl\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100500 vrshl\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200540 vrshl\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200540 vrshl\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200500 vrshl\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300540 vrshl\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300540 vrshl\.u64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300500 vrshl\.u64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000550 vqrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000550 vqrshl\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000510 vqrshl\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100550 vqrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100550 vqrshl\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100510 vqrshl\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200550 vqrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200550 vqrshl\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200510 vqrshl\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300550 vqrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300550 vqrshl\.s64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300510 vqrshl\.s64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000550 vqrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000550 vqrshl\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000510 vqrshl\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> 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vbic\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820175 vbic\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820135 vbic\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820375 vbic\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820335 vbic\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820575 vbic\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820535 vbic\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820775 vbic\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820735 vbic\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387017f vbic\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387013f vbic\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387037f vbic\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387033f vbic\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387057f vbic\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387053f vbic\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387077f vbic\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387073f vbic\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387097f vbic\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387093f vbic\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b7f vbic\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b3f vbic\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800970 vbic\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800930 vbic\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820155 vorr\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820115 vorr\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820355 vorr\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820315 vorr\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820555 vorr\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820515 vorr\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820755 vorr\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820715 vorr\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387015f vorr\.i32 q0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387011f vorr\.i32 d0, #255 ; 0x000000ff +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387035f vorr\.i32 q0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387031f vorr\.i32 d0, #65280 ; 0x0000ff00 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387055f vorr\.i32 q0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387051f vorr\.i32 d0, #16711680 ; 0x00ff0000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387075f vorr\.i32 q0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f387071f vorr\.i32 d0, #-16777216 ; 0xff000000 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820955 vorr\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820915 vorr\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b55 vorr\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820b15 vorr\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387095f vorr\.i16 q0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f387091f vorr\.i16 d0, #255 ; 0x00ff +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b5f vorr\.i16 q0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f3870b1f vorr\.i16 d0, #65280 ; 0xff00 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800950 vorr\.i16 q0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f2800910 vorr\.i16 d0, #0 ; 0x0000 +0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100150 vbsl q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100110 vbsl d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200150 vbit q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200150 vbit q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200110 vbit d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300150 vbif q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300150 vbif q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300110 vbif d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000740 vabd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000740 vabd\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000700 vabd\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100740 vabd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100740 vabd\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100700 vabd\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200740 vabd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200740 vabd\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200700 vabd\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000740 vabd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000740 vabd\.u8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000700 vabd\.u8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100740 vabd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100740 vabd\.u16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100700 vabd\.u16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200740 vabd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200740 vabd\.u32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200700 vabd\.u32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200d40 vabd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200d40 vabd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200d00 vabd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000640 vmax\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000640 vmax\.s8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000600 vmax\.s8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100640 vmax\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100640 vmax\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100600 vmax\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200640 vmax\.s32 q0, q0, q0 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f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00040 vmla\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00040 vmla\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00140 vmla\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00140 vmla\.f32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3000940 vmls\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000940 vmls\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000900 vmls\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100940 vmls\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100940 vmls\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100900 vmls\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200940 vmls\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200900 vmls\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d50 vmls\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d10 vmls\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900440 vmls\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900440 vmls\.i16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900440 vmls\.i16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00440 vmls\.i32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00440 vmls\.i32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00540 vmls\.f32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00540 vmls\.f32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2000b10 vpadd\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100b10 vpadd\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b10 vpadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000d00 vpadd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000840 vadd\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000800 vadd\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100840 vadd\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100840 vadd\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100800 vadd\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200840 vadd\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200800 vadd\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300840 vadd\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2300800 vadd\.i64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000d40 vadd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d40 vadd\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000d00 vadd\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000840 vsub\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000840 vsub\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000800 vsub\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3100840 vsub\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100840 vsub\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100800 vsub\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200840 vsub\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200800 vsub\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300840 vsub\.i64 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3300800 vsub\.i64 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200d40 vsub\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d40 vsub\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200d00 vsub\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000850 vtst\.8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000850 vtst\.8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000810 vtst\.8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100850 vtst\.16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100850 vtst\.16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100810 vtst\.16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200850 vtst\.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200850 vtst\.32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200810 vtst\.32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000950 vmul\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000950 vmul\.i8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000910 vmul\.i8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100950 vmul\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100950 vmul\.i16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100910 vmul\.i16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200950 vmul\.i32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200910 vmul\.i32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000d50 vmul\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000d10 vmul\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000950 vmul\.p8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000950 vmul\.p8 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000910 vmul\.p8 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2100b40 vqdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100b40 vqdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2100b00 vqdmulh\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200b40 vqdmulh\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200b40 vqdmulh\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200b00 vqdmulh\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900c40 vqdmulh\.s16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900c40 vqdmulh\.s16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900c40 vqdmulh\.s16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00c40 vqdmulh\.s32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00c40 vqdmulh\.s32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00c40 vqdmulh\.s32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3100b40 vqrdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100b40 vqrdmulh\.s16 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3100b00 vqrdmulh\.s16 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200b40 vqrdmulh\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200b40 vqrdmulh\.s32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200b00 vqrdmulh\.s32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900d40 vqrdmulh\.s16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900d40 vqrdmulh\.s16 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900d40 vqrdmulh\.s16 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00d40 vqrdmulh\.s32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00d40 vqrdmulh\.s32 q0, q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00d40 vqrdmulh\.s32 d0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e50 vacge\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3000e10 vacge\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e50 vacgt\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f3200e10 vacgt\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000f50 vrecps\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000f10 vrecps\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200f50 vrsqrts\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200f50 vrsqrts\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200f10 vrsqrts\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f3b10340 vabs\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b10340 vabs\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b10300 vabs\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b50340 vabs\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b50340 vabs\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b50300 vabs\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b90340 vabs\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b90340 vabs\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b90300 vabs\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b90740 vabs\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b90740 vabs\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b90700 vabs\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b103c0 vneg\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b103c0 vneg\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b10380 vneg\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b503c0 vneg\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b503c0 vneg\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b50380 vneg\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b903c0 vneg\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b903c0 vneg\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b90380 vneg\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b907c0 vneg\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b907c0 vneg\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b90780 vneg\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f2890050 vshr\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890050 vshr\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890010 vshr\.s8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f2910050 vshr\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910050 vshr\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910010 vshr\.s16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f2a10050 vshr\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10050 vshr\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10010 vshr\.s32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f28100d0 vshr\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f28100d0 vshr\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f2810090 vshr\.s64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f3890050 vshr\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890050 vshr\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890010 vshr\.u8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f3910050 vshr\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910050 vshr\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910010 vshr\.u16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f3a10050 vshr\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10050 vshr\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10010 vshr\.u32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f38100d0 vshr\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f38100d0 vshr\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f3810090 vshr\.u64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f2890250 vrshr\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890250 vrshr\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890210 vrshr\.s8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f2910250 vrshr\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910250 vrshr\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910210 vrshr\.s16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f2a10250 vrshr\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10250 vrshr\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10210 vrshr\.s32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f28102d0 vrshr\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f28102d0 vrshr\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f2810290 vrshr\.s64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f3890250 vrshr\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890250 vrshr\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890210 vrshr\.u8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f3910250 vrshr\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910250 vrshr\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910210 vrshr\.u16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f3a10250 vrshr\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10250 vrshr\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10210 vrshr\.u32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f38102d0 vrshr\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f38102d0 vrshr\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f3810290 vrshr\.u64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f2890150 vsra\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890150 vsra\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890110 vsra\.s8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f2910150 vsra\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910150 vsra\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910110 vsra\.s16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f2a10150 vsra\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10150 vsra\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10110 vsra\.s32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f28101d0 vsra\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f28101d0 vsra\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f2810190 vsra\.s64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f3890150 vsra\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890150 vsra\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890110 vsra\.u8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f3910150 vsra\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910150 vsra\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910110 vsra\.u16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f3a10150 vsra\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10150 vsra\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10110 vsra\.u32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f38101d0 vsra\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f38101d0 vsra\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f3810190 vsra\.u64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f2890350 vrsra\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890350 vrsra\.s8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f2890310 vrsra\.s8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f2910350 vrsra\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910350 vrsra\.s16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910310 vrsra\.s16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f2a10350 vrsra\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10350 vrsra\.s32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f2a10310 vrsra\.s32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f28103d0 vrsra\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f28103d0 vrsra\.s64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f2810390 vrsra\.s64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f3890350 vrsra\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890350 vrsra\.u8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890310 vrsra\.u8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f3910350 vrsra\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910350 vrsra\.u16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910310 vrsra\.u16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f3a10350 vrsra\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10350 vrsra\.u32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10310 vrsra\.u32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f38103d0 vrsra\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f38103d0 vrsra\.u64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f3810390 vrsra\.u64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f3880550 vsli\.8 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3880550 vsli\.8 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3880510 vsli\.8 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f3900550 vsli\.16 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3900550 vsli\.16 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3900510 vsli\.16 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f3a00550 vsli\.32 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3a00550 vsli\.32 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3a00510 vsli\.32 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f38005d0 vsli\.64 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f38005d0 vsli\.64 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3800590 vsli\.64 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f3890450 vsri\.8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890450 vsri\.8 q0, q0, #7 +0[0-9a-f]+ <[^>]+> f3890410 vsri\.8 d0, d0, #7 +0[0-9a-f]+ <[^>]+> f3910450 vsri\.16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910450 vsri\.16 q0, q0, #15 +0[0-9a-f]+ <[^>]+> f3910410 vsri\.16 d0, d0, #15 +0[0-9a-f]+ <[^>]+> f3a10450 vsri\.32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10450 vsri\.32 q0, q0, #31 +0[0-9a-f]+ <[^>]+> f3a10410 vsri\.32 d0, d0, #31 +0[0-9a-f]+ <[^>]+> f38104d0 vsri\.64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f38104d0 vsri\.64 q0, q0, #63 +0[0-9a-f]+ <[^>]+> f3810490 vsri\.64 d0, d0, #63 +0[0-9a-f]+ <[^>]+> f3880650 vqshlu\.s8 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3880650 vqshlu\.s8 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3880610 vqshlu\.s8 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f3900650 vqshlu\.s16 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3900650 vqshlu\.s16 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3900610 vqshlu\.s16 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f3a00650 vqshlu\.s32 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3a00650 vqshlu\.s32 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3a00610 vqshlu\.s32 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f38006d0 vqshlu\.s64 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f38006d0 vqshlu\.s64 q0, q0, #0 +0[0-9a-f]+ <[^>]+> f3800690 vqshlu\.s64 d0, d0, #0 +0[0-9a-f]+ <[^>]+> f2890910 vqshrn\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910910 vqshrn\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10910 vqshrn\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890910 vqshrn\.u16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910910 vqshrn\.u32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10910 vqshrn\.u64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890950 vqrshrn\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910950 vqrshrn\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10950 vqrshrn\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890950 vqrshrn\.u16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910950 vqrshrn\.u32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10950 vqrshrn\.u64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890810 vqshrun\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910810 vqshrun\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10810 vqshrun\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f3890850 vqrshrun\.s16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f3910850 vqrshrun\.s32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f3a10850 vqrshrun\.s64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890810 vshrn\.i16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910810 vshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10810 vshrn\.i64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890850 vrshrn\.i16 d0, q0, #7 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2910850 vrshrn\.i32 d0, q0, #15 +0[0-9a-f]+ <[^>]+> f2a10850 vrshrn\.i64 d0, q0, #31 +0[0-9a-f]+ <[^>]+> f2890a10 vshll\.s8 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f2910a10 vshll\.s16 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f2a10a10 vshll\.s32 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3890a10 vshll\.u8 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3910a10 vshll\.u16 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3a10a10 vshll\.u32 q0, d0, #1 +0[0-9a-f]+ <[^>]+> f3b20300 vshll\.i8 q0, d0, #8 +0[0-9a-f]+ <[^>]+> f3b60300 vshll\.i16 q0, d0, #16 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3ba0300 vshll\.i32 q0, d0, #32 +0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb06c0 vcvt\.f32\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0740 vcvt\.s32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb07c0 vcvt\.u32\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0640 vcvt\.f32\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb06c0 vcvt\.f32\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0700 vcvt\.s32\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0780 vcvt\.u32\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0600 vcvt\.f32\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0680 vcvt\.f32\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f2bf0f50 vcvt\.s32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f50 vcvt\.u32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e50 vcvt\.f32\.s32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e50 vcvt\.f32\.u32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0f50 vcvt\.s32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f50 vcvt\.u32\.f32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e50 vcvt\.f32\.s32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e50 vcvt\.f32\.u32 q0, q0, #1 +0[0-9a-f]+ <[^>]+> f2bf0f10 vcvt\.s32\.f32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f3bf0f10 vcvt\.u32\.f32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f2bf0e10 vcvt\.f32\.s32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f3bf0e10 vcvt\.f32\.u32 d0, d0, #1 +0[0-9a-f]+ <[^>]+> f2200150 vorr q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200110 vorr d0, d0, d0 +0[0-9a-f]+ <[^>]+> ee400b10 vmov\.8 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b30 vmov\.16 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ec400b10 vmov d0, r0, r0 +0[0-9a-f]+ <[^>]+> ee500b10 vmov\.s8 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b30 vmov\.s16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> eed00b10 vmov\.u8 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee900b30 vmov\.u16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870057 vmov\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870017 vmov\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870077 vmvn\.i32 q0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870037 vmvn\.i32 d0, #119 ; 0x00000077 +0[0-9a-f]+ <[^>]+> f2870257 vmov\.i32 q0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870217 vmov\.i32 d0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870277 vmvn\.i32 q0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870237 vmvn\.i32 d0, #30464 ; 0x00007700 +0[0-9a-f]+ <[^>]+> f2870457 vmov\.i32 q0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870417 vmov\.i32 d0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870477 vmvn\.i32 q0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870437 vmvn\.i32 d0, #7798784 ; 0x00770000 +0[0-9a-f]+ <[^>]+> f2870657 vmov\.i32 q0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870617 vmov\.i32 d0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870677 vmvn\.i32 q0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870637 vmvn\.i32 d0, #1996488704 ; 0x77000000 +0[0-9a-f]+ <[^>]+> f2870857 vmov\.i16 q0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870817 vmov\.i16 d0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870877 vmvn\.i16 q0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870837 vmvn\.i16 d0, #119 ; 0x0077 +0[0-9a-f]+ <[^>]+> f2870a57 vmov\.i16 q0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a17 vmov\.i16 d0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a77 vmvn\.i16 q0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870a37 vmvn\.i16 d0, #30464 ; 0x7700 +0[0-9a-f]+ <[^>]+> f2870c57 vmov\.i32 q0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c17 vmov\.i32 d0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c77 vmvn\.i32 q0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870c37 vmvn\.i32 d0, #30719 ; 0x000077ff +0[0-9a-f]+ <[^>]+> f2870d57 vmov\.i32 q0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d17 vmov\.i32 d0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d77 vmvn\.i32 q0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870d37 vmvn\.i32 d0, #7864319 ; 0x0077ffff +0[0-9a-f]+ <[^>]+> f2870e57 vmov\.i8 q0, #119 ; 0x77 +0[0-9a-f]+ <[^>]+> f2870e17 vmov\.i8 d0, #119 ; 0x77 +0[0-9a-f]+ <[^>]+> f3810e71 vmov\.i64 q0, #0xff0000ff000000ff +0[0-9a-f]+ <[^>]+> f3810e31 vmov\.i64 d0, #0xff0000ff000000ff +0[0-9a-f]+ <[^>]+> f2810f51 vmov\.f32 q0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f2810f11 vmov\.f32 d0, #4\.25 ; 0x40880000 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820e55 vmov\.i8 q0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f3820e15 vmov\.i8 d0, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f2850e5a vmov\.i8 q0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f2850e1a vmov\.i8 d0, #90 ; 0x5a +0[0-9a-f]+ <[^>]+> f3820855 vmov\.i16 q0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820815 vmov\.i16 d0, #165 ; 0x00a5 +0[0-9a-f]+ <[^>]+> f3820a55 vmov\.i16 q0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820a15 vmov\.i16 d0, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f3820055 vmov\.i32 q0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820015 vmov\.i32 d0, #165 ; 0x000000a5 +0[0-9a-f]+ <[^>]+> f3820255 vmov\.i32 q0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820215 vmov\.i32 d0, #42240 ; 0x0000a500 +0[0-9a-f]+ <[^>]+> f3820455 vmov\.i32 q0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820415 vmov\.i32 d0, #10813440 ; 0x00a50000 +0[0-9a-f]+ <[^>]+> f3820655 vmov\.i32 q0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820615 vmov\.i32 d0, #-1526726656 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f3820c55 vmov\.i32 q0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820c15 vmov\.i32 d0, #42495 ; 0x0000a5ff +0[0-9a-f]+ <[^>]+> f3820d55 vmov\.i32 q0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f3820d15 vmov\.i32 d0, #10878975 ; 0x00a5ffff +0[0-9a-f]+ <[^>]+> f285067a vmvn\.i32 q0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f285063a vmvn\.i32 d0, #1509949440 ; 0x5a000000 +0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 +0[0-9a-f]+ <[^>]+> f3b005c0 vmvn q0, q0 +0[0-9a-f]+ <[^>]+> f3b00580 vmvn d0, d0 +0[0-9a-f]+ <[^>]+> f2800500 vabal\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900500 vabal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00500 vabal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800500 vabal\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900500 vabal\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00500 vabal\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800700 vabdl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900700 vabdl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00700 vabdl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800700 vabdl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900700 vabdl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00700 vabdl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800000 vaddl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900000 vaddl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00000 vaddl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800000 vaddl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900000 vaddl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00000 vaddl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800200 vsubl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900200 vsubl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00200 vsubl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800200 vsubl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900200 vsubl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00200 vsubl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800800 vmlal\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900800 vmlal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00800 vmlal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800800 vmlal\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900800 vmlal\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00800 vmlal\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900240 vmlal\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00240 vmlal\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900240 vmlal\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00240 vmlal\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800a00 vmlsl\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900a00 vmlsl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00a00 vmlsl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800a00 vmlsl\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900a00 vmlsl\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00a00 vmlsl\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900640 vmlsl\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00640 vmlsl\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900640 vmlsl\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00640 vmlsl\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800100 vaddw\.s8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2900100 vaddw\.s16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2a00100 vaddw\.s32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3800100 vaddw\.u8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3900100 vaddw\.u16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3a00100 vaddw\.u32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2800300 vsubw\.s8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2900300 vsubw\.s16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2a00300 vsubw\.s32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3800300 vsubw\.u8 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3900300 vsubw\.u16 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f3a00300 vsubw\.u32 q0, q0, d0 +0[0-9a-f]+ <[^>]+> f2800400 vaddhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900400 vaddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2a00400 vaddhn\.i64 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3800400 vraddhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900400 vraddhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3a00400 vraddhn\.i64 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2800600 vsubhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900600 vsubhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2a00600 vsubhn\.i64 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3800600 vrsubhn\.i16 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3900600 vrsubhn\.i32 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f3a00600 vrsubhn\.i64 d0, q0, q0 +0[0-9a-f]+ <[^>]+> f2900900 vqdmlal\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00900 vqdmlal\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900340 vqdmlal\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00340 vqdmlal\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900b00 vqdmlsl\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00b00 vqdmlsl\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900740 vqdmlsl\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00740 vqdmlsl\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2900d00 vqdmull\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00d00 vqdmull\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900b40 vqdmull\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00b40 vqdmull\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2800c00 vmull\.s8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900c00 vmull\.s16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2a00c00 vmull\.s32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3800c00 vmull\.u8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3900c00 vmull\.u16 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f3a00c00 vmull\.u32 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2800e00 vmull\.p8 q0, d0, d0 +0[0-9a-f]+ <[^>]+> f2900a40 vmull\.s16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2a00a40 vmull\.s32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3900a40 vmull\.u16 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3a00a40 vmull\.u32 q0, d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2b00040 vext\.8 q0, q0, q0, #0 +0[0-9a-f]+ <[^>]+> f2b00040 vext\.8 q0, q0, q0, #0 +0[0-9a-f]+ <[^>]+> f2b00000 vext\.8 d0, d0, d0, #0 +0[0-9a-f]+ <[^>]+> f2b00840 vext\.8 q0, q0, q0, #8 +0[0-9a-f]+ <[^>]+> f3b00040 vrev64\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00040 vrev64\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00000 vrev64\.8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40040 vrev64\.16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40040 vrev64\.16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40000 vrev64\.16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80040 vrev64\.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80040 vrev64\.32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80000 vrev64\.32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b000c0 vrev32\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b000c0 vrev32\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00080 vrev32\.8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b400c0 vrev32\.16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b400c0 vrev32\.16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40080 vrev32\.16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00140 vrev16\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00140 vrev16\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00100 vrev16\.8 d0, d0 +0[0-9a-f]+ <[^>]+> eee00b10 vdup\.8 q0, r0 +0[0-9a-f]+ <[^>]+> eee00b10 vdup\.8 q0, r0 +0[0-9a-f]+ <[^>]+> eec00b10 vdup\.8 d0, r0 +0[0-9a-f]+ <[^>]+> f3b10c40 vdup\.8 q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3b10c40 vdup\.8 q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3b10c00 vdup\.8 d0, d0\[0\] +0[0-9a-f]+ <[^>]+> eea00b30 vdup\.16 q0, r0 +0[0-9a-f]+ <[^>]+> eea00b30 vdup\.16 q0, r0 +0[0-9a-f]+ <[^>]+> ee800b30 vdup\.16 d0, r0 +0[0-9a-f]+ <[^>]+> f3b20c40 vdup\.16 q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3b20c40 vdup\.16 q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3b20c00 vdup\.16 d0, d0\[0\] +0[0-9a-f]+ <[^>]+> eea00b10 vdup\.32 q0, r0 +0[0-9a-f]+ <[^>]+> eea00b10 vdup\.32 q0, r0 +0[0-9a-f]+ <[^>]+> ee800b10 vdup\.32 d0, r0 +0[0-9a-f]+ <[^>]+> f3b40c40 vdup\.32 q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3b40c40 vdup\.32 q0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3b40c00 vdup\.32 d0, d0\[0\] +0[0-9a-f]+ <[^>]+> f2880a10 vmovl\.s8 q0, d0 +0[0-9a-f]+ <[^>]+> f2900a10 vmovl\.s16 q0, d0 +0[0-9a-f]+ <[^>]+> f2a00a10 vmovl\.s32 q0, d0 +0[0-9a-f]+ <[^>]+> f3880a10 vmovl\.u8 q0, d0 +0[0-9a-f]+ <[^>]+> f3900a10 vmovl\.u16 q0, d0 +0[0-9a-f]+ <[^>]+> f3a00a10 vmovl\.u32 q0, d0 +0[0-9a-f]+ <[^>]+> f3b20200 vmovn\.i16 d0, q0 +0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i32 d0, q0 +0[0-9a-f]+ <[^>]+> f3ba0200 vmovn\.i64 d0, q0 +0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i32 d0, q0 +0[0-9a-f]+ <[^>]+> f3b60200 vmovn\.i32 d0, q0 +0[0-9a-f]+ <[^>]+> f3b20280 vqmovn\.s16 d0, q0 +0[0-9a-f]+ <[^>]+> f3b60280 vqmovn\.s32 d0, q0 +0[0-9a-f]+ <[^>]+> f3ba0280 vqmovn\.s64 d0, q0 +0[0-9a-f]+ <[^>]+> f3b202c0 vqmovn\.u16 d0, q0 +0[0-9a-f]+ <[^>]+> f3b602c0 vqmovn\.u32 d0, q0 +0[0-9a-f]+ <[^>]+> f3ba02c0 vqmovn\.u64 d0, q0 +0[0-9a-f]+ <[^>]+> f3b20240 vqmovun\.s16 d0, q0 +0[0-9a-f]+ <[^>]+> f3b60240 vqmovun\.s32 d0, q0 +0[0-9a-f]+ <[^>]+> f3ba0240 vqmovun\.s64 d0, q0 +0[0-9a-f]+ <[^>]+> f3b201c2 vzip\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b201c2 vzip\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b20181 vzip\.8 d0, d1 +0[0-9a-f]+ <[^>]+> f3b601c2 vzip\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b601c2 vzip\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b60181 vzip\.16 d0, d1 +0[0-9a-f]+ <[^>]+> f3ba01c2 vzip\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba01c2 vzip\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba0081 vtrn\.32 d0, d1 +0[0-9a-f]+ <[^>]+> f3b20142 vuzp\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b20142 vuzp\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b20101 vuzp\.8 d0, d1 +0[0-9a-f]+ <[^>]+> f3b60142 vuzp\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b60142 vuzp\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b60101 vuzp\.16 d0, d1 +0[0-9a-f]+ <[^>]+> f3ba0142 vuzp\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba0142 vuzp\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba0081 vtrn\.32 d0, d1 +0[0-9a-f]+ <[^>]+> f3b00740 vqabs\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00740 vqabs\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00700 vqabs\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40740 vqabs\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40740 vqabs\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40700 vqabs\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80740 vqabs\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80740 vqabs\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80700 vqabs\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b007c0 vqneg\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b007c0 vqneg\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00780 vqneg\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b407c0 vqneg\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b407c0 vqneg\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40780 vqneg\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b807c0 vqneg\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b807c0 vqneg\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80780 vqneg\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00640 vpadal\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00640 vpadal\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00600 vpadal\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40640 vpadal\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40640 vpadal\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40600 vpadal\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80640 vpadal\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80640 vpadal\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80600 vpadal\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b006c0 vpadal\.u8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b006c0 vpadal\.u8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00680 vpadal\.u8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b406c0 vpadal\.u16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b406c0 vpadal\.u16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40680 vpadal\.u16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b806c0 vpadal\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b806c0 vpadal\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80680 vpadal\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00240 vpaddl\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00240 vpaddl\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00200 vpaddl\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40240 vpaddl\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40240 vpaddl\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40200 vpaddl\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80240 vpaddl\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80240 vpaddl\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80200 vpaddl\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b002c0 vpaddl\.u8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b002c0 vpaddl\.u8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00280 vpaddl\.u8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b402c0 vpaddl\.u16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b402c0 vpaddl\.u16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40280 vpaddl\.u16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b802c0 vpaddl\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b802c0 vpaddl\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80280 vpaddl\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0440 vrecpe\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0440 vrecpe\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0400 vrecpe\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb0540 vrecpe\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0540 vrecpe\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0500 vrecpe\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb04c0 vrsqrte\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb04c0 vrsqrte\.u32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0480 vrsqrte\.u32 d0, d0 +0[0-9a-f]+ <[^>]+> f3bb05c0 vrsqrte\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb05c0 vrsqrte\.f32 q0, q0 +0[0-9a-f]+ <[^>]+> f3bb0580 vrsqrte\.f32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00440 vcls\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00440 vcls\.s8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00400 vcls\.s8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b40440 vcls\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40440 vcls\.s16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40400 vcls\.s16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b80440 vcls\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80440 vcls\.s32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80400 vcls\.s32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b004c0 vclz\.i8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b004c0 vclz\.i8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00480 vclz\.i8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b404c0 vclz\.i16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b404c0 vclz\.i16 q0, q0 +0[0-9a-f]+ <[^>]+> f3b40480 vclz\.i16 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b804c0 vclz\.i32 q0, q0 +0[0-9a-f]+ <[^>]+> f3b80480 vclz\.i32 d0, d0 +0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00540 vcnt\.8 q0, q0 +0[0-9a-f]+ <[^>]+> f3b00500 vcnt\.8 d0, d0 +0[0-9a-f]+ <[^>]+> f3b20042 vswp q0, q1 +0[0-9a-f]+ <[^>]+> f3b20042 vswp q0, q1 +0[0-9a-f]+ <[^>]+> f3b20001 vswp d0, d1 +0[0-9a-f]+ <[^>]+> f3b200c2 vtrn\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b200c2 vtrn\.8 q0, q1 +0[0-9a-f]+ <[^>]+> f3b20081 vtrn\.8 d0, d1 +0[0-9a-f]+ <[^>]+> f3b600c2 vtrn\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b600c2 vtrn\.16 q0, q1 +0[0-9a-f]+ <[^>]+> f3b60081 vtrn\.16 d0, d1 +0[0-9a-f]+ <[^>]+> f3ba00c2 vtrn\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba00c2 vtrn\.32 q0, q1 +0[0-9a-f]+ <[^>]+> f3ba0081 vtrn\.32 d0, d1 +0[0-9a-f]+ <[^>]+> f3b00800 vtbl\.8 d0, {d0}, d0 +0[0-9a-f]+ <[^>]+> f3b00840 vtbx\.8 d0, {d0}, d0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-cov.s b/binutils-2.25/gas/testsuite/gas/arm/neon-cov.s new file mode 100644 index 00000000..04194a83 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-cov.s @@ -0,0 +1,666 @@ +@ Neon tests. Basic bitfield tests, using zero for as many registers/fields as +@ possible, but without causing instructions to be badly-formed. + + .arm + .syntax unified + .text + + .macro regs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + .macro dregs3_1 op vtype + \op\vtype d0,d0,d0 + .endm + + .macro regn3_1 op operand2 vtype + \op\vtype d0,q0,\operand2 + .endm + + .macro regl3_1 op operand2 vtype + \op\vtype q0,d0,\operand2 + .endm + + .macro regw3_1 op operand2 vtype + \op\vtype q0,q0,\operand2 + .endm + + .macro regs2_1 op opq vtype + \op\vtype q0,q0 + \opq\vtype q0,q0 + \op\vtype d0,d0 + .endm + + .macro regs3_su_32 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + .endm + + regs3_su_32 vaba vabaq + regs3_su_32 vhadd vhaddq + regs3_su_32 vrhadd vrhaddq + regs3_su_32 vhsub vhsubq + + .macro regs3_su_64 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .s64 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .u64 + .endm + + regs3_su_64 vqadd vqaddq + regs3_su_64 vqsub vqsubq + regs3_su_64 vrshl vrshlq + regs3_su_64 vqrshl vqrshlq + + regs3_su_64 vshl vshlq + regs3_su_64 vqshl vqshlq + + .macro regs2i_1 op opq imm vtype + \op\vtype q0,q0,\imm + \opq\vtype q0,q0,\imm + \op\vtype d0,d0,\imm + .endm + + .macro regs2i_su_64 op opq imm + regs2i_1 \op \opq \imm .s8 + regs2i_1 \op \opq \imm .s16 + regs2i_1 \op \opq \imm .s32 + regs2i_1 \op \opq \imm .s64 + regs2i_1 \op \opq \imm .u8 + regs2i_1 \op \opq \imm .u16 + regs2i_1 \op \opq \imm .u32 + regs2i_1 \op \opq \imm .u64 + .endm + + .macro regs2i_i_64 op opq imm + regs2i_1 \op \opq \imm .i8 + regs2i_1 \op \opq \imm .i16 + regs2i_1 \op \opq \imm .i32 + regs2i_1 \op \opq \imm .s32 + regs2i_1 \op \opq \imm .u32 + regs2i_1 \op \opq \imm .i64 + .endm + + regs2i_i_64 vshl vshlq 0 + regs2i_su_64 vqshl vqshlq 0 + + .macro regs3_ntyp op opq + regs3_1 \op \opq .8 + .endm + + regs3_ntyp vand vandq + regs3_ntyp vbic vbicq + regs3_ntyp vorr vorrq + regs3_ntyp vorn vornq + regs3_ntyp veor veorq + + .macro logic_imm_1 op opq imm vtype + \op\vtype q0,\imm + \opq\vtype q0,\imm + \op\vtype d0,\imm + .endm + + .macro logic_imm op opq + logic_imm_1 \op \opq 0x000000a5000000a5 .i64 + logic_imm_1 \op \opq 0x0000a5000000a500 .i64 + logic_imm_1 \op \opq 0x00a5000000a50000 .i64 + logic_imm_1 \op \opq 0xa5000000a5000000 .i64 + logic_imm_1 \op \opq 0x00a500a500a500a5 .i64 + logic_imm_1 \op \opq 0xa500a500a500a500 .i64 + logic_imm_1 \op \opq 0x000000ff .i32 + logic_imm_1 \op \opq 0x000000ff .s32 + logic_imm_1 \op \opq 0x000000ff .u32 + logic_imm_1 \op \opq 0x0000ff00 .i32 + logic_imm_1 \op \opq 0x00ff0000 .i32 + logic_imm_1 \op \opq 0xff000000 .i32 + logic_imm_1 \op \opq 0x00a500a5 .i32 + logic_imm_1 \op \opq 0xa500a500 .i32 + logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00 .i8 + .endm + + logic_imm vbic vbicq + logic_imm vorr vorrq + + .macro logic_inv_imm op opq + logic_imm_1 \op \opq 0xffffff5affffff5a .i64 + logic_imm_1 \op \opq 0xffff5affffff5aff .i64 + logic_imm_1 \op \opq 0xff5affffff5affff .i64 + logic_imm_1 \op \opq 0x5affffff5affffff .i64 + logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64 + logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64 + logic_imm_1 \op \opq 0xffffff00 .i32 + logic_imm_1 \op \opq 0xffffff00 .s32 + logic_imm_1 \op \opq 0xffffff00 .u32 + logic_imm_1 \op \opq 0xffff00ff .i32 + logic_imm_1 \op \opq 0xff00ffff .i32 + logic_imm_1 \op \opq 0x00ffffff .i32 + logic_imm_1 \op \opq 0xff5aff5a .i32 + logic_imm_1 \op \opq 0x5aff5aff .i32 + logic_imm_1 \op \opq 0xff00 .i16 + logic_imm_1 \op \opq 0x00ff .i16 + logic_imm_1 \op \opq 0xff .i8 + .endm + + logic_inv_imm vand vandq + logic_inv_imm vorn vornq + + regs3_ntyp vbsl vbslq + regs3_ntyp vbit vbitq + regs3_ntyp vbif vbifq + + .macro regs3_suf_32 op opq + regs3_1 \op \opq .s8 + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u8 + regs3_1 \op \opq .u16 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + .endm + + .macro regs3_if_32 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + .endm + + regs3_suf_32 vabd vabdq + regs3_suf_32 vmax vmaxq + regs3_suf_32 vmin vminq + + regs3_suf_32 vcge vcgeq + regs3_suf_32 vcgt vcgtq + regs3_suf_32 vcle vcleq + regs3_suf_32 vclt vcltq + + regs3_if_32 vceq vceqq + + .macro regs2i_sf_0 op opq + regs2i_1 \op \opq 0 .s8 + regs2i_1 \op \opq 0 .s16 + regs2i_1 \op \opq 0 .s32 + regs2i_1 \op \opq 0 .f32 + .endm + + regs2i_sf_0 vcge vcgeq + regs2i_sf_0 vcgt vcgtq + regs2i_sf_0 vcle vcleq + regs2i_sf_0 vclt vcltq + + .macro regs2i_if_0 op opq + regs2i_1 \op \opq 0 .i8 + regs2i_1 \op \opq 0 .i16 + regs2i_1 \op \opq 0 .i32 + regs2i_1 \op \opq 0 .s32 + regs2i_1 \op \opq 0 .u32 + regs2i_1 \op \opq 0 .f32 + .endm + + regs2i_if_0 vceq vceqq + + .macro dregs3_suf_32 op + dregs3_1 \op .s8 + dregs3_1 \op .s16 + dregs3_1 \op .s32 + dregs3_1 \op .u8 + dregs3_1 \op .u16 + dregs3_1 \op .u32 + dregs3_1 \op .f32 + .endm + + dregs3_suf_32 vpmax + dregs3_suf_32 vpmin + + .macro sregs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + .macro sclr21_1 op opq vtype + \op\vtype q0,q0,d0[0] + \opq\vtype q0,q0,d0[0] + \op\vtype d0,d0,d0[0] + .endm + + .macro mul_incl_scalar op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + sclr21_1 \op \opq .i16 + sclr21_1 \op \opq .i32 + sclr21_1 \op \opq .s32 + sclr21_1 \op \opq .u32 + sclr21_1 \op \opq .f32 + .endm + + mul_incl_scalar vmla vmlaq + mul_incl_scalar vmls vmlsq + + .macro dregs3_if_32 op + dregs3_1 \op .i8 + dregs3_1 \op .i16 + dregs3_1 \op .i32 + dregs3_1 \op .s32 + dregs3_1 \op .u32 + dregs3_1 \op .f32 + .endm + + dregs3_if_32 vpadd + + .macro regs3_if_64 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .i64 + regs3_1 \op \opq .f32 + .endm + + regs3_if_64 vadd vaddq + regs3_if_64 vsub vsubq + + .macro regs3_sz_32 op opq + regs3_1 \op \opq .8 + regs3_1 \op \opq .16 + regs3_1 \op \opq .32 + .endm + + regs3_sz_32 vtst vtstq + + .macro regs3_ifp_32 op opq + regs3_1 \op \opq .i8 + regs3_1 \op \opq .i16 + regs3_1 \op \opq .i32 + regs3_1 \op \opq .s32 + regs3_1 \op \opq .u32 + regs3_1 \op \opq .f32 + regs3_1 \op \opq .p8 + .endm + + regs3_ifp_32 vmul vmulq + + .macro dqmulhs op opq + regs3_1 \op \opq .s16 + regs3_1 \op \opq .s32 + sclr21_1 \op \opq .s16 + sclr21_1 \op \opq .s32 + .endm + + dqmulhs vqdmulh vqdmulhq + dqmulhs vqrdmulh vqrdmulhq + + regs3_1 vacge vacgeq .f32 + regs3_1 vacgt vacgtq .f32 + regs3_1 vacle vacleq .f32 + regs3_1 vaclt vacltq .f32 + regs3_1 vrecps vrecpsq .f32 + regs3_1 vrsqrts vrsqrtsq .f32 + + .macro regs2_sf_32 op opq + regs2_1 \op \opq .s8 + regs2_1 \op \opq .s16 + regs2_1 \op \opq .s32 + regs2_1 \op \opq .f32 + .endm + + regs2_sf_32 vabs vabsq + regs2_sf_32 vneg vnegq + + .macro rshift_imm op opq + regs2i_1 \op \opq 7 .s8 + regs2i_1 \op \opq 15 .s16 + regs2i_1 \op \opq 31 .s32 + regs2i_1 \op \opq 63 .s64 + regs2i_1 \op \opq 7 .u8 + regs2i_1 \op \opq 15 .u16 + regs2i_1 \op \opq 31 .u32 + regs2i_1 \op \opq 63 .u64 + .endm + + rshift_imm vshr vshrq + rshift_imm vrshr vrshrq + rshift_imm vsra vsraq + rshift_imm vrsra vrsraq + + regs2i_1 vsli vsliq 0 .8 + regs2i_1 vsli vsliq 0 .16 + regs2i_1 vsli vsliq 0 .32 + regs2i_1 vsli vsliq 0 .64 + + regs2i_1 vsri vsriq 7 .8 + regs2i_1 vsri vsriq 15 .16 + regs2i_1 vsri vsriq 31 .32 + regs2i_1 vsri vsriq 63 .64 + + regs2i_1 vqshlu vqshluq 0 .s8 + regs2i_1 vqshlu vqshluq 0 .s16 + regs2i_1 vqshlu vqshluq 0 .s32 + regs2i_1 vqshlu vqshluq 0 .s64 + + .macro qrshift_imm op + regn3_1 \op 7 .s16 + regn3_1 \op 15 .s32 + regn3_1 \op 31 .s64 + regn3_1 \op 7 .u16 + regn3_1 \op 15 .u32 + regn3_1 \op 31 .u64 + .endm + + .macro qrshiftu_imm op + regn3_1 \op 7 .s16 + regn3_1 \op 15 .s32 + regn3_1 \op 31 .s64 + .endm + + .macro qrshifti_imm op + regn3_1 \op 7 .i16 + regn3_1 \op 15 .i32 + regn3_1 \op 15 .s32 + regn3_1 \op 15 .u32 + regn3_1 \op 31 .i64 + .endm + + qrshift_imm vqshrn + qrshift_imm vqrshrn + qrshiftu_imm vqshrun + qrshiftu_imm vqrshrun + + qrshifti_imm vshrn + qrshifti_imm vrshrn + + regl3_1 vshll 1 .s8 + regl3_1 vshll 1 .s16 + regl3_1 vshll 1 .s32 + regl3_1 vshll 1 .u8 + regl3_1 vshll 1 .u16 + regl3_1 vshll 1 .u32 + + regl3_1 vshll 8 .i8 + regl3_1 vshll 16 .i16 + regl3_1 vshll 32 .i32 + regl3_1 vshll 32 .s32 + regl3_1 vshll 32 .u32 + + .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32" + \op\t1 \opr,\opr\arg + \op\t2 \opr,\opr\arg + \op\t3 \opr,\opr\arg + \op\t4 \opr,\opr\arg + .endm + + convert vcvt q0 + convert vcvtq q0 + convert vcvt d0 + convert vcvt q0 ",1" + convert vcvtq q0 ",1" + convert vcvt d0 ",1" + + vmov q0,q0 + vmov d0,d0 + vmov.8 d0[0],r0 + vmov.16 d0[0],r0 + vmov.32 d0[0],r0 + vmov d0,r0,r0 + vmov.s8 r0,d0[0] + vmov.s16 r0,d0[0] + vmov.u8 r0,d0[0] + vmov.u16 r0,d0[0] + vmov.32 r0,d0[0] + vmov r0,r1,d0 + + .macro mov_imm op imm vtype + \op\vtype q0,\imm + \op\vtype d0,\imm + .endm + + mov_imm vmov 0x00000077 .i32 + mov_imm vmov 0x00000077 .s32 + mov_imm vmov 0x00000077 .u32 + mov_imm vmvn 0x00000077 .i32 + mov_imm vmvn 0x00000077 .s32 + mov_imm vmvn 0x00000077 .u32 + mov_imm vmov 0x00007700 .i32 + mov_imm vmvn 0x00007700 .i32 + mov_imm vmov 0x00770000 .i32 + mov_imm vmvn 0x00770000 .i32 + mov_imm vmov 0x77000000 .i32 + mov_imm vmvn 0x77000000 .i32 + mov_imm vmov 0x0077 .i16 + mov_imm vmvn 0x0077 .i16 + mov_imm vmov 0x7700 .i16 + mov_imm vmvn 0x7700 .i16 + mov_imm vmov 0x000077ff .i32 + mov_imm vmvn 0x000077ff .i32 + mov_imm vmov 0x0077ffff .i32 + mov_imm vmvn 0x0077ffff .i32 + mov_imm vmov 0x77 .i8 + mov_imm vmov 0xff0000ff000000ff .i64 + mov_imm vmov 4.25 .f32 + + mov_imm vmov 0xa5a5 .i16 + mov_imm vmvn 0xa5a5 .i16 + mov_imm vmov 0xa5a5a5a5 .i32 + mov_imm vmvn 0xa5a5a5a5 .i32 + mov_imm vmov 0x00a500a5 .i32 + mov_imm vmov 0xa500a500 .i32 + mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64 + mov_imm vmov 0x00a500a500a500a5 .i64 + mov_imm vmov 0xa500a500a500a500 .i64 + mov_imm vmov 0x000000a5000000a5 .i64 + mov_imm vmov 0x0000a5000000a500 .i64 + mov_imm vmov 0x00a5000000a50000 .i64 + mov_imm vmov 0xa5000000a5000000 .i64 + mov_imm vmov 0x0000a5ff0000a5ff .i64 + mov_imm vmov 0x00a5ffff00a5ffff .i64 + mov_imm vmov 0xa5ffffffa5ffffff .i64 + + vmvn q0,q0 + vmvnq q0,q0 + vmvn d0,d0 + + .macro long_ops op + regl3_1 \op d0 .s8 + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op d0 .u8 + regl3_1 \op d0 .u16 + regl3_1 \op d0 .u32 + .endm + + long_ops vabal + long_ops vabdl + long_ops vaddl + long_ops vsubl + + .macro long_mac op + regl3_1 \op d0 .s8 + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op d0 .u8 + regl3_1 \op d0 .u16 + regl3_1 \op d0 .u32 + regl3_1 \op "d0[0]" .s16 + regl3_1 \op "d0[0]" .s32 + regl3_1 \op "d0[0]" .u16 + regl3_1 \op "d0[0]" .u32 + .endm + + long_mac vmlal + long_mac vmlsl + + .macro wide_ops op + regw3_1 \op d0 .s8 + regw3_1 \op d0 .s16 + regw3_1 \op d0 .s32 + regw3_1 \op d0 .u8 + regw3_1 \op d0 .u16 + regw3_1 \op d0 .u32 + .endm + + wide_ops vaddw + wide_ops vsubw + + .macro narr_ops op + regn3_1 \op q0 .i16 + regn3_1 \op q0 .i32 + regn3_1 \op q0 .s32 + regn3_1 \op q0 .u32 + regn3_1 \op q0 .i64 + .endm + + narr_ops vaddhn + narr_ops vraddhn + narr_ops vsubhn + narr_ops vrsubhn + + .macro long_dmac op + regl3_1 \op d0 .s16 + regl3_1 \op d0 .s32 + regl3_1 \op "d0[0]" .s16 + regl3_1 \op "d0[0]" .s32 + .endm + + long_dmac vqdmlal + long_dmac vqdmlsl + long_dmac vqdmull + + regl3_1 vmull d0 .s8 + regl3_1 vmull d0 .s16 + regl3_1 vmull d0 .s32 + regl3_1 vmull d0 .u8 + regl3_1 vmull d0 .u16 + regl3_1 vmull d0 .u32 + regl3_1 vmull d0 .p8 + regl3_1 vmull "d0[0]" .s16 + regl3_1 vmull "d0[0]" .s32 + regl3_1 vmull "d0[0]" .u16 + regl3_1 vmull "d0[0]" .u32 + + vext.8 q0,q0,q0,0 + vextq.8 q0,q0,q0,0 + vext.8 d0,d0,d0,0 + vext.8 q0,q0,q0,8 + + .macro revs op opq vtype + \op\vtype q0,q0 + \opq\vtype q0,q0 + \op\vtype d0,d0 + .endm + + revs vrev64 vrev64q .8 + revs vrev64 vrev64q .16 + revs vrev64 vrev64q .32 + revs vrev32 vrev32q .8 + revs vrev32 vrev32q .16 + revs vrev16 vrev16q .8 + + .macro dups op opq vtype + \op\vtype q0,r0 + \opq\vtype q0,r0 + \op\vtype d0,r0 + \op\vtype q0,d0[0] + \opq\vtype q0,d0[0] + \op\vtype d0,d0[0] + .endm + + dups vdup vdupq .8 + dups vdup vdupq .16 + dups vdup vdupq .32 + + .macro binop_3typ op op1 op2 t1 t2 t3 + \op\t1 \op1,\op2 + \op\t2 \op1,\op2 + \op\t3 \op1,\op2 + .endm + + binop_3typ vmovl q0 d0 .s8 .s16 .s32 + binop_3typ vmovl q0 d0 .u8 .u16 .u32 + binop_3typ vmovn d0 q0 .i16 .i32 .i64 + vmovn.s32 d0, q0 + vmovn.u32 d0, q0 + binop_3typ vqmovn d0 q0 .s16 .s32 .s64 + binop_3typ vqmovn d0 q0 .u16 .u32 .u64 + binop_3typ vqmovun d0 q0 .s16 .s32 .s64 + + .macro binops op opq vtype="" rhs="0" + \op\vtype q0,q\rhs + \opq\vtype q0,q\rhs + \op\vtype d0,d\rhs + .endm + + .macro regs2_sz_32 op opq + binops \op \opq .8 1 + binops \op \opq .16 1 + binops \op \opq .32 1 + .endm + + regs2_sz_32 vzip vzipq + regs2_sz_32 vuzp vuzpq + + .macro regs2_s_32 op opq + binops \op \opq .s8 + binops \op \opq .s16 + binops \op \opq .s32 + .endm + + regs2_s_32 vqabs vqabsq + regs2_s_32 vqneg vqnegq + + .macro regs2_su_32 op opq + regs2_s_32 \op \opq + binops \op \opq .u8 + binops \op \opq .u16 + binops \op \opq .u32 + .endm + + regs2_su_32 vpadal vpadalq + regs2_su_32 vpaddl vpaddlq + + binops vrecpe vrecpeq .u32 + binops vrecpe vrecpeq .f32 + binops vrsqrte vrsqrteq .u32 + binops vrsqrte vrsqrteq .f32 + + regs2_s_32 vcls vclsq + + .macro regs2_i_32 op opq + binops \op \opq .i8 + binops \op \opq .i16 + binops \op \opq .i32 + binops \op \opq .s32 + binops \op \opq .u32 + .endm + + regs2_i_32 vclz vclzq + + binops vcnt vcntq .8 + + binops vswp vswpq "" 1 + + regs2_sz_32 vtrn vtrnq + + vtbl.8 d0,{d0},d0 + vtbx.8 d0,{d0},d0 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-fma-cov.d b/binutils-2.25/gas/testsuite/gas/arm/neon-fma-cov.d new file mode 100644 index 00000000..1c51d7bf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-fma-cov.d @@ -0,0 +1,13 @@ +# name: Neon FMA instruction coverage +# as: -mfpu=neon-vfpv4 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f2000c50 vfma\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000c50 vfma\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2000c10 vfma\.f32 d0, d0, d0 +0[0-9a-f]+ <[^>]+> f2200c50 vfms\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200c50 vfms\.f32 q0, q0, q0 +0[0-9a-f]+ <[^>]+> f2200c10 vfms\.f32 d0, d0, d0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-fma-cov.s b/binutils-2.25/gas/testsuite/gas/arm/neon-fma-cov.s new file mode 100644 index 00000000..db34807d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-fma-cov.s @@ -0,0 +1,12 @@ + .arm + .syntax unified + .text + + .macro regs3_1 op opq vtype + \op\vtype q0,q0,q0 + \opq\vtype q0,q0,q0 + \op\vtype d0,d0,d0 + .endm + + regs3_1 vfma vfma .f32 + regs3_1 vfms vfms .f32 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.d b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.d new file mode 100644 index 00000000..28ebb9d4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.d @@ -0,0 +1,3 @@ +# name: Bad alignment in Advanced SIMD Neon instructions +# as: -mfpu=neon +# error-output: neon-ldst-align-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.l b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.l new file mode 100644 index 00000000..5d32ace8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: bad alignment -- `vld1.8 {d0},\[r0:128\]' +[^:]*:2: Error: bad alignment -- `vld1.8 {q0},\[r0:256\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.s b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.s new file mode 100644 index 00000000..a899f810 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-align-bad.s @@ -0,0 +1,2 @@ +vld1.8 {d0}, [r0 :128] +vld1.8 {q0}, [r0 :256] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.d b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.d new file mode 100644 index 00000000..576ee7aa --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.d @@ -0,0 +1,3 @@ +# name: Bad element size combinations in Neon load/store instructions +# as: -mfpu=neon +# error-output: neon-ldst-es-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.l b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.l new file mode 100644 index 00000000..b0c854ee --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.l @@ -0,0 +1,12 @@ +[^:]*: Assembler messages: +[^:]*:2: Error: bad type in Neon instruction -- `vld1\.64 {d0\[1\]},\[r0\]' +[^:]*:3: Error: bad type in Neon instruction -- `vld1\.64 {d0\[\]},\[r0\]' +[^:]*:4: Error: bad type in Neon instruction -- `vld2\.64 {d0\[1\]},\[r0\]' +[^:]*:5: Error: bad type in Neon instruction -- `vld2\.64 {d0\[\]},\[r0\]' +[^:]*:6: Error: bad element type for instruction -- `vld2\.64 {d0-d1},\[r0\]' +[^:]*:7: Error: bad type in Neon instruction -- `vld3\.64 {d0\[1\]},\[r0\]' +[^:]*:8: Error: bad type in Neon instruction -- `vld3\.64 {d0\[\]},\[r0\]' +[^:]*:9: Error: bad element type for instruction -- `vld3\.64 {d0-d2},\[r0\]' +[^:]*:10: Error: bad type in Neon instruction -- `vld4\.64 {d0\[1\]},\[r0\]' +[^:]*:11: Error: bad type in Neon instruction -- `vld4\.64 {d0\[\]},\[r0\]' +[^:]*:12: Error: bad element type for instruction -- `vld4\.64 {d0-d3},\[r0\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.s b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.s new file mode 100644 index 00000000..f7e335e0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es-bad.s @@ -0,0 +1,12 @@ + .text + vld1.64 {d0[1]}, [r0] + vld1.64 {d0[]}, [r0] + vld2.64 {d0[1]}, [r0] + vld2.64 {d0[]}, [r0] + vld2.64 {d0-d1}, [r0] + vld3.64 {d0[1]}, [r0] + vld3.64 {d0[]}, [r0] + vld3.64 {d0-d2}, [r0] + vld4.64 {d0[1]}, [r0] + vld4.64 {d0[]}, [r0] + vld4.64 {d0-d3}, [r0] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es.d b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es.d new file mode 100644 index 00000000..e9c07347 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es.d @@ -0,0 +1,60 @@ +# name: Neon element and structure loads and stores +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> f406282f vst2\.8 {d2-d3}, \[r6 :128\] +0[0-9a-f]+ <[^>]+> f427140d vld3\.8 {d1-d3}, \[r7\]! +0[0-9a-f]+ <[^>]+> f4091553 vst3\.16 {d1,d3,d5}, \[r9 :64\], r3 +0[0-9a-f]+ <[^>]+> f42a208f vld4\.32 {d2-d5}, \[sl\] +0[0-9a-f]+ <[^>]+> f40a114f vst4\.16 {d1,d3,d5,d7}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa1c6f vld1\.16 {d1\[\]-d2\[\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa1c5f vld1\.16 {d1\[\]}, \[sl :16\] +0[0-9a-f]+ <[^>]+> f4aa1dbf vld2\.32 {d1\[\],d3\[\]}, \[sl :64\] +0[0-9a-f]+ <[^>]+> f4aa3e0c vld3\.8 {d3\[\]-d5\[\]}, \[sl\], ip +0[0-9a-f]+ <[^>]+> f4a9af6d vld4\.16 {d10\[\],d12\[\],d14\[\],d16\[\]}, \[r9\]! +0[0-9a-f]+ <[^>]+> f4a9af5f vld4\.16 {d10\[\]-d13\[\]}, \[r9 :64\] +0[0-9a-f]+ <[^>]+> f4a9af9f vld4\.32 {d10\[\]-d13\[\]}, \[r9 :64\] +0[0-9a-f]+ <[^>]+> f4a9afdf vld4\.32 {d10\[\]-d13\[\]}, \[r9 :128\] +0[0-9a-f]+ <[^>]+> f4a530ed vld1\.8 {d3\[7\]}, \[r5\]! +0[0-9a-f]+ <[^>]+> f48554df vst1\.16 {d5\[3\]}, \[r5 :16\] +0[0-9a-f]+ <[^>]+> f4a535dd vld2\.16 {d3\[3\],d4\[3\]}, \[r5 :32\]! +0[0-9a-f]+ <[^>]+> f4858a83 vst3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r5\], r3 +0[0-9a-f]+ <[^>]+> f4a7804f vld1\.8 {d8\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7848f vld1\.16 {d8\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7849f vld1\.16 {d8\[2\]}, \[r7 :16\] +0[0-9a-f]+ <[^>]+> f4a7888f vld1\.32 {d8\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a788bf vld1\.32 {d8\[1\]}, \[r7 :32\] +0[0-9a-f]+ <[^>]+> f4a7812f vld2\.8 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7813f vld2\.8 {d8\[1\],d9\[1\]}, \[r7 :16\] +0[0-9a-f]+ <[^>]+> f4a7854f vld2\.16 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7855f vld2\.16 {d8\[1\],d9\[1\]}, \[r7 :32\] +0[0-9a-f]+ <[^>]+> f4a7856f vld2\.16 {d8\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7857f vld2\.16 {d8\[1\],d10\[1\]}, \[r7 :32\] +0[0-9a-f]+ <[^>]+> f4a7898f vld2\.32 {d8\[1\],d9\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7899f vld2\.32 {d8\[1\],d9\[1\]}, \[r7 :64\] +0[0-9a-f]+ <[^>]+> f4a789cf vld2\.32 {d8\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a789df vld2\.32 {d8\[1\],d10\[1\]}, \[r7 :64\] +0[0-9a-f]+ <[^>]+> f4a7822f vld3\.8 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7864f vld3\.16 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7866f vld3\.16 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78a8f vld3\.32 {d8\[1\],d9\[1\],d10\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78acf vld3\.32 {d8\[1\],d10\[1\],d12\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7834f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7835f vld4\.8 {d8\[2\],d9\[2\],d10\[2\],d11\[2\]}, \[r7 :32\] +0[0-9a-f]+ <[^>]+> f4a7876f vld4\.16 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a7875f vld4\.16 {d8\[1\],d9\[1\],d10\[1\],d11\[1\]}, \[r7 :64\] +0[0-9a-f]+ <[^>]+> f4a78bcf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a78bdf vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7 :64\] +0[0-9a-f]+ <[^>]+> f4a78bef vld4\.32 {d8\[1\],d10\[1\],d12\[1\],d14\[1\]}, \[r7 :128\] +0[0-9a-f]+ <[^>]+> f3b43805 vtbl\.8 d3, {d4}, d5 +0[0-9a-f]+ <[^>]+> f3b23b05 vtbl\.8 d3, {d2-d5}, d5 +0[0-9a-f]+ <[^>]+> f3be3985 vtbl\.8 d3, {d30-d31}, d5 +0[0-9a-f]+ <[^>]+> f427288f vld2\.32 {d2-d3}, \[r7\] +0[0-9a-f]+ <[^>]+> f427208f vld4\.32 {d2-d5}, \[r7\] +0[0-9a-f]+ <[^>]+> f467c08f vld4\.32 {d28-d31}, \[r7\] +0[0-9a-f]+ <[^>]+> f4a21c83 vld1\.32 {d1\[\]}, \[r2\], r3 +0[0-9a-f]+ <[^>]+> f42007cf vld1\.64 {d0}, \[r0\] +0[0-9a-f]+ <[^>]+> f42002cf vld1\.64 {d0-d3}, \[r0\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es.s b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es.s new file mode 100644 index 00000000..cb93f061 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-es.s @@ -0,0 +1,65 @@ +@ test element and structure loads and stores. + + .text + .arm + .syntax unified + + vst2.8 {d2,d3},[r6,:128] + vld3.8 {d1,d2,d3},[r7]! + vst3.16 {d1,d3,d5},[r9:64],r3 + vld4.32 {d2,d3,d4,d5},[r10] + vst4.16 {d1,d3,d5,d7},[r10] + vld1.16 {d1[],d2[]},[r10] + vld1.16 {d1[]},[r10,:16] + vld2.32 {d1[],d3[]},[r10:64] + vld3.s8 {d3[],d4[],d5[]},[r10],r12 + vld4.16 {d10[],d12[],d14[],d16[]},[r9]! + vld4.16 {d10[],d11[],d12[],d13[]},[r9,:64] + vld4.32 {d10[],d11[],d12[],d13[]},[r9,:64] + vld4.32 {d10[],d11[],d12[],d13[]},[r9,:128] + vld1.8 {d3[7]},[r5]! + vst1.16 {d5[3]},[r5,:16] + vld2.16 {d3[3],d4[3]},[r5,:32]! + vst3.32 {d8[1],d9[1],d10[1]},[r5],r3 + + vld1.8 {d8[2]},[r7] + vld1.16 {d8[2]},[r7] + vld1.16 {d8[2]},[r7:16] + vld1.32 {d8[1]},[r7] + vld1.32 {d8[1]},[r7:32] + vld2.8 {d8[1],d9[1]},[r7] + vld2.8 {d8[1],d9[1]},[r7:16] + vld2.16 {d8[1],d9[1]},[r7] + vld2.16 {d8[1],d9[1]},[r7:32] + vld2.16 {d8[1],d10[1]},[r7] + vld2.16 {d8[1],d10[1]},[r7:32] + vld2.32 {d8[1],d9[1]},[r7] + vld2.32 {d8[1],d9[1]},[r7:64] + vld2.32 {d8[1],d10[1]},[r7] + vld2.32 {d8[1],d10[1]},[r7:64] + vld3.8 {d8[1],d9[1],d10[1]},[r7] + vld3.16 {d8[1],d9[1],d10[1]},[r7] + vld3.16 {d8[1],d10[1],d12[1]},[r7] + vld3.32 {d8[1],d9[1],d10[1]},[r7] + vld3.32 {d8[1],d10[1],d12[1]},[r7] + vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7] + vld4.8 {d8[2],d9[2],d10[2],d11[2]},[r7:32] + vld4.16 {d8[1],d10[1],d12[1],d14[1]},[r7] + vld4.16 {d8[1],d9[1],d10[1],d11[1]},[r7:64] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7:64] + vld4.32 {d8[1],d10[1],d12[1],d14[1]},[r7:128] + + vtbl.8 d3,{d4},d5 + vtbl.8 d3,{q1-q2},d5 + vtbl.8 d3,{q15},d5 + + vld2.32 {q1},[r7] + vld4.32 {q1-q2},[r7] + vld4.32 {q14-q15},[r7] + + @ PR 14987 and 14887: Allow for whitespace in the instruction. + vld1.32 { d1 [ ] } , [ r2 ] , r3 + + vld1.64 {d0}, [r0] + vld1.64 {d0-d3}, [r0] diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-rm.d b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-rm.d new file mode 100644 index 00000000..813672cd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-rm.d @@ -0,0 +1,63 @@ +# name: Neon single and multiple register loads and stores +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ec922b02 vldmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec922b04 vldmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec924b08 vldmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecd28b10 vldmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec923b20 vldmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ecb22b02 vldmia r2!, {d2} +0[0-9a-f]+ <[^>]+> ecb22b04 vldmia r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ecb24b08 vldmia r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ecf28b10 vldmia r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ecb23b20 vldmia r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ed322b02 vldmdb r2!, {d2} +0[0-9a-f]+ <[^>]+> ed322b04 vldmdb r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ed324b08 vldmdb r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ed728b10 vldmdb r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ed323b20 vldmdb r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> ec822b02 vstmia r2, {d2} +0[0-9a-f]+ <[^>]+> ec822b04 vstmia r2, {d2-d3} +0[0-9a-f]+ <[^>]+> ec824b08 vstmia r2, {d4-d7} +0[0-9a-f]+ <[^>]+> ecc28b10 vstmia r2, {d24-d31} +0[0-9a-f]+ <[^>]+> ec823b20 vstmia r2, {d3-d18} +0[0-9a-f]+ <[^>]+> eca22b02 vstmia r2!, {d2} +0[0-9a-f]+ <[^>]+> eca22b04 vstmia r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> eca24b08 vstmia r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ece28b10 vstmia r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> eca23b20 vstmia r2!, {d3-d18} +0[0-9a-f]+ <[^>]+> ed222b02 vstmdb r2!, {d2} +0[0-9a-f]+ <[^>]+> ed222b04 vstmdb r2!, {d2-d3} +0[0-9a-f]+ <[^>]+> ed224b08 vstmdb r2!, {d4-d7} +0[0-9a-f]+ <[^>]+> ed628b10 vstmdb r2!, {d24-d31} +0[0-9a-f]+ <[^>]+> ed223b20 vstmdb r2!, {d3-d18} +0[0-9a-f]+ <backward> 000001f4 .* +0[0-9a-f]+ <[^>]+> eddf6b0b vldr d22, \[pc, #44\] ; 0[0-9a-f]+ <forward> +0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed135b01 vldr d5, \[r3, #-4\] +0[0-9a-f]+ <[^>]+> ed935b01 vldr d5, \[r3, #4\] +0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed035b01 vstr d5, \[r3, #-4\] +0[0-9a-f]+ <[^>]+> ed835b01 vstr d5, \[r3, #4\] +0[0-9a-f]+ <[^>]+> ed935b00 vldr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed135b40 vldr d5, \[r3, #-256\].* +0[0-9a-f]+ <[^>]+> ed935b40 vldr d5, \[r3, #256\].* +0[0-9a-f]+ <[^>]+> ed835b00 vstr d5, \[r3\] +0[0-9a-f]+ <[^>]+> ed035b40 vstr d5, \[r3, #-256\].* +0[0-9a-f]+ <[^>]+> ed835b40 vstr d5, \[r3, #256\].* +0[0-9a-f]+ <forward> 000002bc .* +0[0-9a-f]+ <[^>]+> ed1f7b11 vldr d7, \[pc, #-68\] ; 0[0-9a-f]+ <backward> diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-rm.s b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-rm.s new file mode 100644 index 00000000..f9421ac5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-ldst-rm.s @@ -0,0 +1,44 @@ +@ test register and multi-register loads and stores. + + .text + .arm + .syntax unified + + .macro multi op dir="" wb="" + \op\dir r2\wb,{d2} + \op\dir r2\wb,{d2-d3} + \op\dir r2\wb,{q2-q3} + \op\dir r2\wb,{q12-q14,q15} + \op\dir r2\wb,{d3,d4,d5-d8,d9,d10,d11,d12-d16,d17-d18} + .endm + + multi vldm + multi vldm ia + multi vldm ia "!" + multi vldm db "!" + + multi vstm + multi vstm ia + multi vstm ia "!" + multi vstm db "!" + +backward: + .word 500 + + .macro single op offset="" + \op d5,[r3] + \op d5,[r3,#-\offset] + \op d5,[r3,#\offset] + .endm + + vldr d22, forward + + single vldr 4 + single vstr 4 + single vldr 256 + single vstr 256 + +forward: + .word 700 + + vldr d7, backward diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-logic.d b/binutils-2.25/gas/testsuite/gas/arm/neon-logic.d new file mode 100644 index 00000000..8e997fac --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-logic.d @@ -0,0 +1,16 @@ +# name: Neon logic insns with two and three operands including imm. values +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + + +Disassembly of section \.text: +00000000 <.text> f387015f vorr.i32 q0, #255 ; 0x000000ff +00000004 <.text\+0x4> f387015f vorr.i32 q0, #255 ; 0x000000ff +00000008 <.text\+0x8> f2220154 vorr q0, q1, q2 +0000000c <.text\+0xc> f2200152 vorr q0, q0, q1 +00000010 <.text\+0x10> f387011f vorr.i32 d0, #255 ; 0x000000ff +00000014 <.text\+0x14> f387011f vorr.i32 d0, #255 ; 0x000000ff +00000018 <.text\+0x18> f2210112 vorr d0, d1, d2 +0000001c <.text\+0x1c> f2200111 vorr d0, d0, d1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-logic.s b/binutils-2.25/gas/testsuite/gas/arm/neon-logic.s new file mode 100644 index 00000000..20fc1341 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-logic.s @@ -0,0 +1,9 @@ +.syntax unified +vorr.i32 q0, q0, #0xff +vorr.i32 q0, #0xff +vorr.i32 q0, q1, q2 +vorr.i32 q0, q1 +vorr.i32 d0, d0, #0xff +vorr.i32 d0, #0xff +vorr.i32 d0, d1, d2 +vorr.i32 d0, d1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-omit.d b/binutils-2.25/gas/testsuite/gas/arm/neon-omit.d new file mode 100644 index 00000000..540f453b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-omit.d @@ -0,0 +1,98 @@ +# name: Neon optional register operands +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f3022746 vabd\.u8 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f26cc0c6 vhadd\.s32 q14, q14, q3 +0[0-9a-f]+ <[^>]+> f2222144 vrhadd\.s32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f22aa24e vhsub\.s32 q5, q5, q7 +0[0-9a-f]+ <[^>]+> f3186446 vshl\.u16 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f32ca45a vqshl\.u32 q5, q5, q6 +0[0-9a-f]+ <[^>]+> f20ee170 vand q7, q7, q8 +0[0-9a-f]+ <[^>]+> f30ee170 veor q7, q7, q8 +0[0-9a-f]+ <[^>]+> f3b5a14a vceq\.i16 q5, q5, #0 +0[0-9a-f]+ <[^>]+> f31aa85a vceq\.i16 q5, q5, q5 +0[0-9a-f]+ <[^>]+> f3b5a24a vclt\.s16 q5, q5, #0 +0[0-9a-f]+ <[^>]+> f3b5a34c vabs\.s16 q5, q6 +0[0-9a-f]+ <[^>]+> f3b57388 vneg\.s16 d7, d8 +0[0-9a-f]+ <[^>]+> f3b97708 vabs\.f32 d7, d8 +0[0-9a-f]+ <[^>]+> f3f927e4 vneg\.f32 q9, q10 +0[0-9a-f]+ <[^>]+> f2211a03 vpmax\.s32 d1, d1, d3 +0[0-9a-f]+ <[^>]+> f2255a17 vpmin\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f3011f03 vpmax\.f32 d1, d1, d3 +0[0-9a-f]+ <[^>]+> f3255f07 vpmin\.f32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f2122b46 vqdmulh\.s16 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f3255b07 vqrdmulh\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f3922c6d vqdmulh\.s16 q1, q1, d5\[3\] +0[0-9a-f]+ <[^>]+> f2122056 vqadd\.s16 q1, q1, q3 +0[0-9a-f]+ <[^>]+> f2255017 vqadd\.s32 d5, d5, d7 +0[0-9a-f]+ <[^>]+> f2222944 vmla\.i32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f2133b14 vpadd\.i16 d3, d3, d4 +0[0-9a-f]+ <[^>]+> f3266948 vmls\.i32 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f3022e54 vacge\.f32 q1, q1, q2 +0[0-9a-f]+ <[^>]+> f3266e58 vacgt\.f32 q3, q3, q4 +0[0-9a-f]+ <[^>]+> f30cae5a vacge\.f32 q5, q6, q5 +0[0-9a-f]+ <[^>]+> f320eede vacgt\.f32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f32ee370 vcge\.u32 q7, q7, q8 +0[0-9a-f]+ <[^>]+> f32ee360 vcgt\.u32 q7, q7, q8 +0[0-9a-f]+ <[^>]+> f320e3de vcge\.u32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f320e3ce vcgt\.u32 q7, q8, q7 +0[0-9a-f]+ <[^>]+> f3a22102 vaddw\.u32 q1, q1, d2 +0[0-9a-f]+ <[^>]+> f2a66304 vsubw\.s32 q3, q3, d4 +0[0-9a-f]+ <[^>]+> f2244856 vtst\.32 q2, q2, q3 +0[0-9a-f]+ <[^>]+> f2011f12 vrecps\.f32 d1, d1, d2 +0[0-9a-f]+ <[^>]+> f29c2052 vshr\.s16 q1, q1, #4 +0[0-9a-f]+ <[^>]+> f28b4254 vrshr\.s8 q2, q2, #5 +0[0-9a-f]+ <[^>]+> f39a6156 vsra\.u16 q3, q3, #6 +0[0-9a-f]+ <[^>]+> f39a8358 vrsra\.u16 q4, q4, #6 +0[0-9a-f]+ <[^>]+> f3954554 vsli\.16 q2, q2, #5 +0[0-9a-f]+ <[^>]+> f3bff69f vqshlu\.s64 d15, d15, #63.* +0[0-9a-f]+ <[^>]+> f2b55306 vext\.8 d5, d5, d6, #3 +0[0-9a-f]+ <[^>]+> f3042746 vabd\.u8 q1, q2, q3 +0[0-9a-f]+ <[^>]+> f262c0c6 vhadd\.s32 q14, q9, q3 +0[0-9a-f]+ <[^>]+> f22a2144 vrhadd\.s32 q1, q5, q2 +0[0-9a-f]+ <[^>]+> f220a2ce vhsub\.s32 q5, q8, q7 +0[0-9a-f]+ <[^>]+> f31a6448 vshl\.u16 q3, q4, q5 +0[0-9a-f]+ <[^>]+> f322a45c vqshl\.u32 q5, q6, q1 +0[0-9a-f]+ <[^>]+> f200e1dc vand q7, q8, q6 +0[0-9a-f]+ <[^>]+> f300e1dc veor q7, q8, q6 +0[0-9a-f]+ <[^>]+> f3b5a146 vceq\.i16 q5, q3, #0 +0[0-9a-f]+ <[^>]+> f316a85a vceq\.i16 q5, q3, q5 +0[0-9a-f]+ <[^>]+> f3b5a246 vclt\.s16 q5, q3, #0 +0[0-9a-f]+ <[^>]+> f2231a20 vpmax\.s32 d1, d3, d16 +0[0-9a-f]+ <[^>]+> f2275a34 vpmin\.s32 d5, d7, d20 +0[0-9a-f]+ <[^>]+> f3031f07 vpmax\.f32 d1, d3, d7 +0[0-9a-f]+ <[^>]+> f32c5f07 vpmin\.f32 d5, d12, d7 +0[0-9a-f]+ <[^>]+> f2162b60 vqdmulh\.s16 q1, q3, q8 +0[0-9a-f]+ <[^>]+> f3275b09 vqrdmulh\.s32 d5, d7, d9 +0[0-9a-f]+ <[^>]+> f39c2c6d vqdmulh\.s16 q1, q6, d5\[3\] +0[0-9a-f]+ <[^>]+> f21620d6 vqadd\.s16 q1, q11, q3 +0[0-9a-f]+ <[^>]+> f227503f vqadd\.s32 d5, d7, d31 +0[0-9a-f]+ <[^>]+> f2242962 vmla\.i32 q1, q2, q9 +0[0-9a-f]+ <[^>]+> f21a3b94 vpadd\.i16 d3, d26, d4 +0[0-9a-f]+ <[^>]+> f328694a vmls\.i32 q3, q4, q5 +0[0-9a-f]+ <[^>]+> f3082e54 vacge\.f32 q1, q4, q2 +0[0-9a-f]+ <[^>]+> f3226e58 vacgt\.f32 q3, q1, q4 +0[0-9a-f]+ <[^>]+> f30cae72 vacge\.f32 q5, q6, q9 +0[0-9a-f]+ <[^>]+> f320eed2 vacgt\.f32 q7, q8, q1 +0[0-9a-f]+ <[^>]+> f320e3d6 vcge\.u32 q7, q8, q3 +0[0-9a-f]+ <[^>]+> f320e3c6 vcgt\.u32 q7, q8, q3 +0[0-9a-f]+ <[^>]+> f326e370 vcge\.u32 q7, q3, q8 +0[0-9a-f]+ <[^>]+> f326e360 vcgt\.u32 q7, q3, q8 +0[0-9a-f]+ <[^>]+> f3aa2102 vaddw\.u32 q1, q5, d2 +0[0-9a-f]+ <[^>]+> f2a26304 vsubw\.s32 q3, q1, d4 +0[0-9a-f]+ <[^>]+> f22648d6 vtst\.32 q2, q11, q3 +0[0-9a-f]+ <[^>]+> f20e1f92 vrecps\.f32 d1, d30, d2 +0[0-9a-f]+ <[^>]+> f29c207a vshr\.s16 q1, q13, #4 +0[0-9a-f]+ <[^>]+> f28b4272 vrshr\.s8 q2, q9, #5 +0[0-9a-f]+ <[^>]+> f39a6152 vsra\.u16 q3, q1, #6 +0[0-9a-f]+ <[^>]+> f3dae358 vrsra\.u16 q15, q4, #6 +0[0-9a-f]+ <[^>]+> f3954556 vsli\.16 q2, q3, #5 +0[0-9a-f]+ <[^>]+> f3bff6b7 vqshlu\.s64 d15, d23, #63.* +0[0-9a-f]+ <[^>]+> f2b25386 vext\.8 d5, d18, d6, #3 +0[0-9a-f]+ <[^>]+> ee000b10 vmov(\.32)? d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee100b10 vmov(\.32)? r0, d0\[0\] +0[0-9a-f]+ <[^>]+> f3020d54 vmul\.f32 q0, q1, q2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-omit.s b/binutils-2.25/gas/testsuite/gas/arm/neon-omit.s new file mode 100644 index 00000000..54f18174 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-omit.s @@ -0,0 +1,105 @@ +@ test omitted optional arguments + + .text + .arm + .syntax unified + + vabd.u8 q1,q3 + vhadd.s32 q14, q3 + vrhadd.s32 q1,q2 + vhsub.s32 q5,q7 + vshl.u16 q3,q4 + vqshl.u32 q5,q6 + vand.64 q7,q8 + veor.64 q7,q8 + vceq.i16 q5,#0 + vceq.i16 q5,q5 + vclt.s16 q5,#0 + vabs.s16 q5,q6 + vneg.s16 d7,d8 + vabs.f d7,d8 + vneg.f q9,q10 + vpmax.s32 d1,d3 + vpmin.s32 d5,d7 + vpmax.f32 d1,d3 + vpmin.f32 d5,d7 + vqdmulh.s16 q1,q3 + vqrdmulh.s32 d5,d7 + vqdmulh.s16 q1,d5[3] + vqadd.s16 q1,q3 + vqadd.s32 d5,d7 + vmla.i32 q1,q2 + vpadd.i16 d3,d4 + vmls.s32 q3,q4 + vacge.f q1,q2 + vacgt.f q3,q4 + vacle.f q5,q6 + vaclt.f q7,q8 + vcge.u32 q7,q8 + vcgt.u32 q7,q8 + vcle.u32 q7,q8 + vclt.u32 q7,q8 + vaddw.u32 q1,d2 + vsubw.s32 q3,d4 + vtst.i32 q2,q3 + vrecps.f d1,d2 + vshr.s16 q1,#4 + vrshr.s8 q2,#5 + vsra.u16 q3,#6 + vrsra.u16 q4,#6 + vsli.16 q2,#5 + vqshlu.s64 d15,#63 + vext.8 d5,d6,#3 + +@ Also test three-argument forms without omitted arguments + + vabd.u8 q1,q2,q3 + vhadd.s32 q14,q9,q3 + vrhadd.s32 q1,q5,q2 + vhsub.s32 q5,q8,q7 + vshl.u16 q3,q4,q5 + vqshl.u32 q5,q6,q1 + vand.64 q7,q8,q6 + veor.64 q7,q8,q6 + vceq.i16 q5,q3,#0 + vceq.i16 q5,q3,q5 + vclt.s16 q5,q3,#0 + vpmax.s32 d1,d3,d16 + vpmin.s32 d5,d7,d20 + vpmax.f32 d1,d3,d7 + vpmin.f32 d5,d12,d7 + vqdmulh.s16 q1,q3,q8 + vqrdmulh.s32 d5,d7,d9 + vqdmulh.s16 q1,q6,d5[3] + vqadd.s16 q1,q11,q3 + vqadd.s32 d5,d7,d31 + vmla.i32 q1,q2,q9 + vpadd.i16 d3,d26,d4 + vmls.s32 q3,q4,q5 + vacge.f q1,q4,q2 + vacgt.f q3,q1,q4 + vacle.f q5,q9,q6 + vaclt.f q7,q1,q8 + vcge.u32 q7,q8,q3 + vcgt.u32 q7,q8,q3 + vcle.u32 q7,q8,q3 + vclt.u32 q7,q8,q3 + vaddw.u32 q1,q5,d2 + vsubw.s32 q3,q1,d4 + vtst.i32 q2,q11,q3 + vrecps.f d1,d30,d2 + vshr.s16 q1,q13,#4 + vrshr.s8 q2,q9,#5 + vsra.u16 q3,q1,#6 + vrsra.u16 q15,q4,#6 + vsli.16 q2,q3,#5 + vqshlu.s64 d15,d23,#63 + vext.8 d5,d18,d6,#3 + +@ Also test VMOV with omitted suffix: + + vmov d0[0], r0 + vmov r0, d0[0] + +@ PR 11136 - this used to crash the assembler. + vmul.f32 q0,q1,q2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-psyn.d b/binutils-2.25/gas/testsuite/gas/arm/neon-psyn.d new file mode 100644 index 00000000..c318672f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-psyn.d @@ -0,0 +1,37 @@ +# name: Neon programmers syntax +# as: -mfpu=neon +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f2144954 vmul\.i16 q2, q2, q2 +0[0-9a-f]+ <[^>]+> f2a33862 vmul\.i32 d3, d3, d2\[1\] +0[0-9a-f]+ <[^>]+> f2233912 vmul\.i32 d3, d3, d2 +0[0-9a-f]+ <[^>]+> f2222803 vadd\.i32 d2, d2, d3 +0[0-9a-f]+ <[^>]+> f3924a4a vmull\.u16 q2, d2, d2\[1\] +0[0-9a-f]+ <[^>]+> f2910061 vmla\.i16 d0, d1, d1\[2\] +0[0-9a-f]+ <[^>]+> f2910061 vmla\.i16 d0, d1, d1\[2\] +0[0-9a-f]+ <[^>]+> f2255805 vadd\.i32 d5, d5, d5 +0[0-9a-f]+ <[^>]+> f2275117 vorr d5, d7, d7 +0[0-9a-f]+ <[^>]+> ee021b70 vmov\.16 d2\[1\], r1 +0[0-9a-f]+ <[^>]+> ee251b10 vmov\.32 d5\[1\], r1 +0[0-9a-f]+ <[^>]+> ec432b15 vmov d5, r2, r3 +0[0-9a-f]+ <[^>]+> ee554b30 vmov\.s8 r4, d5\[1\] +0[0-9a-f]+ <[^>]+> ec565b15 vmov r5, r6, d5 +0[0-9a-f]+ <[^>]+> f396a507 vabal\.u16 q5, d6, d7 +0[0-9a-f]+ <[^>]+> f3bb2744 vcvt\.s32\.f32 q1, q2 +0[0-9a-f]+ <[^>]+> f3bb4e15 vcvt\.f32\.u32 d4, d5, #5 +0[0-9a-f]+ <[^>]+> f3bc7c05 vdup\.32 d7, d5\[1\] +0[0-9a-f]+ <[^>]+> f3ba1904 vtbl\.8 d1, {d10-d11}, d4 +0[0-9a-f]+ <[^>]+> f4aa698f vld2\.32 {d6\[1\],d7\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa476f vld4\.16 {d4\[1\],d6\[1\],d8\[1\],d10\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa6e4f vld3\.16 {d6\[\]-d8\[\]}, \[sl\] +0[0-9a-f]+ <[^>]+> ee100b30 vmov\.s16 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> f42a604f vld4\.16 {d6-d9}, \[sl\] +0[0-9a-f]+ <[^>]+> f4aa266f vld3\.16 {d2\[1\],d4\[1\],d6\[1\]}, \[sl\] +0[0-9a-f]+ <[^>]+> f3b47908 vtbl\.8 d7, {d4-d5}, d8 +0[0-9a-f]+ <[^>]+> f3142156 vbsl q1, q2, q3 +0[0-9a-f]+ <[^>]+> f3032e04 vcge\.f32 d2, d3, d4 +0[0-9a-f]+ <[^>]+> f3b52083 vcge\.s16 d2, d3, #0 +0[0-9a-f]+ <[^>]+> ee823b30 vdup\.16 d2, r3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-psyn.s b/binutils-2.25/gas/testsuite/gas/arm/neon-psyn.s new file mode 100644 index 00000000..5d412a85 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-psyn.s @@ -0,0 +1,78 @@ + .arm + .syntax unified + +fish .qn q2 +cow .dn d2[1] +chips .dn d2 +banana .dn d3 + + vmul fish.s16, fish.s16, fish.s16 + + vmul banana, banana, cow.s32 + vmul d3.s32, d3.s32, d2.s32 + vadd d2.s32, d3.s32 + vmull fish.u32, chips.u16, chips.u16[1] + +X .dn D0.S16 +Y .dn D1.S16 +Z .dn Y[2] + + VMLA X, Y, Z + VMLA X, Y, Y[2] + +foo .dn d5 +bar .dn d7 +foos .dn foo[1] + + vadd foo, foo, foo.u32 + + vmov foo, bar + vmov d2.s16[1], r1 + vmov d5.s32[1], r1 + vmov foo, r2, r3 + vmov r4, foos.s8 + vmov r5, r6, foo + +baa .qn q5 +moo .dn d6 +sheep .dn d7 +chicken .dn d8 + + vabal baa, moo.u16, sheep.u16 + + vcvt q1.s32, q2.f32 + vcvt d4.f, d5.u32, #5 + + vdup bar, foos.32 + vtbl d1, {baa}, d4.8 + +el1 .dn d4.16[1] +el2 .dn d6.16[1] +el3 .dn d8.16[1] +el4 .dn d10.16[1] + + vld2 {moo.32[1], sheep.32[1]}, [r10] + vld4 {el1, el2, el3, el4}, [r10] + vld3 {moo.16[], sheep.16[], chicken.16[]}, [r10] + + vmov r0,d0.s16[0] + +el5 .qn q3.16 +el6 .qn q4.16 + + vld4 {el5,el6}, [r10] + + vld3 {d2.s16[1], d4.s16[1], d6.s16[1]}, [r10] + +chicken8 .dn chicken.8 + + vtbl d7.8, {d4, d5}, chicken8 + + vbsl q1.8, q2.16, q3.8 + + vcge d2.32, d3.f, d4.f + vcge d2.16, d3.s16, #0 + +dupme .dn d2.s16 + + vdup dupme, r3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.d b/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.d new file mode 100644 index 00000000..36bb9860 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.d @@ -0,0 +1,3 @@ +# name: Bad suffix for non-Neon mnemonic +# as: -mfpu=neon +# error-output: neon-suffix-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.l b/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.l new file mode 100644 index 00000000..091429dc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.l @@ -0,0 +1,9 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: invalid neon suffix for non neon instruction +[^:]*:4: Error: invalid neon suffix for non neon instruction +[^:]*:5: Error: invalid neon suffix for non neon instruction +[^:]*:6: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11' +[^:]*:9: Error: invalid neon suffix for non neon instruction +[^:]*:10: Error: invalid neon suffix for non neon instruction +[^:]*:11: Error: invalid neon suffix for non neon instruction +[^:]*:12: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11' diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.s b/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.s new file mode 100644 index 00000000..20c60fe8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-suffix-bad.s @@ -0,0 +1,13 @@ +.syntax unified +.arm +add.f32 r0, r0, r0 +faddd.f32 d0, d0, d0 +faddd.f64 d0, d0, d0 +vcvt.f64.s32 d0, s0, #11 + +.thumb +add.f32 r0, r0, r0 +faddd.f32 d0, d0, d0 +faddd.f64 d0, d0, d0 +vcvt.f64.s32 d0, s0, #11 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.d b/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.d new file mode 100644 index 00000000..47ba4d84 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.d @@ -0,0 +1,3 @@ +# name: Bad shape for vmov +# as: -mfpu=neon +# error-output: neon-vmov-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.l b/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.l new file mode 100644 index 00000000..543dd370 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: invalid instruction shape -- `vmov Q0,d0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.s b/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.s new file mode 100644 index 00000000..ec87eeab --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/neon-vmov-bad.s @@ -0,0 +1,3 @@ +.syntax unified +.arm + vmov Q0, d0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/noarm.d b/binutils-2.25/gas/testsuite/gas/arm/noarm.d new file mode 100644 index 00000000..ae34f834 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/noarm.d @@ -0,0 +1,3 @@ +# name: Disallow ARM instructions on V7M +# as: +# error-output: noarm.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/noarm.l b/binutils-2.25/gas/testsuite/gas/arm/noarm.l new file mode 100644 index 00000000..edc59a2d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/noarm.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:12: Error: selected processor does not support ARM opcodes +[^:]*:13: Error: attempt to use an ARM instruction on a Thumb-only processor -- `nop' diff --git a/binutils-2.25/gas/testsuite/gas/arm/noarm.s b/binutils-2.25/gas/testsuite/gas/arm/noarm.s new file mode 100644 index 00000000..3dadd446 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/noarm.s @@ -0,0 +1,13 @@ + .arch armv7a + .syntax unified + .text +func: + nop + movw r0, #0 + + .arch armv7 + .thumb + nop + movw r0, #0 + .arm + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/nomapping.d b/binutils-2.25/gas/testsuite/gas/arm/nomapping.d new file mode 100644 index 00000000..76f28334 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/nomapping.d @@ -0,0 +1,8 @@ +#nm: -n +#name: ARM Mapping Symbols Ignored +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# Check ARM ELF Mapping Symbols are ignored properly +0+0 t sym1 +0+c t sym2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/nomapping.s b/binutils-2.25/gas/testsuite/gas/arm/nomapping.s new file mode 100644 index 00000000..efe92ae5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/nomapping.s @@ -0,0 +1,19 @@ + .text + .arm +sym1: + nop + .thumb + nop + nop +$a.foo: +$t.foo: +$d.foo: +@ Obsolete mapping symbols generated by armcc. +$m: +$m.foo: +$f: +$f.foo: +$p: +$p.foo: + .word 0 +sym2: diff --git a/binutils-2.25/gas/testsuite/gas/arm/offset-1.d b/binutils-2.25/gas/testsuite/gas/arm/offset-1.d new file mode 100644 index 00000000..bec9386f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/offset-1.d @@ -0,0 +1,23 @@ +# name: MINUS ZERO OFFSET +# as: +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e51f0000 ? ldr r0, \[pc, #-0\] ; 0+8 <[^>]+> +0+04 <[^>]+> e59f0000 ? ldr r0, \[pc\] ; 0+c <[^>]+> +0+08 <[^>]+> e5110000 ? ldr r0, \[r1, #-0\] +0+0c <[^>]+> e5910000 ? ldr r0, \[r1\] +0+10 <[^>]+> e4110000 ? ldr r0, \[r1\], #-0 +0+14 <[^>]+> e4910000 ? ldr r0, \[r1\], #0 +0+18 <[^>]+> e15f00b0 ? ldrh r0, \[pc, #-0\] ; 0+20 <[^>]+> +0+1c <[^>]+> e1df00b0 ? ldrh r0, \[pc\] ; 0+24 <[^>]+> +0+20 <[^>]+> e15100b0 ? ldrh r0, \[r1, #-0\] +0+24 <[^>]+> e1d100b0 ? ldrh r0, \[r1\] +0+28 <[^>]+> e05100b0 ? ldrh r0, \[r1\], #-0 +0+2c <[^>]+> e0d100b0 ? ldrh r0, \[r1\], #0 +0+30 <[^>]+> e5310000 ? ldr r0, \[r1, #-0\]! +0+34 <[^>]+> e5b10000 ? ldr r0, \[r1, #0\]! +0+38 <[^>]+> e17100b0 ? ldrh r0, \[r1, #-0\]! +0+3c <[^>]+> e1f100b0 ? ldrh r0, \[r1, #0\]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/offset-1.s b/binutils-2.25/gas/testsuite/gas/arm/offset-1.s new file mode 100644 index 00000000..3e99317b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/offset-1.s @@ -0,0 +1,16 @@ + ldr r0, [pc, #-0] + ldr r0, [pc, #0] + ldr r0, [r1, #-0] + ldr r0, [r1, #0] + ldr r0, [r1], #-0 + ldr r0, [r1], #0 + ldrh r0, [pc, #-0] + ldrh r0, [pc, #0] + ldrh r0, [r1, #-0] + ldrh r0, [r1, #0] + ldrh r0, [r1], #-0 + ldrh r0, [r1], #0 + ldr r0, [r1, #-0]! + ldr r0, [r1, #0]! + ldrh r0, [r1, #-0]! + ldrh r0, [r1, #0]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/offset.d b/binutils-2.25/gas/testsuite/gas/arm/offset.d new file mode 100644 index 00000000..1795477f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/offset.d @@ -0,0 +1,11 @@ +# name: OFFSET_IMM regression +# as: +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+> +0+4 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+8 <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) +0+c <[^>]+> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/offset.s b/binutils-2.25/gas/testsuite/gas/arm/offset.s new file mode 100644 index 00000000..53d567de --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/offset.s @@ -0,0 +1,14 @@ + @ test that an OFFSET_IMM reloc against a global symbol is + @ still resolved by the assembler, as long as the symbol is in + @ the same section as the reference + .text + .globl l + .globl foo +l: + ldr r0, foo +foo: + nop + + @ pad section for a.out's benefit + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/pic.d b/binutils-2.25/gas/testsuite/gas/arm/pic.d new file mode 100644 index 00000000..ac2a65d7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pic.d @@ -0,0 +1,24 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: PIC +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# VxWorks needs a special variant of this file. +#skip: *-*-vxworks* + +# Test generation of PIC + +.*: +file format .*arm.* + +Disassembly of section .text: +00+0 <[^>]*> eb...... bl 00+. <[^>]*> + 0: R_ARM_(PC24|CALL) foo.* +00+4 <[^>]*> eb...... bl 0[0123456789abcdef]+ <[^>]*> + 4: R_ARM_(PLT32|CALL) foo + \.\.\. + 8: R_ARM_ABS32 sym + c: R_ARM_GOT32 sym + 10: R_ARM_GOTOFF32 sym + 14: R_ARM_GOTPC _GLOBAL_OFFSET_TABLE_ + 18: R_ARM_TARGET1 foo2 + 1c: R_ARM_SBREL32 foo3 + 20: R_ARM_TARGET2 foo4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/pic.s b/binutils-2.25/gas/testsuite/gas/arm/pic.s new file mode 100644 index 00000000..3c3c3293 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pic.s @@ -0,0 +1,14 @@ +@ Test file for ARM ELF PIC + +.text +.align 0 + bl foo + bl foo(PLT) + .word sym + .word sym(GOT) + .word sym(GOTOFF) +1: + .word _GLOBAL_OFFSET_TABLE_ - 1b + .word foo2(TARGET1) + .word foo3(SBREL) + .word foo4(TARGET2) diff --git a/binutils-2.25/gas/testsuite/gas/arm/pic_vxworks.d b/binutils-2.25/gas/testsuite/gas/arm/pic_vxworks.d new file mode 100644 index 00000000..6b0f3edd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pic_vxworks.d @@ -0,0 +1,22 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: PIC +#source: pic.s +#not-skip: *-*-vxworks* + +# Test generation of PIC + +.*: +file format .*arm.* + +Disassembly of section .text: +00+0 <[^>]*> eb000000 bl .* + 0: R_ARM_PC24 foo-0x8 +00+4 <[^>]*> eb000000 bl .* + 4: R_ARM_PLT32 foo-0x8 + \.\.\. + 8: R_ARM_ABS32 sym + c: R_ARM_GOT32 sym + 10: R_ARM_GOTOFF32 sym + 14: R_ARM_GOTPC _GLOBAL_OFFSET_TABLE_ + 18: R_ARM_TARGET1 foo2 + 1c: R_ARM_SBREL32 foo3 + 20: R_ARM_TARGET2 foo4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/plt-1.d b/binutils-2.25/gas/testsuite/gas/arm/plt-1.d new file mode 100644 index 00000000..d2a64f7e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/plt-1.d @@ -0,0 +1,38 @@ +# name: Thumb branch to PLT +# as: +# objdump: -dr +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + + +Disassembly of section \.text: + +0+000 <Strong1>: + 0: f7ff bffe b\.w 14 <Strong2> + 0: R_ARM_THM_JUMP24 Strong2 + 4: f7ff bffe b\.w 14 <Strong2> + 4: R_ARM_THM_JUMP24 Strong2 + 8: e7fe b\.n 14 <Strong2> + 8: R_ARM_THM_JUMP11 Strong2 + a: f7ff bffe b\.w 14 <Strong2> + a: R_ARM_THM_JUMP24 Strong2 + e: f7ff bffe b\.w 14 <Strong2> + e: R_ARM_THM_JUMP24 Strong2 + 12: e7fe b\.n 14 <Strong2> + 12: R_ARM_THM_JUMP11 Strong2 + +0+014 <Strong2>: + 14: f7ff bffe b\.w 0 <Strong1> + 14: R_ARM_THM_JUMP24 Strong1 + 18: f7ff bffe b\.w 0 <Strong1> + 18: R_ARM_THM_JUMP24 Strong1 + 1c: e7fe b\.n 0 <Strong1> + 1c: R_ARM_THM_JUMP11 Strong1 + 1e: f7ff bffe b\.w 0 <Strong1> + 1e: R_ARM_THM_JUMP24 Strong1 + 22: f7ff bffe b\.w 0 <Strong1> + 22: R_ARM_THM_JUMP24 Strong1 + 26: e7fe b\.n 0 <Strong1> + 26: R_ARM_THM_JUMP11 Strong1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/plt-1.s b/binutils-2.25/gas/testsuite/gas/arm/plt-1.s new file mode 100644 index 00000000..262980a9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/plt-1.s @@ -0,0 +1,27 @@ + .syntax unified + .text + .thumb + + .globl Strong1 + .thumb_func + .type Strong1, %function +Strong1: + b Strong2(PLT) + b.w Strong2(PLT) + b.n Strong2(PLT) + b Strong2 + b.w Strong2 + b.n Strong2 + .size Strong1,.-Strong1 + + .globl Strong2 + .thumb_func + .type Strong2, %function +Strong2: + b Strong1(PLT) + b.w Strong1(PLT) + b.n Strong1(PLT) + b Strong1 + b.w Strong1 + b.n Strong1 + .size Strong2, .-Strong2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/pr12198-1.d b/binutils-2.25/gas/testsuite/gas/arm/pr12198-1.d new file mode 100644 index 00000000..8c20b039 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pr12198-1.d @@ -0,0 +1,11 @@ +# name: PR12198 - Only select v6S-M when v6-M is selected (1) +# source: pr12198-1.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v4T + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/pr12198-1.s b/binutils-2.25/gas/testsuite/gas/arm/pr12198-1.s new file mode 100644 index 00000000..15c88055 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pr12198-1.s @@ -0,0 +1,7 @@ + .thumb + .global f + .type f, %function +f: + svc 0xab + bx lr + diff --git a/binutils-2.25/gas/testsuite/gas/arm/pr12198-2.d b/binutils-2.25/gas/testsuite/gas/arm/pr12198-2.d new file mode 100644 index 00000000..6469c3ed --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pr12198-2.d @@ -0,0 +1,12 @@ +# name: PR12198 - Only select v6S-M when v6-M is selected (2) +# source: pr12198-2.s +# as: +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_arch: v6S-M + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Thumb-1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/pr12198-2.s b/binutils-2.25/gas/testsuite/gas/arm/pr12198-2.s new file mode 100644 index 00000000..711cc7ef --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pr12198-2.s @@ -0,0 +1,8 @@ + .thumb + .global f + .type f, %function +f: + svc 0xab + dsb + bx lr + diff --git a/binutils-2.25/gas/testsuite/gas/arm/pr9722.d b/binutils-2.25/gas/testsuite/gas/arm/pr9722.d new file mode 100644 index 00000000..44f7e48d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pr9722.d @@ -0,0 +1,10 @@ +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#objdump: -dr --prefix-addresses --show-raw-insn +#name: PR9722: Generation of Thumb NOP instruction + +.*: +file format .*arm.* + +Disassembly of section .text: +0+0 <.*> 46c0[ ]+nop.* +0+2 <.*> 46c0[ ]+nop.* +0+4 <.*> bf00[ ]+nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/pr9722.s b/binutils-2.25/gas/testsuite/gas/arm/pr9722.s new file mode 100644 index 00000000..0d54d3a9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/pr9722.s @@ -0,0 +1,8 @@ + .thumb + .text + .arch armv4t + nop + .syntax unified + nop + .arch armv6t2 + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/push-pop.d b/binutils-2.25/gas/testsuite/gas/arm/push-pop.d new file mode 100644 index 00000000..6eabbfaf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/push-pop.d @@ -0,0 +1,14 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: PUSH and POP + +# Test the `PUSH' and `POP' instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <.*> e52d0004 push {r0} ; \(str r0, \[sp, #-4\]!\) +0+004 <.*> e92d000e push {r1, r2, r3} +0+008 <.*> e52d9004 push {r9} ; \(str r9, \[sp, #-4\]!\) +0+00c <.*> e49d9004 pop {r9} ; \(ldr r9, \[sp\], #4\) +0+010 <.*> e8bd000e pop {r1, r2, r3} +0+014 <.*> e49d0004 pop {r0} ; \(ldr r0, \[sp\], #4\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/push-pop.s b/binutils-2.25/gas/testsuite/gas/arm/push-pop.s new file mode 100644 index 00000000..d86ec9ec --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/push-pop.s @@ -0,0 +1,8 @@ + .text + .syntax unified + push {r0} + push {r1, r2, r3} + push {r9} + pop {r9} + pop {r1, r2, r3} + pop {r0} diff --git a/binutils-2.25/gas/testsuite/gas/arm/r15-bad.d b/binutils-2.25/gas/testsuite/gas/arm/r15-bad.d new file mode 100644 index 00000000..ec7c3055 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/r15-bad.d @@ -0,0 +1,2 @@ +#name: Invalid use of r15 errors +#error-output: r15-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/r15-bad.l b/binutils-2.25/gas/testsuite/gas/arm/r15-bad.l new file mode 100644 index 00000000..a172e9e9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/r15-bad.l @@ -0,0 +1,64 @@ +[^:]*: Assembler messages: +[^:]*:5: Error: r15 not allowed here -- `mul r15,r1,r2' +[^:]*:6: Error: r15 not allowed here -- `mul r1,r15,r2' +[^:]*:7: Error: r15 not allowed here -- `mla r15,r2,r3,r4' +[^:]*:8: Error: r15 not allowed here -- `mla r1,r15,r3,r4' +[^:]*:9: Error: r15 not allowed here -- `mla r1,r2,r15,r4' +[^:]*:10: Error: r15 not allowed here -- `mla r1,r2,r3,r15' +[^:]*:11: Error: r15 not allowed here -- `smlabb r15,r2,r3,r4' +[^:]*:12: Error: r15 not allowed here -- `smlabb r1,r15,r3,r4' +[^:]*:13: Error: r15 not allowed here -- `smlabb r1,r2,r15,r4' +[^:]*:14: Error: r15 not allowed here -- `smlabb r1,r2,r3,r15' +[^:]*:15: Error: r15 not allowed here -- `smlalbb r15,r2,r3,r4' +[^:]*:16: Error: r15 not allowed here -- `smlalbb r1,r15,r3,r4' +[^:]*:17: Error: r15 not allowed here -- `smlalbb r1,r2,r15,r4' +[^:]*:18: Error: r15 not allowed here -- `smlalbb r1,r2,r3,r15' +[^:]*:19: Error: r15 not allowed here -- `smulbb r15,r2,r3' +[^:]*:20: Error: r15 not allowed here -- `smulbb r1,r15,r3' +[^:]*:21: Error: r15 not allowed here -- `smulbb r1,r2,r15' +[^:]*:22: Error: r15 not allowed here -- `qadd r15,r2,r3' +[^:]*:23: Error: r15 not allowed here -- `qadd r1,r15,r3' +[^:]*:24: Error: r15 not allowed here -- `qadd r1,r2,r15' +[^:]*:25: Error: r15 not allowed here -- `qadd16 r15,r2,r3' +[^:]*:26: Error: r15 not allowed here -- `qadd16 r1,r15,r3' +[^:]*:27: Error: r15 not allowed here -- `qadd16 r1,r2,r15' +[^:]*:28: Error: r15 not allowed here -- `clz r15,r2' +[^:]*:29: Error: r15 not allowed here -- `clz r1,r15' +[^:]*:30: Error: r15 not allowed here -- `umaal r15,r2,r3,r4' +[^:]*:31: Error: r15 not allowed here -- `umaal r1,r15,r3,r4' +[^:]*:32: Error: r15 not allowed here -- `umaal r1,r2,r15,r4' +[^:]*:33: Error: r15 not allowed here -- `umaal r1,r2,r3,r15' +[^:]*:34: Error: r15 not allowed here -- `strex r15,r2,[[]r3[]]' +[^:]*:35: Error: r15 not allowed here -- `strex r1,r15,[[]r3[]]' +[^:]*:36: Error: instruction does not accept this addressing mode -- `strex r1,r2,[[]r15[]]' +[^:]*:37: Error: r15 not allowed here -- `ssat r15,#1,r2' +[^:]*:38: Error: r15 not allowed here -- `ssat r1,#1,r15' +[^:]*:39: Error: r15 not allowed here -- `ssat16 r15,#1,r2' +[^:]*:40: Error: r15 not allowed here -- `ssat16 r1,#1,r15' +[^:]*:41: Error: r15 not allowed here -- `smmul r15,r2,r3' +[^:]*:42: Error: r15 not allowed here -- `smmul r1,r15,r3' +[^:]*:43: Error: r15 not allowed here -- `smmul r1,r2,r15' +[^:]*:44: Error: r15 not allowed here -- `smlald r15,r2,r3,r4' +[^:]*:45: Error: r15 not allowed here -- `smlald r1,r15,r3,r4' +[^:]*:46: Error: r15 not allowed here -- `smlald r1,r2,r15,r4' +[^:]*:47: Error: r15 not allowed here -- `smlald r1,r2,r3,r15' +[^:]*:48: Error: r15 not allowed here -- `smlad r15,r2,r3,r4' +[^:]*:49: Error: r15 not allowed here -- `smlad r1,r15,r3,r4' +[^:]*:50: Error: r15 not allowed here -- `smlad r1,r2,r15,r4' +[^:]*:51: Error: r15 not allowed here -- `smlad r1,r2,r3,r15' +[^:]*:52: Error: r15 not allowed here -- `sxth r15,r2' +[^:]*:53: Error: r15 not allowed here -- `sxth r1,r15' +[^:]*:54: Error: r15 not allowed here -- `sxtah r15,r2,r3' +[^:]*:55: Error: r15 not allowed here -- `sxtah r1,r15,r3' +[^:]*:56: Error: r15 not allowed here -- `sxtah r1,r2,r15' +[^:]*:57: Error: r15 not allowed here -- `rfeda r15' +[^:]*:58: Error: r15 not allowed here -- `rev r15,r2' +[^:]*:59: Error: r15 not allowed here -- `rev r1,r15' +[^:]*:60: Error: r15 not allowed here -- `pkhtb r15,r2,r3' +[^:]*:61: Error: r15 not allowed here -- `pkhtb r1,r15,r3' +[^:]*:62: Error: r15 not allowed here -- `pkhtb r1,r2,r15' +[^:]*:63: Error: r15 not allowed here -- `ldrex r15,[[]r2[]]' +[^:]*:64: Error: instruction does not accept this addressing mode -- `ldrex r1,[[]r15[]]' +[^:]*:65: Error: r15 not allowed here -- `swp r15,r2,[[]r3[]]' +[^:]*:66: Error: r15 not allowed here -- `swp r1,r15,[[]r3[]]' +[^:]*:67: Error: r15 not allowed here -- `swp r1,r2,[[]r15[]]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/r15-bad.s b/binutils-2.25/gas/testsuite/gas/arm/r15-bad.s new file mode 100644 index 00000000..59a6ea83 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/r15-bad.s @@ -0,0 +1,68 @@ +.text +.align 0 + +label: + mul r15, r1, r2 + mul r1, r15, r2 + mla r15, r2, r3, r4 + mla r1, r15, r3, r4 + mla r1, r2, r15, r4 + mla r1, r2, r3, r15 + smlabb r15, r2, r3, r4 + smlabb r1, r15, r3, r4 + smlabb r1, r2, r15, r4 + smlabb r1, r2, r3, r15 + smlalbb r15, r2, r3, r4 + smlalbb r1, r15, r3, r4 + smlalbb r1, r2, r15, r4 + smlalbb r1, r2, r3, r15 + smulbb r15, r2, r3 + smulbb r1, r15, r3 + smulbb r1, r2, r15 + qadd r15, r2, r3 + qadd r1, r15, r3 + qadd r1, r2, r15 + qadd16 r15, r2, r3 + qadd16 r1, r15, r3 + qadd16 r1, r2, r15 + clz r15, r2 + clz r1, r15 + umaal r15, r2, r3, r4 + umaal r1, r15, r3, r4 + umaal r1, r2, r15, r4 + umaal r1, r2, r3, r15 + strex r15, r2, [r3] + strex r1, r15, [r3] + strex r1, r2, [r15] + ssat r15, #1, r2 + ssat r1, #1, r15 + ssat16 r15, #1, r2 + ssat16 r1, #1, r15 + smmul r15, r2, r3 + smmul r1, r15, r3 + smmul r1, r2, r15 + smlald r15, r2, r3, r4 + smlald r1, r15, r3, r4 + smlald r1, r2, r15, r4 + smlald r1, r2, r3, r15 + smlad r15, r2, r3, r4 + smlad r1, r15, r3, r4 + smlad r1, r2, r15, r4 + smlad r1, r2, r3, r15 + sxth r15, r2 + sxth r1, r15 + sxtah r15, r2, r3 + sxtah r1, r15, r3 + sxtah r1, r2, r15 + rfeda r15 + rev r15, r2 + rev r1, r15 + pkhtb r15, r2, r3 + pkhtb r1, r15, r3 + pkhtb r1, r2, r15 + ldrex r15, [r2] + ldrex r1, [r15] + swp r15, r2, [r3] + swp r1, r15, [r3] + swp r1, r2, [r15] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/reg-alias.d b/binutils-2.25/gas/testsuite/gas/arm/reg-alias.d new file mode 100644 index 00000000..06e87d83 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/reg-alias.d @@ -0,0 +1,10 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Case Sensitive Register Aliases + +.*: +file format .*arm.* + +Disassembly of section .text: +0+0 <.*> ee060f10 mcr 15, 0, r0, cr6, cr0, \{0\} +0+4 <.*> e1a00000 nop ; \(mov r0, r0\) +0+8 <.*> e1a00000 nop ; \(mov r0, r0\) +0+c <.*> e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/reg-alias.s b/binutils-2.25/gas/testsuite/gas/arm/reg-alias.s new file mode 100644 index 00000000..5086b8b4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/reg-alias.s @@ -0,0 +1,14 @@ + @ Test case-sensitive register aliases + .text + .global fred +fred: + +MMUPurgeTLBReg .req c6 +MMUCP .req p15 + +MCR MMUCP, 0, a1, MMUPurgeTLBReg, c0, 0 + @ The NOPs are here for ports like arm-aout which will pad + @ the .text section to a 16 byte boundary. + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/relax_branch_align.d b/binutils-2.25/gas/testsuite/gas/arm/relax_branch_align.d new file mode 100644 index 00000000..e19857a5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/relax_branch_align.d @@ -0,0 +1,13 @@ +#name: Branch relaxation with alignment. +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+002 <[^>]+> f000 8080 beq.w 0+106 <[^>]*> +0+006 <[^>]+> 46c0 nop ; \(mov r8, r8\) +#... +0+100 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+102 <[^>]+> f47f af80 bne.w 0+006 <[^>]*> +0+106 <[^>]+> 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/relax_branch_align.s b/binutils-2.25/gas/testsuite/gas/arm/relax_branch_align.s new file mode 100644 index 00000000..718ce498 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/relax_branch_align.s @@ -0,0 +1,17 @@ + .syntax unified + .thumb +fn: + nop +.L191: + beq .L192 +.L46: + nop + .align 2 +.L54: + .rept 62 + .word 0 + .endr + nop + bne .L46 +.L192: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/relax_load_align.d b/binutils-2.25/gas/testsuite/gas/arm/relax_load_align.d new file mode 100644 index 00000000..776fc3bb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/relax_load_align.d @@ -0,0 +1,9 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> f510 707a adds.w r0, r0, #1000 ; 0x3e8 +0+004 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\) +0+006 <[^>]+> 4800 ldr r0, \[pc, #0\] ; \(0+008 <[^>]+>\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/relax_load_align.s b/binutils-2.25/gas/testsuite/gas/arm/relax_load_align.s new file mode 100644 index 00000000..e4612910 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/relax_load_align.s @@ -0,0 +1,12 @@ +@ The relaxation algorithm used to not compensate for alignment statements. +@ The early termination to avoid infinite looping would make the second load +@ a wide instruction. + .text + .thumb + .syntax unified +fn: + adds r0, r0, #1000 + ldr r0, 1f + ldr r0, 1f +.align 2 +1: diff --git a/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.d b/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.d new file mode 100644 index 00000000..48668714 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.d @@ -0,0 +1,2 @@ +#name: Invalid relocations +#error-output: reloc-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.l b/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.l new file mode 100644 index 00000000..a95bb996 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:5: Error: internal_relocation \(type: OFFSET_IMM\) not fixed up +[^:]*:3: Error: cannot represent T32_OFFSET_IMM relocation in this object file format diff --git a/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.s b/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.s new file mode 100644 index 00000000..88c45c8a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/reloc-bad.s @@ -0,0 +1,5 @@ +.syntax unified +.thumb +ldr r0, 0 +.arm +ldr r0, 0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/req.d b/binutils-2.25/gas/testsuite/gas/arm/req.d new file mode 100644 index 00000000..41707fff --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/req.d @@ -0,0 +1,3 @@ +#name: .req errors +#as: -mcpu=arm7m +#error-output: req.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/req.l b/binutils-2.25/gas/testsuite/gas/arm/req.l new file mode 100644 index 00000000..7e76764f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/req.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +[^:]*:18: Error: ARM register expected -- `add foo,foo,foo' +[^:]*:21: Warning: ignoring attempt to use .unreq on fixed register name: 'r0' +[^:]*:41: Warning: ignoring redefinition of register alias 'FOO' diff --git a/binutils-2.25/gas/testsuite/gas/arm/req.s b/binutils-2.25/gas/testsuite/gas/arm/req.s new file mode 100644 index 00000000..1330e751 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/req.s @@ -0,0 +1,41 @@ + .text + .global test_dot_req_and_unreq +test_dot_req_and_unreq: + + # Check that builtin register alias 'r0' works. + add r0, r0, r0 + + # Create an alias for r0. + foo .req r0 + + # Check that it works. + add foo, foo, foo + + # Now remove the alias. + .unreq foo + + # And make sure that it no longer works. + add foo, foo, foo + + # Attempt to remove the builtin alias for r0. + .unreq r0 + + # That is ignored, so this should still work. + add r0, r0, r0 + + # Now attempt to re-alias foo. There used to be a bug whereby the + # first creation of an alias called foo would also create an alias + # called FOO, but the .unreq of foo would not delete FOO. Thus a + # second attempt at aliasing foo (to something different than + # before) would fail because the assembler would complain that FOO + # already existed. + foo .req r1 + + add foo, foo, foo + + # Check that the upper case alias was also recreated. + add FOO, FOO, FOO + + # Check that a second attempt to alias foo, using a mixed case + # verison of the name, will fail. + Foo .req r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/shift-bad.d b/binutils-2.25/gas/testsuite/gas/arm/shift-bad.d new file mode 100644 index 00000000..7d4cac19 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/shift-bad.d @@ -0,0 +1,3 @@ +# name: PR 12854: Extraneous shifts +# as: +# error-output: shift-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/shift-bad.l b/binutils-2.25/gas/testsuite/gas/arm/shift-bad.l new file mode 100644 index 00000000..3c9fb6e4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/shift-bad.l @@ -0,0 +1,9 @@ +.*shift-bad.s: Assembler messages: +.*shift-bad.s:2: Error: extraneous shift as part of operand to shift insn -- `asr r0,r1,r2,ror#5' +.*shift-bad.s:3: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl r3' +.*shift-bad.s:7: Error: extraneous shift as part of operand to shift insn -- `ror r0,r0,r2,lsl#1' +.*shift-bad.s:8: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r0,r2,lsl#1' +.*shift-bad.s:9: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r0,r2,asr r0' +.*shift-bad.s:13: Error: extraneous shift as part of operand to shift insn -- `ror r0,r1,r2,lsl#1' +.*shift-bad.s:14: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,lsl#1' +.*shift-bad.s:15: Error: extraneous shift as part of operand to shift insn -- `lsl r0,r1,r2,asr r0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/shift-bad.s b/binutils-2.25/gas/testsuite/gas/arm/shift-bad.s new file mode 100644 index 00000000..6ee069b1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/shift-bad.s @@ -0,0 +1,15 @@ + + asr r0, r1, r2, ror #5 + ror r0, r1, r2, lsl r3 + + .thumb_func +foo: + ror r0, r0, r2, lsl #1 + lsl r0, r0, r2, lsl #1 + lsl r0, r0, r2, asr r0 + + .syntax unified + + ror r0, r1, r2, lsl #1 + lsl r0, r1, r2, lsl #1 + lsl r0, r1, r2, asr r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-usage-t.d b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-usage-t.d new file mode 100644 index 00000000..6dedc00c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-usage-t.d @@ -0,0 +1,82 @@ +# name: SP and PC registers special uses test. +# objdump: -d --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <foo> 4685 mov sp, r0 +00000002 <foo\+0x2> 4668 mov r0, sp +00000004 <foo\+0x4> b000 add sp, #0 +00000006 <foo\+0x6> f20d 0d00 addw sp, sp, #0 +0000000a <foo\+0xa> b080 sub sp, #0 +0000000c <foo\+0xc> f2ad 0d00 subw sp, sp, #0 +00000010 <foo\+0x10> 4485 add sp, r0 +00000012 <foo\+0x12> eb0d 0d40 add.w sp, sp, r0, lsl #1 +00000016 <foo\+0x16> ebad 0d00 sub.w sp, sp, r0 +0000001a <foo\+0x1a> ebad 0d40 sub.w sp, sp, r0, lsl #1 +0000001e <foo\+0x1e> 9800 ldr r0, \[sp, #0\] +00000020 <foo\+0x20> 4800 ldr r0, \[pc, #0\] ; \(00000024 <foo\+0x24>\) +00000022 <foo\+0x22> f8d0 f000 ldr.w pc, \[r0\] +00000026 <foo\+0x26> f8d0 d000 ldr.w sp, \[r0\] +0000002a <foo\+0x2a> f8df f000 ldr.w pc, \[pc\] ; 0000002c <foo\+0x2c> +0000002e <foo\+0x2e> f8dd d000 ldr.w sp, \[sp\] +00000032 <foo\+0x32> f8dd f000 ldr.w pc, \[sp\] +00000036 <foo\+0x36> f8df d000 ldr.w sp, \[pc\] ; 00000038 <foo\+0x38> +0000003a <foo\+0x3a> 9000 str r0, \[sp, #0\] +0000003c <foo\+0x3c> f8c0 d000 str.w sp, \[r0\] +00000040 <foo\+0x40> f8cd d000 str.w sp, \[sp\] +00000044 <foo\+0x44> 4468 add r0, sp +00000046 <foo\+0x46> eb1d 0000 adds.w r0, sp, r0 +0000004a <foo\+0x4a> eb0d 0040 add.w r0, sp, r0, lsl #1 +0000004e <foo\+0x4e> eb1d 0040 adds.w r0, sp, r0, lsl #1 +00000052 <foo\+0x52> f11d 0f00 cmn.w sp, #0 +00000056 <foo\+0x56> eb1d 0f00 cmn.w sp, r0 +0000005a <foo\+0x5a> eb1d 0f40 cmn.w sp, r0, lsl #1 +0000005e <foo\+0x5e> f1bd 0f00 cmp.w sp, #0 +00000062 <foo\+0x62> 4585 cmp sp, r0 +00000064 <foo\+0x64> ebbd 0f40 cmp.w sp, r0, lsl #1 +00000068 <foo\+0x68> b080 sub sp, #0 +0000006a <foo\+0x6a> f1bd 0d00 subs.w sp, sp, #0 +0000006e <foo\+0x6e> f1ad 0000 sub.w r0, sp, #0 +00000072 <foo\+0x72> f1bd 0000 subs.w r0, sp, #0 +00000076 <foo\+0x76> b001 add sp, #4 +00000078 <foo\+0x78> a801 add r0, sp, #4 +0000007a <foo\+0x7a> f11d 0d04 adds.w sp, sp, #4 +0000007e <foo\+0x7e> f11d 0004 adds.w r0, sp, #4 +00000082 <foo\+0x82> f20d 0004 addw r0, sp, #4 +00000086 <foo\+0x86> b001 add sp, #4 +00000088 <foo\+0x88> f11d 0d04 adds.w sp, sp, #4 +0000008c <foo\+0x8c> f20d 0d04 addw sp, sp, #4 +00000090 <foo\+0x90> 4485 add sp, r0 +00000092 <foo\+0x92> 4468 add r0, sp +00000094 <foo\+0x94> eb0d 0040 add.w r0, sp, r0, lsl #1 +00000098 <foo\+0x98> eb1d 0d00 adds.w sp, sp, r0 +0000009c <foo\+0x9c> eb1d 0000 adds.w r0, sp, r0 +000000a0 <foo\+0xa0> eb1d 0040 adds.w r0, sp, r0, lsl #1 +000000a4 <foo\+0xa4> 4485 add sp, r0 +000000a6 <foo\+0xa6> eb0d 0d40 add.w sp, sp, r0, lsl #1 +000000aa <foo\+0xaa> eb1d 0d00 adds.w sp, sp, r0 +000000ae <foo\+0xae> eb1d 0d40 adds.w sp, sp, r0, lsl #1 +000000b2 <foo\+0xb2> 44ed add sp, sp +000000b4 <foo\+0xb4> f1ad 0000 sub.w r0, sp, #0 +000000b8 <foo\+0xb8> f1bd 0000 subs.w r0, sp, #0 +000000bc <foo\+0xbc> f2ad 0000 subw r0, sp, #0 +000000c0 <foo\+0xc0> b080 sub sp, #0 +000000c2 <foo\+0xc2> f1bd 0d00 subs.w sp, sp, #0 +000000c6 <foo\+0xc6> f2ad 0d00 subw sp, sp, #0 +000000ca <foo\+0xca> b080 sub sp, #0 +000000cc <foo\+0xcc> f1bd 0d00 subs.w sp, sp, #0 +000000d0 <foo\+0xd0> ebad 0040 sub.w r0, sp, r0, lsl #1 +000000d4 <foo\+0xd4> ebbd 0040 subs.w r0, sp, r0, lsl #1 +000000d8 <foo\+0xd8> ebad 0d40 sub.w sp, sp, r0, lsl #1 +000000dc <foo\+0xdc> ebbd 0d40 subs.w sp, sp, r0, lsl #1 +000000e0 <foo\+0xe0> a001 add r0, pc, #4 ; \(adr r0, 000000e8 <foo\+0xe8>\) +000000e2 <foo\+0xe2> f2af 0004 subw r0, pc, #4 +000000e6 <foo\+0xe6> f20f 0004 addw r0, pc, #4 +000000ea <foo\+0xea> f2af 0004 subw r0, pc, #4 +000000ee <foo\+0xee> f20f 0004 addw r0, pc, #4 +000000f2 <foo\+0xf2> f2af 0004 subw r0, pc, #4 +000000f6 <foo\+0xf6> bf00 nop +000000f8 <foo\+0xf8> bf00 nop +000000fa <foo\+0xfa> bf00 nop + diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-usage-t.s b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-usage-t.s new file mode 100644 index 00000000..6cfebed4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-usage-t.s @@ -0,0 +1,123 @@ +.arch armv7-r +.syntax unified +.text +.thumb + .global foo +foo: +@ Section A6.1.3 "Use of 0b1101 as a register specifier". + +@ R13 as the source or destination register of a mov instruction. +@ only register to register transfers without shifts are supported, +@ with no flag setting + +mov sp,r0 +mov r0,sp + +@ Using the following instructions to adjust r13 up or down by a +@ multiple of 4: + +add sp,sp,#0 +addw sp,sp,#0 +sub sp,sp,#0 +subw sp,sp,#0 +add sp,sp,r0 +add sp,sp,r0,lsl #1 +sub sp,sp,r0 +sub sp,sp,r0,lsl #1 + +@ R13 as a base register <Rn> of any load/store instruction. + +ldr r0, [sp] +ldr r0, [pc] +ldr pc, [r0] +ldr sp, [r0] +ldr pc, [pc] +ldr sp, [sp] +ldr pc, [sp] +ldr sp, [pc] + +str r0, [sp] +str sp, [r0] +str sp, [sp] + +@ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction. + +add r0, sp, r0 +adds r0, sp, r0 +add r0, sp, r0, lsl #1 +adds r0, sp, r0, lsl #1 + +cmn sp, #0 +cmn sp, r0 +cmn sp, r0, lsl #1 +cmp sp, #0 +cmp sp, r0 +cmp sp, r0, lsl #1 + +sub sp, #0 +subs sp, #0 +sub r0, sp, #0 +subs r0, sp, #0 + +@ ADD (sp plus immediate). + +add sp, #4 +add r0, sp, #4 +adds sp, #4 +adds r0, sp, #4 +addw r0, sp, #4 + +add sp, sp, #4 +adds sp, sp, #4 +addw sp, sp, #4 + +@ ADD (sp plus register). + +add sp, r0 +add r0, sp, r0 +add r0, sp, r0, lsl #1 +adds sp, r0 +adds r0, sp, r0 +adds r0, sp, r0, lsl #1 + +add sp, sp, r0 +add sp, sp, r0, lsl #1 +adds sp, sp, r0 +adds sp, sp, r0, lsl #1 + +add sp, sp, sp + +@ SUB (sp minus immediate). + +sub r0, sp , #0 +subs r0, sp , #0 +subw r0, sp , #0 + +sub sp, sp , #0 +subs sp, sp , #0 +subw sp, sp , #0 + +@ SUB (sp minus register). + +sub sp, #0 +subs sp, #0 +sub r0, sp, r0, lsl #1 +subs r0, sp, r0, lsl #1 + +sub sp, sp, r0, lsl #1 +subs sp, sp, r0, lsl #1 + +@ PC-related insns (equivalent to adr). + +add r0, pc, #4 +sub r0, pc, #4 +adds r0, pc, #4 +subs r0, pc, #4 +addw r0, pc, #4 +subw r0, pc, #4 + +@ nops to pad the section out to an alignment boundary. + +nop +nop +nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.d b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.d new file mode 100644 index 00000000..8579f43a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.d @@ -0,0 +1,2 @@ +# name: Invalid SP and PC operands test - THUMB +# error-output: sp-pc-validations-bad-t.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.l b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.l new file mode 100644 index 00000000..d20f1c5d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.l @@ -0,0 +1,249 @@ +[^:]*: Assembler messages: +[^:]*:27: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\]' +[^:]*:28: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]' +[^:]*:29: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp\]' +[^:]*:30: Error: branch must be last instruction in IT block -- `ldreq r15,\[sp,#0\]' +[^:]*:31: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0\]' +[^:]*:32: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,#0\]' +[^:]*:33: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#-4\]' +[^:]*:34: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0\],#4' +[^:]*:35: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,#0\]!' +[^:]*:38: Error: branch must be last instruction in IT block -- `ldreq r15,label' +[^:]*:39: Error: branch must be last instruction in IT block -- `ldreq.w r15,label' +[^:]*:40: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[pc,#-0\]' +[^:]*:43: Error: branch must be last instruction in IT block -- `ldreq r15,\[r0,r1\]' +[^:]*:44: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1\]' +[^:]*:45: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]' +[^:]*:48: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]' +[^:]*:50: Error: r13 not allowed here -- `ldrb.w sp,\[r0,#4\]' +[^:]*:51: Error: r15 not allowed here -- `ldrb.w pc,\[r0,#4\]' +[^:]*:52: Error: r15 not allowed here -- `ldrb pc,\[r0,#-4\]' +[^:]*:54: Error: r15 not allowed here -- `ldrb pc,\[r0\],#4' +[^:]*:55: Error: r13 not allowed here -- `ldrb sp,\[r0\],#4' +[^:]*:56: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]!' +[^:]*:57: Error: r13 not allowed here -- `ldrb sp,\[r0,#4\]!' +[^:]*:60: Error: r15 not allowed here -- `ldrb pc,label' +[^:]*:61: Error: r15 not allowed here -- `ldrb pc,\[PC,#-0\]' +[^:]*:62: Error: r13 not allowed here -- `ldrb sp,label' +[^:]*:63: Error: r13 not allowed here -- `ldrb sp,\[PC,#-0\]' +[^:]*:66: Error: r15 not allowed here -- `ldrb pc,\[r0,r1\]' +[^:]*:67: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1\]' +[^:]*:68: Error: r15 not allowed here -- `ldrb r0,\[r1,pc\]' +[^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL#1\]' +[^:]*:70: Error: r13 not allowed here -- `ldrb.w sp,\[r0,r1\]' +[^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL#2\]' +[^:]*:72: Error: r13 not allowed here -- `ldrb.w r2,\[r0,sp,LSL#2\]' +[^:]*:75: Error: r15 not allowed here -- `ldrbt pc,\[r0,#4\]' +[^:]*:76: Error: r13 not allowed here -- `ldrbt sp,\[r0,#4\]' +[^:]*:79: Error: r15 not allowed here -- `ldrd pc,r0,\[r1\]' +[^:]*:80: Error: r13 not allowed here -- `ldrd sp,r0,\[r1\]' +[^:]*:81: Error: r12 not allowed here -- `ldrd r12,\[r1\]' +[^:]*:82: Error: r14 not allowed here -- `ldrd r14,\[r1\]' +[^:]*:83: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\]' +[^:]*:84: Error: r13 not allowed here -- `ldrd r0,sp,\[r1\]' +[^:]*:85: Error: r15 not allowed here -- `ldrd pc,r0,\[r1\],#4' +[^:]*:86: Error: r13 not allowed here -- `ldrd sp,r0,\[r1\],#4' +[^:]*:87: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\],#4' +[^:]*:88: Error: r13 not allowed here -- `ldrd r0,sp,\[r1\],#4' +[^:]*:89: Error: r12 not allowed here -- `ldrd r12,\[r1\],#4' +[^:]*:90: Error: r14 not allowed here -- `ldrd r14,\[r1\],#4' +[^:]*:91: Error: r15 not allowed here -- `ldrd pc,r0,\[r1,#4\]!' +[^:]*:92: Error: r13 not allowed here -- `ldrd sp,r0,\[r1,#4\]!' +[^:]*:93: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]!' +[^:]*:94: Error: r13 not allowed here -- `ldrd r0,sp,\[r1,#4\]!' +[^:]*:95: Error: r12 not allowed here -- `ldrd r12,\[r1,#4\]!' +[^:]*:96: Error: r14 not allowed here -- `ldrd r14,\[r1,#4\]!' +[^:]*:99: Error: r15 not allowed here -- `ldrd pc,r0,label' +[^:]*:100: Error: r13 not allowed here -- `ldrd sp,r0,label' +[^:]*:101: Error: r15 not allowed here -- `ldrd r0,pc,label' +[^:]*:102: Error: r13 not allowed here -- `ldrd r0,sp,label' +[^:]*:103: Error: r15 not allowed here -- `ldrd pc,r0,\[pc,#-0\]' +[^:]*:104: Error: r13 not allowed here -- `ldrd sp,r0,\[pc,#-0\]' +[^:]*:105: Error: r15 not allowed here -- `ldrd r0,pc,\[pc,#-0\]' +[^:]*:106: Error: r13 not allowed here -- `ldrd r0,sp,\[pc,#-0\]' +[^:]*:111: Error: r15 not allowed here -- `ldrex pc,\[r0\]' +[^:]*:112: Error: r13 not allowed here -- `ldrex sp,\[r0\]' +[^:]*:113: Error: r15 not allowed here -- `ldrex r0,\[pc\]' +[^:]*:114: Error: r15 not allowed here -- `ldrexb pc,\[r0\]' +[^:]*:115: Error: r13 not allowed here -- `ldrexb sp,\[r0\]' +[^:]*:116: Error: r15 not allowed here -- `ldrexb r0,\[pc\]' +[^:]*:117: Error: r15 not allowed here -- `ldrexd pc,r0,\[r1\]' +[^:]*:118: Error: r13 not allowed here -- `ldrexd sp,r0,\[r1\]' +[^:]*:119: Error: r15 not allowed here -- `ldrexd r0,pc,\[r1\]' +[^:]*:120: Error: r13 not allowed here -- `ldrexd r0,sp,\[r1\]' +[^:]*:121: Error: r15 not allowed here -- `ldrexd r0,r1,\[pc\]' +[^:]*:122: Error: r15 not allowed here -- `ldrexh pc,\[r0\]' +[^:]*:123: Error: r13 not allowed here -- `ldrexh sp,\[r0\]' +[^:]*:124: Error: r15 not allowed here -- `ldrexh r0,\[pc\]' +[^:]*:127: Error: r15 not allowed here -- `ldrh pc,\[r0\]' +[^:]*:128: Error: r15 not allowed here -- `ldrh pc,\[r0,#4\]' +[^:]*:131: Error: r15 not allowed here -- `ldrh.w pc,\[r0\]' +[^:]*:132: Error: r15 not allowed here -- `ldrh.w pc,\[r0,#4\]' +[^:]*:133: Error: r13 not allowed here -- `ldrh.w sp,\[r0\]' +[^:]*:134: Error: r13 not allowed here -- `ldrh.w sp,\[r0,#4\]' +[^:]*:135: Error: r15 not allowed here -- `ldrh pc,\[r0,#-3\]' +[^:]*:137: Error: r15 not allowed here -- `ldrh pc,\[r0\],#4' +[^:]*:138: Error: r13 not allowed here -- `ldrh sp,\[r0\],#4' +[^:]*:139: Error: r15 not allowed here -- `ldrh pc,\[r0,#4\]!' +[^:]*:140: Error: r13 not allowed here -- `ldrh sp,\[r0,#4\]!' +[^:]*:143: Error: r15 not allowed here -- `ldrh pc,label' +[^:]*:144: Error: r15 not allowed here -- `ldrh pc,\[pc,#-0\]' +[^:]*:145: Error: r13 not allowed here -- `ldrh sp,label' +[^:]*:146: Error: r13 not allowed here -- `ldrh sp,\[pc,#-0\]' +[^:]*:149: Error: r15 not allowed here -- `ldrh pc,\[r0,r1\]' +[^:]*:150: Error: cannot use register index with PC-relative addressing -- `ldrh r0,\[pc,r1\]' +[^:]*:151: Error: r15 not allowed here -- `ldrh r0,\[r1,pc\]' +[^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL#1\]' +[^:]*:153: Error: r13 not allowed here -- `ldrh.w sp,\[r0,r1,LSL#1\]' +[^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL#1\]' +[^:]*:155: Error: r13 not allowed here -- `ldrh.w r2,\[r0,sp,LSL#1\]' +[^:]*:158: Error: r15 not allowed here -- `ldrht pc,\[r0,#4\]' +[^:]*:159: Error: r13 not allowed here -- `ldrht sp,\[r0,#4\]' +[^:]*:162: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]' +[^:]*:164: Error: r13 not allowed here -- `ldrsb sp,\[r0,#4\]' +[^:]*:165: Error: r15 not allowed here -- `ldrsb pc,\[r0,#-4\]' +[^:]*:166: Error: r13 not allowed here -- `ldrsb sp,\[r0,#-4\]' +[^:]*:167: Error: r15 not allowed here -- `ldrsb pc,\[r0\],#4' +[^:]*:168: Error: r13 not allowed here -- `ldrsb sp,\[r0\],#4' +[^:]*:169: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]!' +[^:]*:170: Error: r13 not allowed here -- `ldrsb sp,\[r0,#4\]!' +[^:]*:173: Error: r15 not allowed here -- `ldrsb pc,label' +[^:]*:174: Error: r15 not allowed here -- `ldrsb pc,\[pc,#-0\]' +[^:]*:175: Error: r13 not allowed here -- `ldrsb sp,label' +[^:]*:176: Error: r13 not allowed here -- `ldrsb sp,\[pc,#-0\]' +[^:]*:179: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]' +[^:]*:180: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[pc,r1\]' +[^:]*:181: Error: r15 not allowed here -- `ldrsb r0,\[r1,pc\]' +[^:]*:182: Error: r15 not allowed here -- `ldrsb.w pc,\[r0,r1,LSL#2\]' +[^:]*:184: Error: r13 not allowed here -- `ldrsb.w sp,\[r0,r1,LSL#2\]' +[^:]*:185: Error: r15 not allowed here -- `ldrsb.w r2,\[r0,pc,LSL#2\]' +[^:]*:186: Error: r13 not allowed here -- `ldrsb.w r2,\[r0,sp,LSL#2\]' +[^:]*:190: Error: r15 not allowed here -- `ldrsbt pc,\[r0,#4\]' +[^:]*:191: Error: r13 not allowed here -- `ldrsbt sp,\[r0,#4\]' +[^:]*:195: Error: r15 not allowed here -- `ldrsh pc,\[r0,#4\]' +[^:]*:196: Error: r13 not allowed here -- `ldrsh sp,\[r0,#4\]' +[^:]*:197: Error: r15 not allowed here -- `ldrsh pc,\[r0,#-4\]' +[^:]*:198: Error: r15 not allowed here -- `ldrsh pc,\[r0\],#4' +[^:]*:199: Error: r15 not allowed here -- `ldrsh pc,\[r0,#4\]!' +[^:]*:200: Error: r13 not allowed here -- `ldrsh sp,\[r0,#-4\]' +[^:]*:201: Error: r13 not allowed here -- `ldrsh sp,\[r0\],#4' +[^:]*:202: Error: r13 not allowed here -- `ldrsh sp,\[r0,#4\]!' +[^:]*:205: Error: r15 not allowed here -- `ldrsh pc,label' +[^:]*:206: Error: r13 not allowed here -- `ldrsh sp,label' +[^:]*:207: Error: r13 not allowed here -- `ldrsh sp,\[pc,#-0\]' +[^:]*:210: Error: r15 not allowed here -- `ldrsh pc,\[r0,r1\]' +[^:]*:211: Error: cannot use register index with PC-relative addressing -- `ldrsh r0,\[pc,r1\]' +[^:]*:212: Error: r15 not allowed here -- `ldrsh r0,\[r1,pc\]' +[^:]*:214: Error: r15 not allowed here -- `ldrsh.w pc,\[r0,r1,LSL#3\]' +[^:]*:215: Error: r13 not allowed here -- `ldrsh.w sp,\[r0,r1,LSL#3\]' +[^:]*:216: Error: r13 not allowed here -- `ldrsh.w r0,\[r1,sp,LSL#3\]' +[^:]*:217: Error: r15 not allowed here -- `ldrsh.w r0,\[r1,pc,LSL#3\]' +[^:]*:221: Error: r15 not allowed here -- `ldrsht pc,\[r0,#4\]' +[^:]*:222: Error: r13 not allowed here -- `ldrsht sp,\[r0,#4\]' +[^:]*:226: Error: r15 not allowed here -- `ldrt pc,\[r0,#4\]' +[^:]*:227: Error: r13 not allowed here -- `ldrt sp,\[r0,#4\]' +[^:]*:232: Error: r15 not allowed here -- `str pc,\[r0,#4\]' +[^:]*:233: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,#4\]' +[^:]*:234: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#-4\]' +[^:]*:235: Error: cannot use post-indexing with PC-relative addressing -- `str r0,\[pc\],#4' +[^:]*:236: Error: cannot use writeback with PC-relative addressing -- `str r0,\[pc,#4\]!' +[^:]*:239: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1\]' +[^:]*:240: Error: cannot use register index with PC-relative addressing -- `str.w r0,\[pc,r1,LSL#2\]' +[^:]*:246: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,#4\]' +[^:]*:247: Error: r15 not allowed here -- `strb.w pc,\[r0,#4\]' +[^:]*:248: Error: r13 not allowed here -- `strb.w sp,\[r0,#4\]' +[^:]*:249: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,#-4\]' +[^:]*:250: Error: cannot use post-indexing with PC-relative addressing -- `strb r0,\[pc\],#4' +[^:]*:251: Error: cannot use writeback with PC-relative addressing -- `strb r0,\[pc,#4\]!' +[^:]*:252: Error: r15 not allowed here -- `strb pc,\[r0,#-4\]' +[^:]*:253: Error: r15 not allowed here -- `strb pc,\[r0\],#4' +[^:]*:254: Error: r15 not allowed here -- `strb pc,\[r0,#4\]!' +[^:]*:255: Error: r13 not allowed here -- `strb sp,\[r0,#-4\]' +[^:]*:256: Error: r13 not allowed here -- `strb sp,\[r0\],#4' +[^:]*:257: Error: r13 not allowed here -- `strb sp,\[r0,#4\]!' +[^:]*:260: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1\]' +[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strb.w r0,\[pc,r1,LSL#2\]' +[^:]*:262: Error: r15 not allowed here -- `strb.w pc,\[r0,r1\]' +[^:]*:263: Error: r15 not allowed here -- `strb.w pc,\[r0,r1,LSL#2\]' +[^:]*:264: Error: r13 not allowed here -- `strb.w sp,\[r0,r1\]' +[^:]*:265: Error: r13 not allowed here -- `strb.w sp,\[r0,r1,LSL#2\]' +[^:]*:266: Error: r15 not allowed here -- `strb.w r0,\[r1,pc\]' +[^:]*:267: Error: r15 not allowed here -- `strb.w r0,\[r1,pc,LSL#2\]' +[^:]*:268: Error: r13 not allowed here -- `strb.w r0,\[r1,sp\]' +[^:]*:269: Error: r13 not allowed here -- `strb.w r0,\[r1,sp,LSL#2\]' +[^:]*:272: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc,#4\]' +[^:]*:273: Error: r15 not allowed here -- `strbt pc,\[r0,#4\]' +[^:]*:274: Error: r13 not allowed here -- `strbt sp,\[r0,#4\]' +[^:]*:277: Error: cannot use register index with PC-relative addressing -- `strd r0,r1,\[pc,#4\]' +[^:]*:278: Error: cannot use post-indexing with PC-relative addressing -- `strd r0,r1,\[pc\],#4' +[^:]*:279: Error: cannot use writeback with PC-relative addressing -- `strd r0,r1,\[pc,#4\]!' +[^:]*:280: Error: r15 not allowed here -- `strd pc,r0,\[r1,#4\]' +[^:]*:281: Error: r15 not allowed here -- `strd pc,r0,\[r1\],#4' +[^:]*:282: Error: r15 not allowed here -- `strd pc,r0,\[r1,#4\]!' +[^:]*:283: Error: r13 not allowed here -- `strd sp,r0,\[r1,#4\]' +[^:]*:284: Error: r13 not allowed here -- `strd sp,r0,\[r1\],#4' +[^:]*:285: Error: r13 not allowed here -- `strd sp,r0,\[r1,#4\]!' +[^:]*:286: Error: r15 not allowed here -- `strd r0,pc,\[r1,#4\]' +[^:]*:287: Error: r15 not allowed here -- `strd r0,pc,\[r1\],#4' +[^:]*:288: Error: r15 not allowed here -- `strd r0,pc,\[r1,#4\]!' +[^:]*:289: Error: r13 not allowed here -- `strd r0,sp,\[r1,#4\]' +[^:]*:290: Error: r13 not allowed here -- `strd r0,sp,\[r1\],#4' +[^:]*:291: Error: r13 not allowed here -- `strd r0,sp,\[r1,#4\]!' +[^:]*:297: Error: r15 not allowed here -- `strex pc,r0,\[r1\]' +[^:]*:298: Error: r15 not allowed here -- `strex pc,r0,\[r1,#4\]' +[^:]*:299: Error: r13 not allowed here -- `strex sp,r0,\[r1\]' +[^:]*:300: Error: r13 not allowed here -- `strex sp,r0,\[r1,#4\]' +[^:]*:301: Error: r15 not allowed here -- `strex r0,pc,\[r1\]' +[^:]*:302: Error: r15 not allowed here -- `strex r0,pc,\[r1,#4\]' +[^:]*:303: Error: r13 not allowed here -- `strex r0,sp,\[r1\]' +[^:]*:304: Error: r13 not allowed here -- `strex r0,sp,\[r1,#4\]' +[^:]*:305: Error: r15 not allowed here -- `strex r0,r1,\[pc\]' +[^:]*:306: Error: r15 not allowed here -- `strex r0,r1,\[pc,#4\]' +[^:]*:309: Error: r15 not allowed here -- `strexb pc,r0,\[r1\]' +[^:]*:310: Error: r13 not allowed here -- `strexb sp,r0,\[r1\]' +[^:]*:311: Error: r15 not allowed here -- `strexb r0,pc,\[r1\]' +[^:]*:312: Error: r13 not allowed here -- `strexb r0,sp,\[r1\]' +[^:]*:313: Error: r15 not allowed here -- `strexb r0,r1,\[pc\]' +[^:]*:316: Error: r15 not allowed here -- `strexd pc,r0,r1,\[r2\]' +[^:]*:317: Error: r13 not allowed here -- `strexd sp,r0,r1,\[r2\]' +[^:]*:318: Error: r15 not allowed here -- `strexd r0,pc,r1,\[r2\]' +[^:]*:319: Error: r13 not allowed here -- `strexd r0,sp,r1,\[r2\]' +[^:]*:320: Error: r15 not allowed here -- `strexd r0,r1,pc,\[r2\]' +[^:]*:321: Error: r13 not allowed here -- `strexd r0,r1,sp,\[r2\]' +[^:]*:322: Error: r15 not allowed here -- `strexd r0,r1,r2,\[pc\]' +[^:]*:325: Error: r15 not allowed here -- `strexh pc,r0,\[r1\]' +[^:]*:326: Error: r13 not allowed here -- `strexh sp,r0,\[r1\]' +[^:]*:327: Error: r15 not allowed here -- `strexh r0,pc,\[r1\]' +[^:]*:328: Error: r13 not allowed here -- `strexh r0,sp,\[r1\]' +[^:]*:329: Error: r15 not allowed here -- `strexh r0,r1,\[pc\]' +[^:]*:332: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc\]' +[^:]*:333: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,#4\]' +[^:]*:334: Error: cannot use register index with PC-relative addressing -- `strh r0,\[pc,#-4\]' +[^:]*:335: Error: cannot use post-indexing with PC-relative addressing -- `strh r0,\[pc\],#4' +[^:]*:336: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc,#4\]!' +[^:]*:339: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1\]' +[^:]*:340: Error: cannot use register index with PC-relative addressing -- `strh.w r0,\[pc,r1,LSL#2\]' +[^:]*:341: Error: r15 not allowed here -- `strh.w pc,\[r0,#4\]' +[^:]*:342: Error: r15 not allowed here -- `strh.w pc,\[r0\]' +[^:]*:343: Error: r13 not allowed here -- `strh.w sp,\[r0,#4\]' +[^:]*:344: Error: r13 not allowed here -- `strh.w sp,\[r0\]' +[^:]*:345: Error: r15 not allowed here -- `strh pc,\[r0,#-4\]' +[^:]*:346: Error: r15 not allowed here -- `strh pc,\[r0\],#4' +[^:]*:347: Error: r15 not allowed here -- `strh pc,\[r0,#4\]!' +[^:]*:348: Error: r13 not allowed here -- `strh sp,\[r0,#-4\]' +[^:]*:349: Error: r13 not allowed here -- `strh sp,\[r0\],#4' +[^:]*:350: Error: r13 not allowed here -- `strh sp,\[r0,#4\]!' +[^:]*:351: Error: r15 not allowed here -- `strh.w pc,\[r0,r1\]' +[^:]*:352: Error: r13 not allowed here -- `strh.w sp,\[r0,r1\]' +[^:]*:353: Error: r15 not allowed here -- `strh.w r0,\[r1,pc\]' +[^:]*:354: Error: r13 not allowed here -- `strh.w r0,\[r1,sp\]' +[^:]*:355: Error: r15 not allowed here -- `strh.w pc,\[r0,r1,LSL#2\]' +[^:]*:356: Error: r13 not allowed here -- `strh.w sp,\[r0,r1,LSL#2\]' +[^:]*:357: Error: r15 not allowed here -- `strh.w r0,\[r1,pc,LSL#2\]' +[^:]*:358: Error: r13 not allowed here -- `strh.w r0,\[r1,sp,LSL#2\]' +[^:]*:361: Error: cannot use register index with PC-relative addressing -- `strht r0,\[pc,#4\]' +[^:]*:362: Error: r15 not allowed here -- `strht pc,\[r0,#4\]' +[^:]*:363: Error: r13 not allowed here -- `strht sp,\[pc,#4\]' +[^:]*:366: Error: cannot use register index with PC-relative addressing -- `strt r0,\[pc,#4\]' +[^:]*:367: Error: r15 not allowed here -- `strt pc,\[r0,#4\]' +[^:]*:368: Error: r13 not allowed here -- `strt sp,\[r0,#4\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s new file mode 100644 index 00000000..3da08610 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad-t.s @@ -0,0 +1,373 @@ +.syntax unified +.arch armv7-a +.thumb +.macro it_test opcode operands:vararg +itt eq +\opcode\()eq r15, \operands +moveq r0, r0 +.endm + +.macro it_testw opcode operands:vararg +itt eq +\opcode\()eq.w r15, \operands +moveq r0, r0 +.endm + +.macro LOAD operands:vararg +it_test ldr, \operands +.endm + +.macro LOADw operands:vararg +it_testw ldr, \operands +.endm + +@ Loads =============================================================== + +@ LDR (register) +LOAD [r0] +LOAD [r0,#0] +LOAD [sp] +LOAD [sp,#0] +LOADw [r0] +LOADw [r0,#0] +LOAD [r0,#-4] +LOAD [r0],#4 +LOAD [r0,#0]! + +@ LDR (literal) +LOAD label +LOADw label +LOADw [pc, #-0] + +@ LDR (register) +LOAD [r0, r1] +LOADw [r0, r1] +LOADw [r0, r1, LSL #2] + +@ LDRB (immediate, Thumb) +ldrb pc, [r0,#4] @ low reg +@ldrb r0, [pc,#4] @ ALLOWED! +ldrb.w sp, [r0,#4] @ Unpredictable +ldrb.w pc, [r0,#4] @ => PLD +ldrb pc, [r0, #-4] @ => PLD +@ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT +ldrb pc, [r0],#4 @ BadReg +ldrb sp, [r0],#4 @ ditto +ldrb pc,[r0,#4]! @ ditto +ldrb sp,[r0,#4]! @ ditto + +@ LDRB (literal) +ldrb pc,label @ => PLD +ldrb pc,[PC,#-0] @ => PLD (special case) +ldrb sp,label @ Unpredictable +ldrb sp,[PC,#-0] @ ditto + +@ LDRB (register) +ldrb pc,[r0,r1] @ low reg +ldrb r0,[pc,r1] @ ditto +ldrb r0,[r1,pc] @ ditto +ldrb.w pc,[r0,r1,LSL #1] @ => PLD +ldrb.w sp,[r0,r1] @ Unpredictable +ldrb.w r2,[r0,pc,LSL #2] @ BadReg +ldrb.w r2,[r0,sp,LSL #2] @ ditto + +@ LDRBT +ldrbt pc, [r0, #4] @ BadReg +ldrbt sp, [r0, #4] @ ditto + +@ LDRD (immediate) +ldrd pc, r0, [r1] @ BadReg +ldrd sp, r0, [r1] @ ditto +ldrd r12, [r1] @ ditto +ldrd r14, [r1] @ ditto +ldrd r0, pc, [r1] @ ditto +ldrd r0, sp, [r1] @ ditto +ldrd pc, r0, [r1], #4 @ ditto +ldrd sp, r0, [r1], #4 @ ditto +ldrd r0, pc, [r1], #4 @ ditto +ldrd r0, sp, [r1], #4 @ ditto +ldrd r12, [r1], #4 @ ditto +ldrd r14, [r1], #4 @ ditto +ldrd pc, r0, [r1, #4]! @ ditto +ldrd sp, r0, [r1, #4]! @ ditto +ldrd r0, pc, [r1, #4]! @ ditto +ldrd r0, sp, [r1, #4]! @ ditto +ldrd r12, [r1, #4]! @ ditto +ldrd r14, [r1, #4]! @ ditto + +@ LDRD (literal) +ldrd pc, r0, label @ BadReg +ldrd sp, r0, label @ ditto +ldrd r0, pc, label @ ditto +ldrd r0, sp, label @ ditto +ldrd pc, r0, [pc, #-0] @ ditto +ldrd sp, r0, [pc, #-0] @ ditto +ldrd r0, pc, [pc, #-0] @ ditto +ldrd r0, sp, [pc, #-0] @ ditto + +@ LDRD (register): ARM only + +@ LDREX/B/D/H +ldrex pc, [r0] @ BadReg +ldrex sp, [r0] @ ditto +ldrex r0, [pc] @ Unpredictable +ldrexb pc, [r0] @ BadReg +ldrexb sp, [r0] @ ditto +ldrexb r0, [pc] @ Unpredictable +ldrexd pc, r0, [r1] @ BadReg +ldrexd sp, r0, [r1] @ ditto +ldrexd r0, pc, [r1] @ ditto +ldrexd r0, sp, [r1] @ ditto +ldrexd r0, r1, [pc] @ Unpredictable +ldrexh pc, [r0] @ BadReg +ldrexh sp, [r0] @ ditto +ldrexh r0, [pc] @ Unpredictable + +@ LDRH (immediate) +ldrh pc, [r0] @ low reg +ldrh pc, [r0, #4] @ ditto +@ldrh r0, [pc] @ ALLOWED! +@ldrh r0, [pc, #4] @ ditto +ldrh.w pc, [r0] @ => Unallocated memory hints +ldrh.w pc, [r0, #4] @ ditto +ldrh.w sp, [r0] @ Unpredictable +ldrh.w sp, [r0, #4] @ ditto +ldrh pc, [r0, #-3] @ => Unallocated memory hint +@ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT +ldrh pc,[r0],#4 @ BadReg +ldrh sp,[r0],#4 @ ditto +ldrh pc,[r0,#4]! @ ditto +ldrh sp,[r0,#4]! @ ditto + +@ LDRH (literal) +ldrh pc, label @ Unallocated memory hint +ldrh pc, [pc, #-0] @ ditto +ldrh sp, label @ Unpredictable +ldrh sp, [pc, #-0] @ ditto + +@ LDRH (register) +ldrh pc, [r0, r1] @ low reg +ldrh r0, [pc, r1] @ ditto +ldrh r0, [r1, pc] @ ditto +ldrh.w pc,[r0,r1,LSL #1] @ => Unallocated memory hints +ldrh.w sp,[r0,r1,LSL #1] @ Unpredictable +ldrh.w r2,[r0,pc,LSL #1] @ ditto +ldrh.w r2,[r0,sp,LSL #1] @ ditto + +@ LDRHT +ldrht pc, [r0, #4] @ BadReg +ldrht sp, [r0, #4] @ ditto + +@ LDRSB (immediate) +ldrsb pc, [r0, #4] @ => PLI +@ldrsb r0, [pc, #4] => LDRSB (literal) +ldrsb sp, [r0, #4] @ Unpredictable +ldrsb pc, [r0, #-4] @ => PLI +ldrsb sp,[r0,#-4] @ BadReg +ldrsb pc,[r0],#4 @ ditto +ldrsb sp,[r0],#4 @ ditto +ldrsb pc,[r0,#4]! @ ditto +ldrsb sp,[r0,#4]! @ ditto + +@ LDRSB (literal) +ldrsb pc, label @ => PLI +ldrsb pc, [pc, #-0] @ => PLI +ldrsb sp, label @ Unpredictable +ldrsb sp, [pc, #-0] @ ditto + +@ LDRSB (register) +ldrsb pc, [r0, r1] @ low reg +ldrsb r0, [pc, r1] @ ditto +ldrsb r0, [r1, pc] @ ditto +ldrsb.w pc, [r0, r1, LSL #2] @ => PLI +@ldrsb.w r0, [pc, r0, LSL #2] => LDRSB (literal) +ldrsb.w sp, [r0, r1, LSL #2] @ Unpredictable +ldrsb.w r2, [r0, pc, LSL #2] @ ditto +ldrsb.w r2, [r0, sp, LSL #2] @ ditto + +@ LDRSBT +@ldrsbt r0, [pc, #4] => LDRSB (literal) +ldrsbt pc, [r0, #4] @ BadReg +ldrsbt sp, [r0, #4] @ ditto + +@ LDRSH (immediate) +@ldrsh r0,[pc,#4] => LDRSH (literal) +ldrsh pc,[r0,#4] @ => Unallocated memory hints +ldrsh sp,[r0,#4] @ Unpredictable +ldrsh pc, [r0, #-4] @ => Unallocated memory hints +ldrsh pc,[r0],#4 @ BadReg +ldrsh pc,[r0,#4]! @ ditto +ldrsh sp,[r0,#-4] @ ditto +ldrsh sp,[r0],#4 @ ditto +ldrsh sp,[r0,#4]! @ ditto + +@ LDRSH (literal) +ldrsh pc, label @ => Unallocated memory hints +ldrsh sp, label @ Unpredictable +ldrsh sp, [pc,#-0] @ ditto + +@ LDRSH (register) +ldrsh pc,[r0,r1] @ low reg +ldrsh r0,[pc,r1] @ ditto +ldrsh r0,[r1,pc] @ ditto +@ldrsh.w r0,[pc,r1,LSL #3] => LDRSH (literal) +ldrsh.w pc,[r0,r1,LSL #3] @ => Unallocated memory hints +ldrsh.w sp,[r0,r1,LSL #3] @ Unpredictable +ldrsh.w r0,[r1,sp,LSL #3] @ BadReg +ldrsh.w r0,[r1,pc,LSL #3] @ ditto + +@ LDRSHT +@ldrsht r0,[pc,#4] => LDRSH (literal) +ldrsht pc,[r0,#4] @ BadReg +ldrsht sp,[r0,#4] @ ditto + +@ LDRT +@ldrt r0,[pc,#4] => LDR (literal) +ldrt pc,[r0,#4] @ BadReg +ldrt sp,[r0,#4] @ ditto + +@ Stores ============================================================== + +@ STR (immediate, Thumb) +str pc, [r0, #4] @ Unpredictable +str.w r0, [pc, #4] @ Undefined +str r0, [pc, #-4] @ ditto +str r0, [pc], #4 @ ditto +str r0, [pc, #4]! @ ditto + +@ STR (register) +str.w r0,[pc,r1] @ Undefined +str.w r0,[pc,r1,LSL #2] @ ditto +@str.w pc,[r0,r1{,LSL #<imm2>}] @ Unpredictable +@str.w r1,[r0,sp{,LSL #<imm2>}] @ ditto +@str.w r1,[r0,pc{,LSL #<imm2>}] @ ditto + +@ STRB (immediate, Thumb) +strb.w r0,[pc,#4] @ Undefined +strb.w pc,[r0,#4] @ Unpredictable +strb.w sp,[r0,#4] @ ditto +strb r0,[pc,#-4] @ Undefined +strb r0,[pc],#4 @ ditto +strb r0,[pc,#4]! @ ditto +strb pc,[r0,#-4] @ Unpredictable +strb pc,[r0],#4 @ ditto +strb pc,[r0,#4]! @ ditto +strb sp,[r0,#-4] @ ditto +strb sp,[r0],#4 @ ditto +strb sp,[r0,#4]! @ ditto + +@ STRB (register) +strb.w r0,[pc,r1] @ Undefined +strb.w r0,[pc,r1,LSL #2] @ ditto +strb.w pc,[r0,r1] @ Unpredictable +strb.w pc,[r0,r1,LSL #2] @ ditto +strb.w sp,[r0,r1] @ ditto +strb.w sp,[r0,r1,LSL #2] @ ditto +strb.w r0,[r1,pc] @ ditto +strb.w r0,[r1,pc,LSL #2] @ ditto +strb.w r0,[r1,sp] @ ditto +strb.w r0,[r1,sp,LSL #2] @ ditto + +@ STRBT +strbt r0,[pc,#4] @ Undefined +strbt pc,[r0,#4] @ Unpredictable +strbt sp,[r0,#4] @ ditto + +@ STRD (immediate) +strd r0,r1,[pc,#4] @ Unpredictable +strd r0,r1,[pc],#4 @ ditto +strd r0,r1,[pc,#4]! @ ditto +strd pc,r0,[r1,#4] @ ditto +strd pc,r0,[r1],#4 @ ditto +strd pc,r0,[r1,#4]! @ ditto +strd sp,r0,[r1,#4] @ ditto +strd sp,r0,[r1],#4 @ ditto +strd sp,r0,[r1,#4]! @ ditto +strd r0,pc,[r1,#4] @ ditto +strd r0,pc,[r1],#4 @ ditto +strd r0,pc,[r1,#4]! @ ditto +strd r0,sp,[r1,#4] @ ditto +strd r0,sp,[r1],#4 @ ditto +strd r0,sp,[r1,#4]! @ ditto + +@ STRD (register) +@No thumb. + +@ STREX +strex pc,r0,[r1] @ Unpredictable +strex pc,r0,[r1,#4] @ ditto +strex sp,r0,[r1] @ ditto +strex sp,r0,[r1,#4] @ ditto +strex r0,pc,[r1] @ ditto +strex r0,pc,[r1,#4] @ ditto +strex r0,sp,[r1] @ ditto +strex r0,sp,[r1,#4] @ ditto +strex r0,r1,[pc] @ ditto +strex r0,r1,[pc,#4] @ ditto + +@ STREXB +strexb pc,r0,[r1] @ Unpredictable +strexb sp,r0,[r1] @ ditto +strexb r0,pc,[r1] @ ditto +strexb r0,sp,[r1] @ ditto +strexb r0,r1,[pc] @ ditto + +@ STREXD +strexd pc,r0,r1,[r2] @ Unpredictable +strexd sp,r0,r1,[r2] @ ditto +strexd r0,pc,r1,[r2] @ ditto +strexd r0,sp,r1,[r2] @ ditto +strexd r0,r1,pc,[r2] @ ditto +strexd r0,r1,sp,[r2] @ ditto +strexd r0,r1,r2,[pc] @ ditto + +@ STREXH +strexh pc,r0,[r1] @ Unpredictable +strexh sp,r0,[r1] @ ditto +strexh r0,pc,[r1] @ ditto +strexh r0,sp,[r1] @ ditto +strexh r0,r1,[pc] @ ditto + +@ STRH (immediate, Thumb) +strh.w r0,[pc] @ Undefined +strh.w r0,[pc,#4] @ ditto +strh r0,[pc,#-4] @ ditto +strh r0,[pc],#4 @ ditto +strh r0,[pc,#4]! @ ditto + +@ STRH (register) +strh.w r0,[pc,r1] @ Undefined +strh.w r0,[pc,r1,LSL #2] @ ditto +strh.w pc,[r0,#4] @ Unpredictable +strh.w pc,[r0] @ ditto +strh.w sp,[r0,#4] @ ditto +strh.w sp,[r0] @ ditto +strh pc,[r0,#-4] @ ditto +strh pc,[r0],#4 @ ditto +strh pc,[r0,#4]! @ ditto +strh sp,[r0,#-4] @ ditto +strh sp,[r0],#4 @ ditto +strh sp,[r0,#4]! @ ditto +strh.w pc,[r0,r1] @ ditto +strh.w sp,[r0,r1] @ ditto +strh.w r0,[r1,pc] @ ditto +strh.w r0,[r1,sp] @ ditto +strh.w pc,[r0,r1,LSL #2] @ ditto +strh.w sp,[r0,r1,LSL #2] @ ditto +strh.w r0,[r1,pc,LSL #2] @ ditto +strh.w r0,[r1,sp,LSL #2] @ ditto + +@ STRHT +strht r0,[pc,#4] @ Undefined +strht pc,[r0,#4] @ Unpredictable +strht sp,[pc,#4] @ ditto + +@ STRT +strt r0,[pc,#4] @ Undefined +strt pc,[r0,#4] @ Unpredictable +strt sp,[r0,#4] @ ditto + +@ ============================================================================ + +.label: +ldr r0, [r1] diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.d b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.d new file mode 100644 index 00000000..558a683d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.d @@ -0,0 +1,2 @@ +# name: Invalid SP and PC operands test - ARM +# error-output: sp-pc-validations-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.l b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.l new file mode 100644 index 00000000..6e0a52b7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.l @@ -0,0 +1,171 @@ +[^:]*: Assembler messages: +[^:]*:11: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL#2\]' +[^:]*:12: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1,pc,LSL#2\]!' +[^:]*:13: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[r1\],pc,LSL#2' +[^:]*:14: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc,r1,LSL#2\]!' +[^:]*:15: Error: cannot use register index with PC-relative addressing -- `ldr r0,\[pc\],r1,LSL#2' +[^:]*:18: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]' +[^:]*:19: Error: r15 not allowed here -- `ldrb pc,\[r0\],#4' +[^:]*:20: Error: r15 not allowed here -- `ldrb pc,\[r0,#4\]!' +[^:]*:23: Error: r15 not allowed here -- `ldrb pc,label' +[^:]*:24: Error: r15 not allowed here -- `ldrb pc,\[pc,#-0\]' +[^:]*:27: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL#2\]' +[^:]*:28: Error: r15 not allowed here -- `ldrb pc,\[r0,r1,LSL#2\]!' +[^:]*:29: Error: r15 not allowed here -- `ldrb pc,\[r0\],r1,LSL#2' +[^:]*:30: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL#2\]' +[^:]*:31: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1,pc,LSL#2\]!' +[^:]*:32: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[r1\],pc,LSL#2' +[^:]*:33: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc,r1,LSL#2\]!' +[^:]*:34: Error: cannot use register index with PC-relative addressing -- `ldrb r0,\[pc\],r1,LSL#2' +[^:]*:37: Error: r15 not allowed here -- `ldrbt pc,\[r0\],#4' +[^:]*:38: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[pc\],#4' +[^:]*:39: Error: r15 not allowed here -- `ldrbt pc,\[r0\],r1,LSL#4' +[^:]*:40: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[pc\],r1,LSL#4' +[^:]*:41: Error: cannot use register index with PC-relative addressing -- `ldrbt r0,\[r1\],pc,LSL#4' +[^:]*:44: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]' +[^:]*:45: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\],#4' +[^:]*:46: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,#4\]!' +[^:]*:49: Error: r15 not allowed here -- `ldrd r0,pc,label' +[^:]*:50: Error: r15 not allowed here -- `ldrd r0,pc,\[PC,#-0\]' +[^:]*:53: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,r2\]' +[^:]*:54: Error: r15 not allowed here -- `ldrd r0,pc,\[r1,r2\]!' +[^:]*:55: Error: r15 not allowed here -- `ldrd r0,pc,\[r1\],r2' +[^:]*:56: Error: cannot use register index with PC-relative addressing -- `ldrd r0,r1,\[r2,pc\]' +[^:]*:57: Error: cannot use register index with PC-relative addressing -- `ldrd r0,r1,\[r2,pc\]!' +[^:]*:58: Error: cannot use register index with PC-relative addressing -- `ldrd r0,r1,\[r2\],pc' +[^:]*:59: Error: cannot use writeback with PC-relative addressing -- `ldrd r0,r1,\[pc,r2\]!' +[^:]*:60: Error: cannot use writeback with PC-relative addressing -- `ldrd r0,r1,\[pc\],r2' +[^:]*:63: Error: r15 not allowed here -- `ldrex pc,\[r0\]' +[^:]*:64: Error: instruction does not accept this addressing mode -- `ldrex r0,\[pc\]' +[^:]*:67: Error: r15 not allowed here -- `ldrexb pc,\[r0\]' +[^:]*:68: Error: r15 not allowed here -- `ldrexb r0,\[pc\]' +[^:]*:71: Error: r15 not allowed here -- `ldrexd r0,r1,\[pc\]' +[^:]*:74: Error: r15 not allowed here -- `ldrexh pc,\[r0\]' +[^:]*:75: Error: r15 not allowed here -- `ldrexh r0,\[pc\]' +[^:]*:78: Error: r15 not allowed here -- `ldrh pc,\[r0,#4\]' +[^:]*:79: Error: r15 not allowed here -- `ldrh pc,\[r0\],#4' +[^:]*:80: Error: r15 not allowed here -- `ldrh pc,\[r0,#4\]!' +[^:]*:83: Error: r15 not allowed here -- `ldrh pc,label' +[^:]*:84: Error: r15 not allowed here -- `ldrh pc,\[pc,#-0\]' +[^:]*:87: Error: r15 not allowed here -- `ldrh pc,\[r0,r1\]' +[^:]*:88: Error: r15 not allowed here -- `ldrh pc,\[r0,r1\]!' +[^:]*:89: Error: r15 not allowed here -- `ldrh pc,\[r0\],r1' +[^:]*:90: Error: cannot use register index with PC-relative addressing -- `ldrh r0,\[r1,pc\]' +[^:]*:91: Error: cannot use register index with PC-relative addressing -- `ldrh r0,\[r1,pc\]!' +[^:]*:92: Error: cannot use register index with PC-relative addressing -- `ldrh r0,\[r1\],pc' +[^:]*:93: Error: cannot use writeback with PC-relative addressing -- `ldrh r0,\[pc,r1\]!' +[^:]*:94: Error: cannot use writeback with PC-relative addressing -- `ldrh r0,\[pc\],r1' +[^:]*:97: Error: r15 not allowed here -- `ldrht pc,\[r0\],#4' +[^:]*:98: Error: cannot use writeback with PC-relative addressing -- `ldrht r0,\[pc\],#4' +[^:]*:99: Error: r15 not allowed here -- `ldrht pc,\[r0\],r1' +[^:]*:100: Error: cannot use register index with PC-relative addressing -- `ldrht r0,\[pc\],r1' +[^:]*:101: Error: cannot use register index with PC-relative addressing -- `ldrht r0,\[r1\],pc' +[^:]*:104: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]' +[^:]*:105: Error: r15 not allowed here -- `ldrsb pc,\[r0\],#4' +[^:]*:106: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]!' +[^:]*:109: Error: r15 not allowed here -- `ldrsb pc,label' +[^:]*:110: Error: r15 not allowed here -- `ldrsb pc,\[pc,#-0\]' +[^:]*:113: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]' +[^:]*:114: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]!' +[^:]*:115: Error: r15 not allowed here -- `ldrsb pc,\[r0\],r1' +[^:]*:116: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[r1,pc\]' +[^:]*:117: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[r1,pc\]!' +[^:]*:118: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[r1\],pc' +[^:]*:119: Error: cannot use writeback with PC-relative addressing -- `ldrsb r0,\[pc,r1\]!' +[^:]*:120: Error: cannot use writeback with PC-relative addressing -- `ldrsb r0,\[pc\],r1' +[^:]*:123: Error: r15 not allowed here -- `ldrsbt pc,\[r0\],#4' +[^:]*:124: Error: cannot use writeback with PC-relative addressing -- `ldrsbt r0,\[pc\],#4' +[^:]*:125: Error: r15 not allowed here -- `ldrsbt pc,\[r0\],r1' +[^:]*:126: Error: cannot use register index with PC-relative addressing -- `ldrsbt r0,\[pc\],r1' +[^:]*:127: Error: cannot use register index with PC-relative addressing -- `ldrsbt r0,\[r1\],pc' +[^:]*:130: Error: r15 not allowed here -- `ldrsh pc,\[r0,#4\]' +[^:]*:131: Error: r15 not allowed here -- `ldrsh pc,\[r0\],#4' +[^:]*:132: Error: r15 not allowed here -- `ldrsh pc,\[r0,#4\]!' +[^:]*:135: Error: r15 not allowed here -- `ldrsh pc,label' +[^:]*:136: Error: r15 not allowed here -- `ldrsh pc,\[pc,#-0\]' +[^:]*:139: Error: r15 not allowed here -- `ldrsh pc,\[r0,r1\]' +[^:]*:140: Error: r15 not allowed here -- `ldrsh pc,\[r0,r1\]!' +[^:]*:141: Error: r15 not allowed here -- `ldrsh pc,\[r0\],r1' +[^:]*:142: Error: cannot use register index with PC-relative addressing -- `ldrsh r0,\[r1,pc\]' +[^:]*:143: Error: cannot use register index with PC-relative addressing -- `ldrsh r0,\[r1,pc\]!' +[^:]*:144: Error: cannot use register index with PC-relative addressing -- `ldrsh r0,\[r1\],pc' +[^:]*:145: Error: cannot use writeback with PC-relative addressing -- `ldrsh r0,\[pc,r1\]!' +[^:]*:146: Error: cannot use writeback with PC-relative addressing -- `ldrsh r0,\[pc\],r1' +[^:]*:149: Error: r15 not allowed here -- `ldrsht pc,\[r0\],#4' +[^:]*:150: Error: cannot use writeback with PC-relative addressing -- `ldrsht r0,\[pc\],#4' +[^:]*:151: Error: r15 not allowed here -- `ldrsht pc,\[r0\],r1' +[^:]*:152: Error: cannot use register index with PC-relative addressing -- `ldrsht r0,\[pc\],r1' +[^:]*:153: Error: cannot use register index with PC-relative addressing -- `ldrsht r0,\[r1\],pc' +[^:]*:156: Error: r15 not allowed here -- `ldrt pc,\[r0\],#4' +[^:]*:157: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],#4' +[^:]*:158: Error: r15 not allowed here -- `ldrt pc,\[r0\],r1,LSL#4' +[^:]*:159: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[pc\],r1,LSL#4' +[^:]*:160: Error: cannot use register index with PC-relative addressing -- `ldrt r0,\[r1\],pc,LSL#4' +[^:]*:166: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc\],#4' +[^:]*:167: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,#4\]!' +[^:]*:170: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL#4\]' +[^:]*:171: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1,pc,LSL#4\]!' +[^:]*:172: Error: cannot use register index with PC-relative addressing -- `str r0,\[r1\],pc,LSL#4' +[^:]*:175: Error: r15 not allowed here -- `strb pc,\[r0,#4\]' +[^:]*:176: Error: r15 not allowed here -- `strb pc,\[r0\],#4' +[^:]*:177: Error: r15 not allowed here -- `strb pc,\[r0,#4\]!' +[^:]*:178: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc\],#4' +[^:]*:179: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,#4\]!' +[^:]*:182: Error: r15 not allowed here -- `strb pc,\[r0,r1,LSL#4\]' +[^:]*:183: Error: r15 not allowed here -- `strb pc,\[r0,r1,LSL#4\]!' +[^:]*:184: Error: r15 not allowed here -- `strb pc,\[r0\],r1,LSL#4' +[^:]*:185: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0,pc,LSL#4\]' +[^:]*:186: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0,pc,LSL#4\]!' +[^:]*:187: Error: cannot use register index with PC-relative addressing -- `strb r1,\[r0\],pc,LSL#4' +[^:]*:188: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc,r1,LSL#4\]!' +[^:]*:189: Error: cannot use register index with PC-relative addressing -- `strb r0,\[pc\],r1,LSL#4' +[^:]*:192: Error: r15 not allowed here -- `strbt pc,\[r0\],#4' +[^:]*:193: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc\],#4' +[^:]*:194: Error: r15 not allowed here -- `strbt pc,\[r0\],r1,LSL#4' +[^:]*:195: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[pc\],r1,LSL#4' +[^:]*:196: Error: cannot use register index with PC-relative addressing -- `strbt r0,\[r1\],pc,LSL#4' +[^:]*:199: Error: r15 not allowed here -- `strd r0,pc,\[r1,#4\]' +[^:]*:200: Error: r15 not allowed here -- `strd r0,pc,\[r1\],#4' +[^:]*:201: Error: r15 not allowed here -- `strd r0,pc,\[r1,#4\]!' +[^:]*:202: Error: cannot use writeback with PC-relative addressing -- `strd r0,r1,\[pc\],#4' +[^:]*:203: Error: cannot use writeback with PC-relative addressing -- `strd r0,r1,\[pc,#4\]!' +[^:]*:206: Error: r15 not allowed here -- `strd r0,pc,\[r1,r2\]' +[^:]*:207: Error: r15 not allowed here -- `strd r0,pc,\[r1,r2\]!' +[^:]*:208: Error: r15 not allowed here -- `strd r0,pc,\[r1\],r2' +[^:]*:209: Error: cannot use register index with PC-relative addressing -- `strd r0,r1,\[r2,pc\]' +[^:]*:210: Error: cannot use register index with PC-relative addressing -- `strd r0,r1,\[r2,pc\]!' +[^:]*:211: Error: cannot use register index with PC-relative addressing -- `strd r0,r1,\[r2\],pc' +[^:]*:212: Error: cannot use writeback with PC-relative addressing -- `strd r0,r1,\[pc,r2\]!' +[^:]*:213: Error: cannot use writeback with PC-relative addressing -- `strd r0,r1,\[pc\],r2' +[^:]*:216: Error: r15 not allowed here -- `strex pc,r0,\[r1\]' +[^:]*:217: Error: r15 not allowed here -- `strex r0,pc,\[r1\]' +[^:]*:218: Error: instruction does not accept this addressing mode -- `strex r0,r1,\[pc\]' +[^:]*:221: Error: r15 not allowed here -- `strexb pc,r0,\[r1\]' +[^:]*:222: Error: r15 not allowed here -- `strexb r0,pc,\[r1\]' +[^:]*:223: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[pc\]' +[^:]*:226: Error: r15 not allowed here -- `strexd pc,r0,r1,\[r2\]' +[^:]*:227: Error: r15 not allowed here -- `strexd r0,r1,r2,\[pc\]' +[^:]*:230: Error: r15 not allowed here -- `strexh pc,r0,\[r1\]' +[^:]*:231: Error: r15 not allowed here -- `strexh r0,pc,\[r1\]' +[^:]*:232: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[pc\]' +[^:]*:235: Error: r15 not allowed here -- `strh pc,\[r0,#4\]' +[^:]*:236: Error: r15 not allowed here -- `strh pc,\[r0\],#4' +[^:]*:237: Error: r15 not allowed here -- `strh pc,\[r0,#4\]!' +[^:]*:238: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc\],#4' +[^:]*:239: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc,#4\]!' +[^:]*:242: Error: r15 not allowed here -- `strh pc,\[r0,r1\]' +[^:]*:243: Error: r15 not allowed here -- `strh pc,\[r0,r1\]!' +[^:]*:244: Error: r15 not allowed here -- `strh pc,\[r0\],r1' +[^:]*:245: Error: cannot use register index with PC-relative addressing -- `strh r0,\[r1,pc\]' +[^:]*:246: Error: cannot use register index with PC-relative addressing -- `strh r0,\[r1,pc\]!' +[^:]*:247: Error: cannot use register index with PC-relative addressing -- `strh r0,\[r1\],pc' +[^:]*:248: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc,r1\]!' +[^:]*:249: Error: cannot use writeback with PC-relative addressing -- `strh r0,\[pc\],r1' +[^:]*:252: Error: r15 not allowed here -- `strht pc,\[r0\],#4' +[^:]*:253: Error: cannot use writeback with PC-relative addressing -- `strht r0,\[pc\],#4' +[^:]*:254: Error: r15 not allowed here -- `strht pc,\[r0\],r1' +[^:]*:255: Error: cannot use register index with PC-relative addressing -- `strht r0,\[pc\],r1' +[^:]*:256: Error: cannot use register index with PC-relative addressing -- `strht r0,\[r1\],pc' +[^:]*:259: Error: cannot use register index with PC-relative addressing -- `strt r0,\[pc\],#4' +[^:]*:260: Error: cannot use register index with PC-relative addressing -- `strt r0,\[pc\],r1,LSL#4' +[^:]*:261: Error: cannot use register index with PC-relative addressing -- `strt r0,\[r1\],pc,LSL#4' diff --git a/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.s b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.s new file mode 100644 index 00000000..70c7bb0e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/sp-pc-validations-bad.s @@ -0,0 +1,266 @@ +.syntax unified + +@ Loads, ARM ================================================================ +.arm + +@ LDR (immediate, ARM) +@ LDR (literal) +@No unpredictable or undefined combinations. + +@ LDR (register) +ldr r0,[r1,pc, LSL #2] @ Unpredictable +ldr r0,[r1,pc, LSL #2]! @ ditto +ldr r0,[r1],pc, LSL #2 @ ditto +ldr r0,[pc,r1, LSL #2]! @ ditto +ldr r0,[pc],r1, LSL #2 @ ditto + +@ LDRB (immediate, ARM) +ldrb pc,[r0,#4] @ Unpredictable +ldrb pc,[r0],#4 @ ditto +ldrb pc,[r0,#4]! @ ditto + +@ LDRB (literal) +ldrb pc, label @ Unpredictable +ldrb pc,[pc,#-0] @ ditto + +@ LDRB (register) +ldrb pc,[r0,r1, LSL #2] @ Unpredictable +ldrb pc,[r0,r1, LSL #2]! @ ditto +ldrb pc,[r0],r1, LSL #2 @ ditto +ldrb r0,[r1,pc, LSL #2] @ ditto +ldrb r0,[r1,pc, LSL #2]! @ ditto +ldrb r0,[r1],pc, LSL #2 @ ditto +ldrb r0,[pc,r1, LSL #2]! @ ditto +ldrb r0,[pc],r1, LSL #2 @ ditto + +@ LDRBT +ldrbt pc,[r0],#4 @ Unpredictable +ldrbt r0,[pc],#4 @ ditto +ldrbt pc,[r0],r1, LSL #4 @ ditto +ldrbt r0,[pc],r1, LSL #4 @ ditto +ldrbt r0,[r1],pc, LSL #4 @ ditto + +@ LDRD (immediate) +ldrd r0,pc,[r1,#4] @ Unpredictable +ldrd r0,pc,[r1],#4 @ ditto +ldrd r0,pc,[r1,#4]! @ ditto + +@ LDRD (literal) +ldrd r0,pc, label @ Unpredictable +ldrd r0,pc,[PC,#-0] @ ditto + +@ LDRD (register) +ldrd r0,pc,[r1,r2] @ Unpredictable +ldrd r0,pc,[r1,r2]! @ ditto +ldrd r0,pc,[r1],r2 @ ditto +ldrd r0,r1,[r2,pc] @ ditto +ldrd r0,r1,[r2,pc]! @ ditto +ldrd r0,r1,[r2],pc @ ditto +ldrd r0,r1,[pc,r2]! @ ditto +ldrd r0,r1,[pc],r2 @ ditto + +@ LDREX +ldrex pc,[r0] @ Unpredictable +ldrex r0,[pc] @ ditto + +@ LDREXB +ldrexb pc,[r0] @ Unpredictable +ldrexb r0,[pc] @ ditto + +@ LDREXD +ldrexd r0,r1,[pc] @ Unpredictable + +@ LDREXH +ldrexh pc,[r0] @ Unpredictable +ldrexh r0,[pc] @ ditto + +@ LDRH (immediate, ARM) +ldrh pc,[r0,#4] @ Unpredictable +ldrh pc,[r0],#4 @ ditto +ldrh pc,[r0,#4]! @ ditto + +@ LDRH (literal) +ldrh pc, label @ Unpredictable +ldrh pc,[pc,#-0] @ ditto + +@ LDRH (register) +ldrh pc,[r0,r1] @ Unpredictable +ldrh pc,[r0,r1]! @ ditto +ldrh pc,[r0],r1 @ ditto +ldrh r0,[r1,pc] @ ditto +ldrh r0,[r1,pc]! @ ditto +ldrh r0,[r1],pc @ ditto +ldrh r0,[pc,r1]! @ ditto +ldrh r0,[pc],r1 @ ditto + +@ LDRHT +ldrht pc, [r0], #4 @ Unpredictable +ldrht r0, [pc], #4 @ ditto +ldrht pc, [r0], r1 @ ditto +ldrht r0, [pc], r1 @ ditto +ldrht r0, [r1], pc @ ditto + +@ LDRSB (immediate) +ldrsb pc,[r0,#4] @ Unpredictable +ldrsb pc,[r0],#4 @ ditto +ldrsb pc,[r0,#4]! @ ditto + +@ LDRSB (literal) +ldrsb pc, label @ Unpredictable +ldrsb pc,[pc,#-0] @ ditto + +@ LDRSB (register) +ldrsb pc,[r0,r1] @ Unpredictable +ldrsb pc,[r0,r1]! @ ditto +ldrsb pc,[r0],r1 @ ditto +ldrsb r0,[r1,pc] @ ditto +ldrsb r0,[r1,pc]! @ ditto +ldrsb r0,[r1],pc @ ditto +ldrsb r0,[pc,r1]! @ ditto +ldrsb r0,[pc],r1 @ ditto + +@ LDRSBT +ldrsbt pc, [r0], #4 @ Unpredictable +ldrsbt r0, [pc], #4 @ ditto +ldrsbt pc, [r0], r1 @ ditto +ldrsbt r0, [pc], r1 @ ditto +ldrsbt r0, [r1], pc @ ditto + +@ LDRSH (immediate) +ldrsh pc,[r0,#4] @ Unpredictable +ldrsh pc,[r0],#4 @ ditto +ldrsh pc,[r0,#4]! @ ditto + +@ LDRSH (literal) +ldrsh pc, label @ Unpredictable +ldrsh pc,[pc,#-0] @ ditto + +@ LDRSH (register) +ldrsh pc,[r0,r1] @ Unpredictable +ldrsh pc,[r0,r1]! @ ditto +ldrsh pc,[r0],r1 @ ditto +ldrsh r0,[r1,pc] @ ditto +ldrsh r0,[r1,pc]! @ ditto +ldrsh r0,[r1],pc @ ditto +ldrsh r0,[pc,r1]! @ ditto +ldrsh r0,[pc],r1 @ ditto + +@ LDRSHT +ldrsht pc, [r0], #4 @ Unpredictable +ldrsht r0, [pc], #4 @ ditto +ldrsht pc, [r0], r1 @ ditto +ldrsht r0, [pc], r1 @ ditto +ldrsht r0, [r1], pc @ ditto + +@ LDRT +ldrt pc, [r0], #4 @ Unpredictable +ldrt r0, [pc], #4 @ ditto +ldrt pc,[r0],r1, LSL #4 @ ditto +ldrt r0,[pc],r1, LSL #4 @ ditto +ldrt r0,[r1],pc, LSL #4 @ ditto + + +@ Stores, ARM ================================================================ + +@ STR (immediate, ARM) +str r0,[pc],#4 @ Unpredictable +str r0,[pc,#4]! @ ditto + +@ STR (register) +str r0,[r1,pc, LSL #4] @ Unpredictable +str r0,[r1,pc, LSL #4]! @ ditto +str r0,[r1],pc, LSL #4 @ ditto + +@ STRB (immediate, ARM) +strb pc,[r0,#4] @ Unpredictable +strb pc,[r0],#4 @ ditto +strb pc,[r0,#4]! @ ditto +strb r0,[pc],#4 @ ditto +strb r0,[pc,#4]! @ ditto + +@ STRB (register) +strb pc,[r0,r1, LSL #4] @ Unpredictable +strb pc,[r0,r1, LSL #4]! @ ditto +strb pc,[r0],r1, LSL #4 @ ditto +strb r1,[r0,pc, LSL #4] @ ditto +strb r1,[r0,pc, LSL #4]! @ ditto +strb r1,[r0],pc, LSL #4 @ ditto +strb r0,[pc,r1, LSL #4]! @ ditto +strb r0,[pc],r1, LSL #4 @ ditto + +@ STRBT +strbt pc,[r0],#4 @ Unpredictable +strbt r0,[pc],#4 @ ditto +strbt pc,[r0],r1, LSL #4 @ ditto +strbt r0,[pc],r1, LSL #4 @ ditto +strbt r0,[r1],pc, LSL #4 @ ditto + +@ STRD (immediate) +strd r0,pc,[r1,#4] @ ditto +strd r0,pc,[r1],#4 @ ditto +strd r0,pc,[r1,#4]! @ ditto +strd r0,r1,[pc],#4 @ ditto +strd r0,r1,[pc,#4]! @ ditto + +@STRD (register) +strd r0,pc,[r1,r2] @ Unpredictable +strd r0,pc,[r1,r2]! @ ditto +strd r0,pc,[r1],r2 @ ditto +strd r0,r1,[r2,pc] @ ditto +strd r0,r1,[r2,pc]! @ ditto +strd r0,r1,[r2],pc @ ditto +strd r0,r1,[pc,r2]! @ ditto +strd r0,r1,[pc],r2 @ ditto + +@ STREX +strex pc,r0,[r1] @ Unpredictable +strex r0,pc,[r1] @ ditto +strex r0,r1,[pc] @ ditto + +@ STREXB +strexb pc,r0,[r1] @ Unpredictable +strexb r0,pc,[r1] @ ditto +strexb r0,r1,[pc] @ ditto + +@ STREXD +strexd pc,r0,r1,[r2] @ Unpredictable +strexd r0,r1,r2,[pc] @ ditto + +@ STREXH +strexh pc,r0,[r1] @ Unpredictable +strexh r0,pc,[r1] @ ditto +strexh r0,r1,[pc] @ ditto + +@ STRH (immediate, ARM) +strh pc,[r0,#4] @ Unpredictable +strh pc,[r0],#4 @ ditto +strh pc,[r0,#4]! @ ditto +strh r0,[pc],#4 @ ditto +strh r0,[pc,#4]! @ ditto + +@ STRH (register) +strh pc,[r0,r1] @ Unpredictable +strh pc,[r0,r1]! @ ditto +strh pc,[r0],r1 @ ditto +strh r0,[r1,pc] @ ditto +strh r0,[r1,pc]! @ ditto +strh r0,[r1],pc @ ditto +strh r0,[pc,r1]! @ ditto +strh r0,[pc],r1 @ ditto + +@ STRHT +strht pc, [r0], #4 @ Unpredictable +strht r0, [pc], #4 @ ditto +strht pc, [r0], r1 @ ditto +strht r0, [pc], r1 @ ditto +strht r0, [r1], pc @ ditto + +@ STRT +strt r0, [pc], #4 @ Unpredictable +strt r0, [pc],r1, LSL #4 @ ditto +strt r0, [r1],pc, LSL #4 @ ditto + +@ ============================================================================ + +.label: +ldr r0, [r1] diff --git a/binutils-2.25/gas/testsuite/gas/arm/srs-arm.d b/binutils-2.25/gas/testsuite/gas/arm/srs-arm.d new file mode 100644 index 00000000..844c692d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/srs-arm.d @@ -0,0 +1,2 @@ +# name: SRS instruction in ARM mode +# error-output: srs-arm.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/srs-arm.l b/binutils-2.25/gas/testsuite/gas/arm/srs-arm.l new file mode 100644 index 00000000..11389737 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/srs-arm.l @@ -0,0 +1,10 @@ +[^:]*: Assembler messages: +[^:]*:12: Error: SRS base register must be r13 -- `srsdb r4,#13' +[^:]*:13: Error: SRS base register must be r13 -- `srsda r4,#13' +[^:]*:14: Error: SRS base register must be r13 -- `srsia r4,#13' +[^:]*:15: Error: SRS base register must be r13 -- `srsib r4,#13' +[^:]*:24: Error: SRS base register must be r13 -- `srsea r4,#13' +[^:]*:25: Error: SRS base register must be r13 -- `srsfd r4,#13' +[^:]*:26: Error: SRS base register must be r13 -- `srsfa r4,#13' +[^:]*:27: Error: SRS base register must be r13 -- `srsed r4,#13' +[^:]*:30: Error: SRS base register must be r13 -- `srs r4,#13' diff --git a/binutils-2.25/gas/testsuite/gas/arm/srs-arm.s b/binutils-2.25/gas/testsuite/gas/arm/srs-arm.s new file mode 100644 index 00000000..5c24b507 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/srs-arm.s @@ -0,0 +1,30 @@ + .arch armv6 + +foo: + srsdb r13, #13 + srsdb r13!, #13 + srsia r13, #13 + srsia r13!, #13 + srsda r13, #13 + srsda r13!, #13 + srsib r13, #13 + srsib r13!, #13 + srsdb r4, #13 + srsda r4, #13 + srsia r4, #13 + srsib r4, #13 + srsea r13, #13 + srsea r13!, #13 + srsfd r13, #13 + srsfd r13!, #13 + srsfa r13, #13 + srsfa r13!, #13 + srsed r13, #13 + srsed r13!, #13 + srsea r4, #13 + srsfd r4, #13 + srsfa r4, #13 + srsed r4, #13 + srs r13, #13 + srs r13!, #13 + srs r4, #13 diff --git a/binutils-2.25/gas/testsuite/gas/arm/srs-t2.d b/binutils-2.25/gas/testsuite/gas/arm/srs-t2.d new file mode 100644 index 00000000..dfa57dbd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/srs-t2.d @@ -0,0 +1,2 @@ +# name: SRS instruction in Thumb-2 mode +# error-output: srs-t2.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/srs-t2.l b/binutils-2.25/gas/testsuite/gas/arm/srs-t2.l new file mode 100644 index 00000000..e5f6fd4f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/srs-t2.l @@ -0,0 +1,6 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: SRS base register must be r13 -- `srsdb r4,#13' +[^:]*:9: Error: SRS base register must be r13 -- `srsia r4,#13' +[^:]*:16: Error: SRS base register must be r13 -- `srsea r4,#13' +[^:]*:17: Error: SRS base register must be r13 -- `srsfd r4,#13' +[^:]*:18: Error: SRS base register must be r13 -- `srs r4,#13' diff --git a/binutils-2.25/gas/testsuite/gas/arm/srs-t2.s b/binutils-2.25/gas/testsuite/gas/arm/srs-t2.s new file mode 100644 index 00000000..780d3ca1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/srs-t2.s @@ -0,0 +1,19 @@ + .arch armv6t2 + +foo: + srsdb r13, #13 + srsdb r13!, #13 + srsia r13, #13 + srsia r13!, #13 + srsdb r4, #13 + srsia r4, #13 + srsea r13, #13 + srsea r13!, #13 + srsfd r13, #13 + srsfd r13!, #13 + srs r13, #13 + srs r13!, #13 + srsea r4, #13 + srsfd r4, #13 + srs r4, #13 + diff --git a/binutils-2.25/gas/testsuite/gas/arm/stm-ldm.d b/binutils-2.25/gas/testsuite/gas/arm/stm-ldm.d new file mode 100644 index 00000000..3d940a53 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/stm-ldm.d @@ -0,0 +1,43 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: STM and LDM +#warning: writeback of base register when in register list is UNPREDICTABLE + +# Test the `STM*' and `LDM*' instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <.*> e92d0001 stmfd sp!, {r0} +0+004 <.*> e92d0002 stmfd sp!, {r1} +0+008 <.*> e92d0004 stmfd sp!, {r2} +0+00c <.*> e92d0008 stmfd sp!, {r3} +0+010 <.*> e92d0010 stmfd sp!, {r4} +0+014 <.*> e92d0020 stmfd sp!, {r5} +0+018 <.*> e92d0040 stmfd sp!, {r6} +0+01c <.*> e92d0080 stmfd sp!, {r7} +0+020 <.*> e92d0100 stmfd sp!, {r8} +0+024 <.*> e92d0200 stmfd sp!, {r9} +0+028 <.*> e92d0400 stmfd sp!, {sl} +0+02c <.*> e92d0800 stmfd sp!, {fp} +0+030 <.*> e92d1000 stmfd sp!, {ip} +0+034 <.*> e92d2000 stmfd sp!, {sp} +0+038 <.*> e92d4000 stmfd sp!, {lr} +0+03c <.*> e92d8000 stmfd sp!, {pc} +0+040 <.*> e92d000e push {r1, r2, r3} +0+044 <.*> e8bd000e pop {r1, r2, r3} +0+048 <.*> e8bd0001 ldmfd sp!, {r0} +0+04c <.*> e8bd0002 ldmfd sp!, {r1} +0+050 <.*> e8bd0004 ldmfd sp!, {r2} +0+054 <.*> e8bd0008 ldmfd sp!, {r3} +0+058 <.*> e8bd0010 ldmfd sp!, {r4} +0+05c <.*> e8bd0020 ldmfd sp!, {r5} +0+060 <.*> e8bd0040 ldmfd sp!, {r6} +0+064 <.*> e8bd0080 ldmfd sp!, {r7} +0+068 <.*> e8bd0100 ldmfd sp!, {r8} +0+06c <.*> e8bd0200 ldmfd sp!, {r9} +0+070 <.*> e8bd0400 ldmfd sp!, {sl} +0+074 <.*> e8bd0800 ldmfd sp!, {fp} +0+078 <.*> e8bd1000 ldmfd sp!, {ip} +0+07c <.*> e8bd2000 ldmfd sp!, {sp} +0+080 <.*> e8bd4000 ldmfd sp!, {lr} +0+084 <.*> e8bd8000 ldmfd sp!, {pc} diff --git a/binutils-2.25/gas/testsuite/gas/arm/stm-ldm.s b/binutils-2.25/gas/testsuite/gas/arm/stm-ldm.s new file mode 100644 index 00000000..d35179d2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/stm-ldm.s @@ -0,0 +1,36 @@ + .text + .syntax unified + stmfd sp!, {r0} + stmfd sp!, {r1} + stmfd sp!, {r2} + stmfd sp!, {r3} + stmfd sp!, {r4} + stmfd sp!, {r5} + stmfd sp!, {r6} + stmfd sp!, {r7} + stmfd sp!, {r8} + stmfd sp!, {r9} + stmfd sp!, {sl} + stmfd sp!, {fp} + stmfd sp!, {ip} + stmfd sp!, {sp} + stmfd sp!, {lr} + stmfd sp!, {pc} + stmfd sp!, {r1, r2, r3} + ldmia sp!, {r1, r2, r3} + ldmia sp!, {r0} + ldmia sp!, {r1} + ldmia sp!, {r2} + ldmia sp!, {r3} + ldmia sp!, {r4} + ldmia sp!, {r5} + ldmia sp!, {r6} + ldmia sp!, {r7} + ldmia sp!, {r8} + ldmia sp!, {r9} + ldmia sp!, {sl} + ldmia sp!, {fp} + ldmia sp!, {ip} + ldmia sp!, {sp} + ldmia sp!, {lr} + ldmia sp!, {pc} diff --git a/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.d b/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.d new file mode 100644 index 00000000..f5ec4c59 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.d @@ -0,0 +1,3 @@ +# name: Bad addressing modes STREXH/STREXB. - THUMB +# error-output: strex-bad-t.l + diff --git a/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.l b/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.l new file mode 100644 index 00000000..a4900964 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.l @@ -0,0 +1,24 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: r15 not allowed here -- `strexh r0,r1,#0x04' +[^:]*:8: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2\],#0x04' +[^:]*:9: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2,#\+0x00\]!' +[^:]*:10: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2,r3\]' +[^:]*:11: Error: registers may not be the same -- `strexh r0,r0,\[r1]' +[^:]*:12: Error: instruction does not accept this addressing mode -- `strexh r0,r1,\[r2,#-0x04\]' +[^:]*:13: Error: r15 not allowed here -- `strexh r0,r1,\[r15\]' +[^:]*:14: Error: r13 not allowed here -- `strexh r0,r13,\[r1\]' +[^:]*:15: Error: r15 not allowed here -- `strexh r0,r15,\[r1\]' +[^:]*:16: Error: r13 not allowed here -- `strexh r13,r0,\[r1\]' +[^:]*:17: Error: r15 not allowed here -- `strexh r15,r0,\[r1\]' +[^:]*:21: Error: r15 not allowed here -- `strexb r0,r1,#0x04' +[^:]*:22: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2\],#0x04' +[^:]*:23: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2,#\+0x00\]!' +[^:]*:24: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2,r3\]' +[^:]*:25: Error: registers may not be the same -- `strexb r0,r0,\[r1]' +[^:]*:26: Error: instruction does not accept this addressing mode -- `strexb r0,r1,\[r2,#-0x04\]' +[^:]*:27: Error: r15 not allowed here -- `strexb r0,r1,\[r15\]' +[^:]*:28: Error: r13 not allowed here -- `strexb r0,r13,\[r1\]' +[^:]*:29: Error: r15 not allowed here -- `strexb r0,r15,\[r1\]' +[^:]*:30: Error: r13 not allowed here -- `strexb r13,r0,\[r1\]' +[^:]*:31: Error: r15 not allowed here -- `strexb r15,r0,\[r1\]' + diff --git a/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.s b/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.s new file mode 100644 index 00000000..1466ca59 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/strex-bad-t.s @@ -0,0 +1,32 @@ +.syntax unified + +.thumb + +@ strexh + +strexh r0, r1, #0x04 +strexh r0, r1, [r2], #0x04 +strexh r0, r1, [r2, #+0x00]! +strexh r0, r1, [r2, r3] +strexh r0, r0, [r1] +strexh r0, r1, [r2, #-0x04] +strexh r0, r1, [r15] +strexh r0, r13, [r1] +strexh r0, r15, [r1] +strexh r13, r0, [r1] +strexh r15, r0, [r1] + +@ strexb + +strexb r0, r1, #0x04 +strexb r0, r1, [r2], #0x04 +strexb r0, r1, [r2, #+0x00]! +strexb r0, r1, [r2, r3] +strexb r0, r0, [r1] +strexb r0, r1, [r2, #-0x04] +strexb r0, r1, [r15] +strexb r0, r13, [r1] +strexb r0, r15, [r1] +strexb r13, r0, [r1] +strexb r15, r0, [r1] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/strex-t.d b/binutils-2.25/gas/testsuite/gas/arm/strex-t.d new file mode 100644 index 00000000..c38eda64 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/strex-t.d @@ -0,0 +1,14 @@ +# name: STREXH/STREXB. - Thumb +# objdump: -dr --prefix-address --show-raw-insn +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+00 <[^>]+> e8c2 1f50 strexh r0, r1, \[r2\] +0+04 <[^>]+> e8c2 1f50 strexh r0, r1, \[r2\] +0+08 <[^>]+> e8cd 1f50 strexh r0, r1, \[sp\] +0+0c <[^>]+> e8c2 1f40 strexb r0, r1, \[r2\] +0+10 <[^>]+> e8c2 1f40 strexb r0, r1, \[r2\] +0+14 <[^>]+> e8cd 1f40 strexb r0, r1, \[sp\] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/strex-t.s b/binutils-2.25/gas/testsuite/gas/arm/strex-t.s new file mode 100644 index 00000000..d8cddfcf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/strex-t.s @@ -0,0 +1,10 @@ +.syntax unified +.thumb + strexh r0, r1, [r2] + strexh r0, r1, [r2, #+0x00] + strexh r0, r1, [r13] + + strexb r0, r1, [r2] + strexb r0, r1, [r2, #+0x00] + strexb r0, r1, [r13] + diff --git a/binutils-2.25/gas/testsuite/gas/arm/svc.d b/binutils-2.25/gas/testsuite/gas/arm/svc.d new file mode 100644 index 00000000..c1bf5b24 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/svc.d @@ -0,0 +1,14 @@ +# name: SWI/SVC instructions +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+000 <[^>]+> ef123456 (swi|svc) 0x00123456 +0+004 <[^>]+> ef876543 (swi|svc) 0x00876543 +0+008 <[^>]+> ef123456 (swi|svc) 0x00123456 +0+00c <[^>]+> ef876543 (swi|svc) 0x00876543 +0+010 <[^>]+> df5a (swi|svc) 90.* +0+012 <[^>]+> dfa5 (swi|svc) 165.* +0+014 <[^>]+> df5a (swi|svc) 90.* +0+016 <[^>]+> dfa5 (swi|svc) 165.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/svc.s b/binutils-2.25/gas/testsuite/gas/arm/svc.s new file mode 100644 index 00000000..734bd75b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/svc.s @@ -0,0 +1,15 @@ + .text + .arch armv4t + .syntax unified +foo: + swi 0x123456 + swi 0x876543 + svc 0x123456 + svc 0x876543 + + .thumb +bar: + swi 0x5a + swi 0xa5 + svc 0x5a + svc 0xa5 diff --git a/binutils-2.25/gas/testsuite/gas/arm/t16-bad.d b/binutils-2.25/gas/testsuite/gas/arm/t16-bad.d new file mode 100644 index 00000000..b5603add --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/t16-bad.d @@ -0,0 +1,3 @@ +#name: Valid ARM, invalid Thumb +#as: -march=armv6k +#error-output: t16-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/t16-bad.l b/binutils-2.25/gas/testsuite/gas/arm/t16-bad.l new file mode 100644 index 00000000..68ec987d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/t16-bad.l @@ -0,0 +1,194 @@ +[^:]*: Assembler messages: +[^:]*:36: Error: lo register required -- `tst r8,r0' +[^:]*:36: Error: lo register required -- `tst r0,r8' +[^:]*:36: Error: unshifted register required -- `tst r0,#12' +[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl#2' +[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl r3' +[^:]*:37: Error: lo register required -- `cmn r8,r0' +[^:]*:37: Error: lo register required -- `cmn r0,r8' +[^:]*:37: Error: unshifted register required -- `cmn r0,#12' +[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl#2' +[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl r3' +[^:]*:38: Error: lo register required -- `mvn r8,r0' +[^:]*:38: Error: lo register required -- `mvn r0,r8' +[^:]*:38: Error: unshifted register required -- `mvn r0,#12' +[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl#2' +[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl r3' +[^:]*:39: Error: lo register required -- `neg r8,r0' +[^:]*:39: Error: lo register required -- `neg r0,r8' +[^:]*:40: Error: lo register required -- `rev r8,r0' +[^:]*:40: Error: lo register required -- `rev r0,r8' +[^:]*:41: Error: lo register required -- `rev16 r8,r0' +[^:]*:41: Error: lo register required -- `rev16 r0,r8' +[^:]*:42: Error: lo register required -- `revsh r8,r0' +[^:]*:42: Error: lo register required -- `revsh r0,r8' +[^:]*:43: Error: lo register required -- `sxtb r8,r0' +[^:]*:43: Error: lo register required -- `sxtb r0,r8' +[^:]*:43: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8' +[^:]*:44: Error: lo register required -- `sxth r8,r0' +[^:]*:44: Error: lo register required -- `sxth r0,r8' +[^:]*:44: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8' +[^:]*:45: Error: lo register required -- `uxtb r8,r0' +[^:]*:45: Error: lo register required -- `uxtb r0,r8' +[^:]*:45: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8' +[^:]*:46: Error: lo register required -- `uxth r8,r0' +[^:]*:46: Error: lo register required -- `uxth r0,r8' +[^:]*:46: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8' +[^:]*:48: Error: dest must overlap one source register -- `adc r1,r2,r3' +[^:]*:48: Error: lo register required -- `adc r8,r0' +[^:]*:48: Error: lo register required -- `adc r0,r8' +[^:]*:48: Error: unshifted register required -- `adc r0,#12' +[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl#2' +[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl r3' +[^:]*:49: Error: dest must overlap one source register -- `and r1,r2,r3' +[^:]*:49: Error: lo register required -- `and r8,r0' +[^:]*:49: Error: lo register required -- `and r0,r8' +[^:]*:49: Error: unshifted register required -- `and r0,#12' +[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl#2' +[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl r3' +[^:]*:50: Error: dest and source1 must be the same register -- `bic r1,r2,r3' +[^:]*:50: Error: lo register required -- `bic r8,r0' +[^:]*:50: Error: lo register required -- `bic r0,r8' +[^:]*:50: Error: unshifted register required -- `bic r0,#12' +[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl#2' +[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl r3' +[^:]*:51: Error: dest must overlap one source register -- `eor r1,r2,r3' +[^:]*:51: Error: lo register required -- `eor r8,r0' +[^:]*:51: Error: lo register required -- `eor r0,r8' +[^:]*:51: Error: unshifted register required -- `eor r0,#12' +[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl#2' +[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl r3' +[^:]*:52: Error: dest must overlap one source register -- `orr r1,r2,r3' +[^:]*:52: Error: lo register required -- `orr r8,r0' +[^:]*:52: Error: lo register required -- `orr r0,r8' +[^:]*:52: Error: unshifted register required -- `orr r0,#12' +[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl#2' +[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl r3' +[^:]*:53: Error: dest and source1 must be the same register -- `sbc r1,r2,r3' +[^:]*:53: Error: lo register required -- `sbc r8,r0' +[^:]*:53: Error: lo register required -- `sbc r0,r8' +[^:]*:53: Error: unshifted register required -- `sbc r0,#12' +[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl#2' +[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl r3' +[^:]*:54: Error: dest must overlap one source register -- `mul r1,r2,r3' +[^:]*:54: Error: lo register required -- `mul r8,r0' +[^:]*:54: Error: lo register required -- `mul r0,r8' +[^:]*:62: Error: lo register required -- `asr r8,r0,#12' +[^:]*:62: Error: lo register required -- `asr r0,r8,#12' +[^:]*:62: Error: lo register required -- `asr r8,r0' +[^:]*:62: Error: lo register required -- `asr r0,r8' +[^:]*:63: Error: lo register required -- `lsl r8,r0,#12' +[^:]*:63: Error: lo register required -- `lsl r0,r8,#12' +[^:]*:63: Error: lo register required -- `lsl r8,r0' +[^:]*:63: Error: lo register required -- `lsl r0,r8' +[^:]*:64: Error: lo register required -- `lsr r8,r0,#12' +[^:]*:64: Error: lo register required -- `lsr r0,r8,#12' +[^:]*:64: Error: lo register required -- `lsr r8,r0' +[^:]*:64: Error: lo register required -- `lsr r0,r8' +[^:]*:65: Error: lo register required -- `ror r8,r0,#12' +[^:]*:65: Error: lo register required -- `ror r0,r8,#12' +[^:]*:65: Error: lo register required -- `ror r8,r0' +[^:]*:65: Error: lo register required -- `ror r0,r8' +[^:]*:66: Error: ror #imm not supported -- `ror r0,r1,#12' +[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl#2' +[^:]*:70: Error: unshifted register required -- `add r0,r1,lsl r3' +[^:]*:71: Error: lo register required -- `add r8,r0,#1' +[^:]*:72: Error: lo register required -- `add r0,r8,#1' +[^:]*:73: Error: lo register required -- `add r8,#10' +[^:]*:74: Error: dest must overlap one source register -- `add r8,r1,r2' +[^:]*:75: Error: dest must overlap one source register -- `add r1,r8,r2' +[^:]*:76: Error: dest must overlap one source register -- `add r1,r2,r8' +[^:]*:77: Error: lo register required -- `add r8,pc,#4' +[^:]*:78: Error: lo register required -- `add r8,sp,#4' +[^:]*:80: Error: lo register required -- `sub r8,r0' +[^:]*:80: Error: lo register required -- `sub r0,r8' +[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl#2' +[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl r3' +[^:]*:81: Error: lo register required -- `sub r8,r0,#1' +[^:]*:82: Error: lo register required -- `sub r0,r8,#1' +[^:]*:83: Error: lo register required -- `sub r8,#10' +[^:]*:84: Error: lo register required -- `sub r8,r1,r2' +[^:]*:85: Error: lo register required -- `sub r1,r8,r2' +[^:]*:86: Error: lo register required -- `sub r1,r2,r8' +[^:]*:88: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `cmp r0,r1,lsl#2' +[^:]*:89: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `cmp r0,r1,lsl r3' +[^:]*:90: Error: only lo regs allowed with immediate -- `cmp r8,#255' +[^:]*:92: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl#2' +[^:]*:93: Error: shifts in CMP/MOV instructions are only supported in unified syntax -- `mov r0,r1,lsl r3' +[^:]*:94: Error: only lo regs allowed with immediate -- `mov r8,#255' +[^:]*:106: Error: lo register required -- `ldr r8,\[r0\]' +[^:]*:106: Error: lo register required -- `ldr r0,\[r8\]' +[^:]*:106: Error: lo register required -- `ldr r0,\[r0,r8\]' +[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!' +[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4' +[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]' +[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2' +[^:]*:107: Error: lo register required -- `ldrb r8,\[r0\]' +[^:]*:107: Error: lo register required -- `ldrb r0,\[r8\]' +[^:]*:107: Error: lo register required -- `ldrb r0,\[r0,r8\]' +[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!' +[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4' +[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]' +[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2' +[^:]*:108: Error: lo register required -- `ldrh r8,\[r0\]' +[^:]*:108: Error: lo register required -- `ldrh r0,\[r8\]' +[^:]*:108: Error: lo register required -- `ldrh r0,\[r0,r8\]' +[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!' +[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4' +[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,-r2\]' +[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],r2' +[^:]*:109: Error: lo register required -- `ldrsb r8,\[r0\]' +[^:]*:109: Error: lo register required -- `ldrsb r0,\[r8\]' +[^:]*:109: Error: lo register required -- `ldrsb r0,\[r0,r8\]' +[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!' +[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4' +[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]' +[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2' +[^:]*:110: Error: lo register required -- `ldrsh r8,\[r0\]' +[^:]*:110: Error: lo register required -- `ldrsh r0,\[r8\]' +[^:]*:110: Error: lo register required -- `ldrsh r0,\[r0,r8\]' +[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,#4\]!' +[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],#4' +[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,-r2\]' +[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],r2' +[^:]*:111: Error: lo register required -- `str r8,\[r0\]' +[^:]*:111: Error: lo register required -- `str r0,\[r8\]' +[^:]*:111: Error: lo register required -- `str r0,\[r0,r8\]' +[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,#4\]!' +[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],#4' +[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,-r2\]' +[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],r2' +[^:]*:112: Error: lo register required -- `strb r8,\[r0\]' +[^:]*:112: Error: lo register required -- `strb r0,\[r8\]' +[^:]*:112: Error: lo register required -- `strb r0,\[r0,r8\]' +[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,#4\]!' +[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],#4' +[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,-r2\]' +[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],r2' +[^:]*:113: Error: lo register required -- `strh r8,\[r0\]' +[^:]*:113: Error: lo register required -- `strh r0,\[r8\]' +[^:]*:113: Error: lo register required -- `strh r0,\[r0,r8\]' +[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,#4\]!' +[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],#4' +[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,-r2\]' +[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2' +[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl#1\]' +[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl#1\]' +[^:]*:119: Error: lo register required -- `ldmia r8!,{r1,r2}' +[^:]*:120: Error: lo register required -- `ldmia r7!,{r8}' +[^:]*:121: Warning: this instruction will write back the base register +[^:]*:122: Warning: this instruction will not write back the base register +[^:]*:124: Error: lo register required -- `stmia r8!,{r1,r2}' +[^:]*:125: Error: lo register required -- `stmia r7!,{r8}' +[^:]*:126: Warning: this instruction will write back the base register +[^:]*:127: Warning: value stored for r7 is UNKNOWN +[^:]*:129: Error: invalid register list to push/pop instruction -- `push {r8,r9}' +[^:]*:130: Error: invalid register list to push/pop instruction -- `pop {r8,r9}' +[^:]*:133: Error: immediate value out of range -- `bkpt #257' +[^:]*:134: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie ai,#5' +[^:]*:135: Error: Thumb does not support the 2-argument form of this instruction -- `cpsid ai,#5' +[^:]*:138: Error: Thumb does not support conditional execution +[^:]*:141: Error: cannot honor width suffix -- `add r0,r1' +[^:]*:145: Error: lo register required -- `mul r0,r0,r8' +[^:]*:146: Error: lo register required -- `mul r0,r8,r0' +[^:]*:147: Error: dest must overlap one source register -- `mul r8,r0,r0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/t16-bad.s b/binutils-2.25/gas/testsuite/gas/arm/t16-bad.s new file mode 100644 index 00000000..9d2ced3c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/t16-bad.s @@ -0,0 +1,147 @@ + @ Things you can't do with 16-bit Thumb instructions, but you can + @ do with the equivalent ARM instruction. Does not include errors + @ caught by fixup processing (e.g. out-of-range immediates). + + .text + .code 16 + .thumb_func +l: + @ Arithmetic instruction templates + .macro ar2 opc + \opc r8,r0 + \opc r0,r8 + .endm + .macro ar2sh opc + ar2 \opc + \opc r0,#12 + \opc r0,r1,lsl #2 + \opc r0,r1,lsl r3 + .endm + .macro ar2r opc + ar2 \opc + \opc r0,r1,ror #8 + .endm + .macro ar3 opc + \opc r1,r2,r3 + \opc r8,r0 + \opc r0,r8 + .endm + .macro ar3sh opc + ar3 \opc + \opc r0,#12 + \opc r0,r1,lsl #2 + \opc r0,r1,lsl r3 + .endm + + ar2sh tst + ar2sh cmn + ar2sh mvn + ar2 neg + ar2 rev + ar2 rev16 + ar2 revsh + ar2r sxtb + ar2r sxth + ar2r uxtb + ar2r uxth + + ar3sh adc + ar3sh and + ar3sh bic + ar3sh eor + ar3sh orr + ar3sh sbc + ar3 mul + + @ Shift instruction template + .macro shift opc + \opc r8,r0,#12 @ form 1 + \opc r0,r8,#12 + ar2 \opc @ form 2 + .endm + shift asr + shift lsl + shift lsr + shift ror + ror r0,r1,#12 + + @ add/sub/mov/cmp are idiosyncratic + add r0,r1,lsl #2 + add r0,r1,lsl r3 + add r8,r0,#1 @ form 1 + add r0,r8,#1 + add r8,#10 @ form 2 + add r8,r1,r2 @ form 3 + add r1,r8,r2 + add r1,r2,r8 + add r8,pc,#4 @ form 5 + add r8,sp,#4 @ form 6 + + ar3sh sub + sub r8,r0,#1 @ form 1 + sub r0,r8,#1 + sub r8,#10 @ form 2 + sub r8,r1,r2 @ form 3 + sub r1,r8,r2 + sub r1,r2,r8 + + cmp r0,r1,lsl #2 + cmp r0,r1,lsl r3 + cmp r8,#255 + + mov r0,r1,lsl #2 + mov r0,r1,lsl r3 + mov r8,#255 + + @ Load/store template + .macro ldst opc + \opc r8,[r0] + \opc r0,[r8] + \opc r0,[r0,r8] + \opc r0,[r1,#4]! + \opc r0,[r1],#4 + \opc r0,[r1,-r2] + \opc r0,[r1],r2 + .endm + ldst ldr + ldst ldrb + ldst ldrh + ldst ldrsb + ldst ldrsh + ldst str + ldst strb + ldst strh + + ldr r0,[r1,r2,lsl #1] + str r0,[r1,r2,lsl #1] + + @ Load/store multiple + ldmia r8!,{r1,r2} + ldmia r7!,{r8} + ldmia r7,{r1,r2} + ldmia r7!,{r1,r7} + + stmia r8!,{r1,r2} + stmia r7!,{r8} + stmia r7,{r1,r2} + stmia r7!,{r1,r7} + + push {r8,r9} + pop {r8,r9} + + @ Miscellaneous + bkpt #257 + cpsie ai,#5 + cpsid ai,#5 + + @ Conditional suffixes + addeq r0,r1,r2 + @ low register non flag setting add. + .syntax unified + add r0, r1 + + @ Multiply + .syntax divided + mul r0, r0, r8 + mul r0, r8, r0 + mul r8, r0, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/t2-branch-global.d b/binutils-2.25/gas/testsuite/gas/arm/t2-branch-global.d new file mode 100644 index 00000000..5850d6b6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/t2-branch-global.d @@ -0,0 +1,14 @@ +#name: Thumb-2 branch to constant address +#This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#objdump: -rd + + +.*: +file format.*arm.* + + +Disassembly of section .text: + +00000000 <foo>: + 0: f... b... b\.w .* + 0: R_ARM_THM_JUMP24 \*ABS\*.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/t2-branch-global.s b/binutils-2.25/gas/testsuite/gas/arm/t2-branch-global.s new file mode 100644 index 00000000..223d924d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/t2-branch-global.s @@ -0,0 +1,5 @@ +.thumb +.arch armv7 +.syntax unified +foo: + b 0x10 @ Assembler must not relax this diff --git a/binutils-2.25/gas/testsuite/gas/arm/target-reloc-1.d b/binutils-2.25/gas/testsuite/gas/arm/target-reloc-1.d new file mode 100644 index 00000000..7a33b712 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/target-reloc-1.d @@ -0,0 +1,15 @@ +#objdump: -dr --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#name: TARGET reloc + +.*: file format .*arm.* + +Disassembly of section .text: + +00000000 <foo>: + 0: 00001234 .* + 0: R_ARM_TARGET2 foo + 4: cdef0000 .* + 4: R_ARM_TARGET2 foo + 8: 76543210 .* + 8: R_ARM_TARGET2 foo diff --git a/binutils-2.25/gas/testsuite/gas/arm/target-reloc-1.s b/binutils-2.25/gas/testsuite/gas/arm/target-reloc-1.s new file mode 100644 index 00000000..b543ab3a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/target-reloc-1.s @@ -0,0 +1,3 @@ +foo: .word foo(TARGET2) + 0x1234 + .word foo + 0xcdef0000(TARGET2) + .word (foo + 0x76543210)(TARGET2) diff --git a/binutils-2.25/gas/testsuite/gas/arm/tcompat.d b/binutils-2.25/gas/testsuite/gas/arm/tcompat.d new file mode 100644 index 00000000..6e378bfb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tcompat.d @@ -0,0 +1,54 @@ +#name: ARM Thumb-compat pseudos +#objdump: -dr --prefix-addresses --show-raw-insn +#as: + +# Test the ARM pseudo instructions that exist for Thumb source compatibility + +.*: +file format .*arm.* + +Disassembly of section .text: + +0+00 <[^>]*> 91a00000 ? movls r0, r0 +0+04 <[^>]*> e1a09000 ? mov r9, r0 +0+08 <[^>]*> e1a00009 ? mov r0, r9 +0+0c <[^>]*> e1a0c00e ? mov ip, lr +0+10 <[^>]*> 91b09019 ? lslsls r9, r9, r0 +0+14 <[^>]*> 91a00910 ? lslls r0, r0, r9 +0+18 <[^>]*> e1b00880 ? lsls r0, r0, #17 +0+1c <[^>]*> e1a00889 ? lsl r0, r9, #17 +0+20 <[^>]*> 91b09039 ? lsrsls r9, r9, r0 +0+24 <[^>]*> 91a00930 ? lsrls r0, r0, r9 +0+28 <[^>]*> e1b008a0 ? lsrs r0, r0, #17 +0+2c <[^>]*> e1a008a9 ? lsr r0, r9, #17 +0+30 <[^>]*> 91b09059 ? asrsls r9, r9, r0 +0+34 <[^>]*> 91a00950 ? asrls r0, r0, r9 +0+38 <[^>]*> e1b008c0 ? asrs r0, r0, #17 +0+3c <[^>]*> e1a008c9 ? asr r0, r9, #17 +0+40 <[^>]*> 91b09079 ? rorsls r9, r9, r0 +0+44 <[^>]*> 91a00970 ? rorls r0, r0, r9 +0+48 <[^>]*> e1b008e0 ? rors r0, r0, #17 +0+4c <[^>]*> e1a008e9 ? ror r0, r9, #17 +0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 +0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 +0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 +0+5c <[^>]*> 92799000 ? rsbsls r9, r9, #0 +0+60 <[^>]*> e92d000e ? push {r1, r2, r3} +0+64 <[^>]*> 992d8154 ? pushls {r2, r4, r6, r8, pc} +0+68 <[^>]*> e8bd000e ? pop {r1, r2, r3} +0+6c <[^>]*> 98bd8154 ? popls {r2, r4, r6, r8, pc} +0+70 <[^>]*> e0000001 ? and r0, r0, r1 +0+74 <[^>]*> e0200001 ? eor r0, r0, r1 +0+78 <[^>]*> e0400001 ? sub r0, r0, r1 +0+7c <[^>]*> e0600001 ? rsb r0, r0, r1 +0+80 <[^>]*> e0800001 ? add r0, r0, r1 +0+84 <[^>]*> e0a00001 ? adc r0, r0, r1 +0+88 <[^>]*> e0c00001 ? sbc r0, r0, r1 +0+8c <[^>]*> e0e00001 ? rsc r0, r0, r1 +0+90 <[^>]*> e1800001 ? orr r0, r0, r1 +0+94 <[^>]*> e1c00001 ? bic r0, r0, r1 +0+98 <[^>]*> e0000091 ? mul r0, r1, r0 +0+9c <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+a0 <[^>]*> e1a00069 ? rrx r0, r9 +0+a4 <[^>]*> e1b09060 ? rrxs r9, r0 +0+a8 <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) +0+ac <[^>]*> e1a00000 ? nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/tcompat.s b/binutils-2.25/gas/testsuite/gas/arm/tcompat.s new file mode 100644 index 00000000..98b93031 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tcompat.s @@ -0,0 +1,50 @@ + @ ARM instructions defined for source compatibility with Thumb. + .macro shift op opls ops oplss + \oplss r9,r0 + \opls r0,r0,r9 + \ops r0,#17 + \op r0,r9,#17 + .endm + .text + .global l +l: + cpyls r0,r0 + cpy r9,r0 + cpy r0,r9 + cpy ip,lr + + shift lsl lslls lsls lsllss + shift lsr lsrls lsrs lsrlss + shift asr asrls asrs asrlss + shift ror rorls rors rorlss + + neg r0,r9 + negs r9,r0 + negls r0,r0 + neglss r9,r9 + + push {r1,r2,r3} + pushls {r2,r4,r6,r8,pc} + pop {r1,r2,r3} + popls {r2,r4,r6,r8,pc} + + @ Two-argument forms of ARM arithmetic instructions. + and r0,r1 + eor r0,r1 + sub r0,r1 + rsb r0,r1 + + add r0,r1 + adc r0,r1 + sbc r0,r1 + rsc r0,r1 + + orr r0,r1 + bic r0,r1 + mul r0,r1 + nop + + rrx r0,r9 + rrxs r9,r0 + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/tcompat2.d b/binutils-2.25/gas/testsuite/gas/arm/tcompat2.d new file mode 100644 index 00000000..4c6de616 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tcompat2.d @@ -0,0 +1,26 @@ +#name: Thumb ARM-compat pseudos +#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb +#as: + +# Test the Thumb pseudo instructions that exist for ARM source compatibility + +.*: +file format .*arm.* + +Disassembly of section .text: + +0+00 <[^>]*> 4148 * adcs r0, r1 +0+02 <[^>]*> 4148 * adcs r0, r1 +0+04 <[^>]*> 4008 * ands r0, r1 +0+06 <[^>]*> 4008 * ands r0, r1 +0+08 <[^>]*> 4048 * eors r0, r1 +0+0a <[^>]*> 4048 * eors r0, r1 +0+0c <[^>]*> 4348 * muls r0, r1 +0+0e <[^>]*> 4348 * muls r0, r1 +0+10 <[^>]*> 4308 * orrs r0, r1 +0+12 <[^>]*> 4308 * orrs r0, r1 +0+14 <[^>]*> 4388 * bics r0, r1 +0+16 <[^>]*> 4188 * sbcs r0, r1 +0+18 <[^>]*> 46c0 * nop ; \(mov r8, r8\) +0+1a <[^>]*> 46c0 * nop ; \(mov r8, r8\) +0+1c <[^>]*> 46c0 * nop ; \(mov r8, r8\) +0+1e <[^>]*> 46c0 * nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/tcompat2.s b/binutils-2.25/gas/testsuite/gas/arm/tcompat2.s new file mode 100644 index 00000000..b034ce2f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tcompat2.s @@ -0,0 +1,32 @@ + @ Three-argument forms of Thumb arithmetic instructions. + @ Commutative instructions allow either the second or third + @ operand to equal the first. + + .text + .global m + .thumb_func +m: + adc r0,r0,r1 + adc r0,r1,r0 + + and r0,r0,r1 + and r0,r1,r0 + + eor r0,r0,r1 + eor r0,r1,r0 + + mul r0,r0,r1 + mul r0,r1,r0 + + orr r0,r0,r1 + orr r0,r1,r0 + + bic r0,r0,r1 + + sbc r0,r0,r1 + + @ section padding for a.out's sake + nop + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.d b/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.d new file mode 100644 index 00000000..958773db --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.d @@ -0,0 +1,4 @@ +#name: Out of range Thumb branches (PR 12848) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#as: -mthumb +#error-output: thumb-b-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.l b/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.l new file mode 100644 index 00000000..0c76b4d4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.l @@ -0,0 +1,6 @@ +[^:]*: Assembler messages: +[^:]*:9: Error: branch out of range +[^:]*:5: Error: branch out of range +[^:]*:8: Error: branch out of range +[^:]*:11: Error: branch out of range +[^:]*:15: Error: branch out of range diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.s b/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.s new file mode 100644 index 00000000..7306b790 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-b-bad.s @@ -0,0 +1,17 @@ +.syntax unified + +.type f, %function +e: + b . - 0xfffffe @ gas mis-assembles as a forward branch + b . - 0xfffffc + b . + 0x1000002 + b . + 0x1000004 @ gas mis-assembles as a backward branch + b.w . + 0x2000002 @ gas mis-assembles as a backward branch + +f: b g @ gas mis-assembles as a backward branch + + .space 0x1fffff0 + +g: b f @ gas mis-assembles as a forward branch + + diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-eabi.d b/binutils-2.25/gas/testsuite/gas/arm/thumb-eabi.d new file mode 100644 index 00000000..19fc7972 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-eabi.d @@ -0,0 +1,165 @@ +# name: Thumb instructions (EABI) +# as: -mcpu=arm7t +# objdump: -dr --prefix-addresses --show-raw-insn +# source: thumb.s +# target: *-*-*eabi* *-*-symbianelf *-*-nacl* + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+000 <[^>]+> 00ca lsls r2, r1, #3 +0+002 <[^>]+> 0fe3 lsrs r3, r4, #31 +0+004 <[^>]+> 1147 asrs r7, r0, #5 +0+006 <[^>]+> 0011 movs r1, r2 +0+008 <[^>]+> 0023 movs r3, r4 +0+00a <[^>]+> 002c movs r4, r5 +0+00c <[^>]+> 083e lsrs r6, r7, #32 +0+00e <[^>]+> 1008 asrs r0, r1, #32 +0+010 <[^>]+> 18d1 adds r1, r2, r3 +0+012 <[^>]+> 1ca2 adds r2, r4, #2 +0+014 <[^>]+> 1beb subs r3, r5, r7 +0+016 <[^>]+> 1fe2 subs r2, r4, #7 +0+018 <[^>]+> 24ff movs r4, #255.* +0+01a <[^>]+> 2bfa cmp r3, #250.* +0+01c <[^>]+> 367b adds r6, #123.* +0+01e <[^>]+> 3d80 subs r5, #128.* +0+020 <[^>]+> 402b ands r3, r5 +0+022 <[^>]+> 4074 eors r4, r6 +0+024 <[^>]+> 4081 lsls r1, r0 +0+026 <[^>]+> 40da lsrs r2, r3 +0+028 <[^>]+> 4134 asrs r4, r6 +0+02a <[^>]+> 417d adcs r5, r7 +0+02c <[^>]+> 41a0 sbcs r0, r4 +0+02e <[^>]+> 41e1 rors r1, r4 +0+030 <[^>]+> 422a tst r2, r5 +0+032 <[^>]+> 4249 negs r1, r1 +0+034 <[^>]+> 429a cmp r2, r3 +0+036 <[^>]+> 42e1 cmn r1, r4 +0+038 <[^>]+> 4318 orrs r0, r3 +0+03a <[^>]+> 436c muls r4, r5 +0+03c <[^>]+> 43bd bics r5, r7 +0+03e <[^>]+> 43ed mvns r5, r5 +0+040 <[^>]+> 4469 add r1, sp +0+042 <[^>]+> 4494 add ip, r2 +0+044 <[^>]+> 44c9 add r9, r9 +0+046 <[^>]+> 4571 cmp r1, lr +0+048 <[^>]+> 4580 cmp r8, r0 +0+04a <[^>]+> 45f4 cmp ip, lr +0+04c <[^>]+> 4648 mov r0, r9 +0+04e <[^>]+> 46a1 mov r9, r4 +0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+052 <[^>]+> 4738 bx r7 +0+054 <[^>]+> 4740 bx r8 +0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+058 <[^>]+> 4778 bx pc +0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\) +0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\) +0+05e <[^>]+> 5088 str r0, \[r1, r2\] +0+060 <[^>]+> 5511 strb r1, \[r2, r4\] +0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] +0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] +0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] +0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] +0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] +0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\] +0+070 <[^>]+> 67db str r3, \[r3, #124\].* +0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\].* +0+074 <[^>]+> 682d ldr r5, \[r5, #0\] +0+076 <[^>]+> 77e9 strb r1, \[r5, #31\] +0+078 <[^>]+> 7161 strb r1, \[r4, #5\] +0+07a <[^>]+> 7032 strb r2, \[r6, #0\] +0+07c <[^>]+> 87ec strh r4, \[r5, #62\].* +0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\] +0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\] +0+082 <[^>]+> 93ff str r3, \[sp, #1020\].* +0+084 <[^>]+> 990b ldr r1, \[sp, #44\].* +0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] +0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\) +0+08a <[^>]+> ac80 add r4, sp, #512.* +0+08c <[^>]+> b043 add sp, #268.* +0+08e <[^>]+> b09a sub sp, #104.* +0+090 <[^>]+> b0c3 sub sp, #268.* +0+092 <[^>]+> b01b add sp, #108.* +0+094 <[^>]+> b417 push {r0, r1, r2, r4} +0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr} +0+098 <[^>]+> bc98 pop {r3, r4, r7} +0+09a <[^>]+> bdff pop {r0, r1, r2, r3, r4, r5, r6, r7, pc} +0+09c <[^>]+> c3f3 stmia r3!, {r0, r1, r4, r5, r6, r7} +0+09e <[^>]+> c8fe ldmia r0!, {r1, r2, r3, r4, r5, r6, r7} +0+0a0 <[^>]+> d0e2 beq.n 0+068 <[^>]+> +0+0a2 <[^>]+> d1e1 bne.n 0+068 <[^>]+> +0+0a4 <[^>]+> d2e0 bcs.n 0+068 <[^>]+> +0+0a6 <[^>]+> d3df bcc.n 0+068 <[^>]+> +0+0a8 <[^>]+> d4de bmi.n 0+068 <[^>]+> +0+0aa <[^>]+> d5dd bpl.n 0+068 <[^>]+> +0+0ac <[^>]+> d6dc bvs.n 0+068 <[^>]+> +0+0ae <[^>]+> d7db bvc.n 0+068 <[^>]+> +0+0b0 <[^>]+> d8da bhi.n 0+068 <[^>]+> +0+0b2 <[^>]+> d9d9 bls.n 0+068 <[^>]+> +0+0b4 <[^>]+> dad8 bge.n 0+068 <[^>]+> +0+0b6 <[^>]+> dcd7 bgt.n 0+068 <[^>]+> +0+0b8 <[^>]+> dbd6 blt.n 0+068 <[^>]+> +0+0ba <[^>]+> dcd5 bgt.n 0+068 <[^>]+> +0+0bc <[^>]+> ddd4 ble.n 0+068 <[^>]+> +0+0be <[^>]+> d8d3 bhi.n 0+068 <[^>]+> +0+0c0 <[^>]+> d3d2 bcc.n 0+068 <[^>]+> +0+0c2 <[^>]+> d3d1 bcc.n 0+068 <[^>]+> +0+0c4 <[^>]+> e7d0 b.n 0+068 <[^>]+> +0+0c6 <[^>]+> 00ac lsls r4, r5, #2 +0+0c8 <[^>]+> 1c9a adds r2, r3, #2 +0+0ca <[^>]+> b07f add sp, #508.* +0+0cc <[^>]+> b0ff sub sp, #508.* +0+0ce <[^>]+> a8ff add r0, sp, #1020.* +0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\) +0+0d2 <[^>]+> b01a add sp, #104.* +0+0d4 <[^>]+> b09a sub sp, #104.* +0+0d6 <[^>]+> a81a add r0, sp, #104.* +0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\) +0+0da <[^>]+> 3168 adds r1, #104.* +0+0dc <[^>]+> 2668 movs r6, #104.* +0+0de <[^>]+> 2f68 cmp r7, #104.* +0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+> +0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+> +0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+> +0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+> +0+0f4 <[^>]+> e12fff10 bx r0 +.*: R_ARM_V4BX.* +0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 +0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\) +0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> +0+100 <[^>]+> e018 b.n 0+134 <[^>]+> +0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> +0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> +0+10a <[^>]+> 4700 bx r0 +0+10c <[^>]+> dfff (swi|svc) 255.* +0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> +0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> +0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> +0+116 <[^>]+> d30d bcc.n 0+134 <[^>]+> +0+118 <[^>]+> d40c bmi.n 0+134 <[^>]+> +0+11a <[^>]+> d50b bpl.n 0+134 <[^>]+> +0+11c <[^>]+> d60a bvs.n 0+134 <[^>]+> +0+11e <[^>]+> d709 bvc.n 0+134 <[^>]+> +0+120 <[^>]+> d808 bhi.n 0+134 <[^>]+> +0+122 <[^>]+> d907 bls.n 0+134 <[^>]+> +0+124 <[^>]+> da06 bge.n 0+134 <[^>]+> +0+126 <[^>]+> dc05 bgt.n 0+134 <[^>]+> +0+128 <[^>]+> db04 blt.n 0+134 <[^>]+> +0+12a <[^>]+> dc03 bgt.n 0+134 <[^>]+> +0+12c <[^>]+> dd02 ble.n 0+134 <[^>]+> +0+12e <[^>]+> d801 bhi.n 0+134 <[^>]+> +0+130 <[^>]+> d300 bcc.n 0+134 <[^>]+> +0+132 <[^>]+> d3ff bcc.n 0+134 <[^>]+> +0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+> + \.\.\. +0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+> +0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+944 <[^>]+> 1c08 adds r0, r1, #0 +0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-nop.d b/binutils-2.25/gas/testsuite/gas/arm/thumb-nop.d new file mode 100644 index 00000000..648ed986 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-nop.d @@ -0,0 +1,11 @@ +# name: Thumb NOP +# objdump: -dr --prefix-addresses --show-raw-insn +# +# Both explicit nop and padding should not use Thumb-2 NOP for the +# default CPU. + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+000 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+002 <[^>]+> 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-nop.s b/binutils-2.25/gas/testsuite/gas/arm/thumb-nop.s new file mode 100644 index 00000000..12dd5bb4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-nop.s @@ -0,0 +1,6 @@ + .text + .code 16 + .p2align 2 + .syntax unified +.foo: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.d b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.d new file mode 100644 index 00000000..7b3b2c0a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.d @@ -0,0 +1,3 @@ +#name: Wide instruction rejected in non-Thumb2 cores. +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: thumb-w-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.l b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.l new file mode 100644 index 00000000..342b5e71 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: selected processor does not support Thumb-2 mode `mov.w r1,r2' +[^:]*:5: Error: selected processor does not support Thumb mode `mrs.w r0,apsr' diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.s b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.s new file mode 100644 index 00000000..c41f7934 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-bad.s @@ -0,0 +1,6 @@ +.syntax unified +.arch armv4t +.thumb +mov.w r1, r2 +mrs.w r0, apsr + diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-w-good.d b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-good.d new file mode 100644 index 00000000..da25e644 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-good.d @@ -0,0 +1,13 @@ +#name: Wide instruction acceptance in Thumb-2 cores +#objdump: -d --prefix-addresses --show-raw-insn +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +00000000 <.text> f7ff fffe bl 00000000 <foo> +00000004 <.text\+0x4> f3ef 8000 mrs r0, CPSR +00000008 <.text\+0x8> f84d 0d04 (str(\.w)? r0, \[sp, #-4\]!|push(\.w)? \{r0\}) +0000000c <.text\+0xc> e92d 4001 (stmdb(\.w)? sp!,|push(\.w)?)[ ]+\{r0, lr\} +00000010 <.text\+0x10> f85d 0b04 (ldr(\.w)? r0, \[sp\], #4|pop(\.w)? \{r0\}) +00000014 <.text\+0x14> e8bd 8001 (ldmia(\.w)? sp!,|pop(\.w)?)[ ]+\{r0, pc\} diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb-w-good.s b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-good.s new file mode 100644 index 00000000..feebef13 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb-w-good.s @@ -0,0 +1,12 @@ +.thumb +.syntax unified +.arch armv4t +bl.w foo +.arch armv6-m +mrs.w r0, apsr + +.arch armv6t2 +push.w {r0} +push.w {r0, lr} +pop.w {r0} +pop.w {r0, pc} diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb.d b/binutils-2.25/gas/testsuite/gas/arm/thumb.d new file mode 100644 index 00000000..c928aaff --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb.d @@ -0,0 +1,165 @@ +# name: Thumb instructions +# as: -mcpu=arm7t +# objdump: -dr --prefix-addresses --show-raw-insn +# The arm-aout and arm-pe ports do not support Thumb branch relocations. +# EABI targets have their own variant. +# not-target: *-*-*aout* *-*-pe *-*-*eabi* *-*-symbianelf *-*-nacl* + +.*: +file format .*arm.* + +Disassembly of section \.text: +0+000 <[^>]+> 00ca lsls r2, r1, #3 +0+002 <[^>]+> 0fe3 lsrs r3, r4, #31 +0+004 <[^>]+> 1147 asrs r7, r0, #5 +0+006 <[^>]+> 0011 movs r1, r2 +0+008 <[^>]+> 0023 movs r3, r4 +0+00a <[^>]+> 002c movs r4, r5 +0+00c <[^>]+> 083e lsrs r6, r7, #32 +0+00e <[^>]+> 1008 asrs r0, r1, #32 +0+010 <[^>]+> 18d1 adds r1, r2, r3 +0+012 <[^>]+> 1ca2 adds r2, r4, #2 +0+014 <[^>]+> 1beb subs r3, r5, r7 +0+016 <[^>]+> 1fe2 subs r2, r4, #7 +0+018 <[^>]+> 24ff movs r4, #255.* +0+01a <[^>]+> 2bfa cmp r3, #250.* +0+01c <[^>]+> 367b adds r6, #123.* +0+01e <[^>]+> 3d80 subs r5, #128.* +0+020 <[^>]+> 402b ands r3, r5 +0+022 <[^>]+> 4074 eors r4, r6 +0+024 <[^>]+> 4081 lsls r1, r0 +0+026 <[^>]+> 40da lsrs r2, r3 +0+028 <[^>]+> 4134 asrs r4, r6 +0+02a <[^>]+> 417d adcs r5, r7 +0+02c <[^>]+> 41a0 sbcs r0, r4 +0+02e <[^>]+> 41e1 rors r1, r4 +0+030 <[^>]+> 422a tst r2, r5 +0+032 <[^>]+> 4249 negs r1, r1 +0+034 <[^>]+> 429a cmp r2, r3 +0+036 <[^>]+> 42e1 cmn r1, r4 +0+038 <[^>]+> 4318 orrs r0, r3 +0+03a <[^>]+> 436c muls r4, r5 +0+03c <[^>]+> 43bd bics r5, r7 +0+03e <[^>]+> 43ed mvns r5, r5 +0+040 <[^>]+> 4469 add r1, sp +0+042 <[^>]+> 4494 add ip, r2 +0+044 <[^>]+> 44c9 add r9, r9 +0+046 <[^>]+> 4571 cmp r1, lr +0+048 <[^>]+> 4580 cmp r8, r0 +0+04a <[^>]+> 45f4 cmp ip, lr +0+04c <[^>]+> 4648 mov r0, r9 +0+04e <[^>]+> 46a1 mov r9, r4 +0+050 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+052 <[^>]+> 4738 bx r7 +0+054 <[^>]+> 4740 bx r8 +0+056 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+058 <[^>]+> 4778 bx pc +0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] ; \(0+0dc <[^>]+>\) +0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] ; \(0+068 <[^>]+>\) +0+05e <[^>]+> 5088 str r0, \[r1, r2\] +0+060 <[^>]+> 5511 strb r1, \[r2, r4\] +0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] +0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] +0+066 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] +0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] +0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] +0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\] +0+070 <[^>]+> 67db str r3, \[r3, #124\].* +0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\].* +0+074 <[^>]+> 682d ldr r5, \[r5, #0\] +0+076 <[^>]+> 77e9 strb r1, \[r5, #31\] +0+078 <[^>]+> 7161 strb r1, \[r4, #5\] +0+07a <[^>]+> 7032 strb r2, \[r6, #0\] +0+07c <[^>]+> 87ec strh r4, \[r5, #62\].* +0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\] +0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\] +0+082 <[^>]+> 93ff str r3, \[sp, #1020\].* +0+084 <[^>]+> 990b ldr r1, \[sp, #44\].* +0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] +0+088 <[^>]+> a7ff add r7, pc, #1020 ; \(adr r7, 0+488 <[^>]+>\) +0+08a <[^>]+> ac80 add r4, sp, #512.* +0+08c <[^>]+> b043 add sp, #268.* +0+08e <[^>]+> b09a sub sp, #104.* +0+090 <[^>]+> b0c3 sub sp, #268.* +0+092 <[^>]+> b01b add sp, #108.* +0+094 <[^>]+> b417 push {r0, r1, r2, r4} +0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr} +0+098 <[^>]+> bc98 pop {r3, r4, r7} +0+09a <[^>]+> bdff pop {r0, r1, r2, r3, r4, r5, r6, r7, pc} +0+09c <[^>]+> c3f3 stmia r3!, {r0, r1, r4, r5, r6, r7} +0+09e <[^>]+> c8fe ldmia r0!, {r1, r2, r3, r4, r5, r6, r7} +0+0a0 <[^>]+> d0e2 beq.n 0+068 <[^>]+> +0+0a2 <[^>]+> d1e1 bne.n 0+068 <[^>]+> +0+0a4 <[^>]+> d2e0 bcs.n 0+068 <[^>]+> +0+0a6 <[^>]+> d3df bcc.n 0+068 <[^>]+> +0+0a8 <[^>]+> d4de bmi.n 0+068 <[^>]+> +0+0aa <[^>]+> d5dd bpl.n 0+068 <[^>]+> +0+0ac <[^>]+> d6dc bvs.n 0+068 <[^>]+> +0+0ae <[^>]+> d7db bvc.n 0+068 <[^>]+> +0+0b0 <[^>]+> d8da bhi.n 0+068 <[^>]+> +0+0b2 <[^>]+> d9d9 bls.n 0+068 <[^>]+> +0+0b4 <[^>]+> dad8 bge.n 0+068 <[^>]+> +0+0b6 <[^>]+> dcd7 bgt.n 0+068 <[^>]+> +0+0b8 <[^>]+> dbd6 blt.n 0+068 <[^>]+> +0+0ba <[^>]+> dcd5 bgt.n 0+068 <[^>]+> +0+0bc <[^>]+> ddd4 ble.n 0+068 <[^>]+> +0+0be <[^>]+> d8d3 bhi.n 0+068 <[^>]+> +0+0c0 <[^>]+> d3d2 bcc.n 0+068 <[^>]+> +0+0c2 <[^>]+> d3d1 bcc.n 0+068 <[^>]+> +0+0c4 <[^>]+> e7d0 b.n 0+068 <[^>]+> +0+0c6 <[^>]+> 00ac lsls r4, r5, #2 +0+0c8 <[^>]+> 1c9a adds r2, r3, #2 +0+0ca <[^>]+> b07f add sp, #508.* +0+0cc <[^>]+> b0ff sub sp, #508.* +0+0ce <[^>]+> a8ff add r0, sp, #1020.* +0+0d0 <[^>]+> a0ff add r0, pc, #1020 ; \(adr r0, 0+4d0 <[^>]+>\) +0+0d2 <[^>]+> b01a add sp, #104.* +0+0d4 <[^>]+> b09a sub sp, #104.* +0+0d6 <[^>]+> a81a add r0, sp, #104.* +0+0d8 <[^>]+> a01a add r0, pc, #104 ; \(adr r0, 0+144 <[^>]+>\) +0+0da <[^>]+> 3168 adds r1, #104.* +0+0dc <[^>]+> 2668 movs r6, #104.* +0+0de <[^>]+> 2f68 cmp r7, #104.* +0+0e0 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0e2 <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+> +0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+> +0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+> +0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+> +0+0f4 <[^>]+> e12fff10 bx r0 +0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 +0+0fc <[^>]+> a004 add r0, pc, #16 ; \(adr r0, 0+110 <[^>]+>\) +0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> +0+100 <[^>]+> e018 b.n 0+134 <[^>]+> +0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> +0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> +0+10a <[^>]+> 4700 bx r0 +0+10c <[^>]+> dfff (swi|svc) 255.* +0+10e <[^>]+> 46c0 nop ; \(mov r8, r8\) +0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> +0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> +0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> +0+116 <[^>]+> d30d bcc.n 0+134 <[^>]+> +0+118 <[^>]+> d40c bmi.n 0+134 <[^>]+> +0+11a <[^>]+> d50b bpl.n 0+134 <[^>]+> +0+11c <[^>]+> d60a bvs.n 0+134 <[^>]+> +0+11e <[^>]+> d709 bvc.n 0+134 <[^>]+> +0+120 <[^>]+> d808 bhi.n 0+134 <[^>]+> +0+122 <[^>]+> d907 bls.n 0+134 <[^>]+> +0+124 <[^>]+> da06 bge.n 0+134 <[^>]+> +0+126 <[^>]+> dc05 bgt.n 0+134 <[^>]+> +0+128 <[^>]+> db04 blt.n 0+134 <[^>]+> +0+12a <[^>]+> dc03 bgt.n 0+134 <[^>]+> +0+12c <[^>]+> dd02 ble.n 0+134 <[^>]+> +0+12e <[^>]+> d801 bhi.n 0+134 <[^>]+> +0+130 <[^>]+> d300 bcc.n 0+134 <[^>]+> +0+132 <[^>]+> d3ff bcc.n 0+134 <[^>]+> +0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+> + \.\.\. +0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+> +0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+944 <[^>]+>\) +0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] ; \(0+948 <[^>]+>\) +0+944 <[^>]+> 1c08 adds r0, r1, #0 +0+946 <[^>]+> 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb.s b/binutils-2.25/gas/testsuite/gas/arm/thumb.s new file mode 100644 index 00000000..a044bdfc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb.s @@ -0,0 +1,203 @@ + .text + .code 16 +.foo: + lsl r2, r1, #3 + lsr r3, r4, #31 +wibble/data: + asr r7, r0, #5 + + lsl r1, r2, #0 + lsr r3, r4, #0 + asr r4, r5, #0 + + lsr r6, r7, #32 + asr r0, r1, #32 + + add r1, r2, r3 + add r2, r4, #2 + sub r3, r5, r7 + sub r2, r4, #7 + + mov r4, #255 + cmp r3, #250 + add r6, #123 + sub r5, #128 + + and r3, r5 + eor r4, r6 + lsl r1, r0 + lsr r2, r3 + asr r4, r6 + adc r5, r7 + sbc r0, r4 + ror r1, r4 + tst r2, r5 + neg r1, r1 + cmp r2, r3 + cmn r1, r4 + orr r0, r3 + mul r4, r5 + bic r5, r7 + mvn r5, r5 + + add r1, r13 + add r12, r2 + add r9, r9 + cmp r1, r14 + cmp r8, r0 + cmp r12, r14 + mov r0, r9 + mov r9, r4 + mov r8, r8 + bx r7 + bx r8 + .align 0 + bx pc + + ldr r3, [pc, #128] + ldr r4, bar + + str r0, [r1, r2] + strb r1, [r2, r4] + ldr r5, [r6, r7] + ldrb r2, [r4, r5] + + .align 0 +bar: + strh r1, [r2, r3] + ldrh r3, [r4, r0] + ldsb r1, [r6, r7] + ldsh r2, [r0, r5] + + str r3, [r3, #124] + ldr r1, [r4, #124] + ldr r5, [r5] + strb r1, [r5, #31] + strb r1, [r4, #5] + strb r2, [r6] + + strh r4, [r5, #62] + ldrh r5, [r0, #4] + ldrh r3, [r2] + + str r3, [r13, #1020] + ldr r1, [r13, #44] + ldr r2, [r13] + + add r7, r15, #1020 + add r4, r13, #512 + + add r13, #268 + add r13, #-104 + sub r13, #268 + sub r13, #-108 + + push {r0, r1, r2, r4} + push {r0, r3-r7, lr} + pop {r3, r4, r7} + pop {r0-r7, r15} + + stmia r3!, {r0, r1, r4-r7} + ldmia r0!, {r1-r7} + + beq bar + bne bar + bcs bar + bcc bar + bmi bar + bpl bar + bvs bar + bvc bar + bhi bar + bls bar + bge bar + bgt bar + blt bar + bgt bar + ble bar + bhi bar + blo bar + bul bar + bal bar + +close: + lsl r4, r5, #near - close +near: + add r2, r3, #near - close + + add sp, sp, #127 << 2 + sub sp, sp, #127 << 2 + add r0, sp, #255 << 2 + add r0, pc, #255 << 2 + + add sp, sp, #bar - .foo + sub sp, sp, #bar - .foo + add r0, sp, #bar - .foo + add r0, pc, #bar - .foo + + add r1, #bar - .foo + mov r6, #bar - .foo + cmp r7, #bar - .foo + + nop + nop + + .arm +.localbar: + b .localbar + b .back + bl .localbar + bl .back + + bx r0 + swi 0x123456 + + .thumb + @ The following will be disassembled incorrectly if we do not + @ have a Thumb symbol defined before the first Thumb instruction: +morethumb: + adr r0, forwardonly + + b .foo + b .back + bl .foo + bl .back + + bx r0 + + swi 0xff + .align 0 +forwardonly: + beq .back + bne .back + bcs .back + bcc .back + bmi .back + bpl .back + bvs .back + bvc .back + bhi .back + bls .back + bge .back + bgt .back + blt .back + bgt .back + ble .back + bhi .back + blo .back + bul .back + +.back: + bl .local + .space (1 << 11) @ leave space to force long offsets +.local: + bl .back + + ldr r0, .target + ldr r0, .target + ldr r0, [pc, #4] + ldr r0, [pc, #4] +.target: +baz: + mov r0, r1 + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb1_unified.d b/binutils-2.25/gas/testsuite/gas/arm/thumb1_unified.d new file mode 100644 index 00000000..e34f3978 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb1_unified.d @@ -0,0 +1,20 @@ +# name: Thumb-1 unified +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> 200c movs r0, #12 +0[0-9a-f]+ <[^>]+> 1cd1 adds r1, r2, #3 +0[0-9a-f]+ <[^>]+> 1ed1 subs r1, r2, #3 +0[0-9a-f]+ <[^>]+> 3364 adds r3, #100.* +0[0-9a-f]+ <[^>]+> 3c83 subs r4, #131.* +0[0-9a-f]+ <[^>]+> 2d27 cmp r5, #39.* +0[0-9a-f]+ <[^>]+> a103 add r1, pc, #12 ; \(adr [^)]*\) +0[0-9a-f]+ <[^>]+> 4a03 ldr r2, \[pc, #12\] ; \([^)]*\) +0[0-9a-f]+ <[^>]+> 6863 ldr r3, \[r4, #4\] +0[0-9a-f]+ <[^>]+> 9d01 ldr r5, \[sp, #4\] +0[0-9a-f]+ <[^>]+> b001 add sp, #4 +0[0-9a-f]+ <[^>]+> b081 sub sp, #4 +0[0-9a-f]+ <[^>]+> af01 add r7, sp, #4 +0[0-9a-f]+ <[^>]+> 4251 negs r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb1_unified.s b/binutils-2.25/gas/testsuite/gas/arm/thumb1_unified.s new file mode 100644 index 00000000..c8da6ec5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb1_unified.s @@ -0,0 +1,25 @@ +.text +.arch armv4t +.syntax unified +.thumb +foo: +movs r0, #12 +adds r1, r2, #3 +subs r1, r2, #3 +adds r3, r3, #0x64 +subs r4, r4, #0x83 +cmp r5, #0x27 + +adr r1, bar +ldr r2, bar +ldr r3, [r4, #4] +ldr r5, [sp, #4] +add sp, sp, #4 +sub sp, sp, #4 +add r7, sp, #4 + +rsbs r1, r2, #0 + +.align 2 +bar: + diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_add.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_add.d new file mode 100644 index 00000000..1c438968 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_add.d @@ -0,0 +1,30 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> f60f 0000 addw r0, pc, #2048 ; 0x800 +0+004 <[^>]+> f20f 0900 addw r9, pc, #0 +0+008 <[^>]+> f20f 4900 addw r9, pc, #1024 ; 0x400 +0+00c <[^>]+> f509 6880 add.w r8, r9, #1024 ; 0x400 +0+010 <[^>]+> f209 1801 addw r8, r9, #257 ; 0x101 +0+014 <[^>]+> f201 1301 addw r3, r1, #257 ; 0x101 +0+018 <[^>]+> f6af 0000 subw r0, pc, #2048 ; 0x800 +0+01c <[^>]+> f2af 0900 subw r9, pc, #0 +0+020 <[^>]+> f2af 4900 subw r9, pc, #1024 ; 0x400 +0+024 <[^>]+> f5a9 6880 sub.w r8, r9, #1024 ; 0x400 +0+028 <[^>]+> f2a9 1801 subw r8, r9, #257 ; 0x101 +0+02c <[^>]+> f2a1 1301 subw r3, r1, #257 ; 0x101 +0+030 <[^>]+> f103 0301 add.w r3, r3, #1 +0+034 <[^>]+> f1a3 0301 sub.w r3, r3, #1 +0+038 <[^>]+> b0c0 sub sp, #256 ; 0x100 +0+03a <[^>]+> f5ad 7d00 sub.w sp, sp, #512 ; 0x200 +0+03e <[^>]+> f2ad 1d01 subw sp, sp, #257 ; 0x101 +0+042 <[^>]+> b040 add sp, #256 ; 0x100 +0+044 <[^>]+> f50d 7d00 add.w sp, sp, #512 ; 0x200 +0+048 <[^>]+> f20d 1d01 addw sp, sp, #257 ; 0x101 +0+04c <[^>]+> a840 add r0, sp, #256 ; 0x100 +0+04e <[^>]+> f50d 6580 add.w r5, sp, #1024 ; 0x400 +0+052 <[^>]+> f20d 1901 addw r9, sp, #257 ; 0x101 +0+056 <[^>]+> 4271 negs r1, r6 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_add.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_add.s new file mode 100644 index 00000000..a3b178a0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_add.s @@ -0,0 +1,31 @@ + .syntax unified + .text + .align 2 + .global thumb2_add + .thumb + .thumb_func +thumb2_add: + add r0, pc, #0x800 + add r9, pc, #0 + add r9, pc, #0x400 + add r8, r9, #0x400 + add r8, r9, #0x101 + add r3, r1, #0x101 + sub r0, pc, #0x800 + sub r9, pc, #0 + sub r9, pc, #0x400 + sub r8, r9, #0x400 + sub r8, r9, #0x101 + sub r3, r1, #0x101 + add r3, #1 + sub r3, #1 + sub sp, sp, #0x100 + sub sp, sp, #0x200 + sub sp, sp, #0x101 + add sp, sp, #0x100 + add sp, sp, #0x200 + add sp, sp, #0x101 + add r0, sp, #0x100 + add r5, sp, #0x400 + add r9, sp, #0x101 + rsbs r1, r6, #0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.d new file mode 100644 index 00000000..87128559 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.d @@ -0,0 +1,3 @@ +#name: Invalid r13/r15 register usage +#as: -march=armv7r +#error-output: thumb2_bad_reg.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.l b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.l new file mode 100644 index 00000000..2679e591 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.l @@ -0,0 +1,797 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adc.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adc.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `addw r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r1,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adds.w r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `addw r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r15,r13,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `add.w r0,r13,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `add.w r0,r13,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `adr.w r13,test' +[^:]*:[0-9]+: Error: r15 not allowed here -- `adr.w r15,test' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `and.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `and.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `asr.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `asr.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bfc r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bfc r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bfi r13,r0,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bfi r15,r0,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bfi r0,r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bfi r0,r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bic.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bic.w r0,r1,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `blx r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `bxj r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `bxj r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `clz r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `clz r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `clz r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `clz r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn r15,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `cmn.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmn.w r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r15,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp r15,r0' +[^:]*:[0-9]+: Warning: use of r13 is deprecated +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp r0,r15' +[^:]*:[0-9]+: Warning: use of r13 is deprecated +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.n r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `cmp.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `cmp.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `eor.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `eor.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsl.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsl.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `lsr.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `lsr.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mcr p0,#1,r13,cr0,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mcr p0,#1,r15,cr0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mcrr p0,#1,r13,r0,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mcrr p0,#1,r15,r0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mcrr p0,#1,r0,r13,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mcrr p0,#1,r0,r15,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mla r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mla r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mls r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mls r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movs.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movs.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movs.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movs.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mov.w r13,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r13,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mov.w r15,r15' +[^:]*:[0-9]+: Warning: Use of r13 as a source register is deprecated when r13 is the destination register. +[^:]*:[0-9]+: Warning: Use of r13 as a source register is deprecated when r15 is the destination register. +[^:]*:[0-9]+: Warning: Use of r15 as a source register is deprecated when r13 is the destination register. +[^:]*:[0-9]+: Warning: Use of r15 as a source register is deprecated when r15 is the destination register. +[^:]*:[0-9]+: Error: r13 not allowed here -- `movs r13,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movs r15,r13' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movs r13,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movs r15,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `movt r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `movt r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrc p0,#1,r13,cr0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrrc p0,#1,r13,r0,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mrrc p0,#1,r15,r0,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrrc p0,#1,r0,r13,cr0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mrrc p0,#1,r0,r15,cr0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mrs r13,cpsr' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mrs r15,cpsr' +[^:]*:[0-9]+: Error: r13 not allowed here -- `msr cpsr,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `msr cpsr,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mul r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mul r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `mvn.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `mvn.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orn r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orn r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `orr r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `orr r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pkhbt r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pkhbt r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pld \[r0,r13\]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pld \[r0,r15\]' +[^:]*:[0-9]+: Error: cannot use register index with PC-relative addressing -- `pld \[r15,r0\]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `pli \[r0,r13\]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `pli \[r0,r15\]' +[^:]*:[0-9]+: Error: cannot use register index with PC-relative addressing -- `pli \[r15,r0\]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdadd r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdadd r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qdsub r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qdsub r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `qsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `qsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rbit r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rbit r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rbit r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rbit r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rev16.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rev16.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `revsh.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `revsh.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `revsh.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `revsh.w r0,r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rfedb r15' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rfeia r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ror.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ror.w r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rrx r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rrx r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rrx r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rrx r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb.w r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb.w r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb.w r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb.w r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `rsb r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `rsb r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbc r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbc r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbfx r13,r0,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbfx r15,r0,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sbfx r0,r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sbfx r0,r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sdiv r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sdiv r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sel r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sel r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `shsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `shsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlabb r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlabb r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlad r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlad r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlal r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlal r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlalbb r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlalbb r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlald r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlald r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlawb r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlawb r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsd r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsd r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smlsld r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smlsld r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmla r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmla r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmls r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmls r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smmul r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smmul r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smuad r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smuad r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulbb r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulbb r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smull r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smull r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smulwb r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smulwb r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `smusd r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `smusd r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat r0,#1,r15' +[^:]*:[0-9]+: Error: shift expression is too large -- `ssat r1,#1,r3,asr#32' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssat16 r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssat16 r0,#1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssax r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssax r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ssub8 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ssub8 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r13,r0,#1' +[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `sub.w r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `subw r13,r0,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `subw r15,r0,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r15,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r1,r15' +[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `sub.w r15,r13,#1' +[^:]*:[0-9]+: Error: only SUBS PC, LR, #const allowed -- `subs.w r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `subw r15,r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r15,r13,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sub.w r0,r13,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sub.w r0,r13,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtab16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtab16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtah r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtah r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb16 r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb16 r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxtb16 r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxtb16 r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxth r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxth r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `sxth r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `sxth r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbb \[r13,r0]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbb \[r0,r13]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tbb \[r0,r15]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbh \[r13,r0]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tbh \[r0,r13]' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tbh \[r0,r15]' +[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `teq r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `teq r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tst r13,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tst r15,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tst.w r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tst.w r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `tst.w r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `tst.w r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ubfx r13,r0,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ubfx r15,r0,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `ubfx r0,r13,#1,#1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `ubfx r0,r15,#1,#1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `udiv r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `udiv r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uhsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uhsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umaal r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umaal r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umlal r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umlal r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `umull r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `umull r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqadd8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqadd8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqasx r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqasx r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsax r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsax r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub16 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub16 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uqsub8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uqsub8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usad8 r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usad8 r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r13,r0,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r15,r0,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r13,r0,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r15,r0,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r0,r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r0,r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usada8 r0,r0,r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usada8 r0,r0,r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat r0,#1,r15' +[^:]*:[0-9]+: Error: shift expression is too large -- `usat r1,#1,r3,asr#32' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r13,#1,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r15,#1,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usat16 r0,#1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usat16 r0,#1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usax r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usax r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `usub8 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `usub8 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtab16 r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtab16 r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r13,r0,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r15,r0,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r0,r13,r1' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r0,r15,r1' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtah r0,r1,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtah r0,r1,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb16 r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb16 r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxtb16 r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxtb16 r0,r15' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxth r13,r0' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxth r15,r0' +[^:]*:[0-9]+: Error: r13 not allowed here -- `uxth r0,r13' +[^:]*:[0-9]+: Error: r15 not allowed here -- `uxth r0,r15' diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.s new file mode 100644 index 00000000..f1b1c0b7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bad_reg.s @@ -0,0 +1,983 @@ + .syntax unified + .text + .align 2 + .thumb + .thumb_func +test: + @ ADC (immediate) + adc r13, r0, #1 + adc r15, r0, #1 + adc r0, r13, #1 + adc r0, r15, #1 + @ ADC (register) + adc.w r13, r0, r1 + adc.w r15, r0, r1 + adc.w r0, r13, r1 + adc.w r0, r15, r1 + adc.w r0, r1, r13 + adc.w r0, r1, r15 + @ ADD (immediate) + add.w r13, r0, #1 + add.w r15, r0, #1 + add.w r0, r13, #1 @ ADD (SP plus immediate) + add.w r0, r15, #1 @ Converted implicitly to ADDW + addw r13, r0, #1 + addw r15, r0, #1 + addw r0, r13, #1 @ ADD (SP plus immediate) + addw r0, r15, #1 @ ADR + @ ADD (register) + add.w r13, r0, r1 + add.w r15, r0, r1 + adds.w r15, r0, r1 + add.w r0, r13, r1 @ ADD (SP plus register) + add.w r0, r15, r1 + add.w r0, r1, r13 + add.w r0, r1, r15 + @ ADD (SP plus immediate) + add.w r0, r13, #1 @ OK + add.w r15, r13, #1 + adds.w r15, r13, #1 + addw r15, r13, #1 + @ ADD (SP plus register) + add.w r15, r13, r0 + add.w r0, r13, r13 + add.w r0, r13, r15 + @ ADR + adr.w r13, test + adr.w r15, test + @ AND (immediate) + and r13, r0, #1 + and r15, r0, #1 + and r0, r13, #1 + and r0, r15, #1 + @ AND (register) + and.w r13, r0, r1 + and.w r15, r0, r1 + and.w r0, r13, r1 + and.w r0, r15, r1 + and.w r0, r1, r13 + and.w r0, r1, r15 + @ ASR (immediate) + asr r13, r0, #1 + asr r15, r0, #1 + asr r0, r13, #1 + asr r0, r15, #1 + @ ASR (register) + asr.w r13, r0, r1 + asr.w r15, r0, r1 + asr.w r0, r13, r1 + asr.w r0, r15, r1 + asr.w r0, r1, r13 + asr.w r0, r1, r15 + @ BFC + bfc r13, #1, #1 + bfc r15, #1, #1 + @ BFI + bfi r13, r0, #1, #1 + bfi r15, r0, #1, #1 + bfi r0, r13, #1, #1 + bfi r0, r15, #1, #1 + @ BIC (immediate) + bic r13, r0, #1 + bic r15, r0, #1 + bic r0, r13, #1 + bic r0, r15, #1 + @ BIC (register) + bic.w r13, r0, r1 + bic.w r15, r0, r1 + bic.w r0, r13, r1 + bic.w r0, r15, r1 + bic.w r0, r1, r13 + bic.w r0, r1, r15 + @ BLX (register) + blx r13 @ OK + blx r15 + @ BXJ + bxj r13 + bxj r15 + @ CLZ + clz r13, r0 + clz r15, r0 + clz r0, r13 + clz r0, r15 + @ CMN (immediate) + cmn r13, #1 @ OK + cmn r15, #1 + @ CMN (register) + cmn.w r13, r0 @ OK + cmn.w r15, r0 + cmn.w r0, r13 + cmn.w r0, r15 + @ CMP (immediate) + cmp.w r13, #1 @ OK + cmp.w r15, #1 + @ CMP (register) + cmp r13, r0 @ OK + cmp r15, r0 + cmp r0, r13 @ Deprecated + cmp r0, r15 + cmp.n r0, r13 @ Deprecated + cmp.n r0, r15 + cmp.w r13, r0 @ OK + cmp.w r15, r0 + cmp.w r0, r13 + cmp.w r0, r15 + @ EOR (immediate) + eor r13, r0, #1 + eor r15, r0, #1 + eor r0, r13, #1 + eor r0, r15, #1 + @ EOR (register) + eor.w r13, r0, r1 + eor.w r15, r0, r1 + eor.w r0, r13, r1 + eor.w r0, r15, r1 + eor.w r0, r1, r13 + eor.w r0, r1, r15 + @ LSL (immediate) + lsl r13, r0, #1 + lsl r15, r0, #1 + lsl r0, r13, #1 + lsl r0, r15, #1 + @ LSL (register) + lsl.w r13, r0, r1 + lsl.w r15, r0, r1 + lsl.w r0, r13, r1 + lsl.w r0, r15, r1 + lsl.w r0, r1, r13 + lsl.w r0, r1, r15 + @ LSR (immediate) + lsr r13, r0, #1 + lsr r15, r0, #1 + lsr r0, r13, #1 + lsr r0, r15, #1 + @ LSR (register) + lsr.w r13, r0, r1 + lsr.w r15, r0, r1 + lsr.w r0, r13, r1 + lsr.w r0, r15, r1 + lsr.w r0, r1, r13 + lsr.w r0, r1, r15 + @ MCR + mcr p0, #1, r13, cr0, cr0 + mcr p0, #1, r15, cr0, cr0 @ OK + @ MCRR + mcrr p0, #1, r13, r0, cr0 + mcrr p0, #1, r15, r0, cr0 + mcrr p0, #1, r0, r13, cr0 + mcrr p0, #1, r0, r15, cr0 + @ MLA + mla r13, r0, r0, r0 + mla r15, r0, r0, r0 + mla r0, r13, r0, r0 + mla r0, r15, r0, r0 + mla r0, r0, r13, r0 + mla r0, r0, r15, r0 + mla r0, r0, r0, r13 + mla r0, r0, r0, r15 + @ MLS + mls r13, r0, r0, r0 + mls r15, r0, r0, r0 + mls r0, r13, r0, r0 + mls r0, r15, r0, r0 + mls r0, r0, r13, r0 + mls r0, r0, r15, r0 + mls r0, r0, r0, r13 + mls r0, r0, r0, r15 + @ MOV (immediate) + mov.w r13, #1 + mov.w r15, #1 + @ MOV (register) + mov r13, r0 @ OK + mov r15, r0 @ OK + mov.w r0, r13 @ OK + mov.w r0, r15 + mov.w r15, r0 + mov.w r13, r0 @ OK + movs.w r0, r13 + movs.w r0, r15 + movs.w r13, r0 + movs.w r15, r0 + mov.w r13, r13 + mov.w r15, r13 + mov.w r13, r15 + mov.w r15, r15 + mov r13, r13 @ Deprecated + mov r15, r13 @ Deprecated + mov r13, r15 @ Deprecated + mov r15, r15 @ Deprecated + movs r13, r13 + movs r15, r13 + movs r13, r15 + movs r15, r15 + @ MOVT + movt r13, #1 + movt r15, #1 + @ MRC + mrc p0, #1, r13, cr0, cr0 + mrc p0, #1, r15, cr0, cr0 @ OK + @ MRCC + mrrc p0, #1, r13, r0, cr0 + mrrc p0, #1, r15, r0, cr0 + mrrc p0, #1, r0, r13, cr0 + mrrc p0, #1, r0, r15, cr0 + @ MRS + mrs r13, cpsr + mrs r15, cpsr + @ MSR (register) + msr cpsr, r13 + msr cpsr, r15 + @ MUL + mul r13, r0, r0 + mul r15, r0, r0 + mul r0, r13, r0 + mul r0, r15, r0 + mul r0, r0, r13 + mul r0, r0, r15 + @ MVN (immediate) + mvn r13, #1 + mvn r15, #1 + @ MVN (register) + mvn.w r13, r0 + mvn.w r15, r0 + mvn.w r0, r13 + mvn.w r0, r15 + @ ORN (immediate) + orn r13, r0, #1 + orn r15, r0, #1 + orn r0, r13, #1 + orn r0, r15, #1 + @ ORN (register) + orn r13, r0, r0 + orn r15, r0, r0 + orn r0, r13, r0 + orn r0, r15, r0 + orn r0, r0, r13 + orn r0, r0, r15 + @ ORR (immediate) + orr r13, r0, #1 + orr r15, r0, #1 + orr r0, r13, #1 + orr r0, r15, #1 + @ ORR (register) + orr r13, r0, r0 + orr r15, r0, r0 + orr r0, r13, r0 + orr r0, r15, r0 + orr r0, r0, r13 + orr r0, r0, r15 + @ PKH + pkhbt r13, r0, r0 + pkhbt r15, r0, r0 + pkhbt r0, r13, r0 + pkhbt r0, r15, r0 + pkhbt r0, r0, r13 + pkhbt r0, r0, r15 + @ PLD (register) + pld [r0, r13] + pld [r0, r15] + pld [r13, r0] @ OK + pld [r15, r0] + @ PLI (register) + pli [r0, r13] + pli [r0, r15] + pli [r13, r0] @ OK + pli [r15, r0] + @ QADD + qadd r13, r0, r0 + qadd r15, r0, r0 + qadd r0, r13, r0 + qadd r0, r15, r0 + qadd r0, r0, r13 + qadd r0, r0, r15 + @ QADD16 + qadd16 r13, r0, r0 + qadd16 r15, r0, r0 + qadd16 r0, r13, r0 + qadd16 r0, r15, r0 + qadd16 r0, r0, r13 + qadd16 r0, r0, r15 + @ QADD8 + qadd8 r13, r0, r0 + qadd8 r15, r0, r0 + qadd8 r0, r13, r0 + qadd8 r0, r15, r0 + qadd8 r0, r0, r13 + qadd8 r0, r0, r15 + @ QASX + qasx r13, r0, r0 + qasx r15, r0, r0 + qasx r0, r13, r0 + qasx r0, r15, r0 + qasx r0, r0, r13 + qasx r0, r0, r15 + @ QDADD + qdadd r13, r0, r0 + qdadd r15, r0, r0 + qdadd r0, r13, r0 + qdadd r0, r15, r0 + qdadd r0, r0, r13 + qdadd r0, r0, r15 + @ QDSUB + qdsub r13, r0, r0 + qdsub r15, r0, r0 + qdsub r0, r13, r0 + qdsub r0, r15, r0 + qdsub r0, r0, r13 + qdsub r0, r0, r15 + @ QSAX + qsax r13, r0, r0 + qsax r15, r0, r0 + qsax r0, r13, r0 + qsax r0, r15, r0 + qsax r0, r0, r13 + qsax r0, r0, r15 + @ QSUB + qsub r13, r0, r0 + qsub r15, r0, r0 + qsub r0, r13, r0 + qsub r0, r15, r0 + qsub r0, r0, r13 + qsub r0, r0, r15 + @ QSUB16 + qsub16 r13, r0, r0 + qsub16 r15, r0, r0 + qsub16 r0, r13, r0 + qsub16 r0, r15, r0 + qsub16 r0, r0, r13 + qsub16 r0, r0, r15 + @ QSUB8 + qsub8 r13, r0, r0 + qsub8 r15, r0, r0 + qsub8 r0, r13, r0 + qsub8 r0, r15, r0 + qsub8 r0, r0, r13 + qsub8 r0, r0, r15 + @ RBIT + rbit r13, r0 + rbit r15, r0 + rbit r0, r13 + rbit r0, r15 + @ REV + rev.w r13, r0 + rev.w r15, r0 + rev.w r0, r13 + rev.w r0, r15 + @ REV16 + rev16.w r13, r0 + rev16.w r15, r0 + rev16.w r0, r13 + rev16.w r0, r15 + @ REVSH + revsh.w r13, r0 + revsh.w r15, r0 + revsh.w r0, r13 + revsh.w r0, r15 + @ RFE + rfedb r15 + rfeia r15 + @ ROR (immediate) + ror r13, r0, #1 + ror r15, r0, #1 + ror r0, r13, #1 + ror r0, r15, #1 + @ ROR (register) + ror.w r13, r0, r1 + ror.w r15, r0, r1 + ror.w r0, r13, r1 + ror.w r0, r15, r1 + ror.w r0, r1, r13 + ror.w r0, r1, r15 + @ RRX + rrx r13, r0 + rrx r15, r0 + rrx r0, r13 + rrx r0, r15 + @ RSB (immediate) + rsb.w r13, r0, #1 + rsb.w r15, r0, #1 + rsb.w r0, r13, #1 + rsb.w r0, r15, #1 + @ RSB (register) + rsb r13, r0, r1 + rsb r15, r0, r1 + rsb r0, r13, r1 + rsb r0, r15, r1 + rsb r0, r1, r13 + rsb r0, r1, r15 + @ SADD16 + sadd16 r13, r0, r0 + sadd16 r15, r0, r0 + sadd16 r0, r13, r0 + sadd16 r0, r15, r0 + sadd16 r0, r0, r13 + sadd16 r0, r0, r15 + @ SADD8 + sadd8 r13, r0, r0 + sadd8 r15, r0, r0 + sadd8 r0, r13, r0 + sadd8 r0, r15, r0 + sadd8 r0, r0, r13 + sadd8 r0, r0, r15 + @ SASX + sasx r13, r0, r0 + sasx r15, r0, r0 + sasx r0, r13, r0 + sasx r0, r15, r0 + sasx r0, r0, r13 + sasx r0, r0, r15 + @ SBC (immediate) + sbc r13, r0, #1 + sbc r15, r0, #1 + sbc r0, r13, #1 + sbc r0, r15, #1 + @ SBC (register) + sbc r13, r0, r1 + sbc r15, r0, r1 + sbc r0, r13, r1 + sbc r0, r15, r1 + sbc r0, r1, r13 + sbc r0, r1, r15 + @ SBFX (immediate) + sbfx r13, r0, #1, #1 + sbfx r15, r0, #1, #1 + sbfx r0, r13, #1, #1 + sbfx r0, r15, #1, #1 + @ SDIV (register) + sdiv r13, r0, r1 + sdiv r15, r0, r1 + sdiv r0, r13, r1 + sdiv r0, r15, r1 + sdiv r0, r1, r13 + sdiv r0, r1, r15 + @ SEL (register) + sel r13, r0, r1 + sel r15, r0, r1 + sel r0, r13, r1 + sel r0, r15, r1 + sel r0, r1, r13 + sel r0, r1, r15 + @ SHADD16 + shadd16 r13, r0, r0 + shadd16 r15, r0, r0 + shadd16 r0, r13, r0 + shadd16 r0, r15, r0 + shadd16 r0, r0, r13 + shadd16 r0, r0, r15 + @ SHADD8 + shadd8 r13, r0, r0 + shadd8 r15, r0, r0 + shadd8 r0, r13, r0 + shadd8 r0, r15, r0 + shadd8 r0, r0, r13 + shadd8 r0, r0, r15 + @ SHASX + shasx r13, r0, r0 + shasx r15, r0, r0 + shasx r0, r13, r0 + shasx r0, r15, r0 + shasx r0, r0, r13 + shasx r0, r0, r15 + @ SHSAX + shsax r13, r0, r0 + shsax r15, r0, r0 + shsax r0, r13, r0 + shsax r0, r15, r0 + shsax r0, r0, r13 + shsax r0, r0, r15 + @ SHSUB16 + shsub16 r13, r0, r0 + shsub16 r15, r0, r0 + shsub16 r0, r13, r0 + shsub16 r0, r15, r0 + shsub16 r0, r0, r13 + shsub16 r0, r0, r15 + @ SHSUB8 + shsub8 r13, r0, r0 + shsub8 r15, r0, r0 + shsub8 r0, r13, r0 + shsub8 r0, r15, r0 + shsub8 r0, r0, r13 + shsub8 r0, r0, r15 + @ SMLABB + smlabb r13, r0, r0, r0 + smlabb r15, r0, r0, r0 + smlabb r0, r13, r0, r0 + smlabb r0, r15, r0, r0 + smlabb r0, r0, r13, r0 + smlabb r0, r0, r15, r0 + smlabb r0, r0, r0, r13 + smlabb r0, r0, r0, r15 + @ SMLAD + smlad r13, r0, r0, r0 + smlad r15, r0, r0, r0 + smlad r0, r13, r0, r0 + smlad r0, r15, r0, r0 + smlad r0, r0, r13, r0 + smlad r0, r0, r15, r0 + smlad r0, r0, r0, r13 + smlad r0, r0, r0, r15 + @ SMLAL + smlal r13, r0, r0, r0 + smlal r15, r0, r0, r0 + smlal r0, r13, r0, r0 + smlal r0, r15, r0, r0 + smlal r0, r0, r13, r0 + smlal r0, r0, r15, r0 + smlal r0, r0, r0, r13 + smlal r0, r0, r0, r15 + @ SMLALBB + smlalbb r13, r0, r0, r0 + smlalbb r15, r0, r0, r0 + smlalbb r0, r13, r0, r0 + smlalbb r0, r15, r0, r0 + smlalbb r0, r0, r13, r0 + smlalbb r0, r0, r15, r0 + smlalbb r0, r0, r0, r13 + smlalbb r0, r0, r0, r15 + @ SMLALD + smlald r13, r0, r0, r0 + smlald r15, r0, r0, r0 + smlald r0, r13, r0, r0 + smlald r0, r15, r0, r0 + smlald r0, r0, r13, r0 + smlald r0, r0, r15, r0 + smlald r0, r0, r0, r13 + smlald r0, r0, r0, r15 + @ SMLAWB + smlawb r13, r0, r0, r0 + smlawb r15, r0, r0, r0 + smlawb r0, r13, r0, r0 + smlawb r0, r15, r0, r0 + smlawb r0, r0, r13, r0 + smlawb r0, r0, r15, r0 + smlawb r0, r0, r0, r13 + smlawb r0, r0, r0, r15 + @ SMLSD + smlsd r13, r0, r0, r0 + smlsd r15, r0, r0, r0 + smlsd r0, r13, r0, r0 + smlsd r0, r15, r0, r0 + smlsd r0, r0, r13, r0 + smlsd r0, r0, r15, r0 + smlsd r0, r0, r0, r13 + smlsd r0, r0, r0, r15 + @ SMLSLD + smlsld r13, r0, r0, r0 + smlsld r15, r0, r0, r0 + smlsld r0, r13, r0, r0 + smlsld r0, r15, r0, r0 + smlsld r0, r0, r13, r0 + smlsld r0, r0, r15, r0 + smlsld r0, r0, r0, r13 + smlsld r0, r0, r0, r15 + @ SMMLA + smmla r13, r0, r0, r0 + smmla r15, r0, r0, r0 + smmla r0, r13, r0, r0 + smmla r0, r15, r0, r0 + smmla r0, r0, r13, r0 + smmla r0, r0, r15, r0 + smmla r0, r0, r0, r13 + smmla r0, r0, r0, r15 + @ SMMLS + smmls r13, r0, r0, r0 + smmls r15, r0, r0, r0 + smmls r0, r13, r0, r0 + smmls r0, r15, r0, r0 + smmls r0, r0, r13, r0 + smmls r0, r0, r15, r0 + smmls r0, r0, r0, r13 + smmls r0, r0, r0, r15 + @ SMMUL + smmul r13, r0, r0 + smmul r15, r0, r0 + smmul r0, r13, r0 + smmul r0, r15, r0 + smmul r0, r0, r13 + smmul r0, r0, r15 + @ SMUAD + smuad r13, r0, r0 + smuad r15, r0, r0 + smuad r0, r13, r0 + smuad r0, r15, r0 + smuad r0, r0, r13 + smuad r0, r0, r15 + @ SMULBB + smulbb r13, r0, r0 + smulbb r15, r0, r0 + smulbb r0, r13, r0 + smulbb r0, r15, r0 + smulbb r0, r0, r13 + smulbb r0, r0, r15 + @ SMULL + smull r13, r0, r0, r0 + smull r15, r0, r0, r0 + smull r0, r13, r0, r0 + smull r0, r15, r0, r0 + smull r0, r0, r13, r0 + smull r0, r0, r15, r0 + smull r0, r0, r0, r13 + smull r0, r0, r0, r15 + @ SMULWB + smulwb r13, r0, r0 + smulwb r15, r0, r0 + smulwb r0, r13, r0 + smulwb r0, r15, r0 + smulwb r0, r0, r13 + smulwb r0, r0, r15 + @ SMUSD + smusd r13, r0, r0 + smusd r15, r0, r0 + smusd r0, r13, r0 + smusd r0, r15, r0 + smusd r0, r0, r13 + smusd r0, r0, r15 + @ SSAT + ssat r13, #1, r0 + ssat r15, #1, r0 + ssat r0, #1, r13 + ssat r0, #1, r15 + ssat r1, #1, r3,asr #32 + @ SSAT16 + ssat16 r13, #1, r0 + ssat16 r15, #1, r0 + ssat16 r0, #1, r13 + ssat16 r0, #1, r15 + @ SSAX + ssax r13, r0, r1 + ssax r15, r0, r1 + ssax r0, r13, r1 + ssax r0, r15, r1 + ssax r0, r1, r13 + ssax r0, r1, r15 + @ SSUB16 + ssub16 r13, r0, r1 + ssub16 r15, r0, r1 + ssub16 r0, r13, r1 + ssub16 r0, r15, r1 + ssub16 r0, r1, r13 + ssub16 r0, r1, r15 + @ SSUB8 + ssub8 r13, r0, r1 + ssub8 r15, r0, r1 + ssub8 r0, r13, r1 + ssub8 r0, r15, r1 + ssub8 r0, r1, r13 + ssub8 r0, r1, r15 + @ SUB (immediate) + sub.w r13, r0, #1 + sub.w r15, r0, #1 + sub.w r0, r13, #1 @ SUB (SP minus immediate) + sub.w r0, r15, #1 @ ADR + subw r13, r0, #1 + subw r15, r0, #1 + subw r0, r13, #1 @ SUB (SP minus immediate) + subw r0, r15, #1 @ ADR + @ SUB (register) + sub.w r13, r0, r1 + sub.w r15, r0, r1 + sub.w r0, r13, r1 @ SUB (SP minus register) + sub.w r0, r15, r1 + sub.w r0, r1, r13 + sub.w r0, r1, r15 + @ SUB (SP minus immediate) + sub.w r0, r13, #1 @ OK + sub.w r15, r13, #1 + subs.w r15, r13, #1 + subw r15, r13, #1 + @ SUB (SP minus register) + sub.w r13, r13, r0 @ OK + sub.w r15, r13, r0 + sub.w r0, r13, r13 + sub.w r0, r13, r15 + @ SXTAB + sxtab r13, r0, r1 + sxtab r15, r0, r1 + sxtab r0, r13, r1 + sxtab r0, r15, r1 + sxtab r0, r1, r13 + sxtab r0, r1, r15 + @ SXTAB16 + sxtab16 r13, r0, r1 + sxtab16 r15, r0, r1 + sxtab16 r0, r13, r1 + sxtab16 r0, r15, r1 + sxtab16 r0, r1, r13 + sxtab16 r0, r1, r15 + @ SXTAH + sxtah r13, r0, r1 + sxtah r15, r0, r1 + sxtah r0, r13, r1 + sxtah r0, r15, r1 + sxtah r0, r1, r13 + sxtah r0, r1, r15 + @ SXTB + sxtb r13, r0 + sxtb r15, r0 + sxtb r0, r13 + sxtb r0, r15 + @ SXTB16 + sxtb16 r13, r0 + sxtb16 r15, r0 + sxtb16 r0, r13 + sxtb16 r0, r15 + @ SXTH + sxth r13, r0 + sxth r15, r0 + sxth r0, r13 + sxth r0, r15 + @ TBB + tbb [r13, r0] + tbb [r15, r0] @ OK + tbb [r0, r13] + tbb [r0, r15] + @ TBH + tbh [r13, r0] + tbh [r15, r0] @ OK + tbh [r0, r13] + tbh [r0, r15] + @ TEQ (immediate) + teq r13, #1 + teq r15, #1 + @ TEQ (register) + teq r13, r0 + teq r15, r0 + teq r0, r13 + teq r0, r15 + @ TST (immediate) + tst r13, #1 + tst r15, #1 + @ TST (register) + tst.w r13, r0 + tst.w r15, r0 + tst.w r0, r13 + tst.w r0, r15 + @ UADD16 + uadd16 r13, r0, r0 + uadd16 r15, r0, r0 + uadd16 r0, r13, r0 + uadd16 r0, r15, r0 + uadd16 r0, r0, r13 + uadd16 r0, r0, r15 + @ UADD8 + uadd8 r13, r0, r0 + uadd8 r15, r0, r0 + uadd8 r0, r13, r0 + uadd8 r0, r15, r0 + uadd8 r0, r0, r13 + uadd8 r0, r0, r15 + @ UASX + uasx r13, r0, r0 + uasx r15, r0, r0 + uasx r0, r13, r0 + uasx r0, r15, r0 + uasx r0, r0, r13 + uasx r0, r0, r15 + @ UBFX (immediate) + ubfx r13, r0, #1, #1 + ubfx r15, r0, #1, #1 + ubfx r0, r13, #1, #1 + ubfx r0, r15, #1, #1 + @ UDIV (register) + udiv r13, r0, r1 + udiv r15, r0, r1 + udiv r0, r13, r1 + udiv r0, r15, r1 + udiv r0, r1, r13 + udiv r0, r1, r15 + @ UHADD16 + uhadd16 r13, r0, r0 + uhadd16 r15, r0, r0 + uhadd16 r0, r13, r0 + uhadd16 r0, r15, r0 + uhadd16 r0, r0, r13 + uhadd16 r0, r0, r15 + @ UHADD8 + uhadd8 r13, r0, r0 + uhadd8 r15, r0, r0 + uhadd8 r0, r13, r0 + uhadd8 r0, r15, r0 + uhadd8 r0, r0, r13 + uhadd8 r0, r0, r15 + @ UHASX + uhasx r13, r0, r0 + uhasx r15, r0, r0 + uhasx r0, r13, r0 + uhasx r0, r15, r0 + uhasx r0, r0, r13 + uhasx r0, r0, r15 + @ UHSAX + uhsax r13, r0, r0 + uhsax r15, r0, r0 + uhsax r0, r13, r0 + uhsax r0, r15, r0 + uhsax r0, r0, r13 + uhsax r0, r0, r15 + @ UHSUB16 + uhsub16 r13, r0, r0 + uhsub16 r15, r0, r0 + uhsub16 r0, r13, r0 + uhsub16 r0, r15, r0 + uhsub16 r0, r0, r13 + uhsub16 r0, r0, r15 + @ UHSUB8 + uhsub8 r13, r0, r0 + uhsub8 r15, r0, r0 + uhsub8 r0, r13, r0 + uhsub8 r0, r15, r0 + uhsub8 r0, r0, r13 + uhsub8 r0, r0, r15 + @ UMAAL + umaal r13, r0, r0, r0 + umaal r15, r0, r0, r0 + umaal r0, r13, r0, r0 + umaal r0, r15, r0, r0 + umaal r0, r0, r13, r0 + umaal r0, r0, r15, r0 + umaal r0, r0, r0, r13 + umaal r0, r0, r0, r15 + @ UMLAL + umlal r13, r0, r0, r0 + umlal r15, r0, r0, r0 + umlal r0, r13, r0, r0 + umlal r0, r15, r0, r0 + umlal r0, r0, r13, r0 + umlal r0, r0, r15, r0 + umlal r0, r0, r0, r13 + umlal r0, r0, r0, r15 + @ UMULL + umull r13, r0, r0, r0 + umull r15, r0, r0, r0 + umull r0, r13, r0, r0 + umull r0, r15, r0, r0 + umull r0, r0, r13, r0 + umull r0, r0, r15, r0 + umull r0, r0, r0, r13 + umull r0, r0, r0, r15 + @ UQADD16 + uqadd16 r13, r0, r0 + uqadd16 r15, r0, r0 + uqadd16 r0, r13, r0 + uqadd16 r0, r15, r0 + uqadd16 r0, r0, r13 + uqadd16 r0, r0, r15 + @ UQADD8 + uqadd8 r13, r0, r0 + uqadd8 r15, r0, r0 + uqadd8 r0, r13, r0 + uqadd8 r0, r15, r0 + uqadd8 r0, r0, r13 + uqadd8 r0, r0, r15 + @ UQASX + uqasx r13, r0, r0 + uqasx r15, r0, r0 + uqasx r0, r13, r0 + uqasx r0, r15, r0 + uqasx r0, r0, r13 + uqasx r0, r0, r15 + @ UQSAX + uqsax r13, r0, r0 + uqsax r15, r0, r0 + uqsax r0, r13, r0 + uqsax r0, r15, r0 + uqsax r0, r0, r13 + uqsax r0, r0, r15 + @ UQSUB16 + uqsub16 r13, r0, r0 + uqsub16 r15, r0, r0 + uqsub16 r0, r13, r0 + uqsub16 r0, r15, r0 + uqsub16 r0, r0, r13 + uqsub16 r0, r0, r15 + @ UQSUB8 + uqsub8 r13, r0, r0 + uqsub8 r15, r0, r0 + uqsub8 r0, r13, r0 + uqsub8 r0, r15, r0 + uqsub8 r0, r0, r13 + uqsub8 r0, r0, r15 + @ USAD8 + usad8 r13, r0, r0 + usad8 r15, r0, r0 + usad8 r0, r13, r0 + usad8 r0, r15, r0 + usad8 r0, r0, r13 + usad8 r0, r0, r15 + @ USADA8 + usada8 r13, r0, r0, r0 + usada8 r15, r0, r0, r0 + usada8 r0, r13, r0, r0 + usada8 r0, r15, r0, r0 + usada8 r0, r0, r13, r0 + usada8 r0, r0, r15, r0 + usada8 r0, r0, r0, r13 + usada8 r0, r0, r0, r15 + @ USAT + usat r13, #1, r0 + usat r15, #1, r0 + usat r0, #1, r13 + usat r0, #1, r15 + usat r1, #1, r3,asr #32 + @ USAT16 + usat16 r13, #1, r0 + usat16 r15, #1, r0 + usat16 r0, #1, r13 + usat16 r0, #1, r15 + @ USAX + usax r13, r0, r1 + usax r15, r0, r1 + usax r0, r13, r1 + usax r0, r15, r1 + usax r0, r1, r13 + usax r0, r1, r15 + @ USUB16 + usub16 r13, r0, r1 + usub16 r15, r0, r1 + usub16 r0, r13, r1 + usub16 r0, r15, r1 + usub16 r0, r1, r13 + usub16 r0, r1, r15 + @ USUB8 + usub8 r13, r0, r1 + usub8 r15, r0, r1 + usub8 r0, r13, r1 + usub8 r0, r15, r1 + usub8 r0, r1, r13 + usub8 r0, r1, r15 + @ UXTAB + uxtab r13, r0, r1 + uxtab r15, r0, r1 + uxtab r0, r13, r1 + uxtab r0, r15, r1 + uxtab r0, r1, r13 + uxtab r0, r1, r15 + @ UXTAB16 + uxtab16 r13, r0, r1 + uxtab16 r15, r0, r1 + uxtab16 r0, r13, r1 + uxtab16 r0, r15, r1 + uxtab16 r0, r1, r13 + uxtab16 r0, r1, r15 + @ UXTAH + uxtah r13, r0, r1 + uxtah r15, r0, r1 + uxtah r0, r13, r1 + uxtah r0, r15, r1 + uxtah r0, r1, r13 + uxtah r0, r1, r15 + @ UXTB + uxtb r13, r0 + uxtb r15, r0 + uxtb r0, r13 + uxtb r0, r15 + @ UXTB16 + uxtb16 r13, r0 + uxtb16 r15, r0 + uxtb16 r0, r13 + uxtb16 r0, r15 + @ UXTH + uxth r13, r0 + uxth r15, r0 + uxth r0, r13 + uxth r0, r15 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_bcond.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bcond.d new file mode 100644 index 00000000..be4605ee --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bcond.d @@ -0,0 +1,27 @@ +# as: +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> bf18[ ]+it ne +0+002 <[^>]+> [0-9a-f ]+[ ]+bne.[nw] 0+0 <[^>]+> +0+00. <[^>]+> bf38[ ]+it cc +0+00. <[^>]+> f7ff bff[ab][ ]+bcc.w 0+0 <[^>]+> +0+00. <[^>]+> bf28[ ]+it cs +0+0.. <[^>]+> f7ff fff[78][ ]+blcs 0+0 <[^>]+> +0+0.. <[^>]+> bfb8[ ]+it lt +0+0.. <[^>]+> 47a8[ ]+blxlt r5 +0+0.. <[^>]+> bf08[ ]+it eq +0+0.. <[^>]+> 4740[ ]+bxeq r8 +0+0.. <[^>]+> bfc8[ ]+it gt +0+0.. <[^>]+> e8d4 f001[ ]+tbbgt \[r4, r1\] +0+0.. <[^>]+> bfb8[ ]+it lt +0+0.. <[^>]+> df00[ ]+svclt 0 +0+0.. <[^>]+> bf08[ ]+it eq +0+0.. <[^>]+> f8d0 f000[ ]+ldreq.w pc, \[r0\] +0+0.. <[^>]+> bfdc[ ]+itt le +0+0.. <[^>]+> be00[ ]+bkpt 0x0000 +0+0.. <[^>]+> bf00[ ]+nople +0+0.. <[^>]+> bf00[ ]+nop +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_bcond.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bcond.s new file mode 100644 index 00000000..aef6e8f5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_bcond.s @@ -0,0 +1,27 @@ + .text + .arch armv7 + .thumb + .syntax unified + .thumb_func +thumb2_bcond: + it ne + bne thumb2_bcond + it cc + bcc.w thumb2_bcond + it cs + blcs thumb2_bcond + it lt + blxlt r5 + it eq + bxeq r8 + it gt + tbbgt [r4, r1] + it lt + svclt 0 + it eq + ldreq pc, [r0] + itt le + bkpt #0 + nople + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_invert.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_invert.d new file mode 100644 index 00000000..75a37bae --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_invert.d @@ -0,0 +1,18 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 ; 0x400000 +0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 ; 0x400000 +0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 ; 0x400000 +0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 ; 0x400000 +0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 ; 0x80000000 +0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 ; 0x80000000 +0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 ; 0x80000000 +0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 ; 0x80000000 +0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 ; 0x80000000 +0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 ; 0x80000000 +0+028 <[^>]+> f062 4600 orn r6, r2, #2147483648 ; 0x80000000 +0+02c <[^>]+> f042 4800 orr.w r8, r2, #2147483648 ; 0x80000000 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_invert.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_invert.s new file mode 100644 index 00000000..e72e63c1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_invert.s @@ -0,0 +1,16 @@ + .text + .thumb + .syntax unified +thumb2_invert: + cmp r7, #0xffc00000 + cmn r8, #0xffc00000 + add r9, r4, #0xffc00000 + sub r3, r6, #0xffc00000 + adc r5, r0, #0x7fffffff + sbc r4, r7, #0x7fffffff + and r6, r2, #0x7fffffff + bic r8, r2, #0x7fffffff + mov r3, 0x7fffffff + mvn r1, 0x7fffffff + orr r6, r2, #0x7fffffff + orn r8, r2, #0x7fffffff diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it.d new file mode 100644 index 00000000..073d01f0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it.d @@ -0,0 +1,64 @@ +# name: Mixed 16 and 32-bit Thumb conditional instructions +# as: -march=armv6kt2 +#skip: *-*-*aout* +# objdump: -dr --prefix-addresses --show-raw-insn +# Modifications to this file shall be mirrored to thumb2_it_auto.d + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> bf05 ittet eq +0+002 <[^>]+> 1880 addeq r0, r0, r2 +0+004 <[^>]+> 4440 addeq r0, r8 +0+006 <[^>]+> 1888 addne r0, r1, r2 +0+008 <[^>]+> eb11 0002 addseq.w r0, r1, r2 +0+00c <[^>]+> 4410 add r0, r2 +0+00e <[^>]+> 4440 add r0, r8 +0+010 <[^>]+> 1880 adds r0, r0, r2 +0+012 <[^>]+> eb10 0008 adds.w r0, r0, r8 +0+016 <[^>]+> 1888 adds r0, r1, r2 +0+018 <[^>]+> bf0a itet eq +0+01a <[^>]+> 4310 orreq r0, r2 +0+01c <[^>]+> ea40 0008 orrne.w r0, r0, r8 +0+020 <[^>]+> ea50 0002 orrseq.w r0, r0, r2 +0+024 <[^>]+> ea40 0002 orr.w r0, r0, r2 +0+028 <[^>]+> ea40 0008 orr.w r0, r0, r8 +0+02c <[^>]+> 4310 orrs r0, r2 +0+02e <[^>]+> bf01 itttt eq +0+030 <[^>]+> 4090 lsleq r0, r2 +0+032 <[^>]+> fa00 f008 lsleq.w r0, r0, r8 +0+036 <[^>]+> fa01 f002 lsleq.w r0, r1, r2 +0+03a <[^>]+> fa10 f002 lslseq.w r0, r0, r2 +0+03e <[^>]+> bf02 ittt eq +0+040 <[^>]+> 0048 lsleq r0, r1, #1 +0+042 <[^>]+> ea4f 0048 moveq.w r0, r8, lsl #1 +0+046 <[^>]+> ea5f 0040 movseq.w r0, r0, lsl #1 +0+04a <[^>]+> fa00 f002 lsl.w r0, r0, r2 +0+04e <[^>]+> 4090 lsls r0, r2 +0+050 <[^>]+> ea4f 0041 mov.w r0, r1, lsl #1 +0+054 <[^>]+> 0048 lsls r0, r1, #1 +0+056 <[^>]+> bf01 itttt eq +0+058 <[^>]+> 4288 cmpeq r0, r1 +0+05a <[^>]+> 4540 cmpeq r0, r8 +0+05c <[^>]+> 4608 moveq r0, r1 +0+05e <[^>]+> ea5f 0001 movseq.w r0, r1 +0+062 <[^>]+> bf08 it eq +0+064 <[^>]+> 4640 moveq r0, r8 +0+066 <[^>]+> 4608 mov r0, r1 +0+068 <[^>]+> 0008 movs r0, r1 +0+06a <[^>]+> ea5f 0008 movs.w r0, r8 +0+06e <[^>]+> bf01 itttt eq +0+070 <[^>]+> 43c8 mvneq r0, r1 +0+072 <[^>]+> ea6f 0008 mvneq.w r0, r8 +0+076 <[^>]+> ea7f 0001 mvnseq.w r0, r1 +0+07a <[^>]+> 42c8 cmneq r0, r1 +0+07c <[^>]+> ea6f 0001 mvn.w r0, r1 +0+080 <[^>]+> 43c8 mvns r0, r1 +0+082 <[^>]+> bf02 ittt eq +0+084 <[^>]+> 4248 negeq r0, r1 +0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 +0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 +0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 +0+092 <[^>]+> 4248 negs r0, r1 +0+094 <[^>]+> bfc8 it gt +0+096 <[^>]+> 4220 tstgt r0, r4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it.s new file mode 100644 index 00000000..3b37f34d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it.s @@ -0,0 +1,66 @@ + .text + .thumb + .syntax unified + .thumb_func +foo: + ittet eq + addeq r0, r0, r2 + addeq r0, r0, r8 + addne r0, r1, r2 + addseq r0, r1, r2 + add r0, r0, r2 + add r0, r0, r8 + adds r0, r0, r2 + adds r0, r0, r8 + adds r0, r1, r2 + + itet eq + orreq r0, r0, r2 + orrne r0, r0, r8 + orrseq r0, r0, r2 + orr r0, r0, r2 + orr r0, r0, r8 + orrs r0, r0, r2 + + itttt eq + lsleq r0, r0, r2 + lsleq r0, r0, r8 + lsleq r0, r1, r2 + lslseq r0, r0, r2 + ittt eq + lsleq r0, r1, #1 + lsleq r0, r8, #1 + lslseq r0, r0, #1 + lsl r0, r0, r2 + lsls r0, r0, r2 + lsl r0, r1, #1 + lsls r0, r1, #1 + + itttt eq + cmpeq r0, r1 + cmpeq r0, r8 + moveq r0, r1 + movseq r0, r1 + it eq + moveq r0, r8 + mov r0, r1 + movs r0, r1 + movs r0, r8 + + itttt eq + mvneq r0, r1 + mvneq r0, r8 + mvnseq r0, r1 + cmneq r0, r1 + mvn r0, r1 + mvns r0, r1 + + ittt eq + negeq r0, r1 + negeq r0, r8 + negseq r0, r1 + neg r0, r1 + negs r0, r1 + + it gt + tstgt.n r0, r4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_auto.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_auto.d new file mode 100644 index 00000000..384d605b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_auto.d @@ -0,0 +1,64 @@ +# name: Mixed 16 and 32-bit Thumb conditional instructions +# as: -march=armv6kt2 -mimplicit-it=always +#skip: *-*-*aout* +# source: thumb2_it.s +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> bf05 ittet eq +0+002 <[^>]+> 1880 addeq r0, r0, r2 +0+004 <[^>]+> 4440 addeq r0, r8 +0+006 <[^>]+> 1888 addne r0, r1, r2 +0+008 <[^>]+> eb11 0002 addseq.w r0, r1, r2 +0+00c <[^>]+> 4410 add r0, r2 +0+00e <[^>]+> 4440 add r0, r8 +0+010 <[^>]+> 1880 adds r0, r0, r2 +0+012 <[^>]+> eb10 0008 adds.w r0, r0, r8 +0+016 <[^>]+> 1888 adds r0, r1, r2 +0+018 <[^>]+> bf0a itet eq +0+01a <[^>]+> 4310 orreq r0, r2 +0+01c <[^>]+> ea40 0008 orrne.w r0, r0, r8 +0+020 <[^>]+> ea50 0002 orrseq.w r0, r0, r2 +0+024 <[^>]+> ea40 0002 orr.w r0, r0, r2 +0+028 <[^>]+> ea40 0008 orr.w r0, r0, r8 +0+02c <[^>]+> 4310 orrs r0, r2 +0+02e <[^>]+> bf01 itttt eq +0+030 <[^>]+> 4090 lsleq r0, r2 +0+032 <[^>]+> fa00 f008 lsleq.w r0, r0, r8 +0+036 <[^>]+> fa01 f002 lsleq.w r0, r1, r2 +0+03a <[^>]+> fa10 f002 lslseq.w r0, r0, r2 +0+03e <[^>]+> bf02 ittt eq +0+040 <[^>]+> 0048 lsleq r0, r1, #1 +0+042 <[^>]+> ea4f 0048 moveq.w r0, r8, lsl #1 +0+046 <[^>]+> ea5f 0040 movseq.w r0, r0, lsl #1 +0+04a <[^>]+> fa00 f002 lsl.w r0, r0, r2 +0+04e <[^>]+> 4090 lsls r0, r2 +0+050 <[^>]+> ea4f 0041 mov.w r0, r1, lsl #1 +0+054 <[^>]+> 0048 lsls r0, r1, #1 +0+056 <[^>]+> bf01 itttt eq +0+058 <[^>]+> 4288 cmpeq r0, r1 +0+05a <[^>]+> 4540 cmpeq r0, r8 +0+05c <[^>]+> 4608 moveq r0, r1 +0+05e <[^>]+> ea5f 0001 movseq.w r0, r1 +0+062 <[^>]+> bf08 it eq +0+064 <[^>]+> 4640 moveq r0, r8 +0+066 <[^>]+> 4608 mov r0, r1 +0+068 <[^>]+> 0008 movs r0, r1 +0+06a <[^>]+> ea5f 0008 movs.w r0, r8 +0+06e <[^>]+> bf01 itttt eq +0+070 <[^>]+> 43c8 mvneq r0, r1 +0+072 <[^>]+> ea6f 0008 mvneq.w r0, r8 +0+076 <[^>]+> ea7f 0001 mvnseq.w r0, r1 +0+07a <[^>]+> 42c8 cmneq r0, r1 +0+07c <[^>]+> ea6f 0001 mvn.w r0, r1 +0+080 <[^>]+> 43c8 mvns r0, r1 +0+082 <[^>]+> bf02 ittt eq +0+084 <[^>]+> 4248 negeq r0, r1 +0+086 <[^>]+> f1c8 0000 rsbeq r0, r8, #0 +0+08a <[^>]+> f1d1 0000 rsbseq r0, r1, #0 +0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 +0+092 <[^>]+> 4248 negs r0, r1 +0+094 <[^>]+> bfc8 it gt +0+096 <[^>]+> 4220 tstgt r0, r4 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.d new file mode 100644 index 00000000..0b841ed1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.d @@ -0,0 +1,4 @@ +#name: Invalid IT instructions +#as: +#error-output: thumb2_it_bad.l +# Modifications to this test shall be mirrored to thumb2_it_bad_auto.d. diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.l b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.l new file mode 100644 index 00000000..aa1f6587 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.l @@ -0,0 +1,12 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: branch must be last instruction in IT block -- `beq foo' +[^:]*:9: Error: branch must be last instruction in IT block -- `bleq foo' +[^:]*:10: Error: branch must be last instruction in IT block -- `blxeq r0' +[^:]*:11: Error: instruction not allowed in IT block -- `cbzeq r0,foo' +[^:]*:13: Error: branch must be last instruction in IT block -- `bxeq r0' +[^:]*:14: Error: branch must be last instruction in IT block -- `tbbeq \[r0,r1\]' +[^:]*:15: Error: instruction not allowed in IT block -- `cpsieeq f' +[^:]*:17: Error: instruction not allowed in IT block -- `cpseq #0x10' +[^:]*:19: Error: instruction is always unconditional -- `bkpteq 0' +[^:]*:20: Error: instruction not allowed in IT block -- `setendeq le' +[^:]*:22: Error: IT falling in the range of a previous IT block -- `iteq eq' diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.s new file mode 100644 index 00000000..6add4fb5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad.s @@ -0,0 +1,24 @@ + .text + .syntax unified + .arch armv7a + .thumb + .thumb_func +thumb2_it_bad: + itttt eq + beq foo + bleq foo + blxeq r0 + cbzeq r0, foo + ittt eq + bxeq r0 + tbbeq [r0, r1] + cpsieeq f + it eq + cpseq #0x10 + itt eq + bkpteq 0 + setendeq le + it eq + iteq eq + nop +foo: diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad_auto.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad_auto.d new file mode 100644 index 00000000..72743115 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_it_bad_auto.d @@ -0,0 +1,4 @@ +#name: Invalid IT instructions +#as: -mimplicit-it=always +#source: thumb2_it_bad.s +#error-output: thumb2_it_bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm.d new file mode 100644 index 00000000..3ab53ac6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm.d @@ -0,0 +1,60 @@ +# name: Thumb-2 LDM/STM +# as: -march=armv6t2 +# objdump: -dr --prefix-addresses --show-raw-insn +# not-target: *-*-*aout* + + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> bc01 pop {r0} +0[0-9a-f]+ <[^>]+> f85d 8b04 ldr.w r8, \[sp\], #4 +0[0-9a-f]+ <[^>]+> f8d1 9000 ldr.w r9, \[r1\] +0[0-9a-f]+ <[^>]+> f852 cb04 ldr.w ip, \[r2\], #4 +0[0-9a-f]+ <[^>]+> f85d 2d04 ldr.w r2, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f85d 8d04 ldr.w r8, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f856 4c04 ldr.w r4, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f856 8c04 ldr.w r8, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f852 4d04 ldr.w r4, \[r2, #-4\]! +0[0-9a-f]+ <[^>]+> f852 cd04 ldr.w ip, \[r2, #-4\]! +0[0-9a-f]+ <[^>]+> b408 push {r3} +0[0-9a-f]+ <[^>]+> f84d 9b04 str.w r9, \[sp\], #4 +0[0-9a-f]+ <[^>]+> f8c3 c000 str.w ip, \[r3\] +0[0-9a-f]+ <[^>]+> f844 cb04 str.w ip, \[r4\], #4 +0[0-9a-f]+ <[^>]+> f84d 3d04 str.w r3, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f84d 9d04 str.w r9, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f847 5c04 str.w r5, \[r7, #-4\] +0[0-9a-f]+ <[^>]+> f846 cc04 str.w ip, \[r6, #-4\] +0[0-9a-f]+ <[^>]+> f846 bd04 str.w fp, \[r6, #-4\]! +0[0-9a-f]+ <[^>]+> f845 8d04 str.w r8, \[r5, #-4\]! +0[0-9a-f]+ <[^>]+> c80e ldmia r0!, {r1, r2, r3} +0[0-9a-f]+ <[^>]+> c80f ldmia r0, {r0, r1, r2, r3} +0[0-9a-f]+ <[^>]+> c802 ldmia r0!, {r1} +0[0-9a-f]+ <[^>]+> e890 0f00 ldmia.w r0, {r8, r9, sl, fp} +0[0-9a-f]+ <[^>]+> e8b0 000e ldmia.w r0!, {r1, r2, r3} +0[0-9a-f]+ <[^>]+> e8b0 0f00 ldmia.w r0!, {r8, r9, sl, fp} +0[0-9a-f]+ <[^>]+> e8b0 5000 ldmia.w r0!, {ip, lr} +0[0-9a-f]+ <[^>]+> e8b0 9000 ldmia.w r0!, {ip, pc} +0[0-9a-f]+ <[^>]+> bf08 it eq +0[0-9a-f]+ <[^>]+> e8b0 9000 ldmiaeq.w r0!, {ip, pc} +0[0-9a-f]+ <[^>]+> c00f stmia r0!, {r0, r1, r2, r3} +0[0-9a-f]+ <[^>]+> c0f0 stmia r0!, {r4, r5, r6, r7} +0[0-9a-f]+ <[^>]+> e8a0 00f0 stmia.w r0!, {r4, r5, r6, r7} +0[0-9a-f]+ <[^>]+> e8a0 0f00 stmia.w r0!, {r8, r9, sl, fp} +0[0-9a-f]+ <[^>]+> e880 000f stmia.w r0, {r0, r1, r2, r3} +0[0-9a-f]+ <[^>]+> e880 0f00 stmia.w r0, {r8, r9, sl, fp} +0[0-9a-f]+ <[^>]+> f850 1b04 ldr.w r1, \[r0\], #4 +0[0-9a-f]+ <[^>]+> f8d0 1000 ldr.w r1, \[r0\] +0[0-9a-f]+ <[^>]+> f858 9b04 ldr.w r9, \[r8\], #4 +0[0-9a-f]+ <[^>]+> f8d8 9000 ldr.w r9, \[r8\] +0[0-9a-f]+ <[^>]+> f840 1b04 str.w r1, \[r0\], #4 +0[0-9a-f]+ <[^>]+> 6001 str r1, \[r0, #0\] +0[0-9a-f]+ <[^>]+> 680a ldr r2, \[r1, #0\] +0[0-9a-f]+ <[^>]+> 6807 ldr r7, \[r0, #0\] +0[0-9a-f]+ <[^>]+> 9700 str r7, \[sp, #0\] +0[0-9a-f]+ <[^>]+> 9000 str r0, \[sp, #0\] +0[0-9a-f]+ <[^>]+> 9f00 ldr r7, \[sp, #0\] +0[0-9a-f]+ <[^>]+> 9800 ldr r0, \[sp, #0\] +0[0-9a-f]+ <[^>]+> f848 9b04 str.w r9, \[r8\], #4 +0[0-9a-f]+ <[^>]+> f8c8 9000 str.w r9, \[r8\] +#pass diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm.s new file mode 100644 index 00000000..ab7701c7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm.s @@ -0,0 +1,63 @@ +.syntax unified +.thumb +ldmstm: + ldmia sp!, {r0} + ldmia sp!, {r8} + ldmia r1, {r9} + ldmia r2!, {ip} + ldmdb sp!, {r2} + ldmdb sp!, {r8} + ldmdb r6, {r4} + ldmdb r6, {r8} + ldmdb r2!, {r4} + ldmdb r2!, {ip} + stmia sp!, {r3} + stmia sp!, {r9} + stmia r3, {ip} + stmia r4!, {ip} + stmdb sp!, {r3} + stmdb sp!, {r9} + stmdb r7, {r5} + stmdb r6, {ip} + stmdb r6!, {fp} + stmdb r5!, {r8} + + @ Valid Thumb-2 encodings of LDM/LDMIA/LDMFD as specified by section + @ A8.6.53 of the ARM ARM + ldmia r0!, {r1-r3} @ Encoding T1 + ldmia r0, {r0-r3} @ Encoding T1 + ldmia r0!, {r1} @ Encoding T1 + ldmia r0, {r8-r11} @ Encoding T2 + ldmia.w r0!, {r1-r3} @ Encoding T2 + ldmia r0!, {r8-r11} @ Encoding T2 + ldmia r0!, {r12, r14} @ Encoding T2 + ldmia r0!, {r12, pc} @ Encoding T2 + it eq + ldmiaeq r0!, {r12, pc} @ Encoding T2 + + @ Valid Thumb-2 encodings of STM/STMIA/STMEA as specified by section + @ A8.6.189 of the ARMARM. + stmia r0!, {r0-r3} @ Encoding T1, Allowed as r0 is lowest reg + stmia r0!, {r4-r7} @ Encoding T1 + stmia.w r0!, {r4-r7} @ Encoding T2 + stmia r0!, {r8-r11} @ Encoding T2 + stmia r0, {r0-r3} @ Encoding T2 + stmia r0, {r8-r11} @ Encoding T2 + + @ The following are technically UNPREDICTABLE if we assemble them + @ as written, but gas translates (stm|ldm) rn(!), {rd} into an + @ equivalent, and well-defined, (ldr, str) rd, [rn], (#4). + ldmia.w r0!, {r1} @ ldr.w r1, [r0], #4 + ldmia.w r0, {r1} @ ldr.w r1, [r0] + ldmia r8!, {r9} @ ldr.w r9, [r8], #4 + ldmia r8, {r9} @ ldr.w r9, [r8] + stmia.w r0!, {r1} @ str.w r1, [r0], #4 + stmia r0, {r1} @ T1 str r1, [r0] + ldmia r1, {r2} @ T1 ldr r2, [r1] + ldmia r0, {r7} @ T1 ldr r7, [r0] + stmia sp, {r7} @ T1 str r7, [sp] + stmia sp, {r0} @ T1 str r0, [sp] + ldmia sp, {r7} @ T1 ldr r7, [sp] + ldmia sp, {r0} @ T1 ldr r0, [sp] + stmia r8!, {r9} @ str.w r9, [r8], #4 + stmia r8, {r9} @ str.w r9, [r8] diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.d new file mode 100644 index 00000000..05d53144 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.d @@ -0,0 +1,3 @@ +#name: Invalid Thumb-2 LDM/STM instructions +#as: -march=armv6t2 +#error-output: thumb2_ldmstm_bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.l b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.l new file mode 100644 index 00000000..70c4bdee --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.l @@ -0,0 +1,12 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: r15 not allowed here -- `ldmia r15,{r0-r3}' +[^:]*:7: Error: r15 not allowed here -- `ldmia r15!,{r0-r3}' +[^:]*:8: Error: LR and PC should not both be in register list -- `ldmia r1,{r14,r15}' +[^:]*:9: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `ldmia r0!,{r0-r3}' +[^:]*:12: Error: branch must be last instruction in IT block -- `ldmiaeq r0,{r12,r15}' +[^:]*:13: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `ldmiaeq r0!,{r0,r1}' +[^:]*:17: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `stmia.w r0!,{r0-r3}' +[^:]*:18: Warning: value stored for r1 is UNKNOWN +[^:]*:19: Error: r15 not allowed here -- `stmia r15!,{r0-r3}' +[^:]*:20: Error: r15 not allowed here -- `stmia r15,{r0-r3}' +[^:]*:21: Error: having the base register in the register list when using write back is UNPREDICTABLE -- `stmia r8!,{r0-r11}' diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.s new file mode 100644 index 00000000..70d4bdd2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldmstm_bad.s @@ -0,0 +1,30 @@ +.syntax unified +.thumb +ldmstm_bad: + @ UNPREDICTABLE Thumb-2 encodings of LDM/LDMIA/LDMFD as specified + @ by section A8.6.53 of the ARMARM. + ldmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE + ldmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE + ldmia r1, {r14, r15} @ Encoding T2, UNPREDICTABLE + ldmia r0!, {r0-r3} @ Encoding T2, UNPREDICTABLE + + itt eq + ldmiaeq r0, {r12, r15} @ Encoding T2, UNPREDICTABLE + ldmiaeq r0!, {r0, r1} @ Encoding T2, UNPREDICTABLE + + @ UNPREDICTABLE Thumb-2 encodings of STM/STMIA/STMEA as specified + @ by section A8.6.189 of the ARMARM. + stmia.w r0!, {r0-r3} @ Encoding T2, UNPREDICTABLE + stmia r1!, {r0-r3} @ Encoding T1, r1 is UNKNOWN + stmia r15!, {r0-r3} @ Encoding T2, UNPREDICTABLE + stmia r15, {r0-r3} @ Encoding T2, UNPREDICTABLE + stmia r8!, {r0-r11} @ Encoding T2, UNPREDICTABLE + + @ The following are technically UNDEFINED, but gas converts them to + @ an equivalent, and well-defined instruction automatically. + @stmia.w r0!, {r1} @ str.w r1, [r0], #4 + @stmia r8!, {r9} @ str.w r9, [r8], #4 + @stmia r8, {r9} @ str.w r9, [r8] + @ldmia.w r0!, {r1} @ ldr.w r1, [r0], #4 + @ldmia r8!, {r9} @ ldr.w r9, [r8], #4 + @ldmia r8, {r9} @ ldr.w r9, [r8] diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.d new file mode 100644 index 00000000..0f4293e1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.d @@ -0,0 +1,2 @@ +# name: Unpredictable LDRD and STRD instructions. - Thumb-2 +# error-output: thumb2_ldstd_unpredictable.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.l b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.l new file mode 100644 index 00000000..632ecd40 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.l @@ -0,0 +1,9 @@ +[^:]*: Assembler messages: +[^:]*:5: Warning: base register written back, and overlaps one of transfer registers +[^:]*:6: Warning: base register written back, and overlaps one of transfer registers +[^:]*:7: Warning: base register written back, and overlaps one of transfer registers +[^:]*:8: Warning: base register written back, and overlaps one of transfer registers +[^:]*:10: Warning: base register written back, and overlaps one of transfer registers +[^:]*:11: Warning: base register written back, and overlaps one of transfer registers +[^:]*:12: Warning: base register written back, and overlaps one of transfer registers +[^:]*:13: Warning: base register written back, and overlaps one of transfer registers diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.s new file mode 100644 index 00000000..bc81b7a6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_ldstd_unpredictable.s @@ -0,0 +1,13 @@ + .syntax unified + .cpu cortex-a9 + .text + .thumb + strd r10,r11,[r10], #4 @ Unpredictable + strd r10,r11,[r11], #4 @ Ditto + strd r4,r6,[r4, #4]! @ Ditto + strd r4,r6,[r6, #4]! @ Ditto + + ldrd r4,r6,[r4, #4]! @ Ditto + ldrd r4,r6,[r6, #4]! @ Ditto + ldrd r10,r11,[r10], #4 @ Ditto + ldrd r10,r11,[r11], #4 @ Ditto diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.d new file mode 100644 index 00000000..c09bf428 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.d @@ -0,0 +1,3 @@ +#name: Invalid Thumb-2 multiply instructions +#as: -march=armv6kt2 +#error-output: thumb2_mul-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.l b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.l new file mode 100644 index 00000000..7b7a0448 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.l @@ -0,0 +1,8 @@ +[^:]*: Assembler messages: +[^:]*:10: Error: cannot honor width suffix -- `muleq.n r0,r0,r8' +[^:]*:12: Error: cannot honor width suffix -- `muleq.n r0,r1,r1' +[^:]*:13: Error: cannot honor width suffix -- `muleq.n r0,r1,r2' +[^:]*:15: Error: Thumb-2 MUL must not set flags -- `mulseq r0,r0,r1' +[^:]*:17: Error: Thumb-2 MUL must not set flags -- `muls.w r0,r0,r1' +[^:]*:19: Error: Thumb-2 MUL must not set flags -- `muls r0,r0,r8' +[^:]*:20: Error: Thumb-2 MUL must not set flags -- `muls r0,r8,r0' diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.s new file mode 100644 index 00000000..aa02847a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul-bad.s @@ -0,0 +1,20 @@ + .syntax unified + .text + .align 2 + .global thumb2_mul + .thumb + .thumb_func +thumb2_mul: + itttt eq + # Cannot use 16-bit encoding because of use of high register. + muleq.n r0, r0, r8 + # Cannot use 16-bit encoding because source does not match destination. + muleq.n r0, r1, r1 + muleq.n r0, r1, r2 + # There is no conditional "muls". + mulseq r0, r0, r1 + # There is no 32-bit "muls". + muls.w r0, r0, r1 + # Cannot use high registers with "muls". + muls r0, r0, r8 + muls r0, r8, r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul.d new file mode 100644 index 00000000..11943c48 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul.d @@ -0,0 +1,19 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> bf04 itt eq +0+002 <[^>]+> 4348 muleq r0, r1 +0+004 <[^>]+> 4348 muleq r0, r1 +0+006 <[^>]+> bf02 ittt eq +0+008 <[^>]+> fb00 f008 muleq.w r0, r0, r8 +0+00c <[^>]+> fb08 f000 muleq.w r0, r8, r0 +0+010 <[^>]+> fb00 f808 muleq.w r8, r0, r8 +0+014 <[^>]+> bf04 itt eq +0+016 <[^>]+> fb01 f001 muleq.w r0, r1, r1 +0+01a <[^>]+> fb01 f002 muleq.w r0, r1, r2 +0+01e <[^>]+> bf04 itt eq +0+020 <[^>]+> fb01 f000 muleq.w r0, r1, r0 +0+024 <[^>]+> fb00 f001 muleq.w r0, r0, r1 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul.s new file mode 100644 index 00000000..e6d7a653 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_mul.s @@ -0,0 +1,29 @@ + .syntax unified + .text + .align 2 + .global thumb2_mul + .thumb + .thumb_func +thumb2_mul: + # These can use the 16-bit encoding. + itt eq + muleq r0, r1, r0 + muleq r0, r0, r1 + # These must use the 32-bit encoding because they involve + # high registers. + ittt eq + muleq r0, r0, r8 + muleq r0, r8, r0 + muleq r8, r0, r8 + # These must use the 32-bit encoding because the source and + # destination do not match. + itt eq + muleq r0, r1, r1 + muleq r0, r1, r2 + # These must use the 32-bit encoding because of the explicit + # suffix. + itt eq + muleq.w r0, r1, r0 + muleq.w r0, r0, r1 + + diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_pool.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_pool.d new file mode 100644 index 00000000..4d6ce445 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_pool.d @@ -0,0 +1,16 @@ +# as: -march=armv6t2 +# objdump: -dr --prefix-addresses --show-raw-insn +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] ; \(00+14 <[^>]+>\) +0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(00+14 <[^>]+>\) +0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] ; 00+14 <[^>]+> +0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] ; 00+14 <[^>]+> +0+00c <[^>]+> bf00 nop +0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+> +0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] ; \(00+14 <[^>]+>\) +0+014 <[^>]+> 12345678 ? .word 0x12345678 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_pool.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_pool.s new file mode 100644 index 00000000..844e77ec --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_pool.s @@ -0,0 +1,13 @@ + .text + .thumb + .syntax unified + .thumb_func +thumb2_ldr: + ldr r6, =0x12345678 + ldr.n r1, =0x12345678 + ldr.w r6, =0x12345678 + ldr r9, =0x12345678 + nop + ldr.w r5, =0x12345678 + ldr r1, =0x12345678 + .pool diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_relax.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_relax.d new file mode 100644 index 00000000..53483a78 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_relax.d @@ -0,0 +1,104 @@ +# as: -march=armv6kt2 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> 7829 ldrb r1, \[r5, #0\] +0+002 <[^>]+> f895 1023 ldrb.w r1, \[r5, #35\].* +0+006 <[^>]+> 7fe9 ldrb r1, \[r5, #31\] +0+008 <[^>]+> f895 101f ldrb.w r1, \[r5, #31\] +0+00c <[^>]+> f815 1c1f ldrb.w r1, \[r5, #-31\] +0+010 <[^>]+> f815 1b1f ldrb.w r1, \[r5\], #31 +0+014 <[^>]+> f815 1b1f ldrb.w r1, \[r5\], #31 +0+018 <[^>]+> f815 1f1f ldrb.w r1, \[r5, #31\]! +0+01c <[^>]+> f815 1d1f ldrb.w r1, \[r5, #-31\]! +0+020 <[^>]+> 5d29 ldrb r1, \[r5, r4\] +0+022 <[^>]+> f819 100c ldrb.w r1, \[r9, ip\] +0+026 <[^>]+> f89f 1014 ldrb.w r1, \[pc, #20\] ; 0+03c <[^>]+> +0+02a <[^>]+> f89f 1010 ldrb.w r1, \[pc, #16\] ; 0+03c <[^>]+> +0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] ; 0+03c <[^>]+> +0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] ; 0+03e <[^>]+> +0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] ; 0+000 <[^>]+> +0+03a <[^>]+> bf00 nop +0+03c <[^>]+> bf00 nop +0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\] +0+042 <[^>]+> f995 1023 ldrsb.w r1, \[r5, #35\].* +0+046 <[^>]+> f995 101f ldrsb.w r1, \[r5, #31\] +0+04a <[^>]+> f995 101f ldrsb.w r1, \[r5, #31\] +0+04e <[^>]+> f915 1c1f ldrsb.w r1, \[r5, #-31\] +0+052 <[^>]+> f915 1b1f ldrsb.w r1, \[r5\], #31 +0+056 <[^>]+> f915 1b1f ldrsb.w r1, \[r5\], #31 +0+05a <[^>]+> f915 1f1f ldrsb.w r1, \[r5, #31\]! +0+05e <[^>]+> f915 1d1f ldrsb.w r1, \[r5, #-31\]! +0+062 <[^>]+> 5729 ldrsb r1, \[r5, r4\] +0+064 <[^>]+> f919 100c ldrsb.w r1, \[r9, ip\] +0+068 <[^>]+> f99f 1010 ldrsb.w r1, \[pc, #16\] ; 0+07c <[^>]+> +0+06c <[^>]+> f99f 100c ldrsb.w r1, \[pc, #12\] ; 0+07c <[^>]+> +0+070 <[^>]+> f99f 8008 ldrsb.w r8, \[pc, #8\] ; 0+07c <[^>]+> +0+074 <[^>]+> f99f 1006 ldrsb.w r1, \[pc, #6\] ; 0+07e <[^>]+> +0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] ; 0+03e <[^>]+> +0+07c <[^>]+> bf00 nop +0+07e <[^>]+> 8829 ldrh r1, \[r5, #0\] +0+080 <[^>]+> f8b5 1042 ldrh.w r1, \[r5, #66\].* +0+084 <[^>]+> 8fe9 ldrh r1, \[r5, #62\].* +0+086 <[^>]+> f8b5 103e ldrh.w r1, \[r5, #62\].* +0+08a <[^>]+> f835 1c3e ldrh.w r1, \[r5, #-62\].* +0+08e <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62.* +0+092 <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62.* +0+096 <[^>]+> f835 1f3e ldrh.w r1, \[r5, #62\]!.* +0+09a <[^>]+> f835 1d3e ldrh.w r1, \[r5, #-62\]!.* +0+09e <[^>]+> 5b29 ldrh r1, \[r5, r4\] +0+0a0 <[^>]+> f839 100c ldrh.w r1, \[r9, ip\] +0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] ; 0+0b8 <[^>]+> +0+0a8 <[^>]+> f8bf 100c ldrh.w r1, \[pc, #12\] ; 0+0b8 <[^>]+> +0+0ac <[^>]+> f8bf 8008 ldrh.w r8, \[pc, #8\] ; 0+0b8 <[^>]+> +0+0b0 <[^>]+> f8bf 1006 ldrh.w r1, \[pc, #6\] ; 0+0ba <[^>]+> +0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] ; 0+07e <[^>]+> +0+0b8 <[^>]+> bf00 nop +0+0ba <[^>]+> f9b5 1000 ldrsh.w r1, \[r5\] +0+0be <[^>]+> f9b5 1042 ldrsh.w r1, \[r5, #66\].* +0+0c2 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\].* +0+0c6 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\].* +0+0ca <[^>]+> f935 1c3e ldrsh.w r1, \[r5, #-62\].* +0+0ce <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62.* +0+0d2 <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62.* +0+0d6 <[^>]+> f935 1f3e ldrsh.w r1, \[r5, #62\]!.* +0+0da <[^>]+> f935 1d3e ldrsh.w r1, \[r5, #-62\]!.* +0+0de <[^>]+> 5f29 ldrsh r1, \[r5, r4\] +0+0e0 <[^>]+> f939 100c ldrsh.w r1, \[r9, ip\] +0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] ; 0+0f8 <[^>]+> +0+0e8 <[^>]+> f9bf 100c ldrsh.w r1, \[pc, #12\] ; 0+0f8 <[^>]+> +0+0ec <[^>]+> f9bf 8008 ldrsh.w r8, \[pc, #8\] ; 0+0f8 <[^>]+> +0+0f0 <[^>]+> f9bf 1006 ldrsh.w r1, \[pc, #6\] ; 0+0fa <[^>]+> +0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] ; 0+0ba <[^>]+> +0+0f8 <[^>]+> bf00 nop +0+0fa <[^>]+> 6829 ldr r1, \[r5, #0\] +0+0fc <[^>]+> f8d5 1080 ldr.w r1, \[r5, #128\].* +0+100 <[^>]+> 6fe9 ldr r1, \[r5, #124\].* +0+102 <[^>]+> f8d5 107c ldr.w r1, \[r5, #124\].* +0+106 <[^>]+> f855 1c7c ldr.w r1, \[r5, #-124\].* +0+10a <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124.* +0+10e <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124.* +0+112 <[^>]+> f855 1f7c ldr.w r1, \[r5, #124\]!.* +0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]!.* +0+11a <[^>]+> 5929 ldr r1, \[r5, r4\] +0+11c <[^>]+> f859 100c ldr.w r1, \[r9, ip\] +0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] ; \(0+134 <[^>]+>\) +0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] ; 0+134 <[^>]+> +0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+> +0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+> +0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] ; 0+0fa <[^>]+> +0+132 <[^>]+> bf00 nop +0+134 <[^>]+> bf00 nop +0+136 <[^>]+> a104 add r1, pc, #16 ; \(adr r1, 0+148 <[^>]+>\) +0+138 <[^>]+> f20f 010c addw r1, pc, #12 +0+13c <[^>]+> f20f 0808 addw r8, pc, #8 +0+140 <[^>]+> f20f 0106 addw r1, pc, #6 +0+144 <[^>]+> f2af 0112 subw r1, pc, #18 +0+148 <[^>]+> bf00 nop +0+14a <[^>]+> bf00 nop +0+14c <[^>]+> f20f 0104 addw r1, pc, #4 +0+150 <[^>]+> f20f 0102 addw r1, pc, #2 +0+154 <[^>]+> bf00 nop +0+156 <[^>]+> bf00 nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_relax.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_relax.s new file mode 100644 index 00000000..60661e80 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_relax.s @@ -0,0 +1,56 @@ + .text + .thumb + .syntax unified +thumb2_relax: + .macro ls op w=".w" +1: + \op r1, [r5] + \op r1, [r5, #(far_\op + 4)] + \op r1, [r5, #far_\op] + \op\w r1, [r5, #far_\op] + \op r1, [r5, #-far_\op] + \op r1, [r5], #far_\op + \op r1, [r5], #far_\op + \op r1, [r5, #far_\op]! + \op r1, [r5, #-far_\op]! + \op r1, [r5, r4] + \op r1, [r9, ip] + \op r1, 1f + \op\w r1, 1f + \op r8, 1f + \op r1, 2f + \op r1, 1b + .align 2 +1: + nop +2: + .endm +.equ far_ldrb, 0x1f +.equ far_ldrsb, 0x1f +.equ far_ldrh, 0x3e +.equ far_ldrsh, 0x3e +.equ far_ldr, 0x7c + ls ldrb + ls ldrsb + ls ldrh + ls ldrsh + ls ldr + .purgem ls +1: + adr r1, 1f + adr.w r1, 1f + adr r8, 1f + adr r1, 2f + adr r1, 1b +.align 2 +1: + nop +2: + nop + @ Relaxation with conflicting alignment requirements. + adr r1, 1f + adr r1, 2f +1: + nop +2: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.d b/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.d new file mode 100644 index 00000000..6041643a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.d @@ -0,0 +1,3 @@ +#name: Invalid Thumb-2 str instructions +#as: -march=armv6kt2 +#error-output: thumb2_str-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.l b/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.l new file mode 100644 index 00000000..5ee05972 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.l @@ -0,0 +1,4 @@ +[^:]*: Assembler messages: +[^:]*:8: Error: cannot use register index with PC-relative addressing -- `str r0,\[pc,4\]' +[^:]*:9: Error: cannot use register index with PC-relative addressing -- `str r0,d' +[^:]*:10: Error: r15 not allowed here -- `str pc,\[r0\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.s new file mode 100644 index 00000000..d5c37a57 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_str-bad.s @@ -0,0 +1,15 @@ + .syntax unified + .text + .align 2 + .global thumb2_str + .thumb + .thumb_func +thumb2_str: + str r0, [pc, 4] + str r0, d + str pc, [r0] + + .space 4 + .align +d: + .long 0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb32.d b/binutils-2.25/gas/testsuite/gas/arm/thumb32.d new file mode 100644 index 00000000..9fd5f242 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb32.d @@ -0,0 +1,1067 @@ +# name: 32-bit Thumb instructions +# as: -march=armv6zkt2 +# objdump: -dr --prefix-addresses --show-raw-insn +# The arm-aout and arm-pe ports do not support Thumb branch relocations. +# not-target: *-*-*aout* *-*-pe +# stderr: thumb32.l + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f041 0000 orr\.w r0, r1, #0 +0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 ; 0xa5 +0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 ; 0xa500a5 +0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 ; 0xa500a500 +0[0-9a-f]+ <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 ; 0xa5a5a5a5 +0[0-9a-f]+ <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 ; 0x80000000 +0[0-9a-f]+ <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 ; 0x40000000 +0[0-9a-f]+ <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 ; 0xa0000000 +0[0-9a-f]+ <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 ; 0x50000000 +0[0-9a-f]+ <[^>]+> f041 5020 orr\.w r0, r1, #671088640 ; 0x28000000 +0[0-9a-f]+ <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 ; 0x94000000 +0[0-9a-f]+ <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 ; 0x4a000000 +0[0-9a-f]+ <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 ; 0xa5000000 +0[0-9a-f]+ <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 ; 0x52800000 +0[0-9a-f]+ <[^>]+> f041 5025 orr\.w r0, r1, #692060160 ; 0x29400000 +0[0-9a-f]+ <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 ; 0x14a00000 +0[0-9a-f]+ <[^>]+> f041 6025 orr\.w r0, r1, #173015040 ; 0xa500000 +0[0-9a-f]+ <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 ; 0x5280000 +0[0-9a-f]+ <[^>]+> f041 7025 orr\.w r0, r1, #43253760 ; 0x2940000 +0[0-9a-f]+ <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 ; 0x14a0000 +0[0-9a-f]+ <[^>]+> f441 0025 orr\.w r0, r1, #10813440 ; 0xa50000 +0[0-9a-f]+ <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 ; 0x528000 +0[0-9a-f]+ <[^>]+> f441 1025 orr\.w r0, r1, #2703360 ; 0x294000 +0[0-9a-f]+ <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 ; 0x14a000 +0[0-9a-f]+ <[^>]+> f441 2025 orr\.w r0, r1, #675840 ; 0xa5000 +0[0-9a-f]+ <[^>]+> f441 20a5 orr\.w r0, r1, #337920 ; 0x52800 +0[0-9a-f]+ <[^>]+> f441 3025 orr\.w r0, r1, #168960 ; 0x29400 +0[0-9a-f]+ <[^>]+> f441 30a5 orr\.w r0, r1, #84480 ; 0x14a00 +0[0-9a-f]+ <[^>]+> f441 4025 orr\.w r0, r1, #42240 ; 0xa500 +0[0-9a-f]+ <[^>]+> f441 40a5 orr\.w r0, r1, #21120 ; 0x5280 +0[0-9a-f]+ <[^>]+> f441 5025 orr\.w r0, r1, #10560 ; 0x2940 +0[0-9a-f]+ <[^>]+> f441 50a5 orr\.w r0, r1, #5280 ; 0x14a0 +0[0-9a-f]+ <[^>]+> f441 6025 orr\.w r0, r1, #2640 ; 0xa50 +0[0-9a-f]+ <[^>]+> f441 60a5 orr\.w r0, r1, #1320 ; 0x528 +0[0-9a-f]+ <[^>]+> f441 7025 orr\.w r0, r1, #660 ; 0x294 +0[0-9a-f]+ <[^>]+> f441 70a5 orr\.w r0, r1, #330 ; 0x14a +0[0-9a-f]+ <[^>]+> 3000 adds r0, #0 +0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0 +0[0-9a-f]+ <[^>]+> 1c28 adds r0, r5, #0 +0[0-9a-f]+ <[^>]+> 1d50 adds r0, r2, #5 +0[0-9a-f]+ <[^>]+> 3081 adds r0, #129.* +0[0-9a-f]+ <[^>]+> 3081 adds r0, #129.* +0[0-9a-f]+ <[^>]+> 357e adds r5, #126.* +0[0-9a-f]+ <[^>]+> 1800 adds r0, r0, r0 +0[0-9a-f]+ <[^>]+> 1805 adds r5, r0, r0 +0[0-9a-f]+ <[^>]+> 1828 adds r0, r5, r0 +0[0-9a-f]+ <[^>]+> 1940 adds r0, r0, r5 +0[0-9a-f]+ <[^>]+> 18d1 adds r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4480 add r8, r0 +0[0-9a-f]+ <[^>]+> 4440 add r0, r8 +0[0-9a-f]+ <[^>]+> 4440 add r0, r8 +0[0-9a-f]+ <[^>]+> 4440 add r0, r8 +0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0 +0[0-9a-f]+ <[^>]+> 4401 add r1, r0 +0[0-9a-f]+ <[^>]+> 4408 add r0, r1 +0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 ; \(adr r0, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 ; \(adr r5, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 ; \(adr r0, [0-9a-f]+ <[^>]+>\) +0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0 +0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0 +0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516.* +0[0-9a-f]+ <[^>]+> b000 add sp, #0 +0[0-9a-f]+ <[^>]+> b000 add sp, #0 +0[0-9a-f]+ <[^>]+> b041 add sp, #260.* +0[0-9a-f]+ <[^>]+> f100 0000 add\.w r0, r0, #0 +0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0 +0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0 +0[0-9a-f]+ <[^>]+> f109 0000 add\.w r0, r9, #0 +0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 ; 0x10000 +0[0-9a-f]+ <[^>]+> f10d 0001 add\.w r0, sp, #1 +0[0-9a-f]+ <[^>]+> f10d 0900 add\.w r9, sp, #0 +0[0-9a-f]+ <[^>]+> f10d 0d04 add\.w sp, sp, #4 +0[0-9a-f]+ <[^>]+> eb00 0000 add\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> eb10 0000 adds\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> eb00 0900 add\.w r9, r0, r0 +0[0-9a-f]+ <[^>]+> eb09 0000 add\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> eb00 0009 add\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> eb09 080a add\.w r8, r9, sl +0[0-9a-f]+ <[^>]+> eb09 484a add\.w r8, r9, sl, lsl #17 +0[0-9a-f]+ <[^>]+> eb08 081a add\.w r8, r8, sl, lsr #32 +0[0-9a-f]+ <[^>]+> eb08 485a add\.w r8, r8, sl, lsr #17 +0[0-9a-f]+ <[^>]+> eb09 082a add\.w r8, r9, sl, asr #32 +0[0-9a-f]+ <[^>]+> eb09 486a add\.w r8, r9, sl, asr #17 +0[0-9a-f]+ <[^>]+> eb09 083a add\.w r8, r9, sl, rrx +0[0-9a-f]+ <[^>]+> eb09 487a add\.w r8, r9, sl, ror #17 +0[0-9a-f]+ <[^>]+> 3800 subs r0, #0 +0[0-9a-f]+ <[^>]+> 1e05 subs r5, r0, #0 +0[0-9a-f]+ <[^>]+> 1e28 subs r0, r5, #0 +0[0-9a-f]+ <[^>]+> 1f50 subs r0, r2, #5 +0[0-9a-f]+ <[^>]+> 3881 subs r0, #129.* +0[0-9a-f]+ <[^>]+> 3d08 subs r5, #8 +0[0-9a-f]+ <[^>]+> 1a00 subs r0, r0, r0 +0[0-9a-f]+ <[^>]+> 1a05 subs r5, r0, r0 +0[0-9a-f]+ <[^>]+> 1a28 subs r0, r5, r0 +0[0-9a-f]+ <[^>]+> 1b40 subs r0, r0, r5 +0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260.* +0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260.* +0[0-9a-f]+ <[^>]+> ebb8 0800 subs\.w r8, r8, r0 +0[0-9a-f]+ <[^>]+> ebb0 0008 subs\.w r0, r0, r8 +0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104 +0[0-9a-f]+ <[^>]+> f1b2 0104 subs\.w r1, r2, #4 +0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 ; 0x10000 +0[0-9a-f]+ <[^>]+> f1ad 0104 sub\.w r1, sp, #4 +0[0-9a-f]+ <[^>]+> f1ad 0900 sub\.w r9, sp, #0 +0[0-9a-f]+ <[^>]+> f1ad 0d04 sub\.w sp, sp, #4 +0[0-9a-f]+ <[^>]+> 4140 adcs r0, r0 +0[0-9a-f]+ <[^>]+> 4145 adcs r5, r0 +0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 +0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 +0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 +0[0-9a-f]+ <[^>]+> eb45 0000 adc\.w r0, r5, r0 +0[0-9a-f]+ <[^>]+> eb41 0002 adc\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> eb40 0900 adc\.w r9, r0, r0 +0[0-9a-f]+ <[^>]+> eb49 0000 adc\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> eb40 0009 adc\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> eb50 0000 adcs\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> eb41 4062 adc\.w r0, r1, r2, asr #17 +0[0-9a-f]+ <[^>]+> f141 0081 adc\.w r0, r1, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 4000 ands r0, r0 +0[0-9a-f]+ <[^>]+> 4005 ands r5, r0 +0[0-9a-f]+ <[^>]+> 4028 ands r0, r5 +0[0-9a-f]+ <[^>]+> 4028 ands r0, r5 +0[0-9a-f]+ <[^>]+> 4028 ands r0, r5 +0[0-9a-f]+ <[^>]+> ea05 0000 and\.w r0, r5, r0 +0[0-9a-f]+ <[^>]+> ea01 0002 and\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> ea00 0900 and\.w r9, r0, r0 +0[0-9a-f]+ <[^>]+> ea09 0000 and\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> ea00 0009 and\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> ea10 0000 ands\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> ea01 4062 and\.w r0, r1, r2, asr #17 +0[0-9a-f]+ <[^>]+> f001 0081 and\.w r0, r1, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 4380 bics r0, r0 +0[0-9a-f]+ <[^>]+> 4385 bics r5, r0 +0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5 +0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5 +0[0-9a-f]+ <[^>]+> ea35 0000 bics\.w r0, r5, r0 +0[0-9a-f]+ <[^>]+> ea25 0000 bic\.w r0, r5, r0 +0[0-9a-f]+ <[^>]+> ea21 0002 bic\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> ea20 0900 bic\.w r9, r0, r0 +0[0-9a-f]+ <[^>]+> ea29 0000 bic\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> ea20 0009 bic\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> ea30 0000 bics\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> ea21 4062 bic\.w r0, r1, r2, asr #17 +0[0-9a-f]+ <[^>]+> f021 0081 bic\.w r0, r1, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 4040 eors r0, r0 +0[0-9a-f]+ <[^>]+> 4045 eors r5, r0 +0[0-9a-f]+ <[^>]+> 4068 eors r0, r5 +0[0-9a-f]+ <[^>]+> 4068 eors r0, r5 +0[0-9a-f]+ <[^>]+> 4068 eors r0, r5 +0[0-9a-f]+ <[^>]+> ea85 0000 eor\.w r0, r5, r0 +0[0-9a-f]+ <[^>]+> ea81 0002 eor\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> ea80 0900 eor\.w r9, r0, r0 +0[0-9a-f]+ <[^>]+> ea89 0000 eor\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> ea80 0009 eor\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> ea90 0000 eors\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> ea81 4062 eor\.w r0, r1, r2, asr #17 +0[0-9a-f]+ <[^>]+> f081 0081 eor\.w r0, r1, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 4300 orrs r0, r0 +0[0-9a-f]+ <[^>]+> 4305 orrs r5, r0 +0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5 +0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5 +0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5 +0[0-9a-f]+ <[^>]+> ea45 0000 orr\.w r0, r5, r0 +0[0-9a-f]+ <[^>]+> ea41 0002 orr\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> ea40 0900 orr\.w r9, r0, r0 +0[0-9a-f]+ <[^>]+> ea49 0000 orr\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> ea40 0009 orr\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> ea50 0000 orrs\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> ea41 4062 orr\.w r0, r1, r2, asr #17 +0[0-9a-f]+ <[^>]+> f041 0081 orr\.w r0, r1, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0 +0[0-9a-f]+ <[^>]+> ebd5 0500 rsbs r5, r5, r0 +0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5 +0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5 +0[0-9a-f]+ <[^>]+> ebd5 0000 rsbs r0, r5, r0 +0[0-9a-f]+ <[^>]+> ebc5 0000 rsb r0, r5, r0 +0[0-9a-f]+ <[^>]+> ebc1 0002 rsb r0, r1, r2 +0[0-9a-f]+ <[^>]+> ebc0 0900 rsb r9, r0, r0 +0[0-9a-f]+ <[^>]+> ebc9 0000 rsb r0, r9, r0 +0[0-9a-f]+ <[^>]+> ebc0 0009 rsb r0, r0, r9 +0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0 +0[0-9a-f]+ <[^>]+> ebc1 4062 rsb r0, r1, r2, asr #17 +0[0-9a-f]+ <[^>]+> f1c1 0081 rsb r0, r1, #129 ; 0x81 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<[^>]+> d02a beq\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d1fc bne\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d128 bne\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d2fa bcs\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d226 bcs\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d2f8 bcs\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d224 bcs\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d3f6 bcc\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d322 bcc\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d3f4 bcc\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d320 bcc\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d3f2 bcc\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d31e bcc\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d4f0 bmi\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d41c bmi\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d5ee bpl\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d51a bpl\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d6ec bvs\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d618 bvs\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d7ea bvc\.n 0+2fe <[^>]+> +0[0-9a-f]+ <[^>]+> d716 bvc\.n 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> d8e8 bhi\.n 0+2fe <[^>]+> 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<[^>]+> f43f affe beq\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f000 8058 beq\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f47f affa bne\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f040 8054 bne\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f4bf aff6 bcs\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f080 8050 bcs\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f4bf aff2 bcs\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f080 804c bcs\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f4ff afee bcc\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f0c0 8048 bcc\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f4ff afea bcc\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f0c0 8044 bcc\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f4ff afe6 bcc\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f0c0 8040 bcc\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f53f afe2 bmi\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f100 803c bmi\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f57f afde bpl\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f140 8038 bpl\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f5bf afda bvs\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f180 8034 bvs\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f5ff afd6 bvc\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f1c0 8030 bvc\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f63f afd2 bhi\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f200 802c bhi\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f67f afce bls\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f240 8028 bls\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f5ff afca bvc\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f1c0 8024 bvc\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f63f afc6 bhi\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f200 8020 bhi\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f67f afc2 bls\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f240 801c bls\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f6bf afbe bge\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f280 8018 bge\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f6ff afba blt\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f2c0 8014 blt\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f73f afb6 bgt\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f300 8010 bgt\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f77f afb2 ble\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f340 800c ble\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f7ff bfae b\.w 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f000 b808 b\.w 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f7ff ffaa bl 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f000 f804 bl 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> f7ff efa6 blx 0+358 <[^>]+> +0[0-9a-f]+ <[^>]+> f000 e800 blx 0+410 <[^>]+> +0[0-9a-f]+ <[^>]+> 4748 bx r9 +0[0-9a-f]+ <[^>]+> 4780 blx r0 +0[0-9a-f]+ <[^>]+> 47c8 blx r9 +0[0-9a-f]+ <[^>]+> f3c0 8f00 bxj r0 +0[0-9a-f]+ <[^>]+> f3c9 8f00 bxj r9 +0[0-9a-f]+ <[^>]+> fab0 f080 clz r0, r0 +0[0-9a-f]+ <[^>]+> fab0 f980 clz r9, r0 +0[0-9a-f]+ <[^>]+> fab9 f089 clz r0, r9 +0[0-9a-f]+ <[^>]+> b661 cpsie f +0[0-9a-f]+ <[^>]+> b672 cpsid i +0[0-9a-f]+ <[^>]+> b664 cpsie a +0[0-9a-f]+ <[^>]+> f3af 8620 cpsid\.w f +0[0-9a-f]+ <[^>]+> f3af 8440 cpsie\.w i +0[0-9a-f]+ <[^>]+> f3af 8680 cpsid\.w a +0[0-9a-f]+ <[^>]+> f3af 8540 cpsie i, #0 +0[0-9a-f]+ <[^>]+> f3af 8751 cpsid i, #17 +0[0-9a-f]+ <[^>]+> f3af 8100 cps #0 +0[0-9a-f]+ <[^>]+> f3af 8111 cps #17 +0[0-9a-f]+ <[^>]+> 4600 mov r0, r0 +0[0-9a-f]+ <[^>]+> 4681 mov r9, r0 +0[0-9a-f]+ <[^>]+> 4648 mov r0, r9 +0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0 +0[0-9a-f]+ <[^>]+> ea4f 0900 mov\.w r9, r0 +0[0-9a-f]+ <[^>]+> ea4f 0009 mov\.w r0, r9 +0[0-9a-f]+ <[^>]+> b910 cbnz r0, 0+466 <[^>]+> +0[0-9a-f]+ <[^>]+> b105 cbz r5, 0+464 <[^>]+> +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf10 yield +0[0-9a-f]+ <[^>]+> bf20 wfe +0[0-9a-f]+ <[^>]+> bf30 wfi +0[0-9a-f]+ <[^>]+> bf40 sev +0[0-9a-f]+ <[^>]+> f3af 8000 nop\.w +0[0-9a-f]+ <[^>]+> f3af 8001 yield\.w +0[0-9a-f]+ <[^>]+> f3af 8002 wfe\.w +0[0-9a-f]+ <[^>]+> f3af 8003 wfi\.w +0[0-9a-f]+ <[^>]+> f3af 8004 sev\.w +0[0-9a-f]+ <[^>]+> bf90 nop \{9\} +0[0-9a-f]+ <[^>]+> f3af 8081 nop\.w \{129\}.* +0[0-9a-f]+ <[^>]+> bf08 it eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf18 it ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf28 it cs +0[0-9a-f]+ <[^>]+> bf00 nopcs +0[0-9a-f]+ <[^>]+> bf28 it cs +0[0-9a-f]+ <[^>]+> bf00 nopcs +0[0-9a-f]+ <[^>]+> bf38 it cc +0[0-9a-f]+ <[^>]+> bf00 nopcc +0[0-9a-f]+ <[^>]+> bf38 it cc +0[0-9a-f]+ <[^>]+> bf00 nopcc +0[0-9a-f]+ <[^>]+> bf38 it cc +0[0-9a-f]+ <[^>]+> bf00 nopcc +0[0-9a-f]+ <[^>]+> bf48 it mi +0[0-9a-f]+ <[^>]+> bf00 nopmi +0[0-9a-f]+ <[^>]+> bf58 it pl +0[0-9a-f]+ <[^>]+> bf00 noppl +0[0-9a-f]+ <[^>]+> bf68 it vs +0[0-9a-f]+ <[^>]+> bf00 nopvs +0[0-9a-f]+ <[^>]+> bf78 it vc +0[0-9a-f]+ <[^>]+> bf00 nopvc +0[0-9a-f]+ <[^>]+> bf88 it hi +0[0-9a-f]+ <[^>]+> bf00 nophi +0[0-9a-f]+ <[^>]+> bfa8 it ge +0[0-9a-f]+ <[^>]+> bf00 nopge +0[0-9a-f]+ <[^>]+> bfb8 it lt +0[0-9a-f]+ <[^>]+> bf00 noplt +0[0-9a-f]+ <[^>]+> bfc8 it gt +0[0-9a-f]+ <[^>]+> bf00 nopgt +0[0-9a-f]+ <[^>]+> bfd8 it le +0[0-9a-f]+ <[^>]+> bf00 nople +0[0-9a-f]+ <[^>]+> bfe8 it al +0[0-9a-f]+ <[^>]+> bf00 nopal +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf0c ite eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf02 ittt eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf0a itet eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf06 itte eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf0e itee eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf09 itett eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf05 ittet eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf03 ittte eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf07 ittee eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf0b itete eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf0d iteet eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf0f iteee eq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf1c itt ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf14 ite ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf1e ittt ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf16 itet ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf1a itte ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf12 itee ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf1f itttt ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf17 itett ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf1b ittet ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf1d ittte ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf19 ittee ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf15 itete ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf13 iteet ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf11 iteee ne +0[0-9a-f]+ <[^>]+> bf00 nopne +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> bf00 nopeq +0[0-9a-f]+ <[^>]+> f895 f000 pld \[r5\] +0[0-9a-f]+ <[^>]+> f895 f330 pld \[r5, #816\].* +0[0-9a-f]+ <[^>]+> f815 fc30 pld \[r5, #-48\].* +0[0-9a-f]+ <[^>]+> f815 fb30 pld \[r5\], #48.* +0[0-9a-f]+ <[^>]+> f815 f930 pld \[r5\], #-48.* +0[0-9a-f]+ <[^>]+> f815 ff30 pld \[r5, #48\]!.* +0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]!.* +0[0-9a-f]+ <[^>]+> f815 f004 pld \[r5, r4\] +0[0-9a-f]+ <[^>]+> f819 f00c pld \[r9, ip\] +0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] ; 0+5ee <[^>]+> +0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] ; 0+5c2 <[^>]+> +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\] +0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].* +0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] ; 000005f0 <here> +0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\] +0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].* +0[0-9a-f]+ <[^>]+> f815 1e00 ldrbt r1, \[r5\] +0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> f915 1e00 ldrsbt r1, \[r5\] +0[0-9a-f]+ <[^>]+> f915 1e30 ldrsbt r1, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> f835 1e00 ldrht r1, \[r5\] +0[0-9a-f]+ <[^>]+> f835 1e30 ldrht r1, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> f935 1e00 ldrsht r1, \[r5\] +0[0-9a-f]+ <[^>]+> f935 1e30 ldrsht r1, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> f855 1e00 ldrt r1, \[r5\] +0[0-9a-f]+ <[^>]+> f855 1e30 ldrt r1, \[r5, #48\].* +0[0-9a-f]+ <[^>]+> e8d4 1f4f ldrexb r1, \[r4\] +0[0-9a-f]+ <[^>]+> e8d4 1f5f ldrexh r1, \[r4\] +0[0-9a-f]+ <[^>]+> e854 1f00 ldrex r1, \[r4\] +0[0-9a-f]+ <[^>]+> e8d4 127f ldrexd r1, r2, \[r4\] +0[0-9a-f]+ <[^>]+> e8c4 2f41 strexb r1, r2, \[r4\] +0[0-9a-f]+ <[^>]+> e8c4 2f51 strexh r1, r2, \[r4\] +0[0-9a-f]+ <[^>]+> e844 2100 strex r1, r2, \[r4\] +0[0-9a-f]+ <[^>]+> e8c4 2371 strexd r1, r2, r3, \[r4\] +0[0-9a-f]+ <[^>]+> e8c4 3371 strexd r1, r3, r3, \[r4\] +0[0-9a-f]+ <[^>]+> e854 1f81 ldrex r1, \[r4, #516\].* +0[0-9a-f]+ <[^>]+> e844 2181 strex r1, r2, \[r4, #516\].* +0[0-9a-f]+ <[^>]+> c80e ldmia r0!, \{r1, r2, r3\} +0[0-9a-f]+ <[^>]+> ca07 ldmia r2, \{r0, r1, r2\} +0[0-9a-f]+ <[^>]+> e892 0007 ldmia\.w r2, \{r0, r1, r2\} +0[0-9a-f]+ <[^>]+> e899 0007 ldmia\.w r9, \{r0, r1, r2\} +0[0-9a-f]+ <[^>]+> e890 0580 ldmia\.w r0, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> e8b0 0580 ldmia\.w r0!, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> c00e stmia r0!, \{r1, r2, r3\} +0[0-9a-f]+ <[^>]+> c20b stmia r2!, \{r0, r1, r3\} +0[0-9a-f]+ <[^>]+> e8a2 000b stmia\.w r2!, \{r0, r1, r3\} +0[0-9a-f]+ <[^>]+> e889 0007 stmia\.w r9, \{r0, r1, r2\} +0[0-9a-f]+ <[^>]+> e880 0580 stmia\.w r0, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> e8a0 0580 stmia\.w r0!, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> e910 0580 ldmdb r0, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> e900 0580 stmdb r0, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> fb00 0000 mla r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb00 0010 mls r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb00 0900 mla r9, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb09 0000 mla r0, r9, r0, r0 +0[0-9a-f]+ <[^>]+> fb00 0009 mla r0, r0, r9, r0 +0[0-9a-f]+ <[^>]+> fb00 9000 mla r0, r0, r0, r9 +0[0-9a-f]+ <[^>]+> 4200 tst r0, r0 +0[0-9a-f]+ <[^>]+> 4200 tst r0, r0 +0[0-9a-f]+ <[^>]+> 4205 tst r5, r0 +0[0-9a-f]+ <[^>]+> 4228 tst r0, r5 +0[0-9a-f]+ <[^>]+> ea10 4f65 tst\.w r0, r5, asr #17 +0[0-9a-f]+ <[^>]+> ea10 0f00 tst\.w r0, r0 +0[0-9a-f]+ <[^>]+> ea19 0f00 tst\.w r9, r0 +0[0-9a-f]+ <[^>]+> ea10 0f09 tst\.w r0, r9 +0[0-9a-f]+ <[^>]+> f010 0f81 tst\.w r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f015 0f81 tst\.w r5, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0 +0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0 +0[0-9a-f]+ <[^>]+> ea95 0f00 teq r5, r0 +0[0-9a-f]+ <[^>]+> ea90 0f05 teq r0, r5 +0[0-9a-f]+ <[^>]+> ea90 4f65 teq r0, r5, asr #17 +0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0 +0[0-9a-f]+ <[^>]+> ea99 0f00 teq r9, r0 +0[0-9a-f]+ <[^>]+> ea90 0f09 teq r0, r9 +0[0-9a-f]+ <[^>]+> f090 0f81 teq r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f095 0f81 teq r5, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0 +0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0 +0[0-9a-f]+ <[^>]+> 4285 cmp r5, r0 +0[0-9a-f]+ <[^>]+> 42a8 cmp r0, r5 +0[0-9a-f]+ <[^>]+> ebb0 4f65 cmp\.w r0, r5, asr #17 +0[0-9a-f]+ <[^>]+> ebb0 0f00 cmp\.w r0, r0 +0[0-9a-f]+ <[^>]+> 4581 cmp r9, r0 +0[0-9a-f]+ <[^>]+> ebb0 0f09 cmp\.w r0, r9 +0[0-9a-f]+ <[^>]+> f1b0 0f81 cmp\.w r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f1b5 0f81 cmp\.w r5, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0 +0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0 +0[0-9a-f]+ <[^>]+> 42c5 cmn r5, r0 +0[0-9a-f]+ <[^>]+> 42e8 cmn r0, r5 +0[0-9a-f]+ <[^>]+> eb10 4f65 cmn\.w r0, r5, asr #17 +0[0-9a-f]+ <[^>]+> eb10 0f00 cmn\.w r0, r0 +0[0-9a-f]+ <[^>]+> eb19 0f00 cmn\.w r9, r0 +0[0-9a-f]+ <[^>]+> eb10 0f09 cmn\.w r0, r9 +0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 0000 movs r0, r0 +0[0-9a-f]+ <[^>]+> 4600 mov r0, r0 +0[0-9a-f]+ <[^>]+> 0005 movs r5, r0 +0[0-9a-f]+ <[^>]+> 4628 mov r0, r5 +0[0-9a-f]+ <[^>]+> ea4f 4065 mov\.w r0, r5, asr #17 +0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0 +0[0-9a-f]+ <[^>]+> ea5f 0900 movs\.w r9, r0 +0[0-9a-f]+ <[^>]+> ea5f 0009 movs\.w r0, r9 +0[0-9a-f]+ <[^>]+> f04f 0081 mov\.w r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f04f 0581 mov\.w r5, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> 43c0 mvns r0, r0 +0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0 +0[0-9a-f]+ <[^>]+> 43c5 mvns r5, r0 +0[0-9a-f]+ <[^>]+> ea6f 0005 mvn\.w r0, r5 +0[0-9a-f]+ <[^>]+> ea6f 4065 mvn\.w r0, r5, asr #17 +0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0 +0[0-9a-f]+ <[^>]+> ea7f 0900 mvns\.w r9, r0 +0[0-9a-f]+ <[^>]+> ea7f 0009 mvns\.w r0, r9 +0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 +0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 +0[0-9a-f]+ <[^>]+> f240 0900 movw r9, #0 +0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 ; 0x9000 +0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 ; 0x800 +0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 ; 0x500 +0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 ; 0x81 +0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 ; 0xffff +0[0-9a-f]+ <[^>]+> f3ef 8000 mrs r0, CPSR +0[0-9a-f]+ <[^>]+> f3ff 8000 mrs r0, SPSR +0[0-9a-f]+ <[^>]+> f3ef 8900 mrs r9, CPSR +0[0-9a-f]+ <[^>]+> f3ff 8900 mrs r9, SPSR +0[0-9a-f]+ <[^>]+> f380 8100 msr CPSR_c, r0 +0[0-9a-f]+ <[^>]+> f390 8100 msr SPSR_c, r0 +0[0-9a-f]+ <[^>]+> f389 8100 msr CPSR_c, r9 +0[0-9a-f]+ <[^>]+> f380 8200 msr CPSR_x, r0 +0[0-9a-f]+ <[^>]+> f380 8400 msr CPSR_s, r0 +0[0-9a-f]+ <[^>]+> f380 8800 msr CPSR_f, r0 +0[0-9a-f]+ <[^>]+> fb00 f000 mul\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb09 f000 mul\.w r0, r9, r0 +0[0-9a-f]+ <[^>]+> fb00 f009 mul\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> fb00 f000 mul\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb00 f909 mul\.w r9, r0, r9 +0[0-9a-f]+ <[^>]+> 4345 muls r5, r0 +0[0-9a-f]+ <[^>]+> 4345 muls r5, r0 +0[0-9a-f]+ <[^>]+> 4368 muls r0, r5 +0[0-9a-f]+ <[^>]+> fb80 0100 smull r0, r1, r0, r0 +0[0-9a-f]+ <[^>]+> fba0 0100 umull r0, r1, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0100 smlal r0, r1, r0, r0 +0[0-9a-f]+ <[^>]+> fbe0 0100 umlal r0, r1, r0, r0 +0[0-9a-f]+ <[^>]+> fb80 9000 smull r9, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb80 0900 smull r0, r9, r0, r0 +0[0-9a-f]+ <[^>]+> fb89 0100 smull r0, r1, r9, r0 +0[0-9a-f]+ <[^>]+> fb80 0109 smull r0, r1, r0, r9 +0[0-9a-f]+ <[^>]+> 4240 negs r0, r0 +0[0-9a-f]+ <[^>]+> 4268 negs r0, r5 +0[0-9a-f]+ <[^>]+> 4245 negs r5, r0 +0[0-9a-f]+ <[^>]+> f1d0 0000 rsbs r0, r0, #0 +0[0-9a-f]+ <[^>]+> f1d0 0500 rsbs r5, r0, #0 +0[0-9a-f]+ <[^>]+> f1d5 0000 rsbs r0, r5, #0 +0[0-9a-f]+ <[^>]+> f1c9 0000 rsb r0, r9, #0 +0[0-9a-f]+ <[^>]+> f1c0 0900 rsb r9, r0, #0 +0[0-9a-f]+ <[^>]+> f1d9 0000 rsbs r0, r9, #0 +0[0-9a-f]+ <[^>]+> f1d0 0900 rsbs r9, r0, #0 +0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0 +0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0 +0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0 +0[0-9a-f]+ <[^>]+> eac0 0009 pkhbt r0, r0, r9 +0[0-9a-f]+ <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20 +0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3 +0[0-9a-f]+ <[^>]+> eac3 0102 pkhbt r1, r3, r2 +0[0-9a-f]+ <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17 +0[0-9a-f]+ <[^>]+> b401 push \{r0\} +0[0-9a-f]+ <[^>]+> bc01 pop \{r0\} +0[0-9a-f]+ <[^>]+> b502 push \{r1, lr\} +0[0-9a-f]+ <[^>]+> bd02 pop \{r1, pc\} +0[0-9a-f]+ <[^>]+> e92d 1f00 stmdb sp!, \{r8, r9, sl, fp, ip\} +0[0-9a-f]+ <[^>]+> e8bd 1f00 ldmia\.w sp!, \{r8, r9, sl, fp, ip\} +0[0-9a-f]+ <[^>]+> fa83 f182 qadd r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f113 qasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa83 f192 qdadd r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa83 f1b2 qdsub r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa83 f1a2 qsub r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f113 qsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f103 sadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f103 sadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f103 sasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f103 ssub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f103 ssub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f103 ssax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f123 shadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f123 shadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f123 shasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f123 shsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f123 shsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f123 shsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f143 uadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f143 uadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f143 uasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f143 usub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f143 usub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f143 usax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f163 uhadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f163 uhadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f163 uhasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f163 uhsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f163 uhsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f163 uhsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa92 f153 uqadd16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa82 f153 uqadd8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f153 uqasx r1, r2, r3 +0[0-9a-f]+ <[^>]+> fad2 f153 uqsub16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fac2 f153 uqsub8 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> fae2 f153 uqsax r1, r2, r3 +0[0-9a-f]+ <[^>]+> faa2 f183 sel r1, r2, r3 +0[0-9a-f]+ <[^>]+> ba00 rev r0, r0 +0[0-9a-f]+ <[^>]+> fa90 f080 rev\.w r0, r0 +0[0-9a-f]+ <[^>]+> ba28 rev r0, r5 +0[0-9a-f]+ <[^>]+> ba05 rev r5, r0 +0[0-9a-f]+ <[^>]+> fa99 f089 rev\.w r0, r9 +0[0-9a-f]+ <[^>]+> fa90 f980 rev\.w r9, r0 +0[0-9a-f]+ <[^>]+> ba40 rev16 r0, r0 +0[0-9a-f]+ <[^>]+> fa90 f090 rev16\.w r0, r0 +0[0-9a-f]+ <[^>]+> ba68 rev16 r0, r5 +0[0-9a-f]+ <[^>]+> ba45 rev16 r5, r0 +0[0-9a-f]+ <[^>]+> fa99 f099 rev16\.w r0, r9 +0[0-9a-f]+ <[^>]+> fa90 f990 rev16\.w r9, r0 +0[0-9a-f]+ <[^>]+> bac0 revsh r0, r0 +0[0-9a-f]+ <[^>]+> fa90 f0b0 revsh\.w r0, r0 +0[0-9a-f]+ <[^>]+> bae8 revsh r0, r5 +0[0-9a-f]+ <[^>]+> bac5 revsh r5, r0 +0[0-9a-f]+ <[^>]+> fa99 f0b9 revsh\.w r0, r9 +0[0-9a-f]+ <[^>]+> fa90 f9b0 revsh\.w r9, r0 +0[0-9a-f]+ <[^>]+> fa90 f0a0 rbit r0, r0 +0[0-9a-f]+ <[^>]+> fa90 f0a0 rbit r0, r0 +0[0-9a-f]+ <[^>]+> fa95 f0a5 rbit r0, r5 +0[0-9a-f]+ <[^>]+> fa90 f5a0 rbit r5, r0 +0[0-9a-f]+ <[^>]+> fa99 f0a9 rbit r0, r9 +0[0-9a-f]+ <[^>]+> fa90 f9a0 rbit r9, r0 +0[0-9a-f]+ <[^>]+> 0440 lsls r0, r0, #17 +0[0-9a-f]+ <[^>]+> 0380 lsls r0, r0, #14 +0[0-9a-f]+ <[^>]+> 0445 lsls r5, r0, #17 +0[0-9a-f]+ <[^>]+> 03a8 lsls r0, r5, #14 +0[0-9a-f]+ <[^>]+> 4080 lsls r0, r0 +0[0-9a-f]+ <[^>]+> 40a8 lsls r0, r5 +0[0-9a-f]+ <[^>]+> 40a8 lsls r0, r5 +0[0-9a-f]+ <[^>]+> ea4f 4949 mov\.w r9, r9, lsl #17 +0[0-9a-f]+ <[^>]+> ea4f 3989 mov\.w r9, r9, lsl #14 +0[0-9a-f]+ <[^>]+> ea5f 4049 movs\.w r0, r9, lsl #17 +0[0-9a-f]+ <[^>]+> ea4f 3980 mov\.w r9, r0, lsl #14 +0[0-9a-f]+ <[^>]+> fa00 f000 lsl\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa09 f909 lsl\.w r9, r9, r9 +0[0-9a-f]+ <[^>]+> fa19 f900 lsls\.w r9, r9, r0 +0[0-9a-f]+ <[^>]+> fa00 f009 lsl\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> fa00 f005 lsl\.w r0, r0, r5 +0[0-9a-f]+ <[^>]+> fa11 f002 lsls\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> 0c40 lsrs r0, r0, #17 +0[0-9a-f]+ <[^>]+> 0b80 lsrs r0, r0, #14 +0[0-9a-f]+ <[^>]+> 0c45 lsrs r5, r0, #17 +0[0-9a-f]+ <[^>]+> 0ba8 lsrs r0, r5, #14 +0[0-9a-f]+ <[^>]+> 40c0 lsrs r0, r0 +0[0-9a-f]+ <[^>]+> 40e8 lsrs r0, r5 +0[0-9a-f]+ <[^>]+> 40e8 lsrs r0, r5 +0[0-9a-f]+ <[^>]+> ea4f 4959 mov\.w r9, r9, lsr #17 +0[0-9a-f]+ <[^>]+> ea4f 3999 mov\.w r9, r9, lsr #14 +0[0-9a-f]+ <[^>]+> ea5f 4059 movs\.w r0, r9, lsr #17 +0[0-9a-f]+ <[^>]+> ea4f 3990 mov\.w r9, r0, lsr #14 +0[0-9a-f]+ <[^>]+> fa20 f000 lsr\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa29 f909 lsr\.w r9, r9, r9 +0[0-9a-f]+ <[^>]+> fa39 f900 lsrs\.w r9, r9, r0 +0[0-9a-f]+ <[^>]+> fa20 f009 lsr\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> fa20 f005 lsr\.w r0, r0, r5 +0[0-9a-f]+ <[^>]+> fa31 f002 lsrs\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> 1440 asrs r0, r0, #17 +0[0-9a-f]+ <[^>]+> 1380 asrs r0, r0, #14 +0[0-9a-f]+ <[^>]+> 1445 asrs r5, r0, #17 +0[0-9a-f]+ <[^>]+> 13a8 asrs r0, r5, #14 +0[0-9a-f]+ <[^>]+> 4100 asrs r0, r0 +0[0-9a-f]+ <[^>]+> 4128 asrs r0, r5 +0[0-9a-f]+ <[^>]+> 4128 asrs r0, r5 +0[0-9a-f]+ <[^>]+> ea4f 4969 mov\.w r9, r9, asr #17 +0[0-9a-f]+ <[^>]+> ea4f 39a9 mov\.w r9, r9, asr #14 +0[0-9a-f]+ <[^>]+> ea5f 4069 movs\.w r0, r9, asr #17 +0[0-9a-f]+ <[^>]+> ea4f 39a0 mov\.w r9, r0, asr #14 +0[0-9a-f]+ <[^>]+> fa40 f000 asr\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa49 f909 asr\.w r9, r9, r9 +0[0-9a-f]+ <[^>]+> fa59 f900 asrs\.w r9, r9, r0 +0[0-9a-f]+ <[^>]+> fa40 f009 asr\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> fa40 f005 asr\.w r0, r0, r5 +0[0-9a-f]+ <[^>]+> fa51 f002 asrs\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> ea5f 4070 movs\.w r0, r0, ror #17 +0[0-9a-f]+ <[^>]+> ea5f 30b0 movs\.w r0, r0, ror #14 +0[0-9a-f]+ <[^>]+> ea5f 4570 movs\.w r5, r0, ror #17 +0[0-9a-f]+ <[^>]+> ea5f 30b5 movs\.w r0, r5, ror #14 +0[0-9a-f]+ <[^>]+> 41c0 rors r0, r0 +0[0-9a-f]+ <[^>]+> 41e8 rors r0, r5 +0[0-9a-f]+ <[^>]+> 41e8 rors r0, r5 +0[0-9a-f]+ <[^>]+> ea4f 4979 mov\.w r9, r9, ror #17 +0[0-9a-f]+ <[^>]+> ea4f 39b9 mov\.w r9, r9, ror #14 +0[0-9a-f]+ <[^>]+> ea5f 4079 movs\.w r0, r9, ror #17 +0[0-9a-f]+ <[^>]+> ea4f 39b0 mov\.w r9, r0, ror #14 +0[0-9a-f]+ <[^>]+> fa60 f000 ror\.w r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa69 f909 ror\.w r9, r9, r9 +0[0-9a-f]+ <[^>]+> fa79 f900 rors\.w r9, r9, r0 +0[0-9a-f]+ <[^>]+> fa60 f009 ror\.w r0, r0, r9 +0[0-9a-f]+ <[^>]+> fa60 f005 ror\.w r0, r0, r5 +0[0-9a-f]+ <[^>]+> fa71 f002 rors\.w r0, r1, r2 +0[0-9a-f]+ <[^>]+> ea4f 0132 mov.w r1, r2, rrx +0[0-9a-f]+ <[^>]+> ea5f 0334 movs.w r3, r4, rrx +0[0-9a-f]+ <[^>]+> f7f0 8000 smc #0 +0[0-9a-f]+ <[^>]+> f7fd 8bca smc #43981 ; 0xabcd +0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb19 0000 smlabb r0, r9, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0009 smlabb r0, r0, r9, r0 +0[0-9a-f]+ <[^>]+> fb10 9000 smlabb r0, r0, r0, r9 +0[0-9a-f]+ <[^>]+> fb10 0020 smlatb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0010 smlabt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 0030 smlatt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 0000 smlawb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 0010 smlawt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 0000 smlad r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 0010 smladx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 0000 smlsd r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 0010 smlsdx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 0000 smmla r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 0010 smmlar r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb60 0000 smmls r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb60 0010 smmlsr r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb70 0000 usada8 r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0080 smlalbb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 9080 smlalbb r9, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0980 smlalbb r0, r9, r0, r0 +0[0-9a-f]+ <[^>]+> fbc9 0080 smlalbb r0, r0, r9, r0 +0[0-9a-f]+ <[^>]+> fbc0 0089 smlalbb r0, r0, r0, r9 +0[0-9a-f]+ <[^>]+> fbc0 00a0 smlaltb r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 0090 smlalbt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 00b0 smlaltt r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 00c0 smlald r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbc0 00d0 smlaldx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbd0 00c0 smlsld r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbd0 00d0 smlsldx r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fbe0 0060 umaal r0, r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f000 smulbb r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f900 smulbb r9, r0, r0 +0[0-9a-f]+ <[^>]+> fb19 f000 smulbb r0, r9, r0 +0[0-9a-f]+ <[^>]+> fb10 f009 smulbb r0, r0, r9 +0[0-9a-f]+ <[^>]+> fb10 f020 smultb r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f010 smulbt r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb10 f030 smultt r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 f000 smulwb r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb30 f010 smulwt r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 f000 smmul r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb50 f010 smmulr r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 f000 smuad r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb20 f010 smuadx r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0 +0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0 +0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0 +0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0 +0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0 +0[0-9a-f]+ <[^>]+> f300 0900 ssat r9, #0, r0 +0[0-9a-f]+ <[^>]+> f300 0011 ssat r0, #17, r0 +0[0-9a-f]+ <[^>]+> f309 0000 ssat r0, #0, r9 +0[0-9a-f]+ <[^>]+> f300 7000 ssat r0, #0, r0, lsl #28 +0[0-9a-f]+ <[^>]+> f320 00c0 ssat r0, #0, r0, asr #3 +0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0 +0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0 +0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0 +0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9 +0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0 +0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0 +0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0 +0[0-9a-f]+ <[^>]+> f380 0900 usat r9, #0, r0 +0[0-9a-f]+ <[^>]+> f380 0011 usat r0, #17, r0 +0[0-9a-f]+ <[^>]+> f389 0000 usat r0, #0, r9 +0[0-9a-f]+ <[^>]+> f380 7000 usat r0, #0, r0, lsl #28 +0[0-9a-f]+ <[^>]+> f3a0 00c0 usat r0, #0, r0, asr #3 +0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0 +0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0 +0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0 +0[0-9a-f]+ <[^>]+> f3a9 0000 usat16 r0, #0, r9 +0[0-9a-f]+ <[^>]+> b240 sxtb r0, r0 +0[0-9a-f]+ <[^>]+> b240 sxtb r0, r0 +0[0-9a-f]+ <[^>]+> b245 sxtb r5, r0 +0[0-9a-f]+ <[^>]+> b268 sxtb r0, r5 +0[0-9a-f]+ <[^>]+> fa4f f182 sxtb\.w r1, r2 +0[0-9a-f]+ <[^>]+> fa4f f192 sxtb\.w r1, r2, ror #8 +0[0-9a-f]+ <[^>]+> fa4f f1a2 sxtb\.w r1, r2, ror #16 +0[0-9a-f]+ <[^>]+> fa4f f1b2 sxtb\.w r1, r2, ror #24 +0[0-9a-f]+ <[^>]+> fa2f f182 sxtb16 r1, r2 +0[0-9a-f]+ <[^>]+> fa2f f889 sxtb16 r8, r9 +0[0-9a-f]+ <[^>]+> b211 sxth r1, r2 +0[0-9a-f]+ <[^>]+> fa0f f889 sxth\.w r8, r9 +0[0-9a-f]+ <[^>]+> b2d1 uxtb r1, r2 +0[0-9a-f]+ <[^>]+> fa5f f889 uxtb\.w r8, r9 +0[0-9a-f]+ <[^>]+> fa3f f182 uxtb16 r1, r2 +0[0-9a-f]+ <[^>]+> fa3f f889 uxtb16 r8, r9 +0[0-9a-f]+ <[^>]+> b291 uxth r1, r2 +0[0-9a-f]+ <[^>]+> fa1f f889 uxth\.w r8, r9 +0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0 +0[0-9a-f]+ <[^>]+> fa40 f990 sxtab r9, r0, r0, ror #8 +0[0-9a-f]+ <[^>]+> fa49 f0a0 sxtab r0, r9, r0, ror #16 +0[0-9a-f]+ <[^>]+> fa40 f0b9 sxtab r0, r0, r9, ror #24 +0[0-9a-f]+ <[^>]+> fa22 f183 sxtab16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa02 f183 sxtah r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3 +0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] ; 0+e86 <[^>]+> +0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] ; 0+d35 <[^>]+> +0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] ; 0+93a <[^>]+> +0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] ; 0+a93 <[^>]+> +0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] ; 0+e96 <[^>]+> +0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] ; 0+d45 <[^>]+> +0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] ; 0+94a <[^>]+> +0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] ; 0+aa3 <[^>]+> +0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] ; 0+ea6 <[^>]+> +0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] ; 0+d55 <[^>]+> +0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] ; 0+95a <[^>]+> +0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] ; 0+ab3 <[^>]+> +0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] ; 0+eb6 <[^>]+> +0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] ; 0+d65 <[^>]+> +0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] ; 0+96a <[^>]+> +0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] ; 0+ac3 <[^>]+> +0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] ; 0+ec6 <[^>]+> +0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+d75 <[^>]+> +0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+97a <[^>]+> +0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+ad3 <[^>]+> +0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0 +0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 ; 0xfff +0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 ; 0xa85 +0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 ; 0x57a +0[0-9a-f]+ <[^>]+> e8df f006 tbb \[pc, r6\] +0[0-9a-f]+ <[^>]+> e8d0 f009 tbb \[r0, r9\] +0[0-9a-f]+ <[^>]+> e8df f017 tbh \[pc, r7, lsl #1\] +0[0-9a-f]+ <[^>]+> e8d0 f018 tbh \[r0, r8, lsl #1\] +0[0-9a-f]+ <[^>]+> f84d 8d04 str.w r8, \[sp, #-4\]! +0[0-9a-f]+ <[^>]+> f85d 8b04 ldr.w r8, \[sp\], #4 +0[0-9a-f]+ <[^>]+> e930 0580 ldmdb r0!, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> e920 0580 stmdb r0!, \{r7, r8, sl\} +0[0-9a-f]+ <[^>]+> c806 ldmia r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> c006 stmia r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> c806 ldmiaeq r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> c006 stmiaeq r0!, \{r1, r2\} +0[0-9a-f]+ <[^>]+> e890 0300 ldmiaeq.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> e880 0300 stmiaeq.w r0, \{r8, r9\} +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> e98d c010 srsia sp, #16 +0[0-9a-f]+ <[^>]+> e80d c010 srsdb sp, #16 +0[0-9a-f]+ <[^>]+> e9ad c015 srsia sp!, #21 +0[0-9a-f]+ <[^>]+> e9ad c00a srsia sp!, #10 +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3de 8f00 subs pc, lr, #0 +0[0-9a-f]+ <[^>]+> f3de 8f04 subs pc, lr, #4 +0[0-9a-f]+ <[^>]+> f3de 8fff subs pc, lr, #255.* +0[0-9a-f]+ <[^>]+> e9f9 240c ldrd r2, r4, \[r9, #48\]!.* +0[0-9a-f]+ <[^>]+> e979 240c ldrd r2, r4, \[r9, #-48\]!.* +0[0-9a-f]+ <[^>]+> e9e9 240c strd r2, r4, \[r9, #48\]!.* +0[0-9a-f]+ <[^>]+> e969 240c strd r2, r4, \[r9, #-48\]!.* +0[0-9a-f]+ <[^>]+> e8f9 240c ldrd r2, r4, \[r9\], #48.* +0[0-9a-f]+ <[^>]+> e879 240c ldrd r2, r4, \[r9\], #-48.* +0[0-9a-f]+ <[^>]+> e8e9 240c strd r2, r4, \[r9\], #48.* +0[0-9a-f]+ <[^>]+> e869 240c strd r2, r4, \[r9\], #-48.* +0[0-9a-f]+ <[^>]+> f8d5 1301 ldr.w r1, \[r5, #769].* +0[0-9a-f]+ <[^>]+> f855 1f30 ldr.w r1, \[r5, #48]!.* +0[0-9a-f]+ <[^>]+> f855 1d30 ldr.w r1, \[r5, #-48]!.* +0[0-9a-f]+ <[^>]+> f855 1b30 ldr.w r1, \[r5\], #48.* +0[0-9a-f]+ <[^>]+> f855 1930 ldr.w r1, \[r5\], #-48.* +0[0-9a-f]+ <[^>]+> f855 1009 ldr.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f895 1301 ldrb.w r1, \[r5, #769].* +0[0-9a-f]+ <[^>]+> f815 1f30 ldrb.w r1, \[r5, #48]!.* +0[0-9a-f]+ <[^>]+> f815 1d30 ldrb.w r1, \[r5, #-48]!.* +0[0-9a-f]+ <[^>]+> f815 1b30 ldrb.w r1, \[r5\], #48.* +0[0-9a-f]+ <[^>]+> f815 1930 ldrb.w r1, \[r5\], #-48.* +0[0-9a-f]+ <[^>]+> f815 1009 ldrb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f995 1301 ldrsb.w r1, \[r5, #769].* +0[0-9a-f]+ <[^>]+> f915 1f30 ldrsb.w r1, \[r5, #48]!.* +0[0-9a-f]+ <[^>]+> f915 1d30 ldrsb.w r1, \[r5, #-48]!.* +0[0-9a-f]+ <[^>]+> f915 1b30 ldrsb.w r1, \[r5\], #48.* +0[0-9a-f]+ <[^>]+> f915 1930 ldrsb.w r1, \[r5\], #-48.* +0[0-9a-f]+ <[^>]+> f915 1009 ldrsb.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f8b5 1301 ldrh.w r1, \[r5, #769].* +0[0-9a-f]+ <[^>]+> f835 1f30 ldrh.w r1, \[r5, #48]!.* +0[0-9a-f]+ <[^>]+> f835 1d30 ldrh.w r1, \[r5, #-48]!.* +0[0-9a-f]+ <[^>]+> f835 1b30 ldrh.w r1, \[r5\], #48.* +0[0-9a-f]+ <[^>]+> f835 1930 ldrh.w r1, \[r5\], #-48.* +0[0-9a-f]+ <[^>]+> f835 1009 ldrh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> f9b5 1301 ldrsh.w r1, \[r5, #769].* +0[0-9a-f]+ <[^>]+> f935 1f30 ldrsh.w r1, \[r5, #48]!.* +0[0-9a-f]+ <[^>]+> f935 1d30 ldrsh.w r1, \[r5, #-48]!.* +0[0-9a-f]+ <[^>]+> f935 1b30 ldrsh.w r1, \[r5\], #48.* +0[0-9a-f]+ <[^>]+> f935 1930 ldrsh.w r1, \[r5\], #-48.* +0[0-9a-f]+ <[^>]+> f935 1009 ldrsh.w r1, \[r5, r9\] +0[0-9a-f]+ <[^>]+> 00a1 lsls r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 0389 movs.w r3, r9, lsl #2 +0[0-9a-f]+ <[^>]+> fa12 f103 lsls.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4099 lsls r1, r3 +0[0-9a-f]+ <[^>]+> fa11 f109 lsls.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa02 f103 lsl.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa01 f103 lsl.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> 08a1 lsrs r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 0399 movs.w r3, r9, lsr #2 +0[0-9a-f]+ <[^>]+> fa32 f103 lsrs.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 40d9 lsrs r1, r3 +0[0-9a-f]+ <[^>]+> fa31 f109 lsrs.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa22 f103 lsr.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa21 f103 lsr.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> 10a1 asrs r1, r4, #2 +0[0-9a-f]+ <[^>]+> ea5f 03a9 movs.w r3, r9, asr #2 +0[0-9a-f]+ <[^>]+> fa52 f103 asrs.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 4119 asrs r1, r3 +0[0-9a-f]+ <[^>]+> fa51 f109 asrs.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa42 f103 asr.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa41 f103 asr.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> ea5f 01b4 movs.w r1, r4, ror #2 +0[0-9a-f]+ <[^>]+> ea5f 03b9 movs.w r3, r9, ror #2 +0[0-9a-f]+ <[^>]+> fa72 f103 rors.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> 41d9 rors r1, r3 +0[0-9a-f]+ <[^>]+> fa71 f109 rors.w r1, r1, r9 +0[0-9a-f]+ <[^>]+> fa62 f103 ror.w r1, r2, r3 +0[0-9a-f]+ <[^>]+> fa61 f103 ror.w r1, r1, r3 +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb32.l b/binutils-2.25/gas/testsuite/gas/arm/thumb32.l new file mode 100644 index 00000000..d2860e3e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb32.l @@ -0,0 +1,17 @@ +[^;]*: Assembler messages: +[^;]*:450: Warning: s suffix on comparison instruction is deprecated +[^;]*:450: Warning: s suffix on comparison instruction is deprecated +[^;]*:450: Warning: s suffix on comparison instruction is deprecated +[^;]*:450: Warning: s suffix on comparison instruction is deprecated +[^;]*:451: Warning: s suffix on comparison instruction is deprecated +[^;]*:451: Warning: s suffix on comparison instruction is deprecated +[^;]*:451: Warning: s suffix on comparison instruction is deprecated +[^;]*:451: Warning: s suffix on comparison instruction is deprecated +[^;]*:452: Warning: s suffix on comparison instruction is deprecated +[^;]*:452: Warning: s suffix on comparison instruction is deprecated +[^;]*:452: Warning: s suffix on comparison instruction is deprecated +[^;]*:452: Warning: s suffix on comparison instruction is deprecated +[^;]*:453: Warning: s suffix on comparison instruction is deprecated +[^;]*:453: Warning: s suffix on comparison instruction is deprecated +[^;]*:453: Warning: s suffix on comparison instruction is deprecated +[^;]*:453: Warning: s suffix on comparison instruction is deprecated diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb32.s b/binutils-2.25/gas/testsuite/gas/arm/thumb32.s new file mode 100644 index 00000000..d6dbdd65 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb32.s @@ -0,0 +1,845 @@ + .text + .thumb + .syntax unified + +encode_thumb32_immediate: + orr r0, r1, #0x00000000 + orr r0, r1, #0x000000a5 + orr r0, r1, #0x00a500a5 + orr r0, r1, #0xa500a500 + orr r0, r1, #0xa5a5a5a5 + + orr r0, r1, #0xa5 << 31 + orr r0, r1, #0xa5 << 30 + orr r0, r1, #0xa5 << 29 + orr r0, r1, #0xa5 << 28 + orr r0, r1, #0xa5 << 27 + orr r0, r1, #0xa5 << 26 + orr r0, r1, #0xa5 << 25 + orr r0, r1, #0xa5 << 24 + orr r0, r1, #0xa5 << 23 + orr r0, r1, #0xa5 << 22 + orr r0, r1, #0xa5 << 21 + orr r0, r1, #0xa5 << 20 + orr r0, r1, #0xa5 << 19 + orr r0, r1, #0xa5 << 18 + orr r0, r1, #0xa5 << 17 + orr r0, r1, #0xa5 << 16 + orr r0, r1, #0xa5 << 15 + orr r0, r1, #0xa5 << 14 + orr r0, r1, #0xa5 << 13 + orr r0, r1, #0xa5 << 12 + orr r0, r1, #0xa5 << 11 + orr r0, r1, #0xa5 << 10 + orr r0, r1, #0xa5 << 9 + orr r0, r1, #0xa5 << 8 + orr r0, r1, #0xa5 << 7 + orr r0, r1, #0xa5 << 6 + orr r0, r1, #0xa5 << 5 + orr r0, r1, #0xa5 << 4 + orr r0, r1, #0xa5 << 3 + orr r0, r1, #0xa5 << 2 + orr r0, r1, #0xa5 << 1 + +add_sub: + @ Should be format 1, Some have equivalent format 2 encodings + adds r0, r0, #0 + adds r5, r0, #0 + adds r0, r5, #0 + adds r0, r2, #5 + + adds r0, #129 @ format 2 + adds r0, r0, #129 + adds r5, #126 + + adds r0, r0, r0 @ format 3 + adds r5, r0, r0 + adds r0, r5, r0 + adds r0, r0, r5 + adds r1, r2, r3 + + add r8, r0 @ format 4 + add r0, r8 + add r0, r8, r0 + add r0, r0, r8 + add r8, r0, r0 @ ... not this one + + add r1, r0 + add r0, r1 + + add r0, pc, #0 @ format 5 + add r5, pc, #0 + add r0, pc, #516 + + add r0, sp, #0 @ format 6 + add r5, sp, #0 + add r0, sp, #516 + + add sp, #0 @ format 7 + add sp, sp, #0 + add sp, #260 + + add.w r0, r0, #0 @ T32 format 1 + adds.w r0, r0, #0 + add.w r9, r0, #0 + add.w r0, r9, #0 + add.w r0, r0, #129 + adds r5, r3, #0x10000 + add r0, sp, #1 + add r9, sp, #0 + add.w sp, sp, #4 + + add.w r0, r0, r0 @ T32 format 2 + adds.w r0, r0, r0 + add.w r9, r0, r0 + add.w r0, r9, r0 + add.w r0, r0, r9 + + add.w r8, r9, r10 + add.w r8, r9, r10, lsl #17 + add.w r8, r8, r10, lsr #32 + add.w r8, r8, r10, lsr #17 + add.w r8, r9, r10, asr #32 + add.w r8, r9, r10, asr #17 + add.w r8, r9, r10, rrx + add.w r8, r9, r10, ror #17 + + subs r0, r0, #0 @ format 1 + subs r5, r0, #0 + subs r0, r5, #0 + subs r0, r2, #5 + + subs r0, r0, #129 + subs r5, #8 + + subs r0, r0, r0 @ format 3 + subs r5, r0, r0 + subs r0, r5, r0 + subs r0, r0, r5 + + sub sp, #260 @ format 4 + sub sp, sp, #260 + + subs r8, r0 @ T32 format 2 + subs r0, r8 + subs r0, #260 @ T32 format 1 + subs.w r1, r2, #4 + subs r5, r3, #0x10000 + sub r1, sp, #4 + sub r9, sp, #0 + sub.w sp, sp, #4 + +arit3: + .macro arit3 op ops opw opsw + \ops r0, r0 + \ops r5, r0 + \ops r0, r5 + \ops r0, r0, r5 + \ops r0, r5, r0 + \op r0, r5, r0 + \op r0, r1, r2 + \op r9, r0, r0 + \op r0, r9, r0 + \op r0, r0, r9 + \opsw r0, r0, r0 + \opw r0, r1, r2, asr #17 + \opw r0, r1, #129 + .endm + + arit3 adc adcs adc.w adcs.w + arit3 and ands and.w ands.w + arit3 bic bics bic.w bics.w + arit3 eor eors eor.w eors.w + arit3 orr orrs orr.w orrs.w + arit3 rsb rsbs rsb.w rsbs.w + arit3 sbc sbcs sbc.w sbcs.w + arit3 orn orns orn orns + + .purgem arit3 + +bfc_bfi_bfx: + bfc r0, #0, #1 + bfc r9, #0, #1 + bfi r9, #0, #0, #1 + bfc r0, #21, #1 + bfc r0, #0, #18 + + bfi r0, r0, #0, #1 + bfi r9, r0, #0, #1 + bfi r0, r9, #0, #1 + bfi r0, r0, #21, #1 + bfi r0, r0, #0, #18 + + sbfx r0, r0, #0, #1 + ubfx r9, r0, #0, #1 + sbfx r0, r9, #0, #1 + ubfx r0, r0, #21, #1 + sbfx r0, r0, #0, #18 + + .globl branches +branches: + .macro bra op + \op 1b + \op 1f + .endm +1: + bra beq.n + bra bne.n + bra bcs.n + bra bhs.n + bra bcc.n + bra bul.n + bra blo.n + bra bmi.n + bra bpl.n + bra bvs.n + bra bvc.n + bra bhi.n + bra bls.n + bra bvc.n + bra bhi.n + bra bls.n + bra bge.n + bra blt.n + bra bgt.n + bra ble.n + bra bal.n + bra b.n + @ bl, blx have no short form. + .balign 4 +1: + bra beq.w + bra bne.w + bra bcs.w + bra bhs.w + bra bcc.w + bra bul.w + bra blo.w + bra bmi.w + bra bpl.w + bra bvs.w + bra bvc.w + bra bhi.w + bra bls.w + bra bvc.w + bra bhi.w + bra bls.w + bra bge.w + bra blt.w + bra bgt.w + bra ble.w + bra b.w + bra bl + bra blx + .balign 4 +1: + bx r9 + blx r0 + blx r9 + bxj r0 + bxj r9 + .purgem bra + +clz: + clz r0, r0 + clz r9, r0 + clz r0, r9 + +cps: + cpsie f + cpsid i + cpsie a + cpsid.w f + cpsie.w i + cpsid.w a + cpsie i, #0 + cpsid i, #17 + cps #0 + cps #17 + +cpy: + cpy r0, r0 + cpy r9, r0 + cpy r0, r9 + cpy.w r0, r0 + cpy.w r9, r0 + cpy.w r0, r9 + +czb: + cbnz r0, 2f + cbz r5, 1f + +nop_hint: + nop +1: yield +2: wfe + wfi + sev + + nop.w + yield.w + wfe.w + wfi.w + sev.w + + nop {9} + nop {129} + +it: + .macro nop1 cond ncond a + .ifc \a,t + nop\cond + .else + nop\ncond + .endif + .endm + .macro it0 cond m= + it\m \cond + nop\cond + .endm + .macro it1 cond ncond a m= + it0 \cond \a\m + nop1 \cond \ncond \a + .endm + .macro it2 cond ncond a b m= + it1 \cond \ncond \a \b\m + nop1 \cond \ncond \b + .endm + .macro it3 cond ncond a b c + it2 \cond \ncond \a \b \c + nop1 \cond \ncond \c + .endm + + it0 eq + it0 ne + it0 cs + it0 hs + it0 cc + it0 ul + it0 lo + it0 mi + it0 pl + it0 vs + it0 vc + it0 hi + it0 ge + it0 lt + it0 gt + it0 le + it0 al + it1 eq ne t + it1 eq ne e + it2 eq ne t t + it2 eq ne e t + it2 eq ne t e + it2 eq ne e e + it3 eq ne t t t + it3 eq ne e t t + it3 eq ne t e t + it3 eq ne t t e + it3 eq ne t e e + it3 eq ne e t e + it3 eq ne e e t + it3 eq ne e e e + + it1 ne eq t + it1 ne eq e + it2 ne eq t t + it2 ne eq e t + it2 ne eq t e + it2 ne eq e e + it3 ne eq t t t + it3 ne eq e t t + it3 ne eq t e t + it3 ne eq t t e + it3 ne eq t e e + it3 ne eq e t e + it3 ne eq e e t + it3 ne eq e e e + +ldst: +1: + pld [r5] + pld [r5, #0x330] + pld [r5, #-0x30] + pld [r5], #0x30 + pld [r5], #-0x30 + pld [r5, #0x30]! + pld [r5, #-0x30]! + pld [r5, r4] + pld [r9, ip] + pld 1f + pld 1b +1: + nop +here: + ldrd r2, r3, [r5] + ldrd r2, [r5, #0x30] + ldrd r2, [r5, #-0x30] + ldrd r4, r5, here + strd r2, r3, [r5] + strd r2, [r5, #0x30] + strd r2, [r5, #-0x30] + + ldrbt r1, [r5] + ldrbt r1, [r5, #0x30] + ldrsbt r1, [r5] + ldrsbt r1, [r5, #0x30] + ldrht r1, [r5] + ldrht r1, [r5, #0x30] + ldrsht r1, [r5] + ldrsht r1, [r5, #0x30] + ldrt r1, [r5] + ldrt r1, [r5, #0x30] + +ldxstx: + ldrexb r1, [r4] + ldrexh r1, [r4] + ldrex r1, [r4] + ldrexd r1, r2, [r4] + + strexb r1, r2, [r4] + strexh r1, r2, [r4] + strex r1, r2, [r4] + strexd r1, r2, r3, [r4] + strexd r1, r3, r3, [r4] + + ldrex r1, [r4,#516] + strex r1, r2, [r4,#516] + +ldmstm: + ldmia r0!, {r1,r2,r3} + ldmia r2, {r0,r1,r2} + ldmia.w r2, {r0,r1,r2} + ldmia r9, {r0,r1,r2} + ldmia r0, {r7,r8,r10} + ldmia r0!, {r7,r8,r10} + + stmia r0!, {r1,r2,r3} + stmia r2!, {r0,r1,r3} + stmia.w r2!, {r0,r1,r3} + stmia r9, {r0,r1,r2} + stmia r0, {r7,r8,r10} + stmia r0!, {r7,r8,r10} + + ldmdb r0, {r7,r8,r10} + stmdb r0, {r7,r8,r10} + +mlas: + mla r0, r0, r0, r0 + mls r0, r0, r0, r0 + mla r9, r0, r0, r0 + mla r0, r9, r0, r0 + mla r0, r0, r9, r0 + mla r0, r0, r0, r9 + +tst_teq_cmp_cmn_mov_mvn: + .macro mt op ops opw opsw + \ops r0, r0 + \op r0, r0 + \ops r5, r0 + \op r0, r5 + \op r0, r5, asr #17 + \opw r0, r0 + \ops r9, r0 + \opsw r0, r9 + \opw r0, #129 + \opw r5, #129 + .endm + + mt tst tsts tst.w tsts.w + mt teq teqs teq.w teqs.w + mt cmp cmps cmp.w cmps.w + mt cmn cmns cmn.w cmns.w + mt mov movs mov.w movs.w + mt mvn mvns mvn.w mvns.w + .purgem mt + +mov16: + movw r0, #0 + movt r0, #0 + movw r9, #0 + movw r0, #0x9000 + movw r0, #0x0800 + movw r0, #0x0500 + movw r0, #0x0081 + movw r0, #0xffff + +mrs_msr: + mrs r0, CPSR + mrs r0, SPSR + mrs r9, CPSR_all + mrs r9, SPSR_all + + msr CPSR_c, r0 + msr SPSR_c, r0 + msr CPSR_c, r9 + msr CPSR_x, r0 + msr CPSR_s, r0 + msr CPSR_f, r0 + +mul: + mul r0, r0, r0 + mul r0, r9, r0 + mul r0, r0, r9 + mul r0, r0 + mul r9, r0 + muls r5, r0 + muls r5, r0, r5 + muls r0, r5 + +mull: + smull r0, r1, r0, r0 + umull r0, r1, r0, r0 + smlal r0, r1, r0, r0 + umlal r0, r1, r0, r0 + smull r9, r0, r0, r0 + smull r0, r9, r0, r0 + smull r0, r1, r9, r0 + smull r0, r1, r0, r9 + +neg: + negs r0, r0 + negs r0, r5 + negs r5, r0 + negs.w r0, r0 + negs.w r5, r0 + negs.w r0, r5 + + neg r0, r9 + neg r9, r0 + negs r0, r9 + negs r9, r0 + +pkh: + pkhbt r0, r0, r0 + pkhbt r9, r0, r0 + pkhbt r0, r9, r0 + pkhbt r0, r0, r9 + pkhbt r0, r0, r0, lsl #0x14 + pkhbt r0, r0, r0, lsl #3 + pkhtb r1, r2, r3 + pkhtb r1, r2, r3, asr #0x11 + +push_pop: + push {r0} + pop {r0} + push {r1,lr} + pop {r1,pc} + push {r8,r9,r10,r11,r12} + pop {r8,r9,r10,r11,r12} + +qadd: + qadd r1, r2, r3 + qadd16 r1, r2, r3 + qadd8 r1, r2, r3 + qasx r1, r2, r3 + qaddsubx r1, r2, r3 + qdadd r1, r2, r3 + qdsub r1, r2, r3 + qsub r1, r2, r3 + qsub16 r1, r2, r3 + qsub8 r1, r2, r3 + qsax r1, r2, r3 + qsubaddx r1, r2, r3 + sadd16 r1, r2, r3 + sadd8 r1, r2, r3 + sasx r1, r2, r3 + saddsubx r1, r2, r3 + ssub16 r1, r2, r3 + ssub8 r1, r2, r3 + ssax r1, r2, r3 + ssubaddx r1, r2, r3 + shadd16 r1, r2, r3 + shadd8 r1, r2, r3 + shasx r1, r2, r3 + shaddsubx r1, r2, r3 + shsub16 r1, r2, r3 + shsub8 r1, r2, r3 + shsax r1, r2, r3 + shsubaddx r1, r2, r3 + uadd16 r1, r2, r3 + uadd8 r1, r2, r3 + uasx r1, r2, r3 + uaddsubx r1, r2, r3 + usub16 r1, r2, r3 + usub8 r1, r2, r3 + usax r1, r2, r3 + usubaddx r1, r2, r3 + uhadd16 r1, r2, r3 + uhadd8 r1, r2, r3 + uhasx r1, r2, r3 + uhaddsubx r1, r2, r3 + uhsub16 r1, r2, r3 + uhsub8 r1, r2, r3 + uhsax r1, r2, r3 + uhsubaddx r1, r2, r3 + uqadd16 r1, r2, r3 + uqadd8 r1, r2, r3 + uqasx r1, r2, r3 + uqaddsubx r1, r2, r3 + uqsub16 r1, r2, r3 + uqsub8 r1, r2, r3 + uqsax r1, r2, r3 + uqsubaddx r1, r2, r3 + sel r1, r2, r3 + +rbit_rev: + .macro rx op opw + \op r0, r0 + \opw r0, r0 + \op r0, r5 + \op r5, r0 + \op r0, r9 + \op r9, r0 + .endm + + rx rev rev.w + rx rev16 rev16.w + rx revsh revsh.w + rx rbit rbit.w + + .purgem rx + +shift: + .macro sh op ops opw opsw + \ops r0, #17 @ 16-bit format 1 + \ops r0, r0, #14 + \ops r5, r0, #17 + \ops r0, r5, #14 + \ops r0, r0 @ 16-bit format 2 + \ops r0, r5 + \ops r0, r0, r5 + \op r9, #17 @ 32-bit format 1 + \op r9, r9, #14 + \ops r0, r9, #17 + \op r9, r0, #14 + \opw r0, r0, r0 @ 32-bit format 2 + \op r9, r9 + \ops r9, r0 + \op r0, r9 + \op r0, r5 + \ops r0, r1, r2 + .endm + + sh lsl lsls lsl.w lsls.w + sh lsr lsrs lsr.w lsrs.w + sh asr asrs asr.w asrs.w + sh ror rors ror.w rors.w + + .purgem sh + +rrx: + rrx r1, r2 + rrxs r3, r4 + + .arch armv7-a + .arch_extension sec +smc: + smc #0 + smc #0xabcd + +smla: + smlabb r0, r0, r0, r0 + smlabb r9, r0, r0, r0 + smlabb r0, r9, r0, r0 + smlabb r0, r0, r9, r0 + smlabb r0, r0, r0, r9 + + smlatb r0, r0, r0, r0 + smlabt r0, r0, r0, r0 + smlatt r0, r0, r0, r0 + smlawb r0, r0, r0, r0 + smlawt r0, r0, r0, r0 + smlad r0, r0, r0, r0 + smladx r0, r0, r0, r0 + smlsd r0, r0, r0, r0 + smlsdx r0, r0, r0, r0 + smmla r0, r0, r0, r0 + smmlar r0, r0, r0, r0 + smmls r0, r0, r0, r0 + smmlsr r0, r0, r0, r0 + usada8 r0, r0, r0, r0 + +smlal: + smlalbb r0, r0, r0, r0 + smlalbb r9, r0, r0, r0 + smlalbb r0, r9, r0, r0 + smlalbb r0, r0, r9, r0 + smlalbb r0, r0, r0, r9 + + smlaltb r0, r0, r0, r0 + smlalbt r0, r0, r0, r0 + smlaltt r0, r0, r0, r0 + smlald r0, r0, r0, r0 + smlaldx r0, r0, r0, r0 + smlsld r0, r0, r0, r0 + smlsldx r0, r0, r0, r0 + umaal r0, r0, r0, r0 + +smul: + smulbb r0, r0, r0 + smulbb r9, r0, r0 + smulbb r0, r9, r0 + smulbb r0, r0, r9 + + smultb r0, r0, r0 + smulbt r0, r0, r0 + smultt r0, r0, r0 + smulwb r0, r0, r0 + smulwt r0, r0, r0 + smmul r0, r0, r0 + smmulr r0, r0, r0 + smuad r0, r0, r0 + smuadx r0, r0, r0 + smusd r0, r0, r0 + smusdx r0, r0, r0 + usad8 r0, r0, r0 + +sat: + ssat r0, #1, r0 + ssat r0, #1, r0, lsl #0 + ssat r0, #1, r0, asr #0 + ssat r9, #1, r0 + ssat r0, #18, r0 + ssat r0, #1, r9 + ssat r0, #1, r0, lsl #0x1c + ssat r0, #1, r0, asr #0x03 + + ssat16 r0, #1, r0 + ssat16 r9, #1, r0 + ssat16 r0, #10, r0 + ssat16 r0, #1, r9 + + usat r0, #0, r0 + usat r0, #0, r0, lsl #0 + usat r0, #0, r0, asr #0 + usat r9, #0, r0 + usat r0, #17, r0 + usat r0, #0, r9 + usat r0, #0, r0, lsl #0x1c + usat r0, #0, r0, asr #0x03 + + usat16 r0, #0, r0 + usat16 r9, #0, r0 + usat16 r0, #9, r0 + usat16 r0, #0, r9 + +xt: + sxtb r0, r0 + sxtb r0, r0, ror #0 + sxtb r5, r0 + sxtb r0, r5 + sxtb.w r1, r2 + sxtb r1, r2, ror #8 + sxtb r1, r2, ror #16 + sxtb r1, r2, ror #24 + + sxtb16 r1, r2 + sxtb16 r8, r9 + sxth r1, r2 + sxth r8, r9 + uxtb r1, r2 + uxtb r8, r9 + uxtb16 r1, r2 + uxtb16 r8, r9 + uxth r1, r2 + uxth r8, r9 + +xta: + sxtab r0, r0, r0 + sxtab r0, r0, r0, ror #0 + sxtab r9, r0, r0, ror #8 + sxtab r0, r9, r0, ror #16 + sxtab r0, r0, r9, ror #24 + + sxtab16 r1, r2, r3 + sxtah r1, r2, r3 + uxtab r1, r2, r3 + uxtab16 r1, r2, r3 + uxtah r1, r2, r3 + + .macro ldpcimm op + \op r1, [pc, #0x2aa] + \op r1, [pc, #0x155] + \op r1, [pc, #-0x2aa] + \op r1, [pc, #-0x155] + .endm + ldpcimm ldrb + ldpcimm ldrsb + ldpcimm ldrh + ldpcimm ldrsh + ldpcimm ldr + addw r9, r0, #0 + addw r6, pc, #0xfff + subw r6, r9, #0xa85 + subw r6, r9, #0x57a + tbb [pc, r6] + tbb [r0, r9] + tbh [pc, r7, lsl #1] + tbh [r0, r8, lsl #1] + + push {r8} + pop {r8} + + ldmdb r0!, {r7,r8,r10} + stmdb r0!, {r7,r8,r10} + + ldm r0!, {r1, r2} + stm r0!, {r1, r2} + ldm r0, {r8, r9} + stm r0, {r8, r9} + itttt eq + ldmeq r0!, {r1, r2} + stmeq r0!, {r1, r2} + ldmeq r0, {r8, r9} + stmeq r0, {r8, r9} + nop + +srs: + srsia sp, #16 + srsdb sp, #16 + srsia sp!, #21 + srsia sp!, #10 + + movs pc, lr + subs pc, lr, #0 + subs pc, lr, #4 + subs pc, lr, #255 + + ldrd r2, r4, [r9, #48]! + ldrd r2, r4, [r9, #-48]! + strd r2, r4, [r9, #48]! + strd r2, r4, [r9, #-48]! + ldrd r2, r4, [r9], #48 + ldrd r2, r4, [r9], #-48 + strd r2, r4, [r9], #48 + strd r2, r4, [r9], #-48 + + .macro ldaddr op + ldr\op r1, [r5, #0x301] + ldr\op r1, [r5, #0x30]! + ldr\op r1, [r5, #-0x30]! + ldr\op r1, [r5], #0x30 + ldr\op r1, [r5], #-0x30 + ldr\op r1, [r5, r9] + .endm + ldaddr + ldaddr b + ldaddr sb + ldaddr h + ldaddr sh + .macro movshift op s="s" + movs r1, r4, \op #2 + movs r3, r9, \op #2 + movs r1, r2, \op r3 + movs r1, r1, \op r3 + movs r1, r1, \op r9 + mov r1, r2, \op r3 + mov r1, r1, \op r3 + .endm + movshift lsl + movshift lsr + movshift asr + movshift ror + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbrel.d b/binutils-2.25/gas/testsuite/gas/arm/thumbrel.d new file mode 100644 index 00000000..21839c92 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbrel.d @@ -0,0 +1,14 @@ +#objdump: -sr +# This test is only valid on EABI based ports. +#target: *-*-*eabi* *-*-symbianelf *-*-nacl* + +.*: file format.* + +RELOCATION RECORDS FOR \[.text\]: +OFFSET TYPE VALUE +00000004 R_ARM_REL32 b + +Contents of section .text: + 0000 00000000 (00000004|04000000) 00000000 00000000 .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbrel.s b/binutils-2.25/gas/testsuite/gas/arm/thumbrel.s new file mode 100644 index 00000000..769da161 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbrel.s @@ -0,0 +1,11 @@ +@ Check that PC-relative relocs against local function symbols are +@ generated correctly. +.text +.thumb +a: +.word 0 +.word b - a +.word 0 +.word 0 +.type b, %function +b: diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbv6.d b/binutils-2.25/gas/testsuite/gas/arm/thumbv6.d new file mode 100644 index 00000000..5da70351 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbv6.d @@ -0,0 +1,23 @@ +#name: THUMB V6 instructions +#as: -march=armv6j -mthumb +#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> b666 * cpsie ai +0+002 <[^>]*> b675 * cpsid af +0+004 <[^>]*> 4623 * mov r3, r4 +0+006 <[^>]*> ba3a * rev r2, r7 +0+008 <[^>]*> ba4d * rev16 r5, r1 +0+00a <[^>]*> baf3 * revsh r3, r6 +0+00c <[^>]*> b658 * setend be +0+00e <[^>]*> b650 * setend le +0+010 <[^>]*> b208 * sxth r0, r1 +0+012 <[^>]*> b251 * sxtb r1, r2 +0+014 <[^>]*> b2a3 * uxth r3, r4 +0+016 <[^>]*> b2f5 * uxtb r5, r6 +0+018 <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) +0+01a <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) +0+01c <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) +0+01e <[^>]*> 46c0 * nop[ ]+; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbv6.s b/binutils-2.25/gas/testsuite/gas/arm/thumbv6.s new file mode 100644 index 00000000..a4049750 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbv6.s @@ -0,0 +1,24 @@ +.text +.align 0 + +.thumb +label: + cpsie ia + cpsid af + cpy r3, r4 + rev r2, r7 + rev16 r5, r1 + revsh r3, r6 + setend be + setend le + sxth r0, r1 + sxtb r1, r2 + uxth r3, r4 + uxtb r5, r6 + + # Add four nop instructions to ensure that the output is + # 32-byte aligned as required for arm-aout. + nop + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbv6k.d b/binutils-2.25/gas/testsuite/gas/arm/thumbv6k.d new file mode 100644 index 00000000..1dd30eca --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbv6k.d @@ -0,0 +1,15 @@ +#name: THUMB V6K instructions +#as: -march=armv6k -mthumb +#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> bf10 * yield +0+002 <[^>]*> bf20 * wfe +0+004 <[^>]*> bf30 * wfi +0+006 <[^>]*> bf40 * sev +0+008 <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) +0+00a <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) +0+00c <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) +0+00e <[^>]*> 46c0 * nop[ \t]+; \(mov r8, r8\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbv6k.s b/binutils-2.25/gas/testsuite/gas/arm/thumbv6k.s new file mode 100644 index 00000000..86198432 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbv6k.s @@ -0,0 +1,14 @@ + .text + .align 0 + .thumb +label: + yield + wfe + wfi + sev + # arm-aout wants the segment padded to an 16-byte boundary; + # do this explicitly so it's consistent for all object formats. + nop + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbver.d b/binutils-2.25/gas/testsuite/gas/arm/thumbver.d new file mode 100644 index 00000000..d33d3150 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbver.d @@ -0,0 +1,15 @@ +# as: -meabi=4 +# readelf: -s +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Symbol table '\.symtab' contains .* entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name + +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND + +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1 +#... + +.*: 00000001 +0 +FUNC +LOCAL +DEFAULT +1 a_alias + +.*: 00000001 +0 +FUNC +LOCAL +DEFAULT +1 a_body + +.*: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +1 \$t + +.*: 00000001 +0 +FUNC +LOCAL +DEFAULT +1 a_export@VERSION +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumbver.s b/binutils-2.25/gas/testsuite/gas/arm/thumbver.s new file mode 100644 index 00000000..ad81395e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumbver.s @@ -0,0 +1,9 @@ +@ Check that symbols created by .symver are marked as Thumb. + + .thumb_set a_alias, a_body + .symver a_alias, a_export@VERSION + .type a_body, %function + .code 16 + .thumb_func +a_body: + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/tls.d b/binutils-2.25/gas/testsuite/gas/arm/tls.d new file mode 100644 index 00000000..727f8e4e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tls.d @@ -0,0 +1,49 @@ +#objdump: -dr +#name: TLS +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# VxWorks needs a special variant of this file. +#skip: *-*-vxworks* + +# Test generation of TLS relocations + +.*: +file format .*arm.* + +Disassembly of section .text: + +0+00 <arm_fn>: + 0: e1a00000 nop ; .* + 0: R_ARM_TLS_DESCSEQ af + 4: e59f0014 ldr r0, \[pc, #20\] ; 20 .* + 8: fa000000 blx 8 <ae\+.*> + 8: R_ARM_TLS_CALL ae + c: e1a00000 nop ; .* +0+10 <.arm_pool>: + 10: 00000008 .word 0x00000008 + 10: R_ARM_TLS_GD32 aa + 14: 0000000c .word 0x0000000c + 14: R_ARM_TLS_LDM32 ab + 18: 00000010 .word 0x00000010 + 18: R_ARM_TLS_IE32 ac + 1c: 00000000 .word 0x00000000 + 1c: R_ARM_TLS_LE32 ad + 20: 00000018 .word 0x00000018 + 20: R_ARM_TLS_GOTDESC ae +0+24 <thumb_fn>: + 24: 46c0 nop ; .* + 26: 46c0 nop ; .* + 26: R_ARM_THM_TLS_DESCSEQ tf + 28: 4805 ldr r0, \[pc, #20\] ; \(40 .*\) + 2a: f000 e800 blx 4 <te\+0x4> + 2a: R_ARM_THM_TLS_CALL te + 2e: 46c0 nop ; .* + 30: 00000002 .word 0x00000002 + 30: R_ARM_TLS_GD32 ta + 34: 00000006 .word 0x00000006 + 34: R_ARM_TLS_LDM32 tb + 38: 0000000a .word 0x0000000a + 38: R_ARM_TLS_IE32 tc + 3c: 00000000 .word 0x00000000 + 3c: R_ARM_TLS_LE32 td + 40: 00000017 .word 0x00000017 + 40: R_ARM_TLS_GOTDESC te diff --git a/binutils-2.25/gas/testsuite/gas/arm/tls.s b/binutils-2.25/gas/testsuite/gas/arm/tls.s new file mode 100644 index 00000000..96a25f56 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tls.s @@ -0,0 +1,38 @@ + .text + .arm + .globl arm_fn + .type arm_fn, %function +arm_fn: +1: +.tlsdescseq af + nop + ldr r0, 1f +2: blx ae(tlscall) + nop + +.arm_pool: + .word aa(tlsgd) + (. - 1b - 8) + .word ab(tlsldm) + (. - 1b- 8) + .word ac(gottpoff) + (. - 1b - 8) + .word ad(tpoff) +1: .word ae(tlsdesc) + (. - 2b) + + .thumb + .globl thumb_fn + .type thumb_fn, %function +thumb_fn: + nop +1: +.tlsdescseq tf + nop + ldr r0, 1f +2: blx te(tlscall) + nop + + .p2align 2 +.Lpool: + .word ta(tlsgd) + (. - 1b - 8) + .word tb(tlsldm) + (. - 1b - 8) + .word tc(gottpoff) + (. - 1b - 8) + .word td(tpoff) +1: .word te(tlsdesc) + (. - 2b + 1) diff --git a/binutils-2.25/gas/testsuite/gas/arm/tls_vxworks.d b/binutils-2.25/gas/testsuite/gas/arm/tls_vxworks.d new file mode 100644 index 00000000..6303a54b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/tls_vxworks.d @@ -0,0 +1,30 @@ +#objdump: -dr +#name: TLS +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# This is the VxWorks variant of this file. +#source: tls.s +#not-skip: *-*-vxworks* + +# Test generation of TLS relocations + +.*: +file format .*arm.* + +Disassembly of section .text: + +00+0 <main>: + 0: e1a00000 nop \(mov r0,r0\) + 4: e1a00000 nop \(mov r0,r0\) + 8: e1a0f00e mov pc, lr + c: 00000000 .word 0x00000000 + c: R_ARM_TLS_GD32 a +# ??? The addend is appearing in both the RELA field and the +# contents. Shouldn't it be just one? bfd_install_relocation +# appears to write the addend into the contents unconditionally, +# yet somehow this does not happen for the majority of relocations. + 10: 00000004 .word 0x00000004 + 10: R_ARM_TLS_LDM32 b\+0x4 + 14: 00000008 .word 0x00000008 + 14: R_ARM_TLS_IE32 c\+0x8 + 18: 00000000 .word 0x00000000 + 18: R_ARM_TLS_LE32 d diff --git a/binutils-2.25/gas/testsuite/gas/arm/udf-bad.d b/binutils-2.25/gas/testsuite/gas/arm/udf-bad.d new file mode 100644 index 00000000..94706d10 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/udf-bad.d @@ -0,0 +1,2 @@ +#name: Invalid UDF operands +#error-output: udf-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/udf-bad.l b/binutils-2.25/gas/testsuite/gas/arm/udf-bad.l new file mode 100644 index 00000000..4145ef01 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/udf-bad.l @@ -0,0 +1,5 @@ +[^:]*: Assembler messages: +^[^:]*:4: Error: immediate value out of range -- `udf #0x10000' +^[^:]*:7: Error: immediate value out of range -- `udf #0x10000' +^[^:]*:8: Error: immediate value out of range -- `udf.w #0x10000' +^[^:]*:9: Error: immediate value out of range -- `udf.n #0x100' diff --git a/binutils-2.25/gas/testsuite/gas/arm/udf-bad.s b/binutils-2.25/gas/testsuite/gas/arm/udf-bad.s new file mode 100644 index 00000000..60576982 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/udf-bad.s @@ -0,0 +1,9 @@ + .syntax unified + +arm: .arm + udf #0x10000 + +thumb: .thumb + udf #0x10000 + udf.w #0x10000 + udf.n #0x100 diff --git a/binutils-2.25/gas/testsuite/gas/arm/udf.d b/binutils-2.25/gas/testsuite/gas/arm/udf.d new file mode 100644 index 00000000..db41080f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/udf.d @@ -0,0 +1,30 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: UDF +#error-output: udf.l + +.*: +file format .*arm.* + +Disassembly of section \.text: + +0+0 <arm>: +\s*0:\s+e7f000f0\s+udf #0 +\s*4:\s+e7fabcfd\s+udf #43981 ; 0xabcd + +0+0 <thumb>: +\s*8:\s+deab\s+udf #171 ; 0xab +\s*a:\s+decd\s+udf #205 ; 0xcd +\s*c:\s+de00\s+udf #0 +\s*e:\s+46c0\s+nop.* +\s*10:\s+f7f0 a000\s+udf\.w #0 +\s*14:\s+f7f1 a234\s+udf\.w #4660 ; 0x1234 +\s*18:\s+f7fc acdd\s+udf\.w #52445 ; 0xccdd +\s*1c:\s+bf08\s+it eq +\s*1e:\s+de12\s+udfeq #18 +\s*20:\s+de23\s+udf #35 ; 0x23 +\s*22:\s+de34\s+udf #52 ; 0x34 +\s*24:\s+de56\s+udf #86 ; 0x56 +\s*26:\s+bf18\s+it ne +\s*28:\s+f7f1 a234\s+udfne\.w #4660 ; 0x1234 +\s*2c:\s+f7f2 a345\s+udf\.w #9029 ; 0x2345 +\s*30:\s+f7f3 a456\s+udf\.w #13398 ; 0x3456 +\s*34:\s+f7f5 a678\s+udf\.w #22136 ; 0x5678 diff --git a/binutils-2.25/gas/testsuite/gas/arm/udf.l b/binutils-2.25/gas/testsuite/gas/arm/udf.l new file mode 100644 index 00000000..67218cd2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/udf.l @@ -0,0 +1,3 @@ +^[^:]*: Assembler messages: +^[^:]*:16: Warning: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Short branches, Undefined, SVC, LDM/STM +^[^:]*:21: Warning: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8 diff --git a/binutils-2.25/gas/testsuite/gas/arm/udf.s b/binutils-2.25/gas/testsuite/gas/arm/udf.s new file mode 100644 index 00000000..d85b88ff --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/udf.s @@ -0,0 +1,24 @@ + .syntax unified + +arm: .arm + udf + udf #0xabcd + +thumb: .thumb + udf #0xab + udf.n #0xcd + udf + nop + udf.w + udf #0x1234 + udf.w #0xccdd + it eq + udf #0x12 + udf #0x23 + udf #0x34 + udf #0x56 + it ne + udf #0x1234 + udf #0x2345 + udf #0x3456 + udf #0x5678 diff --git a/binutils-2.25/gas/testsuite/gas/arm/undefined.d b/binutils-2.25/gas/testsuite/gas/arm/undefined.d new file mode 100644 index 00000000..6c8bca7d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/undefined.d @@ -0,0 +1,5 @@ +#name: Undefined local label error +# COFF and aout based ports, except Windows CE, +# use a different naming convention for local labels. +#skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix* *-*-vxworks +#error-output: undefined.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/undefined.l b/binutils-2.25/gas/testsuite/gas/arm/undefined.l new file mode 100644 index 00000000..89cfa041 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/undefined.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: undefined local label `\.Lval' diff --git a/binutils-2.25/gas/testsuite/gas/arm/undefined.s b/binutils-2.25/gas/testsuite/gas/arm/undefined.s new file mode 100644 index 00000000..f7b76d7d --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/undefined.s @@ -0,0 +1 @@ + ldr a1, .Lval diff --git a/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.d b/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.d new file mode 100644 index 00000000..d2800275 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.d @@ -0,0 +1,5 @@ +#name: Undefined local label error +# COFF and aout based ports, except Windows CE, +# use a different naming convention for local labels. +#not-skip: *-*-*coff *-unknown-pe *-epoc-pe *-*-*aout* *-*-netbsd *-*-riscix* +#error-output: undefined_coff.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.l b/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.l new file mode 100644 index 00000000..1bd8dcfc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:1: Error: undefined local label `Lval' diff --git a/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.s b/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.s new file mode 100644 index 00000000..dd18dad2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/undefined_coff.s @@ -0,0 +1 @@ + ldr a1, Lval diff --git a/binutils-2.25/gas/testsuite/gas/arm/unpredictable.d b/binutils-2.25/gas/testsuite/gas/arm/unpredictable.d new file mode 100644 index 00000000..e78727a4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/unpredictable.d @@ -0,0 +1,74 @@ +# name: Upredictable Instructions +# objdump: -D --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]+> [^<]+<UNPREDICTABLE> +0+004 <[^>]+> [^<]+<UNPREDICTABLE> +0+008 <[^>]+> [^<]+<UNPREDICTABLE> +0+00c <[^>]+> [^<]+<UNPREDICTABLE> +0+010 <[^>]+> [^<]+<UNPREDICTABLE> +0+014 <[^>]+> [^<]+<UNPREDICTABLE> +0+018 <[^>]+> [^<]+<UNPREDICTABLE> +0+01c <[^>]+> [^<]+<UNPREDICTABLE> +0+020 <[^>]+> [^<]+<UNPREDICTABLE> +0+024 <[^>]+> [^<]+<UNPREDICTABLE> +0+028 <[^>]+> [^<]+<UNPREDICTABLE> +0+02c <[^>]+> [^<]+<UNPREDICTABLE> +0+030 <[^>]+> [^<]+<UNPREDICTABLE> +0+034 <[^>]+> [^<]+<UNPREDICTABLE> +0+038 <[^>]+> [^<]+<UNPREDICTABLE> +0+03c <[^>]+> [^<]+<UNPREDICTABLE> +0+040 <[^>]+> [^<]+<UNPREDICTABLE> +0+044 <[^>]+> [^<]+<UNPREDICTABLE> +0+048 <[^>]+> [^<]+<UNPREDICTABLE> +0+04c <[^>]+> [^<]+<UNPREDICTABLE> +0+050 <[^>]+> [^<]+<UNPREDICTABLE> +0+054 <[^>]+> [^<]+<UNPREDICTABLE> +0+058 <[^>]+> [^<]+<UNPREDICTABLE> +0+05c <[^>]+> [^<]+<UNPREDICTABLE> +0+060 <[^>]+> [^<]+<UNPREDICTABLE> +0+064 <[^>]+> [^<]+<UNPREDICTABLE> +0+068 <[^>]+> [^<]+<UNPREDICTABLE> +0+06c <[^>]+> [^<]+<UNPREDICTABLE> +0+070 <[^>]+> [^<]+<UNPREDICTABLE> +0+074 <[^>]+> [^<]+<UNPREDICTABLE> +0+078 <[^>]+> [^<]+<UNPREDICTABLE> +0+07c <[^>]+> [^<]+<UNPREDICTABLE> +0+080 <[^>]+> [^<]+<UNPREDICTABLE> +0+084 <[^>]+> [^<]+<UNPREDICTABLE> +0+088 <[^>]+> [^<]+<UNPREDICTABLE> +0+08c <[^>]+> [^<]+<UNPREDICTABLE> +0+090 <[^>]+> [^<]+<UNPREDICTABLE> +0+094 <[^>]+> [^<]+<UNPREDICTABLE> +0+098 <[^>]+> [^<]+<UNPREDICTABLE> +0+09c <[^>]+> [^<]+<UNPREDICTABLE> +0+0a0 <[^>]+> [^<]+<UNPREDICTABLE> +0+0a4 <[^>]+> [^<]+<UNPREDICTABLE> +0+0a8 <[^>]+> [^<]+<UNPREDICTABLE> +0+0ac <[^>]+> [^<]+<UNPREDICTABLE> +0+0b0 <[^>]+> [^<]+<UNPREDICTABLE> +0+0b4 <[^>]+> [^<]+<UNPREDICTABLE> +0+0b8 <[^>]+> [^<]+<UNPREDICTABLE> +0+0bc <[^>]+> [^<]+<UNPREDICTABLE> +0+0c0 <[^>]+> [^<]+<UNPREDICTABLE> +0+0c4 <[^>]+> [^<]+<UNPREDICTABLE> +0+0c8 <[^>]+> [^<]+<UNPREDICTABLE> +0+0cc <[^>]+> [^<]+<UNPREDICTABLE> +0+0d0 <[^>]+> [^<]+<UNPREDICTABLE> +0+0d4 <[^>]+> [^<]+<UNPREDICTABLE> +0+0d8 <[^>]+> [^<]+<UNPREDICTABLE> +0+0dc <[^>]+> [^<]+<UNPREDICTABLE> +0+0e0 <[^>]+> [^<]+<UNPREDICTABLE> +0+0e4 <[^>]+> [^<]+<UNPREDICTABLE> +0+0e8 <[^>]+> [^<]+<UNPREDICTABLE> +0+0ec <[^>]+> [^<]+<UNPREDICTABLE> +0+0f0 <[^>]+> [^<]+<UNPREDICTABLE> +0+0f4 <[^>]+> [^<]+<UNPREDICTABLE> +0+0f8 <[^>]+> [^<]+<UNPREDICTABLE> +0+0fc <[^>]+> [^<]+<UNPREDICTABLE> +0+100 <[^>]+> [^<]+<UNPREDICTABLE> +0+104 <[^>]+> [^<]+<UNPREDICTABLE> +0+108 <[^>]+> e1a00000[ ]+nop[ ]+; \(mov r0, r0\) +#pass diff --git a/binutils-2.25/gas/testsuite/gas/arm/unpredictable.s b/binutils-2.25/gas/testsuite/gas/arm/unpredictable.s new file mode 100644 index 00000000..5fab0a44 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/unpredictable.s @@ -0,0 +1,84 @@ + .text + .global upredictable +unpredictable: + .word 0x004f00b1 @ strheq r0, [pc], #-1 + .word 0x005fffff @ ldrsheq pc, [pc], #-255 + .word 0x007fffff @ ldrsheq pc, [pc, #-255]! + .word 0x00cf00b0 @ strheq r0, [pc], #0 + .word 0x00df00b0 @ ldrheq r0, [pc], #0 + .word 0x00dfffff @ ldrsheq pc, [pc], #255 + .word 0x00ffffff @ ldrsheq pc, [pc, #255] + .word 0x0000f0b0 @ strheq pc, [r0], -r0 + .word 0x000ff0be @ strheq pc, [pc], -lr + .word 0xe16fff10 @ clz pc, r0 + .word 0xe16f0f1f @ clz r0, r15 + + .word 0xe99f0001 @ ldmib r15, { r0 } + .word 0xe9910000 @ ldmib r1, { } + .word 0xe89f0002 @ ldmia pc, { r1 } + .word 0xe93f0004 @ ldmdb r15!, { r2 } + .word 0xe83f0008 @ ldmda pc!, { r3 } + + .word 0xe7d0f001 @ ldrb pc, [r0, r1] + .word 0xe6f0f001 @ ldrbt pc, [r0], r1 + .word 0xe190f0b1 @ ldrh pc, [r0, r1] + .word 0xe190f0d1 @ ldrsb pc, [r0, r1] + .word 0xe010f0d0 @ ldrsb pc, [r0], -r0 + .word 0xe190f0f1 @ ldrsh pc, [r0, r1] + .word 0xe6b0f001 @ ldrt pc, [r0], r1 + + .word 0xe020f291 @ mla r0, r1, r2, pc + .word 0xe0202f91 @ mla r0, r1, pc, r2 + .word 0xe020219f @ mla r0, pc, r1, r2 + .word 0xe02f2190 @ mla pc, r0, r1, r2 + + .word 0xe10ff000 @ mrs pc, cpsr + + .word 0xe0000f91 @ mul r0, r1, pc + .word 0xe001009f @ mul r0, pc, r1 + .word 0xe00f0091 @ mul pc, r1, r0 + + .word 0xe0e21f93 @ smlal r1, r2, r3, pc + .word 0xe0e2149f @ smlal r1, r2, pc, r4 + .word 0xe0ef1493 @ smlal r1, pc, r3, r4 + .word 0xe0e2f493 @ smlal pc, r2, r3, r4 + .word 0xe0e11493 @ smlal r1, r1, r3, r4 + + .word 0xe0c21f93 @ smull r1, r2, r3, pc + .word 0xe0c2149f @ smull r1, r2, pc, r4 + .word 0xe0cf1493 @ smull r1, pc, r3, r4 + .word 0xe0c2f493 @ smull pc, r2, r3, r4 + .word 0xe0c11493 @ smull r1, r1, r3, r4 + + .word 0xe98f0004 @ stmib r15, { r2 } + .word 0xe88f0008 @ stmia r15, { r3 } + .word 0xe92f0010 @ stmdb r15!, { r4 } + .word 0xe82f0020 @ stmda r15!, { r5 } + + .word 0xe180f0b1 @ strh pc, [r0, r1] + + .word 0xe103f092 @ swp r15, r2, [r3] + .word 0xe103109f @ swp r1, r15, [r3] + .word 0xe10f1092 @ swp r1, r2, [r15] + .word 0xe1031093 @ swp r1, r3, [r3] + .word 0xe1033092 @ swp r3, r2, [r3] + + .word 0xe143f092 @ swpb r15, r2, [r3] + .word 0xe143109f @ swpb r1, r15, [r3] + .word 0xe14f1092 @ swpb r1, r2, [r15] + .word 0xe1431093 @ swpb r1, r3, [r3] + .word 0xe1433092 @ swpb r3, r2, [r3] + + .word 0xe0a21f93 @ umlal r1, r2, r3, r15 + .word 0xe0a2149f @ umlal r1, r2, r15, r4 + .word 0xe0af1493 @ umlal r1, r15, r3, r4 + .word 0xe0a2f493 @ umlal r15, r2, r3, r4 + .word 0xe0a11493 @ umlal r1, r1, r3, r4 + + .word 0xe0821f93 @ umull r1, r2, r3, r15 + .word 0xe082149f @ umull r1, r2, r15, r4 + .word 0xe08f1493 @ umull r1, r15, r3, r4 + .word 0xe082f493 @ umull r15, r2, r3, r4 + .word 0xe0811493 @ umull r1, r1, r3, r4 + + nop @ Marker to indicated end of unpredictable insns. diff --git a/binutils-2.25/gas/testsuite/gas/arm/unwind.d b/binutils-2.25/gas/testsuite/gas/arm/unwind.d new file mode 100644 index 00000000..060f7ba5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/unwind.d @@ -0,0 +1,46 @@ +#objdump: -sr +#name: Unwind table generation +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* +# VxWorks needs a special variant of this file. +#skip: *-*-vxworks* + +.*: file format.* + +RELOCATION RECORDS FOR \[.ARM.extab\]: +OFFSET TYPE VALUE +0000000c R_ARM_PREL31 .text + + +RELOCATION RECORDS FOR \[.ARM.exidx\]: +OFFSET TYPE VALUE +00000000 R_ARM_PREL31 .text +00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0 +00000008 R_ARM_PREL31 .text.* +00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1 +0000000c R_ARM_PREL31 .ARM.extab +00000010 R_ARM_PREL31 .text.* +00000014 R_ARM_PREL31 .ARM.extab.* +00000018 R_ARM_PREL31 .text.* +0000001c R_ARM_PREL31 .ARM.extab.* +00000020 R_ARM_PREL31 .text.* +00000028 R_ARM_PREL31 .text.* +00000030 R_ARM_PREL31 .text.* +00000034 R_ARM_PREL31 .ARM.extab.* + + +Contents of section .text: + 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* + 0010 (04200520 0600a0e3|20052004 e3a00006) .* +Contents of section .ARM.extab: + 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .* + 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42) .* + 0030 (b0008086|868000b0) 00000000 .* +Contents of section .ARM.exidx: + 0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000 .* + 0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c) .* + 0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0) .* + 0030 (14000000 2c000000|00000014 0000002c) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/unwind.s b/binutils-2.25/gas/testsuite/gas/arm/unwind.s new file mode 100644 index 00000000..bbd73a15 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/unwind.s @@ -0,0 +1,67 @@ +# Test generation of unwind tables + .text +foo: @ Simple function + .fnstart + .save {r4, lr} + mov r0, #0 + .fnend +foo1: @ Typical frame pointer prologue + .fnstart + .movsp ip + @mov ip, sp + .pad #4 + .save {fp, ip, lr} + @stmfd sp!, {fp, ip, lr, pc} + .setfp fp, ip, #4 + @sub fp, ip, #4 + mov r0, #1 + .fnend +foo2: @ Custom personality routine + .fnstart + .save {r1, r4, r6, lr} + @stmfd {r1, r4, r6, lr} + mov r0, #2 + .personality foo + .handlerdata + .word 42 + .fnend +foo3: @ Saving iwmmxt registers + .fnstart + .save {wr12} + .save {wr13} + .save {wr11} + .save {wr10} + .save {wr10, wr11} + .save {wr0} + mov r0, #3 + .fnend + .code 16 +foo4: @ Thumb frame pointer + .fnstart + .save {r7, lr} + @push {r7, lr} + .setfp r7, sp + @mov r7, sp + .pad #8 + @sub sp, sp, #8 + mov r0, #4 + .fnend +foo5: @ Save r0-r3 only. + .fnstart + .save {r0, r1, r2, r3} + mov r0, #5 + .fnend + .code 32 +foo6: @ Nested function with frame pointer + .fnstart + .pad #4 + @push {ip} + .movsp ip, #4 + @mov ip, sp + .pad #4 + .save {fp, ip, lr} + @stmfd sp!, {fp, ip, lr, pc} + .setfp fp, ip, #-8 + @sub fp, ip, #8 + mov r0, #6 + .fnend diff --git a/binutils-2.25/gas/testsuite/gas/arm/unwind_vxworks.d b/binutils-2.25/gas/testsuite/gas/arm/unwind_vxworks.d new file mode 100644 index 00000000..bb3edff8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/unwind_vxworks.d @@ -0,0 +1,45 @@ +#objdump: -sr +#name: Unwind table generation +# This is the VxWorks variant of this file. +#source: unwind.s +#not-skip: *-*-vxworks* + +.*: file format.* + +RELOCATION RECORDS FOR \[.ARM.extab\]: +OFFSET TYPE VALUE +0000000c R_ARM_PREL31 .text + + +RELOCATION RECORDS FOR \[.ARM.exidx\]: +OFFSET TYPE VALUE +00000000 R_ARM_PREL31 .text +00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0 +00000008 R_ARM_PREL31 .text.*\+0x00000004 +00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1 +0000000c R_ARM_PREL31 .ARM.extab +00000010 R_ARM_PREL31 .text.*\+0x00000008 +00000014 R_ARM_PREL31 .ARM.extab.*\+0x0000000c +00000018 R_ARM_PREL31 .text.*\+0x0000000c +0000001c R_ARM_PREL31 .ARM.extab.*\+0x0000001c +00000020 R_ARM_PREL31 .text.*\+0x00000010 +00000028 R_ARM_PREL31 .text.*\+0x00000012 +00000030 R_ARM_PREL31 .text.*\+0x00000014 +00000034 R_ARM_PREL31 .ARM.extab.*\+0x0000002c + + +Contents of section .text: + 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* + 0010 (04200520|20052004) .* +Contents of section .ARM.extab: + 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* + 0010 (8402b101 b0b0b005 2a000000 00c60281|01b10284 05b0b0b0 0000002a 8102c600) .* + 0020 (d0c6c1c1 b0b0c0c6|c1c1c6d0 c6c0b0b0) 00000000 (429b0181|81019b42) .* + 0030 (b0008086|868000b0) 00000000 .* +Contents of section .ARM.exidx: + 0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000 .* + 0010 00000000 00000000 00000000 00000000 .* + 0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0) .* + 0030 00000000 00000000 .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.25/gas/testsuite/gas/arm/v4bx.d b/binutils-2.25/gas/testsuite/gas/arm/v4bx.d new file mode 100644 index 00000000..d37c25bf --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/v4bx.d @@ -0,0 +1,10 @@ +# objdump: -dr --prefix-addresses --show-raw-insn +# as: -meabi=4 --fix-v4bx +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <[^>]+> e12fff1e bx lr + 0: R_ARM_V4BX \*ABS\* diff --git a/binutils-2.25/gas/testsuite/gas/arm/v4bx.s b/binutils-2.25/gas/testsuite/gas/arm/v4bx.s new file mode 100644 index 00000000..fecedccb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/v4bx.s @@ -0,0 +1,4 @@ + .arch armv4 + .text +foo: + bx lr diff --git a/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.d new file mode 100644 index 00000000..20b7798f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.d @@ -0,0 +1,4 @@ +#name: Invalid Immediate field for VCVT (between floating-point and fixed-point, VFP) +#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd +#error-output: vcvt-bad.l +#as: -mcpu=cortex-a8 -mfpu=vfpv3 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.l new file mode 100644 index 00000000..0c4f542e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.l @@ -0,0 +1,41 @@ +[^:]*: Assembler messages: +[^:]*:3: Error: immediate value out of range -- `vcvt.f64.u16 d1,d1,#-1' +[^:]*:4: Error: immediate value out of range -- `vcvt.f64.u16 d1,d1,#65535' +[^:]*:5: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.f64.u16 d1,d1,#17' +[^:]*:6: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.f64.u32 d1,d1,#0' +[^:]*:7: Error: immediate value out of range -- `vcvt.f64.u32 d1,d1,#33' +[^:]*:9: Error: immediate value out of range -- `vcvt.f32.u16 s1,s1,#-1' +[^:]*:10: Error: immediate value out of range -- `vcvt.f32.u16 s1,s1,#65535' +[^:]*:11: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.f32.u16 s1,s1,#17' +[^:]*:12: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.f32.u32 s1,s1,#0' +[^:]*:13: Error: immediate value out of range -- `vcvt.f32.u32 s1,s1,#33' +[^:]*:15: Error: immediate value out of range -- `vcvt.u16.f64 d1,d1,#-1' +[^:]*:16: Error: immediate value out of range -- `vcvt.u16.f64 d1,d1,#65535' +[^:]*:17: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.u16.f64 d1,d1,#17' +[^:]*:18: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.u32.f64 d1,d1,#0' +[^:]*:19: Error: immediate value out of range -- `vcvt.u32.f64 d1,d1,#33' +[^:]*:21: Error: immediate value out of range -- `vcvt.u16.f32 s1,s1,#-1' +[^:]*:22: Error: immediate value out of range -- `vcvt.u16.f32 s1,s1,#65535' +[^:]*:23: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.u16.f32 s1,s1,#17' +[^:]*:24: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.u32.f32 s1,s1,#0' +[^:]*:25: Error: immediate value out of range -- `vcvt.u32.f32 s1,s1,#33' +[^:]*:27: Error: immediate value out of range -- `vcvt.f64.s16 d1,d1,#-1' +[^:]*:28: Error: immediate value out of range -- `vcvt.f64.s16 d1,d1,#65535' +[^:]*:29: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.f64.s16 d1,d1,#17' +[^:]*:30: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.f64.s32 d1,d1,#0' +[^:]*:31: Error: immediate value out of range -- `vcvt.f64.s32 d1,d1,#33' +[^:]*:33: Error: immediate value out of range -- `vcvt.f32.s16 s1,s1,#-1' +[^:]*:34: Error: immediate value out of range -- `vcvt.f32.s16 s1,s1,#65535' +[^:]*:35: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.f32.s16 s1,s1,#17' +[^:]*:36: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.f32.s32 s1,s1,#0' +[^:]*:37: Error: immediate value out of range -- `vcvt.f32.s32 s1,s1,#33' +[^:]*:39: Error: immediate value out of range -- `vcvt.s16.f64 d1,d1,#-1' +[^:]*:40: Error: immediate value out of range -- `vcvt.s16.f64 d1,d1,#65535' +[^:]*:41: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.s16.f64 d1,d1,#17' +[^:]*:42: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.s32.f64 d1,d1,#0' +[^:]*:43: Error: immediate value out of range -- `vcvt.s32.f64 d1,d1,#33' +[^:]*:45: Error: immediate value out of range -- `vcvt.s16.f32 s1,s1,#-1' +[^:]*:46: Error: immediate value out of range -- `vcvt.s16.f32 s1,s1,#65535' +[^:]*:47: Error: immediate value out of range, expected range \[0, 16\] -- `vcvt.s16.f32 s1,s1,#17' +[^:]*:48: Error: immediate value out of range, expected range \[1, 32\] -- `vcvt.s32.f32 s1,s1,#0' +[^:]*:49: Error: immediate value out of range -- `vcvt.s32.f32 s1,s1,#33' diff --git a/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.s b/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.s new file mode 100644 index 00000000..273bbc69 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vcvt-bad.s @@ -0,0 +1,51 @@ +.text +.syntax unified +VCVT.F64.U16 d1,d1,#-1 +VCVT.F64.U16 d1,d1,#65535 +VCVT.F64.U16 d1,d1,#17 +VCVT.F64.U32 d1,d1,#0 +VCVT.F64.U32 d1,d1,#33 + +VCVT.F32.U16 s1,s1,#-1 +VCVT.F32.U16 s1,s1,#65535 +VCVT.F32.U16 s1,s1,#17 +VCVT.F32.U32 s1,s1,#0 +VCVT.F32.U32 s1,s1,#33 + +VCVT.U16.F64 d1,d1,#-1 +VCVT.U16.F64 d1,d1,#65535 +VCVT.U16.F64 d1,d1,#17 +VCVT.U32.F64 d1,d1,#0 +VCVT.U32.F64 d1,d1,#33 + +VCVT.U16.F32 s1,s1,#-1 +VCVT.U16.F32 s1,s1,#65535 +VCVT.U16.F32 s1,s1,#17 +VCVT.U32.F32 s1,s1,#0 +VCVT.U32.F32 s1,s1,#33 + +VCVT.F64.S16 d1,d1,#-1 +VCVT.F64.S16 d1,d1,#65535 +VCVT.F64.S16 d1,d1,#17 +VCVT.F64.S32 d1,d1,#0 +VCVT.F64.S32 d1,d1,#33 + +VCVT.F32.S16 s1,s1,#-1 +VCVT.F32.S16 s1,s1,#65535 +VCVT.F32.S16 s1,s1,#17 +VCVT.F32.S32 s1,s1,#0 +VCVT.F32.S32 s1,s1,#33 + +VCVT.S16.F64 d1,d1,#-1 +VCVT.S16.F64 d1,d1,#65535 +VCVT.S16.F64 d1,d1,#17 +VCVT.S32.F64 d1,d1,#0 +VCVT.S32.F64 d1,d1,#33 + +VCVT.S16.F32 s1,s1,#-1 +VCVT.S16.F32 s1,s1,#65535 +VCVT.S16.F32 s1,s1,#17 +VCVT.S32.F32 s1,s1,#0 +VCVT.S32.F32 s1,s1,#33 + +.end diff --git a/binutils-2.25/gas/testsuite/gas/arm/vcvt.d b/binutils-2.25/gas/testsuite/gas/arm/vcvt.d new file mode 100644 index 00000000..9c92b13e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vcvt.d @@ -0,0 +1,33 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: VCVT +#as: -mcpu=cortex-a8 -mfpu=vfpv3 + +# Test the `VCVT' op + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eebb1b48 vcvt.f64.u16 d1, d1, #0 +0+004 <[^>]*> eebb1b40 vcvt.f64.u16 d1, d1, #16 +0+008 <[^>]*> eebb1b44 vcvt.f64.u16 d1, d1, #8 +0+00c <[^>]*> eebb1bef vcvt.f64.u32 d1, d1, #1 +0+010 <[^>]*> eebb1bc0 vcvt.f64.u32 d1, d1, #32 +0+014 <[^>]*> eebb1be7 vcvt.f64.u32 d1, d1, #17 +0+018 <[^>]*> eefb0a48 vcvt.f32.u16 s1, s1, #0 +0+01c <[^>]*> eefb0a40 vcvt.f32.u16 s1, s1, #16 +0+020 <[^>]*> eefb0a60 vcvt.f32.u16 s1, s1, #15 +0+024 <[^>]*> eefb0aef vcvt.f32.u32 s1, s1, #1 +0+028 <[^>]*> eefb0ac0 vcvt.f32.u32 s1, s1, #32 +0+02c <[^>]*> eefb0ac8 vcvt.f32.u32 s1, s1, #16 +0+030 <[^>]*> eebf1b48 vcvt.u16.f64 d1, d1, #0 +0+034 <[^>]*> eebf1b40 vcvt.u16.f64 d1, d1, #16 +0+038 <[^>]*> eebf1b60 vcvt.u16.f64 d1, d1, #15 +0+03c <[^>]*> eebf1bef vcvt.u32.f64 d1, d1, #1 +0+040 <[^>]*> eebf1bc0 vcvt.u32.f64 d1, d1, #32 +0+044 <[^>]*> eebf1bc8 vcvt.u32.f64 d1, d1, #16 +0+048 <[^>]*> eeff0a48 vcvt.u16.f32 s1, s1, #0 +0+04c <[^>]*> eeff0a40 vcvt.u16.f32 s1, s1, #16 +0+050 <[^>]*> eeff0a44 vcvt.u16.f32 s1, s1, #8 +0+054 <[^>]*> eeff0aef vcvt.u32.f32 s1, s1, #1 +0+058 <[^>]*> eeff0ac0 vcvt.u32.f32 s1, s1, #32 +0+05c <[^>]*> eeff0ae7 vcvt.u32.f32 s1, s1, #17 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vcvt.s b/binutils-2.25/gas/testsuite/gas/arm/vcvt.s new file mode 100644 index 00000000..13212500 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vcvt.s @@ -0,0 +1,31 @@ +.text +.syntax unified +VCVT.F64.U16 d1,d1,#0 +VCVT.F64.U16 d1,d1,#16 +VCVT.F64.U16 d1,d1,#8 +VCVT.F64.U32 d1,d1,#1 +VCVT.F64.U32 d1,d1,#32 +VCVT.F64.U32 d1,d1,#17 + +VCVT.F32.U16 s1,s1,#0 +VCVT.F32.U16 s1,s1,#16 +VCVT.F32.U16 s1,s1,#15 +VCVT.F32.U32 s1,s1,#1 +VCVT.F32.U32 s1,s1,#32 +VCVT.F32.U32 s1,s1,#16 + +VCVT.U16.F64 d1,d1,#0 +VCVT.U16.F64 d1,d1,#16 +VCVT.U16.F64 d1,d1,#15 +VCVT.U32.F64 d1,d1,#1 +VCVT.U32.F64 d1,d1,#32 +VCVT.U32.F64 d1,d1,#16 + +VCVT.U16.F32 s1,s1,#0 +VCVT.U16.F32 s1,s1,#16 +VCVT.U16.F32 s1,s1,#8 +VCVT.U32.F32 s1,s1,#1 +VCVT.U32.F32 s1,s1,#32 +VCVT.U32.F32 s1,s1,#17 + +.end diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfma1.d b/binutils-2.25/gas/testsuite/gas/arm/vfma1.d new file mode 100644 index 00000000..a60e4308 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfma1.d @@ -0,0 +1,36 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: VFMA decoding +#as: -mcpu=arm7m +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# Test VFMA instruction disassembly + +.*: *file format .*arm.* + + +Disassembly of section .text: +00000000 <[^>]*> ee000a00 vmla.f32 s0, s0, s0 +00000004 <[^>]*> ee000b00 vmla.f64 d0, d0, d0 +00000008 <[^>]*> f2000d10 vmla.f32 d0, d0, d0 +0000000c <[^>]*> f2000d50 vmla.f32 q0, q0, q0 +00000010 <[^>]*> eea00a00 vfma.f32 s0, s0, s0 +00000014 <[^>]*> eea00b00 vfma.f64 d0, d0, d0 +00000018 <[^>]*> f2000c10 vfma.f32 d0, d0, d0 +0000001c <[^>]*> f2000c50 vfma.f32 q0, q0, q0 +00000020 <[^>]*> ee000a40 vmls.f32 s0, s0, s0 +00000024 <[^>]*> ee000b40 vmls.f64 d0, d0, d0 +00000028 <[^>]*> f2200d10 vmls.f32 d0, d0, d0 +0000002c <[^>]*> f2200d50 vmls.f32 q0, q0, q0 +00000030 <[^>]*> eea00a40 vfms.f32 s0, s0, s0 +00000034 <[^>]*> eea00b40 vfms.f64 d0, d0, d0 +00000038 <[^>]*> f2200c10 vfms.f32 d0, d0, d0 +0000003c <[^>]*> f2200c50 vfms.f32 q0, q0, q0 +00000040 <[^>]*> ee100a40 vnmla.f32 s0, s0, s0 +00000044 <[^>]*> ee100b40 vnmla.f64 d0, d0, d0 +00000048 <[^>]*> ee900a40 vfnma.f32 s0, s0, s0 +0000004c <[^>]*> ee900b40 vfnma.f64 d0, d0, d0 +00000050 <[^>]*> ee100a00 vnmls.f32 s0, s0, s0 +00000054 <[^>]*> ee100b00 vnmls.f64 d0, d0, d0 +00000058 <[^>]*> ee900a00 vfnms.f32 s0, s0, s0 +0000005c <[^>]*> ee900b00 vfnms.f64 d0, d0, d0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfma1.s b/binutils-2.25/gas/testsuite/gas/arm/vfma1.s new file mode 100644 index 00000000..bc124f89 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfma1.s @@ -0,0 +1,43 @@ + + .eabi_attribute Tag_Advanced_SIMD_arch, 2 + .eabi_attribute Tag_VFP_arch, 6 + + @VMLA + .inst 0xee000a00 @ VFP vmla.f32 s0,s0,s0 + .inst 0xee000b00 @ VFP vmla.f64 d0,d0,d0 + .inst 0xf2000d10 @ NEON vmla.f32 d0,d0,d0 + .inst 0xf2000d50 @ NEON vmla.f32 q0,q0,q0 + + @VFMA new + .inst 0xeea00a00 @ VFP vfma.f32 s0,s0,s0 + .inst 0xeea00b00 @ VFP vfma.f64 d0,d0,d0 + .inst 0xf2000c10 @ NEON vfma.f32 d0,d0,d0 + .inst 0xf2000c50 @ NEON vfma.f32 q0,q0,q0 + + @VMLS + .inst 0xee000a40 @ VFP vmls.F32 s0,s0,s0 + .inst 0xee000b40 @ VFP vmls.F64 d0,d0,d0 + .inst 0xf2200d10 @ NEON vmls.F32 d0,d0,d0 + .inst 0xf2200d50 @ NEON vmls.F32 q0,q0,q0 + + @VFMS new + .inst 0xeea00a40 @ VFP vfms.F32 s0,s0,s0 + .inst 0xeea00b40 @ VFP vfms.F64 d0,d0,d0 + .inst 0xf2200c10 @ NEON vfms.F32 d0,d0,d0 + .inst 0xf2200c50 @ NEON vfms.F32 q0,q0,q0 + + @VNMLA + .inst 0xee100a40 @ VFP vnmla.F32 s0,s0,s0 + .inst 0xee100b40 @ VFP vnmla.F64 d0,d0,d0 + + @VFNMA new + .inst 0xee900a40 @ VFP vfnma.F32 s0,s0,s0 + .inst 0xee900b40 @ VFP vfnma.F64 d0,d0,d0 + + @VNMLS + .inst 0xee100a00 @ VFP vnmls.F32 s0,s0,s0 + .inst 0xee100b00 @ VFP vnmls.F64 d0,d0,d0 + + @VFNMS new + .inst 0xee900a00 @ VFP vfnms.F32 s0,s0,s0 + .inst 0xee900b00 @ VFP vfnms.F64 d0,d0,d0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.d new file mode 100644 index 00000000..760c4d5c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.d @@ -0,0 +1,3 @@ +#name: VFP errors +#as: -mfpu=vfp +#error-output: vfp-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.l new file mode 100644 index 00000000..7726e631 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.l @@ -0,0 +1,9 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8' +[^:]*:5: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!' +[^:]*:6: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8' +[^:]*:7: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!' +[^:]*:8: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8' +[^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!' +[^:]*:10: Error: instruction does not support writeback -- `flds s0,\[r0\],#8' +[^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.s new file mode 100644 index 00000000..ac443717 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad.s @@ -0,0 +1,11 @@ + .global entry + .text +entry: + fstd d0, [r0], #8 + fstd d0, [r0, #-8]! + fsts s0, [r0], #8 + fsts s0, [r0, #-8]! + fldd d0, [r0], #8 + fldd d0, [r0, #-8]! + flds s0, [r0], #8 + flds s0, [r0, #-8]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.d new file mode 100644 index 00000000..1ef83bab --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.d @@ -0,0 +1,3 @@ +#name: Thumb-2 VFP errors +#as: -mfpu=vfp +#error-output: vfp-bad_t2.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.l b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.l new file mode 100644 index 00000000..ecc0640b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.l @@ -0,0 +1,9 @@ +[^:]*: Assembler messages: +[^:]*:7: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8' +[^:]*:8: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!' +[^:]*:9: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8' +[^:]*:10: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!' +[^:]*:11: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8' +[^:]*:12: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!' +[^:]*:13: Error: instruction does not support writeback -- `flds s0,\[r0\],#8' +[^:]*:14: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!' diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.s new file mode 100644 index 00000000..3b904b36 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-bad_t2.s @@ -0,0 +1,14 @@ + .global entry +@ Same as vfp-bad.s, but for Thumb-2 + .syntax unified + .thumb + .text +entry: + fstd d0, [r0], #8 + fstd d0, [r0, #-8]! + fsts s0, [r0], #8 + fsts s0, [r0, #-8]! + fldd d0, [r0], #8 + fldd d0, [r0, #-8]! + flds s0, [r0], #8 + flds s0, [r0, #-8]! diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-arm.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-arm.d new file mode 100644 index 00000000..6a4f7170 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-arm.d @@ -0,0 +1,23 @@ +# name: FMA instructions, ARM mode +# as: -mfpu=vfpv4 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eea00a81 vfma\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> eea10b02 vfma\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0ea00a81 vfmaeq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0ea10b02 vfmaeq\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> eea00ac1 vfms\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> eea10b42 vfms\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0ea00ac1 vfmseq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0ea10b42 vfmseq\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee900ac1 vfnma\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee910b42 vfnma\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e900ac1 vfnmaeq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e910b42 vfnmaeq\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee900a81 vfnms\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee910b02 vfnms\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e900a81 vfnmseq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e910b02 vfnmseq\.f64 d0, d1, d2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-arm.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-arm.s new file mode 100644 index 00000000..945926b1 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-arm.s @@ -0,0 +1,2 @@ + .arm + .include "vfp-fma-inc.s" diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-inc.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-inc.s new file mode 100644 index 00000000..4f349e1f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-inc.s @@ -0,0 +1,22 @@ + .syntax unified + .arch armv7-a + .fpu neon-vfpv4 + + .include "itblock.s" + +func: + .macro dyadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1,s2 + \op\cond\f64 d0,d1,d2 + .endm + + .macro dyadic_c op + dyadic \op + dyadic \op eq + .endm + + dyadic_c vfma + dyadic_c vfms + dyadic_c vfnma + dyadic_c vfnms diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-thumb.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-thumb.d new file mode 100644 index 00000000..2ee77fd8 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-thumb.d @@ -0,0 +1,27 @@ +# name: FMA instructions, Thumb mode +# as: -mfpu=vfpv4 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eea0 0a81 vfma\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> eea1 0b02 vfma\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eea0 0a81 vfmaeq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> eea1 0b02 vfmaeq\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> eea0 0ac1 vfms\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> eea1 0b42 vfms\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eea0 0ac1 vfmseq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> eea1 0b42 vfmseq\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee90 0ac1 vfnma\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee91 0b42 vfnma\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee90 0ac1 vfnmaeq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee91 0b42 vfnmaeq\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee90 0a81 vfnms\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee91 0b02 vfnms\.f64 d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee90 0a81 vfnmseq\.f32 s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee91 0b02 vfnmseq\.f64 d0, d1, d2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-thumb.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-thumb.s new file mode 100644 index 00000000..fa3b7924 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-fma-thumb.s @@ -0,0 +1,2 @@ + .thumb + .include "vfp-fma-inc.s" diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-overlap.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-overlap.d new file mode 100644 index 00000000..6c328d3f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-overlap.d @@ -0,0 +1,35 @@ +# name: VFP/Neon overlapping instructions +# as: -mfpu=vfp +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1 +0[0-9a-f]+ <[^>]+> ec410b10 vmov d0, r0, r1 +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> ec510b10 vmov r0, r1, d0 +0[0-9a-f]+ <[^>]+> ec900b09 fldmiax r0, {d0-d3}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ed300b09 fldmdbx r0!, {d0-d3}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ec800b09 fstmiax r0, {d0-d3}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ed200b09 fstmdbx r0!, {d0-d3}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed900b00 vldr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ed800b00 vstr d0, \[r0\] +0[0-9a-f]+ <[^>]+> ec900b08 vldmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ec900b08 vldmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b08 vldmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed300b08 vldmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b08 vstmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ec800b08 vstmia r0, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b08 vstmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ed200b08 vstmdb r0!, {d0-d3} +0[0-9a-f]+ <[^>]+> ee300b10 vmov\.32 r0, d0\[1\] +0[0-9a-f]+ <[^>]+> ee300b10 vmov\.32 r0, d0\[1\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee100b10 vmov\.32 r0, d0\[0\] +0[0-9a-f]+ <[^>]+> ee200b10 vmov\.32 d0\[1\], r0 +0[0-9a-f]+ <[^>]+> ee200b10 vmov\.32 d0\[1\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 +0[0-9a-f]+ <[^>]+> ee000b10 vmov\.32 d0\[0\], r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-overlap.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-overlap.s new file mode 100644 index 00000000..19c286af --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-overlap.s @@ -0,0 +1,41 @@ +@ VFP/Neon overlapping instructions + + .arm + .text + .syntax unified + + fmdrr d0,r0,r1 + vmov d0,r0,r1 + fmrrd r0,r1,d0 + vmov r0,r1,d0 + + @ the 'x' versions should disassemble as VFP instructions, because + @ they can't be represented in Neon syntax. + + fldmiax r0,{d0-d3} + fldmdbx r0!,{d0-d3} + fstmiax r0,{d0-d3} + fstmdbx r0!,{d0-d3} + + fldd d0,[r0] + vldr d0,[r0] + fstd d0,[r0] + vstr d0,[r0] + + fldmiad r0,{d0-d3} + vldmia r0,{d0-d3} + fldmdbd r0!,{d0-d3} + vldmdb r0!,{d0-d3} + fstmiad r0,{d0-d3} + vstmia r0,{d0-d3} + fstmdbd r0!,{d0-d3} + vstmdb r0!,{d0-d3} + + fmrdh r0,d0 + vmov.32 r0,d0[1] + fmrdl r0,d0 + vmov.32 r0,d0[0] + fmdhr d0,r0 + vmov.32 d0[1],r0 + fmdlr d0,r0 + vmov.32 d0[0],r0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s new file mode 100644 index 00000000..5005cb7c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax-inc.s @@ -0,0 +1,163 @@ +@ VFP with Neon-style syntax + .syntax unified + .arch armv7-a + + .include "itblock.s" + +func: + .macro testvmov cond="" f32=".f32" f64=".f64" + itblock 4 \cond + vmov\cond\f32 s0,s1 + vmov\cond\f64 d0,d1 + vmov\cond\f32 s0,#0.25 + vmov\cond\f64 d0,#1.0 + itblock 4 \cond + vmov\cond r0,s1 + vmov\cond s0,r1 + vmov\cond r0,r1,s2,s3 + vmov\cond s0,s1,r2,r4 + .endm + + @ Test VFP vmov variants. These can all be conditional. + testvmov + testvmov eq + + .macro monadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1 + \op\cond\f64 d0,d1 + .endm + + .macro monadic_c op + monadic \op + monadic \op eq + .endm + + .macro dyadic op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,s1,s2 + \op\cond\f64 d0,d1,d2 + .endm + + .macro dyadic_c op + dyadic \op + dyadic \op eq + .endm + + .macro dyadicz op cond="" f32=".f32" f64=".f64" + itblock 2 \cond + \op\cond\f32 s0,#0 + \op\cond\f64 d0,#0 + .endm + + .macro dyadicz_c op + dyadicz \op + dyadicz \op eq + .endm + + monadic_c vsqrt + monadic_c vabs + monadic_c vneg + monadic_c vcmp + monadic_c vcmpe + + dyadic_c vnmul + dyadic_c vnmla + dyadic_c vnmls + + dyadic_c vmul + dyadic_c vmla + dyadic_c vmls + + dyadic_c vadd + dyadic_c vsub + + dyadic_c vdiv + + dyadicz_c vcmp + dyadicz_c vcmpe + + .macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvtz\cond\s32\f32 s0,s1 + vcvtz\cond\u32\f32 s0,s1 + vcvtz\cond\s32\f64 s0,d1 + vcvtz\cond\u32\f64 s0,d1 + .endm + + cvtz + cvtz eq + + .macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s1 + vcvt\cond\u32\f32 s0,s1 + vcvt\cond\f32\s32 s0,s1 + vcvt\cond\f32\u32 s0,s1 + itblock 4 \cond + vcvt\cond\f32\f64 s0,d1 + vcvt\cond\f64\f32 d0,s1 + vcvt\cond\s32\f64 s0,d1 + vcvt\cond\u32\f64 s0,d1 + itblock 2 \cond + vcvt\cond\f64\s32 d0,s1 + vcvt\cond\f64\u32 d0,s1 + .endm + + cvt + cvt eq + + .macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16" + itblock 4 \cond + vcvt\cond\s32\f32 s0,s0,#1 + vcvt\cond\u32\f32 s0,s0,#1 + vcvt\cond\f32\s32 s0,s0,#1 + vcvt\cond\f32\u32 s0,s0,#1 + itblock 4 \cond + vcvt\cond\s32\f64 d0,d0,#1 + vcvt\cond\u32\f64 d0,d0,#1 + vcvt\cond\f64\s32 d0,d0,#1 + vcvt\cond\f64\u32 d0,d0,#1 + itblock 4 \cond + vcvt\cond\f32\s16 s0,s0,#1 + vcvt\cond\f32\u16 s0,s0,#1 + vcvt\cond\f64\s16 d0,d0,#1 + vcvt\cond\f64\u16 d0,d0,#1 + itblock 4 \cond + vcvt\cond\s16\f32 s0,s0,#1 + vcvt\cond\u16\f32 s0,s0,#1 + vcvt\cond\s16\f64 d0,d0,#1 + vcvt\cond\u16\f64 d0,d0,#1 + .endm + + cvti + cvti eq + + .macro multi op cond="" n="" ia="ia" db="db" + itblock 4 \cond + \op\n\cond r0,{s3-s6} + \op\ia\cond r0,{s3-s6} + \op\ia\cond r0!,{s3-s6} + \op\db\cond r0!,{s3-s6} + itblock 4 \cond + \op\n\cond r0,{d3-d6} + \op\ia\cond r0,{d3-d6} + \op\ia\cond r0!,{d3-d6} + \op\db\cond r0!,{d3-d6} + .endm + + multi vldm + multi vldm eq + multi vstm + multi vstm eq + + .macro single op cond="" + itblock 2 \cond + \op\cond s0,[r0,#4] + \op\cond d0,[r0,#4] + .endm + + single vldr + single vldr eq + single vstr + single vstr eq diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax.d new file mode 100644 index 00000000..8b2a2570 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax.d @@ -0,0 +1,187 @@ +# name: VFP Neon-style syntax, ARM mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> eeb00a60 (vmov\.f32|fcpys) s0, s1 +0[0-9a-f]+ <[^>]+> eeb00b41 (vmov\.f64|fcpyd) d0, d1 +0[0-9a-f]+ <[^>]+> eeb50a00 (vmov\.f32|fconsts) s0, #80.* +0[0-9a-f]+ <[^>]+> eeb70b00 (vmov\.f64|fconstd) d0, #112.* +0[0-9a-f]+ <[^>]+> ee100a90 (vmov|fmrs) r0, s1 +0[0-9a-f]+ <[^>]+> ee001a10 (vmov|fmsr) s0, r1 +0[0-9a-f]+ <[^>]+> ec510a11 (vmov r0, r1, s2, s3|fmrrs r0, r1, {s2, s3}) +0[0-9a-f]+ <[^>]+> ec442a10 (vmov s0, s1, r2, r4|fmsrr {s0, s1}, r2, r4) +0[0-9a-f]+ <[^>]+> 0eb00a60 (vmoveq\.f32|fcpyseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00b41 (vmoveq\.f64|fcpydeq) d0, d1 +0[0-9a-f]+ <[^>]+> 0eb50a00 (vmoveq\.f32|fconstseq) s0, #80.* +0[0-9a-f]+ <[^>]+> 0eb70b00 (vmoveq\.f64|fconstdeq) d0, #112.* +0[0-9a-f]+ <[^>]+> 0e100a90 (vmoveq|fmrseq) r0, s1 +0[0-9a-f]+ <[^>]+> 0e001a10 (vmoveq|fmsreq) s0, r1 +0[0-9a-f]+ <[^>]+> 0c510a11 (vmoveq r0, r1, s2, s3|fmrrseq r0, r1, {s2, s3}) +0[0-9a-f]+ <[^>]+> 0c442a10 (vmoveq s0, s1, r2, r4|fmsrreq {s0, s1}, r2, r4) +0[0-9a-f]+ <[^>]+> eeb10ae0 (vsqrt\.f32|fsqrts) s0, s1 +0[0-9a-f]+ <[^>]+> eeb10bc1 (vsqrt\.f64|fsqrtd) d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10ae0 (vsqrteq.f32|fsqrtseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10bc1 (vsqrteq.f64|fsqrtdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb00ae0 (vabs\.f32|fabss) s0, s1 +0[0-9a-f]+ <[^>]+> eeb00bc1 (vabs\.f64|fabsd) d0, d1 +0[0-9a-f]+ <[^>]+> 0eb00ae0 (vabseq\.f32|fabsseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb00bc1 (vabseq\.f64|fabsdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb10a60 (vneg\.f32|fnegs) s0, s1 +0[0-9a-f]+ <[^>]+> eeb10b41 (vneg\.f64|fnegd) d0, d1 +0[0-9a-f]+ <[^>]+> 0eb10a60 (vnegeq\.f32|fnegseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb10b41 (vnegeq\.f64|fnegdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb40a60 (vcmp\.f32|fcmps) s0, s1 +0[0-9a-f]+ <[^>]+> eeb40b41 (vcmp\.f64|fcmpd) d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40a60 (vcmpeq\.f32|fcmpseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40b41 (vcmpeq\.f64|fcmpdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb40ae0 (vcmpe\.f32|fcmpes) s0, s1 +0[0-9a-f]+ <[^>]+> eeb40bc1 (vcmpe\.f64|fcmped) d0, d1 +0[0-9a-f]+ <[^>]+> 0eb40ae0 (vcmpeeq\.f32|fcmpeseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb40bc1 (vcmpeeq\.f64|fcmpedeq) d0, d1 +0[0-9a-f]+ <[^>]+> ee200ac1 (vnmul\.f32|fnmuls) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b42 (vnmul\.f64|fnmuld) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200ac1 (vnmuleq\.f32|fnmulseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b42 (vnmuleq\.f64|fnmuldeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100ac1 (vnmla\.f32|fnmacs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b42 (vnmla\.f64|fnmacd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100ac1 (vnmlaeq\.f32|fnmacseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b42 (vnmlaeq\.f64|fnmacdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee100a81 (vnmls\.f32|fnmscs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee110b02 (vnmls\.f64|fnmscd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e100a81 (vnmlseq\.f32|fnmscseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e110b02 (vnmlseq\.f64|fnmscdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee200a81 (vmul\.f32|fmuls) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee210b02 (vmul\.f64|fmuld) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e200a81 (vmuleq\.f32|fmulseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e210b02 (vmuleq\.f64|fmuldeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000a81 (vmla\.f32|fmacs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b02 (vmla\.f64|fmacd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000a81 (vmlaeq\.f32|fmacseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b02 (vmlaeq\.f64|fmacdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee000ac1 (vmls\.f32|fmscs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee010b42 (vmls\.f64|fmscd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e000ac1 (vmlseq\.f32|fmscseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e010b42 (vmlseq\.f64|fmscdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300a81 (vadd\.f32|fadds) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b02 (vadd\.f64|faddd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300a81 (vaddeq\.f32|faddseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b02 (vaddeq\.f64|fadddeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee300ac1 (vsub\.f32|fsubs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee310b42 (vsub\.f64|fsubd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e300ac1 (vsubeq\.f32|fsubseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e310b42 (vsubeq\.f64|fsubdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee800a81 (vdiv\.f32|fdivs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee810b02 (vdiv\.f64|fdivd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> 0e800a81 (vdiveq\.f32|fdivseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> 0e810b02 (vdiveq\.f64|fdivdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0) +0[0-9a-f]+ <[^>]+> eeb50b40 (vcmp\.f64 d0, #0.0|fcmpzd d0) +0[0-9a-f]+ <[^>]+> 0eb50a40 (vcmpeq\.f32 s0, #0.0|fcmpzseq s0) +0[0-9a-f]+ <[^>]+> 0eb50b40 (vcmpeq\.f64 d0, #0.0|fcmpzdeq d0) +0[0-9a-f]+ <[^>]+> eeb50ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0) +0[0-9a-f]+ <[^>]+> eeb50bc0 (vcmpe\.f64 d0, #0.0|fcmpezd d0) +0[0-9a-f]+ <[^>]+> 0eb50ac0 (vcmpeeq\.f32 s0, #0.0|fcmpezseq s0) +0[0-9a-f]+ <[^>]+> 0eb50bc0 (vcmpeeq\.f64 d0, #0.0|fcmpezdeq d0) +0[0-9a-f]+ <[^>]+> eebd0ae0 (vcvt\.s32\.f32|ftosizs) s0, s1 +0[0-9a-f]+ <[^>]+> eebc0ae0 (vcvt\.u32\.f32|ftouizs) s0, s1 +0[0-9a-f]+ <[^>]+> eebd0bc1 (vcvt\.s32\.f64|ftosizd) s0, d1 +0[0-9a-f]+ <[^>]+> eebc0bc1 (vcvt\.u32\.f64|ftouizd) s0, d1 +0[0-9a-f]+ <[^>]+> 0ebd0ae0 (vcvteq\.s32\.f32|ftosizseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0ae0 (vcvteq\.u32\.f32|ftouizseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0bc1 (vcvteq\.s32\.f64|ftosizdeq) s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0bc1 (vcvteq\.u32\.f64|ftouizdeq) s0, d1 +0[0-9a-f]+ <[^>]+> eebd0ae0 (vcvt\.s32\.f32|ftosis) s0, s1 +0[0-9a-f]+ <[^>]+> eebc0ae0 (vcvt\.u32\.f32|ftouis) s0, s1 +0[0-9a-f]+ <[^>]+> eeb80ae0 (vcvt\.f32\.s32|fsitos) s0, s1 +0[0-9a-f]+ <[^>]+> eeb80a60 (vcvt\.f32\.u32|fuitos) s0, s1 +0[0-9a-f]+ <[^>]+> eeb70bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1 +0[0-9a-f]+ <[^>]+> eeb70ae0 (vcvt\.f64\.f32|fcvtds) d0, s1 +0[0-9a-f]+ <[^>]+> eebd0bc1 (vcvt\.s32\.f64|ftosid) s0, d1 +0[0-9a-f]+ <[^>]+> eebc0bc1 (vcvt\.u32\.f64|ftouid) s0, d1 +0[0-9a-f]+ <[^>]+> eeb80be0 (vcvt\.f64\.s32|fsitod) d0, s1 +0[0-9a-f]+ <[^>]+> eeb80b60 (vcvt\.f64\.u32|fuitod) d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0ae0 (vcvteq\.s32\.f32|ftosiseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0ebc0ae0 (vcvteq\.u32\.f32|ftouiseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80ae0 (vcvteq\.f32\.s32|fsitoseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb80a60 (vcvteq\.f32\.u32|fuitoseq) s0, s1 +0[0-9a-f]+ <[^>]+> 0eb70bc1 (vcvteq\.f32\.f64|fcvtsdeq) s0, d1 +0[0-9a-f]+ <[^>]+> 0eb70ae0 (vcvteq\.f64\.f32|fcvtdseq) d0, s1 +0[0-9a-f]+ <[^>]+> 0ebd0bc1 (vcvteq\.s32\.f64|ftosideq) s0, d1 +0[0-9a-f]+ <[^>]+> 0ebc0bc1 (vcvteq\.u32\.f64|ftouideq) s0, d1 +0[0-9a-f]+ <[^>]+> 0eb80be0 (vcvteq\.f64\.s32|fsitodeq) d0, s1 +0[0-9a-f]+ <[^>]+> 0eb80b60 (vcvteq\.f64\.u32|fuitodeq) d0, s1 +0[0-9a-f]+ <[^>]+> eebe0aef (vcvt\.s32\.f32 s0, s0, #1|ftosls s0, #1) +0[0-9a-f]+ <[^>]+> eebf0aef (vcvt\.u32\.f32 s0, s0, #1|ftouls s0, #1) +0[0-9a-f]+ <[^>]+> eeba0aef (vcvt\.f32\.s32 s0, s0, #1|fsltos s0, #1) +0[0-9a-f]+ <[^>]+> eebb0aef (vcvt\.f32\.u32 s0, s0, #1|fultos s0, #1) +0[0-9a-f]+ <[^>]+> eebe0bef (vcvt\.s32\.f64 d0, d0, #1|ftosld d0, #1) +0[0-9a-f]+ <[^>]+> eebf0bef (vcvt\.u32\.f64 d0, d0, #1|ftould d0, #1) +0[0-9a-f]+ <[^>]+> eeba0bef (vcvt\.f64\.s32 d0, d0, #1|fsltod d0, #1) +0[0-9a-f]+ <[^>]+> eebb0bef (vcvt\.f64\.u32 d0, d0, #1|fultod d0, #1) +0[0-9a-f]+ <[^>]+> eeba0a67 (vcvt\.f32\.s16 s0, s0, #1|fshtos s0, #1) +0[0-9a-f]+ <[^>]+> eebb0a67 (vcvt\.f32\.u16 s0, s0, #1|fuhtos s0, #1) +0[0-9a-f]+ <[^>]+> eeba0b67 (vcvt\.f64\.s16 d0, d0, #1|fshtod d0, #1) +0[0-9a-f]+ <[^>]+> eebb0b67 (vcvt\.f64\.u16 d0, d0, #1|fuhtod d0, #1) +0[0-9a-f]+ <[^>]+> eebe0a67 (vcvt\.s16\.f32 s0, s0, #1|ftoshs s0, #1) +0[0-9a-f]+ <[^>]+> eebf0a67 (vcvt\.u16\.f32 s0, s0, #1|ftouhs s0, #1) +0[0-9a-f]+ <[^>]+> eebe0b67 (vcvt\.s16\.f64 d0, d0, #1|ftoshd d0, #1) +0[0-9a-f]+ <[^>]+> eebf0b67 (vcvt\.u16\.f64 d0, d0, #1|ftouhd d0, #1) +0[0-9a-f]+ <[^>]+> 0ebe0aef (vcvteq\.s32\.f32 s0, s0, #1|ftoslseq s0, #1) +0[0-9a-f]+ <[^>]+> 0ebf0aef (vcvteq\.u32\.f32 s0, s0, #1|ftoulseq s0, #1) +0[0-9a-f]+ <[^>]+> 0eba0aef (vcvteq\.f32\.s32 s0, s0, #1|fsltoseq s0, #1) +0[0-9a-f]+ <[^>]+> 0ebb0aef (vcvteq\.f32\.u32 s0, s0, #1|fultoseq s0, #1) +0[0-9a-f]+ <[^>]+> 0ebe0bef (vcvteq\.s32\.f64 d0, d0, #1|ftosldeq d0, #1) +0[0-9a-f]+ <[^>]+> 0ebf0bef (vcvteq\.u32\.f64 d0, d0, #1|ftouldeq d0, #1) +0[0-9a-f]+ <[^>]+> 0eba0bef (vcvteq\.f64\.s32 d0, d0, #1|fsltodeq d0, #1) +0[0-9a-f]+ <[^>]+> 0ebb0bef (vcvteq\.f64\.u32 d0, d0, #1|fultodeq d0, #1) +0[0-9a-f]+ <[^>]+> 0eba0a67 (vcvteq\.f32\.s16 s0, s0, #1|fshtoseq s0, #1) +0[0-9a-f]+ <[^>]+> 0ebb0a67 (vcvteq\.f32\.u16 s0, s0, #1|fuhtoseq s0, #1) +0[0-9a-f]+ <[^>]+> 0eba0b67 (vcvteq\.f64\.s16 d0, d0, #1|fshtodeq d0, #1) +0[0-9a-f]+ <[^>]+> 0ebb0b67 (vcvteq\.f64\.u16 d0, d0, #1|fuhtodeq d0, #1) +0[0-9a-f]+ <[^>]+> 0ebe0a67 (vcvteq\.s16\.f32 s0, s0, #1|ftoshseq s0, #1) +0[0-9a-f]+ <[^>]+> 0ebf0a67 (vcvteq\.u16\.f32 s0, s0, #1|ftouhseq s0, #1) +0[0-9a-f]+ <[^>]+> 0ebe0b67 (vcvteq\.s16\.f64 d0, d0, #1|ftoshdeq d0, #1) +0[0-9a-f]+ <[^>]+> 0ebf0b67 (vcvteq\.u16\.f64 d0, d0, #1|ftouhdeq d0, #1) +0[0-9a-f]+ <[^>]+> ecd01a04 (vldmia|fldmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd01a04 (vldmia|fldmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf01a04 (vldmia|fldmias) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed701a04 (vldmdb|fldmdbs) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec903b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb03b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed303b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cd01a04 (vldmiaeq|fldmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cd01a04 (vldmiaeq|fldmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cf01a04 (vldmiaeq|fldmiaseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d701a04 (vldmdbeq|fldmdbseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c903b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cb03b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d303b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc01a04 (vstmia|fstmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc01a04 (vstmia|fstmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece01a04 (vstmia|fstmias) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed601a04 (vstmdb|fstmdbs) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec803b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca03b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed203b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0cc01a04 (vstmiaeq|fstmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0cc01a04 (vstmiaeq|fstmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> 0ce01a04 (vstmiaeq|fstmiaseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0d601a04 (vstmdbeq|fstmdbseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0c803b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> 0ca03b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> 0d203b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed900a01 (vldr|flds) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed900b01 (vldr|vldr) d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900a01 (vldreq|fldseq) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d900b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800a01 (vstr|fsts) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed800b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800a01 (vstreq|fstseq) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> 0d800b01 vstreq d0, \[r0, #4\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax.s new file mode 100644 index 00000000..7c0bc633 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax.s @@ -0,0 +1,2 @@ + .arm + .include "vfp-neon-syntax-inc.s" diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d new file mode 100644 index 00000000..40ff132b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax_t2.d @@ -0,0 +1,219 @@ +# name: VFP Neon-style syntax, Thumb mode +# as: -mfpu=vfp3 -I$srcdir/$subdir +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmov\.f32|fcpys) s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 (vmov\.f64|fcpyd) d0, d1 +0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmov\.f32|fconsts) s0, #80.* +0[0-9a-f]+ <[^>]+> eeb7 0b00 (vmov\.f64|fconstd) d0, #112.* +0[0-9a-f]+ <[^>]+> ee10 0a90 (vmov|fmrs) r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 (vmov|fmsr) s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 (vmov r0, r1, s2, s3|fmrrs r0, r1, {s2, s3}) +0[0-9a-f]+ <[^>]+> ec44 2a10 (vmov s0, s1, r2, r4|fmsrr {s0, s1}, r2, r4) +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb0 0a60 (vmoveq\.f32|fcpyseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0b41 (vmoveq\.f64|fcpydeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb5 0a00 (vmoveq\.f32|fconstseq) s0, #80.* +0[0-9a-f]+ <[^>]+> eeb7 0b00 (vmoveq\.f64|fconstdeq) d0, #112.* +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ee10 0a90 (vmoveq|fmrseq) r0, s1 +0[0-9a-f]+ <[^>]+> ee00 1a10 (vmoveq|fmsreq) s0, r1 +0[0-9a-f]+ <[^>]+> ec51 0a11 (vmoveq r0, r1, s2, s3|fmrrseq r0, r1, {s2, s3}) +0[0-9a-f]+ <[^>]+> ec44 2a10 (vmoveq s0, s1, r2, r4|fmsrreq {s0, s1}, r2, r4) +0[0-9a-f]+ <[^>]+> eeb1 0ae0 (vsqrt\.f32|fsqrts) s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 (vsqrt\.f64|fsqrtd) d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0ae0 (vsqrteq\.f32|fsqrtseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0bc1 (vsqrteq\.f64|fsqrtdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb0 0ae0 (vabs\.f32|fabss) s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 (vabs\.f64|fabsd) d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb0 0ae0 (vabseq\.f32|fabsseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb0 0bc1 (vabseq\.f64|fabsdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb1 0a60 (vneg\.f32|fnegs) s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 (vneg\.f64|fnegd) d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb1 0a60 (vnegeq\.f32|fnegseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb1 0b41 (vnegeq\.f64|fnegdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0a60 (vcmp\.f32|fcmps) s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 (vcmp\.f64|fcmpd) d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0a60 (vcmpeq\.f32|fcmpseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0b41 (vcmpeq\.f64|fcmpdeq) d0, d1 +0[0-9a-f]+ <[^>]+> eeb4 0ae0 (vcmpe\.f32|fcmpes) s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 (vcmpe\.f64|fcmped) d0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb4 0ae0 (vcmpeeq\.f32|fcmpeseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb4 0bc1 (vcmpeeq\.f64|fcmpedeq) d0, d1 +0[0-9a-f]+ <[^>]+> ee20 0ac1 (vnmul\.f32|fnmuls) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 (vnmul\.f64|fnmuld) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0ac1 (vnmuleq\.f32|fnmulseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b42 (vnmuleq\.f64|fnmuldeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0ac1 (vnmla\.f32|fnmacs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 (vnmla\.f64|fnmacd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0ac1 (vnmlaeq\.f32|fnmacseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b42 (vnmlaeq\.f64|fnmacdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee10 0a81 (vnmls\.f32|fnmscs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 (vnmls\.f64|fnmscd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee10 0a81 (vnmlseq\.f32|fnmscseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee11 0b02 (vnmlseq\.f64|fnmscdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee20 0a81 (vmul\.f32|fmuls) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 (vmul\.f64|fmuld) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee20 0a81 (vmuleq\.f32|fmulseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee21 0b02 (vmuleq\.f64|fmuldeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0a81 (vmla\.f32|fmacs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 (vmla\.f64|fmacd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0a81 (vmlaeq\.f32|fmacseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b02 (vmlaeq\.f64|fmacdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee00 0ac1 (vmls\.f32|fmscs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 (vmls\.f64|fmscd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee00 0ac1 (vmlseq\.f32|fmscseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee01 0b42 (vmlseq\.f64|fmscdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0a81 (vadd\.f32|fadds) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 (vadd\.f64|faddd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0a81 (vaddeq\.f32|faddseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b02 (vaddeq\.f64|fadddeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee30 0ac1 (vsub\.f32|fsubs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 (vsub\.f64|fsubd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee30 0ac1 (vsubeq\.f32|fsubseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee31 0b42 (vsubeq\.f64|fsubdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> ee80 0a81 (vdiv\.f32|fdivs) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 (vdiv\.f64|fdivd) d0, d1, d2 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ee80 0a81 (vdiveq\.f32|fdivseq) s0, s1, s2 +0[0-9a-f]+ <[^>]+> ee81 0b02 (vdiveq\.f64|fdivdeq) d0, d1, d2 +0[0-9a-f]+ <[^>]+> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0) +0[0-9a-f]+ <[^>]+> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0) +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0a40 (vcmpeq\.f32 s0, #0.0|fcmpzseq s0) +0[0-9a-f]+ <[^>]+> eeb5 0b40 (vcmpeq\.f64 d0, #0.0|fcmpzdeq d0) +0[0-9a-f]+ <[^>]+> eeb5 0ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0) +0[0-9a-f]+ <[^>]+> eeb5 0bc0 (vcmpe\.f64 d0, #0.0|fcmpezd d0) +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb5 0ac0 (vcmpeeq\.f32 s0, #0.0|fcmpezseq s0) +0[0-9a-f]+ <[^>]+> eeb5 0bc0 (vcmpeeq\.f64 d0, #0.0|fcmpezdeq d0) +0[0-9a-f]+ <[^>]+> eebd 0ae0 (vcvt\.s32\.f32|ftosizs) s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvt\.u32\.f32|ftouizs) s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvt\.s32\.f64|ftosizd) s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvt\.u32\.f64|ftouizd) s0, d1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0ae0 (vcvteq\.s32\.f32|ftosizseq) s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvteq\.u32\.f32|ftouizseq) s0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvteq\.s32\.f64|ftosizdeq) s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvteq\.u32\.f64|ftouizdeq) s0, d1 +0[0-9a-f]+ <[^>]+> eebd 0ae0 (vcvt\.s32\.f32|ftosis) s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvt\.u32\.f32|ftouis) s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 (vcvt\.f32\.s32|fsitos) s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 (vcvt\.f32\.u32|fuitos) s0, s1 +0[0-9a-f]+ <[^>]+> eeb7 0bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 (vcvt\.f64\.f32|fcvtds) d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvt\.s32\.f64|ftosid) s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvt\.u32\.f64|ftouid) s0, d1 +0[0-9a-f]+ <[^>]+> eeb8 0be0 (vcvt\.f64\.s32|fsitod) d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 (vcvt\.f64\.u32|fuitod) d0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebd 0ae0 (vcvteq\.s32\.f32|ftosiseq) s0, s1 +0[0-9a-f]+ <[^>]+> eebc 0ae0 (vcvteq\.u32\.f32|ftouiseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0ae0 (vcvteq\.f32\.s32|fsitoseq) s0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0a60 (vcvteq\.f32\.u32|fuitoseq) s0, s1 +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeb7 0bc1 (vcvteq\.f32\.f64|fcvtsdeq) s0, d1 +0[0-9a-f]+ <[^>]+> eeb7 0ae0 (vcvteq\.f64\.f32|fcvtdseq) d0, s1 +0[0-9a-f]+ <[^>]+> eebd 0bc1 (vcvteq\.s32\.f64|ftosideq) s0, d1 +0[0-9a-f]+ <[^>]+> eebc 0bc1 (vcvteq\.u32\.f64|ftouideq) s0, d1 +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> eeb8 0be0 (vcvteq\.f64\.s32|fsitodeq) d0, s1 +0[0-9a-f]+ <[^>]+> eeb8 0b60 (vcvteq\.f64\.u32|fuitodeq) d0, s1 +0[0-9a-f]+ <[^>]+> eebe 0aef (vcvt\.s32\.f32 s0, s0, #1|ftosls s0, #1) +0[0-9a-f]+ <[^>]+> eebf 0aef (vcvt\.u32\.f32 s0, s0, #1|ftouls s0, #1) +0[0-9a-f]+ <[^>]+> eeba 0aef (vcvt\.f32\.s32 s0, s0, #1|fsltos s0, #1) +0[0-9a-f]+ <[^>]+> eebb 0aef (vcvt\.f32\.u32 s0, s0, #1|fultos s0, #1) +0[0-9a-f]+ <[^>]+> eebe 0bef (vcvt\.s32\.f64 d0, d0, #1|ftosld d0, #1) +0[0-9a-f]+ <[^>]+> eebf 0bef (vcvt\.u32\.f64 d0, d0, #1|ftould d0, #1) +0[0-9a-f]+ <[^>]+> eeba 0bef (vcvt\.f64\.s32 d0, d0, #1|fsltod d0, #1) +0[0-9a-f]+ <[^>]+> eebb 0bef (vcvt\.f64\.u32 d0, d0, #1|fultod d0, #1) +0[0-9a-f]+ <[^>]+> eeba 0a67 (vcvt\.f32\.s16 s0, s0, #1|fshtos s0, #1) +0[0-9a-f]+ <[^>]+> eebb 0a67 (vcvt\.f32\.u16 s0, s0, #1|fuhtos s0, #1) +0[0-9a-f]+ <[^>]+> eeba 0b67 (vcvt\.f64\.s16 d0, d0, #1|fshtod d0, #1) +0[0-9a-f]+ <[^>]+> eebb 0b67 (vcvt\.f64\.u16 d0, d0, #1|fuhtod d0, #1) +0[0-9a-f]+ <[^>]+> eebe 0a67 (vcvt\.s16\.f32 s0, s0, #1|ftoshs s0, #1) +0[0-9a-f]+ <[^>]+> eebf 0a67 (vcvt\.u16\.f32 s0, s0, #1|ftouhs s0, #1) +0[0-9a-f]+ <[^>]+> eebe 0b67 (vcvt\.s16\.f64 d0, d0, #1|ftoshd d0, #1) +0[0-9a-f]+ <[^>]+> eebf 0b67 (vcvt\.u16\.f64 d0, d0, #1|ftouhd d0, #1) +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0aef (vcvteq\.s32\.f32 s0, s0, #1|ftoslseq s0, #1) +0[0-9a-f]+ <[^>]+> eebf 0aef (vcvteq\.u32\.f32 s0, s0, #1|ftoulseq s0, #1) +0[0-9a-f]+ <[^>]+> eeba 0aef (vcvteq\.f32\.s32 s0, s0, #1|fsltoseq s0, #1) +0[0-9a-f]+ <[^>]+> eebb 0aef (vcvteq\.f32\.u32 s0, s0, #1|fultoseq s0, #1) +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0bef (vcvteq\.s32\.f64 d0, d0, #1|ftosldeq d0, #1) +0[0-9a-f]+ <[^>]+> eebf 0bef (vcvteq\.u32\.f64 d0, d0, #1|ftouldeq d0, #1) +0[0-9a-f]+ <[^>]+> eeba 0bef (vcvteq\.f64\.s32 d0, d0, #1|fsltodeq d0, #1) +0[0-9a-f]+ <[^>]+> eebb 0bef (vcvteq\.f64\.u32 d0, d0, #1|fultodeq d0, #1) +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eeba 0a67 (vcvteq\.f32\.s16 s0, s0, #1|fshtoseq s0, #1) +0[0-9a-f]+ <[^>]+> eebb 0a67 (vcvteq\.f32\.u16 s0, s0, #1|fuhtoseq s0, #1) +0[0-9a-f]+ <[^>]+> eeba 0b67 (vcvteq\.f64\.s16 d0, d0, #1|fshtodeq d0, #1) +0[0-9a-f]+ <[^>]+> eebb 0b67 (vcvteq\.f64\.u16 d0, d0, #1|fuhtodeq d0, #1) +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> eebe 0a67 (vcvteq\.s16\.f32 s0, s0, #1|ftoshseq s0, #1) +0[0-9a-f]+ <[^>]+> eebf 0a67 (vcvteq\.u16\.f32 s0, s0, #1|ftouhseq s0, #1) +0[0-9a-f]+ <[^>]+> eebe 0b67 (vcvteq\.s16\.f64 d0, d0, #1|ftoshdeq d0, #1) +0[0-9a-f]+ <[^>]+> eebf 0b67 (vcvteq\.u16\.f64 d0, d0, #1|ftouhdeq d0, #1) +0[0-9a-f]+ <[^>]+> ecd0 1a04 (vldmia|fldmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 (vldmia|fldmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 (vldmia|fldmias) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 (vldmdb|fldmdbs) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecd0 1a04 (vldmiaeq|fldmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecd0 1a04 (vldmiaeq|fldmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecf0 1a04 (vldmiaeq|fldmiaseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed70 1a04 (vldmdbeq|fldmdbseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec90 3b08 vldmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ecb0 3b08 vldmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed30 3b08 vldmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 (vstmia|fstmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 (vstmia|fstmias) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 (vstmia|fstmias) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 (vstmdb|fstmdbs) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmia r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmia r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdb r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ecc0 1a04 (vstmiaeq|fstmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ecc0 1a04 (vstmiaeq|fstmiaseq) r0, {s3-s6} +0[0-9a-f]+ <[^>]+> ece0 1a04 (vstmiaeq|fstmiaseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> ed60 1a04 (vstmdbeq|fstmdbseq) r0!, {s3-s6} +0[0-9a-f]+ <[^>]+> bf01 itttt eq +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> ec80 3b08 vstmiaeq r0, {d3-d6} +0[0-9a-f]+ <[^>]+> eca0 3b08 vstmiaeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed20 3b08 vstmdbeq r0!, {d3-d6} +0[0-9a-f]+ <[^>]+> ed90 0a01 (vldr|flds) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed90 0a01 (vldreq|fldseq) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed90 0b01 vldreq d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0a01 (vstr|fsts) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstr d0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> bf04 itt eq +0[0-9a-f]+ <[^>]+> ed80 0a01 (vstreq|fstseq) s0, \[r0, #4\] +0[0-9a-f]+ <[^>]+> ed80 0b01 vstreq d0, \[r0, #4\] diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s new file mode 100644 index 00000000..00f78d01 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp-neon-syntax_t2.s @@ -0,0 +1,2 @@ + .thumb + .include "vfp-neon-syntax-inc.s" diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1.d b/binutils-2.25/gas/testsuite/gas/arm/vfp1.d new file mode 100644 index 00000000..a7a127a3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1.d @@ -0,0 +1,193 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: VFP Double-precision instructions +#as: -mfpu=vfp + +# Test the ARM VFP Double Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eeb40bc0 (vcmpe\.f64|fcmped) d0, d0 +0+004 <[^>]*> eeb50bc0 (vcmpe\.f64 d0, #0.0|fcmpezd d0) +0+008 <[^>]*> eeb40b40 (vcmp\.f64|fcmpd) d0, d0 +0+00c <[^>]*> eeb50b40 (vcmp\.f64 d0, #0.0|fcmpzd d0) +0+010 <[^>]*> eeb00bc0 (vabs\.f64|fabsd) d0, d0 +0+014 <[^>]*> eeb00b40 (vmov\.f64|fcpyd) d0, d0 +0+018 <[^>]*> eeb10b40 (vneg\.f64|fnegd) d0, d0 +0+01c <[^>]*> eeb10bc0 (vsqrt\.f64|fsqrtd) d0, d0 +0+020 <[^>]*> ee300b00 (vadd\.f64|faddd) d0, d0, d0 +0+024 <[^>]*> ee800b00 (vdiv\.f64|fdivd) d0, d0, d0 +0+028 <[^>]*> ee000b00 (vmla\.f64|fmacd) d0, d0, d0 +0+02c <[^>]*> ee100b00 (vnmls\.f64|fmscd) d0, d0, d0 +0+030 <[^>]*> ee200b00 (vmul\.f64|fmuld) d0, d0, d0 +0+034 <[^>]*> ee000b40 (vmls\.f64|fnmacd) d0, d0, d0 +0+038 <[^>]*> ee100b40 (vnmla\.f64|fnmscd) d0, d0, d0 +0+03c <[^>]*> ee200b40 (vnmul\.f64|fnmuld) d0, d0, d0 +0+040 <[^>]*> ee300b40 (vsub\.f64|fsubd) d0, d0, d0 +0+044 <[^>]*> ed900b00 vldr d0, \[r0\] +0+048 <[^>]*> ed800b00 vstr d0, \[r0\] +0+04c <[^>]*> ec900b02 vldmia r0, {d0} +0+050 <[^>]*> ec900b02 vldmia r0, {d0} +0+054 <[^>]*> ecb00b02 vldmia r0!, {d0} +0+058 <[^>]*> ecb00b02 vldmia r0!, {d0} +0+05c <[^>]*> ed300b02 vldmdb r0!, {d0} +0+060 <[^>]*> ed300b02 vldmdb r0!, {d0} +0+064 <[^>]*> ec800b02 vstmia r0, {d0} +0+068 <[^>]*> ec800b02 vstmia r0, {d0} +0+06c <[^>]*> eca00b02 vstmia r0!, {d0} +0+070 <[^>]*> eca00b02 vstmia r0!, {d0} +0+074 <[^>]*> ed200b02 vstmdb r0!, {d0} +0+078 <[^>]*> ed200b02 vstmdb r0!, {d0} +0+07c <[^>]*> eeb80bc0 (vcvt\.f64\.s32|fsitod) d0, s0 +0+080 <[^>]*> eeb80b40 (vcvt\.f64\.u32|fuitod) d0, s0 +0+084 <[^>]*> eebd0b40 (vcvtr\.s32\.f64|ftosid) s0, d0 +0+088 <[^>]*> eebd0bc0 (vcvt\.s32\.f64|ftosizd) s0, d0 +0+08c <[^>]*> eebc0b40 (vcvtr\.u32\.f64|ftouid) s0, d0 +0+090 <[^>]*> eebc0bc0 (vcvt\.u32\.f64|ftouizd) s0, d0 +0+094 <[^>]*> eeb70ac0 (vcvt\.f64\.f32|fcvtds) d0, s0 +0+098 <[^>]*> eeb70bc0 (vcvt\.f32\.f64|fcvtsd) s0, d0 +0+09c <[^>]*> ee300b10 vmov\.32 r0, d0\[1\] +0+0a0 <[^>]*> ee100b10 vmov\.32 r0, d0\[0\] +0+0a4 <[^>]*> ee200b10 vmov\.32 d0\[1\], r0 +0+0a8 <[^>]*> ee000b10 vmov\.32 d0\[0\], r0 +0+0ac <[^>]*> eeb51b40 (vcmp\.f64 d1, #0.0|fcmpzd d1) +0+0b0 <[^>]*> eeb52b40 (vcmp\.f64 d2, #0.0|fcmpzd d2) +0+0b4 <[^>]*> eeb5fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15) +0+0b8 <[^>]*> eeb40b41 (vcmp\.f64|fcmpd) d0, d1 +0+0bc <[^>]*> eeb40b42 (vcmp\.f64|fcmpd) d0, d2 +0+0c0 <[^>]*> eeb40b4f (vcmp\.f64|fcmpd) d0, d15 +0+0c4 <[^>]*> eeb41b40 (vcmp\.f64|fcmpd) d1, d0 +0+0c8 <[^>]*> eeb42b40 (vcmp\.f64|fcmpd) d2, d0 +0+0cc <[^>]*> eeb4fb40 (vcmp\.f64|fcmpd) d15, d0 +0+0d0 <[^>]*> eeb45b4c (vcmp\.f64|fcmpd) d5, d12 +0+0d4 <[^>]*> eeb10b41 (vneg\.f64|fnegd) d0, d1 +0+0d8 <[^>]*> eeb10b42 (vneg\.f64|fnegd) d0, d2 +0+0dc <[^>]*> eeb10b4f (vneg\.f64|fnegd) d0, d15 +0+0e0 <[^>]*> eeb11b40 (vneg\.f64|fnegd) d1, d0 +0+0e4 <[^>]*> eeb12b40 (vneg\.f64|fnegd) d2, d0 +0+0e8 <[^>]*> eeb1fb40 (vneg\.f64|fnegd) d15, d0 +0+0ec <[^>]*> eeb1cb45 (vneg\.f64|fnegd) d12, d5 +0+0f0 <[^>]*> ee300b01 (vadd\.f64|faddd) d0, d0, d1 +0+0f4 <[^>]*> ee300b02 (vadd\.f64|faddd) d0, d0, d2 +0+0f8 <[^>]*> ee300b0f (vadd\.f64|faddd) d0, d0, d15 +0+0fc <[^>]*> ee310b00 (vadd\.f64|faddd) d0, d1, d0 +0+100 <[^>]*> ee320b00 (vadd\.f64|faddd) d0, d2, d0 +0+104 <[^>]*> ee3f0b00 (vadd\.f64|faddd) d0, d15, d0 +0+108 <[^>]*> ee301b00 (vadd\.f64|faddd) d1, d0, d0 +0+10c <[^>]*> ee302b00 (vadd\.f64|faddd) d2, d0, d0 +0+110 <[^>]*> ee30fb00 (vadd\.f64|faddd) d15, d0, d0 +0+114 <[^>]*> ee39cb05 (vadd\.f64|faddd) d12, d9, d5 +0+118 <[^>]*> eeb70ae0 (vcvt\.f64\.f32|fcvtds) d0, s1 +0+11c <[^>]*> eeb70ac1 (vcvt\.f64\.f32|fcvtds) d0, s2 +0+120 <[^>]*> eeb70aef (vcvt\.f64\.f32|fcvtds) d0, s31 +0+124 <[^>]*> eeb71ac0 (vcvt\.f64\.f32|fcvtds) d1, s0 +0+128 <[^>]*> eeb72ac0 (vcvt\.f64\.f32|fcvtds) d2, s0 +0+12c <[^>]*> eeb7fac0 (vcvt\.f64\.f32|fcvtds) d15, s0 +0+130 <[^>]*> eef70bc0 (vcvt\.f32\.f64|fcvtsd) s1, d0 +0+134 <[^>]*> eeb71bc0 (vcvt\.f32\.f64|fcvtsd) s2, d0 +0+138 <[^>]*> eef7fbc0 (vcvt\.f32\.f64|fcvtsd) s31, d0 +0+13c <[^>]*> eeb70bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1 +0+140 <[^>]*> eeb70bc2 (vcvt\.f32\.f64|fcvtsd) s0, d2 +0+144 <[^>]*> eeb70bcf (vcvt\.f32\.f64|fcvtsd) s0, d15 +0+148 <[^>]*> ee301b10 vmov\.32 r1, d0\[1\] +0+14c <[^>]*> ee30eb10 vmov\.32 lr, d0\[1\] +0+150 <[^>]*> ee310b10 vmov\.32 r0, d1\[1\] +0+154 <[^>]*> ee320b10 vmov\.32 r0, d2\[1\] +0+158 <[^>]*> ee3f0b10 vmov\.32 r0, d15\[1\] +0+15c <[^>]*> ee101b10 vmov\.32 r1, d0\[0\] +0+160 <[^>]*> ee10eb10 vmov\.32 lr, d0\[0\] +0+164 <[^>]*> ee110b10 vmov\.32 r0, d1\[0\] +0+168 <[^>]*> ee120b10 vmov\.32 r0, d2\[0\] +0+16c <[^>]*> ee1f0b10 vmov\.32 r0, d15\[0\] +0+170 <[^>]*> ee201b10 vmov\.32 d0\[1\], r1 +0+174 <[^>]*> ee20eb10 vmov\.32 d0\[1\], lr +0+178 <[^>]*> ee210b10 vmov\.32 d1\[1\], r0 +0+17c <[^>]*> ee220b10 vmov\.32 d2\[1\], r0 +0+180 <[^>]*> ee2f0b10 vmov\.32 d15\[1\], r0 +0+184 <[^>]*> ee001b10 vmov\.32 d0\[0\], r1 +0+188 <[^>]*> ee00eb10 vmov\.32 d0\[0\], lr +0+18c <[^>]*> ee010b10 vmov\.32 d1\[0\], r0 +0+190 <[^>]*> ee020b10 vmov\.32 d2\[0\], r0 +0+194 <[^>]*> ee0f0b10 vmov\.32 d15\[0\], r0 +0+198 <[^>]*> ed910b00 vldr d0, \[r1\] +0+19c <[^>]*> ed9e0b00 vldr d0, \[lr\] +0+1a0 <[^>]*> ed900b00 vldr d0, \[r0\] +0+1a4 <[^>]*> ed900bff vldr d0, \[r0, #1020\].* +0+1a8 <[^>]*> ed100bff vldr d0, \[r0, #-1020\].* +0+1ac <[^>]*> ed901b00 vldr d1, \[r0\] +0+1b0 <[^>]*> ed902b00 vldr d2, \[r0\] +0+1b4 <[^>]*> ed90fb00 vldr d15, \[r0\] +0+1b8 <[^>]*> ed8ccbc9 vstr d12, \[ip, #804\].* +0+1bc <[^>]*> ec901b02 vldmia r0, {d1} +0+1c0 <[^>]*> ec902b02 vldmia r0, {d2} +0+1c4 <[^>]*> ec90fb02 vldmia r0, {d15} +0+1c8 <[^>]*> ec900b04 vldmia r0, {d0-d1} +0+1cc <[^>]*> ec900b06 vldmia r0, {d0-d2} +0+1d0 <[^>]*> ec900b20 vldmia r0, {d0-d15} +0+1d4 <[^>]*> ec901b1e vldmia r0, {d1-d15} +0+1d8 <[^>]*> ec902b1c vldmia r0, {d2-d15} +0+1dc <[^>]*> ec90eb04 vldmia r0, {d14-d15} +0+1e0 <[^>]*> ec910b02 vldmia r1, {d0} +0+1e4 <[^>]*> ec9e0b02 vldmia lr, {d0} +0+1e8 <[^>]*> eeb50b40 (vcmp\.f64 d0, #0.0|fcmpzd d0) +0+1ec <[^>]*> eeb51b40 (vcmp\.f64 d1, #0.0|fcmpzd d1) +0+1f0 <[^>]*> eeb52b40 (vcmp\.f64 d2, #0.0|fcmpzd d2) +0+1f4 <[^>]*> eeb53b40 (vcmp\.f64 d3, #0.0|fcmpzd d3) +0+1f8 <[^>]*> eeb54b40 (vcmp\.f64 d4, #0.0|fcmpzd d4) +0+1fc <[^>]*> eeb55b40 (vcmp\.f64 d5, #0.0|fcmpzd d5) +0+200 <[^>]*> eeb56b40 (vcmp\.f64 d6, #0.0|fcmpzd d6) +0+204 <[^>]*> eeb57b40 (vcmp\.f64 d7, #0.0|fcmpzd d7) +0+208 <[^>]*> eeb58b40 (vcmp\.f64 d8, #0.0|fcmpzd d8) +0+20c <[^>]*> eeb59b40 (vcmp\.f64 d9, #0.0|fcmpzd d9) +0+210 <[^>]*> eeb5ab40 (vcmp\.f64 d10, #0.0|fcmpzd d10) +0+214 <[^>]*> eeb5bb40 (vcmp\.f64 d11, #0.0|fcmpzd d11) +0+218 <[^>]*> eeb5cb40 (vcmp\.f64 d12, #0.0|fcmpzd d12) +0+21c <[^>]*> eeb5db40 (vcmp\.f64 d13, #0.0|fcmpzd d13) +0+220 <[^>]*> eeb5eb40 (vcmp\.f64 d14, #0.0|fcmpzd d14) +0+224 <[^>]*> eeb5fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15) +0+228 <[^>]*> 0eb41bcf (vcmpeeq\.f64|fcmpedeq) d1, d15 +0+22c <[^>]*> 0eb52bc0 (vcmpeeq\.f64 d2, #0.0|fcmpezdeq d2) +0+230 <[^>]*> 0eb43b4e (vcmpeq\.f64|fcmpdeq) d3, d14 +0+234 <[^>]*> 0eb54b40 (vcmpeq\.f64 d4, #0.0|fcmpzdeq d4) +0+238 <[^>]*> 0eb05bcd (vabseq\.f64|fabsdeq) d5, d13 +0+23c <[^>]*> 0eb06b4c (vmoveq\.f64|fcpydeq) d6, d12 +0+240 <[^>]*> 0eb17b4b (vnegeq\.f64|fnegdeq) d7, d11 +0+244 <[^>]*> 0eb18bca (vsqrteq\.f64|fsqrtdeq) d8, d10 +0+248 <[^>]*> 0e319b0f (vaddeq\.f64|fadddeq) d9, d1, d15 +0+24c <[^>]*> 0e832b0e (vdiveq\.f64|fdivdeq) d2, d3, d14 +0+250 <[^>]*> 0e0d4b0c (vmlaeq\.f64|fmacdeq) d4, d13, d12 +0+254 <[^>]*> 0e165b0b (vnmlseq\.f64|fmscdeq) d5, d6, d11 +0+258 <[^>]*> 0e2a7b09 (vmuleq\.f64|fmuldeq) d7, d10, d9 +0+25c <[^>]*> 0e098b4a (vmlseq\.f64|fnmacdeq) d8, d9, d10 +0+260 <[^>]*> 0e167b4b (vnmlaeq\.f64|fnmscdeq) d7, d6, d11 +0+264 <[^>]*> 0e245b4c (vnmuleq\.f64|fnmuldeq) d5, d4, d12 +0+268 <[^>]*> 0e3d3b4e (vsubeq\.f64|fsubdeq) d3, d13, d14 +0+26c <[^>]*> 0d952b00 vldreq d2, \[r5\] +0+270 <[^>]*> 0d8c1b00 vstreq d1, \[ip\] +0+274 <[^>]*> 0c911b02 vldmiaeq r1, {d1} +0+278 <[^>]*> 0c922b02 vldmiaeq r2, {d2} +0+27c <[^>]*> 0cb33b02 vldmiaeq r3!, {d3} +0+280 <[^>]*> 0cb44b02 vldmiaeq r4!, {d4} +0+284 <[^>]*> 0d355b02 vldmdbeq r5!, {d5} +0+288 <[^>]*> 0d366b02 vldmdbeq r6!, {d6} +0+28c <[^>]*> 0c87fb02 vstmiaeq r7, {d15} +0+290 <[^>]*> 0c88eb02 vstmiaeq r8, {d14} +0+294 <[^>]*> 0ca9db02 vstmiaeq r9!, {d13} +0+298 <[^>]*> 0caacb02 vstmiaeq sl!, {d12} +0+29c <[^>]*> 0d2bbb02 vstmdbeq fp!, {d11} +0+2a0 <[^>]*> 0d2cab02 vstmdbeq ip!, {d10} +0+2a4 <[^>]*> 0eb8fbe0 (vcvteq\.f64\.s32|fsitodeq) d15, s1 +0+2a8 <[^>]*> 0eb81b6f (vcvteq\.f64\.u32|fuitodeq) d1, s31 +0+2ac <[^>]*> 0efd0b4f (vcvtreq\.s32\.f64|ftosideq) s1, d15 +0+2b0 <[^>]*> 0efdfbc2 (vcvteq\.s32\.f64|ftosizdeq) s31, d2 +0+2b4 <[^>]*> 0efc7b42 (vcvtreq\.u32\.f64|ftouideq) s15, d2 +0+2b8 <[^>]*> 0efc5bc3 (vcvteq\.u32\.f64|ftouizdeq) s11, d3 +0+2bc <[^>]*> 0eb71ac5 (vcvteq\.f64\.f32|fcvtdseq) d1, s10 +0+2c0 <[^>]*> 0ef75bc1 (vcvteq\.f32\.f64|fcvtsdeq) s11, d1 +0+2c4 <[^>]*> 0e318b10 vmoveq\.32 r8, d1\[1\] +0+2c8 <[^>]*> 0e1f7b10 vmoveq\.32 r7, d15\[0\] +0+2cc <[^>]*> 0e21fb10 vmoveq\.32 d1\[1\], pc +0+2d0 <[^>]*> 0e0f1b10 vmoveq\.32 d15\[0\], r1 +0+2d4 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+2d8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+2dc <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1.s b/binutils-2.25/gas/testsuite/gas/arm/vfp1.s new file mode 100644 index 00000000..1a80877c --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1.s @@ -0,0 +1,284 @@ +@ VFP Instructions for D variants (Double precision) + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Most of these tests deliberatly use d0/r0 to avoid setting + @ any more bits than necessary. + + @ Comparison operations + + fcmped d0, d0 + fcmpezd d0 + fcmpd d0, d0 + fcmpzd d0 + + @ Monadic data operations + + fabsd d0, d0 + fcpyd d0, d0 + fnegd d0, d0 + fsqrtd d0, d0 + + @ Dyadic data operations + + faddd d0, d0, d0 + fdivd d0, d0, d0 + fmacd d0, d0, d0 + fmscd d0, d0, d0 + fmuld d0, d0, d0 + fnmacd d0, d0, d0 + fnmscd d0, d0, d0 + fnmuld d0, d0, d0 + fsubd d0, d0, d0 + + @ Load/store operations + + fldd d0, [r0] + fstd d0, [r0] + + @ Load/store multiple operations + + fldmiad r0, {d0} + fldmfdd r0, {d0} + fldmiad r0!, {d0} + fldmfdd r0!, {d0} + fldmdbd r0!, {d0} + fldmead r0!, {d0} + + fstmiad r0, {d0} + fstmead r0, {d0} + fstmiad r0!, {d0} + fstmead r0!, {d0} + fstmdbd r0!, {d0} + fstmfdd r0!, {d0} + + @ Conversion operations + + fsitod d0, s0 + fuitod d0, s0 + + ftosid s0, d0 + ftosizd s0, d0 + ftouid s0, d0 + ftouizd s0, d0 + + fcvtds d0, s0 + fcvtsd s0, d0 + + @ ARM from VFP operations + + fmrdh r0, d0 + fmrdl r0, d0 + + @ VFP From ARM operations + + fmdhr d0, r0 + fmdlr d0, r0 + + @ Now we test that the register fields are updated correctly for + @ each class of instruction. + + @ Single register operations (compare-zero): + + fcmpzd d1 + fcmpzd d2 + fcmpzd d15 + + @ Two register comparison operations: + + fcmpd d0, d1 + fcmpd d0, d2 + fcmpd d0, d15 + fcmpd d1, d0 + fcmpd d2, d0 + fcmpd d15, d0 + fcmpd d5, d12 + + @ Two register data operations (monadic) + + fnegd d0, d1 + fnegd d0, d2 + fnegd d0, d15 + fnegd d1, d0 + fnegd d2, d0 + fnegd d15, d0 + fnegd d12, d5 + + @ Three register data operations (dyadic) + + faddd d0, d0, d1 + faddd d0, d0, d2 + faddd d0, d0, d15 + faddd d0, d1, d0 + faddd d0, d2, d0 + faddd d0, d15, d0 + faddd d1, d0, d0 + faddd d2, d0, d0 + faddd d15, d0, d0 + faddd d12, d9, d5 + + @ Conversion operations + + fcvtds d0, s1 + fcvtds d0, s2 + fcvtds d0, s31 + fcvtds d1, s0 + fcvtds d2, s0 + fcvtds d15, s0 + fcvtsd s1, d0 + fcvtsd s2, d0 + fcvtsd s31, d0 + fcvtsd s0, d1 + fcvtsd s0, d2 + fcvtsd s0, d15 + + @ Move to VFP from ARM + + fmrdh r1, d0 + fmrdh r14, d0 + fmrdh r0, d1 + fmrdh r0, d2 + fmrdh r0, d15 + fmrdl r1, d0 + fmrdl r14, d0 + fmrdl r0, d1 + fmrdl r0, d2 + fmrdl r0, d15 + + @ Move to ARM from VFP + + fmdhr d0, r1 + fmdhr d0, r14 + fmdhr d1, r0 + fmdhr d2, r0 + fmdhr d15, r0 + fmdlr d0, r1 + fmdlr d0, r14 + fmdlr d1, r0 + fmdlr d2, r0 + fmdlr d15, r0 + + @ Load/store operations + + fldd d0, [r1] + fldd d0, [r14] + fldd d0, [r0, #0] + fldd d0, [r0, #1020] + fldd d0, [r0, #-1020] + fldd d1, [r0] + fldd d2, [r0] + fldd d15, [r0] + fstd d12, [r12, #804] + + @ Load/store multiple operations + + fldmiad r0, {d1} + fldmiad r0, {d2} + fldmiad r0, {d15} + fldmiad r0, {d0-d1} + fldmiad r0, {d0-d2} + fldmiad r0, {d0-d15} + fldmiad r0, {d1-d15} + fldmiad r0, {d2-d15} + fldmiad r0, {d14-d15} + fldmiad r1, {d0} + fldmiad r14, {d0} + + @ Check that we assemble all the register names correctly + + fcmpzd d0 + fcmpzd d1 + fcmpzd d2 + fcmpzd d3 + fcmpzd d4 + fcmpzd d5 + fcmpzd d6 + fcmpzd d7 + fcmpzd d8 + fcmpzd d9 + fcmpzd d10 + fcmpzd d11 + fcmpzd d12 + fcmpzd d13 + fcmpzd d14 + fcmpzd d15 + + @ Now we check the placement of the conditional execution substring. + @ On VFP this is always at the end of the instruction. + + @ Comparison operations + + fcmpedeq d1, d15 + fcmpezdeq d2 + fcmpdeq d3, d14 + fcmpzdeq d4 + + @ Monadic data operations + + fabsdeq d5, d13 + fcpydeq d6, d12 + fnegdeq d7, d11 + fsqrtdeq d8, d10 + + @ Dyadic data operations + + fadddeq d9, d1, d15 + fdivdeq d2, d3, d14 + fmacdeq d4, d13, d12 + fmscdeq d5, d6, d11 + fmuldeq d7, d10, d9 + fnmacdeq d8, d9, d10 + fnmscdeq d7, d6, d11 + fnmuldeq d5, d4, d12 + fsubdeq d3, d13, d14 + + @ Load/store operations + + flddeq d2, [r5] + fstdeq d1, [r12] + + @ Load/store multiple operations + + fldmiadeq r1, {d1} + fldmfddeq r2, {d2} + fldmiadeq r3!, {d3} + fldmfddeq r4!, {d4} + fldmdbdeq r5!, {d5} + fldmeadeq r6!, {d6} + + fstmiadeq r7, {d15} + fstmeadeq r8, {d14} + fstmiadeq r9!, {d13} + fstmeadeq r10!, {d12} + fstmdbdeq r11!, {d11} + fstmfddeq r12!, {d10} + + @ Conversion operations + + fsitodeq d15, s1 + fuitodeq d1, s31 + + ftosideq s1, d15 + ftosizdeq s31, d2 + ftouideq s15, d2 + ftouizdeq s11, d3 + + fcvtdseq d1, s10 + fcvtsdeq s11, d1 + + @ ARM from VFP operations + + fmrdheq r8, d1 + fmrdleq r7, d15 + + @ VFP From ARM operations + + fmdhreq d1, r15 + fmdlreq d15, r1 + + # Add three nop instructions to ensure that the + # output is 32-byte aligned as required for arm-aout. + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1_t2.d b/binutils-2.25/gas/testsuite/gas/arm/vfp1_t2.d new file mode 100644 index 00000000..757bf103 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1_t2.d @@ -0,0 +1,204 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Thumb-2 VFP Double-precision instructions +#as: -mfpu=vfp -mcpu=arm1156t2f-s + +# Test the ARM VFP Double Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eeb4 0bc0 (vcmpe\.f64|fcmped) d0, d0 +0+004 <[^>]*> eeb5 0bc0 (vcmpe\.f64 d0, #0.0|fcmpezd d0) +0+008 <[^>]*> eeb4 0b40 (vcmp\.f64|fcmpd) d0, d0 +0+00c <[^>]*> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0) +0+010 <[^>]*> eeb0 0bc0 (vabs\.f64|fabsd) d0, d0 +0+014 <[^>]*> eeb0 0b40 (vmov\.f64|fcpyd) d0, d0 +0+018 <[^>]*> eeb1 0b40 (vneg\.f64|fnegd) d0, d0 +0+01c <[^>]*> eeb1 0bc0 (vsqrt\.f64|fsqrtd) d0, d0 +0+020 <[^>]*> ee30 0b00 (vadd\.f64|faddd) d0, d0, d0 +0+024 <[^>]*> ee80 0b00 (vdiv\.f64|fdivd) d0, d0, d0 +0+028 <[^>]*> ee00 0b00 (vmla\.f64|fmacd) d0, d0, d0 +0+02c <[^>]*> ee10 0b00 (vnmls\.f64|fmscd) d0, d0, d0 +0+030 <[^>]*> ee20 0b00 (vmul\.f64|fmuld) d0, d0, d0 +0+034 <[^>]*> ee00 0b40 (vmls\.f64|fnmacd) d0, d0, d0 +0+038 <[^>]*> ee10 0b40 (vnmla\.f64|fnmscd) d0, d0, d0 +0+03c <[^>]*> ee20 0b40 (vnmul\.f64|fnmuld) d0, d0, d0 +0+040 <[^>]*> ee30 0b40 (vsub\.f64|fsubd) d0, d0, d0 +0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\] +0+048 <[^>]*> ed80 0b00 vstr d0, \[r0\] +0+04c <[^>]*> ec90 0b02 vldmia r0, {d0} +0+050 <[^>]*> ec90 0b02 vldmia r0, {d0} +0+054 <[^>]*> ecb0 0b02 vldmia r0!, {d0} +0+058 <[^>]*> ecb0 0b02 vldmia r0!, {d0} +0+05c <[^>]*> ed30 0b02 vldmdb r0!, {d0} +0+060 <[^>]*> ed30 0b02 vldmdb r0!, {d0} +0+064 <[^>]*> ec80 0b02 vstmia r0, {d0} +0+068 <[^>]*> ec80 0b02 vstmia r0, {d0} +0+06c <[^>]*> eca0 0b02 vstmia r0!, {d0} +0+070 <[^>]*> eca0 0b02 vstmia r0!, {d0} +0+074 <[^>]*> ed20 0b02 vstmdb r0!, {d0} +0+078 <[^>]*> ed20 0b02 vstmdb r0!, {d0} +0+07c <[^>]*> eeb8 0bc0 (vcvt\.f64\.s32|fsitod) d0, s0 +0+080 <[^>]*> eeb8 0b40 (vcvt\.f64\.u32|fuitod) d0, s0 +0+084 <[^>]*> eebd 0b40 (vcvtr\.s32\.f64|ftosid) s0, d0 +0+088 <[^>]*> eebd 0bc0 (vcvt\.s32\.f64|ftosizd) s0, d0 +0+08c <[^>]*> eebc 0b40 (vcvtr\.u32\.f64|ftouid) s0, d0 +0+090 <[^>]*> eebc 0bc0 (vcvt\.u32\.f64|ftouizd) s0, d0 +0+094 <[^>]*> eeb7 0ac0 (vcvt\.f64\.f32|fcvtds) d0, s0 +0+098 <[^>]*> eeb7 0bc0 (vcvt\.f32\.f64|fcvtsd) s0, d0 +0+09c <[^>]*> ee30 0b10 vmov\.32 r0, d0\[1\] +0+0a0 <[^>]*> ee10 0b10 vmov\.32 r0, d0\[0\] +0+0a4 <[^>]*> ee20 0b10 vmov\.32 d0\[1\], r0 +0+0a8 <[^>]*> ee00 0b10 vmov\.32 d0\[0\], r0 +0+0ac <[^>]*> eeb5 1b40 (vcmp\.f64 d1, #0.0|fcmpzd d1) +0+0b0 <[^>]*> eeb5 2b40 (vcmp\.f64 d2, #0.0|fcmpzd d2) +0+0b4 <[^>]*> eeb5 fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15) +0+0b8 <[^>]*> eeb4 0b41 (vcmp\.f64|fcmpd) d0, d1 +0+0bc <[^>]*> eeb4 0b42 (vcmp\.f64|fcmpd) d0, d2 +0+0c0 <[^>]*> eeb4 0b4f (vcmp\.f64|fcmpd) d0, d15 +0+0c4 <[^>]*> eeb4 1b40 (vcmp\.f64|fcmpd) d1, d0 +0+0c8 <[^>]*> eeb4 2b40 (vcmp\.f64|fcmpd) d2, d0 +0+0cc <[^>]*> eeb4 fb40 (vcmp\.f64|fcmpd) d15, d0 +0+0d0 <[^>]*> eeb4 5b4c (vcmp\.f64|fcmpd) d5, d12 +0+0d4 <[^>]*> eeb1 0b41 (vneg\.f64|fnegd) d0, d1 +0+0d8 <[^>]*> eeb1 0b42 (vneg\.f64|fnegd) d0, d2 +0+0dc <[^>]*> eeb1 0b4f (vneg\.f64|fnegd) d0, d15 +0+0e0 <[^>]*> eeb1 1b40 (vneg\.f64|fnegd) d1, d0 +0+0e4 <[^>]*> eeb1 2b40 (vneg\.f64|fnegd) d2, d0 +0+0e8 <[^>]*> eeb1 fb40 (vneg\.f64|fnegd) d15, d0 +0+0ec <[^>]*> eeb1 cb45 (vneg\.f64|fnegd) d12, d5 +0+0f0 <[^>]*> ee30 0b01 (vadd\.f64|faddd) d0, d0, d1 +0+0f4 <[^>]*> ee30 0b02 (vadd\.f64|faddd) d0, d0, d2 +0+0f8 <[^>]*> ee30 0b0f (vadd\.f64|faddd) d0, d0, d15 +0+0fc <[^>]*> ee31 0b00 (vadd\.f64|faddd) d0, d1, d0 +0+100 <[^>]*> ee32 0b00 (vadd\.f64|faddd) d0, d2, d0 +0+104 <[^>]*> ee3f 0b00 (vadd\.f64|faddd) d0, d15, d0 +0+108 <[^>]*> ee30 1b00 (vadd\.f64|faddd) d1, d0, d0 +0+10c <[^>]*> ee30 2b00 (vadd\.f64|faddd) d2, d0, d0 +0+110 <[^>]*> ee30 fb00 (vadd\.f64|faddd) d15, d0, d0 +0+114 <[^>]*> ee39 cb05 (vadd\.f64|faddd) d12, d9, d5 +0+118 <[^>]*> eeb7 0ae0 (vcvt\.f64\.f32|fcvtds) d0, s1 +0+11c <[^>]*> eeb7 0ac1 (vcvt\.f64\.f32|fcvtds) d0, s2 +0+120 <[^>]*> eeb7 0aef (vcvt\.f64\.f32|fcvtds) d0, s31 +0+124 <[^>]*> eeb7 1ac0 (vcvt\.f64\.f32|fcvtds) d1, s0 +0+128 <[^>]*> eeb7 2ac0 (vcvt\.f64\.f32|fcvtds) d2, s0 +0+12c <[^>]*> eeb7 fac0 (vcvt\.f64\.f32|fcvtds) d15, s0 +0+130 <[^>]*> eef7 0bc0 (vcvt\.f32\.f64|fcvtsd) s1, d0 +0+134 <[^>]*> eeb7 1bc0 (vcvt\.f32\.f64|fcvtsd) s2, d0 +0+138 <[^>]*> eef7 fbc0 (vcvt\.f32\.f64|fcvtsd) s31, d0 +0+13c <[^>]*> eeb7 0bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1 +0+140 <[^>]*> eeb7 0bc2 (vcvt\.f32\.f64|fcvtsd) s0, d2 +0+144 <[^>]*> eeb7 0bcf (vcvt\.f32\.f64|fcvtsd) s0, d15 +0+148 <[^>]*> ee30 1b10 vmov\.32 r1, d0\[1\] +0+14c <[^>]*> ee30 eb10 vmov\.32 lr, d0\[1\] +0+150 <[^>]*> ee31 0b10 vmov\.32 r0, d1\[1\] +0+154 <[^>]*> ee32 0b10 vmov\.32 r0, d2\[1\] +0+158 <[^>]*> ee3f 0b10 vmov\.32 r0, d15\[1\] +0+15c <[^>]*> ee10 1b10 vmov\.32 r1, d0\[0\] +0+160 <[^>]*> ee10 eb10 vmov\.32 lr, d0\[0\] +0+164 <[^>]*> ee11 0b10 vmov\.32 r0, d1\[0\] +0+168 <[^>]*> ee12 0b10 vmov\.32 r0, d2\[0\] +0+16c <[^>]*> ee1f 0b10 vmov\.32 r0, d15\[0\] +0+170 <[^>]*> ee20 1b10 vmov\.32 d0\[1\], r1 +0+174 <[^>]*> ee20 eb10 vmov\.32 d0\[1\], lr +0+178 <[^>]*> ee21 0b10 vmov\.32 d1\[1\], r0 +0+17c <[^>]*> ee22 0b10 vmov\.32 d2\[1\], r0 +0+180 <[^>]*> ee2f 0b10 vmov\.32 d15\[1\], r0 +0+184 <[^>]*> ee00 1b10 vmov\.32 d0\[0\], r1 +0+188 <[^>]*> ee00 eb10 vmov\.32 d0\[0\], lr +0+18c <[^>]*> ee01 0b10 vmov\.32 d1\[0\], r0 +0+190 <[^>]*> ee02 0b10 vmov\.32 d2\[0\], r0 +0+194 <[^>]*> ee0f 0b10 vmov\.32 d15\[0\], r0 +0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\] +0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\] +0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\] +0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\].* +0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\].* +0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\] +0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\] +0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\] +0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\].* +0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1} +0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2} +0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15} +0+1c8 <[^>]*> ec90 0b04 vldmia r0, {d0-d1} +0+1cc <[^>]*> ec90 0b06 vldmia r0, {d0-d2} +0+1d0 <[^>]*> ec90 0b20 vldmia r0, {d0-d15} +0+1d4 <[^>]*> ec90 1b1e vldmia r0, {d1-d15} +0+1d8 <[^>]*> ec90 2b1c vldmia r0, {d2-d15} +0+1dc <[^>]*> ec90 eb04 vldmia r0, {d14-d15} +0+1e0 <[^>]*> ec91 0b02 vldmia r1, {d0} +0+1e4 <[^>]*> ec9e 0b02 vldmia lr, {d0} +0+1e8 <[^>]*> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0) +0+1ec <[^>]*> eeb5 1b40 (vcmp\.f64 d1, #0.0|fcmpzd d1) +0+1f0 <[^>]*> eeb5 2b40 (vcmp\.f64 d2, #0.0|fcmpzd d2) +0+1f4 <[^>]*> eeb5 3b40 (vcmp\.f64 d3, #0.0|fcmpzd d3) +0+1f8 <[^>]*> eeb5 4b40 (vcmp\.f64 d4, #0.0|fcmpzd d4) +0+1fc <[^>]*> eeb5 5b40 (vcmp\.f64 d5, #0.0|fcmpzd d5) +0+200 <[^>]*> eeb5 6b40 (vcmp\.f64 d6, #0.0|fcmpzd d6) +0+204 <[^>]*> eeb5 7b40 (vcmp\.f64 d7, #0.0|fcmpzd d7) +0+208 <[^>]*> eeb5 8b40 (vcmp\.f64 d8, #0.0|fcmpzd d8) +0+20c <[^>]*> eeb5 9b40 (vcmp\.f64 d9, #0.0|fcmpzd d9) +0+210 <[^>]*> eeb5 ab40 (vcmp\.f64 d10, #0.0|fcmpzd d10) +0+214 <[^>]*> eeb5 bb40 (vcmp\.f64 d11, #0.0|fcmpzd d11) +0+218 <[^>]*> eeb5 cb40 (vcmp\.f64 d12, #0.0|fcmpzd d12) +0+21c <[^>]*> eeb5 db40 (vcmp\.f64 d13, #0.0|fcmpzd d13) +0+220 <[^>]*> eeb5 eb40 (vcmp\.f64 d14, #0.0|fcmpzd d14) +0+224 <[^>]*> eeb5 fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15) +0+228 <[^>]*> bf01 itttt eq +0+22a <[^>]*> eeb4 1bcf (vcmpeeq\.f64|fcmpedeq) d1, d15 +0+22e <[^>]*> eeb5 2bc0 (vcmpeeq\.f64 d2, #0.0|fcmpezdeq d2) +0+232 <[^>]*> eeb4 3b4e (vcmpeq\.f64|fcmpdeq) d3, d14 +0+236 <[^>]*> eeb5 4b40 (vcmpeq\.f64 d4, #0.0|fcmpzdeq d4) +0+23a <[^>]*> bf01 itttt eq +0+23c <[^>]*> eeb0 5bcd (vabseq\.f64|fabsdeq) d5, d13 +0+240 <[^>]*> eeb0 6b4c (vmoveq\.f64|fcpydeq) d6, d12 +0+244 <[^>]*> eeb1 7b4b (vnegeq\.f64|fnegdeq) d7, d11 +0+248 <[^>]*> eeb1 8bca (vsqrteq\.f64|fsqrtdeq) d8, d10 +0+24c <[^>]*> bf01 itttt eq +0+24e <[^>]*> ee31 9b0f (vaddeq\.f64|fadddeq) d9, d1, d15 +0+252 <[^>]*> ee83 2b0e (vdiveq\.f64|fdivdeq) d2, d3, d14 +0+256 <[^>]*> ee0d 4b0c (vmlaeq\.f64|fmacdeq) d4, d13, d12 +0+25a <[^>]*> ee16 5b0b (vnmlseq\.f64|fmscdeq) d5, d6, d11 +0+25e <[^>]*> bf01 itttt eq +0+260 <[^>]*> ee2a 7b09 (vmuleq\.f64|fmuldeq) d7, d10, d9 +0+264 <[^>]*> ee09 8b4a (vmlseq\.f64|fnmacdeq) d8, d9, d10 +0+268 <[^>]*> ee16 7b4b (vnmlaeq\.f64|fnmscdeq) d7, d6, d11 +0+26c <[^>]*> ee24 5b4c (vnmuleq\.f64|fnmuldeq) d5, d4, d12 +0+270 <[^>]*> bf02 ittt eq +0+272 <[^>]*> ee3d 3b4e (vsubeq\.f64|fsubdeq) d3, d13, d14 +0+276 <[^>]*> ed95 2b00 vldreq d2, \[r5\] +0+27a <[^>]*> ed8c 1b00 vstreq d1, \[ip\] +0+27e <[^>]*> bf01 itttt eq +0+280 <[^>]*> ec91 1b02 vldmiaeq r1, {d1} +0+284 <[^>]*> ec92 2b02 vldmiaeq r2, {d2} +0+288 <[^>]*> ecb3 3b02 vldmiaeq r3!, {d3} +0+28c <[^>]*> ecb4 4b02 vldmiaeq r4!, {d4} +0+290 <[^>]*> bf01 itttt eq +0+292 <[^>]*> ed35 5b02 vldmdbeq r5!, {d5} +0+296 <[^>]*> ed36 6b02 vldmdbeq r6!, {d6} +0+29a <[^>]*> ec87 fb02 vstmiaeq r7, {d15} +0+29e <[^>]*> ec88 eb02 vstmiaeq r8, {d14} +0+2a2 <[^>]*> bf01 itttt eq +0+2a4 <[^>]*> eca9 db02 vstmiaeq r9!, {d13} +0+2a8 <[^>]*> ecaa cb02 vstmiaeq sl!, {d12} +0+2ac <[^>]*> ed2b bb02 vstmdbeq fp!, {d11} +0+2b0 <[^>]*> ed2c ab02 vstmdbeq ip!, {d10} +0+2b4 <[^>]*> bf01 itttt eq +0+2b6 <[^>]*> eeb8 fbe0 (vcvteq\.f64\.s32|fsitodeq) d15, s1 +0+2ba <[^>]*> eeb8 1b6f (vcvteq\.f64\.u32|fuitodeq) d1, s31 +0+2be <[^>]*> eefd 0b4f (vcvtreq\.s32\.f64|ftosideq) s1, d15 +0+2c2 <[^>]*> eefd fbc2 (vcvteq\.s32\.f64|ftosizdeq) s31, d2 +0+2c6 <[^>]*> bf01 itttt eq +0+2c8 <[^>]*> eefc 7b42 (vcvtreq\.u32\.f64|ftouideq) s15, d2 +0+2cc <[^>]*> eefc 5bc3 (vcvteq\.u32\.f64|ftouizdeq) s11, d3 +0+2d0 <[^>]*> eeb7 1ac5 (vcvteq\.f64\.f32|fcvtdseq) d1, s10 +0+2d4 <[^>]*> eef7 5bc1 (vcvteq\.f32\.f64|fcvtsdeq) s11, d1 +0+2d8 <[^>]*> bf01 itttt eq +0+2da <[^>]*> ee31 8b10 vmoveq\.32 r8, d1\[1\] +0+2de <[^>]*> ee1f 7b10 vmoveq\.32 r7, d15\[0\] +0+2e2 <[^>]*> ee21 fb10 vmoveq\.32 d1\[1\], pc +0+2e6 <[^>]*> ee0f 1b10 vmoveq\.32 d15\[0\], r1 +0+2ea <[^>]*> bf00 nop +0+2ec <[^>]*> bf00 nop +0+2ee <[^>]*> bf00 nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1_t2.s b/binutils-2.25/gas/testsuite/gas/arm/vfp1_t2.s new file mode 100644 index 00000000..dd596cb5 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1_t2.s @@ -0,0 +1,298 @@ +@ VFP Instructions for D variants (Double precision) +@ Same as vfp1.s, but for Thumb-2 + .syntax unified + .thumb + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Most of these tests deliberatly use d0/r0 to avoid setting + @ any more bits than necessary. + + @ Comparison operations + + fcmped d0, d0 + fcmpezd d0 + fcmpd d0, d0 + fcmpzd d0 + + @ Monadic data operations + + fabsd d0, d0 + fcpyd d0, d0 + fnegd d0, d0 + fsqrtd d0, d0 + + @ Dyadic data operations + + faddd d0, d0, d0 + fdivd d0, d0, d0 + fmacd d0, d0, d0 + fmscd d0, d0, d0 + fmuld d0, d0, d0 + fnmacd d0, d0, d0 + fnmscd d0, d0, d0 + fnmuld d0, d0, d0 + fsubd d0, d0, d0 + + @ Load/store operations + + fldd d0, [r0] + fstd d0, [r0] + + @ Load/store multiple operations + + fldmiad r0, {d0} + fldmfdd r0, {d0} + fldmiad r0!, {d0} + fldmfdd r0!, {d0} + fldmdbd r0!, {d0} + fldmead r0!, {d0} + + fstmiad r0, {d0} + fstmead r0, {d0} + fstmiad r0!, {d0} + fstmead r0!, {d0} + fstmdbd r0!, {d0} + fstmfdd r0!, {d0} + + @ Conversion operations + + fsitod d0, s0 + fuitod d0, s0 + + ftosid s0, d0 + ftosizd s0, d0 + ftouid s0, d0 + ftouizd s0, d0 + + fcvtds d0, s0 + fcvtsd s0, d0 + + @ ARM from VFP operations + + fmrdh r0, d0 + fmrdl r0, d0 + + @ VFP From ARM operations + + fmdhr d0, r0 + fmdlr d0, r0 + + @ Now we test that the register fields are updated correctly for + @ each class of instruction. + + @ Single register operations (compare-zero): + + fcmpzd d1 + fcmpzd d2 + fcmpzd d15 + + @ Two register comparison operations: + + fcmpd d0, d1 + fcmpd d0, d2 + fcmpd d0, d15 + fcmpd d1, d0 + fcmpd d2, d0 + fcmpd d15, d0 + fcmpd d5, d12 + + @ Two register data operations (monadic) + + fnegd d0, d1 + fnegd d0, d2 + fnegd d0, d15 + fnegd d1, d0 + fnegd d2, d0 + fnegd d15, d0 + fnegd d12, d5 + + @ Three register data operations (dyadic) + + faddd d0, d0, d1 + faddd d0, d0, d2 + faddd d0, d0, d15 + faddd d0, d1, d0 + faddd d0, d2, d0 + faddd d0, d15, d0 + faddd d1, d0, d0 + faddd d2, d0, d0 + faddd d15, d0, d0 + faddd d12, d9, d5 + + @ Conversion operations + + fcvtds d0, s1 + fcvtds d0, s2 + fcvtds d0, s31 + fcvtds d1, s0 + fcvtds d2, s0 + fcvtds d15, s0 + fcvtsd s1, d0 + fcvtsd s2, d0 + fcvtsd s31, d0 + fcvtsd s0, d1 + fcvtsd s0, d2 + fcvtsd s0, d15 + + @ Move to VFP from ARM + + fmrdh r1, d0 + fmrdh r14, d0 + fmrdh r0, d1 + fmrdh r0, d2 + fmrdh r0, d15 + fmrdl r1, d0 + fmrdl r14, d0 + fmrdl r0, d1 + fmrdl r0, d2 + fmrdl r0, d15 + + @ Move to ARM from VFP + + fmdhr d0, r1 + fmdhr d0, r14 + fmdhr d1, r0 + fmdhr d2, r0 + fmdhr d15, r0 + fmdlr d0, r1 + fmdlr d0, r14 + fmdlr d1, r0 + fmdlr d2, r0 + fmdlr d15, r0 + + @ Load/store operations + + fldd d0, [r1] + fldd d0, [r14] + fldd d0, [r0, #0] + fldd d0, [r0, #1020] + fldd d0, [r0, #-1020] + fldd d1, [r0] + fldd d2, [r0] + fldd d15, [r0] + fstd d12, [r12, #804] + + @ Load/store multiple operations + + fldmiad r0, {d1} + fldmiad r0, {d2} + fldmiad r0, {d15} + fldmiad r0, {d0-d1} + fldmiad r0, {d0-d2} + fldmiad r0, {d0-d15} + fldmiad r0, {d1-d15} + fldmiad r0, {d2-d15} + fldmiad r0, {d14-d15} + fldmiad r1, {d0} + fldmiad r14, {d0} + + @ Check that we assemble all the register names correctly + + fcmpzd d0 + fcmpzd d1 + fcmpzd d2 + fcmpzd d3 + fcmpzd d4 + fcmpzd d5 + fcmpzd d6 + fcmpzd d7 + fcmpzd d8 + fcmpzd d9 + fcmpzd d10 + fcmpzd d11 + fcmpzd d12 + fcmpzd d13 + fcmpzd d14 + fcmpzd d15 + + @ Now we check the placement of the conditional execution substring. + @ On VFP this is always at the end of the instruction. + + @ Comparison operations + + itttt eq + fcmpedeq d1, d15 + fcmpezdeq d2 + fcmpdeq d3, d14 + fcmpzdeq d4 + + @ Monadic data operations + + itttt eq + fabsdeq d5, d13 + fcpydeq d6, d12 + fnegdeq d7, d11 + fsqrtdeq d8, d10 + + @ Dyadic data operations + + itttt eq + fadddeq d9, d1, d15 + fdivdeq d2, d3, d14 + fmacdeq d4, d13, d12 + fmscdeq d5, d6, d11 + itttt eq + fmuldeq d7, d10, d9 + fnmacdeq d8, d9, d10 + fnmscdeq d7, d6, d11 + fnmuldeq d5, d4, d12 + ittt eq + fsubdeq d3, d13, d14 + + @ Load/store operations + + flddeq d2, [r5] + fstdeq d1, [r12] + + @ Load/store multiple operations + + itttt eq + fldmiadeq r1, {d1} + fldmfddeq r2, {d2} + fldmiadeq r3!, {d3} + fldmfddeq r4!, {d4} + itttt eq + fldmdbdeq r5!, {d5} + fldmeadeq r6!, {d6} + + fstmiadeq r7, {d15} + fstmeadeq r8, {d14} + itttt eq + fstmiadeq r9!, {d13} + fstmeadeq r10!, {d12} + fstmdbdeq r11!, {d11} + fstmfddeq r12!, {d10} + + @ Conversion operations + + itttt eq + fsitodeq d15, s1 + fuitodeq d1, s31 + + ftosideq s1, d15 + ftosizdeq s31, d2 + itttt eq + ftouideq s15, d2 + ftouizdeq s11, d3 + + fcvtdseq d1, s10 + fcvtsdeq s11, d1 + + @ ARM from VFP operations + + itttt eq + fmrdheq r8, d1 + fmrdleq r7, d15 + + @ VFP From ARM operations + + fmdhreq d1, r15 + fmdlreq d15, r1 + + # Add three nop instructions to ensure that the + # output is 32-byte aligned as required for arm-aout. + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1xD.d b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD.d new file mode 100644 index 00000000..8eaf9ae2 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD.d @@ -0,0 +1,295 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: VFP Single-precision instructions +#as: -mfpu=vfpxd + +# Test the ARM VFP Single Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eef1fa10 (vmrs APSR_nzcv, fpscr|fmstat) +0+004 <[^>]*> eeb40ac0 (vcmpe\.f32|fcmpes) s0, s0 +0+008 <[^>]*> eeb50ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0) +0+00c <[^>]*> eeb40a40 (vcmp\.f32|fcmps) s0, s0 +0+010 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0) +0+014 <[^>]*> eeb00ac0 (vabs\.f32|fabss) s0, s0 +0+018 <[^>]*> eeb00a40 (vmov\.f32|fcpys) s0, s0 +0+01c <[^>]*> eeb10a40 (vneg\.f32|fnegs) s0, s0 +0+020 <[^>]*> eeb10ac0 (vsqrt\.f32|fsqrts) s0, s0 +0+024 <[^>]*> ee300a00 (vadd\.f32|fadds) s0, s0, s0 +0+028 <[^>]*> ee800a00 (vdiv\.f32|fdivs) s0, s0, s0 +0+02c <[^>]*> ee000a00 (vmla\.f32|fmacs) s0, s0, s0 +0+030 <[^>]*> ee100a00 (vnmls\.f32|fmscs) s0, s0, s0 +0+034 <[^>]*> ee200a00 (vmul\.f32|fmuls) s0, s0, s0 +0+038 <[^>]*> ee000a40 (vmls\.f32|fnmacs) s0, s0, s0 +0+03c <[^>]*> ee100a40 (vnmla\.f32|fnmscs) s0, s0, s0 +0+040 <[^>]*> ee200a40 (vnmul\.f32|fnmuls) s0, s0, s0 +0+044 <[^>]*> ee300a40 (vsub\.f32|fsubs) s0, s0, s0 +0+048 <[^>]*> ed900a00 (vldr|flds) s0, \[r0\] +0+04c <[^>]*> ed800a00 (vstr|fsts) s0, \[r0\] +0+050 <[^>]*> ec900a01 (vldmia|fldmias) r0, {s0} +0+054 <[^>]*> ec900a01 (vldmia|fldmias) r0, {s0} +0+058 <[^>]*> ecb00a01 (vldmia|fldmias) r0!, {s0} +0+05c <[^>]*> ecb00a01 (vldmia|fldmias) r0!, {s0} +0+060 <[^>]*> ed300a01 (vldmdb|fldmdbs) r0!, {s0} +0+064 <[^>]*> ed300a01 (vldmdb|fldmdbs) r0!, {s0} +0+068 <[^>]*> ec900b03 fldmiax r0, {d0}( ;@ Deprecated|) +0+06c <[^>]*> ec900b03 fldmiax r0, {d0}( ;@ Deprecated|) +0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0}( ;@ Deprecated|) +0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0}( ;@ Deprecated|) +0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0}( ;@ Deprecated|) +0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0}( ;@ Deprecated|) +0+080 <[^>]*> ec800a01 (vstmia|fstmias) r0, {s0} +0+084 <[^>]*> ec800a01 (vstmia|fstmias) r0, {s0} +0+088 <[^>]*> eca00a01 (vstmia|fstmias) r0!, {s0} +0+08c <[^>]*> eca00a01 (vstmia|fstmias) r0!, {s0} +0+090 <[^>]*> ed200a01 (vstmdb|fstmdbs) r0!, {s0} +0+094 <[^>]*> ed200a01 (vstmdb|fstmdbs) r0!, {s0} +0+098 <[^>]*> ec800b03 fstmiax r0, {d0}( ;@ Deprecated|) +0+09c <[^>]*> ec800b03 fstmiax r0, {d0}( ;@ Deprecated|) +0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0}( ;@ Deprecated|) +0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0}( ;@ Deprecated|) +0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0}( ;@ Deprecated|) +0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0}( ;@ Deprecated|) +0+0b0 <[^>]*> eeb80ac0 (vcvt\.f32\.s32|fsitos) s0, s0 +0+0b4 <[^>]*> eeb80a40 (vcvt\.f32\.u32|fuitos) s0, s0 +0+0b8 <[^>]*> eebd0a40 (vcvtr\.s32\.f32|ftosis) s0, s0 +0+0bc <[^>]*> eebd0ac0 (vcvt\.s32\.f32|ftosizs) s0, s0 +0+0c0 <[^>]*> eebc0a40 (vcvtr\.u32\.f32|ftouis) s0, s0 +0+0c4 <[^>]*> eebc0ac0 (vcvt\.u32\.f32|ftouizs) s0, s0 +0+0c8 <[^>]*> ee100a10 (vmov|fmrs) r0, s0 +0+0cc <[^>]*> eef00a10 (vmrs|fmrx) r0, fpsid +0+0d0 <[^>]*> eef10a10 (vmrs|fmrx) r0, fpscr +0+0d4 <[^>]*> eef80a10 (vmrs|fmrx) r0, fpexc +0+0d8 <[^>]*> ee000a10 (vmov|fmsr) s0, r0 +0+0dc <[^>]*> eee00a10 (vmsr|fmxr) fpsid, r0 +0+0e0 <[^>]*> eee10a10 (vmsr|fmxr) fpscr, r0 +0+0e4 <[^>]*> eee80a10 (vmsr|fmxr) fpexc, r0 +0+0e8 <[^>]*> eef50a40 (vcmp\.f32 s1, #0.0|fcmpzs s1) +0+0ec <[^>]*> eeb51a40 (vcmp\.f32 s2, #0.0|fcmpzs s2) +0+0f0 <[^>]*> eef5fa40 (vcmp\.f32 s31, #0.0|fcmpzs s31) +0+0f4 <[^>]*> eeb40a60 (vcmp\.f32|fcmps) s0, s1 +0+0f8 <[^>]*> eeb40a41 (vcmp\.f32|fcmps) s0, s2 +0+0fc <[^>]*> eeb40a6f (vcmp\.f32|fcmps) s0, s31 +0+100 <[^>]*> eef40a40 (vcmp\.f32|fcmps) s1, s0 +0+104 <[^>]*> eeb41a40 (vcmp\.f32|fcmps) s2, s0 +0+108 <[^>]*> eef4fa40 (vcmp\.f32|fcmps) s31, s0 +0+10c <[^>]*> eef4aa46 (vcmp\.f32|fcmps) s21, s12 +0+110 <[^>]*> eeb10a60 (vneg\.f32|fnegs) s0, s1 +0+114 <[^>]*> eeb10a41 (vneg\.f32|fnegs) s0, s2 +0+118 <[^>]*> eeb10a6f (vneg\.f32|fnegs) s0, s31 +0+11c <[^>]*> eef10a40 (vneg\.f32|fnegs) s1, s0 +0+120 <[^>]*> eeb11a40 (vneg\.f32|fnegs) s2, s0 +0+124 <[^>]*> eef1fa40 (vneg\.f32|fnegs) s31, s0 +0+128 <[^>]*> eeb16a6a (vneg\.f32|fnegs) s12, s21 +0+12c <[^>]*> ee300a20 (vadd\.f32|fadds) s0, s0, s1 +0+130 <[^>]*> ee300a01 (vadd\.f32|fadds) s0, s0, s2 +0+134 <[^>]*> ee300a2f (vadd\.f32|fadds) s0, s0, s31 +0+138 <[^>]*> ee300a80 (vadd\.f32|fadds) s0, s1, s0 +0+13c <[^>]*> ee310a00 (vadd\.f32|fadds) s0, s2, s0 +0+140 <[^>]*> ee3f0a80 (vadd\.f32|fadds) s0, s31, s0 +0+144 <[^>]*> ee700a00 (vadd\.f32|fadds) s1, s0, s0 +0+148 <[^>]*> ee301a00 (vadd\.f32|fadds) s2, s0, s0 +0+14c <[^>]*> ee70fa00 (vadd\.f32|fadds) s31, s0, s0 +0+150 <[^>]*> ee3a6aa2 (vadd\.f32|fadds) s12, s21, s5 +0+154 <[^>]*> eeb80ae0 (vcvt\.f32\.s32|fsitos) s0, s1 +0+158 <[^>]*> eeb80ac1 (vcvt\.f32\.s32|fsitos) s0, s2 +0+15c <[^>]*> eeb80aef (vcvt\.f32\.s32|fsitos) s0, s31 +0+160 <[^>]*> eef80ac0 (vcvt\.f32\.s32|fsitos) s1, s0 +0+164 <[^>]*> eeb81ac0 (vcvt\.f32\.s32|fsitos) s2, s0 +0+168 <[^>]*> eef8fac0 (vcvt\.f32\.s32|fsitos) s31, s0 +0+16c <[^>]*> eebd0a60 (vcvtr\.s32\.f32|ftosis) s0, s1 +0+170 <[^>]*> eebd0a41 (vcvtr\.s32\.f32|ftosis) s0, s2 +0+174 <[^>]*> eebd0a6f (vcvtr\.s32\.f32|ftosis) s0, s31 +0+178 <[^>]*> eefd0a40 (vcvtr\.s32\.f32|ftosis) s1, s0 +0+17c <[^>]*> eebd1a40 (vcvtr\.s32\.f32|ftosis) s2, s0 +0+180 <[^>]*> eefdfa40 (vcvtr\.s32\.f32|ftosis) s31, s0 +0+184 <[^>]*> ee001a10 (vmov|fmsr) s0, r1 +0+188 <[^>]*> ee007a10 (vmov|fmsr) s0, r7 +0+18c <[^>]*> ee00ea10 (vmov|fmsr) s0, lr +0+190 <[^>]*> ee000a90 (vmov|fmsr) s1, r0 +0+194 <[^>]*> ee010a10 (vmov|fmsr) s2, r0 +0+198 <[^>]*> ee0f0a90 (vmov|fmsr) s31, r0 +0+19c <[^>]*> ee0a7a90 (vmov|fmsr) s21, r7 +0+1a0 <[^>]*> eee01a10 (vmsr|fmxr) fpsid, r1 +0+1a4 <[^>]*> eee0ea10 (vmsr|fmxr) fpsid, lr +0+1a8 <[^>]*> ee100a90 (vmov|fmrs) r0, s1 +0+1ac <[^>]*> ee110a10 (vmov|fmrs) r0, s2 +0+1b0 <[^>]*> ee1f0a90 (vmov|fmrs) r0, s31 +0+1b4 <[^>]*> ee101a10 (vmov|fmrs) r1, s0 +0+1b8 <[^>]*> ee107a10 (vmov|fmrs) r7, s0 +0+1bc <[^>]*> ee10ea10 (vmov|fmrs) lr, s0 +0+1c0 <[^>]*> ee159a90 (vmov|fmrs) r9, s11 +0+1c4 <[^>]*> eef01a10 (vmrs|fmrx) r1, fpsid +0+1c8 <[^>]*> eef0ea10 (vmrs|fmrx) lr, fpsid +0+1cc <[^>]*> ed910a00 (vldr|flds) s0, \[r1\] +0+1d0 <[^>]*> ed9e0a00 (vldr|flds) s0, \[lr\] +0+1d4 <[^>]*> ed900a00 (vldr|flds) s0, \[r0\] +0+1d8 <[^>]*> ed900aff (vldr|flds) s0, \[r0, #1020\].* +0+1dc <[^>]*> ed100aff (vldr|flds) s0, \[r0, #-1020\].* +0+1e0 <[^>]*> edd00a00 (vldr|flds) s1, \[r0\] +0+1e4 <[^>]*> ed901a00 (vldr|flds) s2, \[r0\] +0+1e8 <[^>]*> edd0fa00 (vldr|flds) s31, \[r0\] +0+1ec <[^>]*> edccaac9 (vstr|fsts) s21, \[ip, #804\].* +0+1f0 <[^>]*> ecd00a01 (vldmia|fldmias) r0, {s1} +0+1f4 <[^>]*> ec901a01 (vldmia|fldmias) r0, {s2} +0+1f8 <[^>]*> ecd0fa01 (vldmia|fldmias) r0, {s31} +0+1fc <[^>]*> ec900a02 (vldmia|fldmias) r0, {s0-s1} +0+200 <[^>]*> ec900a03 (vldmia|fldmias) r0, {s0-s2} +0+204 <[^>]*> ec900a20 (vldmia|fldmias) r0, {s0-s31} +0+208 <[^>]*> ecd00a1f (vldmia|fldmias) r0, {s1-s31} +0+20c <[^>]*> ec901a1e (vldmia|fldmias) r0, {s2-s31} +0+210 <[^>]*> ec90fa02 (vldmia|fldmias) r0, {s30-s31} +0+214 <[^>]*> ec910a01 (vldmia|fldmias) r1, {s0} +0+218 <[^>]*> ec9e0a01 (vldmia|fldmias) lr, {s0} +0+21c <[^>]*> ec801b03 fstmiax r0, {d1}( ;@ Deprecated|) +0+220 <[^>]*> ec802b03 fstmiax r0, {d2}( ;@ Deprecated|) +0+224 <[^>]*> ec80fb03 fstmiax r0, {d15}( ;@ Deprecated|) +0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1}( ;@ Deprecated|) +0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2}( ;@ Deprecated|) +0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15}( ;@ Deprecated|) +0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15}( ;@ Deprecated|) +0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15}( ;@ Deprecated|) +0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|) +0+240 <[^>]*> ec810b03 fstmiax r1, {d0}( ;@ Deprecated|) +0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0}( ;@ Deprecated|) +0+248 <[^>]*> eeb50a40 (vcmp\.f32 s0, #0.0|fcmpzs s0) +0+24c <[^>]*> eef50a40 (vcmp\.f32 s1, #0.0|fcmpzs s1) +0+250 <[^>]*> eeb51a40 (vcmp\.f32 s2, #0.0|fcmpzs s2) +0+254 <[^>]*> eef51a40 (vcmp\.f32 s3, #0.0|fcmpzs s3) +0+258 <[^>]*> eeb52a40 (vcmp\.f32 s4, #0.0|fcmpzs s4) +0+25c <[^>]*> eef52a40 (vcmp\.f32 s5, #0.0|fcmpzs s5) +0+260 <[^>]*> eeb53a40 (vcmp\.f32 s6, #0.0|fcmpzs s6) +0+264 <[^>]*> eef53a40 (vcmp\.f32 s7, #0.0|fcmpzs s7) +0+268 <[^>]*> eeb54a40 (vcmp\.f32 s8, #0.0|fcmpzs s8) +0+26c <[^>]*> eef54a40 (vcmp\.f32 s9, #0.0|fcmpzs s9) +0+270 <[^>]*> eeb55a40 (vcmp\.f32 s10, #0.0|fcmpzs s10) +0+274 <[^>]*> eef55a40 (vcmp\.f32 s11, #0.0|fcmpzs s11) +0+278 <[^>]*> eeb56a40 (vcmp\.f32 s12, #0.0|fcmpzs s12) +0+27c <[^>]*> eef56a40 (vcmp\.f32 s13, #0.0|fcmpzs s13) +0+280 <[^>]*> eeb57a40 (vcmp\.f32 s14, #0.0|fcmpzs s14) +0+284 <[^>]*> eef57a40 (vcmp\.f32 s15, #0.0|fcmpzs s15) +0+288 <[^>]*> eeb58a40 (vcmp\.f32 s16, #0.0|fcmpzs s16) +0+28c <[^>]*> eef58a40 (vcmp\.f32 s17, #0.0|fcmpzs s17) +0+290 <[^>]*> eeb59a40 (vcmp\.f32 s18, #0.0|fcmpzs s18) +0+294 <[^>]*> eef59a40 (vcmp\.f32 s19, #0.0|fcmpzs s19) +0+298 <[^>]*> eeb5aa40 (vcmp\.f32 s20, #0.0|fcmpzs s20) +0+29c <[^>]*> eef5aa40 (vcmp\.f32 s21, #0.0|fcmpzs s21) +0+2a0 <[^>]*> eeb5ba40 (vcmp\.f32 s22, #0.0|fcmpzs s22) +0+2a4 <[^>]*> eef5ba40 (vcmp\.f32 s23, #0.0|fcmpzs s23) +0+2a8 <[^>]*> eeb5ca40 (vcmp\.f32 s24, #0.0|fcmpzs s24) +0+2ac <[^>]*> eef5ca40 (vcmp\.f32 s25, #0.0|fcmpzs s25) +0+2b0 <[^>]*> eeb5da40 (vcmp\.f32 s26, #0.0|fcmpzs s26) +0+2b4 <[^>]*> eef5da40 (vcmp\.f32 s27, #0.0|fcmpzs s27) +0+2b8 <[^>]*> eeb5ea40 (vcmp\.f32 s28, #0.0|fcmpzs s28) +0+2bc <[^>]*> eef5ea40 (vcmp\.f32 s29, #0.0|fcmpzs s29) +0+2c0 <[^>]*> eeb5fa40 (vcmp\.f32 s30, #0.0|fcmpzs s30) +0+2c4 <[^>]*> eef5fa40 (vcmp\.f32 s31, #0.0|fcmpzs s31) +0+2c8 <[^>]*> 0ef1fa10 (vmrseq APSR_nzcv, fpscr|fmstateq) +0+2cc <[^>]*> 0ef41ae3 (vcmpeeq\.f32|fcmpeseq) s3, s7 +0+2d0 <[^>]*> 0ef52ac0 (vcmpeeq\.f32 s5, #0.0|fcmpezseq s5) +0+2d4 <[^>]*> 0ef40a41 (vcmpeq\.f32|fcmpseq) s1, s2 +0+2d8 <[^>]*> 0ef50a40 (vcmpeq\.f32 s1, #0.0|fcmpzseq s1) +0+2dc <[^>]*> 0ef00ae1 (vabseq\.f32|fabsseq) s1, s3 +0+2e0 <[^>]*> 0ef0fa69 (vmoveq\.f32|fcpyseq) s31, s19 +0+2e4 <[^>]*> 0eb1aa44 (vnegeq\.f32|fnegseq) s20, s8 +0+2e8 <[^>]*> 0ef12ae3 (vsqrteq\.f32|fsqrtseq) s5, s7 +0+2ec <[^>]*> 0e323a82 (vaddeq\.f32|faddseq) s6, s5, s4 +0+2f0 <[^>]*> 0ec11a20 (vdiveq\.f32|fdivseq) s3, s2, s1 +0+2f4 <[^>]*> 0e4ffa2e (vmlaeq\.f32|fmacseq) s31, s30, s29 +0+2f8 <[^>]*> 0e1dea8d (vnmlseq\.f32|fmscseq) s28, s27, s26 +0+2fc <[^>]*> 0e6cca2b (vmuleq\.f32|fmulseq) s25, s24, s23 +0+300 <[^>]*> 0e0abaca (vmlseq\.f32|fnmacseq) s22, s21, s20 +0+304 <[^>]*> 0e599a68 (vnmlaeq\.f32|fnmscseq) s19, s18, s17 +0+308 <[^>]*> 0e278ac7 (vnmuleq\.f32|fnmulseq) s16, s15, s14 +0+30c <[^>]*> 0e766a65 (vsubeq\.f32|fsubseq) s13, s12, s11 +0+310 <[^>]*> 0d985a00 (vldreq|fldseq) s10, \[r8\] +0+314 <[^>]*> 0dc74a00 (vstreq|fstseq) s9, \[r7\] +0+318 <[^>]*> 0c914a01 (vldmiaeq|fldmiaseq) r1, {s8} +0+31c <[^>]*> 0cd23a01 (vldmiaeq|fldmiaseq) r2, {s7} +0+320 <[^>]*> 0cb33a01 (vldmiaeq|fldmiaseq) r3!, {s6} +0+324 <[^>]*> 0cf42a01 (vldmiaeq|fldmiaseq) r4!, {s5} +0+328 <[^>]*> 0d352a01 (vldmdbeq|fldmdbseq) r5!, {s4} +0+32c <[^>]*> 0d761a01 (vldmdbeq|fldmdbseq) r6!, {s3} +0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1}( ;@ Deprecated|) +0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2}( ;@ Deprecated|) +0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|) +0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|) +0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|) +0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|) +0+348 <[^>]*> 0c8d1a01 (vstmiaeq|fstmiaseq) sp, {s2} +0+34c <[^>]*> 0cce0a01 (vstmiaeq|fstmiaseq) lr, {s1} +0+350 <[^>]*> 0ce1fa01 (vstmiaeq|fstmiaseq) r1!, {s31} +0+354 <[^>]*> 0ca2fa01 (vstmiaeq|fstmiaseq) r2!, {s30} +0+358 <[^>]*> 0d63ea01 (vstmdbeq|fstmdbseq) r3!, {s29} +0+35c <[^>]*> 0d24ea01 (vstmdbeq|fstmdbseq) r4!, {s28} +0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7}( ;@ Deprecated|) +0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8}( ;@ Deprecated|) +0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|) +0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|) +0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|) +0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|) +0+378 <[^>]*> 0ef8dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6 +0+37c <[^>]*> 0efdca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5 +0+380 <[^>]*> 0efdbac2 (vcvteq\.s32\.f32|ftosizseq) s23, s4 +0+384 <[^>]*> 0efcaa61 (vcvtreq\.u32\.f32|ftouiseq) s21, s3 +0+388 <[^>]*> 0efc9ac1 (vcvteq\.u32\.f32|ftouizseq) s19, s2 +0+38c <[^>]*> 0ef88a60 (vcvteq\.f32\.u32|fuitoseq) s17, s1 +0+390 <[^>]*> 0e11ba90 (vmoveq|fmrseq) fp, s3 +0+394 <[^>]*> 0ef09a10 (vmrseq|fmrxeq) r9, fpsid +0+398 <[^>]*> 0e019a90 (vmoveq|fmsreq) s3, r9 +0+39c <[^>]*> 0ee08a10 (vmsreq|fmxreq) fpsid, r8 +0+3a0 <[^>]*> eef90a10 (vmrs|fmrx) r0, fpinst @ Impl def +0+3a4 <[^>]*> eefa0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def +0+3a8 <[^>]*> eef70a10 (vmrs|fmrx) r0, mvfr0 +0+3ac <[^>]*> eef60a10 (vmrs|fmrx) r0, mvfr1 +0+3b0 <[^>]*> eefc0a10 (vmrs|fmrx) r0, <impl def 0xc> +0+3b4 <[^>]*> eee90a10 (vmsr|fmxr) fpinst, r0 @ Impl def +0+3b8 <[^>]*> eeea0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def +0+3bc <[^>]*> eee70a10 (vmsr|fmxr) mvfr0, r0 +0+3c0 <[^>]*> eee60a10 (vmsr|fmxr) mvfr1, r0 +0+3c4 <[^>]*> eeec0a10 (vmsr|fmxr) <impl def 0xc>, r0 +0+3c8 <[^>]*> eef10a10 vmrs r0, fpscr +0+3cc <[^>]*> eef11a10 vmrs r1, fpscr +0+3d0 <[^>]*> eef12a10 vmrs r2, fpscr +0+3d4 <[^>]*> eef13a10 vmrs r3, fpscr +0+3d8 <[^>]*> eef14a10 vmrs r4, fpscr +0+3dc <[^>]*> eef15a10 vmrs r5, fpscr +0+3e0 <[^>]*> eef16a10 vmrs r6, fpscr +0+3e4 <[^>]*> eef17a10 vmrs r7, fpscr +0+3e8 <[^>]*> eef18a10 vmrs r8, fpscr +0+3ec <[^>]*> eef19a10 vmrs r9, fpscr +0+3f0 <[^>]*> eef1aa10 vmrs sl, fpscr +0+3f4 <[^>]*> eef1ba10 vmrs fp, fpscr +0+3f8 <[^>]*> eef1ca10 vmrs ip, fpscr +0+3fc <[^>]*> eef1ea10 vmrs lr, fpscr +0+400 <[^>]*> eef1fa10 vmrs APSR_nzcv, fpscr +0+404 <[^>]*> eee10a10 vmsr fpscr, r0 +0+408 <[^>]*> eee11a10 vmsr fpscr, r1 +0+40c <[^>]*> eee12a10 vmsr fpscr, r2 +0+410 <[^>]*> eee13a10 vmsr fpscr, r3 +0+414 <[^>]*> eee14a10 vmsr fpscr, r4 +0+418 <[^>]*> eee15a10 vmsr fpscr, r5 +0+41c <[^>]*> eee16a10 vmsr fpscr, r6 +0+420 <[^>]*> eee17a10 vmsr fpscr, r7 +0+424 <[^>]*> eee18a10 vmsr fpscr, r8 +0+428 <[^>]*> eee19a10 vmsr fpscr, r9 +0+42c <[^>]*> eee1aa10 vmsr fpscr, sl +0+430 <[^>]*> eee1ba10 vmsr fpscr, fp +0+434 <[^>]*> eee1ca10 vmsr fpscr, ip +0+438 <[^>]*> eee1ea10 vmsr fpscr, lr +0+43c <[^>]*> eee01a10 vmsr fpsid, r1 +0+440 <[^>]*> eee82a10 vmsr fpexc, r2 +0+444 <[^>]*> eee93a10 vmsr fpinst, r3 @ Impl def +0+448 <[^>]*> eeea4a10 vmsr fpinst2, r4 @ Impl def +0+44c <[^>]*> eeef5a10 vmsr (c15|<impl def 0xf>), r5 +0+450 <[^>]*> eef03a10 vmrs r3, fpsid +0+454 <[^>]*> eef64a10 vmrs r4, mvfr1 +0+458 <[^>]*> eef75a10 vmrs r5, mvfr0 +0+45c <[^>]*> eef86a10 vmrs r6, fpexc +0+460 <[^>]*> eef97a10 vmrs r7, fpinst @ Impl def +0+464 <[^>]*> eefa8a10 vmrs r8, fpinst2 @ Impl def +0+468 <[^>]*> eeff9a10 vmrs r9, (c15|<impl def 0xf>) +0+46c <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+470 <[^>]*> e1a00000 nop ; \(mov r0, r0\) +0+474 <[^>]*> e1a00000 nop ; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1xD.s b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD.s new file mode 100644 index 00000000..0e603e97 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD.s @@ -0,0 +1,400 @@ +@ VFP Instructions for v1xD variants (Single precision only) + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Most of these tests deliberatly use s0/r0 to avoid setting + @ any more bits than necessary. + + @ Comparison operations + + fmstat + + fcmpes s0, s0 + fcmpezs s0 + fcmps s0, s0 + fcmpzs s0 + + @ Monadic data operations + + fabss s0, s0 + fcpys s0, s0 + fnegs s0, s0 + fsqrts s0, s0 + + @ Dyadic data operations + + fadds s0, s0, s0 + fdivs s0, s0, s0 + fmacs s0, s0, s0 + fmscs s0, s0, s0 + fmuls s0, s0, s0 + fnmacs s0, s0, s0 + fnmscs s0, s0, s0 + fnmuls s0, s0, s0 + fsubs s0, s0, s0 + + @ Load/store operations + + flds s0, [r0] + fsts s0, [r0] + + @ Load/store multiple operations + + fldmias r0, {s0} + fldmfds r0, {s0} + fldmias r0!, {s0} + fldmfds r0!, {s0} + fldmdbs r0!, {s0} + fldmeas r0!, {s0} + + fldmiax r0, {d0} + fldmfdx r0, {d0} + fldmiax r0!, {d0} + fldmfdx r0!, {d0} + fldmdbx r0!, {d0} + fldmeax r0!, {d0} + + fstmias r0, {s0} + fstmeas r0, {s0} + fstmias r0!, {s0} + fstmeas r0!, {s0} + fstmdbs r0!, {s0} + fstmfds r0!, {s0} + + fstmiax r0, {d0} + fstmeax r0, {d0} + fstmiax r0!, {d0} + fstmeax r0!, {d0} + fstmdbx r0!, {d0} + fstmfdx r0!, {d0} + + @ Conversion operations + + fsitos s0, s0 + fuitos s0, s0 + + ftosis s0, s0 + ftosizs s0, s0 + ftouis s0, s0 + ftouizs s0, s0 + + @ ARM from VFP operations + + fmrs r0, s0 + fmrx r0, fpsid + fmrx r0, fpscr + fmrx r0, fpexc + + @ VFP From ARM operations + + fmsr s0, r0 + fmxr fpsid, r0 + fmxr fpscr, r0 + fmxr fpexc, r0 + + @ Now we test that the register fields are updated correctly for + @ each class of instruction. + + @ Single register operations (compare-zero): + + fcmpzs s1 + fcmpzs s2 + fcmpzs s31 + + @ Two register comparison operations: + + fcmps s0, s1 + fcmps s0, s2 + fcmps s0, s31 + fcmps s1, s0 + fcmps s2, s0 + fcmps s31, s0 + fcmps s21, s12 + + @ Two register data operations (monadic) + + fnegs s0, s1 + fnegs s0, s2 + fnegs s0, s31 + fnegs s1, s0 + fnegs s2, s0 + fnegs s31, s0 + fnegs s12, s21 + + @ Three register data operations (dyadic) + + fadds s0, s0, s1 + fadds s0, s0, s2 + fadds s0, s0, s31 + fadds s0, s1, s0 + fadds s0, s2, s0 + fadds s0, s31, s0 + fadds s1, s0, s0 + fadds s2, s0, s0 + fadds s31, s0, s0 + fadds s12, s21, s5 + + @ Conversion operations + + fsitos s0, s1 + fsitos s0, s2 + fsitos s0, s31 + fsitos s1, s0 + fsitos s2, s0 + fsitos s31, s0 + + ftosis s0, s1 + ftosis s0, s2 + ftosis s0, s31 + ftosis s1, s0 + ftosis s2, s0 + ftosis s31, s0 + + @ Move to VFP from ARM + + fmsr s0, r1 + fmsr s0, r7 + fmsr s0, r14 + fmsr s1, r0 + fmsr s2, r0 + fmsr s31, r0 + fmsr s21, r7 + + fmxr fpsid, r1 + fmxr fpsid, r14 + + @ Move to ARM from VFP + + fmrs r0, s1 + fmrs r0, s2 + fmrs r0, s31 + fmrs r1, s0 + fmrs r7, s0 + fmrs r14, s0 + fmrs r9, s11 + + fmrx r1, fpsid + fmrx r14, fpsid + + @ Load/store operations + + flds s0, [r1] + flds s0, [r14] + flds s0, [r0, #0] + flds s0, [r0, #1020] + flds s0, [r0, #-1020] + flds s1, [r0] + flds s2, [r0] + flds s31, [r0] + fsts s21, [r12, #804] + + @ Load/store multiple operations + + fldmias r0, {s1} + fldmias r0, {s2} + fldmias r0, {s31} + fldmias r0, {s0-s1} + fldmias r0, {s0-s2} + fldmias r0, {s0-s31} + fldmias r0, {s1-s31} + fldmias r0, {s2-s31} + fldmias r0, {s30-s31} + fldmias r1, {s0} + fldmias r14, {s0} + + fstmiax r0, {d1} + fstmiax r0, {d2} + fstmiax r0, {d15} + fstmiax r0, {d0-d1} + fstmiax r0, {d0-d2} + fstmiax r0, {d0-d15} + fstmiax r0, {d1-d15} + fstmiax r0, {d2-d15} + fstmiax r0, {d14-d15} + fstmiax r1, {d0} + fstmiax r14, {d0} + + @ Check that we assemble all the register names correctly + + fcmpzs s0 + fcmpzs s1 + fcmpzs s2 + fcmpzs s3 + fcmpzs s4 + fcmpzs s5 + fcmpzs s6 + fcmpzs s7 + fcmpzs s8 + fcmpzs s9 + fcmpzs s10 + fcmpzs s11 + fcmpzs s12 + fcmpzs s13 + fcmpzs s14 + fcmpzs s15 + fcmpzs s16 + fcmpzs s17 + fcmpzs s18 + fcmpzs s19 + fcmpzs s20 + fcmpzs s21 + fcmpzs s22 + fcmpzs s23 + fcmpzs s24 + fcmpzs s25 + fcmpzs s26 + fcmpzs s27 + fcmpzs s28 + fcmpzs s29 + fcmpzs s30 + fcmpzs s31 + + @ Now we check the placement of the conditional execution substring. + @ On VFP this is always at the end of the instruction. + @ We use different register numbers here to check for correct + @ disassembly + + @ Comparison operations + + fmstateq + + fcmpeseq s3, s7 + fcmpezseq s5 + fcmpseq s1, s2 + fcmpzseq s1 + + @ Monadic data operations + + fabsseq s1, s3 + fcpyseq s31, s19 + fnegseq s20, s8 + fsqrtseq s5, s7 + + @ Dyadic data operations + + faddseq s6, s5, s4 + fdivseq s3, s2, s1 + fmacseq s31, s30, s29 + fmscseq s28, s27, s26 + fmulseq s25, s24, s23 + fnmacseq s22, s21, s20 + fnmscseq s19, s18, s17 + fnmulseq s16, s15, s14 + fsubseq s13, s12, s11 + + @ Load/store operations + + fldseq s10, [r8] + fstseq s9, [r7] + + @ Load/store multiple operations + + fldmiaseq r1, {s8} + fldmfdseq r2, {s7} + fldmiaseq r3!, {s6} + fldmfdseq r4!, {s5} + fldmdbseq r5!, {s4} + fldmeaseq r6!, {s3} + + fldmiaxeq r7, {d1} + fldmfdxeq r8, {d2} + fldmiaxeq r9!, {d3} + fldmfdxeq r10!, {d4} + fldmdbxeq r11!, {d5} + fldmeaxeq r12!, {d6} + + fstmiaseq r13, {s2} + fstmeaseq r14, {s1} + fstmiaseq r1!, {s31} + fstmeaseq r2!, {s30} + fstmdbseq r3!, {s29} + fstmfdseq r4!, {s28} + + fstmiaxeq r5, {d7} + fstmeaxeq r6, {d8} + fstmiaxeq r7!, {d9} + fstmeaxeq r8!, {d10} + fstmdbxeq r9!, {d11} + fstmfdxeq r10!, {d12} + + @ Conversion operations + + fsitoseq s27, s6 + ftosiseq s25, s5 + ftosizseq s23, s4 + ftouiseq s21, s3 + ftouizseq s19, s2 + fuitoseq s17, s1 + + @ ARM from VFP operations + + fmrseq r11, s3 + fmrxeq r9, fpsid + + @ VFP From ARM operations + + fmsreq s3, r9 + fmxreq fpsid, r8 + + @ Implementation specific system registers + fmrx r0, fpinst + fmrx r0, fpinst2 + fmrx r0, mvfr0 + fmrx r0, mvfr1 + fmrx r0, c12 + fmxr fpinst, r0 + fmxr fpinst2, r0 + fmxr mvfr0, r0 + fmxr mvfr1, r0 + fmxr c12, r0 + + @ ARM VMSR/VMRS instructions + vmrs r0, FPSCR + vmrs r1, FPSCR + vmrs r2, FPSCR + vmrs r3, FPSCR + vmrs r4, FPSCR + vmrs r5, FPSCR + vmrs r6, FPSCR + vmrs r7, FPSCR + vmrs r8, FPSCR + vmrs r9, FPSCR + vmrs r10, FPSCR + vmrs r11, FPSCR + vmrs r12, FPSCR + vmrs r14, FPSCR + vmrs APSR_nzcv, FPSCR + + vmsr FPSCR, r0 + vmsr FPSCR, r1 + vmsr FPSCR, r2 + vmsr FPSCR, r3 + vmsr FPSCR, r4 + vmsr FPSCR, r5 + vmsr FPSCR, r6 + vmsr FPSCR, r7 + vmsr FPSCR, r8 + vmsr FPSCR, r9 + vmsr FPSCR, r10 + vmsr FPSCR, r11 + vmsr FPSCR, r12 + vmsr FPSCR, r14 + + @ Priviledged extensions to VMSR/VMRS instructions + vmsr FPSID, r1 + vmsr FPEXC, r2 + vmsr FPINST, r3 + vmsr FPINST2, r4 + vmsr C15, r5 + vmrs r3, FPSID + vmrs r4, MVFR1 + vmrs r5, MVFR0 + vmrs r6, FPEXC + vmrs r7, FPINST + vmrs r8, FPINST2 + vmrs r9, C15 + + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1xD_t2.d b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD_t2.d new file mode 100644 index 00000000..7dd5030f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD_t2.d @@ -0,0 +1,271 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Thumb-2 VFP Single-precision instructions +#as: -mfpu=vfpxd -mcpu=arm1156t2f-s + +# Test the ARM VFP Single Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> eef1 fa10 (vmrs APSR_nzcv, fpscr|fmstat) +0+004 <[^>]*> eeb4 0ac0 (vcmpe\.f32|fcmpes) s0, s0 +0+008 <[^>]*> eeb5 0ac0 (vcmpe\.f32 s0, #0.0|fcmpezs s0) +0+00c <[^>]*> eeb4 0a40 (vcmp\.f32|fcmps) s0, s0 +0+010 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0) +0+014 <[^>]*> eeb0 0ac0 (vabs\.f32|fabss) s0, s0 +0+018 <[^>]*> eeb0 0a40 (vmov\.f32|fcpys) s0, s0 +0+01c <[^>]*> eeb1 0a40 (vneg\.f32|fnegs) s0, s0 +0+020 <[^>]*> eeb1 0ac0 (vsqrt\.f32|fsqrts) s0, s0 +0+024 <[^>]*> ee30 0a00 (vadd\.f32|fadds) s0, s0, s0 +0+028 <[^>]*> ee80 0a00 (vdiv\.f32|fdivs) s0, s0, s0 +0+02c <[^>]*> ee00 0a00 (vmla\.f32|fmacs) s0, s0, s0 +0+030 <[^>]*> ee10 0a00 (vnmls\.f32|fmscs) s0, s0, s0 +0+034 <[^>]*> ee20 0a00 (vmul\.f32|fmuls) s0, s0, s0 +0+038 <[^>]*> ee00 0a40 (vmls\.f32|fnmacs) s0, s0, s0 +0+03c <[^>]*> ee10 0a40 (vnmla\.f32|fnmscs) s0, s0, s0 +0+040 <[^>]*> ee20 0a40 (vnmul\.f32|fnmuls) s0, s0, s0 +0+044 <[^>]*> ee30 0a40 (vsub\.f32|fsubs) s0, s0, s0 +0+048 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\] +0+04c <[^>]*> ed80 0a00 (vstr|fsts) s0, \[r0\] +0+050 <[^>]*> ec90 0a01 (vldmia|fldmias) r0, {s0} +0+054 <[^>]*> ec90 0a01 (vldmia|fldmias) r0, {s0} +0+058 <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0} +0+05c <[^>]*> ecb0 0a01 (vldmia|fldmias) r0!, {s0} +0+060 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0} +0+064 <[^>]*> ed30 0a01 (vldmdb|fldmdbs) r0!, {s0} +0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|) +0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0}( ;@ Deprecated|) +0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|) +0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0}( ;@ Deprecated|) +0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|) +0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0}( ;@ Deprecated|) +0+080 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0} +0+084 <[^>]*> ec80 0a01 (vstmia|fstmias) r0, {s0} +0+088 <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0} +0+08c <[^>]*> eca0 0a01 (vstmia|fstmias) r0!, {s0} +0+090 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0} +0+094 <[^>]*> ed20 0a01 (vstmdb|fstmdbs) r0!, {s0} +0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|) +0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0}( ;@ Deprecated|) +0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|) +0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0}( ;@ Deprecated|) +0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|) +0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0}( ;@ Deprecated|) +0+0b0 <[^>]*> eeb8 0ac0 (vcvt\.f32\.s32|fsitos) s0, s0 +0+0b4 <[^>]*> eeb8 0a40 (vcvt\.f32\.u32|fuitos) s0, s0 +0+0b8 <[^>]*> eebd 0a40 (vcvtr\.s32\.f32|ftosis) s0, s0 +0+0bc <[^>]*> eebd 0ac0 (vcvt\.s32\.f32|ftosizs) s0, s0 +0+0c0 <[^>]*> eebc 0a40 (vcvtr\.u32\.f32|ftouis) s0, s0 +0+0c4 <[^>]*> eebc 0ac0 (vcvt\.u32\.f32|ftouizs) s0, s0 +0+0c8 <[^>]*> ee10 0a10 (vmov|fmrs) r0, s0 +0+0cc <[^>]*> eef0 0a10 (vmrs|fmrx) r0, fpsid +0+0d0 <[^>]*> eef1 0a10 (vmrs|fmrx) r0, fpscr +0+0d4 <[^>]*> eef8 0a10 (vmrs|fmrx) r0, fpexc +0+0d8 <[^>]*> ee00 0a10 (vmov|fmsr) s0, r0 +0+0dc <[^>]*> eee0 0a10 (vmsr|fmxr) fpsid, r0 +0+0e0 <[^>]*> eee1 0a10 (vmsr|fmxr) fpscr, r0 +0+0e4 <[^>]*> eee8 0a10 (vmsr|fmxr) fpexc, r0 +0+0e8 <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1) +0+0ec <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2) +0+0f0 <[^>]*> eef5 fa40 (vcmp\.f32 s31, #0.0|fcmpzs s31) +0+0f4 <[^>]*> eeb4 0a60 (vcmp\.f32|fcmps) s0, s1 +0+0f8 <[^>]*> eeb4 0a41 (vcmp\.f32|fcmps) s0, s2 +0+0fc <[^>]*> eeb4 0a6f (vcmp\.f32|fcmps) s0, s31 +0+100 <[^>]*> eef4 0a40 (vcmp\.f32|fcmps) s1, s0 +0+104 <[^>]*> eeb4 1a40 (vcmp\.f32|fcmps) s2, s0 +0+108 <[^>]*> eef4 fa40 (vcmp\.f32|fcmps) s31, s0 +0+10c <[^>]*> eef4 aa46 (vcmp\.f32|fcmps) s21, s12 +0+110 <[^>]*> eeb1 0a60 (vneg\.f32|fnegs) s0, s1 +0+114 <[^>]*> eeb1 0a41 (vneg\.f32|fnegs) s0, s2 +0+118 <[^>]*> eeb1 0a6f (vneg\.f32|fnegs) s0, s31 +0+11c <[^>]*> eef1 0a40 (vneg\.f32|fnegs) s1, s0 +0+120 <[^>]*> eeb1 1a40 (vneg\.f32|fnegs) s2, s0 +0+124 <[^>]*> eef1 fa40 (vneg\.f32|fnegs) s31, s0 +0+128 <[^>]*> eeb1 6a6a (vneg\.f32|fnegs) s12, s21 +0+12c <[^>]*> ee30 0a20 (vadd\.f32|fadds) s0, s0, s1 +0+130 <[^>]*> ee30 0a01 (vadd\.f32|fadds) s0, s0, s2 +0+134 <[^>]*> ee30 0a2f (vadd\.f32|fadds) s0, s0, s31 +0+138 <[^>]*> ee30 0a80 (vadd\.f32|fadds) s0, s1, s0 +0+13c <[^>]*> ee31 0a00 (vadd\.f32|fadds) s0, s2, s0 +0+140 <[^>]*> ee3f 0a80 (vadd\.f32|fadds) s0, s31, s0 +0+144 <[^>]*> ee70 0a00 (vadd\.f32|fadds) s1, s0, s0 +0+148 <[^>]*> ee30 1a00 (vadd\.f32|fadds) s2, s0, s0 +0+14c <[^>]*> ee70 fa00 (vadd\.f32|fadds) s31, s0, s0 +0+150 <[^>]*> ee3a 6aa2 (vadd\.f32|fadds) s12, s21, s5 +0+154 <[^>]*> eeb8 0ae0 (vcvt\.f32\.s32|fsitos) s0, s1 +0+158 <[^>]*> eeb8 0ac1 (vcvt\.f32\.s32|fsitos) s0, s2 +0+15c <[^>]*> eeb8 0aef (vcvt\.f32\.s32|fsitos) s0, s31 +0+160 <[^>]*> eef8 0ac0 (vcvt\.f32\.s32|fsitos) s1, s0 +0+164 <[^>]*> eeb8 1ac0 (vcvt\.f32\.s32|fsitos) s2, s0 +0+168 <[^>]*> eef8 fac0 (vcvt\.f32\.s32|fsitos) s31, s0 +0+16c <[^>]*> eebd 0a60 (vcvtr\.s32\.f32|ftosis) s0, s1 +0+170 <[^>]*> eebd 0a41 (vcvtr\.s32\.f32|ftosis) s0, s2 +0+174 <[^>]*> eebd 0a6f (vcvtr\.s32\.f32|ftosis) s0, s31 +0+178 <[^>]*> eefd 0a40 (vcvtr\.s32\.f32|ftosis) s1, s0 +0+17c <[^>]*> eebd 1a40 (vcvtr\.s32\.f32|ftosis) s2, s0 +0+180 <[^>]*> eefd fa40 (vcvtr\.s32\.f32|ftosis) s31, s0 +0+184 <[^>]*> ee00 1a10 (vmov|fmsr) s0, r1 +0+188 <[^>]*> ee00 7a10 (vmov|fmsr) s0, r7 +0+18c <[^>]*> ee00 ea10 (vmov|fmsr) s0, lr +0+190 <[^>]*> ee00 0a90 (vmov|fmsr) s1, r0 +0+194 <[^>]*> ee01 0a10 (vmov|fmsr) s2, r0 +0+198 <[^>]*> ee0f 0a90 (vmov|fmsr) s31, r0 +0+19c <[^>]*> ee0a 7a90 (vmov|fmsr) s21, r7 +0+1a0 <[^>]*> eee0 1a10 (vmsr|fmxr) fpsid, r1 +0+1a4 <[^>]*> eee0 ea10 (vmsr|fmxr) fpsid, lr +0+1a8 <[^>]*> ee10 0a90 (vmov|fmrs) r0, s1 +0+1ac <[^>]*> ee11 0a10 (vmov|fmrs) r0, s2 +0+1b0 <[^>]*> ee1f 0a90 (vmov|fmrs) r0, s31 +0+1b4 <[^>]*> ee10 1a10 (vmov|fmrs) r1, s0 +0+1b8 <[^>]*> ee10 7a10 (vmov|fmrs) r7, s0 +0+1bc <[^>]*> ee10 ea10 (vmov|fmrs) lr, s0 +0+1c0 <[^>]*> ee15 9a90 (vmov|fmrs) r9, s11 +0+1c4 <[^>]*> eef0 1a10 (vmrs|fmrx) r1, fpsid +0+1c8 <[^>]*> eef0 ea10 (vmrs|fmrx) lr, fpsid +0+1cc <[^>]*> ed91 0a00 (vldr|flds) s0, \[r1\] +0+1d0 <[^>]*> ed9e 0a00 (vldr|flds) s0, \[lr\] +0+1d4 <[^>]*> ed90 0a00 (vldr|flds) s0, \[r0\] +0+1d8 <[^>]*> ed90 0aff (vldr|flds) s0, \[r0, #1020\].* +0+1dc <[^>]*> ed10 0aff (vldr|flds) s0, \[r0, #-1020\].* +0+1e0 <[^>]*> edd0 0a00 (vldr|flds) s1, \[r0\] +0+1e4 <[^>]*> ed90 1a00 (vldr|flds) s2, \[r0\] +0+1e8 <[^>]*> edd0 fa00 (vldr|flds) s31, \[r0\] +0+1ec <[^>]*> edcc aac9 (vstr|fsts) s21, \[ip, #804\].* +0+1f0 <[^>]*> ecd0 0a01 (vldmia|fldmias) r0, {s1} +0+1f4 <[^>]*> ec90 1a01 (vldmia|fldmias) r0, {s2} +0+1f8 <[^>]*> ecd0 fa01 (vldmia|fldmias) r0, {s31} +0+1fc <[^>]*> ec90 0a02 (vldmia|fldmias) r0, {s0-s1} +0+200 <[^>]*> ec90 0a03 (vldmia|fldmias) r0, {s0-s2} +0+204 <[^>]*> ec90 0a20 (vldmia|fldmias) r0, {s0-s31} +0+208 <[^>]*> ecd0 0a1f (vldmia|fldmias) r0, {s1-s31} +0+20c <[^>]*> ec90 1a1e (vldmia|fldmias) r0, {s2-s31} +0+210 <[^>]*> ec90 fa02 (vldmia|fldmias) r0, {s30-s31} +0+214 <[^>]*> ec91 0a01 (vldmia|fldmias) r1, {s0} +0+218 <[^>]*> ec9e 0a01 (vldmia|fldmias) lr, {s0} +0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1}( ;@ Deprecated|) +0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2}( ;@ Deprecated|) +0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15}( ;@ Deprecated|) +0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1}( ;@ Deprecated|) +0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2}( ;@ Deprecated|) +0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15}( ;@ Deprecated|) +0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15}( ;@ Deprecated|) +0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15}( ;@ Deprecated|) +0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15}( ;@ Deprecated|) +0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0}( ;@ Deprecated|) +0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0}( ;@ Deprecated|) +0+248 <[^>]*> eeb5 0a40 (vcmp\.f32 s0, #0.0|fcmpzs s0) +0+24c <[^>]*> eef5 0a40 (vcmp\.f32 s1, #0.0|fcmpzs s1) +0+250 <[^>]*> eeb5 1a40 (vcmp\.f32 s2, #0.0|fcmpzs s2) +0+254 <[^>]*> eef5 1a40 (vcmp\.f32 s3, #0.0|fcmpzs s3) +0+258 <[^>]*> eeb5 2a40 (vcmp\.f32 s4, #0.0|fcmpzs s4) +0+25c <[^>]*> eef5 2a40 (vcmp\.f32 s5, #0.0|fcmpzs s5) +0+260 <[^>]*> eeb5 3a40 (vcmp\.f32 s6, #0.0|fcmpzs s6) +0+264 <[^>]*> eef5 3a40 (vcmp\.f32 s7, #0.0|fcmpzs s7) +0+268 <[^>]*> eeb5 4a40 (vcmp\.f32 s8, #0.0|fcmpzs s8) +0+26c <[^>]*> eef5 4a40 (vcmp\.f32 s9, #0.0|fcmpzs s9) +0+270 <[^>]*> eeb5 5a40 (vcmp\.f32 s10, #0.0|fcmpzs s10) +0+274 <[^>]*> eef5 5a40 (vcmp\.f32 s11, #0.0|fcmpzs s11) +0+278 <[^>]*> eeb5 6a40 (vcmp\.f32 s12, #0.0|fcmpzs s12) +0+27c <[^>]*> eef5 6a40 (vcmp\.f32 s13, #0.0|fcmpzs s13) +0+280 <[^>]*> eeb5 7a40 (vcmp\.f32 s14, #0.0|fcmpzs s14) +0+284 <[^>]*> eef5 7a40 (vcmp\.f32 s15, #0.0|fcmpzs s15) +0+288 <[^>]*> eeb5 8a40 (vcmp\.f32 s16, #0.0|fcmpzs s16) +0+28c <[^>]*> eef5 8a40 (vcmp\.f32 s17, #0.0|fcmpzs s17) +0+290 <[^>]*> eeb5 9a40 (vcmp\.f32 s18, #0.0|fcmpzs s18) +0+294 <[^>]*> eef5 9a40 (vcmp\.f32 s19, #0.0|fcmpzs s19) +0+298 <[^>]*> eeb5 aa40 (vcmp\.f32 s20, #0.0|fcmpzs s20) +0+29c <[^>]*> eef5 aa40 (vcmp\.f32 s21, #0.0|fcmpzs s21) +0+2a0 <[^>]*> eeb5 ba40 (vcmp\.f32 s22, #0.0|fcmpzs s22) +0+2a4 <[^>]*> eef5 ba40 (vcmp\.f32 s23, #0.0|fcmpzs s23) +0+2a8 <[^>]*> eeb5 ca40 (vcmp\.f32 s24, #0.0|fcmpzs s24) +0+2ac <[^>]*> eef5 ca40 (vcmp\.f32 s25, #0.0|fcmpzs s25) +0+2b0 <[^>]*> eeb5 da40 (vcmp\.f32 s26, #0.0|fcmpzs s26) +0+2b4 <[^>]*> eef5 da40 (vcmp\.f32 s27, #0.0|fcmpzs s27) +0+2b8 <[^>]*> eeb5 ea40 (vcmp\.f32 s28, #0.0|fcmpzs s28) +0+2bc <[^>]*> eef5 ea40 (vcmp\.f32 s29, #0.0|fcmpzs s29) +0+2c0 <[^>]*> eeb5 fa40 (vcmp\.f32 s30, #0.0|fcmpzs s30) +0+2c4 <[^>]*> eef5 fa40 (vcmp\.f32 s31, #0.0|fcmpzs s31) +0+2c8 <[^>]*> bf01 itttt eq +0+2ca <[^>]*> eef1 fa10 (vmrseq APSR_nzcv, fpscr|fmstateq) +0+2ce <[^>]*> eef4 1ae3 (vcmpeeq\.f32|fcmpeseq) s3, s7 +0+2d2 <[^>]*> eef5 2ac0 (vcmpeeq\.f32 s5, #0.0|fcmpezseq s5) +0+2d6 <[^>]*> eef4 0a41 (vcmpeq\.f32|fcmpseq) s1, s2 +0+2da <[^>]*> bf01 itttt eq +0+2dc <[^>]*> eef5 0a40 (vcmpeq\.f32 s1, #0.0|fcmpzseq s1) +0+2e0 <[^>]*> eef0 0ae1 (vabseq\.f32|fabsseq) s1, s3 +0+2e4 <[^>]*> eef0 fa69 (vmoveq\.f32|fcpyseq) s31, s19 +0+2e8 <[^>]*> eeb1 aa44 (vnegeq\.f32|fnegseq) s20, s8 +0+2ec <[^>]*> bf01 itttt eq +0+2ee <[^>]*> eef1 2ae3 (vsqrteq\.f32|fsqrtseq) s5, s7 +0+2f2 <[^>]*> ee32 3a82 (vaddeq\.f32|faddseq) s6, s5, s4 +0+2f6 <[^>]*> eec1 1a20 (vdiveq\.f32|fdivseq) s3, s2, s1 +0+2fa <[^>]*> ee4f fa2e (vmlaeq\.f32|fmacseq) s31, s30, s29 +0+2fe <[^>]*> bf01 itttt eq +0+300 <[^>]*> ee1d ea8d (vnmlseq\.f32|fmscseq) s28, s27, s26 +0+304 <[^>]*> ee6c ca2b (vmuleq\.f32|fmulseq) s25, s24, s23 +0+308 <[^>]*> ee0a baca (vmlseq\.f32|fnmacseq) s22, s21, s20 +0+30c <[^>]*> ee59 9a68 (vnmlaeq\.f32|fnmscseq) s19, s18, s17 +0+310 <[^>]*> bf01 itttt eq +0+312 <[^>]*> ee27 8ac7 (vnmuleq\.f32|fnmulseq) s16, s15, s14 +0+316 <[^>]*> ee76 6a65 (vsubeq\.f32|fsubseq) s13, s12, s11 +0+31a <[^>]*> ed98 5a00 (vldreq|fldseq) s10, \[r8\] +0+31e <[^>]*> edc7 4a00 (vstreq|fstseq) s9, \[r7\] +0+322 <[^>]*> bf01 itttt eq +0+324 <[^>]*> ec91 4a01 (vldmiaeq|fldmiaseq) r1, {s8} +0+328 <[^>]*> ecd2 3a01 (vldmiaeq|fldmiaseq) r2, {s7} +0+32c <[^>]*> ecb3 3a01 (vldmiaeq|fldmiaseq) r3!, {s6} +0+330 <[^>]*> ecf4 2a01 (vldmiaeq|fldmiaseq) r4!, {s5} +0+334 <[^>]*> bf01 itttt eq +0+336 <[^>]*> ed35 2a01 (vldmdbeq|fldmdbseq) r5!, {s4} +0+33a <[^>]*> ed76 1a01 (vldmdbeq|fldmdbseq) r6!, {s3} +0+33e <[^>]*> ec97 1b03 fldmiaxeq r7, {d1}( ;@ Deprecated|) +0+342 <[^>]*> ec98 2b03 fldmiaxeq r8, {d2}( ;@ Deprecated|) +0+346 <[^>]*> bf01 itttt eq +0+348 <[^>]*> ecb9 3b03 fldmiaxeq r9!, {d3}( ;@ Deprecated|) +0+34c <[^>]*> ecba 4b03 fldmiaxeq sl!, {d4}( ;@ Deprecated|) +0+350 <[^>]*> ed3b 5b03 fldmdbxeq fp!, {d5}( ;@ Deprecated|) +0+354 <[^>]*> ed3c 6b03 fldmdbxeq ip!, {d6}( ;@ Deprecated|) +0+358 <[^>]*> bf01 itttt eq +0+35a <[^>]*> ec8d 1a01 (vstmiaeq|fstmiaseq) sp, {s2} +0+35e <[^>]*> ecce 0a01 (vstmiaeq|fstmiaseq) lr, {s1} +0+362 <[^>]*> ece1 fa01 (vstmiaeq|fstmiaseq) r1!, {s31} +0+366 <[^>]*> eca2 fa01 (vstmiaeq|fstmiaseq) r2!, {s30} +0+36a <[^>]*> bf01 itttt eq +0+36c <[^>]*> ed63 ea01 (vstmdbeq|fstmdbseq) r3!, {s29} +0+370 <[^>]*> ed24 ea01 (vstmdbeq|fstmdbseq) r4!, {s28} +0+374 <[^>]*> ec85 7b03 fstmiaxeq r5, {d7}( ;@ Deprecated|) +0+378 <[^>]*> ec86 8b03 fstmiaxeq r6, {d8}( ;@ Deprecated|) +0+37c <[^>]*> bf01 itttt eq +0+37e <[^>]*> eca7 9b03 fstmiaxeq r7!, {d9}( ;@ Deprecated|) +0+382 <[^>]*> eca8 ab03 fstmiaxeq r8!, {d10}( ;@ Deprecated|) +0+386 <[^>]*> ed29 bb03 fstmdbxeq r9!, {d11}( ;@ Deprecated|) +0+38a <[^>]*> ed2a cb03 fstmdbxeq sl!, {d12}( ;@ Deprecated|) +0+38e <[^>]*> bf01 itttt eq +0+390 <[^>]*> eef8 dac3 (vcvteq\.f32\.s32|fsitoseq) s27, s6 +0+394 <[^>]*> eefd ca62 (vcvtreq\.s32\.f32|ftosiseq) s25, s5 +0+398 <[^>]*> eefd bac2 (vcvteq\.s32\.f32|ftosizseq) s23, s4 +0+39c <[^>]*> eefc aa61 (vcvtreq\.u32\.f32|ftouiseq) s21, s3 +0+3a0 <[^>]*> bf01 itttt eq +0+3a2 <[^>]*> eefc 9ac1 (vcvteq\.u32\.f32|ftouizseq) s19, s2 +0+3a6 <[^>]*> eef8 8a60 (vcvteq\.f32\.u32|fuitoseq) s17, s1 +0+3aa <[^>]*> ee11 ba90 (vmoveq|fmrseq) fp, s3 +0+3ae <[^>]*> eef0 9a10 (vmrseq|fmrxeq) r9, fpsid +0+3b2 <[^>]*> bf04 itt eq +0+3b4 <[^>]*> ee01 9a90 (vmoveq|fmsreq) s3, r9 +0+3b8 <[^>]*> eee0 8a10 (vmsreq|fmxreq) fpsid, r8 +0+3bc <[^>]*> eef9 0a10 (vmrs|fmrx) r0, fpinst @ Impl def +0+3c0 <[^>]*> eefa 0a10 (vmrs|fmrx) r0, fpinst2 @ Impl def +0+3c4 <[^>]*> eef7 0a10 (vmrs|fmrx) r0, mvfr0 +0+3c8 <[^>]*> eef6 0a10 (vmrs|fmrx) r0, mvfr1 +0+3cc <[^>]*> eefc 0a10 (vmrs|fmrx) r0, <impl def 0xc> +0+3d0 <[^>]*> eee9 0a10 (vmsr|fmxr) fpinst, r0 @ Impl def +0+3d4 <[^>]*> eeea 0a10 (vmsr|fmxr) fpinst2, r0 @ Impl def +0+3d8 <[^>]*> eee7 0a10 (vmsr|fmxr) mvfr0, r0 +0+3dc <[^>]*> eee6 0a10 (vmsr|fmxr) mvfr1, r0 +0+3e0 <[^>]*> eeec 0a10 (vmsr|fmxr) <impl def 0xc>, r0 +0+3e4 <[^>]*> bf00 nop +0+3e6 <[^>]*> bf00 nop +0+3e8 <[^>]*> bf00 nop +0+3ea <[^>]*> bf00 nop +0+3ec <[^>]*> bf00 nop +0+3ee <[^>]*> bf00 nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp1xD_t2.s b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD_t2.s new file mode 100644 index 00000000..8e962c07 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp1xD_t2.s @@ -0,0 +1,374 @@ +@ VFP Instructions for v1xD variants (Single precision only) +@ Same as vfp1xD.s, but for Thumb-2 + .syntax unified + .thumb + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Most of these tests deliberatly use s0/r0 to avoid setting + @ any more bits than necessary. + + @ Comparison operations + + fmstat + + fcmpes s0, s0 + fcmpezs s0 + fcmps s0, s0 + fcmpzs s0 + + @ Monadic data operations + + fabss s0, s0 + fcpys s0, s0 + fnegs s0, s0 + fsqrts s0, s0 + + @ Dyadic data operations + + fadds s0, s0, s0 + fdivs s0, s0, s0 + fmacs s0, s0, s0 + fmscs s0, s0, s0 + fmuls s0, s0, s0 + fnmacs s0, s0, s0 + fnmscs s0, s0, s0 + fnmuls s0, s0, s0 + fsubs s0, s0, s0 + + @ Load/store operations + + flds s0, [r0] + fsts s0, [r0] + + @ Load/store multiple operations + + fldmias r0, {s0} + fldmfds r0, {s0} + fldmias r0!, {s0} + fldmfds r0!, {s0} + fldmdbs r0!, {s0} + fldmeas r0!, {s0} + + fldmiax r0, {d0} + fldmfdx r0, {d0} + fldmiax r0!, {d0} + fldmfdx r0!, {d0} + fldmdbx r0!, {d0} + fldmeax r0!, {d0} + + fstmias r0, {s0} + fstmeas r0, {s0} + fstmias r0!, {s0} + fstmeas r0!, {s0} + fstmdbs r0!, {s0} + fstmfds r0!, {s0} + + fstmiax r0, {d0} + fstmeax r0, {d0} + fstmiax r0!, {d0} + fstmeax r0!, {d0} + fstmdbx r0!, {d0} + fstmfdx r0!, {d0} + + @ Conversion operations + + fsitos s0, s0 + fuitos s0, s0 + + ftosis s0, s0 + ftosizs s0, s0 + ftouis s0, s0 + ftouizs s0, s0 + + @ ARM from VFP operations + + fmrs r0, s0 + fmrx r0, fpsid + fmrx r0, fpscr + fmrx r0, fpexc + + @ VFP From ARM operations + + fmsr s0, r0 + fmxr fpsid, r0 + fmxr fpscr, r0 + fmxr fpexc, r0 + + @ Now we test that the register fields are updated correctly for + @ each class of instruction. + + @ Single register operations (compare-zero): + + fcmpzs s1 + fcmpzs s2 + fcmpzs s31 + + @ Two register comparison operations: + + fcmps s0, s1 + fcmps s0, s2 + fcmps s0, s31 + fcmps s1, s0 + fcmps s2, s0 + fcmps s31, s0 + fcmps s21, s12 + + @ Two register data operations (monadic) + + fnegs s0, s1 + fnegs s0, s2 + fnegs s0, s31 + fnegs s1, s0 + fnegs s2, s0 + fnegs s31, s0 + fnegs s12, s21 + + @ Three register data operations (dyadic) + + fadds s0, s0, s1 + fadds s0, s0, s2 + fadds s0, s0, s31 + fadds s0, s1, s0 + fadds s0, s2, s0 + fadds s0, s31, s0 + fadds s1, s0, s0 + fadds s2, s0, s0 + fadds s31, s0, s0 + fadds s12, s21, s5 + + @ Conversion operations + + fsitos s0, s1 + fsitos s0, s2 + fsitos s0, s31 + fsitos s1, s0 + fsitos s2, s0 + fsitos s31, s0 + + ftosis s0, s1 + ftosis s0, s2 + ftosis s0, s31 + ftosis s1, s0 + ftosis s2, s0 + ftosis s31, s0 + + @ Move to VFP from ARM + + fmsr s0, r1 + fmsr s0, r7 + fmsr s0, r14 + fmsr s1, r0 + fmsr s2, r0 + fmsr s31, r0 + fmsr s21, r7 + + fmxr fpsid, r1 + fmxr fpsid, r14 + + @ Move to ARM from VFP + + fmrs r0, s1 + fmrs r0, s2 + fmrs r0, s31 + fmrs r1, s0 + fmrs r7, s0 + fmrs r14, s0 + fmrs r9, s11 + + fmrx r1, fpsid + fmrx r14, fpsid + + @ Load/store operations + + flds s0, [r1] + flds s0, [r14] + flds s0, [r0, #0] + flds s0, [r0, #1020] + flds s0, [r0, #-1020] + flds s1, [r0] + flds s2, [r0] + flds s31, [r0] + fsts s21, [r12, #804] + + @ Load/store multiple operations + + fldmias r0, {s1} + fldmias r0, {s2} + fldmias r0, {s31} + fldmias r0, {s0-s1} + fldmias r0, {s0-s2} + fldmias r0, {s0-s31} + fldmias r0, {s1-s31} + fldmias r0, {s2-s31} + fldmias r0, {s30-s31} + fldmias r1, {s0} + fldmias r14, {s0} + + fstmiax r0, {d1} + fstmiax r0, {d2} + fstmiax r0, {d15} + fstmiax r0, {d0-d1} + fstmiax r0, {d0-d2} + fstmiax r0, {d0-d15} + fstmiax r0, {d1-d15} + fstmiax r0, {d2-d15} + fstmiax r0, {d14-d15} + fstmiax r1, {d0} + fstmiax r14, {d0} + + @ Check that we assemble all the register names correctly + + fcmpzs s0 + fcmpzs s1 + fcmpzs s2 + fcmpzs s3 + fcmpzs s4 + fcmpzs s5 + fcmpzs s6 + fcmpzs s7 + fcmpzs s8 + fcmpzs s9 + fcmpzs s10 + fcmpzs s11 + fcmpzs s12 + fcmpzs s13 + fcmpzs s14 + fcmpzs s15 + fcmpzs s16 + fcmpzs s17 + fcmpzs s18 + fcmpzs s19 + fcmpzs s20 + fcmpzs s21 + fcmpzs s22 + fcmpzs s23 + fcmpzs s24 + fcmpzs s25 + fcmpzs s26 + fcmpzs s27 + fcmpzs s28 + fcmpzs s29 + fcmpzs s30 + fcmpzs s31 + + @ Now we check the placement of the conditional execution substring. + @ On VFP this is always at the end of the instruction. + @ We use different register numbers here to check for correct + @ disassembly + + @ Comparison operations + + itttt eq + fmstateq + + fcmpeseq s3, s7 + fcmpezseq s5 + fcmpseq s1, s2 + itttt eq + fcmpzseq s1 + + @ Monadic data operations + + fabsseq s1, s3 + fcpyseq s31, s19 + fnegseq s20, s8 + itttt eq + fsqrtseq s5, s7 + + @ Dyadic data operations + + faddseq s6, s5, s4 + fdivseq s3, s2, s1 + fmacseq s31, s30, s29 + itttt eq + fmscseq s28, s27, s26 + fmulseq s25, s24, s23 + fnmacseq s22, s21, s20 + fnmscseq s19, s18, s17 + itttt eq + fnmulseq s16, s15, s14 + fsubseq s13, s12, s11 + + @ Load/store operations + + fldseq s10, [r8] + fstseq s9, [r7] + + @ Load/store multiple operations + + itttt eq + fldmiaseq r1, {s8} + fldmfdseq r2, {s7} + fldmiaseq r3!, {s6} + fldmfdseq r4!, {s5} + itttt eq + fldmdbseq r5!, {s4} + fldmeaseq r6!, {s3} + + fldmiaxeq r7, {d1} + fldmfdxeq r8, {d2} + itttt eq + fldmiaxeq r9!, {d3} + fldmfdxeq r10!, {d4} + fldmdbxeq r11!, {d5} + fldmeaxeq r12!, {d6} + + itttt eq + fstmiaseq r13, {s2} + fstmeaseq r14, {s1} + fstmiaseq r1!, {s31} + fstmeaseq r2!, {s30} + itttt eq + fstmdbseq r3!, {s29} + fstmfdseq r4!, {s28} + + fstmiaxeq r5, {d7} + fstmeaxeq r6, {d8} + itttt eq + fstmiaxeq r7!, {d9} + fstmeaxeq r8!, {d10} + fstmdbxeq r9!, {d11} + fstmfdxeq r10!, {d12} + + @ Conversion operations + + itttt eq + fsitoseq s27, s6 + ftosiseq s25, s5 + ftosizseq s23, s4 + ftouiseq s21, s3 + itttt eq + ftouizseq s19, s2 + fuitoseq s17, s1 + + @ ARM from VFP operations + + fmrseq r11, s3 + fmrxeq r9, fpsid + + @ VFP From ARM operations + + itt eq + fmsreq s3, r9 + fmxreq fpsid, r8 + + @ Implementation specific system registers + fmrx r0, fpinst + fmrx r0, fpinst2 + fmrx r0, mvfr0 + fmrx r0, mvfr1 + fmrx r0, c12 + fmxr fpinst, r0 + fmxr fpinst2, r0 + fmxr mvfr0, r0 + fmxr mvfr1, r0 + fmxr c12, r0 + + nop + nop + nop + nop + nop + nop diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp2.d b/binutils-2.25/gas/testsuite/gas/arm/vfp2.d new file mode 100644 index 00000000..6dc6d076 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp2.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: VFP Additional instructions +#as: -mfpu=vfp + +# Test the ARM VFP Double Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> ec4a5b10 vmov d0, r5, sl +0+004 <[^>]*> ec5a5b10 vmov r5, sl, d0 +0+008 <[^>]*> ec4a5a37 (vmov s15, s16, r5, sl|fmsrr {s15, s16}, r5, sl) +0+00c <[^>]*> ec5a5a37 (vmov r5, sl, s15, s16|fmrrs r5, sl, {s15, s16}) +0+010 <[^>]*> ec45ab1f vmov d15, sl, r5 +0+014 <[^>]*> ec55ab1f vmov sl, r5, d15 +0+018 <[^>]*> ec45aa38 (vmov s17, s18, sl, r5|fmsrr {s17, s18}, sl, r5) +0+01c <[^>]*> ec55aa38 (vmov sl, r5, s17, s18|fmrrs sl, r5, {s17, s18}) diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp2.s b/binutils-2.25/gas/testsuite/gas/arm/vfp2.s new file mode 100644 index 00000000..8a293abb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp2.s @@ -0,0 +1,18 @@ +@ VFP2 Additional instructions + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise + @ the full register bitpatterns + + fmdrr d0, r5, r10 + fmrrd r5, r10, d0 + fmsrr {s15, s16}, r5, r10 + fmrrs r5, r10, {s15, s16} + + fmdrr d15, r10, r5 + fmrrd r10, r5, d15 + fmsrr {s17, s18}, r10, r5 + fmrrs r10, r5, {s17, s18} + diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp2_t2.d b/binutils-2.25/gas/testsuite/gas/arm/vfp2_t2.d new file mode 100644 index 00000000..50483b09 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp2_t2.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Thumb-2 VFP Additional instructions +#as: -mfpu=vfp + +# Test the ARM VFP Double Precision instructions + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> ec4a 5b10 vmov d0, r5, sl +0+004 <[^>]*> ec5a 5b10 vmov r5, sl, d0 +0+008 <[^>]*> ec4a 5a37 (vmov s15, s16, r5, sl|fmsrr {s15, s16}, r5, sl) +0+00c <[^>]*> ec5a 5a37 (vmov r5, sl, s15, s16|fmrrs r5, sl, {s15, s16}) +0+010 <[^>]*> ec45 ab1f vmov d15, sl, r5 +0+014 <[^>]*> ec55 ab1f vmov sl, r5, d15 +0+018 <[^>]*> ec45 aa38 (vmov s17, s18, sl, r5|fmsrr {s17, s18}, sl, r5) +0+01c <[^>]*> ec55 aa38 (vmov sl, r5, s17, s18|fmrrs sl, r5, {s17, s18}) diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfp2_t2.s b/binutils-2.25/gas/testsuite/gas/arm/vfp2_t2.s new file mode 100644 index 00000000..ba5551b6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfp2_t2.s @@ -0,0 +1,21 @@ +@ VFP2 Additional instructions +@ Same as vfp2.s, but for Thumb-2 + .syntax unified + .thumb + .text + .global F +F: + @ First we test the basic syntax and bit patterns of the opcodes. + @ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise + @ the full register bitpatterns + + fmdrr d0, r5, r10 + fmrrd r5, r10, d0 + fmsrr {s15, s16}, r5, r10 + fmrrs r5, r10, {s15, s16} + + fmdrr d15, r10, r5 + fmrrd r10, r5, d15 + fmsrr {s17, s18}, r10, r5 + fmrrs r10, r5, {s17, s18} + diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3-32drs.d b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-32drs.d new file mode 100644 index 00000000..1f67f029 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-32drs.d @@ -0,0 +1,73 @@ +# name: VFPv3 extra D registers +# as: -mfpu=vfp3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eeb03b66 (vmov\.f64|fcpyd) d3, d22 +0[0-9a-f]+ <[^>]+> eef06b43 (vmov\.f64|fcpyd) d22, d3 +0[0-9a-f]+ <[^>]+> eef76acb (vcvt\.f64\.f32|fcvtds) d22, s22 +0[0-9a-f]+ <[^>]+> eeb7bbe6 (vcvt\.f32\.f64|fcvtsd) s22, d22 +0[0-9a-f]+ <[^>]+> ee254b90 vmov\.32 d21\[1\], r4 +0[0-9a-f]+ <[^>]+> ee0b5b90 vmov\.32 d27\[0\], r5 +0[0-9a-f]+ <[^>]+> ee376b90 vmov\.32 r6, d23\[1\] +0[0-9a-f]+ <[^>]+> ee197b90 vmov\.32 r7, d25\[0\] +0[0-9a-f]+ <[^>]+> eef86bcb (vcvt\.f64\.s32|fsitod) d22, s22 +0[0-9a-f]+ <[^>]+> eef85b6a (vcvt\.f64\.u32|fuitod) d21, s21 +0[0-9a-f]+ <[^>]+> eebdab64 (vcvtr\.s32\.f64|ftosid) s20, d20 +0[0-9a-f]+ <[^>]+> eebdabe4 (vcvt\.s32\.f64|ftosizd) s20, d20 +0[0-9a-f]+ <[^>]+> eefc9b63 (vcvtr\.u32\.f64|ftouid) s19, d19 +0[0-9a-f]+ <[^>]+> eefc9be3 (vcvt\.u32\.f64|ftouizd) s19, d19 +0[0-9a-f]+ <[^>]+> edda3b01 vldr d19, \[sl, #4\] +0[0-9a-f]+ <[^>]+> edca5b01 vstr d21, \[sl, #4\] +0[0-9a-f]+ <[^>]+> ecba5b04 vldmia sl!, {d5-d6} +0[0-9a-f]+ <[^>]+> ecfa2b06 vldmia sl!, {d18-d20} +0[0-9a-f]+ <[^>]+> ecba5b05 fldmiax sl!, {d5-d6}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ecfa2b07 fldmiax sl!, {d18-d20}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ed7a2b05 fldmdbx sl!, {d18-d19}( ;@ Deprecated|) +0[0-9a-f]+ <[^>]+> ecc94b0a vstmia r9, {d20-d24} +0[0-9a-f]+ <[^>]+> eeb03bc5 (vabs\.f64|fabsd) d3, d5 +0[0-9a-f]+ <[^>]+> eeb0cbe2 (vabs\.f64|fabsd) d12, d18 +0[0-9a-f]+ <[^>]+> eef02be3 (vabs\.f64|fabsd) d18, d19 +0[0-9a-f]+ <[^>]+> eeb13b45 (vneg\.f64|fnegd) d3, d5 +0[0-9a-f]+ <[^>]+> eeb1cb62 (vneg\.f64|fnegd) d12, d18 +0[0-9a-f]+ <[^>]+> eef12b63 (vneg\.f64|fnegd) d18, d19 +0[0-9a-f]+ <[^>]+> eeb13bc5 (vsqrt\.f64|fsqrtd) d3, d5 +0[0-9a-f]+ <[^>]+> eeb1cbe2 (vsqrt\.f64|fsqrtd) d12, d18 +0[0-9a-f]+ <[^>]+> eef12be3 (vsqrt\.f64|fsqrtd) d18, d19 +0[0-9a-f]+ <[^>]+> ee353b06 (vadd\.f64|faddd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee32cb84 (vadd\.f64|faddd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee732ba4 (vadd\.f64|faddd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee353b46 (vsub\.f64|fsubd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee32cbc4 (vsub\.f64|fsubd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee732be4 (vsub\.f64|fsubd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee253b06 (vmul\.f64|fmuld) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee22cb84 (vmul\.f64|fmuld) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee632ba4 (vmul\.f64|fmuld) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee853b06 (vdiv\.f64|fdivd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee82cb84 (vdiv\.f64|fdivd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> eec32ba4 (vdiv\.f64|fdivd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee053b06 (vmla\.f64|fmacd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee02cb84 (vmla\.f64|fmacd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee432ba4 (vmla\.f64|fmacd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee153b06 (vnmls\.f64|fmscd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee12cb84 (vnmls\.f64|fmscd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee532ba4 (vnmls\.f64|fmscd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee253b46 (vnmul\.f64|fnmuld) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee22cbc4 (vnmul\.f64|fnmuld) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee632be4 (vnmul\.f64|fnmuld) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee053b46 (vmls\.f64|fnmacd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee02cbc4 (vmls\.f64|fnmacd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee432be4 (vmls\.f64|fnmacd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> ee153b46 (vnmla\.f64|fnmscd) d3, d5, d6 +0[0-9a-f]+ <[^>]+> ee12cbc4 (vnmla\.f64|fnmscd) d12, d18, d4 +0[0-9a-f]+ <[^>]+> ee532be4 (vnmla\.f64|fnmscd) d18, d19, d20 +0[0-9a-f]+ <[^>]+> eeb43b62 (vcmp\.f64|fcmpd) d3, d18 +0[0-9a-f]+ <[^>]+> eef42b43 (vcmp\.f64|fcmpd) d18, d3 +0[0-9a-f]+ <[^>]+> eef53b40 (vcmp\.f64 d19, #0.0|fcmpzd d19) +0[0-9a-f]+ <[^>]+> eeb43be2 (vcmpe\.f64|fcmped) d3, d18 +0[0-9a-f]+ <[^>]+> eef42bc3 (vcmpe\.f64|fcmped) d18, d3 +0[0-9a-f]+ <[^>]+> eef53bc0 (vcmpe\.f64 d19, #0.0|fcmpezd d19) +0[0-9a-f]+ <[^>]+> ec443b3f vmov d31, r3, r4 +0[0-9a-f]+ <[^>]+> ec565b3e vmov r5, r6, d30 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3-32drs.s b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-32drs.s new file mode 100644 index 00000000..ef72c24e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-32drs.s @@ -0,0 +1,68 @@ +.arm +.syntax unified + fcpyd d3,d22 + fcpyd d22,d3 + fcvtds d22,s22 + fcvtsd s22,d22 + fmdhr d21,r4 + fmdlr d27,r5 + fmrdh r6,d23 + fmrdl r7,d25 + fsitod d22,s22 + fuitod d21,s21 + ftosid s20,d20 + ftosizd s20,d20 + ftouid s19,d19 + ftouizd s19,d19 + fldd d19,[r10,#4] + fstd d21,[r10,#4] + fldmiad r10!,{d5,d6} + fldmiad r10!,{d18,d19,d20} + fldmiax r10!,{d5,d6} + fldmiax r10!,{d18,d19,d20} + fldmdbx r10!,{d18,d19} + fstmiad r9,{d20,d21,d22,d23,d24} + fabsd d3,d5 + fabsd d12,d18 + fabsd d18,d19 + fnegd d3,d5 + fnegd d12,d18 + fnegd d18,d19 + fsqrtd d3,d5 + fsqrtd d12,d18 + fsqrtd d18,d19 + faddd d3,d5,d6 + faddd d12,d18,d4 + faddd d18,d19,d20 + fsubd d3,d5,d6 + fsubd d12,d18,d4 + fsubd d18,d19,d20 + fmuld d3,d5,d6 + fmuld d12,d18,d4 + fmuld d18,d19,d20 + fdivd d3,d5,d6 + fdivd d12,d18,d4 + fdivd d18,d19,d20 + fmacd d3,d5,d6 + fmacd d12,d18,d4 + fmacd d18,d19,d20 + fmscd d3,d5,d6 + fmscd d12,d18,d4 + fmscd d18,d19,d20 + fnmuld d3,d5,d6 + fnmuld d12,d18,d4 + fnmuld d18,d19,d20 + fnmacd d3,d5,d6 + fnmacd d12,d18,d4 + fnmacd d18,d19,d20 + fnmscd d3,d5,d6 + fnmscd d12,d18,d4 + fnmscd d18,d19,d20 + fcmpd d3,d18 + fcmpd d18,d3 + fcmpzd d19 + fcmped d3,d18 + fcmped d18,d3 + fcmpezd d19 + fmdrr d31,r3,r4 + fmrrd r5,r6,d30 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3-const-conv.d b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-const-conv.d new file mode 100644 index 00000000..d8d244dc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-const-conv.d @@ -0,0 +1,29 @@ +# name: VFPv3 additional constant and conversion ops +# as: -mfpu=vfp3 +# objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section \.text: +0[0-9a-f]+ <[^>]+> eef08a04 (vmov\.f32|fconsts) s17, #4 +0[0-9a-f]+ <[^>]+> eeba9a05 (vmov\.f32|fconsts) s18, #165.* +0[0-9a-f]+ <[^>]+> eef49a00 (vmov\.f32|fconsts) s19, #64.* +0[0-9a-f]+ <[^>]+> eef01b04 (vmov\.f64|fconstd) d17, #4 +0[0-9a-f]+ <[^>]+> eefa2b05 (vmov\.f64|fconstd) d18, #165.* +0[0-9a-f]+ <[^>]+> eef43b00 (vmov\.f64|fconstd) d19, #64.* +0[0-9a-f]+ <[^>]+> eefa8a63 (vcvt\.f32\.s16 s17, s17, #9|fshtos s17, #9) +0[0-9a-f]+ <[^>]+> eefa1b63 (vcvt\.f64\.s16 d17, d17, #9|fshtod d17, #9) +0[0-9a-f]+ <[^>]+> eefa8aeb (vcvt\.f32\.s32 s17, s17, #9|fsltos s17, #9) +0[0-9a-f]+ <[^>]+> eefa1beb (vcvt\.f64\.s32 d17, d17, #9|fsltod d17, #9) +0[0-9a-f]+ <[^>]+> eefb8a63 (vcvt\.f32\.u16 s17, s17, #9|fuhtos s17, #9) +0[0-9a-f]+ <[^>]+> eefb1b63 (vcvt\.f64\.u16 d17, d17, #9|fuhtod d17, #9) +0[0-9a-f]+ <[^>]+> eefb8aeb (vcvt\.f32\.u32 s17, s17, #9|fultos s17, #9) +0[0-9a-f]+ <[^>]+> eefb1beb (vcvt\.f64\.u32 d17, d17, #9|fultod d17, #9) +0[0-9a-f]+ <[^>]+> eefe9a64 (vcvt\.s16\.f32 s19, s19, #7|ftoshs s19, #7) +0[0-9a-f]+ <[^>]+> eefe3b64 (vcvt\.s16\.f64 d19, d19, #7|ftoshd d19, #7) +0[0-9a-f]+ <[^>]+> eefe9aec (vcvt\.s32\.f32 s19, s19, #7|ftosls s19, #7) +0[0-9a-f]+ <[^>]+> eefe3bec (vcvt\.s32\.f64 d19, d19, #7|ftosld d19, #7) +0[0-9a-f]+ <[^>]+> eeff9a64 (vcvt\.u16\.f32 s19, s19, #7|ftouhs s19, #7) +0[0-9a-f]+ <[^>]+> eeff3b64 (vcvt\.u16\.f64 d19, d19, #7|ftouhd d19, #7) +0[0-9a-f]+ <[^>]+> eeff9aec (vcvt\.u32\.f32 s19, s19, #7|ftouls s19, #7) +0[0-9a-f]+ <[^>]+> eeff3bec (vcvt\.u32\.f64 d19, d19, #7|ftould d19, #7) diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3-const-conv.s b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-const-conv.s new file mode 100644 index 00000000..d726d14b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-const-conv.s @@ -0,0 +1,25 @@ +.arm +.syntax unified + fconsts s17, #4 + fconsts s18, #0xa5 + fconsts s19, #0x40 + fconstd d17, #4 + fconstd d18, #0xa5 + fconstd d19, #0x40 + fshtos s17, 9 + fshtod d17, 9 + fsltos s17, 9 + fsltod d17, 9 + fuhtos s17, 9 + fuhtod d17, 9 + fultos s17, 9 + fultod d17, 9 + + ftoshs s19, 7 + ftoshd d19, 7 + ftosls s19, 7 + ftosld d19, 7 + ftouhs s19, 7 + ftouhd d19, 7 + ftouls s19, 7 + ftould d19, 7 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3-d16-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-d16-bad.d new file mode 100644 index 00000000..0e26c7c3 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-d16-bad.d @@ -0,0 +1,4 @@ +# name: VFPv3-D16 +# as: -mfpu=vfpv3-d16 +# error-output: vfpv3-d16-bad.l +# source: vfpv3-32drs.s diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3-d16-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-d16-bad.l new file mode 100644 index 00000000..1871d204 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3-d16-bad.l @@ -0,0 +1,53 @@ +[^:]*: Assembler messages: +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcpyd d3,d22' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcpyd d22,d3' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcvtds d22,s22' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcvtsd s22,d22' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmdhr d21,r4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmdlr d27,r5' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmrdh r6,d23' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmrdl r7,d25' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsitod d22,s22' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fuitod d21,s21' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftosid s20,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftosizd s20,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftouid s19,d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `ftouizd s19,d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fldd d19,\[r10,#4\]' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fstd d21,\[r10,#4\]' +[^:]*:[0-9]+: Error: register out of range in list -- `fldmiad r10!,\{d18,d19,d20\}' +[^:]*:[0-9]+: Error: register out of range in list -- `fldmiax r10!,\{d18,d19,d20\}' +[^:]*:[0-9]+: Error: register out of range in list -- `fldmdbx r10!,\{d18,d19\}' +[^:]*:[0-9]+: Error: register out of range in list -- `fstmiad r9,\{d20,d21,d22,d23,d24\}' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fabsd d12,d18' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fabsd d18,d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnegd d12,d18' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnegd d18,d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsqrtd d12,d18' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsqrtd d18,d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `faddd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `faddd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsubd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fsubd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmuld d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmuld d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fdivd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fdivd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmacd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmacd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmscd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmscd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmuld d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmuld d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmacd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmacd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmscd d12,d18,d4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fnmscd d18,d19,d20' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpd d3,d18' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpd d18,d3' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpzd d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmped d3,d18' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmped d18,d3' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fcmpezd d19' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmdrr d31,r3,r4' +[^:]*:[0-9]+: Error: D register out of range for selected VFP version -- `fmrrd r5,r6,d30' diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3xd.d b/binutils-2.25/gas/testsuite/gas/arm/vfpv3xd.d new file mode 100644 index 00000000..508f70f7 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3xd.d @@ -0,0 +1,23 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: VFP Double-precision load/store +#as: -mfpu=vfpv3xd + +# Test the ARM VFP Double Precision load/store on single precision FPU + +.*: +file format .*arm.* + +Disassembly of section .text: +0+[0-9a-f]* <[^>]*> ed900b00 vldr d0, \[r0\] +0+[0-9a-f]* <[^>]*> ed800b00 vstr d0, \[r0\] +0+[0-9a-f]* <[^>]*> ec900b02 vldmia r0, {d0} +0+[0-9a-f]* <[^>]*> ec900b02 vldmia r0, {d0} +0+[0-9a-f]* <[^>]*> ecb00b02 vldmia r0!, {d0} +0+[0-9a-f]* <[^>]*> ecb00b02 vldmia r0!, {d0} +0+[0-9a-f]* <[^>]*> ed300b02 vldmdb r0!, {d0} +0+[0-9a-f]* <[^>]*> ed300b02 vldmdb r0!, {d0} +0+[0-9a-f]* <[^>]*> ec800b02 vstmia r0, {d0} +0+[0-9a-f]* <[^>]*> ec800b02 vstmia r0, {d0} +0+[0-9a-f]* <[^>]*> eca00b02 vstmia r0!, {d0} +0+[0-9a-f]* <[^>]*> eca00b02 vstmia r0!, {d0} +0+[0-9a-f]* <[^>]*> ed200b02 vstmdb r0!, {d0} +0+[0-9a-f]* <[^>]*> ed200b02 vstmdb r0!, {d0} diff --git a/binutils-2.25/gas/testsuite/gas/arm/vfpv3xd.s b/binutils-2.25/gas/testsuite/gas/arm/vfpv3xd.s new file mode 100644 index 00000000..a16b969f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vfpv3xd.s @@ -0,0 +1,19 @@ +# Check double precision load/store are allowed on single precision +# implementation + + fldd d0, [r0] + fstd d0, [r0] + + fldmiad r0, {d0} + fldmfdd r0, {d0} + fldmiad r0!, {d0} + fldmfdd r0!, {d0} + fldmdbd r0!, {d0} + fldmead r0!, {d0} + + fstmiad r0, {d0} + fstmead r0, {d0} + fstmiad r0!, {d0} + fstmead r0!, {d0} + fstmdbd r0!, {d0} + fstmfdd r0!, {d0} diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldm-arm.d b/binutils-2.25/gas/testsuite/gas/arm/vldm-arm.d new file mode 100644 index 00000000..37fcb633 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldm-arm.d @@ -0,0 +1,24 @@ +# name: VFP VLDM and VSTM, ARM mode +# as: -mfpu=vfp3 +# source: vldm.s +# objdump: -dr --prefix-addresses --show-raw-insn +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> ec9f0b04 vldmia pc, {d0-d1} +0[0-9a-f]+ <[^>]+> ea000003 b 00000018 <bar> +0[0-9a-f]+ <[^>]+> 00000000 .word 0x00000000 +0[0-9a-f]+ <[^>]+> 3ff00000 .word 0x3ff00000 +0[0-9a-f]+ <[^>]+> 9999999a .word 0x9999999a +0[0-9a-f]+ <[^>]+> 3ff19999 .word 0x3ff19999 +0[0-9a-f]+ <[^>]+> ec8f0b04 vstmia pc, {d0-d1} +0[0-9a-f]+ <[^>]+> ea000003 b 00000030 <foo2> +0[0-9a-f]+ <[^>]+> 00000000 .word 0x00000000 +0[0-9a-f]+ <[^>]+> 3ff00000 .word 0x3ff00000 +0[0-9a-f]+ <[^>]+> 9999999a .word 0x9999999a +0[0-9a-f]+ <[^>]+> 3ff19999 .word 0x3ff19999 +0[0-9a-f]+ <[^>]+> e1a00000 nop.* +0[0-9a-f]+ <[^>]+> e1a00000 nop.* diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldm-thumb-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vldm-thumb-bad.d new file mode 100644 index 00000000..2e2b8c36 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldm-thumb-bad.d @@ -0,0 +1,4 @@ +# name: VFP VLDM and VSTM, Thumb mode +# as: -mfpu=vfp3 -mthumb +# source: vldm.s +# error-output: vldm-thumb-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldm-thumb-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vldm-thumb-bad.l new file mode 100644 index 00000000..9ef9c842 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldm-thumb-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: r15 not allowed here -- `vldmia pc,{d0-d1}' +[^:]*:9: Error: r15 not allowed here -- `vstmia pc,{d0-d1}' diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldm.s b/binutils-2.25/gas/testsuite/gas/arm/vldm.s new file mode 100644 index 00000000..1f92ea27 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldm.s @@ -0,0 +1,16 @@ + .syntax unified + +foo: + vldmia pc, {d0-d1} + b bar +baz: + .word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999 +bar: + vstmia pc, {d0-d1} + b foo2 +baz2: + .word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999 +foo2: + nop + nop + diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldmw-arm-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vldmw-arm-bad.d new file mode 100644 index 00000000..1cbcf454 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldmw-arm-bad.d @@ -0,0 +1,4 @@ +# name: VFP VLDM and VSTM with writeback, ARM mode +# as: -mfpu=vfp3 +# source: vldmw-bad.s +# error-output: vldmw-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldmw-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vldmw-bad.l new file mode 100644 index 00000000..ba0f66f6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldmw-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:4: Error: r15 not allowed here -- `vldmia pc!,{d0-d1}' +[^:]*:9: Error: r15 not allowed here -- `vstmia pc!,{d0-d1}' diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldmw-bad.s b/binutils-2.25/gas/testsuite/gas/arm/vldmw-bad.s new file mode 100644 index 00000000..63fddbfd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldmw-bad.s @@ -0,0 +1,16 @@ + .syntax unified + +foo: + vldmia pc!, {d0-d1} + b bar +baz: + .word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999 +bar: + vstmia pc!, {d0-d1} + b foo2 +baz2: + .word 0x00000000, 0x3ff00000, 0x9999999a, 0x3ff19999 +foo2: + nop + nop + diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldmw-thumb-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vldmw-thumb-bad.d new file mode 100644 index 00000000..aca12092 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldmw-thumb-bad.d @@ -0,0 +1,4 @@ +# name: VFP VLDM and VSTM with writeback, Thumb mode +# as: -mfpu=vfp3 -mthumb +# source: vldmw-bad.s +# error-output: vldmw-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldr.d b/binutils-2.25/gas/testsuite/gas/arm/vldr.d new file mode 100644 index 00000000..fbb15602 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldr.d @@ -0,0 +1,16 @@ +# name: VFP VLDR +# as: -mfpu=vfp3 -mcpu=cortex-a8 -mthumb +# source: vldr.s +# objdump: -dr --prefix-addresses --show-raw-insn +# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> ed9f 0b03 vldr d0, \[pc, #12\] ; 00000010 <float> +0[0-9a-f]+ <[^>]+> ed9f 0b02 vldr d0, \[pc, #8\] ; 00000010 <float> +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nop +0[0-9a-f]+ <[^>]+> bf00 nop + ... diff --git a/binutils-2.25/gas/testsuite/gas/arm/vldr.s b/binutils-2.25/gas/testsuite/gas/arm/vldr.s new file mode 100644 index 00000000..86bc82eb --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vldr.s @@ -0,0 +1,10 @@ +.syntax unified +.text + nop + vldr d0, float + vldr d0, float + nop + nop + +.align +float: .double 0.0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vstr-arm-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vstr-arm-bad.d new file mode 100644 index 00000000..32a041f6 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vstr-arm-bad.d @@ -0,0 +1,4 @@ +# name: VFP PC-relative VSTR arm mode +# as: -mfpu=vfp3 -mcpu=cortex-a8 +# source: vstr-bad.s +# error-output: vstr-arm-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vstr-arm-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vstr-arm-bad.l new file mode 100644 index 00000000..0d483278 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vstr-arm-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:6: Warning: Use of PC here is deprecated +[^:]*:7: Warning: Use of PC here is deprecated diff --git a/binutils-2.25/gas/testsuite/gas/arm/vstr-bad.s b/binutils-2.25/gas/testsuite/gas/arm/vstr-bad.s new file mode 100644 index 00000000..f5a13654 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vstr-bad.s @@ -0,0 +1,12 @@ + +.syntax unified +.text + + nop + vstr d0, float + vstr d0, [pc, #4] + nop + nop + +.align +float: .double 0.0 diff --git a/binutils-2.25/gas/testsuite/gas/arm/vstr-thumb-bad.d b/binutils-2.25/gas/testsuite/gas/arm/vstr-thumb-bad.d new file mode 100644 index 00000000..354689f4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vstr-thumb-bad.d @@ -0,0 +1,4 @@ +# name: VFP PC-relative VSTR thumb mode +# as: -mfpu=vfp -mthumb -mcpu=arm1156t2f-s +# source: vstr-bad.s +# error-output: vstr-thumb-bad.l diff --git a/binutils-2.25/gas/testsuite/gas/arm/vstr-thumb-bad.l b/binutils-2.25/gas/testsuite/gas/arm/vstr-thumb-bad.l new file mode 100644 index 00000000..1660fbfd --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/vstr-thumb-bad.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: Use of PC here is UNPREDICTABLE -- `vstr d0,float' +[^:]*:7: Error: Use of PC here is UNPREDICTABLE -- `vstr d0,\[pc,#4\]' diff --git a/binutils-2.25/gas/testsuite/gas/arm/weakdef-1.d b/binutils-2.25/gas/testsuite/gas/arm/weakdef-1.d new file mode 100644 index 00000000..3ba6f9a4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/weakdef-1.d @@ -0,0 +1,20 @@ +# name: Thumb branch to weak +# as: +# objdump: -dr +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format .*arm.* + + +Disassembly of section .text: + +0+000 <Weak>: + 0: f7ff bffe b.w 4 <Strong> + 0: R_ARM_THM_JUMP24 Strong + +0+004 <Strong>: + 4: f7ff bffe b.w 0 <Random> + 4: R_ARM_THM_JUMP24 Random + 8: f7ff bffe b.w 0 <Weak> + 8: R_ARM_THM_JUMP24 Weak diff --git a/binutils-2.25/gas/testsuite/gas/arm/weakdef-1.s b/binutils-2.25/gas/testsuite/gas/arm/weakdef-1.s new file mode 100644 index 00000000..4aa6bc46 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/weakdef-1.s @@ -0,0 +1,18 @@ + .syntax unified + .text + .thumb + + .globl Weak + .weak Weak + .thumb_func + .type Weak, %function +Weak: + b Strong + .size Weak, .-Weak + + .globl Strong + .type Strong, %function +Strong: + b Random + b Weak + .size Strong, .-Strong diff --git a/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.d b/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.d new file mode 100644 index 00000000..e0ff272a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.d @@ -0,0 +1,5 @@ +# name: adr of weak +# as: +# error-output: weakdef-2.l +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* diff --git a/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.l b/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.l new file mode 100644 index 00000000..7aec5e1f --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:9: Error: symbol Weak is weak and may be overridden later +[^:]*:10: Error: symbol Weak is weak and may be overridden later diff --git a/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.s b/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.s new file mode 100644 index 00000000..08da1961 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/weakdef-2.s @@ -0,0 +1,10 @@ + .syntax unified + .text + .globl Strong +Strong: + adrl r0,Strong + adr r0,Strong + .globl Weak + .weak Weak +Weak: adrl r0,Weak + adr r0,Weak diff --git a/binutils-2.25/gas/testsuite/gas/arm/wince.d b/binutils-2.25/gas/testsuite/gas/arm/wince.d new file mode 100644 index 00000000..3d116bcc --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/wince.d @@ -0,0 +1,30 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM WinCE basic tests +#as: -mcpu=arm7m -EL +#source: wince.s +#not-skip: *-wince-* + +# Some WinCE specific tests. + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <global_data> 00000007 andeq r0, r0, r7 + 0: ARM_32 global_data +0+004 <global_sym> e1a00000 nop ; \(mov r0, r0\) +0+008 <global_sym\+0x4> e1a00000 nop ; \(mov r0, r0\) +0+00c <global_sym\+0x8> e1a00000 nop ; \(mov r0, r0\) +0+010 <global_sym\+0xc> eafffffb b f+ff8 <global_sym\+0xf+ff4> + 10: ARM_26D global_sym-0x4 +0+014 <global_sym\+0x10> ebfffffa bl f+ff4 <global_sym\+0xf+ff0> + 14: ARM_26D global_sym-0x4 +0+018 <global_sym\+0x14> 0afffff9 beq f+ff0 <global_sym\+0xf+fec> + 18: ARM_26D global_sym-0x4 +0+01c <global_sym\+0x18> eafffff8 b 0+004 <global_sym> +0+020 <global_sym\+0x1c> ebfffff7 bl 0+004 <global_sym> +0+024 <global_sym\+0x20> 0afffff6 beq 0+004 <global_sym> +0+028 <global_sym\+0x24> eafffff5 b 0+004 <global_sym> +0+02c <global_sym\+0x28> ebfffff4 bl 0+004 <global_sym> +0+030 <global_sym\+0x2c> e51f0034 ldr r0, \[pc, #-52\] ; 0+004 <global_sym> +0+034 <global_sym\+0x30> e51f0038 ldr r0, \[pc, #-56\] ; 0+004 <global_sym> +0+038 <global_sym\+0x34> e51f003c ldr r0, \[pc, #-60\] ; 0+004 <global_sym> diff --git a/binutils-2.25/gas/testsuite/gas/arm/wince.s b/binutils-2.25/gas/testsuite/gas/arm/wince.s new file mode 100644 index 00000000..e8b76a04 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/wince.s @@ -0,0 +1,25 @@ + .global global_data + .text + .global global_sym + .def global_sym; .scl 2; .type 32; .endef + +global_data: + .word global_data+7 + +global_sym: +def_sym: +undef_sym: + nop + nop + nop + b global_sym + bl global_sym + beq global_sym + b def_sym + bl def_sym + beq def_sym + b undef_sym + bl undef_sym + ldr r0, global_sym + ldr r0, def_sym + ldr r0, undef_sym diff --git a/binutils-2.25/gas/testsuite/gas/arm/wince_inst.d b/binutils-2.25/gas/testsuite/gas/arm/wince_inst.d new file mode 100644 index 00000000..5b489669 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/wince_inst.d @@ -0,0 +1,205 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: ARM basic instructions (WinCE version) +#as: -mcpu=arm7m -EL +#source: inst.s +# inst.d is used for non-WinCE targets. +#not-skip: *-wince-* + +# This file is the same as inst.d except that the BL +# instructions have not had a -8 bias inserted. + +.*: +file format .*arm.* + +Disassembly of section .text: +0+000 <[^>]*> e3a00000 ? mov r0, #0 +0+004 <[^>]*> e1a01002 ? mov r1, r2 +0+008 <[^>]*> e1a03184 ? lsl r3, r4, #3 +0+00c <[^>]*> e1a05736 ? lsr r5, r6, r7 +0+010 <[^>]*> e1a08a59 ? asr r8, r9, sl +0+014 <[^>]*> e1a0bd1c ? lsl fp, ip, sp +0+018 <[^>]*> e1a0e06f ? rrx lr, pc +0+01c <[^>]*> e1a01002 ? mov r1, r2 +0+020 <[^>]*> 01a02003 ? moveq r2, r3 +0+024 <[^>]*> 11a04005 ? movne r4, r5 +0+028 <[^>]*> b1a06007 ? movlt r6, r7 +0+02c <[^>]*> a1a08009 ? movge r8, r9 +0+030 <[^>]*> d1a0a00b ? movle sl, fp +0+034 <[^>]*> c1a0c00d ? movgt ip, sp +0+038 <[^>]*> 31a01002 ? movcc r1, r2 +0+03c <[^>]*> 21a01003 ? movcs r1, r3 +0+040 <[^>]*> 41a03006 ? movmi r3, r6 +0+044 <[^>]*> 51a07009 ? movpl r7, r9 +0+048 <[^>]*> 61a01008 ? movvs r1, r8 +0+04c <[^>]*> 71a09fa1 ? lsrvc r9, r1, #31 +0+050 <[^>]*> 81a0800f ? movhi r8, pc +0+054 <[^>]*> 91a0f00e ? movls pc, lr +0+058 <[^>]*> 21a09008 ? movcs r9, r8 +0+05c <[^>]*> 31a01003 ? movcc r1, r3 +0+060 <[^>]*> e1b00008 ? movs r0, r8 +0+064 <[^>]*> 31b00007 ? movscc r0, r7 +0+068 <[^>]*> e281000a ? add r0, r1, #10 +0+06c <[^>]*> e0832004 ? add r2, r3, r4 +0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 +0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1 +0+078 <[^>]*> e201000a ? and r0, r1, #10 +0+07c <[^>]*> e0032004 ? and r2, r3, r4 +0+080 <[^>]*> e0065287 ? and r5, r6, r7, lsl #5 +0+084 <[^>]*> e0021113 ? and r1, r2, r3, lsl r1 +0+088 <[^>]*> e221000a ? eor r0, r1, #10 +0+08c <[^>]*> e0232004 ? eor r2, r3, r4 +0+090 <[^>]*> e0265287 ? eor r5, r6, r7, lsl #5 +0+094 <[^>]*> e0221113 ? eor r1, r2, r3, lsl r1 +0+098 <[^>]*> e241000a ? sub r0, r1, #10 +0+09c <[^>]*> e0432004 ? sub r2, r3, r4 +0+0a0 <[^>]*> e0465287 ? sub r5, r6, r7, lsl #5 +0+0a4 <[^>]*> e0421113 ? sub r1, r2, r3, lsl r1 +0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 +0+0ac <[^>]*> e0a32004 ? adc r2, r3, r4 +0+0b0 <[^>]*> e0a65287 ? adc r5, r6, r7, lsl #5 +0+0b4 <[^>]*> e0a21113 ? adc r1, r2, r3, lsl r1 +0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 +0+0bc <[^>]*> e0c32004 ? sbc r2, r3, r4 +0+0c0 <[^>]*> e0c65287 ? sbc r5, r6, r7, lsl #5 +0+0c4 <[^>]*> e0c21113 ? sbc r1, r2, r3, lsl r1 +0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 +0+0cc <[^>]*> e0632004 ? rsb r2, r3, r4 +0+0d0 <[^>]*> e0665287 ? rsb r5, r6, r7, lsl #5 +0+0d4 <[^>]*> e0621113 ? rsb r1, r2, r3, lsl r1 +0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 +0+0dc <[^>]*> e0e32004 ? rsc r2, r3, r4 +0+0e0 <[^>]*> e0e65287 ? rsc r5, r6, r7, lsl #5 +0+0e4 <[^>]*> e0e21113 ? rsc r1, r2, r3, lsl r1 +0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 +0+0ec <[^>]*> e1832004 ? orr r2, r3, r4 +0+0f0 <[^>]*> e1865287 ? orr r5, r6, r7, lsl #5 +0+0f4 <[^>]*> e1821113 ? orr r1, r2, r3, lsl r1 +0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 +0+0fc <[^>]*> e1c32004 ? bic r2, r3, r4 +0+100 <[^>]*> e1c65287 ? bic r5, r6, r7, lsl #5 +0+104 <[^>]*> e1c21113 ? bic r1, r2, r3, lsl r1 +0+108 <[^>]*> e3e0000a ? mvn r0, #10 +0+10c <[^>]*> e1e02004 ? mvn r2, r4 +0+110 <[^>]*> e1e05287 ? mvn r5, r7, lsl #5 +0+114 <[^>]*> e1e01113 ? mvn r1, r3, lsl r1 +0+118 <[^>]*> e310000a ? tst r0, #10 +0+11c <[^>]*> e1120004 ? tst r2, r4 +0+120 <[^>]*> e1150287 ? tst r5, r7, lsl #5 +0+124 <[^>]*> e1110113 ? tst r1, r3, lsl r1 +0+128 <[^>]*> e330000a ? teq r0, #10 +0+12c <[^>]*> e1320004 ? teq r2, r4 +0+130 <[^>]*> e1350287 ? teq r5, r7, lsl #5 +0+134 <[^>]*> e1310113 ? teq r1, r3, lsl r1 +0+138 <[^>]*> e350000a ? cmp r0, #10 +0+13c <[^>]*> e1520004 ? cmp r2, r4 +0+140 <[^>]*> e1550287 ? cmp r5, r7, lsl #5 +0+144 <[^>]*> e1510113 ? cmp r1, r3, lsl r1 +0+148 <[^>]*> e370000a ? cmn r0, #10 +0+14c <[^>]*> e1720004 ? cmn r2, r4 +0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 +0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 +0+158 <[^>]*> e330f00a ? teq r0, #10 +0+15c <[^>]*> e132f004 ? teq r2, r4 +0+160 <[^>]*> e135f287 ? teq r5, r7, lsl #5 +0+164 <[^>]*> e131f113 ? teq r1, r3, lsl r1 +0+168 <[^>]*> e370f00a ? cmn r0, #10 +0+16c <[^>]*> e172f004 ? cmn r2, r4 +0+170 <[^>]*> e175f287 ? cmn r5, r7, lsl #5 +0+174 <[^>]*> e171f113 ? cmn r1, r3, lsl r1 +0+178 <[^>]*> e350f00a ? cmp r0, #10 +0+17c <[^>]*> e152f004 ? cmp r2, r4 +0+180 <[^>]*> e155f287 ? cmp r5, r7, lsl #5 +0+184 <[^>]*> e151f113 ? cmp r1, r3, lsl r1 +0+188 <[^>]*> e310f00a ? tst r0, #10 +0+18c <[^>]*> e112f004 ? tst r2, r4 +0+190 <[^>]*> e115f287 ? tst r5, r7, lsl #5 +0+194 <[^>]*> e111f113 ? tst r1, r3, lsl r1 +0+198 <[^>]*> e0000291 ? mul r0, r1, r2 +0+19c <[^>]*> e0110392 ? muls r1, r2, r3 +0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 +0+1a4 <[^>]*> 90190798 ? mulsls r9, r8, r7 +0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp +0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip +0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp +0+1b4 <[^>]*> a034e391 ? mlasge r4, r1, r3, lr +0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] +0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] +0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! +0+1c4 <[^>]*> e5922020 ? ldr r2, \[r2, #32\] +0+1c8 <[^>]*> e7932424 ? ldr r2, \[r3, r4, lsr #8\] +0+1cc <[^>]*> 07b54484 ? ldreq r4, \[r5, r4, lsl #9\]! +0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6 +0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3 +0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 +0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> +0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] +0+1e4 <[^>]*> 14f85000 ? ldrbtne r5, \[r8\] +0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] +0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] +0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! +0+1f4 <[^>]*> e5822020 ? str r2, \[r2, #32\] +0+1f8 <[^>]*> e7832424 ? str r2, \[r3, r4, lsr #8\] +0+1fc <[^>]*> 07a54484 ? streq r4, \[r5, r4, lsl #9\]! +0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6 +0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3 +0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8 +0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> +0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] +0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] +0+218 <[^>]*> e8900002 ? ldm r0, {r1} +0+21c <[^>]*> 09920038 ? ldmibeq r2, {r3, r4, r5} +0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ +0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} +0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} +0+22c <[^>]*> e89201f8 ? ldm r2, {r3, r4, r5, r6, r7, r8} +0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} +0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ +0+238 <[^>]*> e8800002 ? stm r0, {r1} +0+23c <[^>]*> 09820038 ? stmibeq r2, {r3, r4, r5} +0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ +0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} +0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} +0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} +0+250 <[^>]*> e8830003 ? stm r3, {r0, r1} +0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ +0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 +0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 +0+260 <[^>]*> eb000000 ? bl 0.* <[^>]*> +[ ]*260:.*_wombat.* +0+264 <[^>]*> 5b000000 ? blpl 0.* <[^>]*> +[ ]*264:.*ARM.*hohum +0+268 <[^>]*> ea000000 ? b 0.* <[^>]*> +[ ]*268:.*_wibble.* +0+26c <[^>]*> da000000 ? ble 0.* <[^>]*> +[ ]*26c:.*testerfunc.* +0+270 <[^>]*> e1a01102 ? lsl r1, r2, #2 +0+274 <[^>]*> e1a01002 ? mov r1, r2 +0+278 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+27c <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+280 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+284 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+288 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+28c <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+290 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+294 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+298 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+29c <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2a0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2a4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2a8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ac <[^>]*> e1a01062 ? rrx r1, r2 +0+2b0 <[^>]*> e1a01102 ? lsl r1, r2, #2 +0+2b4 <[^>]*> e1a01002 ? mov r1, r2 +0+2b8 <[^>]*> e1a01f82 ? lsl r1, r2, #31 +0+2bc <[^>]*> e1a01312 ? lsl r1, r2, r3 +0+2c0 <[^>]*> e1a01122 ? lsr r1, r2, #2 +0+2c4 <[^>]*> e1a01fa2 ? lsr r1, r2, #31 +0+2c8 <[^>]*> e1a01022 ? lsr r1, r2, #32 +0+2cc <[^>]*> e1a01332 ? lsr r1, r2, r3 +0+2d0 <[^>]*> e1a01142 ? asr r1, r2, #2 +0+2d4 <[^>]*> e1a01fc2 ? asr r1, r2, #31 +0+2d8 <[^>]*> e1a01042 ? asr r1, r2, #32 +0+2dc <[^>]*> e1a01352 ? asr r1, r2, r3 +0+2e0 <[^>]*> e1a01162 ? ror r1, r2, #2 +0+2e4 <[^>]*> e1a01fe2 ? ror r1, r2, #31 +0+2e8 <[^>]*> e1a01372 ? ror r1, r2, r3 +0+2ec <[^>]*> e1a01062 ? rrx r1, r2 diff --git a/binutils-2.25/gas/testsuite/gas/arm/xscale.d b/binutils-2.25/gas/testsuite/gas/arm/xscale.d new file mode 100644 index 00000000..da4d1d7b --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/xscale.d @@ -0,0 +1,37 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: XScale instructions +#as: -mcpu=xscale -EL + +# Test the XScale instructions: + +.*: +file format .*arm.* + +Disassembly of section .text: +0+00 <foo> ee201010 mia acc0, r0, r1 +0+04 <[^>]*> be20d01e mialt acc0, lr, sp +0+08 <[^>]*> ee284012 miaph acc0, r2, r4 +0+0c <[^>]*> 1e286015 miaphne acc0, r5, r6 +0+10 <[^>]*> ee2c8017 miaBB acc0, r7, r8 +0+14 <[^>]*> ee2da019 miaBT acc0, r9, sl +0+18 <[^>]*> ee2eb01c miaTB acc0, ip, fp +0+1c <[^>]*> ee2f0010 miaTT acc0, r0, r0 +0+20 <[^>]*> ec411000 mar acc0, r1, r1 +0+24 <[^>]*> cc4c2000 margt acc0, r2, ip +0+28 <[^>]*> ec543000 mra r3, r4, acc0 +0+2c <[^>]*> ec585000 mra r5, r8, acc0 +0+30 <[^>]*> f5d0f000 pld \[r0\] +0+34 <[^>]*> f5d1f789 pld \[r1, #1929\].* +0+38 <[^>]*> f7d2f003 pld \[r2, r3\] +0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] +0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] +0+44 <[^>]*> 01c327d8 ldrdeq r2, \[r3, #120\].* +0+48 <[^>]*> b10540d6 ldrdlt r4, \[r5, -r6\] +0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]!.* +0+50 <[^>]*> e1ac00fd strd r0, \[ip, sp\]! +0+54 <[^>]*> 30ce21f0 strdcc r2, \[lr\], #16 +0+58 <[^>]*> 708640f8 strdvc r4, \[r6\], r8 +0+5c <[^>]*> e5910000 ldr r0, \[r1\] +0+60 <[^>]*> e5832000 str r2, \[r3\] +0+64 <[^>]*> e321f011 msr CPSR_c, #17 +0+68 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) +0+6c <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\) diff --git a/binutils-2.25/gas/testsuite/gas/arm/xscale.s b/binutils-2.25/gas/testsuite/gas/arm/xscale.s new file mode 100644 index 00000000..7b58c344 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/xscale.s @@ -0,0 +1,42 @@ + .text + .global foo +foo: + mia acc0, r0, r1 + mialt acc0, r14, r13 + + miaph acc0, r2, r4 + miaphne acc0, r5, r6 + + miaBB acc0, r7, r8 + miaBT acc0, r9, r10 + miaTB acc0, r12, r11 + miaTT acc0, r0, r0 + + mar acc0, r1, r1 + margt acc0, r2, r12 + + mra r3, r4, acc0 + mra r5, r8, acc0 + + pld [r0] + pld [r1, #0x789] + pld [r2, r3] + pld [r4, -r5, lsl #5] + + ldrd r0, [r1] + ldreqd r2, [r3, #0x78] + ldrltd r4, [r5, -r6] + strd r8, [r10,#-0x89]! + strald r0, [r12, +r13]! + strlod r2, [r14], #+0x010 + strvcd r4, [r6], r8 + + ldr r0, [r1] + str r2, [r3] + + msr cpsr_ctl, #0x11 + + # Add two nop instructions to ensure that the + # output is 32-byte aligned as required for arm-aout. + nop + nop |