diff options
Diffstat (limited to 'binutils-2.25/gas/testsuite/gas/aarch64')
56 files changed, 1600 insertions, 33 deletions
diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/aarch64.exp b/binutils-2.25/gas/testsuite/gas/aarch64/aarch64.exp index 0a11438c..d70174d8 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/aarch64.exp +++ b/binutils-2.25/gas/testsuite/gas/aarch64/aarch64.exp @@ -1,5 +1,4 @@ -# Copyright 2012 -# Free Software Foundation, Inc. +# Copyright (C) 2012-2014 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/addsub.s b/binutils-2.25/gas/testsuite/gas/aarch64/addsub.s index 568bbceb..da91dbac 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/addsub.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/addsub.s @@ -1,6 +1,6 @@ /* addsub.s Test file for AArch64 add-subtract instructions. - Copyright 2012 Free Software Foundation, Inc. + Copyright (C) 2012-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-across.s b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-across.s index b8c7d277..6ce77c34 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-across.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-across.s @@ -1,7 +1,7 @@ /* advsimd-across.s Test file for AArch64 Advanced-SIMD across instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-misc.s b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-misc.s index a9402e49..86a1c0d3 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-misc.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-misc.s @@ -1,7 +1,7 @@ /* advsimd-abs.s Test file for AArch64 Advanced-SIMD Integer absolute instruction. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-mov-bad.d b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-mov-bad.d new file mode 100644 index 00000000..6ca98873 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-mov-bad.d @@ -0,0 +1,12 @@ +#source: advsimd-mov-bad.s +#readelf: -s --wide + +Symbol table '.symtab' contains 6 entries: + +Num:.* + +[0-9]+:.* + +[0-9]+:.* + +[0-9]+:.* + +[0-9]+:.* + +[0-9]+:.* +#failif + +[0-9]+: +[0-9a-f]+ +0 +NOTYPE +GLOBAL +DEFAULT +UND v0.D diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-mov-bad.s b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-mov-bad.s new file mode 100644 index 00000000..d7ba2262 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/advsimd-mov-bad.s @@ -0,0 +1,2 @@ + .text + mov x0, v0.D[0] diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-copy.s b/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-copy.s index a76865fb..e9f282a7 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-copy.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-copy.s @@ -1,6 +1,6 @@ /* advsisd-copy.s Test file for AArch64 Advanced-SISD copy instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-misc.s b/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-misc.s index 50754f57..bdd80031 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-misc.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/advsisd-misc.s @@ -1,7 +1,7 @@ /* advsimd-abs.s Test file for AArch64 AdvSISD Scalar Misc instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/alias.d b/binutils-2.25/gas/testsuite/gas/aarch64/alias.d index 53cf5e93..5911b210 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/alias.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/alias.d @@ -96,3 +96,13 @@ Disassembly of section \.text: 160: 2f20a448 uxtl v8.2d, v2.2s 164: 6f20a448 uxtl2 v8.2d, v2.4s 168: 6f20a448 uxtl2 v8.2d, v2.4s + 16c: 1a81f420 csinc w0, w1, w1, nv + 170: 1a81e420 csinc w0, w1, w1, al + 174: 1a9ff7e0 csinc w0, wzr, wzr, nv + 178: 1a9fe7e0 csinc w0, wzr, wzr, al + 17c: 5a81f020 csinv w0, w1, w1, nv + 180: 5a81e020 csinv w0, w1, w1, al + 184: 5a9ff3e0 csinv w0, wzr, wzr, nv + 188: 5a9fe3e0 csinv w0, wzr, wzr, al + 18c: 5a81f420 csneg w0, w1, w1, nv + 190: 5a81e420 csneg w0, w1, w1, al diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/alias.s b/binutils-2.25/gas/testsuite/gas/aarch64/alias.s index 0db9affb..4ee04c10 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/alias.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/alias.s @@ -2,7 +2,7 @@ preference. It is also used to test the -Mno-aliases option in the disassemler. - Copyright 2012, 2013 Free Software Foundation, Inc. + Copyright (C) 2012-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. @@ -117,3 +117,14 @@ asimdshll s asimdshll u + + csinc w0, w1, w1, nv + csinc w0, w1, w1, al + csinc w0, wzr, wzr, nv + csinc w0, wzr, wzr, al + csinv w0, w1, w1, nv + csinv w0, w1, w1, al + csinv w0, wzr, wzr, nv + csinv w0, wzr, wzr, al + csneg w0, w1, w1, nv + csneg w0, w1, w1, al diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-alias.s b/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-alias.s index b2a0fc0b..e261c949 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-alias.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-alias.s @@ -1,7 +1,7 @@ /* bitfield-alias.s Test file for AArch64 bitfield instructions alias mnemonics. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-bfm.s b/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-bfm.s index af107ea3..9cfd382a 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-bfm.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/bitfield-bfm.s @@ -1,7 +1,7 @@ /* bitfield-bfm.s Test file for AArch64 bitfield instructions sbfm, bfm and ubfm mnemonics. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/crc32.s b/binutils-2.25/gas/testsuite/gas/aarch64/crc32.s index 34d9d927..621d3ccd 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/crc32.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/crc32.s @@ -1,6 +1,6 @@ /* crc32.s Test file for AArch64 CRC-32 and CRC-32C checksum instructions. - Copyright 2013 Free Software Foundation, Inc. + Copyright (C) 2013-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/crypto.s b/binutils-2.25/gas/testsuite/gas/aarch64/crypto.s index 9a1fe67d..01cb954b 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/crypto.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/crypto.s @@ -1,6 +1,6 @@ /* crypto.s Test file for AArch64 Advanced-SIMD Crypto instructions. - Copyright 2012 Free Software Foundation, Inc. Contributed by ARM Ltd. + Copyright (C) 2012-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.d b/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.d new file mode 100644 index 00000000..91996976 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.d @@ -0,0 +1,4 @@ +#name: Deprecated Support +#source: deprecated.s +#error-output: deprecated.l +#as: --warn diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.l b/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.l new file mode 100644 index 00000000..a2327f7a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +[^:]*:4: Warning: system register name 'spsr_svc' is deprecated and may be removed in a future release +[^:]*:5: Warning: system register name 'spsr_hyp' is deprecated and may be removed in a future release diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.s b/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.s new file mode 100644 index 00000000..442a492e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/deprecated.s @@ -0,0 +1,5 @@ +// deprecated.s Test file for diagnostics on deprecated features. + +.text + mrs x0, spsr_svc + msr spsr_hyp, x15 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.l b/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.l index cca8881b..322e3c0c 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.l +++ b/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.l @@ -14,7 +14,7 @@ [^:]*:16: Error: immediate value out of range 0 to 31 at operand 2 -- `ccmp x0,-1,10,le' [^:]*:17: Error: extraneous register at operand 2 -- `tlbi alle3is,x0' [^:]*:18: Error: missing register at operand 2 -- `tlbi vaale1is' -[^:]*:19: Error: unexpected characters following instruction at operand 1 -- `tlbi vaale1is x0' +[^:]*:19: Error: comma expected between operands at operand 2 -- `tlbi vaale1is x0' [^:]*:20: Error: immediate value out of range 0 to 1 at operand 1 -- `msr spsel,3' [^:]*:21: Error: immediate value out of range 1 to 64 at operand 3 -- `fcvtzu x15,d31,#66' [^:]*:22: Error: immediate value out of range 1 to 32 at operand 3 -- `scvtf s0,w0,33' @@ -87,3 +87,21 @@ [^:]*:89: Error: shift amount expected to be 0 at operand 2 -- `movi v1.8b,97,lsl#8' [^:]*:90: Error: unknown or missing system register name at operand 1 -- `msr dummy,x1' [^:]*:91: Error: invalid floating-point constant at operand 2 -- `fmov s0,0x42000000' +[^:]*:92: Error: immediate value should be a multiple of 8 at operand 3 -- `ldp x0,x1,\[x2,#4\]' +[^:]*:93: Error: immediate value should be a multiple of 8 at operand 3 -- `ldp x0,x1,\[x2,#4\]!' +[^:]*:94: Error: immediate value should be a multiple of 8 at operand 3 -- `ldp x0,x1,\[x2\],#4' +[^:]*:95: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2,#3\]' +[^:]*:96: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2,#2\]!' +[^:]*:97: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2\],#1' +[^:]*:98: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,al' +[^:]*:99: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv' +[^:]*:100: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,al' +[^:]*:101: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,nv' +[^:]*:104: Error: operand 1 should be an integer register -- `ret lr' +[^:]*:105: Error: operand 1 should be an integer register -- `ret kk' +[^:]*:106: Error: immediate operand required at operand 1 -- `clrex x0' +[^:]*:107: Error: immediate operand required at operand 1 -- `clrex w0' +[^:]*:108: Error: constant expression required at operand 1 -- `clrex kk' +[^:]*:109: Error: operand 5 should be an integer register -- `sys #0,c0,c0,#0,kk' +[^:]*:110: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys #0,c0,c0,#0,' +[^:]*:112: Error: selected processor does not support `casp w0,w1,w2,w3,\[x4\]' diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.s b/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.s index e5443ab7..b82ac8b2 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/diagnostic.s @@ -89,3 +89,24 @@ movi v1.8b, 97, lsl #8 msr dummy, x1 fmov s0, 0x42000000 + ldp x0, x1, [x2, #4] + ldp x0, x1, [x2, #4]! + ldp x0, x1, [x2], #4 + stp w0, w1, [x2, #3] + stp w0, w1, [x2, #2]! + stp w0, w1, [x2], #1 + cinc w0, w1, al + cinc w0, w1, nv + cset w0, al + cset w0, nv + + # test diagnostic info on optional operand + ret lr + ret kk + clrex x0 + clrex w0 + clrex kk + sys #0, c0, c0, #0, kk + sys #0, c0, c0, #0, + + casp w0,w1,w2,w3,[x4] diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/floatdp2.s b/binutils-2.25/gas/testsuite/gas/aarch64/floatdp2.s index 6a88e33a..31a9a4b4 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/floatdp2.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/floatdp2.s @@ -1,7 +1,7 @@ /* floatdp2.s Test file for AArch64 Floating-point data-processing (2 source) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/fp-const0-parse.d b/binutils-2.25/gas/testsuite/gas/aarch64/fp-const0-parse.d new file mode 100644 index 00000000..172f35c9 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/fp-const0-parse.d @@ -0,0 +1,37 @@ +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 5ea0dbc0 fcmeq s0, s30, #0.0 + 4: 7ea0cba1 fcmge s1, s29, #0.0 + 8: 5ea0cb82 fcmgt s2, s28, #0.0 + c: 7ea0db63 fcmle s3, s27, #0.0 + 10: 5ea0eb44 fcmlt s4, s26, #0.0 + 14: 5ee0dbc0 fcmeq d0, d30, #0.0 + 18: 7ee0cba1 fcmge d1, d29, #0.0 + 1c: 5ee0cb82 fcmgt d2, d28, #0.0 + 20: 7ee0db63 fcmle d3, d27, #0.0 + 24: 5ee0eb44 fcmlt d4, d26, #0.0 + 28: 0ea0dbc0 fcmeq v0.2s, v30.2s, #0.0 + 2c: 6ea0cba1 fcmge v1.4s, v29.4s, #0.0 + 30: 4ee0cb82 fcmgt v2.2d, v28.2d, #0.0 + 34: 2ea0db63 fcmle v3.2s, v27.2s, #0.0 + 38: 4ea0eb44 fcmlt v4.4s, v26.4s, #0.0 + 3c: 5ea0dbc0 fcmeq s0, s30, #0.0 + 40: 7ea0cba1 fcmge s1, s29, #0.0 + 44: 5ea0cb82 fcmgt s2, s28, #0.0 + 48: 7ea0db63 fcmle s3, s27, #0.0 + 4c: 5ea0eb44 fcmlt s4, s26, #0.0 + 50: 5ee0dbc0 fcmeq d0, d30, #0.0 + 54: 7ee0cba1 fcmge d1, d29, #0.0 + 58: 5ee0cb82 fcmgt d2, d28, #0.0 + 5c: 7ee0db63 fcmle d3, d27, #0.0 + 60: 5ee0eb44 fcmlt d4, d26, #0.0 + 64: 0ea0dbc0 fcmeq v0.2s, v30.2s, #0.0 + 68: 6ea0cba1 fcmge v1.4s, v29.4s, #0.0 + 6c: 4ee0cb82 fcmgt v2.2d, v28.2d, #0.0 + 70: 2ea0db63 fcmle v3.2s, v27.2s, #0.0 + 74: 4ea0eb44 fcmlt v4.4s, v26.4s, #0.0 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/fp-const0-parse.s b/binutils-2.25/gas/testsuite/gas/aarch64/fp-const0-parse.s new file mode 100644 index 00000000..2e904e55 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/fp-const0-parse.s @@ -0,0 +1,60 @@ +/* fp-const0-parse.s Test file For AArch64 float constant 0 parse. + + Copyright (C) 2014 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + + + .text + // Check #0 with scalar register. + fcmeq s0, s30, #0 + fcmge s1, s29, #0 + fcmgt s2, s28, #0 + fcmle s3, s27, #0 + fcmlt s4, s26, #0 + fcmeq d0, d30, #0 + fcmge d1, d29, #0 + fcmgt d2, d28, #0 + fcmle d3, d27, #0 + fcmlt d4, d26, #0 + + // Check #0 with vector register. + fcmeq v0.2s, v30.2s, #0 + fcmge v1.4s, v29.4s, #0 + fcmgt v2.2d, v28.2d, #0 + fcmle v3.2s, v27.2s, #0 + fcmlt v4.4s, v26.4s, #0 + + // Check #0.0 with scalar register. + fcmeq s0, s30, #0.0 + fcmge s1, s29, #0.0 + fcmgt s2, s28, #0.0 + fcmle s3, s27, #0.0 + fcmlt s4, s26, #0.0 + fcmeq d0, d30, #0.0 + fcmge d1, d29, #0.0 + fcmgt d2, d28, #0.0 + fcmle d3, d27, #0.0 + fcmlt d4, d26, #0.0 + + // Check #0.0 with vector register. + fcmeq v0.2s, v30.2s, #0.0 + fcmge v1.4s, v29.4s, #0.0 + fcmgt v2.2d, v28.2d, #0.0 + fcmle v3.2s, v27.2s, #0.0 + fcmlt v4.4s, v26.4s, #0.0 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/fp_cvt_int.s b/binutils-2.25/gas/testsuite/gas/aarch64/fp_cvt_int.s index f6888bac..d732143d 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/fp_cvt_int.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/fp_cvt_int.s @@ -1,7 +1,7 @@ /* fp_cvt_ins.s Test file for AArch64 floating-point<->fixed-point conversion and floating-point<->integer conversion instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.d b/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.d new file mode 100644 index 00000000..bcb965e4 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.d @@ -0,0 +1,4 @@ +#name: LSE Illegal Instruction Operands +#source: illegal-lse.s +#as: -march=armv8-a+lse -mno-verbose-error +#error-output: illegal-lse.l diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.l b/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.l new file mode 100644 index 00000000..ed700652 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.l @@ -0,0 +1,433 @@ +[^:]*: Assembler messages: +[^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cas w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casa w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casl w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casal w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casb w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casb w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `cash w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cash w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casab w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casab w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `caslb w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `caslb w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casalb w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casalb w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casah w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casah w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `caslh w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `caslh w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casalh w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casalh w2,w3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `cas w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `cas x2,x3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casa w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casa x2,x3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casl w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casl x2,x3,\[w4\]' +[^:]*:68: Error: operand mismatch -- `casal w0,x1,\[x2\]' +[^:]*:68: Error: operand 3 should be an address with base register \(no offset\) -- `casal x2,x3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swp w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpa w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpl w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpal w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpb w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpb w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swph w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swph w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpab w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpab w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swplb w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swplb w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpalb w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpalb w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpah w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpah w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swplh w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swplh w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpalh w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpalh w2,w3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swp w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swp x2,x3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpa w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpa x2,x3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpl w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpl x2,x3,\[w4\]' +[^:]*:69: Error: operand mismatch -- `swpal w0,x1,\[x2\]' +[^:]*:69: Error: operand 3 should be an address with base register \(no offset\) -- `swpal x2,x3,\[w4\]' +[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `casp w1,w1,w2,w3,\[x5\]' +[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `casp w4,w4,w6,w7,\[sp\]' +[^:]*:70: Error: operand mismatch -- `casp w0,x1,x2,x3,\[x2\]' +[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `casp x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspa w1,w1,w2,w3,\[x5\]' +[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspa w4,w4,w6,w7,\[sp\]' +[^:]*:70: Error: operand mismatch -- `caspa w0,x1,x2,x3,\[x2\]' +[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspa x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspl w1,w1,w2,w3,\[x5\]' +[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspl w4,w4,w6,w7,\[sp\]' +[^:]*:70: Error: operand mismatch -- `caspl w0,x1,x2,x3,\[x2\]' +[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspl x4,x5,x6,x7,\[w8\]' +[^:]*:70: Error: reg pair must start from even reg at operand 1 -- `caspal w1,w1,w2,w3,\[x5\]' +[^:]*:70: Error: reg pair must be contiguous at operand 2 -- `caspal w4,w4,w6,w7,\[sp\]' +[^:]*:70: Error: operand mismatch -- `caspal w0,x1,x2,x3,\[x2\]' +[^:]*:70: Error: operand 5 should be an address with base register \(no offset\) -- `caspal x4,x5,x6,x7,\[w8\]' +[^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadd w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadda w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddal w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddalb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddalb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddalh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddalh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldadd w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadd x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldadda w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldadda x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldaddal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldaddal x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclr w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclra w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclral w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclralb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclralb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclralh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclralh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclr w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclr x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclra w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclra x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclrl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclrl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldclral w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldclral x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeor w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeora w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoral w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeoralb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoralb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeoralh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoralh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeor w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeor x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeora w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeora x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeorl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeorl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldeoral w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldeoral x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldset w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseta w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetal w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldseth w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseth w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetalb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetalb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetalh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetalh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldset w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldset x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldseta w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldseta x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsetal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsetal x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmax w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxa w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxal w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxalb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxalb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxalh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxalh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmax w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmax x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxa w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxa x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmaxal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmaxal x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmin w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmina w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminal w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminalb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminalb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminalh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminalh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmin w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmin x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsmina w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsmina x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldsminal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldsminal x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumax w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxa w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxal w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxalb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxalb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxalh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxalh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumax w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumax x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxa w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxa x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumaxal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumaxal x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumin w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumina w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminl w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminal w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminab w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminab w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminlb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminlb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminalb w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminalb w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminah w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminah w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminlh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminlh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminalh w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminalh w2,w3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumin w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumin x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `ldumina w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `ldumina x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminl w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminl x2,x3,\[w4\]' +[^:]*:71: Error: operand mismatch -- `lduminal w0,x1,\[x2\]' +[^:]*:71: Error: operand 3 should be an address with base register \(no offset\) -- `lduminal x2,x3,\[w4\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stadd w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `staddb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `staddh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `staddlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `staddlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stadd x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `staddl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclr w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stclrb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stclrh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stclrlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stclrlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclr x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stclrl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steor w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `steorb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `steorh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `steorlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `steorlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steor x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `steorl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stset w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsetb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stseth x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stseth w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsetlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsetlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stset x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsetl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmax w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsmaxb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsmaxh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsmaxlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsmaxlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmax x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmaxl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmin w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsminb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsminh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsminlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stsminlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsmin x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stsminl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumax w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stumaxb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stumaxh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stumaxlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stumaxlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumax x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumaxl x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumin w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminl w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stuminb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stuminh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminh w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stuminlb x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminlb w2,\[w3\]' +[^:]*:72: Error: operand mismatch -- `stuminlh x0,\[x2\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminlh w2,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stumin x0,\[w3\]' +[^:]*:72: Error: operand 2 should be an address with base register \(no offset\) -- `stuminl x0,\[w3\]' diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.s b/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.s new file mode 100644 index 00000000..a9f5b77e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/illegal-lse.s @@ -0,0 +1,72 @@ +/* illegal-lse.s Test file For AArch64 LSE atomic instructions that + could be rejected by the assembler. + + Copyright 2014 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + + + .macro format_0_check op + .irp suffix, , a, l, al, b, h, ab, lb, alb, ah, lh, alh + \op\suffix w0, x1, [x2] + \op\suffix w2, w3, [w4] + .endr + .irp suffix, , a, l, al + \op\suffix w0, x1, [x2] + \op\suffix x2, x3, [w4] + .endr + .endm + + .macro format_0_no_rt_no_acquire_check op + .irp suffix, , l, b, h, lb, lh + \op\suffix x0, [x2] + \op\suffix w2, [w3] + .endr + .irp suffix, , l + \op\suffix x0, [w3] + .endr + .endm + + .macro format_1_check op + .irp suffix, , a, l, al + \op\suffix w1, w1, w2, w3, [x5] + \op\suffix w4, w4, w6, w7, [sp] + \op\suffix w0, x1, x2, x3, [x2] + \op\suffix x4, x5, x6, x7, [w8] + .endr + .endm + + .macro format_2_check op + .irp suffix, add, clr, eor, set, smax, smin, umax, umin + format_0_check \op\suffix + .endr + .endm + + .macro format_3_check op + .irp suffix, add, clr, eor, set, smax, smin, umax, umin + format_0_no_rt_no_acquire_check \op\suffix + .endr + .endm + + .text +func: + format_0_check cas + format_0_check swp + format_1_check casp + format_2_check ld + format_3_check st diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/illegal.d b/binutils-2.25/gas/testsuite/gas/aarch64/illegal.d index ade139c5..904eaced 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/illegal.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/illegal.d @@ -1,4 +1,4 @@ #name: Illegal Instructions -#as: +#as: -mno-verbose-error #source: illegal.s #error-output: illegal.l diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/illegal.l b/binutils-2.25/gas/testsuite/gas/aarch64/illegal.l index e36b8fef..0e8c7eb1 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/illegal.l +++ b/binutils-2.25/gas/testsuite/gas/aarch64/illegal.l @@ -519,7 +519,7 @@ [^:]*:494: Error: .*`bfi x3,x7,#31,#48' [^:]*:496: Error: .*`str x1,page_table_count' [^:]*:498: Error: .*`prfm PLDL3KEEP,\[x9,x15,sxtx#2\]' -[^:]*:500: Error: .*`mrs x5,S1_0_C13_C8_0' +[^:]*:500: Error: .*`mrs x5,S1_0_C17_C8_0' [^:]*:502: Error: .*`msr S3_1_C11_C15_-1,x7' [^:]*:503: Error: .*`msr S3_1_11_15_1,x7' [^:]*:506: Error: .*`movi w1,#15' @@ -552,4 +552,19 @@ [^:]*:544: Error: .*`fmov s0,#0xC0280000C1400000' [^:]*:545: Error: .*`fmov d0,#0xC02f800000000000' [^:]*:550: Error: .*`ands w0,w24,#0xffeefffffffffffd' -[^:]*:553: Error: .* +[^:]*:554: Error: .*`cinc w0,w1,al' +[^:]*:555: Error: .*`cinc w0,w1,nv' +[^:]*:556: Error: .*`cset w0,al' +[^:]*:557: Error: .*`cset w0,nv' +[^:]*:558: Error: .*`cinv w0,w1,al' +[^:]*:559: Error: .*`cinv w0,w1,nv' +[^:]*:560: Error: .*`csetm w0,al' +[^:]*:561: Error: .*`csetm w0,nv' +[^:]*:562: Error: .*`cneg w0,w1,al' +[^:]*:563: Error: .*`cneg w0,w1,nv' +[^:]*:565: Error: .*`mrs x5,S4_0_C12_C8_0' +[^:]*:566: Error: .*`mrs x6,S0_8_C11_C7_5' +[^:]*:567: Error: .*`mrs x7,S1_1_C16_C6_6' +[^:]*:568: Error: .*`mrs x8,S2_2_C15_C16_7' +[^:]*:569: Error: .*`mrs x9,S3_3_C14_C15_8' +[^:]*:569: Error: .* diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/illegal.s b/binutils-2.25/gas/testsuite/gas/aarch64/illegal.s index a46946e8..9cf06001 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/illegal.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/illegal.s @@ -1,7 +1,7 @@ /* illegal.s Test file for AArch64 instructions that should be rejected by the assembler. - Copyright 2011, 2012 Free Software Foundation, Inc. Contributed by ARM Ltd. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. @@ -497,7 +497,7 @@ prfm PLDL3KEEP, [x9, x15, sxtx #2] - mrs x5, S1_0_C13_C8_0 + mrs x5, S1_0_C17_C8_0 msr S3_1_C13_C15_1, x7 msr S3_1_C11_C15_-1, x7 msr S3_1_11_15_1, x7 @@ -550,4 +550,20 @@ ands w0, w24, #0xffeefffffffffffd one_label: - + + cinc w0, w1, al + cinc w0, w1, nv + cset w0, al + cset w0, nv + cinv w0, w1, al + cinv w0, w1, nv + csetm w0, al + csetm w0, nv + cneg w0, w1, al + cneg w0, w1, nv + + mrs x5, S4_0_C12_C8_0 + mrs x6, S0_8_C11_C7_5 + mrs x7, S1_1_C16_C6_6 + mrs x8, S2_2_C15_C16_7 + mrs x9, S3_3_C14_C15_8 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-exclusive.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-exclusive.s index fd66f36e..af7339ed 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-exclusive.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-exclusive.s @@ -1,7 +1,7 @@ /* ldst-exclusive.s Test file for AArch64 load-store exclusive instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s index bedc1577..57299b93 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-post-ind.s @@ -1,7 +1,7 @@ /* ldst-reg-imm-post-ind.s Test file for AArch64 load-store reg. (imm.post-ind.) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s index 22658691..87d6f603 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-imm-pre-ind.s @@ -1,7 +1,7 @@ /* ldst-reg-imm-pre-ind.s Test file for AArch64 load-store reg. (imm.pre-ind.) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-pair.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-pair.s index 2df333d9..8e74c64c 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-pair.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-pair.s @@ -1,6 +1,6 @@ /* ldst-reg-pair.s Test file for AArch64 load-store reg.pair instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d index 486d9c8e..b720633f 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.d @@ -85,3 +85,7 @@ Disassembly of section \.text: 134: fc67fbe7 ldr d7, \[sp,x7,sxtx #3\] 138: 3ce7ebe7 ldr q7, \[sp,x7,sxtx\] 13c: 3ce7fbe7 ldr q7, \[sp,x7,sxtx #4\] + 140: f87ffbe1 ldr x1, \[sp,xzr,sxtx #3\] + 144: f83ffbe1 str x1, \[sp,xzr,sxtx #3\] + 148: b87fdbe1 ldr w1, \[sp,wzr,sxtw #2\] + 14c: b83fdbe1 str w1, \[sp,wzr,sxtw #2\] diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s index afa7c4d1..7ece7bc6 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-reg-offset.s @@ -1,7 +1,7 @@ /* ldst-reg-reg-offset.s Test file for AArch64 load-store reg. (reg.offset) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. @@ -86,3 +86,9 @@ func: ld_or_st str ld_or_st ldr + + /* When the index register is of register 31, it should be ZR. */ + ldr x1, [sp, xzr, sxtx #3] + str x1, [sp, xzr, sxtx #3] + ldr w1, [sp, wzr, sxtw #2] + str w1, [sp, wzr, sxtw #2] diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s index ad3f6013..d700f8b9 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-uns-imm.s @@ -1,7 +1,7 @@ /* ld-reg-uns-imm.s Test file for AArch64 load-store reg. (uns.imm) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s index 72b0c97b..aaf555db 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/ldst-reg-unscaled-imm.s @@ -1,7 +1,7 @@ /* ldst-reg-unscaled-imm.s Test file for AArch64 load-store reg. (unscaled imm.) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/litpool.d b/binutils-2.25/gas/testsuite/gas/aarch64/litpool.d new file mode 100644 index 00000000..15edbc0a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/litpool.d @@ -0,0 +1,30 @@ +#objdump: -d +#name: AArch64 Bignums in Literal Pool (PR 16688) +# This test is only valid on ELF based ports. +#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +.*: +file format.*aarch64.* + +Disassembly of section \.text: + +00+00 <.*>: + 0: 9c000080 ldr q0, 10 <\.text\+0x10> + 4: 9c0000e1 ldr q1, 20 <\.text\+0x20> + 8: 9c000142 ldr q2, 30 <\.text\+0x30> + c: 9c0001a3 ldr q3, 40 <\.text\+0x40> + 10: 5a827999 .word 0x5a827999 + 14: 5a827999 .word 0x5a827999 + 18: 5a827999 .word 0x5a827999 + 1c: 5a827999 .word 0x5a827999 + 20: 6ed9eba1 .word 0x6ed9eba1 + 24: 6ed9eba1 .word 0x6ed9eba1 + 28: 6ed9eba1 .word 0x6ed9eba1 + 2c: 6ed9eba1 .word 0x6ed9eba1 + 30: 8f1bbcdc .word 0x8f1bbcdc + 34: 8f1bbcdc .word 0x8f1bbcdc + 38: 8f1bbcdc .word 0x8f1bbcdc + 3c: 8f1bbcdc .word 0x8f1bbcdc + 40: ca62c1d6 .word 0xca62c1d6 + 44: ca62c1d6 .word 0xca62c1d6 + 48: ca62c1d6 .word 0xca62c1d6 + 4c: ca62c1d6 .word 0xca62c1d6 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/litpool.s b/binutils-2.25/gas/testsuite/gas/aarch64/litpool.s new file mode 100644 index 00000000..83c6f4e0 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/litpool.s @@ -0,0 +1,7 @@ +# Based on PR 16688 this test checks that bignums are correctly added to the literal pool + .text + + ldr q0, =0x5a8279995a8279995a8279995a827999 + ldr q1, =0x6ed9eba16ed9eba16ed9eba16ed9eba1 + ldr q2, =0x8f1bbcdc8f1bbcdc8f1bbcdc8f1bbcdc + ldr q3, =0xca62c1d6ca62c1d6ca62c1d6ca62c1d6 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/lse-atomic.d b/binutils-2.25/gas/testsuite/gas/aarch64/lse-atomic.d new file mode 100644 index 00000000..73847e9e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/lse-atomic.d @@ -0,0 +1,472 @@ +#objdump: -dr +#as:-march=armv8-a+lse + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 88a07c41 cas w0, w1, \[x2\] + 4: 88a27fe3 cas w2, w3, \[sp\] + 8: 88e07c41 casa w0, w1, \[x2\] + c: 88e27fe3 casa w2, w3, \[sp\] + 10: 88a0fc41 casl w0, w1, \[x2\] + 14: 88a2ffe3 casl w2, w3, \[sp\] + 18: 88e0fc41 casal w0, w1, \[x2\] + 1c: 88e2ffe3 casal w2, w3, \[sp\] + 20: 08a07c41 casb w0, w1, \[x2\] + 24: 08a27fe3 casb w2, w3, \[sp\] + 28: 48a07c41 cash w0, w1, \[x2\] + 2c: 48a27fe3 cash w2, w3, \[sp\] + 30: 08e07c41 casab w0, w1, \[x2\] + 34: 08e27fe3 casab w2, w3, \[sp\] + 38: 08a0fc41 caslb w0, w1, \[x2\] + 3c: 08a2ffe3 caslb w2, w3, \[sp\] + 40: 08e0fc41 casalb w0, w1, \[x2\] + 44: 08e2ffe3 casalb w2, w3, \[sp\] + 48: 48e07c41 casah w0, w1, \[x2\] + 4c: 48e27fe3 casah w2, w3, \[sp\] + 50: 48a0fc41 caslh w0, w1, \[x2\] + 54: 48a2ffe3 caslh w2, w3, \[sp\] + 58: 48e0fc41 casalh w0, w1, \[x2\] + 5c: 48e2ffe3 casalh w2, w3, \[sp\] + 60: c8a07c41 cas x0, x1, \[x2\] + 64: c8a27fe3 cas x2, x3, \[sp\] + 68: c8e07c41 casa x0, x1, \[x2\] + 6c: c8e27fe3 casa x2, x3, \[sp\] + 70: c8a0fc41 casl x0, x1, \[x2\] + 74: c8a2ffe3 casl x2, x3, \[sp\] + 78: c8e0fc41 casal x0, x1, \[x2\] + 7c: c8e2ffe3 casal x2, x3, \[sp\] + 80: b8208041 swp w0, w1, \[x2\] + 84: b82283e3 swp w2, w3, \[sp\] + 88: b8a08041 swpa w0, w1, \[x2\] + 8c: b8a283e3 swpa w2, w3, \[sp\] + 90: b8608041 swpl w0, w1, \[x2\] + 94: b86283e3 swpl w2, w3, \[sp\] + 98: b8e08041 swpal w0, w1, \[x2\] + 9c: b8e283e3 swpal w2, w3, \[sp\] + a0: 38208041 swpb w0, w1, \[x2\] + a4: 382283e3 swpb w2, w3, \[sp\] + a8: 78208041 swph w0, w1, \[x2\] + ac: 782283e3 swph w2, w3, \[sp\] + b0: 38a08041 swpab w0, w1, \[x2\] + b4: 38a283e3 swpab w2, w3, \[sp\] + b8: 38608041 swplb w0, w1, \[x2\] + bc: 386283e3 swplb w2, w3, \[sp\] + c0: 38e08041 swpalb w0, w1, \[x2\] + c4: 38e283e3 swpalb w2, w3, \[sp\] + c8: 78a08041 swpah w0, w1, \[x2\] + cc: 78a283e3 swpah w2, w3, \[sp\] + d0: 78608041 swplh w0, w1, \[x2\] + d4: 786283e3 swplh w2, w3, \[sp\] + d8: 78e08041 swpalh w0, w1, \[x2\] + dc: 78e283e3 swpalh w2, w3, \[sp\] + e0: f8208041 swp x0, x1, \[x2\] + e4: f82283e3 swp x2, x3, \[sp\] + e8: f8a08041 swpa x0, x1, \[x2\] + ec: f8a283e3 swpa x2, x3, \[sp\] + f0: f8608041 swpl x0, x1, \[x2\] + f4: f86283e3 swpl x2, x3, \[sp\] + f8: f8e08041 swpal x0, x1, \[x2\] + fc: f8e283e3 swpal x2, x3, \[sp\] + 100: 08207ca2 casp w0, w1, w2, w3, \[x5\] + 104: 08247fe6 casp w4, w5, w6, w7, \[sp\] + 108: 48207c42 casp x0, x1, x2, x3, \[x2\] + 10c: 48247fe6 casp x4, x5, x6, x7, \[sp\] + 110: 08607ca2 caspa w0, w1, w2, w3, \[x5\] + 114: 08647fe6 caspa w4, w5, w6, w7, \[sp\] + 118: 48607c42 caspa x0, x1, x2, x3, \[x2\] + 11c: 48647fe6 caspa x4, x5, x6, x7, \[sp\] + 120: 0820fca2 caspl w0, w1, w2, w3, \[x5\] + 124: 0824ffe6 caspl w4, w5, w6, w7, \[sp\] + 128: 4820fc42 caspl x0, x1, x2, x3, \[x2\] + 12c: 4824ffe6 caspl x4, x5, x6, x7, \[sp\] + 130: 0860fca2 caspal w0, w1, w2, w3, \[x5\] + 134: 0864ffe6 caspal w4, w5, w6, w7, \[sp\] + 138: 4860fc42 caspal x0, x1, x2, x3, \[x2\] + 13c: 4864ffe6 caspal x4, x5, x6, x7, \[sp\] + 140: b8200041 ldadd w0, w1, \[x2\] + 144: b82203e3 ldadd w2, w3, \[sp\] + 148: b8a00041 ldadda w0, w1, \[x2\] + 14c: b8a203e3 ldadda w2, w3, \[sp\] + 150: b8600041 ldaddl w0, w1, \[x2\] + 154: b86203e3 ldaddl w2, w3, \[sp\] + 158: b8e00041 ldaddal w0, w1, \[x2\] + 15c: b8e203e3 ldaddal w2, w3, \[sp\] + 160: 38200041 ldaddb w0, w1, \[x2\] + 164: 382203e3 ldaddb w2, w3, \[sp\] + 168: 78200041 ldaddh w0, w1, \[x2\] + 16c: 782203e3 ldaddh w2, w3, \[sp\] + 170: 38a00041 ldaddab w0, w1, \[x2\] + 174: 38a203e3 ldaddab w2, w3, \[sp\] + 178: 38600041 ldaddlb w0, w1, \[x2\] + 17c: 386203e3 ldaddlb w2, w3, \[sp\] + 180: 38e00041 ldaddalb w0, w1, \[x2\] + 184: 38e203e3 ldaddalb w2, w3, \[sp\] + 188: 78a00041 ldaddah w0, w1, \[x2\] + 18c: 78a203e3 ldaddah w2, w3, \[sp\] + 190: 78600041 ldaddlh w0, w1, \[x2\] + 194: 786203e3 ldaddlh w2, w3, \[sp\] + 198: 78e00041 ldaddalh w0, w1, \[x2\] + 19c: 78e203e3 ldaddalh w2, w3, \[sp\] + 1a0: f8200041 ldadd x0, x1, \[x2\] + 1a4: f82203e3 ldadd x2, x3, \[sp\] + 1a8: f8a00041 ldadda x0, x1, \[x2\] + 1ac: f8a203e3 ldadda x2, x3, \[sp\] + 1b0: f8600041 ldaddl x0, x1, \[x2\] + 1b4: f86203e3 ldaddl x2, x3, \[sp\] + 1b8: f8e00041 ldaddal x0, x1, \[x2\] + 1bc: f8e203e3 ldaddal x2, x3, \[sp\] + 1c0: b8201041 ldclr w0, w1, \[x2\] + 1c4: b82213e3 ldclr w2, w3, \[sp\] + 1c8: b8a01041 ldclra w0, w1, \[x2\] + 1cc: b8a213e3 ldclra w2, w3, \[sp\] + 1d0: b8601041 ldclrl w0, w1, \[x2\] + 1d4: b86213e3 ldclrl w2, w3, \[sp\] + 1d8: b8e01041 ldclral w0, w1, \[x2\] + 1dc: b8e213e3 ldclral w2, w3, \[sp\] + 1e0: 38201041 ldclrb w0, w1, \[x2\] + 1e4: 382213e3 ldclrb w2, w3, \[sp\] + 1e8: 78201041 ldclrh w0, w1, \[x2\] + 1ec: 782213e3 ldclrh w2, w3, \[sp\] + 1f0: 38a01041 ldclrab w0, w1, \[x2\] + 1f4: 38a213e3 ldclrab w2, w3, \[sp\] + 1f8: 38601041 ldclrlb w0, w1, \[x2\] + 1fc: 386213e3 ldclrlb w2, w3, \[sp\] + 200: 38e01041 ldclralb w0, w1, \[x2\] + 204: 38e213e3 ldclralb w2, w3, \[sp\] + 208: 78a01041 ldclrah w0, w1, \[x2\] + 20c: 78a213e3 ldclrah w2, w3, \[sp\] + 210: 78601041 ldclrlh w0, w1, \[x2\] + 214: 786213e3 ldclrlh w2, w3, \[sp\] + 218: 78e01041 ldclralh w0, w1, \[x2\] + 21c: 78e213e3 ldclralh w2, w3, \[sp\] + 220: f8201041 ldclr x0, x1, \[x2\] + 224: f82213e3 ldclr x2, x3, \[sp\] + 228: f8a01041 ldclra x0, x1, \[x2\] + 22c: f8a213e3 ldclra x2, x3, \[sp\] + 230: f8601041 ldclrl x0, x1, \[x2\] + 234: f86213e3 ldclrl x2, x3, \[sp\] + 238: f8e01041 ldclral x0, x1, \[x2\] + 23c: f8e213e3 ldclral x2, x3, \[sp\] + 240: b8202041 ldeor w0, w1, \[x2\] + 244: b82223e3 ldeor w2, w3, \[sp\] + 248: b8a02041 ldeora w0, w1, \[x2\] + 24c: b8a223e3 ldeora w2, w3, \[sp\] + 250: b8602041 ldeorl w0, w1, \[x2\] + 254: b86223e3 ldeorl w2, w3, \[sp\] + 258: b8e02041 ldeoral w0, w1, \[x2\] + 25c: b8e223e3 ldeoral w2, w3, \[sp\] + 260: 38202041 ldeorb w0, w1, \[x2\] + 264: 382223e3 ldeorb w2, w3, \[sp\] + 268: 78202041 ldeorh w0, w1, \[x2\] + 26c: 782223e3 ldeorh w2, w3, \[sp\] + 270: 38a02041 ldeorab w0, w1, \[x2\] + 274: 38a223e3 ldeorab w2, w3, \[sp\] + 278: 38602041 ldeorlb w0, w1, \[x2\] + 27c: 386223e3 ldeorlb w2, w3, \[sp\] + 280: 38e02041 ldeoralb w0, w1, \[x2\] + 284: 38e223e3 ldeoralb w2, w3, \[sp\] + 288: 78a02041 ldeorah w0, w1, \[x2\] + 28c: 78a223e3 ldeorah w2, w3, \[sp\] + 290: 78602041 ldeorlh w0, w1, \[x2\] + 294: 786223e3 ldeorlh w2, w3, \[sp\] + 298: 78e02041 ldeoralh w0, w1, \[x2\] + 29c: 78e223e3 ldeoralh w2, w3, \[sp\] + 2a0: f8202041 ldeor x0, x1, \[x2\] + 2a4: f82223e3 ldeor x2, x3, \[sp\] + 2a8: f8a02041 ldeora x0, x1, \[x2\] + 2ac: f8a223e3 ldeora x2, x3, \[sp\] + 2b0: f8602041 ldeorl x0, x1, \[x2\] + 2b4: f86223e3 ldeorl x2, x3, \[sp\] + 2b8: f8e02041 ldeoral x0, x1, \[x2\] + 2bc: f8e223e3 ldeoral x2, x3, \[sp\] + 2c0: b8203041 ldset w0, w1, \[x2\] + 2c4: b82233e3 ldset w2, w3, \[sp\] + 2c8: b8a03041 ldseta w0, w1, \[x2\] + 2cc: b8a233e3 ldseta w2, w3, \[sp\] + 2d0: b8603041 ldsetl w0, w1, \[x2\] + 2d4: b86233e3 ldsetl w2, w3, \[sp\] + 2d8: b8e03041 ldsetal w0, w1, \[x2\] + 2dc: b8e233e3 ldsetal w2, w3, \[sp\] + 2e0: 38203041 ldsetb w0, w1, \[x2\] + 2e4: 382233e3 ldsetb w2, w3, \[sp\] + 2e8: 78203041 ldseth w0, w1, \[x2\] + 2ec: 782233e3 ldseth w2, w3, \[sp\] + 2f0: 38a03041 ldsetab w0, w1, \[x2\] + 2f4: 38a233e3 ldsetab w2, w3, \[sp\] + 2f8: 38603041 ldsetlb w0, w1, \[x2\] + 2fc: 386233e3 ldsetlb w2, w3, \[sp\] + 300: 38e03041 ldsetalb w0, w1, \[x2\] + 304: 38e233e3 ldsetalb w2, w3, \[sp\] + 308: 78a03041 ldsetah w0, w1, \[x2\] + 30c: 78a233e3 ldsetah w2, w3, \[sp\] + 310: 78603041 ldsetlh w0, w1, \[x2\] + 314: 786233e3 ldsetlh w2, w3, \[sp\] + 318: 78e03041 ldsetalh w0, w1, \[x2\] + 31c: 78e233e3 ldsetalh w2, w3, \[sp\] + 320: f8203041 ldset x0, x1, \[x2\] + 324: f82233e3 ldset x2, x3, \[sp\] + 328: f8a03041 ldseta x0, x1, \[x2\] + 32c: f8a233e3 ldseta x2, x3, \[sp\] + 330: f8603041 ldsetl x0, x1, \[x2\] + 334: f86233e3 ldsetl x2, x3, \[sp\] + 338: f8e03041 ldsetal x0, x1, \[x2\] + 33c: f8e233e3 ldsetal x2, x3, \[sp\] + 340: b8204041 ldsmax w0, w1, \[x2\] + 344: b82243e3 ldsmax w2, w3, \[sp\] + 348: b8a04041 ldsmaxa w0, w1, \[x2\] + 34c: b8a243e3 ldsmaxa w2, w3, \[sp\] + 350: b8604041 ldsmaxl w0, w1, \[x2\] + 354: b86243e3 ldsmaxl w2, w3, \[sp\] + 358: b8e04041 ldsmaxal w0, w1, \[x2\] + 35c: b8e243e3 ldsmaxal w2, w3, \[sp\] + 360: 38204041 ldsmaxb w0, w1, \[x2\] + 364: 382243e3 ldsmaxb w2, w3, \[sp\] + 368: 78204041 ldsmaxh w0, w1, \[x2\] + 36c: 782243e3 ldsmaxh w2, w3, \[sp\] + 370: 38a04041 ldsmaxab w0, w1, \[x2\] + 374: 38a243e3 ldsmaxab w2, w3, \[sp\] + 378: 38604041 ldsmaxlb w0, w1, \[x2\] + 37c: 386243e3 ldsmaxlb w2, w3, \[sp\] + 380: 38e04041 ldsmaxalb w0, w1, \[x2\] + 384: 38e243e3 ldsmaxalb w2, w3, \[sp\] + 388: 78a04041 ldsmaxah w0, w1, \[x2\] + 38c: 78a243e3 ldsmaxah w2, w3, \[sp\] + 390: 78604041 ldsmaxlh w0, w1, \[x2\] + 394: 786243e3 ldsmaxlh w2, w3, \[sp\] + 398: 78e04041 ldsmaxalh w0, w1, \[x2\] + 39c: 78e243e3 ldsmaxalh w2, w3, \[sp\] + 3a0: f8204041 ldsmax x0, x1, \[x2\] + 3a4: f82243e3 ldsmax x2, x3, \[sp\] + 3a8: f8a04041 ldsmaxa x0, x1, \[x2\] + 3ac: f8a243e3 ldsmaxa x2, x3, \[sp\] + 3b0: f8604041 ldsmaxl x0, x1, \[x2\] + 3b4: f86243e3 ldsmaxl x2, x3, \[sp\] + 3b8: f8e04041 ldsmaxal x0, x1, \[x2\] + 3bc: f8e243e3 ldsmaxal x2, x3, \[sp\] + 3c0: b8205041 ldsmin w0, w1, \[x2\] + 3c4: b82253e3 ldsmin w2, w3, \[sp\] + 3c8: b8a05041 ldsmina w0, w1, \[x2\] + 3cc: b8a253e3 ldsmina w2, w3, \[sp\] + 3d0: b8605041 ldsminl w0, w1, \[x2\] + 3d4: b86253e3 ldsminl w2, w3, \[sp\] + 3d8: b8e05041 ldsminal w0, w1, \[x2\] + 3dc: b8e253e3 ldsminal w2, w3, \[sp\] + 3e0: 38205041 ldsminb w0, w1, \[x2\] + 3e4: 382253e3 ldsminb w2, w3, \[sp\] + 3e8: 78205041 ldsminh w0, w1, \[x2\] + 3ec: 782253e3 ldsminh w2, w3, \[sp\] + 3f0: 38a05041 ldsminab w0, w1, \[x2\] + 3f4: 38a253e3 ldsminab w2, w3, \[sp\] + 3f8: 38605041 ldsminlb w0, w1, \[x2\] + 3fc: 386253e3 ldsminlb w2, w3, \[sp\] + 400: 38e05041 ldsminalb w0, w1, \[x2\] + 404: 38e253e3 ldsminalb w2, w3, \[sp\] + 408: 78a05041 ldsminah w0, w1, \[x2\] + 40c: 78a253e3 ldsminah w2, w3, \[sp\] + 410: 78605041 ldsminlh w0, w1, \[x2\] + 414: 786253e3 ldsminlh w2, w3, \[sp\] + 418: 78e05041 ldsminalh w0, w1, \[x2\] + 41c: 78e253e3 ldsminalh w2, w3, \[sp\] + 420: f8205041 ldsmin x0, x1, \[x2\] + 424: f82253e3 ldsmin x2, x3, \[sp\] + 428: f8a05041 ldsmina x0, x1, \[x2\] + 42c: f8a253e3 ldsmina x2, x3, \[sp\] + 430: f8605041 ldsminl x0, x1, \[x2\] + 434: f86253e3 ldsminl x2, x3, \[sp\] + 438: f8e05041 ldsminal x0, x1, \[x2\] + 43c: f8e253e3 ldsminal x2, x3, \[sp\] + 440: b8206041 ldumax w0, w1, \[x2\] + 444: b82263e3 ldumax w2, w3, \[sp\] + 448: b8a06041 ldumaxa w0, w1, \[x2\] + 44c: b8a263e3 ldumaxa w2, w3, \[sp\] + 450: b8606041 ldumaxl w0, w1, \[x2\] + 454: b86263e3 ldumaxl w2, w3, \[sp\] + 458: b8e06041 ldumaxal w0, w1, \[x2\] + 45c: b8e263e3 ldumaxal w2, w3, \[sp\] + 460: 38206041 ldumaxb w0, w1, \[x2\] + 464: 382263e3 ldumaxb w2, w3, \[sp\] + 468: 78206041 ldumaxh w0, w1, \[x2\] + 46c: 782263e3 ldumaxh w2, w3, \[sp\] + 470: 38a06041 ldumaxab w0, w1, \[x2\] + 474: 38a263e3 ldumaxab w2, w3, \[sp\] + 478: 38606041 ldumaxlb w0, w1, \[x2\] + 47c: 386263e3 ldumaxlb w2, w3, \[sp\] + 480: 38e06041 ldumaxalb w0, w1, \[x2\] + 484: 38e263e3 ldumaxalb w2, w3, \[sp\] + 488: 78a06041 ldumaxah w0, w1, \[x2\] + 48c: 78a263e3 ldumaxah w2, w3, \[sp\] + 490: 78606041 ldumaxlh w0, w1, \[x2\] + 494: 786263e3 ldumaxlh w2, w3, \[sp\] + 498: 78e06041 ldumaxalh w0, w1, \[x2\] + 49c: 78e263e3 ldumaxalh w2, w3, \[sp\] + 4a0: f8206041 ldumax x0, x1, \[x2\] + 4a4: f82263e3 ldumax x2, x3, \[sp\] + 4a8: f8a06041 ldumaxa x0, x1, \[x2\] + 4ac: f8a263e3 ldumaxa x2, x3, \[sp\] + 4b0: f8606041 ldumaxl x0, x1, \[x2\] + 4b4: f86263e3 ldumaxl x2, x3, \[sp\] + 4b8: f8e06041 ldumaxal x0, x1, \[x2\] + 4bc: f8e263e3 ldumaxal x2, x3, \[sp\] + 4c0: b8207041 ldumin w0, w1, \[x2\] + 4c4: b82273e3 ldumin w2, w3, \[sp\] + 4c8: b8a07041 ldumina w0, w1, \[x2\] + 4cc: b8a273e3 ldumina w2, w3, \[sp\] + 4d0: b8607041 lduminl w0, w1, \[x2\] + 4d4: b86273e3 lduminl w2, w3, \[sp\] + 4d8: b8e07041 lduminal w0, w1, \[x2\] + 4dc: b8e273e3 lduminal w2, w3, \[sp\] + 4e0: 38207041 lduminb w0, w1, \[x2\] + 4e4: 382273e3 lduminb w2, w3, \[sp\] + 4e8: 78207041 lduminh w0, w1, \[x2\] + 4ec: 782273e3 lduminh w2, w3, \[sp\] + 4f0: 38a07041 lduminab w0, w1, \[x2\] + 4f4: 38a273e3 lduminab w2, w3, \[sp\] + 4f8: 38607041 lduminlb w0, w1, \[x2\] + 4fc: 386273e3 lduminlb w2, w3, \[sp\] + 500: 38e07041 lduminalb w0, w1, \[x2\] + 504: 38e273e3 lduminalb w2, w3, \[sp\] + 508: 78a07041 lduminah w0, w1, \[x2\] + 50c: 78a273e3 lduminah w2, w3, \[sp\] + 510: 78607041 lduminlh w0, w1, \[x2\] + 514: 786273e3 lduminlh w2, w3, \[sp\] + 518: 78e07041 lduminalh w0, w1, \[x2\] + 51c: 78e273e3 lduminalh w2, w3, \[sp\] + 520: f8207041 ldumin x0, x1, \[x2\] + 524: f82273e3 ldumin x2, x3, \[sp\] + 528: f8a07041 ldumina x0, x1, \[x2\] + 52c: f8a273e3 ldumina x2, x3, \[sp\] + 530: f8607041 lduminl x0, x1, \[x2\] + 534: f86273e3 lduminl x2, x3, \[sp\] + 538: f8e07041 lduminal x0, x1, \[x2\] + 53c: f8e273e3 lduminal x2, x3, \[sp\] + 540: b820005f stadd w0, \[x2\] + 544: b82203ff stadd w2, \[sp\] + 548: b860005f staddl w0, \[x2\] + 54c: b86203ff staddl w2, \[sp\] + 550: 3820005f staddb w0, \[x2\] + 554: 382203ff staddb w2, \[sp\] + 558: 7820005f staddh w0, \[x2\] + 55c: 782203ff staddh w2, \[sp\] + 560: 3860005f staddlb w0, \[x2\] + 564: 386203ff staddlb w2, \[sp\] + 568: 7860005f staddlh w0, \[x2\] + 56c: 786203ff staddlh w2, \[sp\] + 570: f820005f stadd x0, \[x2\] + 574: f82203ff stadd x2, \[sp\] + 578: f860005f staddl x0, \[x2\] + 57c: f86203ff staddl x2, \[sp\] + 580: b820105f stclr w0, \[x2\] + 584: b82213ff stclr w2, \[sp\] + 588: b860105f stclrl w0, \[x2\] + 58c: b86213ff stclrl w2, \[sp\] + 590: 3820105f stclrb w0, \[x2\] + 594: 382213ff stclrb w2, \[sp\] + 598: 7820105f stclrh w0, \[x2\] + 59c: 782213ff stclrh w2, \[sp\] + 5a0: 3860105f stclrlb w0, \[x2\] + 5a4: 386213ff stclrlb w2, \[sp\] + 5a8: 7860105f stclrlh w0, \[x2\] + 5ac: 786213ff stclrlh w2, \[sp\] + 5b0: f820105f stclr x0, \[x2\] + 5b4: f82213ff stclr x2, \[sp\] + 5b8: f860105f stclrl x0, \[x2\] + 5bc: f86213ff stclrl x2, \[sp\] + 5c0: b820205f steor w0, \[x2\] + 5c4: b82223ff steor w2, \[sp\] + 5c8: b860205f steorl w0, \[x2\] + 5cc: b86223ff steorl w2, \[sp\] + 5d0: 3820205f steorb w0, \[x2\] + 5d4: 382223ff steorb w2, \[sp\] + 5d8: 7820205f steorh w0, \[x2\] + 5dc: 782223ff steorh w2, \[sp\] + 5e0: 3860205f steorlb w0, \[x2\] + 5e4: 386223ff steorlb w2, \[sp\] + 5e8: 7860205f steorlh w0, \[x2\] + 5ec: 786223ff steorlh w2, \[sp\] + 5f0: f820205f steor x0, \[x2\] + 5f4: f82223ff steor x2, \[sp\] + 5f8: f860205f steorl x0, \[x2\] + 5fc: f86223ff steorl x2, \[sp\] + 600: b820305f stset w0, \[x2\] + 604: b82233ff stset w2, \[sp\] + 608: b860305f stsetl w0, \[x2\] + 60c: b86233ff stsetl w2, \[sp\] + 610: 3820305f stsetb w0, \[x2\] + 614: 382233ff stsetb w2, \[sp\] + 618: 7820305f stseth w0, \[x2\] + 61c: 782233ff stseth w2, \[sp\] + 620: 3860305f stsetlb w0, \[x2\] + 624: 386233ff stsetlb w2, \[sp\] + 628: 7860305f stsetlh w0, \[x2\] + 62c: 786233ff stsetlh w2, \[sp\] + 630: f820305f stset x0, \[x2\] + 634: f82233ff stset x2, \[sp\] + 638: f860305f stsetl x0, \[x2\] + 63c: f86233ff stsetl x2, \[sp\] + 640: b820405f stsmax w0, \[x2\] + 644: b82243ff stsmax w2, \[sp\] + 648: b860405f stsmaxl w0, \[x2\] + 64c: b86243ff stsmaxl w2, \[sp\] + 650: 3820405f stsmaxb w0, \[x2\] + 654: 382243ff stsmaxb w2, \[sp\] + 658: 7820405f stsmaxh w0, \[x2\] + 65c: 782243ff stsmaxh w2, \[sp\] + 660: 3860405f stsmaxlb w0, \[x2\] + 664: 386243ff stsmaxlb w2, \[sp\] + 668: 7860405f stsmaxlh w0, \[x2\] + 66c: 786243ff stsmaxlh w2, \[sp\] + 670: f820405f stsmax x0, \[x2\] + 674: f82243ff stsmax x2, \[sp\] + 678: f860405f stsmaxl x0, \[x2\] + 67c: f86243ff stsmaxl x2, \[sp\] + 680: b820505f stsmin w0, \[x2\] + 684: b82253ff stsmin w2, \[sp\] + 688: b860505f stsminl w0, \[x2\] + 68c: b86253ff stsminl w2, \[sp\] + 690: 3820505f stsminb w0, \[x2\] + 694: 382253ff stsminb w2, \[sp\] + 698: 7820505f stsminh w0, \[x2\] + 69c: 782253ff stsminh w2, \[sp\] + 6a0: 3860505f stsminlb w0, \[x2\] + 6a4: 386253ff stsminlb w2, \[sp\] + 6a8: 7860505f stsminlh w0, \[x2\] + 6ac: 786253ff stsminlh w2, \[sp\] + 6b0: f820505f stsmin x0, \[x2\] + 6b4: f82253ff stsmin x2, \[sp\] + 6b8: f860505f stsminl x0, \[x2\] + 6bc: f86253ff stsminl x2, \[sp\] + 6c0: b820605f stumax w0, \[x2\] + 6c4: b82263ff stumax w2, \[sp\] + 6c8: b860605f stumaxl w0, \[x2\] + 6cc: b86263ff stumaxl w2, \[sp\] + 6d0: 3820605f stumaxb w0, \[x2\] + 6d4: 382263ff stumaxb w2, \[sp\] + 6d8: 7820605f stumaxh w0, \[x2\] + 6dc: 782263ff stumaxh w2, \[sp\] + 6e0: 3860605f stumaxlb w0, \[x2\] + 6e4: 386263ff stumaxlb w2, \[sp\] + 6e8: 7860605f stumaxlh w0, \[x2\] + 6ec: 786263ff stumaxlh w2, \[sp\] + 6f0: f820605f stumax x0, \[x2\] + 6f4: f82263ff stumax x2, \[sp\] + 6f8: f860605f stumaxl x0, \[x2\] + 6fc: f86263ff stumaxl x2, \[sp\] + 700: b820705f stumin w0, \[x2\] + 704: b82273ff stumin w2, \[sp\] + 708: b860705f stuminl w0, \[x2\] + 70c: b86273ff stuminl w2, \[sp\] + 710: 3820705f stuminb w0, \[x2\] + 714: 382273ff stuminb w2, \[sp\] + 718: 7820705f stuminh w0, \[x2\] + 71c: 782273ff stuminh w2, \[sp\] + 720: 3860705f stuminlb w0, \[x2\] + 724: 386273ff stuminlb w2, \[sp\] + 728: 7860705f stuminlh w0, \[x2\] + 72c: 786273ff stuminlh w2, \[sp\] + 730: f820705f stumin x0, \[x2\] + 734: f82273ff stumin x2, \[sp\] + 738: f860705f stuminl x0, \[x2\] + 73c: f86273ff stuminl x2, \[sp\] diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/lse-atomic.s b/binutils-2.25/gas/testsuite/gas/aarch64/lse-atomic.s new file mode 100644 index 00000000..8417af57 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/lse-atomic.s @@ -0,0 +1,72 @@ +/* lse-atomic.s Test file For AArch64 LSE atomic instructions encoding. + + Copyright 2014 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + + + .macro format_0 op + .irp suffix, , a, l, al, b, h, ab, lb, alb, ah, lh, alh + \op\suffix w0, w1, [x2] + \op\suffix w2, w3, [sp] + .endr + .irp suffix, , a, l, al + \op\suffix x0, x1, [x2] + \op\suffix x2, x3, [sp] + .endr + .endm + + .macro format_0_no_rt_no_acquire op + .irp suffix, , l, b, h, lb, lh + \op\suffix w0, [x2] + \op\suffix w2, [sp] + .endr + .irp suffix, , l + \op\suffix x0, [x2] + \op\suffix x2, [sp] + .endr + .endm + + .macro format_1 op + .irp suffix, , a, l, al + \op\suffix w0, w1, w2, w3, [x5] + \op\suffix w4, w5, w6, w7, [sp] + \op\suffix x0, x1, x2, x3, [x2] + \op\suffix x4, x5, x6, x7, [sp] + .endr + .endm + + .macro format_2 op + .irp suffix, add, clr, eor, set, smax, smin, umax, umin + format_0 \op\suffix + .endr + .endm + + .macro format_3 op + .irp suffix, add, clr, eor, set, smax, smin, umax, umin + format_0_no_rt_no_acquire \op\suffix + .endr + .endm + + .text +func: + format_0 cas + format_0 swp + format_1 casp + format_2 ld + format_3 st diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/msr.d b/binutils-2.25/gas/testsuite/gas/aarch64/msr.d index c6c32200..750cae11 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/msr.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/msr.d @@ -13,3 +13,5 @@ Disassembly of section \.text: 14: d5034fff msr daifclr, #0xf 18: d51b4220 msr daif, x0 1c: d53b4220 mrs x0, daif + 20: d50040bf msr spsel, #0x0 + 24: d50041bf msr spsel, #0x1 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/msr.s b/binutils-2.25/gas/testsuite/gas/aarch64/msr.s index 9f67d987..1dc747ad 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/msr.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/msr.s @@ -1,5 +1,5 @@ /* - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. @@ -31,3 +31,6 @@ func: msr daif, x0 mrs x0, daif + + msr spsel, #0 + msr spsel, #1 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/neon-fp-cvt-int.s b/binutils-2.25/gas/testsuite/gas/aarch64/neon-fp-cvt-int.s index 437d9990..ebe705bf 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/neon-fp-cvt-int.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/neon-fp-cvt-int.s @@ -2,7 +2,7 @@ floating-point<->fixed-point conversion and floating-point<->integer conversion instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/no-aliases.d b/binutils-2.25/gas/testsuite/gas/aarch64/no-aliases.d index 1065094f..fd940647 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/no-aliases.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/no-aliases.d @@ -97,3 +97,13 @@ Disassembly of section \.text: 160: 2f20a448 ushll v8.2d, v2.2s, #0 164: 6f20a448 ushll2 v8.2d, v2.4s, #0 168: 6f20a448 ushll2 v8.2d, v2.4s, #0 + 16c: 1a81f420 csinc w0, w1, w1, nv + 170: 1a81e420 csinc w0, w1, w1, al + 174: 1a9ff7e0 csinc w0, wzr, wzr, nv + 178: 1a9fe7e0 csinc w0, wzr, wzr, al + 17c: 5a81f020 csinv w0, w1, w1, nv + 180: 5a81e020 csinv w0, w1, w1, al + 184: 5a9ff3e0 csinv w0, wzr, wzr, nv + 188: 5a9fe3e0 csinv w0, wzr, wzr, al + 18c: 5a81f420 csneg w0, w1, w1, nv + 190: 5a81e420 csneg w0, w1, w1, al diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.d b/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.d new file mode 100644 index 00000000..a60f9874 --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.d @@ -0,0 +1,4 @@ +#name: SIMD Extension Removal +#source: rm-simd-ext.s +#error-output: rm-simd-ext.l +#as: -mcpu=cortex-a57+nosimd diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.l b/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.l new file mode 100644 index 00000000..2e24967a --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.l @@ -0,0 +1,2 @@ +[^:]*: Assembler messages: +[^:]*:27: Error: selected processor does not support `orr v0.16b,v1.16b,v2.16b' diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.s b/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.s new file mode 100644 index 00000000..ce634dde --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/aarch64/rm-simd-ext.s @@ -0,0 +1,28 @@ +/* rm-simd-ext.s Test file for AArch64 extension removal in -mcpu option. + + Copyright (C) 2013-2014 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the license, or + (at your option) any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see <http://www.gnu.org/licenses/>. */ + + .text + mov w3, 200 + mul w3, w2, w3 + add w1, w1, w3 + add w2, w0, w2, lsl 2 + orr v0.16b, v1.16b, v2.16b + orr w1, w1, w3 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/shifted.s b/binutils-2.25/gas/testsuite/gas/aarch64/shifted.s index efa7eeb9..4ee2381a 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/shifted.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/shifted.s @@ -1,7 +1,7 @@ /* shifted.s Test file for AArch64 add-substract (extended reg.) and add-substract (shifted reg.) instructions. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.d b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.d index 75f75b7e..c6be2c40 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.d @@ -4277,3 +4277,19 @@ Disassembly of section \.text: 42b4: d53cc04f mrs x15, rmr_el2 42b8: d51ec04f msr rmr_el3, x15 42bc: d53ec04f mrs x15, rmr_el3 + 42c0: d518400f msr spsr_el1, x15 + 42c4: d538400f mrs x15, spsr_el1 + 42c8: d51c400f msr spsr_el2, x15 + 42cc: d53c400f mrs x15, spsr_el2 + 42d0: d51e400f msr spsr_el3, x15 + 42d4: d53e400f mrs x15, spsr_el3 + 42d8: d500000f msr s0_0_c0_c0_0, x15 + 42dc: d520000f mrs x15, s0_0_c0_c0_0 + 42e0: d50ffffb sys #7, C15, C15, #7, x27 + 42e4: d52ffffb sysl x27, #7, C15, C15, #7 + 42e8: d514680e msr s2_4_c6_c8_0, x14 + 42ec: d534680e mrs x14, s2_4_c6_c8_0 + 42f0: d50ae444 sys #2, C14, C4, #2, x4 + 42f4: d52ae444 sysl x4, #2, C14, C4, #2 + 42f8: d501d167 msr s0_1_c13_c1_3, x7 + 42fc: d521d167 mrs x7, s0_1_c13_c1_3 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.s b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.s index a2fcef4e..fc08328f 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg-1.s @@ -1,6 +1,6 @@ /* sysreg-1.s Test file for AArch64 system registers. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. @@ -162,3 +162,13 @@ rw_sys_reg sys_reg=rmr_el1 xreg=x15 r=1 w=1 rw_sys_reg sys_reg=rmr_el2 xreg=x15 r=1 w=1 rw_sys_reg sys_reg=rmr_el3 xreg=x15 r=1 w=1 + + rw_sys_reg sys_reg=spsr_el1 xreg=x15 r=1 w=1 + rw_sys_reg sys_reg=spsr_el2 xreg=x15 r=1 w=1 + rw_sys_reg sys_reg=spsr_el3 xreg=x15 r=1 w=1 + + rw_sys_reg sys_reg=s0_0_C0_C0_0 xreg=x15 r=1 w=1 + rw_sys_reg sys_reg=s1_7_C15_C15_7 xreg=x27 r=1 w=1 + rw_sys_reg sys_reg=s2_4_C6_C8_0 xreg=x14 r=1 w=1 + rw_sys_reg sys_reg=s1_2_C14_C4_2 xreg=x4 r=1 w=1 + rw_sys_reg sys_reg=s0_1_C13_C1_3 xreg=x7 r=1 w=1 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.d b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.d index c7cf00ef..7795b4dd 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.d +++ b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.d @@ -26,3 +26,5 @@ Disassembly of section \.text: 48: d538cc00 mrs x0, s3_0_c12_c12_0 4c: d5384600 mrs x0, s3_0_c4_c6_0 50: d5184600 msr s3_0_c4_c6_0, x0 + 54: d5310300 mrs x0, s2_1_c0_c3_0 + 58: d5110300 msr s2_1_c0_c3_0, x0 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.s b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.s index 32875944..b7e5ff6c 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/sysreg.s @@ -26,3 +26,6 @@ mrs x0, s3_0_c12_c12_0 mrs x0, s3_0_c4_c6_0 msr s3_0_c4_c6_0, x0 + + mrs x0, s2_1_c0_c3_0 + msr s2_1_c0_c3_0, x0 diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/tls.s b/binutils-2.25/gas/testsuite/gas/aarch64/tls.s index 1c7025ae..104898f8 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/tls.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/tls.s @@ -1,6 +1,6 @@ /* tls.s Test file for AArch64 TLS relocations. - Copyright 2011, 2012 Free Software Foundation, Inc. + Copyright (C) 2011-2014 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.l b/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.l index b7f713e1..3d2c99e7 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.l +++ b/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.l @@ -43,3 +43,135 @@ [^:]*:16: Info: other valid variant\(s\): [^:]*:16: Info: ldnp d3,d7,\[sp\],#16 [^:]*:16: Info: ldnp q3,q7,\[sp\],#16 +[^:]*:18: Error: operand mismatch -- `suqadd v0.8b,v1.16b' +[^:]*:18: Info: did you mean this\? +[^:]*:18: Info: suqadd v0.8b,v1.8b +[^:]*:18: Info: other valid variant\(s\): +[^:]*:18: Info: suqadd v0.16b,v1.16b +[^:]*:18: Info: suqadd v0.4h,v1.4h +[^:]*:18: Info: suqadd v0.8h,v1.8h +[^:]*:18: Info: suqadd v0.2s,v1.2s +[^:]*:18: Info: suqadd v0.4s,v1.4s +[^:]*:18: Info: suqadd v0.2d,v1.2d +[^:]*:20: Error: operand mismatch -- `ursqrte v2.8b,v3.8b' +[^:]*:20: Info: did you mean this\? +[^:]*:20: Info: ursqrte v2.2s,v3.2s +[^:]*:20: Info: other valid variant\(s\): +[^:]*:20: Info: ursqrte v2.4s,v3.4s +[^:]*:22: Error: operand mismatch -- `rev32 v4.2s,v5.2s' +[^:]*:22: Info: did you mean this\? +[^:]*:22: Info: rev32 v4.8b,v5.8b +[^:]*:22: Info: other valid variant\(s\): +[^:]*:22: Info: rev32 v4.16b,v5.16b +[^:]*:22: Info: rev32 v4.4h,v5.4h +[^:]*:22: Info: rev32 v4.8h,v5.8h +[^:]*:24: Error: operand mismatch -- `frintn v6.8b,v7.8b' +[^:]*:24: Info: did you mean this\? +[^:]*:24: Info: frintn v6.2s,v7.2s +[^:]*:24: Info: other valid variant\(s\): +[^:]*:24: Info: frintn v6.4s,v7.4s +[^:]*:24: Info: frintn v6.2d,v7.2d +[^:]*:26: Error: operand mismatch -- `rev64 v8.2d,v9.2d' +[^:]*:26: Info: did you mean this\? +[^:]*:26: Info: rev64 v8.8b,v9.8b +[^:]*:26: Info: other valid variant\(s\): +[^:]*:26: Info: rev64 v8.16b,v9.16b +[^:]*:26: Info: rev64 v8.4h,v9.4h +[^:]*:26: Info: rev64 v8.8h,v9.8h +[^:]*:26: Info: rev64 v8.2s,v9.2s +[^:]*:26: Info: rev64 v8.4s,v9.4s +[^:]*:28: Error: operand mismatch -- `rev16 v10.2s,v11.2s' +[^:]*:28: Info: did you mean this\? +[^:]*:28: Info: rev16 v10.8b,v11.8b +[^:]*:28: Info: other valid variant\(s\): +[^:]*:28: Info: rev16 v10.16b,v11.16b +[^:]*:30: Error: operand mismatch -- `saddlp v12.8b,v13.8b' +[^:]*:30: Info: did you mean this\? +[^:]*:30: Info: saddlp v12.4h,v13.8b +[^:]*:30: Info: other valid variant\(s\): +[^:]*:30: Info: saddlp v12.8h,v13.16b +[^:]*:30: Info: saddlp v12.2s,v13.4h +[^:]*:30: Info: saddlp v12.4s,v13.8h +[^:]*:30: Info: saddlp v12.1d,v13.2s +[^:]*:30: Info: saddlp v12.2d,v13.4s +[^:]*:32: Error: operand mismatch -- `shll v14.8b,v15.8h,#1' +[^:]*:32: Info: did you mean this\? +[^:]*:32: Info: shll v14.8h,v15.8b,#1 +[^:]*:32: Info: other valid variant\(s\): +[^:]*:32: Info: shll v14.4s,v15.4h,#1 +[^:]*:32: Info: shll v14.2d,v15.2s,#1 +[^:]*:34: Error: operand mismatch -- `shll2 v14.8b,v15.8h,#1' +[^:]*:34: Info: did you mean this\? +[^:]*:34: Info: shll2 v14.4s,v15.8h,#1 +[^:]*:34: Info: other valid variant\(s\): +[^:]*:34: Info: shll2 v14.8h,v15.16b,#1 +[^:]*:34: Info: shll2 v14.2d,v15.4s,#1 +[^:]*:36: Error: operand mismatch -- `fcvtxn v22.8b,v23.8b' +[^:]*:36: Info: did you mean this\? +[^:]*:36: Info: fcvtxn v22.2s,v23.2d +[^:]*:38: Error: operand mismatch -- `fcvtxn2 v24.8b,v25.8b' +[^:]*:38: Info: did you mean this\? +[^:]*:38: Info: fcvtxn2 v24.4s,v25.2d +[^:]*:40: Error: operand mismatch -- `fcvtn v25.4s,v26.4s' +[^:]*:40: Info: did you mean this\? +[^:]*:40: Info: fcvtn v25.4h,v26.4s +[^:]*:40: Info: other valid variant\(s\): +[^:]*:40: Info: fcvtn v25.2s,v26.2d +[^:]*:42: Error: operand mismatch -- `fcvtn2 v27.4s,v28.4s' +[^:]*:42: Info: did you mean this\? +[^:]*:42: Info: fcvtn2 v27.8h,v28.4s +[^:]*:42: Info: other valid variant\(s\): +[^:]*:42: Info: fcvtn2 v27.4s,v28.2d +[^:]*:44: Error: operand mismatch -- `fcvtl v29.8b,v30.8b' +[^:]*:44: Info: did you mean this\? +[^:]*:44: Info: fcvtl v29.4s,v30.4h +[^:]*:44: Info: other valid variant\(s\): +[^:]*:44: Info: fcvtl v29.2d,v30.2s +[^:]*:46: Error: operand mismatch -- `fcvtl2 v1.2d,v2.2d' +[^:]*:46: Info: did you mean this\? +[^:]*:46: Info: fcvtl2 v1.2d,v2.4s +[^:]*:46: Info: other valid variant\(s\): +[^:]*:46: Info: fcvtl2 v1.4s,v2.8h +[^:]*:48: Error: operand mismatch -- `sqadd v16.8b,v17.8h,v18.8h' +[^:]*:48: Info: did you mean this\? +[^:]*:48: Info: sqadd v16.8h,v17.8h,v18.8h +[^:]*:48: Info: other valid variant\(s\): +[^:]*:48: Info: sqadd v16.8b,v17.8b,v18.8b +[^:]*:48: Info: sqadd v16.16b,v17.16b,v18.16b +[^:]*:48: Info: sqadd v16.4h,v17.4h,v18.4h +[^:]*:48: Info: sqadd v16.2s,v17.2s,v18.2s +[^:]*:48: Info: sqadd v16.4s,v17.4s,v18.4s +[^:]*:48: Info: sqadd v16.2d,v17.2d,v18.2d +[^:]*:50: Error: operand mismatch -- `shadd v19.8b,v20.8h,v21.8h' +[^:]*:50: Info: did you mean this\? +[^:]*:50: Info: shadd v19.8h,v20.8h,v21.8h +[^:]*:50: Info: other valid variant\(s\): +[^:]*:50: Info: shadd v19.8b,v20.8b,v21.8b +[^:]*:50: Info: shadd v19.16b,v20.16b,v21.16b +[^:]*:50: Info: shadd v19.4h,v20.4h,v21.4h +[^:]*:50: Info: shadd v19.2s,v20.2s,v21.2s +[^:]*:50: Info: shadd v19.4s,v20.4s,v21.4s +[^:]*:52: Error: operand mismatch -- `sha1su0 v1.16b,v2.16b,v3.16b' +[^:]*:52: Info: did you mean this\? +[^:]*:52: Info: sha1su0 v1.4s,v2.4s,v3.4s +[^:]*:54: Error: operand mismatch -- `shadd v1.2d,v2.2d,v3.2d' +[^:]*:54: Info: did you mean this\? +[^:]*:54: Info: shadd v1.8b,v2.8b,v3.8b +[^:]*:54: Info: other valid variant\(s\): +[^:]*:54: Info: shadd v1.16b,v2.16b,v3.16b +[^:]*:54: Info: shadd v1.4h,v2.4h,v3.4h +[^:]*:54: Info: shadd v1.8h,v2.8h,v3.8h +[^:]*:54: Info: shadd v1.2s,v2.2s,v3.2s +[^:]*:54: Info: shadd v1.4s,v2.4s,v3.4s +[^:]*:56: Error: operand mismatch -- `sqdmulh v1.16b,v2.16b,v3.16b' +[^:]*:56: Info: did you mean this\? +[^:]*:56: Info: sqdmulh v1.4h,v2.4h,v3.4h +[^:]*:56: Info: other valid variant\(s\): +[^:]*:56: Info: sqdmulh v1.8h,v2.8h,v3.8h +[^:]*:56: Info: sqdmulh v1.2s,v2.2s,v3.2s +[^:]*:56: Info: sqdmulh v1.4s,v2.4s,v3.4s +[^:]*:58: Error: operand mismatch -- `sqdmlal2 v1.16b,v2.16b,v3.16b' +[^:]*:58: Info: did you mean this\? +[^:]*:58: Info: sqdmlal2 v1.4s,v2.8h,v3.8h +[^:]*:58: Info: other valid variant\(s\): +[^:]*:58: Info: sqdmlal2 v1.2d,v2.4s,v3.4s diff --git a/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.s b/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.s index 5a2c2f16..a173b77b 100644 --- a/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.s +++ b/binutils-2.25/gas/testsuite/gas/aarch64/verbose-error.s @@ -14,3 +14,45 @@ adds w0, wsp, x0, uxtx #1 fmov d0, s0 ldnp h3, h7, [sp], #16 + # QL_V2SAME + suqadd v0.8b, v1.16b + # QL_V2SAME + ursqrte v2.8b, v3.8b + # QL_V2SAMEBH + rev32 v4.2s, v5.2s + #QL_V2SAMESD + frintn v6.8b, v7.8b + #QL_V2SAMEBHS + rev64 v8.2d, v9.2d + #QL_V2SAMEB + rev16 v10.2s, v11.2s + #QL_V2PAIRWISELONGBHS + saddlp v12.8b, v13.8b + #QL_V2LONGBHS + shll v14.8b, v15.8h, #1 + #QL_V2LONGBHS2 + shll2 v14.8b, v15.8h, #1 + #QL_V2NARRS + fcvtxn v22.8b, v23.8b + #QL_V2NARRS2 + fcvtxn2 v24.8b, v25.8b + #QL_V2NARRHS + fcvtn v25.4s, v26.4s + #QL_V2NARRHS2 + fcvtn2 v27.4s, v28.4s + #QL_V2LONGHS + fcvtl v29.8b, v30.8b + #QL_V2LONGHS2 + fcvtl2 v1.2d, v2.2d + #QL_V3SAME + sqadd v16.8b, v17.8h, v18.8h + #QL_V3SAMEBHS + shadd v19.8b, v20.8h, v21.8h + #QL_V3SAME4S + sha1su0 v1.16b, v2.16b, v3.16b + #QL_V3SAMEEB + shadd v1.2d, v2.2d, v3.2d + #QL_V3SAMEEHS + sqdmulh v1.16b, v2.16b, v3.16b + #QL_V3LONGHS2 + sqdmlal2 v1.16b, v2.16b, v3.16b |