diff options
Diffstat (limited to 'binutils-2.24/cpu')
46 files changed, 0 insertions, 75235 deletions
diff --git a/binutils-2.24/cpu/ChangeLog b/binutils-2.24/cpu/ChangeLog deleted file mode 100644 index e5a83617..00000000 --- a/binutils-2.24/cpu/ChangeLog +++ /dev/null @@ -1,845 +0,0 @@ -2013-03-08 Yann Sionneau <yann.sionneau@gmail.com> - - PR binutils/15241 - * lm32.cpu (Control and status registers): Add CFG2, PSW, - TLBVADDR, TLBPADDR and TLBBADVADDR. - -2012-11-30 Oleg Raikhman <oleg@adapteva.com> - Joern Rennecke <joern.rennecke@embecosm.com> - - * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12. - (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l. - (testset-insn): Add NO_DIS attribute to t.l. - (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l. - (move-insns): Add NO-DIS attribute to cmov.l. - (op-mmr-movts): Add NO-DIS attribute to movts.l. - (op-mmr-movfs): Add NO-DIS attribute to movfs.l. - (op-rrr): Add NO-DIS attribute to .l. - (shift-rrr): Add NO-DIS attribute to .l. - (op-shift-rri): Add NO-DIS attribute to i32.l. - (bitrl, movtl): Add NO-DIS attribute. - (op-iextrrr): Add NO-DIS attribute to .l - (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l. - (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise. - -2012-02-27 Alan Modra <amodra@gmail.com> - - * mt.opc (print_dollarhex): Trim values to 32 bits. - -2011-12-15 Nick Clifton <nickc@redhat.com> - - * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit - hosts. - -2011-10-26 Joern Rennecke <joern.rennecke@embecosm.com> - - * epiphany.opc (parse_branch_addr): Fix type of valuep. - Cast value before printing it as a long. - (parse_postindex): Fix type of valuep. - -2011-10-25 Joern Rennecke <joern.rennecke@embecosm.com> - - * cpu/epiphany.cpu: New file. - * cpu/epiphany.opc: New file. - -2011-08-22 Nick Clifton <nickc@redhat.com> - - * fr30.cpu: Newly contributed file. - * fr30.opc: Likewise. - * ip2k.cpu: Likewise. - * ip2k.opc: Likewise. - * mep-avc.cpu: Likewise. - * mep-avc2.cpu: Likewise. - * mep-c5.cpu: Likewise. - * mep-core.cpu: Likewise. - * mep-default.cpu: Likewise. - * mep-ext-cop.cpu: Likewise. - * mep-fmax.cpu: Likewise. - * mep-h1.cpu: Likewise. - * mep-ivc2.cpu: Likewise. - * mep-rhcop.cpu: Likewise. - * mep-sample-ucidsp.cpu: Likewise. - * mep.cpu: Likewise. - * mep.opc: Likewise. - * openrisc.cpu: Likewise. - * openrisc.opc: Likewise. - * xstormy16.cpu: Likewise. - * xstormy16.opc: Likewise. - -2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr> - - * frv.opc: #undef DEBUG. - -2010-07-03 DJ Delorie <dj@delorie.com> - - * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it. - -2010-02-11 Doug Evans <dje@sebabeach.org> - - * m32r.cpu (HASH-PREFIX): Delete. - (duhpo, dshpo): New pmacros. - (simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo. - (uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX - attribute, define with dshpo. - (uimm24): Delete HASH-PREFIX attribute. - * m32r.opc (CGEN_PRINT_NORMAL): Delete. - (print_signed_with_hash_prefix): New function. - (print_unsigned_with_hash_prefix): New function. - * xc16x.cpu (dowh): New pmacro. - (upof16): Define with dowh, specify print handler. - (qbit, qlobit, qhibit): Ditto. - (upag16): Ditto. - * xc16x.opc (CGEN_PRINT_NORMAL): Delete. - (print_with_dot_prefix): New functions. - (print_with_pof_prefix, print_with_pag_prefix): New functions. - -2010-01-24 Doug Evans <dje@sebabeach.org> - - * frv.cpu (floating-point-conversion): Update call to fp conv op. - (floating-point-dual-conversion, ne-floating-point-dual-conversion, - conditional-floating-point-conversion, ne-floating-point-conversion, - float-parallel-mul-add-double-semantics): Ditto. - -2010-01-05 Doug Evans <dje@sebabeach.org> - - * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler. - (f-dsp-40-u20, f-dsp-40-u24): Ditto. - -2010-01-02 Doug Evans <dje@sebabeach.org> - - * m32c.opc (parse_signed16): Fix typo. - -2009-12-11 Nick Clifton <nickc@redhat.com> - - * frv.opc: Fix shadowed variable warnings. - * m32c.opc: Fix shadowed variable warnings. - -2009-11-14 Doug Evans <dje@sebabeach.org> - - Must use VOID expression in VOID context. - * xc16x.cpu (mov4): Fix mode of `sequence'. - (mov9, mov10): Ditto. - (movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'. - (callr, callseg, calls, trap, rets, reti): Ditto. - (jb, jbc, jnb, jnbs): Fix mode of `if'. Comment out no-op `sll'. - (atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'. - (exts, exts1, extsr, extsr1, prior): Ditto. - -2009-10-23 Doug Evans <dje@sebabeach.org> - - * m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h. - cgen-ops.h -> cgen/basic-ops.h. - -2009-09-25 Alan Modra <amodra@bigpond.net.au> - - * m32r.cpu (stb-plus): Typo fix. - -2009-09-23 Doug Evans <dje@sebabeach.org> - - * m32r.cpu (sth-plus): Fix address mode and calculation. - (stb-plus): Ditto. - (clrpsw): Fix mask calculation. - (bset, bclr, btst): Make mode in bit calculation match expression. - - * xc16x.cpu (rtl-version): Set to 0.8. - (gr-names, ext-names,psw-names): Update, print-name -> enum-prefix, - make uppercase. Remove unnecessary name-prefix spec. - (grb-names, conditioncode-names, extconditioncode-names): Ditto. - (grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto. - (reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto. - (h-cr): New hardware. - (muls): Comment out parts that won't compile, add fixme. - (mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto. - (scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto. - (bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto. - -2009-07-16 Doug Evans <dje@sebabeach.org> - - * cpu/simplify.inc (*): One line doc strings don't need \n. - (df): Invoke define-full-ifield instead of claiming it's an alias. - (dno): Define. - (dnop): Mark as deprecated. - -2009-06-22 Alan Modra <amodra@bigpond.net.au> - - * m32c.opc (parse_lab_5_3): Use correct enum. - -2009-01-07 Hans-Peter Nilsson <hp@axis.com> - - * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI. - (DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros. - (media-arith-sat-semantics): Explicitly sign- or zero-extend - arguments of "operation" to DI using "mode" and the new pmacros. - -2009-01-03 Hans-Peter Nilsson <hp@axis.com> - - * cris.cpu (cris-implemented-writable-specregs-v32): Correct size - of number 2, PID. - -2008-12-23 Jon Beniston <jon@beniston.com> - - * lm32.cpu: New file. - * lm32.opc: New file. - -2008-01-29 Alan Modra <amodra@bigpond.net.au> - - * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change - to source. - -2007-10-22 Hans-Peter Nilsson <hp@axis.com> - - * cris.cpu (movs, movu): Use result of extension operation when - updating flags. - -2007-07-04 Nick Clifton <nickc@redhat.com> - - * cris.cpu: Update copyright notice to refer to GPLv3. - * frv.cpu, frv.opc, iq10.cpu, iq2000m.cpu, iq2000.opc, m32c.cpu, - m32c.opc, m32r.cpu, m32r.opc, mt.cpu, mt.opc, sh64-compact.cpu, - sh64-media.cpu, sh.cpu, sh.opc, simplify.inc, xc16x.cpu, - xc16x.opc: Likewise. - * iq2000.cpu: Fix copyright notice to refer to FSF. - -2007-04-30 Mark Salter <msalter@sadr.localdomain> - - * frv.cpu (spr-names): Support new coprocessor SPR registers. - -2007-04-20 Nick Clifton <nickc@redhat.com> - - * xc16x.cpu: Restore after accidentally overwriting this file with - xc16x.opc. - -2007-03-29 DJ Delorie <dj@redhat.com> - - * m32c.cpu (Imm-8-s4n): Fix print hook. - (Lab-24-8, Lab-32-8, Lab-40-8): Fix. - (arith-jnz-imm4-dst-defn): Make relaxable. - (arith-jnz16-imm4-dst-defn): Fix encodings. - -2007-03-20 DJ Delorie <dj@redhat.com> - - * m32c.cpu (f-dsp-40-u20, f-dsp-48-u20, Dsp-40-u20, Dsp-40-u20, - mem20): New. - (src16-16-20-An-relative-*): New. - (dst16-*-20-An-relative-*): New. - (dst16-16-16sa-*): New - (dst16-16-16ar-*): New - (dst32-16-16sa-Unprefixed-*): New - (jsri): Fix operands. - (setzx): Fix encoding. - -2007-03-08 Alan Modra <amodra@bigpond.net.au> - - * m32r.opc: Formatting. - -2006-05-22 Nick Clifton <nickc@redhat.com> - - * iq2000.cpu: Fix include paths for iq2000m.cpu and iq10.cpu. - -2006-04-10 DJ Delorie <dj@redhat.com> - - * m32c.opc (parse_unsigned_bitbase): Take a new parameter which - decides if this function accepts symbolic constants or not. - (parse_signed_bitbase): Likewise. - (parse_unsigned_bitbase8): Pass the new parameter. - (parse_unsigned_bitbase11): Likewise. - (parse_unsigned_bitbase16): Likewise. - (parse_unsigned_bitbase19): Likewise. - (parse_unsigned_bitbase27): Likewise. - (parse_signed_bitbase8): Likewise. - (parse_signed_bitbase11): Likewise. - (parse_signed_bitbase19): Likewise. - -2006-03-13 DJ Delorie <dj@redhat.com> - - * m32c.cpu (Bit3-S): New. - (btst:s): New. - * m32c.opc (parse_bit3_S): New. - - * m32c.cpu (decimal-subtraction16-insn): Add second operand. - (btst): Add optional :G suffix for MACH32. - (or.b:S): New. - (pop.w:G): Add optional :G suffix for MACH16. - (push.b.imm): Fix syntax. - -2006-03-10 DJ Delorie <dj@redhat.com> - - * m32c.cpu (mul.l): New. - (mulu.l): New. - -2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com) - - * xc16x.opc (parse_hash): Return NULL if the input was parsed or - an error message otherwise. - (parse_dot, parse_pof, parse_pag, parse_sof, parse_seg): Likewise. - Fix up comments to correctly describe the functions. - -2006-02-24 DJ Delorie <dj@redhat.com> - - * m32c.cpu (RL_TYPE): New attribute, with macros. - (Lab-8-24): Add RELAX. - (unary-insn-defn-g, binary-arith-imm-dst-defn, - binary-arith-imm4-dst-defn): Add 1ADDR attribute. - (binary-arith-src-dst-defn): Add 2ADDR attribute. - (jcnd16-5, jcnd16, jcnd32, jmp16.s, jmp16.b, jmp16.w, jmp16.a, - jmp32.s, jmp32.b, jmp32.w, jmp32.a, jsr16.w, jsr16.a): Add JUMP - attribute. - (jsri16, jsri32): Add 1ADDR attribute. - (jsr32.w, jsr32.a): Add JUMP attribute. - -2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com> - Anil Paranjape <anilp1@kpitcummins.com> - Shilin Shakti <shilins@kpitcummins.com> - - * xc16x.cpu: New file containing complete CGEN specific XC16X CPU - description. - * xc16x.opc: New file containing supporting XC16C routines. - -2006-02-10 Nick Clifton <nickc@redhat.com> - - * iq2000.opc (parse_hi16): Truncate shifted values to 16 bits. - -2006-01-06 DJ Delorie <dj@redhat.com> - - * m32c.cpu (mov.w:q): Fix mode. - (push32.b.imm): Likewise, for the comment. - -2005-12-16 Nathan Sidwell <nathan@codesourcery.com> - - Second part of ms1 to mt renaming. - * mt.cpu (define-arch, define-isa): Set name to mt. - (define-mach): Adjust. - * mt.opc (CGEN_ASM_HASH): Update. - (mt_asm_hash, mt_cgen_insn_supported): Renamed. - (parse_loopsize, parse_imm16): Adjust. - -2005-12-13 DJ Delorie <dj@redhat.com> - - * m32c.cpu (jsri): Fix order so register names aren't treated as - symbols. - (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw, - indexwd, indexws): Fix encodings. - -2005-12-12 Nathan Sidwell <nathan@codesourcery.com> - - * mt.cpu: Rename from ms1.cpu. - * mt.opc: Rename from ms1.opc. - -2005-12-06 Hans-Peter Nilsson <hp@axis.com> - - * cris.cpu (simplecris-common-writable-specregs) - (simplecris-common-readable-specregs): Split from - simplecris-common-specregs. All users changed. - (cris-implemented-writable-specregs-v0) - (cris-implemented-readable-specregs-v0): Similar from - cris-implemented-specregs-v0. - (cris-implemented-writable-specregs-v3) - (cris-implemented-readable-specregs-v3) - (cris-implemented-writable-specregs-v8) - (cris-implemented-readable-specregs-v8) - (cris-implemented-writable-specregs-v10) - (cris-implemented-readable-specregs-v10) - (cris-implemented-writable-specregs-v32) - (cris-implemented-readable-specregs-v32): Similar. - (bdap-32-pc, move-m-pcplus-p0, move-m-spplus-p8): New - insns and specializations. - -2005-11-08 Nathan Sidwell <nathan@codesourcery.com> - - Add ms2 - * ms1.cpu (ms2, ms2bf): New architecture variant, cpu, machine and - model. - (f-uu8, f-uu1, f-imm16l, f-loopo, f-cb1sel, f-cb2sel, f-cb1incr, - f-cb2incr, f-rc3): New fields. - (LOOP): New instruction. - (JAL-HAZARD): New hazard. - (imm16o, loopsize, imm16l, rc3, cb1sel, cb2sel, cb1incr, cb2incr): - New operands. - (mul, muli, dbnz, iflush): Enable for ms2 - (jal, reti): Has JAL-HAZARD. - (ldctxt, ldfb, stfb): Only ms1. - (fbcb): Only ms1,ms1-003. - (wfbinc, mefbinc, wfbincr, mwfbincr, fbcbincs, mfbcbincs, - fbcbincrs, mfbcbincrs): Enable for ms2. - (loop, loopu, dfbc, dwfb, fbwfb, dfbr): New ms2 insns. - * ms1.opc (parse_loopsize): New. - (parse_imm16): hi16/lo16 relocs are applicable to IMM16L. - (print_pcrel): New. - -2005-10-28 Dave Brolley <brolley@redhat.com> - - Contribute the following change: - 2003-09-24 Dave Brolley <brolley@redhat.com> - - * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of - CGEN_ATTR_VALUE_TYPE. - * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE. - Use cgen_bitset_intersect_p. - -2005-10-27 DJ Delorie <dj@redhat.com> - - * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New. - (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn, - arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which - imm operand is needed. - (adjnz, sbjnz): Pass the right operands. - (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach, - unary-insn): Add -g variants for opcodes that need to support :G. - (not.BW:G, push.BW:G): Call it. - (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb, - stzx16-imm8-imm8-abs16): Fix operand typos. - * m32c.opc (m32c_asm_hash): Support bnCND. - (parse_signed4n, print_signed4n): New. - -2005-10-26 DJ Delorie <dj@redhat.com> - - * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New. - (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn, - mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn): - dsp8[sp] is signed. - (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff). - (mov.BW:S r0,r1): Fix typo r1l->r1. - (tst): Allow :G suffix. - * m32c.opc (parse_signed24): New, for -0x800000..0xffffff. - -2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * m32r.opc (parse_hi16): Do not assume a 32-bit host word size. - -2005-10-25 DJ Delorie <dj@redhat.com> - - * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by - making one a macro of the other. - -2005-10-21 DJ Delorie <dj@redhat.com> - - * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. - (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, - indexld, indexls): .w variants have `1' bit. - (rot32.b): QI, not SI. - (rot32.w): HI, not SI. - (xchg16): HI for .w variant. - -2005-10-19 Nick Clifton <nickc@redhat.com> - - * m32r.opc (parse_slo16): Fix bad application of previous patch. - -2005-10-18 Andreas Schwab <schwab@suse.de> - - * m32r.opc (parse_slo16): Better version of previous patch. - -2005-10-14 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * cpu/m32r.opc (parse_slo16): Do not assume a 32-bit host word - size. - -2005-07-25 DJ Delorie <dj@redhat.com> - - * m32c.opc (parse_unsigned8): Add %dsp8(). - (parse_signed8): Add %hi8(). - (parse_unsigned16): Add %dsp16(). - (parse_signed16): Add %lo16() and %hi16(). - (parse_lab_5_3): Make valuep a bfd_vma *. - -2005-07-18 Nick Clifton <nickc@redhat.com> - - * m32c.cpu (f-16-8, f-24-8, f-32-16, f-dsp-8-u24): New opcode - components. - (f-lab32-jmp-s): Fix insertion sequence. - (Dsp-8-u24, Lab-5-3, Lab32-jmp-s): New operands. - (Dsp-40-s8): Make parameter be signed. - (Dsp-40-s16): Likewise. - (Dsp-48-s8): Likewise. - (Dsp-48-s16): Likewise. - (Imm-13-u3): Likewise. (Despite its name!) - (BitBase16-16-s8): Make the parameter be unsigned. - (BitBase16-8-u11-S): Likewise. - (Lab-8-8, Lab-8-16, Lab-16-8, jcnd16-5, jcnd16, jcnd32, jmp16.s, - jmp16.b, jmp16.w, jmp32.s, jmp32.b, jmp32.w, jsp16.w, jsr32.w): Allow - relaxation. - - * m32c.opc: Fix formatting. - Use safe-ctype.h instead of ctype.h - Move duplicated code sequences into a macro. - Fix compile time warnings about signedness mismatches. - Remove dead code. - (parse_lab_5_3): New parser function. - -2005-07-16 Jim Blandy <jimb@redhat.com> - - * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET, - to represent isa sets. - -2005-07-15 Jim Blandy <jimb@redhat.com> - - * m32c.cpu, m32c.opc: Fix copyright. - -2005-07-14 Jim Blandy <jimb@redhat.com> - - * m32c.cpu, m32c.opc: Machine description for the Renesas M32C. - -2005-07-14 Alan Modra <amodra@bigpond.net.au> - - * ms1.opc (print_dollarhex): Correct format string. - -2005-07-06 Alan Modra <amodra@bigpond.net.au> - - * iq2000.cpu: Include from binutils cpu dir. - -2005-07-05 Nick Clifton <nickc@redhat.com> - - * iq2000.opc (parse_lo16, parse_mlo16): Make value parameter - unsigned in order to avoid compile time warnings about sign - conflicts. - - * ms1.opc (parse_*): Likewise. - (parse_imm16): Use a "void *" as it is passed both signed and - unsigned arguments. - -2005-07-01 Nick Clifton <nickc@redhat.com> - - * frv.opc: Update to ISO C90 function declaration style. - * iq2000.opc: Likewise. - * m32r.opc: Likewise. - * sh.opc: Likewise. - -2005-06-15 Dave Brolley <brolley@redhat.com> - - Contributed by Red Hat. - * ms1.cpu: New file. Written by Nick Clifton, Stan Cox. - * ms1.opc: New file. Written by Stan Cox. - -2005-05-10 Nick Clifton <nickc@redhat.com> - - * Update the address and phone number of the FSF organization in - the GPL notices in the following files: - cris.cpu, frv.cpu, frv.opc, iq10.cpu, iq2000.opc, iq2000m.cpu, - m32r.cpu, m32r.opc, sh.cpu, sh.opc, sh64-compact.cpu, - sh64-media.cpu, simplify.inc - -2005-02-24 Alan Modra <amodra@bigpond.net.au> - - * frv.opc (parse_A): Warning fix. - -2005-02-23 Nick Clifton <nickc@redhat.com> - - * frv.opc: Fixed compile time warnings about differing signed'ness - of pointers passed to functions. - * m32r.opc: Likewise. - -2005-02-11 Nick Clifton <nickc@redhat.com> - - * iq2000.opc (parse_jtargq10): Change type of valuep argument to - 'bfd_vma *' in order avoid compile time warning message. - -2005-01-28 Hans-Peter Nilsson <hp@axis.com> - - * cris.cpu (mstep): Add missing insn. - -2005-01-25 Alexandre Oliva <aoliva@redhat.com> - - 2004-11-10 Alexandre Oliva <aoliva@redhat.com> - * frv.cpu: Add support for TLS annotations in loads and calll. - * frv.opc (parse_symbolic_address): New. - (parse_ldd_annotation): New. - (parse_call_annotation): New. - (parse_ld_annotation): New. - (parse_ulo16, parse_uslo16): Use parse_symbolic_address. - Introduce TLS relocations. - (parse_d12, parse_s12, parse_u12): Likewise. - (parse_uhi16): Likewise. Fix constant checking on 64-bit host. - (parse_call_label, print_at): New. - -2004-12-21 Mikael Starvik <starvik@axis.com> - - * cris.cpu (cris-set-mem): Correct integral write semantics. - -2004-11-29 Hans-Peter Nilsson <hp@axis.com> - - * cris.cpu: New file. - -2004-11-15 Michael K. Lechner <mike.lechner@gmail.com> - - * iq2000.cpu: Added quotes around macro arguments so that they - will work with newer versions of guile. - -2004-10-27 Nick Clifton <nickc@redhat.com> - - * iq2000m.cpu (pkrlr1, pkrlr30, rbr1, rbr30, rxr1, rxr30, wbr1, - wbr1u, wbr30, wbr30u, wxr1, wxr1u, wxr30, wxr30u): Add an index - operand. - * iq2000.cpu (dnop index): Rename to _index to avoid complications - with guile. - -2004-08-27 Richard Sandiford <rsandifo@redhat.com> - - * frv.cpu (cfmovs): Change UNIT attribute to FMALL. - -2004-05-15 Nick Clifton <nickc@redhat.com> - - * iq2000.opc (iq2000_cgen_insn_supported): Make 'insn' argument const. - -2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * m32r.opc (parse_hi16): Fixed shigh(0xffff8000) bug. - -2004-03-01 Richard Sandiford <rsandifo@redhat.com> - - * frv.cpu (define-arch frv): Add fr450 mach. - (define-mach fr450): New. - (define-model fr450): New. Add profile units to every fr450 insn. - (define-attr UNIT): Add MDCUTSSI. - (define-attr FR450-MAJOR): New enum. Add to every fr450 insn. - (define-attr AUDIO): New boolean. - (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL) - (f-LRA-null, f-TLBPR-null): New fields. - (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr) - (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs. - (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands. - (LRA-null, TLBPR-null): New macros. - (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr. - (load-real-address): New macro. - (lrai, lrad, tlbpr): New instructions. - (media-cut-acc, media-cut-acc-ss): Add fr450-major argument. - (mcut, mcuti, mcutss, mcutssi): Adjust accordingly. - (mdcutssi): Change UNIT attribute to MDCUTSSI. - (media-low-clear-semantics, media-scope-limit-semantics) - (media-quad-limit, media-quad-shift): New macros. - (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions. - * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major) - (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn) - (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450. - (fr450_unit_mapping): New array. - (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry - for new MDCUTSSI unit. - (fr450_check_insn_major_constraints): New function. - (check_insn_major_constraints): Use it. - -2004-03-01 Richard Sandiford <rsandifo@redhat.com> - - * frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit. - (scutss): Change unit to I0. - (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit. - (mqsaths): Fix FR400-MAJOR categorization. - (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc) - (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL. - * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1) - combinations. - -2004-03-01 Richard Sandiford <rsandifo@redhat.com> - - * frv.cpu (r-store, r-store-dual, r-store-quad): Delete. - (rstb, rsth, rst, rstd, rstq): Delete. - (rstbf, rsthf, rstf, rstdf, rstqf): Delete. - -2004-02-23 Nick Clifton <nickc@redhat.com> - - * Apply these patches from Renesas: - - 2004-02-10 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * cpu/m32r.opc (my_print_insn): Fixed incorrect output when - disassembling codes for 0x*2 addresses. - - 2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * cpu/m32r.cpu: Add PIPE_O attribute to "pop" instruction. - - 2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> - - * cpu/m32r.cpu : Add new model m32r2. - Add new instructions. - Replace occurrances of 'Mitsubishi' with 'Renesas'. - Changed PIPE attr of push from O to OS. - Care for Little-endian of M32R. - * cpu/m32r.opc (CGEN_DIS_HASH, my_print_insn): - Care for Little-endian of M32R. - (parse_slo16): signed extension for value. - -2004-02-20 Andrew Cagney <cagney@redhat.com> - - * m32r.opc, m32r.cpu: New files. Written by , Doug Evans, Nick - Clifton, Ben Elliston, Matthew Green, and Andrew Haley. - - * sh.cpu, sh.opc, sh64-compact.cpu, sh64-media.cpu: New files, all - written by Ben Elliston. - -2004-01-14 Richard Sandiford <rsandifo@redhat.com> - - * frv.cpu (UNIT): Add IACC. - (iacc-multiply-r-r): Use it. - * frv.opc (fr400_unit_mapping): Add entry for IACC. - (fr500_unit_mapping, fr550_unit_mapping): Likewise. - -2004-01-06 Alexandre Oliva <aoliva@redhat.com> - - 2003-12-19 Alexandre Oliva <aoliva@redhat.com> - * frv.opc (parse_ulo16, parse_uhi16, parse_d12): Fix some - cut&paste errors in shifting/truncating numerical operands. - 2003-08-08 Alexandre Oliva <aoliva@redhat.com> - * frv.opc (parse_ulo16): Parse gotofflo and gotofffuncdesclo. - (parse_uslo16): Likewise. - (parse_uhi16): Parse gotoffhi and gotofffuncdeschi. - (parse_d12): Parse gotoff12 and gotofffuncdesc12. - (parse_s12): Likewise. - 2003-08-04 Alexandre Oliva <aoliva@redhat.com> - * frv.opc (parse_ulo16): Parse gotlo and gotfuncdesclo. - (parse_uslo16): Likewise. - (parse_uhi16): Parse gothi and gotfuncdeschi. - (parse_d12): Parse got12 and gotfuncdesc12. - (parse_s12): Likewise. - -2003-10-10 Dave Brolley <brolley@redhat.com> - - * frv.cpu (dnpmop): New p-macro. - (GRdoublek): Use dnpmop. - (CPRdoublek, FRdoublei, FRdoublej, FRdoublek): Ditto. - (store-double-r-r): Use (.sym regtype doublek). - (r-store-double): Ditto. - (store-double-r-r-u): Ditto. - (conditional-store-double): Ditto. - (conditional-store-double-u): Ditto. - (store-double-r-simm): Ditto. - (fmovs): Assign to UNIT FMALL. - -2003-10-06 Dave Brolley <brolley@redhat.com> - - * frv.cpu, frv.opc: Add support for fr550. - -2003-09-24 Dave Brolley <brolley@redhat.com> - - * frv.cpu (u-commit): New modelling unit for fr500. - (mwtaccg): Use frv_ref_SI to reference ACC40Sk as an input operand. - (commit-r): Use u-commit model for fr500. - (commit): Ditto. - (conditional-float-binary-op): Take profiling data as an argument. - Update callers. - (ne-float-binary-op): Ditto. - -2003-09-19 Michael Snyder <msnyder@redhat.com> - - * frv.cpu (nldqi): Delete unimplemented instruction. - -2003-09-12 Dave Brolley <brolley@redhat.com> - - * frv.cpu (u-clrgr, u-clrfr): New units of model fr500. - (clear-ne-flag-r): Pass insn profiling in as an argument. Call - frv_ref_SI to get input register referenced for profiling. - (clear-ne-flag-all): Pass insn profiling in as an argument. - (clrgr,clrfr,clrga,clrfa): Add profiling information. - -2003-09-11 Michael Snyder <msnyder@redhat.com> - - * frv.cpu: Typographical corrections. - -2003-09-09 Dave Brolley <brolley@redhat.com> - - * frv.cpu (media-dual-complex): Change UNIT to FMALL. - (conditional-media-dual-complex, media-quad-complex): Likewise. - -2003-09-04 Dave Brolley <brolley@redhat.com> - - * frv.cpu (register-transfer): Pass in all attributes in on argument. - Update all callers. - (conditional-register-transfer): Ditto. - (cache-preload): Ditto. - (floating-point-conversion): Ditto. - (floating-point-neg): Ditto. - (float-abs): Ditto. - (float-binary-op-s): Ditto. - (conditional-float-binary-op): Ditto. - (ne-float-binary-op): Ditto. - (float-dual-arith): Ditto. - (ne-float-dual-arith): Ditto. - -2003-09-03 Dave Brolley <brolley@redhat.com> - - * frv.opc (parse_A, parse_A0, parse_A1): New parse handlers. - * frv.cpu (UNIT): Add IALL, FMALL, FMLOW, STORE, SCAN, DCPL, MDUALACC, - MCLRACC-1. - (A): Removed operand. - (A0,A1): New operands replace operand A. - (mnop): Now a real insn - (mclracc): Removed insn. - (mclracc-0, mclracc-1): New insns replace mclracc. - (all insns): Use new UNIT attributes. - -2003-08-21 Nick Clifton <nickc@redhat.com> - - * frv.cpu (mbtoh): Replace input parameter to u-media-dual-expand - and u-media-dual-btoh with output parameter. - (cmbtoh): Add profiling hack. - -2003-08-19 Michael Snyder <msnyder@redhat.com> - - * frv.cpu: Fix typo, Frintkeven -> FRintkeven - -2003-06-10 Doug Evans <dje@sebabeach.org> - - * frv.cpu: Add IDOC attribute. - -2003-06-06 Andrew Cagney <cagney@redhat.com> - - Contributed by Red Hat. - * iq2000.cpu: New file. Written by Ben Elliston, Jeff Johnston, - Stan Cox, and Frank Ch. Eigler. - * iq2000.opc: New file. Written by Ben Elliston, Frank - Ch. Eigler, Chris Moller, Jeff Johnston, and Stan Cox. - * iq2000m.cpu: New file. Written by Jeff Johnston. - * iq10.cpu: New file. Written by Jeff Johnston. - -2003-06-05 Nick Clifton <nickc@redhat.com> - - * frv.cpu (FRintieven): New operand. An even-numbered only - version of the FRinti operand. - (FRintjeven): Likewise for FRintj. - (FRintkeven): Likewise for FRintk. - (mdcutssi, media-dual-word-rotate-r-r, mqsaths, - media-quad-arith-sat-semantics, media-quad-arith-sat, - conditional-media-quad-arith-sat, mdunpackh, - media-quad-multiply-semantics, media-quad-multiply, - conditional-media-quad-multiply, media-quad-complex-i, - media-quad-multiply-acc-semantics, media-quad-multiply-acc, - conditional-media-quad-multiply-acc, munpackh, - media-quad-multiply-cross-acc-semantics, mdpackh, - media-quad-multiply-cross-acc, mbtoh-semantics, - media-quad-cross-multiply-cross-acc-semantics, - media-quad-cross-multiply-cross-acc, mbtoh, mhtob-semantics, - media-quad-cross-multiply-acc-semantics, cmbtoh, - media-quad-cross-multiply-acc, media-quad-complex, mhtob, - media-expand-halfword-to-double-semantics, mexpdhd, cmexpdhd, - cmhtob): Use new operands. - * frv.opc (CGEN_VERBOSE_ASSEMBLER_ERRORS): Define. - (parse_even_register): New function. - -2003-06-03 Nick Clifton <nickc@redhat.com> - - * frv.cpu (media-dual-word-rotate-r-r): Use a signed 6-bit - immediate value not unsigned. - -2003-06-03 Andrew Cagney <cagney@redhat.com> - - Contributed by Red Hat. - * frv.cpu: New file. Written by Dave Brolley, Catherine Moore, - and Eric Christopher. - * frv.opc: New file. Written by Catherine Moore, and Dave - Brolley. - * simplify.inc: New file. Written by Doug Evans. - -2003-05-02 Andrew Cagney <cagney@redhat.com> - - * New file. - - -Copyright (C) 2003-2012 Free Software Foundation, Inc. - -Copying and distribution of this file, with or without modification, -are permitted in any medium without royalty provided the copyright -notice and this notice are preserved. - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/binutils-2.24/cpu/cris.cpu b/binutils-2.24/cpu/cris.cpu deleted file mode 100644 index 97b44581..00000000 --- a/binutils-2.24/cpu/cris.cpu +++ /dev/null @@ -1,4553 +0,0 @@ -; CRIS CPU description. -*- Scheme -*- -; -; Copyright 2003, 2004, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Axis Communications AB. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -;;;;;;;;;;;;;;;;;; -pmacro (generic ones) - -(define-pmacro (.car2 l) (.apply (.pmacro (a b) a) l)) -(define-pmacro (.cadr2 l) (.apply (.pmacro (a b) b) l)) -(define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x) -(define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x)) -(define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x)) -(define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x) -(define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x)) -(define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x)) -(define-pmacro - (define-pmacro-map x) - "On a list ((x0 y0) .. (xN yN)), 0 <= m <= N, (define-pmacro xm ym)" - (.splice - begin - (.unsplice - (.map - (.pmacro (l) (.apply (.pmacro (xm ym) (define-pmacro xm ym)) l)) x))) -) - -;;;;;;;;;;;;;;;;;; -arch -isa -cpu -model - -(define-arch - (name cris) - (comment "Axis Communications CRIS") - (default-alignment unaligned) - (insn-lsb0? #t) - (machs crisv0 crisv3 crisv8 crisv10 crisv32) - (isas cris) -) - -(define-isa - (name cris) - (base-insn-bitsize 16) - (liw-insns 1) - (parallel-insns 1) -) - -(define-pmacro - (define-cpu-cris x-suffix x-comment) - "Define a CRIS CPU family" - (define-cpu - (name (.sym cris x-suffix f)) - (comment x-comment) - (endian little) - ; CGEN-FIXME: Should be deduced from the default? - (word-bitsize 32) - (file-transform (.str x-suffix)) - ) -) - -; Useful when there's a need to iterate over all models. -(define-pmacro (cris-cpu-model-numbers) - "List of CRIS CPU model numbers (version register contents)" - (0 3 8 10 32) -) - -(define-pmacro (cris-cpu-models) - "List of CRIS CPU model names" - (.map (.pmacro (n) (.sym v n)) (cris-cpu-model-numbers)) -) - -; Mapping from model name to number. -(define-pmacro-map - (.map (.pmacro (n) ((.sym v n -number) n)) - (cris-cpu-model-numbers))) - -; FIXME: Rationalize these rules. -; CPU names must be distinct from the architecture name and machine names. -; The "b" suffix stands for "base" and is the convention. -; The "f" suffix stands for "family" and is the convention. -; We ignore the "b" convention, partly because v0 isn't really a "base", at -; least not for some aspects of v32. -(define-cpu-cris v0 "CRIS base family") -(define-cpu-cris v3 "CRIS v3 family") -(define-cpu-cris v8 "CRIS v8 family") -(define-cpu-cris v10 "CRIS v10 family") -(define-cpu-cris v32 "CRIS v32 family") - -(define-pmacro MACH-PRE-V32 (MACH crisv0,crisv3,crisv8,crisv10)) -(define-pmacro MACH-V3-UP (MACH crisv3,crisv8,crisv10,crisv32)) -(define-pmacro MACH-V32 (MACH crisv32)) -(define-pmacro MACH-PC MACH-PRE-V32) -(define-pmacro MACH-ACR MACH-V32) -(define-pmacro MACH-BRANCH-OFFSET-AT-INSN MACH-V32) -(define-pmacro MACH-BRANCH-OFFSET-AFTER-INSN MACH-PRE-V32) - -(define-pmacro - current-mach-is-v32 - "Whether the generated code is for V32. See comment at h-v32." - (reg h-v32) -) - -(define-pmacro (define-mach-cris x-suffix x-comment x-name) - "Define a CRIS mach" - (define-mach - (name (.sym cris x-suffix)) - ; They're all called "cris" in bfd. Watch out for breakages for some - ; uses. - (bfd-name x-name) - (comment x-comment) - (cpu (.sym cris x-suffix f))) -) - -(define-mach-cris v0 "Generic CRIS v0 CPU, ETRAX 1 .. 3" "cris") -(define-mach-cris v3 "Generic CRIS v3 CPU, ETRAX 4" "cris") -(define-mach-cris v8 "Generic CRIS v8 CPU, ETRAX 100" "cris") -(define-mach-cris v10 "Generic CRIS v10 CPU, ETRAX 100 LX" "cris") -(define-mach-cris v32 "Generic CRIS v32 CPU, ETRAX FS" "crisv32") - -(define-pmacro (define-model-simplecris x-name x-comment) - "Define a simple CRIS model" - (define-model - (name (.sym cris x-name)) - (comment x-comment) - (mach (.sym cris x-name)) - - (unit u-exec "Execution Unit" () 1 1 () () () ()) - (unit u-mem "Memory Unit" () 1 1 () () () ()) - - (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) - (unit u-const32 "Fetch 32-bit operand" () 1 1 - () () () ()) - ; Used in special-case insn, for example arithmetic with PC destination. - (unit u-stall "Stall unit" () 1 1 () () () ()) - (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) - (unit u-multiply "Multiply Unit" () 1 1 ((MACH crisv10)) () () ()) - (unit u-movem "Movem Unit" () 1 1 () - ((Rd INT -1)) - () ())) -) - -(define-model-simplecris v0 "Model of CRIS v0, ETRAX 1 .. 3") -(define-model-simplecris v3 "Model of CRIS v3, ETRAX 4") -(define-model-simplecris v8 "Model of CRIS v8, ETRAX 100") -(define-model-simplecris v10 "Model of CRIS v10, ETRAX 100 LX") - -; For some reason, we get an error: -; Generating arch.h ... -; ERROR: In procedure vector-ref: -; ERROR: Wrong type argument in position 1: () -; if we include timings for machs that we don't generate sims for. -; Last checked: CVS as of 2004-11-18. -; CGEN-FIXME: Looks like another CGEN bug. When it's fixed (or when -; generating sims for v0, v3 or v8), add 0, 3 and 8 to -; simplecris-timing-models. But before that, simplecris-timing-x has to -; be rewritten to work on a multiple-element-list, not assume a single -; element. (A change which seems likely to depend on lexical scoping for -; macros to be introduced: try the obvious implementation.) -(define-pmacro simplecris-timing-models (10)) -(define-pmacro (simplecris-common-timing x-units) - "Make timing models, using x-units for all simplecris-timing-models" - ; CGEN-FIXME: Another CGEN bug: the part (.unsplice (10)) will remain - ; unexpanded in (.sym crisv (.unsplice (10)) if we write this as - ; ((.splice (.sym crisv (.unsplice simplecris-timing-models)) - ; (.unsplice x-units))) - ((.splice (.sym crisv (.apply (.pmacro (x) x) simplecris-timing-models)) - (.unsplice x-units))) -) - -(define-pmacro-map - ( - ; Timing for memory instructions running on a simple cris model. - ((simplecris-mem-timing) (simplecris-common-timing - ((unit u-mem) (unit u-exec)))) - ; Timing for movem instructions running on a simple cris model. - ((simplecris-movem-timing) (simplecris-common-timing - ((unit u-movem) (unit u-exec)))) - ; Similar, for an 8- or 16-bit constant ([PC+]) operand. - ((simplecris-const-timing-HI) - (simplecris-common-timing - ((unit u-const16) (unit u-exec)))) - ; Similar, for a 32-bit constant ([PC+]) operand. - ((simplecris-const-timing-SI) - (simplecris-common-timing - ((unit u-const32) (unit u-exec)))) - ; Similar, no particular operand. - ((simplecris-timing) (simplecris-common-timing - ((unit u-exec))))) -) - -(define-model - (name crisv32) - (comment "Model of CRISv32") - (mach crisv32) - - (state - ; Bitmask of h-gr register (0..15) and h-sr register (17..31) - ; modified by 3rd previous insn, updated by the u-exec unit. - ; Because there's no need to mark writes to special registers BZ and - ; WZ, bit 16 is for jump mark and bit 20 for memory-write mark. - (prev-prev-prev-modf-regs UINT) - - ; Ditto for the 2nd previous insn. - (prev-prev-modf-regs UINT) - - ; Ditto for the previous insn. - (prev-modf-regs UINT) - - ; Bit-mask for regs modified by the current insn, propagated to - ; prev-modf-regs. - (modf-regs UINT) - - ; Registers loaded by movem are not forwarded to the execution - ; stage, so we need to insert stall-cycles for ordinary insns - ; accessing such registers. In addition to the *modf-regs - ; above, these are set to tell *ordinary* insns which registers - ; are inaccessible. - - (prev-prev-prev-movem-dest-regs UINT) - - ; Ditto for the 2nd previous insn. - (prev-prev-movem-dest-regs UINT) - - ; Ditto for the previous insn. - (prev-movem-dest-regs UINT) - - ; Bit-mask for regs modified by the current insn, propagated to - ; prev-movem-dest-regs. - (movem-dest-regs UINT)) - - ; It seems this pipeline description isn't used at all; this is just - ; for show. - ; Noteworthy is the placement of the memory stage before the execute stage. - (pipeline all "" () ((fetch) (decode) (memory) (execute) (writeback))) - - ; Units that contribute only a constant pipeline delay are not included. - (unit u-mem "Memory Unit" () 1 1 () - ((Rs INT -1)) - () ()) - - ; Artificial units for read/write-related hazard accounting. - (unit u-mem-r "Memory Unit Read" () 1 1 () () () ()) - (unit u-mem-w "Memory Unit Write" () 1 1 () () () ()) - - (unit u-movem-rtom "Movem-to-memory Unit" () 1 1 () - ((Rs INT -1) (Rd INT -1)) - () ()) - (unit u-movem-mtor "Movem-to-register Unit" () 1 1 () - ((Rs INT -1) (Rd INT -1)) - () ()) - (unit u-multiply "Multiply Unit" () 1 1 () - ((Rs INT -1) (Rd INT -1)) - () ()) - (unit u-branch "Branch Unit" () 1 1 () - () - () ()) - (unit u-jump-r "Jump-to-register Unit" () 1 1 () - ((Rs INT -1)) - () ()) - (unit u-jump-sr "Jump-to-special-register Unit" () 1 1 () - ((Ps INT -1)) - () ()) - (unit u-jump "JAS/BAS Unit, saving PC" () 1 1 () - () - ((Pd INT -1)) ()) - - ; To keep track of PC; not really functional units. - (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) - (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ()) - (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) - - ; For v32, we need to keep track of inputs (for movem destination - ; cycle penalties) and output (for e.g. memory source and jump - ; source cycle penalties). - (unit u-exec "Execution Unit" () 1 1 () - ((Rd INT -1) (Rs INT -1)) - ((Rd INT -1)) - ()) - - ; Special case of u-exec for movem: don't treat Rd as an incoming - ; parameter. - (unit u-exec-movem "Execution Unit" () 1 1 () - ((Rs INT -1)) - ((Rd INT -1)) - ()) - - ; Special case of u-exec when the destination is a special - ; register. - (unit u-exec-to-sr "Execution Unit" () 1 1 () - ((Rs INT -1)) - ((Pd INT -1)) ()) -) - -(define-pmacro (crisv32-timing-destreg d) - "Timing for instructions running on a crisv32 model" - ((crisv32 - (.splice unit u-exec (.unsplice d)))) -) -(define-pmacro (crisv32-timing) (crisv32-timing-destreg ())) - -(define-pmacro (cris-timing-Rd-sfield) - (crisv32-timing-destreg ((out Rd Rd-sfield))) -) - -(define-pmacro (crisv32-timing-c-HI) - ((crisv32 (unit u-const16) (unit u-exec))) -) - -(define-pmacro-map - ((crisv32-timing-c-QI crisv32-timing-c-HI) - ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec)))) - ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr)))) - ((crisv32-reg-sr-timing) ((crisv32 (unit u-exec-to-sr)))) - ((crisv32-mem-sr-timing) - ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec-to-sr)))) - ((crisv32-mem-timing) ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec)))) - ((crisv32-mem-write-timing) ((crisv32 (unit u-mem) (unit u-exec) (unit u-mem-w))))) -) - -(define-pmacro-map - ( - ; Timing for instructions using memory operands. - ((cris-mem-timing) (.splice (.unsplice (simplecris-mem-timing)) - (.unsplice (crisv32-mem-timing)))) - ; Timing for instructions using memory operands. - ((cris-mem-write-timing) (.splice - (.unsplice (simplecris-mem-timing)) - (.unsplice (crisv32-mem-write-timing)))) - ; Timing for moves from general register to special register. - ((cris-reg-sr-timing) (.splice (.unsplice (simplecris-timing)) - (.unsplice (crisv32-reg-sr-timing)))) - ; Timing for moves from memory to special register. - ((cris-mem-sr-timing) (.splice (.unsplice (simplecris-mem-timing)) - (.unsplice (crisv32-mem-sr-timing)))) - ; Timing for non-mul, non-memory, non-special-register, 16-bit instructions. - ((cris-timing) (.splice (.unsplice (simplecris-timing)) - (.unsplice (crisv32-timing)))) - ; Timing for instructions with 8- or 16-bit constant operand ([PC+]). - ((cris-timing-const-HI) (.splice - (.unsplice (simplecris-const-timing-HI)) - (.unsplice (crisv32-timing-c-HI)))) - ; Timing for instructions with a 32-bit constant operand ([PC+]). - ((cris-timing-const-SI) (.splice - (.unsplice (simplecris-const-timing-SI)) - (.unsplice (crisv32-timing-c-SI)))) - ; Like cris-timing-const-SI, but destination special register. - ((cris-timing-const-sr-SI) (.splice - (.unsplice (simplecris-const-timing-SI)) - (.unsplice (crisv32-timing-c-sr-SI)))) - ; Like cris-timing-const-HI, but destination special register. - ((cris-timing-const-sr-HI) (.splice - (.unsplice (simplecris-const-timing-HI)) - (.unsplice (crisv32-timing-c-sr-SI))))) -) - -(define-pmacro cris-timing-const-QI cris-timing-const-HI) -(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI) - -(define-pmacro (simplecris-common-writable-specregs) - "The common writable special registers in pre-v32 models." - ((HI 5) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13)) -) - -(define-pmacro (simplecris-common-readable-specregs) - "The common readable special registers in pre-v32 models." - (.splice (.unsplice (simplecris-common-writable-specregs)) - (QI 0) (QI 1) (HI 4) (SI 8)) -) - -(define-pmacro (cris-implemented-writable-specregs-v0) - "Special writable registers in v0 and their sizes" - (.splice (.unsplice (simplecris-common-writable-specregs)) (HI 6) (HI 7)) -) -(define-pmacro - cris-implemented-specregs-const-v0 - cris-implemented-writable-specregs-v0 -) -(define-pmacro (cris-implemented-readable-specregs-v0) - "Special readable registers in v0 and their sizes" - (.splice (.unsplice (simplecris-common-readable-specregs)) (HI 6) (HI 7)) -) - -(define-pmacro (cris-implemented-writable-specregs-v3) - "Special writable registers in v3 and their sizes" - (.splice (.unsplice (cris-implemented-writable-specregs-v0)) (SI 14)) -) -(define-pmacro - cris-implemented-specregs-const-v3 - cris-implemented-writable-specregs-v3 -) -(define-pmacro (cris-implemented-readable-specregs-v3) - "Special readable registers in v3 and their sizes" - (.splice (.unsplice (cris-implemented-readable-specregs-v0)) (SI 14)) -) - -(define-pmacro (cris-implemented-writable-specregs-v8) - "Special writable registers in v8 and their sizes" - (.splice (.unsplice (simplecris-common-writable-specregs)) (SI 14)) -) -(define-pmacro - cris-implemented-specregs-const-v8 - cris-implemented-writable-specregs-v8 -) -(define-pmacro (cris-implemented-readable-specregs-v8) - "Special readable registers in v8 and their sizes" - (.splice (.unsplice (simplecris-common-readable-specregs)) (SI 14)) -) - -(define-pmacro (cris-implemented-writable-specregs-v10) - "Special writable registers in v10 and their sizes" - (.splice (.unsplice (simplecris-common-writable-specregs)) - (SI 7) (SI 14) (SI 15)) -) -(define-pmacro - cris-implemented-specregs-const-v10 - cris-implemented-writable-specregs-v10 -) -(define-pmacro (cris-implemented-readable-specregs-v10) - "Special registers in v10 and their sizes" - (.splice (.unsplice (simplecris-common-readable-specregs)) - (SI 7) (SI 14) (SI 15)) -) - -(define-pmacro (cris-implemented-writable-specregs-v32) - "Special writable registers in v32 and their sizes" - ((SI 2) (QI 3) - (SI 5) (SI 6) (SI 7) (SI 9) - (SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15)) -) -(define-pmacro (cris-implemented-readable-specregs-v32) - "Special readable registers in v32 and their sizes" - (.splice (.unsplice (cris-implemented-writable-specregs-v32)) - (QI 0) (QI 1) (HI 4) (SI 8)) -) - -; For v32, all special register operations on constants (that is, -; move) take 32-bit operands, not the real size of the register, as in -; other move operations. -(define-pmacro (cris-implemented-specregs-const-v32) - (.map (.pmacro (x) (SI (.cadr2 x))) - (cris-implemented-writable-specregs-v32)) -) - -(define-pmacro cris-swap-codes - "CRIS Swap codes in numeric order (no zero)" - ( r b br w wr wb wbr - n nr nb nbr nw nwr nwb nwbr) -) - -(define-pmacro cris-flagnames - "CRIS flag field values, dest and src fields concatenated" - (c v z n x i u p) ; ... b m for pre-v32 -) - -(define-pmacro-map - ; Bitnumber for each respective flag. - (.map (.pmacro (x num) ((.sym x -bitnumber) num)) - cris-flagnames (.iota 8)) -) - -; I give up. Here's a perl-script to get the values I want for this macro -; (not working along list principles, though). You can run this region. -; perl -e '$x = "cvznxiup"; for ($i = 0; $i < 256; $i++) { $s = ""; -; for ($j = 0; $j < 8; $j++) { if ($i & (1 << $j)) { -; $s .= substr ($x, $j, 1);}} -; printf ("%s%s", $s eq "" ? "_" : $s, (($i + 1) % 8) == 0 ? "\n " : " "); }' -(define-pmacro cris-flag-combinations - "Combinations of flags in numeric order" - (_ c v cv z cz vz cvz - n cn vn cvn zn czn vzn cvzn - x cx vx cvx zx czx vzx cvzx - nx cnx vnx cvnx znx cznx vznx cvznx - i ci vi cvi zi czi vzi cvzi - ni cni vni cvni zni czni vzni cvzni - xi cxi vxi cvxi zxi czxi vzxi cvzxi - nxi cnxi vnxi cvnxi znxi cznxi vznxi cvznxi - u cu vu cvu zu czu vzu cvzu - nu cnu vnu cvnu znu cznu vznu cvznu - xu cxu vxu cvxu zxu czxu vzxu cvzxu - nxu cnxu vnxu cvnxu znxu cznxu vznxu cvznxu - iu ciu viu cviu ziu cziu vziu cvziu - niu cniu vniu cvniu zniu czniu vzniu cvzniu - xiu cxiu vxiu cvxiu zxiu czxiu vzxiu cvzxiu - nxiu cnxiu vnxiu cvnxiu znxiu cznxiu vznxiu cvznxiu - p cp vp cvp zp czp vzp cvzp - np cnp vnp cvnp znp cznp vznp cvznp - xp cxp vxp cvxp zxp czxp vzxp cvzxp - nxp cnxp vnxp cvnxp znxp cznxp vznxp cvznxp - ip cip vip cvip zip czip vzip cvzip - nip cnip vnip cvnip znip cznip vznip cvznip - xip cxip vxip cvxip zxip czxip vzxip cvzxip - nxip cnxip vnxip cvnxip znxip cznxip vznxip cvznxip - up cup vup cvup zup czup vzup cvzup - nup cnup vnup cvnup znup cznup vznup cvznup - xup cxup vxup cvxup zxup czxup vzxup cvzxup - nxup cnxup vnxup cvnxup znxup cznxup vznxup cvznxup - iup ciup viup cviup ziup cziup vziup cvziup - niup cniup vniup cvniup zniup czniup vzniup cvzniup - xiup cxiup vxiup cvxiup zxiup czxiup vzxiup cvzxiup - nxiup cnxiup vnxiup cvnxiup znxiup cznxiup vznxiup cvznxiup - ) -) - -(define-pmacro cc-condition (not cbit)) -(define-pmacro cs-condition cbit) -(define-pmacro ne-condition (not zbit)) -(define-pmacro eq-condition zbit) -(define-pmacro vc-condition (not vbit)) -(define-pmacro vs-condition vbit) -(define-pmacro pl-condition (not nbit)) -(define-pmacro mi-condition nbit) -(define-pmacro ls-condition (or cbit zbit)) -(define-pmacro hi-condition (not (or cbit zbit))) -(define-pmacro ge-condition (not (xor vbit nbit))) -(define-pmacro lt-condition (xor vbit nbit)) -(define-pmacro gt-condition (not (or (xor vbit nbit) zbit))) -(define-pmacro le-condition (or (xor vbit nbit) zbit)) -(define-pmacro a-condition 1) - -; FIXME: define this properly for v10 and pre-v10. -(define-pmacro wf-condition pbit) - -(define-pmacro (cris-condition condno) - "Return condition state for condition number CONDNO" - (sequence - BI - ((SI tmpcond) (BI condres)) - (set tmpcond condno) - (.splice - cond - (.unsplice - (.map - (.pmacro - (condn condc) - ((eq tmpcond condn) (set condres (.sym condc -condition)))) - (.iota 16) - cris-condition-codes))) - condres) -) - -;;;;;;;;;;;;;;;;;; -keyword - -; General registers. -(define-pmacro (cris-general-gregs) - (.splice (SP 14) (.unsplice (.map (.pmacro (n) ((.sym R n) n)) (.iota 15)))) -) - -; Can't keep more than one gr-names definition at the same time; -; generated enum declarations in sim/cris/cris-desc.h will collide. -; FIXME: (include "different-mach-parts") - -(define-keyword - (name gr-names-pcreg) - (attrs MACH-PC) - (print-name h-gr-real-pc) - ; Put PC first so it is preferred over r15. - (.splice values (PC 15) (.unsplice (cris-general-gregs))) -) - -(define-keyword - (name gr-names-acr) - (attrs MACH-ACR) - ; The print-name directive will control the enum prefix. With the - ; arguably more appropriate h-gr-v32 or h-gr-acr, we'd get names like - ; H_GR_ACR_R0 instead of H_GR_R0. Since we have to choose something for - ; unprefixed names, we use the CRISv32 names. FIXME: All users should - ; change to use H_GR_V32_R0 (etc.), then change this to h-gr-v32. - (print-name h-gr) - ; Put ACR first so it is preferred over r15. - (.splice values (ACR 15) (.unsplice (cris-general-gregs))) -) - -(define-keyword - (name gr-names-v32) - (attrs MACH-V32) - ; In preparation for implementing the FIXME above. - (print-name h-gr-v32) - ; Put ACR first so it is preferred over r15. - (.splice values (ACR 15) (.unsplice (cris-general-gregs))) -) - -; Special registers with names common to all. -(define-pmacro (cris-general-pregs) - (.splice - (VR 1) - (SRP 11) - (.unsplice (.map (.pmacro (n) ((.sym P n) n)) (.iota 15)))) -) - -(define-keyword - (name p-names-v10) - (attrs MACH-PRE-V32) - (print-name h-sr-pre-v32) - (.splice - values - (CCR 5) - (MOF 7) - (IBR 9) - (IRP 10) - (BAR 12) - (DCCR 13) - (BRP 14) - (USP 15) - (.unsplice (cris-general-pregs))) -) - -(define-keyword - (name p-names-v32) - (attrs MACH-V32) - ; See comment for gr-names-acr. - (print-name h-sr) - (.splice - values - (BZ 0) - (PID 2) - (SRS 3) - (WZ 4) - (EXS 5) - (EDA 6) - (MOF 7) - (DZ 8) - (EBP 9) - (ERP 10) - (NRP 12) - (CCS 13) - (USP 14) - (SPC 15) - (.unsplice (cris-general-pregs))) -) - -; Similarly as for h-gr-v32, in preparation. -(define-keyword - (name p-names-v32-x) - (attrs MACH-V32) - ; See comment for gr-names-acr. - (print-name h-sr-v32) - (.splice - values - (BZ 0) - (PID 2) - (SRS 3) - (WZ 4) - (EXS 5) - (EDA 6) - (MOF 7) - (DZ 8) - (EBP 9) - (ERP 10) - (NRP 12) - (CCS 13) - (USP 14) - (SPC 15) - (.unsplice (cris-general-pregs))) -) - -(define-pmacro p0 (reg h-sr 0)) -(define-pmacro vr (reg h-sr 1)) -(define-pmacro pid (reg h-sr 2)) -(define-pmacro srs (reg h-sr 3)) -(define-pmacro p4 (reg h-sr 4)) -(define-pmacro ccr (reg h-sr 5)) -(define-pmacro mof (reg h-sr 7)) -(define-pmacro p8 (reg h-sr 8)) -(define-pmacro ibr (reg h-sr 9)) -(define-pmacro ebp (reg h-sr 9)) -(define-pmacro erp (reg h-sr 10)) -(define-pmacro srp (reg h-sr 11)) -(define-pmacro ccs (reg h-sr 13)) -(define-pmacro dccr (reg h-sr 13)) -(define-pmacro usp (reg h-sr 14)) -(define-pmacro spc (reg h-sr 15)) - -(define-pmacro sp (reg h-gr 14)) -(define-pmacro acr (reg h-gr 15)) - -(define-pmacro cris-condition-codes - "CRIS condition codes in numeric order" - (cc cs ne eq vc vs pl mi ls hi ge lt gt le a wf) -) - -; No use having different lists; this is the only CC that -; differs between v10 and v32, and mostly in the name. -(define-pmacro sb wf) - - -;;;;;;;;;;;;;;;;;; -hardware - -;; Various constant generators. - -(define-hardware - (name h-inc) - (comment "autoincrement-bit syntax specifier") - (type immediate (UINT 1)) - (values keyword "" (("" 0) ("+" 1))) -) - -(define-hardware - (name h-ccode) - (comment "Condition code specifier") - (type immediate (UINT 4)) - (values keyword "" - (.map (.pmacro (x y) ((.str x) y)) - cris-condition-codes (.iota 16))) -) - -(define-hardware - (name h-swap) - (comment "Swap option specifier") - (type immediate (UINT 4)) - (values - keyword "" - (.splice - (" " 0) - (.unsplice - (.map - (.pmacro (x y) ((.str x) y)) cris-swap-codes (.iota 15 1))))) -) - -(define-hardware - (name h-flagbits) - (comment "Flag bits specifier") - (type immediate (UINT 8)) - (values - keyword "" - (.map (.pmacro (x y) ((.str x) y)) cris-flag-combinations (.iota 256))) -) - -; Apparently, the semantic-name isn't used for accessors, so external -; users like the sim glue and SID sees the -v32 and -pre-v32 munged names. -; Defining "dispatchers"; virtual registers whose getter and setter works -; on the "real" mach variants, seems to help. CGEN-FIXME: Make -; semantic-name set the generated names. -(define-pmacro (cris-d-hwreg x-name x-type) - (define-hardware - (name x-name) - (comment (.str "Dispatcher for " x-name)) - (attrs VIRTUAL) - (type register x-type) - (get () (reg (.sym x-name -x))) - (set (val) (set (reg (.sym x-name -x)) val))) -) -(define-pmacro (cris-d-hwregf-a x-name x-type x-n x-attrs) - (define-hardware - (name x-name) - (comment (.str "Dispatcher for " x-name)) - (.splice attrs VIRTUAL (.unsplice x-attrs)) - (type register x-type (x-n)) - (get (index) (reg (.sym x-name -x) index)) - (set (index val) (set-quiet (reg (.sym x-name -x) index) val))) -) -(define-pmacro (cris-d-hwregf x-name x-type x-n) - (cris-d-hwregf-a x-name x-type x-n ()) -) -(define-pmacro (cris-d-hwregf-p x-name x-type x-n) - (cris-d-hwregf-a x-name x-type x-n (PROFILE)) -) - -; At first glance we could use (eq-attr (current-mach) ...) for -; everything, but that seems sometimes (always?) to yield false. For -; ifields, it causes noncompilable C-code. For the insn semantics code, -; it causes tests movei.ms and mulv32.ms to fail, apparently because the -; current-mach-is-v32 usage in flags setting is miscompiled as 0 (or -; rather, misgenerated). Instead we use different definitions of a -; MACH-tagged virtual register yielding a constant, together with a -; pmacro. CGEN-FIXME: If eq-attr is someday fixed, we could just remove -; these h-v32 virtual register definitions and change the pmacro -; definition for current-mach-is-v32. -(define-hardware - (semantic-name h-v32) - (name h-v32-v32) - (attrs MACH-V32 VIRTUAL) - (type register BI) - (get () (const BI 1)) - (set (val) (error "Can't set h-v32")) -) -(define-hardware - (semantic-name h-v32) - (name h-v32-non-v32) - (attrs MACH-PRE-V32 VIRTUAL) - (type register BI) - (get () (const BI 0)) - (set (val) (error "Can't set h-v32")) -) - -;; "Real" hardware. - -(define-hardware - (name h-pc) - (comment "program counter") - (attrs PC PROFILE) - (type pc) - ; There's no bit 0 in PC, so just ignore it when jumping etc. - (set (val) (set (raw-reg h-pc) (and val (inv 1)))) -) - -; Note that setting register 15 isn't handled here, but in each insn, so -; the proper "jump" attributes and other special stuff for speedy -; execution can be present. -(cris-d-hwregf-p h-gr SI 16) -(define-hardware - (semantic-name h-gr-x) - (name h-gr-pc) - (attrs MACH-PC VIRTUAL) - (comment "General purpose registers, aborting on PC access") - (type register SI (16)) - (indices extern-keyword gr-names-pcreg) - (get - (index) - (if SI (eq index 15) - (error SI "General register read of PC is not implemented.") - (reg SI h-gr-real-pc index))) - (set - (index val) - (sequence - () - (if (eq index 15) - (error "General register write to PC is not implemented.")) - (set (reg SI h-gr-real-pc index) val))) -) -(define-hardware - (name h-gr-real-pc) - (attrs MACH-PC) - (comment "General purpose registers") - (type register SI (16)) - (indices extern-keyword gr-names-pcreg) -) - -; We have to use a virtual register trick to get the "raw", unaccounted -; contents of the global register; the raw-reg RTX only works for -; non-virtual register files. -(define-hardware - (semantic-name h-raw-gr) - (name h-raw-gr-pc) - (attrs MACH-PC VIRTUAL) - (comment "Unaccounted version of general purpose registers") - (type register SI (16)) - (get (index) (raw-reg h-gr-real-pc index)) - (set (index val) (set-quiet (raw-reg h-gr-real-pc index) val)) -) -(define-hardware - (semantic-name h-gr-x) - (name h-gr-acr) - (attrs MACH-ACR) - (comment "General purpose registers") - (type register SI (16)) - (indices extern-keyword gr-names-acr) -) -(define-hardware - (semantic-name h-raw-gr) - (name h-raw-gr-acr) - (attrs MACH-ACR VIRTUAL) - (comment "Unaccounted version of general purpose registers") - (type register SI (16)) - (get (index) (raw-reg h-gr-x index)) - (set (index val) (set-quiet (raw-reg h-gr-x index) val)) -) - -; FIXME: get and set semantics? Unknown how to split semantics best; with -; get/set semantics or within the insn specification. Doing the former for -; now. Should use different names for pre-v10. -; FIXME: No dccr for v0 and v3. Different high flag bits. -(cris-d-hwregf-p h-sr SI 16) -(define-pmacro - (cris-h-sr machver) - (define-hardware - (semantic-name h-sr-x) - (name (.sym h-sr-v machver)) - (attrs (MACH (.sym crisv machver))) - (comment (.str "Special registers for v" machver)) - (type register SI (16)) - (indices extern-keyword p-names-v10) - (get - (index) - (cond - SI - ((orif (orif (eq index (regno p0)) (eq index (regno p4))) - (eq index (regno p8))) 0) - ((eq index (regno vr)) machver) - ((orif (eq index (regno ccr)) - (eq index (regno dccr))) - ; Return "P U I X N Z V C" for the low 8 bits. - ; FIXME: More bits. - (or SI - (and SI (raw-reg SI h-sr-x (regno ccr)) #xffffff00) - (or - (zext SI (reg BI h-cbit)) - (or - (sll (zext SI (reg BI h-vbit)) 1) - (or - (sll (zext SI (reg BI h-zbit)) 2) - (or - (sll (zext SI (reg BI h-nbit)) 3) - (or - (sll (zext SI (reg BI h-xbit)) 4) - (or - (sll (zext SI (reg BI h-ibit)) 5) - (or - (sll (zext SI (reg BI h-ubit)) 6) - (or - (sll (zext SI (reg BI h-pbit)) 7) - 0)))))))))) - (else (raw-reg SI h-sr-x index)))) - (set - (index val) - (cond - ((orif (orif (eq index (regno p0)) (eq index (regno p4))) - (orif (eq index (regno p8)) (eq index (regno vr)))) - (nop)) - ((orif (eq index (regno ccr)) (eq index (regno dccr))) - (sequence - () - (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) - (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) - (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) - (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) - (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) - (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) - (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) - (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) - (set-quiet (raw-reg SI h-sr-x (regno ccr)) val) - (set-quiet (raw-reg SI h-sr-x (regno dccr)) val))) - (else (set-quiet (raw-reg SI h-sr-x index) val))))) -) - -(cris-h-sr 0) -(cris-h-sr 3) -(cris-h-sr 8) -(cris-h-sr 10) - -(define-hardware - (semantic-name h-sr-x) - (name h-sr-v32) - (attrs MACH-V32) - (comment "Special registers for v32") - (type register SI (16)) - (indices extern-keyword p-names-v32) - - (get - (index) - (cond - SI - ((orif (orif (eq index (regno p0)) (eq index (regno p4))) - (eq index (regno p8))) 0) - ((eq index (regno vr)) 32) - ((eq index (regno ccs)) - ; Return "S R P U I X N Z V C" for the low 10 bits. - (or SI - (and SI (raw-reg SI h-sr-x (regno ccs)) #x3ffffc00) - (or - (zext SI (reg BI h-cbit)) - (or - (sll (zext SI (reg BI h-vbit)) 1) - (or - (sll (zext SI (reg BI h-zbit)) 2) - (or - (sll (zext SI (reg BI h-nbit)) 3) - (or - (sll (zext SI (reg BI h-xbit)) 4) - (or - (sll (zext SI (reg BI h-ibit)) 5) - (or - (sll (zext SI (reg BI h-ubit)) 6) - (or - (sll (zext SI (reg BI h-pbit)) 7) - (or - (sll (zext SI (reg BI h-rbit)) 8) - (or - (sll (zext SI (reg BI h-sbit)) 9) - (or - (sll (zext SI (reg BI h-mbit)) 30) - (or - (sll (zext SI (reg BI h-qbit)) 31) - 0)))))))))))))) - ((eq index (regno usp)) - ; In user mode, return general stack pointer. - (if BI (reg BI h-ubit) - (raw-reg SI h-gr-x (regno sp)) - (raw-reg SI h-sr-x (regno usp)))) - (else (raw-reg SI h-sr-x index)))) - - (set - (index val) - (cond - ((orif (orif (eq index (regno p0)) (eq index (regno p4))) - (orif (eq index (regno p8)) (eq index (regno vr)))) - (nop)) - ((eq index (regno ccs)) - (sequence - () - ; Protected bits are handled as such in the respective setter function. - (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) - (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) - (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) - (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) - (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) - (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) - (set (reg BI h-sbit) (if BI (ne SI (and val (sll 1 9)) 0) 1 0)) - (set (reg BI h-mbit) (if BI (ne SI (and val (sll 1 30)) 0) 1 0)) - (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) - (set (reg BI h-rbit) (if BI (ne SI (and val (sll 1 8)) 0) 1 0)) - (set (reg BI h-qbit) (if BI (ne SI (and val (sll 1 31)) 0) 1 0)) - ; Set the U bit last, so the setter functions for the other bits - ; don't see it as set from this operation. It is not cleared from - ; this operation, so we don't have to handle that; it's only - ; cleared "manually" from within simulator-specific context-switch - ; machinery. - (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) - (set-quiet (raw-reg SI h-sr-x index) val))) - ((eq index (regno usp)) - ; In user mode, set general register 14 too, whenever setting USP. - (sequence - () - (if (reg BI h-ubit) (set (raw-reg SI h-gr-x (regno sp)) val)) - (set (raw-reg SI h-sr-x (regno usp)) val))) - ((eq index (regno srs)) - (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno srs)) val))) - ((eq index (regno ebp)) - (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno ebp)) val))) - ((eq index (regno pid)) - (if (not (reg BI h-ubit)) - (sequence - () - (c-call VOID "@cpu@_write_pid_handler" val) - (set (raw-reg h-sr-x (regno pid)) val)))) - ((eq index (regno spc)) - (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno spc)) val))) - (else (set-quiet (raw-reg SI h-sr-x index) val)))) -) - -(define-hardware - (name h-supr) - (attrs MACH-V32 VIRTUAL) - (comment "Support registers") - (type register SI (16)) - (values keyword "" (.map (.pmacro (y) ((.str S y) y)) (.iota 16))) - (get (index) (c-call SI "@cpu@_read_supr" index)) - (set (index val) (c-call VOID "@cpu@_write_supr" index val)) -) - -(define-pmacro (cris-dsh semantic-name name comment attrs type) - "Like dsh, but the semantic-name is separate" - (define-full-hardware - name comment attrs semantic-name type () () () () () ()) -) - -; We define the condition codes that hold arithmetic flags separately -; and "or" them in, in the get and set methods of the special -; registers. We define arithmetic flags as any of C V Z N X. They -; thankfully have that order (zero-based) in all processor versions. - -; To avoid having two variants of most move-type instructions because V32 -; doesn't set C and V (and N and Z), we fake the setting to virtual -; registers which have two different implementations. -(define-pmacro (cris-move-flag f f-name f-whence) - "Flag set differently in pre-v32 and v32 in some cases" - (begin - (dsh (.sym h- f bit) (.str f-name " bit") () (register BI)) - (cris-d-hwreg (.sym h- f bit-move) BI) - (define-hardware - (semantic-name (.sym h- f bit-move-x)) - (name (.sym h- f bit-move-v32)) - (comment (.str f-name " bit set in " f-whence " instructions, ignored")) - (attrs MACH-V32 VIRTUAL) - (type register BI) - (get - () - (sequence BI () - (error (.str "Can't get h-" f "bit-move on CRISv32")) 0)) - (set (val) (nop))) - (define-hardware - (semantic-name (.sym h- f bit-move-x)) - (name (.sym h- f bit-move-pre-v32)) - (comment - (.str - f-name " bit set in " f-whence " instructions, same as " f "bit")) - (attrs MACH-PRE-V32 VIRTUAL) - (type register BI) - (get () (reg (.sym h- f bit))) - (set (val) (set (reg (.sym h- f bit)) val)))) -) - -(cris-move-flag c "carry" "move-type") -(cris-move-flag v "overflow" "move-type") -(cris-move-flag z "zero" "moveq") -(cris-move-flag n "sign" "moveq") - -(dsh h-xbit "extended-arithmetic bit" () (register BI)) -(cris-d-hwreg h-ibit BI) -(cris-dsh h-ibit-x h-ibit-pre-v32 - "interrupt-enable bit" (MACH-PRE-V32) (register BI)) -(dsh h-pbit "sequence-broken bit" ((MACH crisv10,crisv32)) (register BI)) -(dsh h-rbit "carry bit for MCP+restore-p bit" (MACH-V32) (register BI)) -(cris-d-hwreg h-ubit BI) -(cris-dsh h-ubit-x h-ubit-pre-v32 - "user mode bit" ((MACH crisv10)) (register BI)) -(dsh h-gbit "guru mode bit" (MACH-V32) (register BI)) - -; When doing a transition from kernel to user mode on V32, we save the -; stack pointer in an internal register and copy USP to R14, so we don't -; need non-trivial handlers for general registers. -(dsh - h-kernel-sp - "Kernel stack pointer during user mode" - (MACH-V32) - (register SI) -) - -(define-hardware - (semantic-name h-ubit-x) - (name h-ubit-v32) - (comment "User mode bit") - (attrs MACH-V32) - (type register BI) - (set - (val) - (sequence - () - (if (andif val (not (raw-reg BI h-ubit-x))) - (sequence - () - (set (reg SI h-kernel-sp) (raw-reg h-gr-x (regno sp))) - (set (raw-reg h-gr-x (regno sp)) (raw-reg h-sr-x (regno usp))) - (set (raw-reg BI h-ubit-x) val) - (c-call VOID "@cpu@_usermode_enabled"))))) -) - -(define-hardware - (semantic-name h-ibit-x) - (name h-ibit-v32) - (comment "Interrupt-enable bit") - (attrs MACH-V32) - (type register BI) - (set - (val) - (sequence - () - (if (not (reg BI h-ubit)) - (sequence - ((BI enabled)) - (set enabled (andif val (not (raw-reg BI h-ibit-x)))) - (set (raw-reg BI h-ibit-x) val) - ; Call handler when enabling. - (if enabled (c-call VOID "@cpu@_interrupts_enabled")))))) -) - -(define-hardware - (name h-mbit) - (comment "NMI enable bit") - (attrs MACH-V32) - (type register BI) - (set - (val) - (sequence - () - ; Don't allow clearing (through this handler) when once set. - (if (andif val (andif (not (raw-reg BI h-mbit)) (not (reg BI h-ubit)))) - (sequence - () - (set (raw-reg BI h-mbit) 1) - ; Call handler when enabling. - (c-call VOID "@cpu@_nmi_enabled"))))) -) - -(define-pmacro - (dsh-cond-bit-v32 x-name x-comment x-cond) - "dsh bit for MACH-V32, with bit only changeable when X-COND" - (define-hardware - (name x-name) - (comment x-comment) - (attrs MACH-V32) - (type register BI) - (set (val) (sequence () (if x-cond (set (raw-reg BI x-name) val))))) -) -(define-pmacro - (dsh-protected-bit-v32 x-name x-comment) - "dsh bit for MACH-V32, with bit only changeable in kernel mode" - (dsh-cond-bit-v32 x-name x-comment (not (reg BI h-ubit))) -) -(dsh-protected-bit-v32 h-qbit "Pending single-step bit") - -(define-hardware - (name h-sbit) - (comment "Cause single step exception on ... [see CRISv32 ref] bit") - (attrs MACH-V32) - (type register BI) - (set - (val) - (sequence - () - (if (not (reg BI h-ubit)) - (sequence - ((BI enabled)) - (set enabled (andif val (not (raw-reg BI h-sbit)))) - (set (raw-reg BI h-sbit) val) - ; Call handler when enabling. - (if enabled (c-call VOID "@cpu@_single_step_enabled")))))) -) - -(dnop cbit "" (SEM-ONLY) h-cbit f-nil) -(dnop cbit-move - "cbit for pre-V32, nothing for newer" (SEM-ONLY) h-cbit-move f-nil) -(dnop vbit "" (SEM-ONLY) h-vbit f-nil) -(dnop vbit-move - "vbit for pre-V32, nothing for newer" (SEM-ONLY) h-vbit-move f-nil) -(dnop zbit "" (SEM-ONLY) h-zbit f-nil) -(dnop zbit-move - "zbit for pre-V32, nothing for newer" (SEM-ONLY) h-zbit-move f-nil) -(dnop nbit "" (SEM-ONLY) h-nbit f-nil) -(dnop nbit-move - "nbit for pre-V32, nothing for newer" (SEM-ONLY) h-nbit-move f-nil) -(dnop xbit "" (SEM-ONLY) h-xbit f-nil) -(dnop ibit "" (SEM-ONLY) h-ibit f-nil) -(dnop ubit "" (SEM-ONLY (MACH crisv10,crisv32)) h-ubit f-nil) -(dnop pbit "" (SEM-ONLY (MACH crisv10,crisv32)) h-pbit f-nil) -(dnop - rbit "carry bit for MCP+restore-P flag bit" (SEM-ONLY MACH-V32) h-rbit f-nil) -(dnop sbit "" (SEM-ONLY MACH-V32) h-sbit f-nil) -(dnop mbit "" (SEM-ONLY MACH-V32) h-mbit f-nil) -(dnop qbit "" (SEM-ONLY MACH-V32) h-qbit f-nil) - -(cris-d-hwreg h-insn-prefixed-p BI) -(cris-dsh - h-insn-prefixed-p-x - h-insn-prefixed-p-pre-v32 - "instruction-is-prefixed bit" - (MACH-PRE-V32) - (register BI) -) - -; CRISv32 has no prefixing on memory accesses. CGEN-FIXME: [Once (eq-attr -; (current-mach) ...) works]: can we change andif and/or orif so it -; doesn't look too close at short-circuited operands and avoid defining an -; operand that doesn't apply to a certain mach? -(define-hardware - (semantic-name h-insn-prefixed-p-x) - (name h-insn-prefixed-p-v32) - (attrs MACH-V32 VIRTUAL) - (comment "instruction-is-prefixed bit") - (type register BI) - (get () (const BI 0)) - (set (val) (nop)) -) -(dnop - prefix-set - "Instruction-prefixed flag" - (SEM-ONLY) - h-insn-prefixed-p - f-nil -) - -(cris-dsh - h-prefixreg h-prefixreg-pre-v32 - "Prefix-address register" (MACH-PRE-V32) (register SI)) -(define-hardware - (semantic-name h-prefixreg) - (name h-prefixreg-v32) - (comment "Prefix-address register, redirecting to ACR") - (attrs MACH-V32 VIRTUAL) - (type register SI) - ; Why can't we have just a "acr" a.k.a "(reg h-gr 15)" here? - (get () acr) - (set (value) (set acr value)) -) - -(dnop - prefixreg - "Prefix address" - (SEM-ONLY) - h-prefixreg - f-nil -) - -;;;;;;;;;;;;;;;;;; -ifield - -; 15 0 -; +-----------+-----+-----------+-----+-----------+ -; | Operand2 | Mode| Opcode | Size| Operand1 | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; -; Figure 5. General instruction format. -; -; Some deviations from this format exist, [see below]. - -; Field specifiers in CGEN specify the highest numbered bit followed by -; the number of bits. - -(dnf f-operand1 "Operand1" () 3 4) -(dnf f-size "Size" () 5 2) -(dnf f-opcode "Opcode" () 9 4) -(dnf f-mode "Mode" () 11 2) -(dnf f-operand2 "Operand2" () 15 4) - -; Subfields. FIXME: unfortunately there's some limitation in CGEN so we -; can't (as would be somewhat intuitive) make f-mode a multi-ifield -; consisting of these two, concatenated. -(dnf f-memmode "Indirect of autoincrement" () 10 1) -(dnf f-membit "Memory specifier" () 11 1) - -(dnf f-b5 "Bit 5 (zero for some quick operands)" () 5 1) - -; When the addressing mode is quick immediate, the low bits are -; part of the operand. -(dnf f-opcode-hi "Opcode field, high bits" () 9 2) - -; Common synonyms for those fields. -(define-pmacro f-source f-operand1) -(define-pmacro f-dest f-operand2) - -(dnmf - f-dstsrc "Dest and source fields concatenated" () UINT - (f-dest f-source) - ; Insert-code. - (sequence - ((SI tmpval)) - (set tmpval (ifield f-dstsrc)) - (set (ifield f-dest) (and (srl tmpval 4) #xf)) - (set (ifield f-source) (and tmpval #xf))) - ; Extract-code. - (set - (ifield f-dstsrc) - (and (or (ifield f-source) (sll (ifield f-dest) 4)) #xff)) -) - -;The 6-bit value may be sign or zero extended depending on the instruction. -; -; 15 0 -; +-----------+-----+-----------+-----+-----------+ -; | Operand2 | Mode| Opcode | Immediate value | -; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ -; -; Figure 6. Quick immediate addressing mode instruction format. - -(dnf f-u6 "Quick immediate unsigned 6-bit" () 5 6) -(df f-s6 "Quick signed 6-bit" () 5 6 INT #f #f) - -; There's also a variant used with shift insns, with one bit larger opcode -; and one bit smaller immediate value, though it doesn't have a general -; graphic description. -(dnf f-u5 "Quick unsigned 5-bit" () 4 5) - -; Similarly, a four-bit immediate field. -(dnf f-u4 "Quick unsigned 4-bit" () 3 4) - -; An 8-bit signed value, which doesn't have a general graphic description. -(df f-s8 "Source signed byte" () 7 8 INT #f #f) - -; The 9-bit branch offset, with bit 0 in the field being bit 8 in the -; offset, and bit 0 in the offset always 0. -(df f-disp9-hi "PC-relative 9-bit offset, sign bit" () 0 1 INT #f #f) -(dnf f-disp9-lo "PC-relative 9-bit offset, low bits" () 7 7) - -; It would work to have this in two mach-specific variants, but -; considering that current-mach-is-v32 is a compile-time constant, we -; don't win any simulator performance. -(dnmf - f-disp9 "PC-relative 9-bit offset" - (PCREL-ADDR) - INT - (f-disp9-hi f-disp9-lo) - ; Insert-code. - (sequence - ((SI absval)) - (set absval (srl (sub (sub SI (ifield f-disp9) pc) - (if SI current-mach-is-v32 0 2)) 1)) - (set (ifield f-disp9-hi) (if (lt absval 0) 1 0)) - (set (ifield f-disp9-lo) (and absval) #x7f)) - ; Extract-code. - (sequence - ((SI abslo) (SI absval)) - (set abslo (sll (ifield f-disp9-lo) 1)) - (set absval - (or (if SI (ne (ifield f-disp9-hi) 0) - (inv SI #xff) - 0) - abslo)) - (set (ifield f-disp9) - (add SI (add SI pc absval) (if SI current-mach-is-v32 0 2)))) -) - -; The operand of LAPCQ is PC-relative, similar to f-disp9 but unsigned, -; and only four bits. -(df - f-qo - "PC-relative 4-bit unsigned offset, counted from start of insn" - (MACH-V32 PCREL-ADDR) - 3 4 - UINT - ; Insert-code. - ((value pc) (srl SI (sub SI value pc) 1)) - ; Extract-code. - ((value pc) (add SI pc (sll SI value 1))) -) - -; 8-bit, 16-bit and 32-bit immediates. The 8-bit values are constructed -; through encoding/decoding functions, since the PC increment is by a -; word. -(define-pmacro (dcrisf x-name x-comment x-attrs x-word-offset x-word-length - x-start x-length x-mode x-encode x-decode) - (define-ifield - (name x-name) - (comment x-comment) - (.splice attrs (.unsplice x-attrs)) - (word-offset x-word-offset) - (word-length x-word-length) - (start x-start) - (length x-length) - (mode x-mode) - (.splice encode (.unsplice x-encode)) - (.splice decode (.unsplice x-decode)) - ) -) - -(dcrisf - f-indir-pc+-byte "[PC+] 8-bit field" (SIGN-OPT) - 16 16 - 15 16 ; CGEN-FIXME: Should be 7 8 - INT (#f) (#f) -) - -(dcrisf - f-indir-pc+-word "[PC+] 16-bit field" (SIGN-OPT) - 16 16 15 16 INT (#f) (#f) -) - -; CGEN-FIXME: I shouldn't have to use trunc here, should I? -; Sign-extension should be implicit through use of SI (as opposed to USI) -; and additionally through SIGN-OPT. The ext isn't actually needed, but -; having it there rather than implicit makes more sense than to just have -; the trunc. -(dcrisf - f-indir-pc+-word-pcrel "[PC+] PC-relative 16-bit field" - (PCREL-ADDR SIGN-OPT) - 16 16 15 16 SI - ((value pc) (sub SI value (add SI pc (if SI current-mach-is-v32 0 4)))) - ((value pc) (add SI (ext SI (trunc HI value)) (add SI pc (if SI current-mach-is-v32 0 4)))) -) - -(dcrisf - f-indir-pc+-dword "PC autoincrement - 32-bit field" (SIGN-OPT) - 16 32 31 32 INT (#f) (#f) -) - -(dcrisf - f-indir-pc+-dword-pcrel - "[PC+] PC-relative 32-bit field, counted from start of insn" - (SIGN-OPT MACH-V32 PCREL-ADDR) - 16 32 31 32 INT - ((value pc) (sub SI value pc)) - ((value pc) (add SI pc value)) -) - -;;;;;;;;;;;;;;;;;; -insn-enum -normal-operand -normal-derived-operand - -;; How different fields are transformed into something we put in insns. - -; m := size modifier, byte (00), word (01) or dword (10) -; z := size modifier, byte (0) or word (1) -; (For the latter, the "higher" bit is always 0, mapping trivially on m.) - -(define-normal-insn-enum - insn-size - "Standard instruction operand size" - () - SIZE_ - f-size - ("BYTE" "WORD" "DWORD" "FIXED") -) - -; The mode field for insns with "s" operand (perhaps with a partial set of -; operand types). -(define-normal-insn-enum - insn-mode - "Standard instruction addressing modes" - () - MODE_ - f-mode - ("QUICK_IMMEDIATE" "REGISTER" "INDIRECT" "AUTOINCREMENT") -) - -(define-normal-insn-enum - insn-memoryness-mode - "Whether the operand is indirect" - () - MODEMEMP_ - f-membit - ("NO" "YES") -) - -; FIXME: Needed? -(define-normal-insn-enum - insn-memincness-mode - "Whether the indirect operand is autoincrement" - () - MODEINCP_ - f-memmode - ("NO" "YES") -) - -; Special semantics for multiply. -(define-pmacro MODE_MULU MODE_INDIRECT) -(define-pmacro MODE_MULS MODE_AUTOINCREMENT) - -(define-normal-insn-enum - insn-signed-size - "Signed instruction operand size" - () - SIGNED_ - f-size - ("UNDEF_SIZE_0" "UNDEF_SIZE_1" "BYTE" "WORD") -) - -(define-normal-insn-enum - insn-unsigned-size - "Unsigned instruction operand size" - () - UNSIGNED_ - f-size - ("BYTE" "WORD" "UNDEF_SIZE_2" "UNDEF_SIZE_3") -) - -; Rs := source operand, register addressing mode -(dnop Rs "Source general register" () h-gr f-source) - -; [Rs] := source operand, indirect addressing mode -; = MODE_INDIRECT Rs - -; [Rs+] := source operand, autoincrement addressing mode (see note!) -; = MODE_AUTOINCREMENT Rs - -; The union of [Rs] and [Rs(+)] -; = MODEMEMP_YES Rs - -; Whether an indirect operand is increment can be obtained as an operand by -; = inc -(dnop inc "Incrementness of indirect operand" () h-inc f-memmode) - -; or as an affirmative specifier -; = MODEINCP_YES -; (or MODEINCP_NO) - -; s := source operand, any of the modes Rs, [Rs] or [Rs+] -; No common operand; each are handled separately, using the above definitions. - -; Ps := source operand, special register -; It's in the field usually used for the destination. -(dnop Ps "Source special register" () h-sr f-dest) - -; Ss := source operand, support register -; It's in the field usually used for the destination. -(dnop Ss "Source support register" (MACH-V32) h-supr f-dest) - -; Sd := source operand, support register -(dnop Sd "Destination support register" (MACH-V32) h-supr f-dest) - -; i := 6-bit signed immediate operand -(dnop i "Quick signed 6-bit" () h-sint f-s6) - -; j := 6-bit unsigned immediate operand -(dnop j "Quick unsigned 6-bit" () h-uint f-u6) - -; c := 5-bit immediate shift value -(dnop c "Quick unsigned 5-bit" () h-uint f-u5) - -; qo := 4-bit unsigned immediate operand -(dnop qo "Quick unsigned 4-bit, PC-relative" (MACH-V32) h-addr f-qo) - -; Rd := destination operand, register addressing mode -(dnop Rd "Destination general register" () h-gr f-dest) -(define-pmacro Rd-sfield Rs) -(define-pmacro Rs-dfield Rd) - -; [Rd] := destination operand, indirect addressing mode -; = MODE_INDIRECT Rd - -; [Rd+] := destination operand, autoincrement addressing mode -; = MODE_AUTOINCREMENT Rd - -; [PC+] := destination operand PC, autoincrement addressing mode -; = MODE_AUTOINCREMENT (f-dest 15) X -; where X is one of sconst8, uconst8, sconst16, uconst16 or const32. -(dnop sconst8 "Signed byte [PC+]" () h-sint f-indir-pc+-byte) -(dnop uconst8 "Unsigned byte [PC+]" () h-uint f-indir-pc+-byte) -(dnop sconst16 "Signed word [PC+]" () h-sint f-indir-pc+-word) -(dnop uconst16 "Unsigned word [PC+]" () h-uint f-indir-pc+-word) -(dnop const32 "Dword [PC+]" () h-uint f-indir-pc+-dword) -(dnop const32-pcrel "Dword [PC+]" () h-addr f-indir-pc+-dword-pcrel) - -; d := destination operand, any of the modes Rd, [Rd] or [Rd+] -; No common operand; each are handled separately, using the above definitions. - -; Pd := destination operand, special register -(dnop Pd "Destination special register" () h-sr f-dest) - -; o := 8-bit immediate offset value -(dnop o "Signed 8-bit" () h-sint f-s8) - -; The division of operand semantics and insn fields in the CRIS -; instruction set reference doesn't permit a simple mapping to a -; simulator description, and the division of insn fields and -; semantics in CGEN is not between the define-normal-ifield -; vs. define-normal-operand. For example, the "o" operand is -; PC-relative for branch insns, as described by the CGEN f-disp9 -; field. -; See comment at f-disp9; thankfully the mach -; attribute works here to have two different definitions by the -; same name. -(dnop o-pcrel "9-bit signed immediate PC-rel" - () - h-iaddr f-disp9) - -(dnop o-word-pcrel "16-bit signed immediate PC-rel" - () - h-iaddr f-indir-pc+-word-pcrel) - -; cc := condition code -(dnop cc "Condition codes" () h-ccode f-dest) - -; n := 4 bit breakpoint exception vector index -(dnop n "Quick unsigned 4-bit" () h-uint f-u4) - -; The "option" in the SWAP insn. -(dnop swapoption "Swap option" () h-swap f-dest) - -(dnop list-of-flags "Flag bits as operand" () h-flagbits f-dstsrc) - -; Enumerations for insn codes, for use in insn definitions -; instead of raw numbers. See it as operand definitions for the -; opcode field. - -(define-normal-insn-enum - insn-qi-opc - "Insns for MODE_QUICK_IMMEDIATE" - () - Q_ - f-opcode - ("BCC_0" "BCC_1" "BCC_2" "BCC_3" - "BDAP_0" "BDAP_1" "BDAP_2" "BDAP_3" - "ADDQ" "MOVEQ" "SUBQ" "CMPQ" - "ANDQ" "ORQ" "ASHQ" "LSHQ") -) - -(define-normal-insn-enum - insn-qihi-opc - "Same as insn-qi-opc, though using only the high two bits of the opcode" - () - QHI_ - f-opcode-hi - ("BCC" "BDAP" "OTHER2" "OTHER3") -) -(define-pmacro QHI_ADDOQ QHI_BDAP) - -(define-normal-insn-enum - insn-r-opc - "Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" - () - R_ - f-opcode - ("ADDX" "MOVX" "SUBX" "LSL" - "ADDI" "BIAP" "NEG" "BOUND" - "ADD" "MOVE" "SUB" "CMP" - "AND" "OR" "ASR" "LSR") -) -(define-pmacro R_ADDI_ACR R_BIAP) - -(define-normal-insn-enum - insn-rfix-opc - "Insns for MODE_REGISTER and SIZE_FIXED" - () - RFIX_ - f-opcode - ("ADDX" "MOVX" "SUBX" "BTST" - "SCC" "ADDC" "SETF" "CLEARF" - "MOVE_R_S" "MOVE_S_R" "ABS" "DSTEP" - "LZ" "SWAP" "XOR" "MSTEP") -) -(define-pmacro RFIX_MCP RFIX_MSTEP) - -(define-normal-insn-enum - insn-indir-opc - "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" - () - INDIR_ - f-opcode - ("ADDX" "MOVX" "SUBX" "CMPX" - "MUL" "BDAP_M" "ADDC" "BOUND" - "ADD" "MOVE_M_R" "SUB" "CMP" - "AND" "OR" "TEST" "MOVE_R_M") -) -(define-pmacro INDIR_ADDO INDIR_BDAP_M) - -(define-normal-insn-enum - insn-infix-opc - "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED" - () - INFIX_ - f-opcode - ("ADDX" "MOVX" "SUBX" "CMPX" - "JUMP_M" "DIP" "JUMP_R" "BCC_M" - "MOVE_M_S" "MOVE_S_M" "BMOD" "BSTORE" - "RBF" "SBFS" "MOVEM_M_R" "MOVEM_R_M") -) - -(define-pmacro INFIX_MOVE_SS INFIX_SBFS) -(define-pmacro INFIX_LAPC INFIX_DIP) -(define-pmacro INFIX_RFE INFIX_JUMP_M) -(define-pmacro INFIX_RFN INFIX_JUMP_M) -(define-pmacro INFIX_HALT INFIX_JUMP_M) -(define-pmacro INFIX_SFE INFIX_JUMP_M) -(define-pmacro INFIX_RFG INFIX_JUMP_M) -(define-pmacro INFIX_JAS_R INFIX_JUMP_R) -(define-pmacro INFIX_JAS_M INFIX_JUMP_R) -(define-pmacro INFIX_JASC INFIX_RBF) -(define-pmacro INFIX_JUMP_P INFIX_BCC_M) -(define-pmacro INFIX_BAS INFIX_BMOD) -(define-pmacro INFIX_BASC INFIX_BSTORE) -(define-pmacro INFIX_BREAK INFIX_JUMP_M) -(define-pmacro INFIX_FIDXI INFIX_JUMP_M) -(define-pmacro INFIX_FIDXD INFIX_BAS) -(define-pmacro INFIX_FTAGI INFIX_JUMP_M) -(define-pmacro INFIX_FTAGD INFIX_BAS) - -; Classes of insns: -; Move-to-register, move-to-memory, move-to/from-other-register, -; logical, arithmetic, branch. -; Classes of operands: -; quick, register, memory-indirect, memory-postinc. - - -;;;;;;;;;;;;;;;;;; -normal-insn - -(define-pmacro (dni-bwd-attr name comment attr syntax fmt fsem timing) - (begin - (dni (.sym name .b) (.str "byte " comment) attr (.str name ".b " syntax) - (.splice (.unsplice fmt) SIZE_BYTE) - (fsem QI) - timing) - (dni (.sym name .w) (.str "word " comment) attr (.str name ".w " syntax) - (.splice (.unsplice fmt) SIZE_WORD) - (fsem HI) - timing) - (dni (.sym name .d) (.str "dword " comment) attr (.str name ".d " syntax) - (.splice (.unsplice fmt) SIZE_DWORD) - (fsem SI) - timing)) -) - -(define-pmacro (dni-cdt-attr name comment attr syntax fmt semantics) - "dni without specifying timing" - (dni name comment attr syntax fmt semantics (cris-timing)) -) - -(define-pmacro (dni-cdt-bwd-attr name comment attr syntax fmt fsem) - (begin - (dni-cdt-attr (.sym name .b-r) (.str "byte " comment) attr (.str name ".b " syntax) - (.splice (.unsplice fmt) SIZE_BYTE) - (fsem QI)) - (dni-cdt-attr (.sym name .w-r) (.str "word " comment) attr (.str name ".w " syntax) - (.splice (.unsplice fmt) SIZE_WORD) - (fsem HI)) - (dni-cdt-attr (.sym name .d-r) (.str "dword " comment) attr (.str name ".d " syntax) - (.splice (.unsplice fmt) SIZE_DWORD) - (fsem SI))) -) - -; Some convenience macros based on the above ones. -(define-pmacro (dni-cdt-bwd name comment syntax fmt fsem) - (dni-cdt-bwd-attr name comment () syntax fmt fsem) -) - -(define-pmacro (dni-bwd name comment syntax fmt fsem timing) - (dni-bwd-attr comment () syntax fmt fsem timing) -) - -(define-pmacro-map - (((dni-cdt name comment syntax fmt semantics) - (dni-cdt-attr name comment () syntax fmt semantics)) - ((dni-c-QI-attr name comment attr syntax fmt fsem) - (dni name comment attr syntax fmt fsem (cris-timing-const-QI))) - ((dni-c-HI-attr name comment attr syntax fmt fsem) - (dni name comment attr syntax fmt fsem (cris-timing-const-HI))) - ((dni-c-SI-attr name comment attr syntax fmt fsem) - (dni name comment attr syntax fmt fsem (cris-timing-const-SI)))) -) - -(define-pmacro-map - (((dni-c-QI name comment syntax fmt fsem) - (dni-c-QI-attr name comment () syntax fmt fsem)) - ((dni-c-HI name comment syntax fmt fsem) - (dni-c-HI-attr name comment () syntax fmt fsem)) - ((dni-c-SI name comment syntax fmt fsem) - (dni-c-SI-attr name comment () syntax fmt fsem))) -) - -; These flags are both cleared by all insns except prefixes (before -; CRISv32) and "setf x", so we put them in a handy macro. -(define-pmacro - (reset-x-p) - (sequence - () - (set xbit 0) - (set prefix-set 0)) -) - -; NOP | 0 0 0 0| 0 1| 0 1 0 0| 0 0| 1 1 1 1| -; (For V32, "SETF" (no flags) is used.) -(dni-cdt-attr - nop "nop" (MACH-PC) "nop" - (+ (f-operand2 0) R_ADDI MODE_REGISTER SIZE_BYTE (f-operand1 15)) - (reset-x-p) -) - -; Pre- and v32+ variants MOVE insns set flags differently. These two -; macros for flag settings are meant to be used in all MOVE insns. -(define-pmacro (setf-moveq value) - (sequence - () - (set-quiet nbit-move (lt SI value 0)) - (set-quiet zbit-move (andif BI (eq SI value 0) (if BI xbit zbit 1))) - (set-quiet cbit-move 0) - (set-quiet vbit-move 0) - (reset-x-p)) -) - -(define-pmacro (setf-move size value) - (sequence - () - (set nbit (lt size value 0)) - (set zbit (andif BI (eq size value 0) (if BI xbit zbit 1))) - (set-quiet cbit-move 0) - (set-quiet vbit-move 0) - (reset-x-p)) -) -; The CGEN binop-with-bit operations are not documented well enough that I -; trust their semantics to remain stable. Better define local ones: the -; semantics become explicit. -(define-pmacro-map - (((add-overflow size R D S carry) - (orif BI (andif BI (andif BI (lt size S 0) (lt size D 0)) (ge size R 0)) - (andif BI (andif BI (ge size S 0) (ge size D 0)) (lt size R 0)))) - ((add-carry size R D S carry) - (orif BI (andif BI (lt size S 0) (lt size D 0)) - (orif BI (andif BI (lt size D 0) (ge size R 0)) - (andif BI (lt size S 0) (ge size R 0))))) - ((sub-overflow size R D S carry) - (orif BI (andif BI (andif BI (ge size S 0) (lt size D 0)) (ge size R 0)) - (andif BI (andif BI (lt size S 0) (ge size D 0)) (lt size R 0)))) - ((sub-carry size R D S carry) - (orif BI (andif BI (lt size S 0) (ge size D 0)) - (orif BI (andif BI (ge size D 0) (lt size R 0)) - (andif BI (lt size S 0) (lt size R 0))))) - ; Only valid for size := DI - ((mulu-overflow size R D S carry) - (ne DI R (zext DI (trunc SI R)))) - ((mulu-carry size R D S carry) - (andif current-mach-is-v32 carry)) - ((muls-overflow size R D S carry) - (ne DI R (ext DI (trunc SI R)))) - ((muls-carry size R D S carry) - (andif current-mach-is-v32 carry))) -) - -(define-pmacro (setf-arit2 size op source1 source2 result carryin carryout) - "Set no-prefix, x=0, carryout, v, z and n according to operation OP in size SIZE" - (sequence - () - (set carryout ((.sym op -carry) size result source1 source2 carryin)) - (set nbit (lt size result 0)) - (set zbit (andif BI (eq size result 0) (orif BI zbit (not BI xbit)))) - (set vbit ((.sym op -overflow) size result source1 source2 carryin)) - (reset-x-p)) -) -(define-pmacro (setf-arit size op source1 source2 result carry) - "Set no-prefix, x=0, c, v, z and n according to operation OP in size SIZE" - (setf-arit2 size op source1 source2 result carry cbit) -) - -; Let's have convienence macros for arithmetic, including evaluation of the -; operation, destination modification, flag setting and carry propagation. -(define-pmacro - (cris-arit6-int arit size fdest fdest_op srcop1 srcop2 carryout carryin) - "Core for performing some three-operand arithmetic with carry as parameter" - (sequence - ((size tmpopd) (size tmpops) (BI carry) (size newval)) - (set tmpops srcop2) - (set tmpopd srcop1) - (set carry carryin) - (set newval ((.sym arit c) tmpopd tmpops (if BI (eq xbit 0) 0 carry))) - (fdest size fdest_op newval) - (setf-arit2 size arit tmpopd tmpops newval carry carryout)) -) - -(define-pmacro - (cris-arit5-int arit size destregno srcop1 srcop2 carryout carryin) - "As cris-arit6-int, but to set a part of a general register" - (cris-arit6-int - arit - size - (.pmacro (sz regno val) (set-subreg-gr sz regno val)) - destregno - srcop1 - srcop2 - carryout - carryin) -) - -(define-pmacro (cris-arit5 arit size destreg srcop1 srcop2 carryout carryin) - "As cris-arit5-int, but takes a register as parameter, not register number" - (cris-arit5-int arit size (regno destreg) srcop1 srcop2 carryout carryin) -) -(define-pmacro (cris-arit3-int arit size destregno srcop1 srcop2) - "As cris-arit5-int, but with carry-in same as carry-out" - (cris-arit5-int arit size destregno srcop1 srcop2 cbit cbit) -) -(define-pmacro (cris-arit3 arit size destreg srcop1 srcop2) - "As cris-arit3-int, but takes a register as parameter, not register number" - (cris-arit3-int arit size (regno destreg) srcop1 srcop2) -) -(define-pmacro (cris-arit arit size destreg srcop) - "As cris-arit3, but with destination same as srcop1" - (cris-arit3 arit size destreg destreg srcop) -) -(define-pmacro (cris-arit-3op arit size destsrcop2 srcop1 dest-3op) - "Similar to cris-arit3-int, but for prefixed operand only" - (cris-arit3-int arit size - (if SI (andif prefix-set (not inc)) - (regno dest-3op) - (regno destsrcop2)) - destsrcop2 srcop1) -) - -; Convenience macros to select a part of a value and its complement, for -; the <op>.b, <op>.w and <op>.d operations. -(define-pmacro (QI-part val) (and SI val #xff)) -(define-pmacro (non-QI-part val) (and SI val #xffffff00)) -(define-pmacro (HI-part val) (and SI val #xffff)) -(define-pmacro (non-HI-part val) (and SI val #xffff0000)) -(define-pmacro (SI-part val) val) -(define-pmacro (non-SI-part val) 0) -(define-pmacro - (set-subreg-gr-bw BWD gregno newval) - "Set a byte or word part or full dword of a general register" - (sequence - ((SI oldregval)) - (set oldregval (reg h-raw-gr gregno)) - (set (reg h-gr gregno) - (or SI ((.sym BWD -part) newval) ((.sym non- BWD -part) oldregval)))) -) -(define-pmacro (set-subreg-gr BWD gregno newval) - ((.sym set-subreg-gr- BWD) BWD gregno newval) -) -(define-pmacro (set-subreg-gr-SI SI gregno newval) - (set (reg h-gr gregno) newval) -) -(define-pmacro set-subreg-gr-HI set-subreg-gr-bw) -(define-pmacro set-subreg-gr-QI set-subreg-gr-bw) - -; MOVE.m Rs,Rd [ Rd | 011001mm | Rs ] -(dni-cdt-bwd - move "move.m r,R" - "move.m ${Rs},${Rd}" - (+ Rd MODE_REGISTER R_MOVE Rs) - (.pmacro - (BWD) - (sequence - ((BWD newval)) - (set newval Rs) - (set-subreg-gr BWD (regno Rd) newval) - (setf-move BWD newval))) -) - -; MOVE.D PC,Rd [ Rd | 01100110 | 1111 ] -; This insn is used in PIC code to find out the code address. It's an -; exception to the (guarded) non-implementation of PC operands in this -; file. -(dni-cdt-attr - movepcr "move.d PC,R" - (MACH-PC UNCOND-CTI) - "move.d PC,${Rd}" - (+ Rd MODE_REGISTER R_MOVE SIZE_DWORD (f-source 15)) - (sequence - ((SI pcval)) - (set pcval (add SI pc 2)) - (set Rd pcval) - (setf-move SI pcval)) -) - -; MOVEQ i,Rd [ Rd | 001001 | i ] -(dni-cdt - moveq "moveq" - "moveq $i,$Rd" - (+ Rd MODE_QUICK_IMMEDIATE Q_MOVEQ i) - (sequence - ((SI newval)) - (set newval i) - (set Rd newval) - (setf-moveq newval)) -) - -(define-pmacro (dni-cdt-sbw name comment syntax fmt fsem) - "Insn generator for insns with signed <op>.b and <op>.w variants" - (begin - (dni-cdt - (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) - (.splice (.unsplice fmt) SIGNED_BYTE) - (fsem QI)) - (dni-cdt - (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) - (.splice (.unsplice fmt) SIGNED_WORD) - (fsem HI))) -) - -; MOVS.z Rs,Rd [ Rd | 0100011z | Rs ] -(dni-cdt-sbw - movs "movs.m r,R" - "movs.m ${Rs},${Rd}" - (+ Rd MODE_REGISTER R_MOVX Rs) - (.pmacro - (BW) - (sequence - ((BW tmpops) (SI newval)) - (set tmpops Rs) - (set newval (ext SI tmpops)) - (set Rd newval) - (setf-move SI newval))) -) - -(define-pmacro (dni-cdt-ubw name comment syntax fmt fsem) - "Similar to dni-cdt-sbw but for unsigned operations" - (begin - (dni-cdt - (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) - (.splice (.unsplice fmt) UNSIGNED_BYTE) - (fsem QI)) - (dni-cdt - (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) - (.splice (.unsplice fmt) UNSIGNED_WORD) - (fsem HI))) -) - -; MOVU.z Rs,Rd [ Rd | 0100010z | Rs ] -(dni-cdt-ubw - movu "movu.m r,R" - "movu.m ${Rs},${Rd}" - (+ Rd MODE_REGISTER R_MOVX Rs) - (.pmacro - (BW) - (sequence - ((BW tmpops) (SI newval)) - (set tmpops Rs) - (set newval (zext SI tmpops)) - (set Rd newval) - (setf-move SI newval))) -) - -; (MOVE.m [PC+],Rd [ Rd | 111001mm | 1111 ]) -; For the moment, it doesn't seem worthwhile to make a dni-c-bwd macro; -; too many places to parametrize. -(dni-c-QI - movecbr "move.b [PC+],R" - "move.b ${sconst8},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_BYTE (f-source 15) sconst8) - (sequence - ((QI newval)) - (set newval sconst8) - (set-subreg-gr QI (regno Rd) newval) - (setf-move QI newval)) -) - -(dni-c-HI - movecwr "move.w [PC+],R" - "move.w ${sconst16},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_WORD (f-source 15) sconst16) - (sequence - ((HI newval)) - (set newval sconst16) - (set-subreg-gr HI (regno Rd) newval) - (setf-move HI newval)) -) - -(dni-c-SI - movecdr "move.d [PC+],R" - "move.d ${const32},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_DWORD (f-source 15) const32) - (sequence - ((SI newval)) - (set newval const32) - (set Rd newval) - (setf-move SI newval)) -) - -; (MOVS.z [PC+],Rd [ Rd | 1100011z | 1111 ]) -; Similarly, no likely net improvement for a dni-c-bw. -(dni-c-QI - movscbr "movs.b [PC+],R" - "movs.b ${sconst8},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_BYTE (f-source 15) sconst8) - (sequence - ((SI newval)) - ; FIXME: Make trunc unnecessary. - (set newval (ext SI (trunc QI sconst8))) - (set Rd newval) - (setf-move SI newval)) -) - -(dni-c-HI - movscwr "movs.w [PC+],R" - "movs.w ${sconst16},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_WORD (f-source 15) sconst16) - (sequence - ((SI newval)) - ; FIXME: Make trunc unnecessary. - (set newval (ext SI (trunc HI sconst16))) - (set Rd newval) - (setf-move SI newval)) -) - -; (MOVU.z [PC+],Rd [ Rd | 1100010z | 1111 ]) -(dni-c-QI - movucbr "movu.b [PC+],R" - "movu.b ${uconst8},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_BYTE (f-source 15) uconst8) - (sequence - ((SI newval)) - ; FIXME: Make trunc unnecessary. - (set newval (zext SI (trunc QI uconst8))) - (set Rd newval) - (setf-move SI newval)) -) - -(dni-c-HI - movucwr "movu.w [PC+],R" - "movu.w ${uconst16},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_WORD (f-source 15) uconst16) - (sequence - ((SI newval)) - ; FIXME: Make trunc unnecessary. - (set newval (zext SI (trunc HI uconst16))) - (set Rd newval) - (setf-move SI newval)) -) - -; ADDQ j,Rd [ Rd | 001000 | j ] -(dni-cdt - addq "addq j,Rd" - "addq $j,$Rd" - (+ Rd MODE_QUICK_IMMEDIATE Q_ADDQ j) - (cris-arit add SI Rd j) -) - -; SUBQ j,Rd [ Rd | 001010| j ] -(dni-cdt - subq "subq j,Rd" - "subq $j,$Rd" - (+ Rd MODE_QUICK_IMMEDIATE Q_SUBQ j) - (cris-arit sub SI Rd j) -) - -; Convenience macros for insns with a memory operand. -(define-pmacro - (dni-cmt-attr-tim name comment attr syntax fmt semantics timing) - "dni with memory-access" - (dni name comment attr syntax - ; Specifying MODE_INDIRECT and MODE_AUTOINCREMENT in this - ; manner makes the autoincrementness handily available. - ; It also effectively excludes non-memory use of dni-cmt. - (.splice (.unsplice fmt) MODEMEMP_YES inc) - semantics - timing) -) - -(define-pmacro (dni-cmt-attr name comment attr syntax fmt semantics) - "dni with read memory-access timing" - (dni-cmt-attr-tim name comment attr syntax fmt semantics - (cris-mem-timing)) -) - -(define-pmacro (dni-cmwt-attr name comment attr syntax fmt semantics) - "dni with write memory-access timing" - (dni-cmt-attr-tim name comment attr syntax fmt semantics - (cris-mem-write-timing)) -) - -(define-pmacro QI-size 1) -(define-pmacro HI-size 2) -(define-pmacro SI-size 4) - -(define-pmacro (cris-get-mem size regop) - "Handle reading memory in <size>, with source address register\ - (read once, maybe set once) in <regop> or prefixed" - (sequence - size - ((SI addr) (size tmp-mem) (BI postinc)) - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; Get the address from somewhere. - (set addr - (if SI (eq prefix-set 0) - ; If the insn was prefixed, it's in the prefix-register. - regop - prefixreg)) - - ; Get the memory contents. - (set tmp-mem (mem size addr)) - - ; For non-prefixed post-increment, we increment the address by the - ; size of the memory access. - (if (ne postinc 0) - (sequence - () - (if (eq prefix-set 0) - (set addr (add addr (.sym size -size)))) - ; Update the source-register for post-increments. - (set regop addr))) - - ; Don't forget the return-value. - tmp-mem) -) - -(define-pmacro (cris-set-mem size regop value) - "Handle writing <value> of <size> to memory, with memory address register\ - (read once, maybe set once) in <regop> or prefixed." - (sequence - ((SI addr) (BI postinc)) - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; Get the address from somewhere. - (set addr - (if SI (eq prefix-set 0) - ; If the insn was prefixed, it's in the prefix-register. - regop - prefixreg)) - - ; Set the memory contents. Integral-write semantics apply. - ; FIXME: currently v32 only; when proper semantics needed, fix v10. - (if (andif current-mach-is-v32 (ne xbit 0)) - (if (eq pbit 0) - (sequence - () - (set (mem size addr) value) - ; Write failures are signalled (by whatever entity "sends - ; the signal") by setting P at time of the write above, if X - ; is set. Here, we just need to copy P into C. - (set cbit pbit)) - (set cbit 1)) - (set (mem size addr) value)) - - ; For non-prefixed post-increment, we increment the address by the - ; size of the memory access. As for the integral-write, this needs to - ; be tweaked for pre-v32: increment should have been performed if - ; there's a fault at the memory access above. - (if (ne postinc 0) - (sequence - () - (if (eq prefix-set 0) - (set addr (add addr (.sym size -size)))) - ; Update the source-register for post-increments. - (set regop addr)))) -) - -(define-pmacro - (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem timing) - "Core generator macro for insns with <op>.b, <op>.w and <op>.d variants\ - and a memory operand." - (begin - (dni-cmt-attr-tim - (.sym name .b-m) - (.str "byte mem " comment) - attr - (.str name ".b " syntax) - (.splice (.unsplice fmt) SIZE_BYTE) - (fsem QI) - timing) - (dni-cmt-attr-tim - (.sym name .w-m) - (.str "word mem " comment) - attr - (.str name ".w " syntax) - (.splice (.unsplice fmt) SIZE_WORD) - (fsem HI) - timing) - (dni-cmt-attr-tim - (.sym name .d-m) - (.str "dword mem " comment) - attr - (.str name ".d " syntax) - (.splice (.unsplice fmt) SIZE_DWORD) - (fsem SI) - timing)) -) - -; Further refinement macros. -(define-pmacro (dni-cmt-bwd-attr name comment attr syntax fmt fsem) - (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem - (cris-mem-timing)) -) - -(define-pmacro (dni-cmwt-bwd name comment syntax fmt fsem) - (dni-cmt-bwd-attr-tim name comment () syntax fmt fsem - (cris-mem-write-timing)) -) - -(define-pmacro (dni-cmt-bwd name comment syntax fmt fsem) - (dni-cmt-bwd-attr name comment () syntax fmt fsem) -) - -(define-pmacro (dni-cmt-sbw name comment syntax fmt fsem) - "Core generator macro for insns with <op>.b and <op>.w variants\ - and a signed memory operand." - (begin - (dni-cmt-attr - (.sym name .b-m) (.str "byte mem " comment) - () - (.str name ".b " syntax) - (.splice (.unsplice fmt) SIGNED_BYTE) - (fsem QI)) - (dni-cmt-attr - (.sym name .w-m) (.str "word mem " comment) - () - (.str name ".w " syntax) - (.splice (.unsplice fmt) SIGNED_WORD) - (fsem HI))) -) - -(define-pmacro (dni-cmt-ubw name comment syntax fmt fsem) - "Core generator macro for insns with <op>.b and <op>.w variants\ - and an unsigned memory operand." - (begin - (dni-cmt-attr - (.sym name .b-m) (.str "byte mem " comment) - () - (.str name ".b " syntax) - (.splice (.unsplice fmt) UNSIGNED_BYTE) - (fsem QI)) - (dni-cmt-attr - (.sym name .w-m) (.str "word mem " comment) - () - (.str name ".w " syntax) - (.splice (.unsplice fmt) UNSIGNED_WORD) - (fsem HI))) -) - -; CMP.m Rs,Rd [ Rd | 011011mm | Rs ] -(dni-cdt-bwd - cmp-r "compare register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_CMP Rs) - (.pmacro - (BWD) - (cris-arit6-int - sub BWD (.pmacro (sz regno val) (nop)) 0 - Rd Rs cbit cbit)) -) - -; CMP.m [Rs],Rd [ Rd | 101011mm | Rs ] -; CMP.m [Rs+],Rd [ Rd | 111011mm | Rs ] -(dni-cmt-bwd - cmp-m "compare memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_CMP Rs Rd) - (.pmacro - (BWD) - (cris-arit6-int - sub BWD (.pmacro (sz regno val) (nop)) 0 - Rd (cris-get-mem BWD Rs) cbit cbit)) -) - -; (CMP.m [PC+],Rd [ Rd | 111011mm | 1111 ]) -(dni-c-QI - cmpcbr "cmp constant byte to register" - "cmp.b $sconst8,$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_BYTE (f-source 15) sconst8) - (cris-arit6-int - sub QI (.pmacro (sz regno val) (nop)) 0 - Rd (trunc QI sconst8) cbit cbit) -) - -(dni-c-HI - cmpcwr "cmp constant word to register" - "cmp.w $sconst16,$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_WORD (f-source 15) sconst16) - (cris-arit6-int - sub HI (.pmacro (sz regno val) (nop)) 0 - Rd (trunc HI sconst16) cbit cbit) -) - -(dni-c-SI - cmpcdr "cmp constant dword to register" - "cmp.d $const32,$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_DWORD (f-source 15) const32) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd const32 cbit cbit) -) - -; CMPQ i,Rd [ Rd | 001011 | i ] -(dni-cdt - cmpq "cmpq i,Rd" - "cmpq $i,$Rd" - (+ Rd MODE_QUICK_IMMEDIATE Q_CMPQ i) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd i cbit cbit) -) - -; CMPS.z [Rs],Rd [ Rd | 1000111z | Rs ] -; CMPS.z [Rs+],Rd [ Rd | 1100111z | Rs ] -(dni-cmt-sbw - cmps-m "cmp sign-extended from memory to register" - "[${Rs}${inc}],$Rd" - (+ Rd INDIR_CMPX Rs) - (.pmacro - (BW) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit)) -) - -; (CMPS.z [PC+],Rd [ Rd | 1100111z | 1111 ]) -(dni-c-QI - cmpscbr "cmp sign-extended constant byte to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_BYTE (f-source 15) sconst8) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd (ext SI (trunc QI sconst8)) cbit cbit) -) -(dni-c-HI - cmpscwr "cmp sign-extended constant word to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_WORD (f-source 15) sconst16) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd (ext SI (trunc HI sconst16)) cbit cbit) -) - -; CMPU.z [Rs],Rd [ Rd | 1000110z | Rs ] -; CMPU.z [Rs+],Rd [ Rd | 1100110z | Rs ] -(dni-cmt-ubw - cmpu-m "cmp zero-extended from memory to register" - "[${Rs}${inc}],$Rd" - (+ Rd INDIR_CMPX Rs) - (.pmacro - (BW) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit)) -) - -; (CMPU.z [PC+],Rd [ Rd | 1100110z | 1111 ]) -(dni-c-QI - cmpucbr "cmp zero-extended constant byte to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_BYTE (f-source 15) uconst8) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd (zext SI (trunc QI uconst8)) cbit cbit) -) -(dni-c-HI - cmpucwr "cmp zero-extended constant word to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_WORD (f-source 15) uconst16) - (cris-arit6-int - sub SI (.pmacro (sz regno val) (nop)) 0 - Rd (zext SI (trunc HI uconst16)) cbit cbit) -) - -; MOVE.m [Rs],Rd [ Rd | 101001mm | Rs ] -; MOVE.m [Rs+],Rd [ Rd | 111001mm | Rs ] -(dni-cmt-bwd - move-m "move from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_MOVE_M_R Rs Rd) - (.pmacro - (BWD) - (sequence - ((SI tmp)) - (set tmp (cris-get-mem BWD Rs)) - (set-subreg-gr - BWD - (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) - tmp) - (setf-move BWD tmp))) -) - -; MOVS.z [Rs],Rd [ Rd | 1000011z | Rs ] -; MOVS.z [Rs+],Rd [ Rd | 1100011z | Rs ] -(dni-cmt-sbw - movs-m "movs from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_MOVX Rs Rd) - (.pmacro - (BW) - (sequence - ((SI tmp)) - (set tmp (ext SI (cris-get-mem BW Rs))) - (if (andif prefix-set (not inc)) - (set Rs tmp) - (set Rd tmp)) - (setf-move SI tmp))) -) - -; MOVU.z [Rs],Rd [ Rd | 1000010z | Rs ] -; MOVU.z [Rs+],Rd [ Rd | 1100010z | Rs ] -(dni-cmt-ubw - movu-m "movu from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_MOVX Rs Rd) - (.pmacro - (BW) - (sequence - ((SI tmp)) - (set tmp (zext SI (cris-get-mem BW Rs))) - (if (andif prefix-set (not inc)) - (set Rs tmp) - (set Rd tmp)) - (setf-move SI tmp))) -) - -; MOVE Rs,Pd [ Pd | 01100011 | Rs ] -(.splice - begin - (.unsplice - (.map - (.pmacro - (VER) - (dni - (.sym move-r-spr VER) - "Move from general register to special register" - ((MACH (.sym cris VER))) - "move ${Rs},${Pd}" - (+ RFIX_MOVE_R_S MODE_REGISTER SIZE_FIXED Rs Pd) - (sequence - ((SI tmp) (SI rno)) - (set tmp Rs) - (set rno (regno Pd)) - (cond - ; See reg-sr setter for most of the special-register semantics. - ; The sanity check for known read-only registers is for program - ; debug help; the real insn would be harmless and have no effect. - ; CGEN-FIXME: regno of symbolic h-sr names doesn't work here. - ((orif (orif (eq rno 0) (eq rno 1)) (orif (eq rno 4) (eq rno 8))) - (error "move-r-spr: trying to set a read-only special register")) - (else (set Pd tmp))) - (reset-x-p)) - (cris-reg-sr-timing))) - (cris-cpu-models))) -) - -(define-pmacro (dni-cdt-ver-attr name comment fattr syntax fmt fsem) - "Generator for each MACH, using default timing." - (.splice - begin - (.unsplice - (.map - (.pmacro (v) (dni-cdt-attr name comment (fattr v) syntax fmt (fsem v))) - (cris-cpu-models)))) -) - -; MOVE Ps,Rd [ Ps | 01100111 | Rd ] -; Note that in the insn format, the Rd operand is in the Rs field (the -; Rd field by the definition used everywhere else is the Ps position in -; this insn). -; It gets a little weird here because we can't get this insn into a -; define-pmacro unless we make named pmacros for e.g. a separate attr -; function and a semantics function: a .pmacro can't refer to the -; parameters of the outer define-pmacro. (The manual refers to this as -; not implementing "lexical scoping"). -(.splice - begin - (.unsplice - (.map - (.pmacro - (VER) - (dni-cdt-attr - (.sym move-spr-r VER) - "Move from special register to general register" - ((MACH (.sym cris VER))) - "move ${Ps},${Rd-sfield}" - (+ Ps RFIX_MOVE_S_R MODE_REGISTER SIZE_FIXED Rd-sfield) - (sequence - ((SI grno) (SI prno) (SI newval)) - (set prno (regno Ps)) - ; CGEN-FIXME: Can't use the following and then "grno" below because - ; CGEN will emit a "tmp_grno" *also* in decodev32.c:crisv32f_decode - ; (set grno (regno Rd-sfield)) - (set newval Ps) - (.splice - cond - (.unsplice - (.map - (.pmacro - (r) - ((eq prno (.cadr2 r)) - (set-subreg-gr (.car2 r) (regno Rd-sfield) newval))) - ((.sym cris-implemented-readable-specregs- VER)))) - (else (error "move-spr-r from unimplemented register"))) - (reset-x-p)))) - (cris-cpu-models))) -) - -; MOVE Ps,PC [ Ps | 01100111 | 1111 ] -; The move-special-register-to-pc insns are return-type instructions and -; have to be special-cased to get the delay-slot and avoid being indicated -; as invalid. -(dni-cdt-attr - ret-type - "ret-type" - (MACH-PC) - "ret/reti/retb" - (+ Ps MODE_REGISTER RFIX_MOVE_S_R SIZE_FIXED (f-source 15)) - (sequence - ((SI retaddr)) - (set retaddr Ps) - (reset-x-p) - (delay 1 (set pc retaddr))) -) - -; MOVE [Rs],Pd [ Pd | 10100011 | Rs ] -; MOVE [Rs+],Pd [ Pd | 11100011 | Rs ] -; We make variants that loads constants or memory for each MACH version, -; since each consider some subset of the "special registers" to have -; different sizes. FIXME: Should be able to simplify this. -(.splice - begin - (.unsplice - (.map - (.pmacro - (VER) - (dni - (.sym move-m-spr VER) - "Move from memory to special register" - ((MACH (.sym cris VER))) - "move [${Rs}${inc}],${Pd}" - (+ Pd INFIX_MOVE_M_S MODEMEMP_YES inc SIZE_FIXED Rs) - (sequence - ((SI rno) (SI newval)) - (set rno (regno Pd)) - (.splice - cond - ; No sanity check for constant special register here, since the - ; memory read side-effect or post-increment may be the goal, or - ; for pre-v32 a prefix assignment side-effect. - (.unsplice - (.map - (.pmacro - (r) - ((eq rno (.cadr2 r)) - (set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs))))) - ((.sym cris-implemented-writable-specregs- VER)))) - (else (error "Trying to set unimplemented special register"))) - (set Pd newval) - (reset-x-p)) - (cris-mem-sr-timing))) - (cris-cpu-models))) -) - -(define-pmacro QI-operand sconst8) -(define-pmacro HI-operand sconst16) -(define-pmacro SI-operand const32) - -(define-pmacro - (cris-move-c-spr VER VERFN) - "Generator for loading constant into special register" - (.splice - begin - (.unsplice - (.map - (.pmacro - (srdef v) - (dni - (.sym move-c-spr v -p (.cadr2 srdef)) - (.str "Move constant to special register p" (.cadr2 srdef)) - ((MACH (.sym cris v))) - (.str "move ${" (.sym (.car2 srdef) -operand) "},${Pd}") - ; We use Pd in semantics without naming it in the format (which - ; would CGEN-FIXME: cause a CGEN error for some reason, likely - ; related to specifying an insn field multiple times). This - ; currently works and is guarded with test-cases (specifically - ; wrt. the timing model) but may need to be tweaked in the future. - ; Note that using instead (ifield f-dest) causes incorrect timing - ; model to be generated; the timing model requires that Pd is set. - (+ (f-dest (.cadr2 srdef)) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED - (f-source 15) (.sym (.car2 srdef) -operand)) - (sequence - () - (set Pd (.sym (.car2 srdef) -operand)) ; (reg h-sr (.cadr2 srdef)) - (reset-x-p)) - ((.sym cris-timing-const-sr- (.car2 srdef))))) - ((.sym cris-implemented-specregs-const- VER)) - (.map VERFN ((.sym cris-implemented-specregs-const- VER)))))) -) - -; CGEN-FIXME: -; Unfortunately we can't iterate over the list of models due to the -; problem with referring to the parameters of a surrounding pmacro from -; within an enclosed .pmacro (perhaps related to "lexical scoping"). -; We get e.g. 'insn already defined:: (move-c-sprvn-p0)' with this: -;(.splice -; begin (.unsplice (.map (.pmacro (vn) (cris-move-c-spr vn (.pmacro (x) vn))) -; (cris-cpu-models))) -;) -(cris-move-c-spr v0 (.pmacro (x) v0)) -(cris-move-c-spr v3 (.pmacro (x) v3)) -(cris-move-c-spr v8 (.pmacro (x) v8)) -(cris-move-c-spr v10 (.pmacro (x) v10)) -(cris-move-c-spr v32 (.pmacro (x) v32)) - -; MOVE Ps,[Rd] [ Ps | 10100111 | Rd ] -; MOVE Ps,[Rd+] [ Ps | 11100111 | Rd ] -(.splice - begin - (.unsplice - (.map - (.pmacro - (VER) - (dni-cmwt-attr - (.sym move-spr-m VER) - "Move from special register to memory" - ((MACH (.sym cris VER))) - "move ${Ps},[${Rd-sfield}${inc}]" - (+ INFIX_MOVE_S_M SIZE_FIXED Rd-sfield Ps) - (sequence - ((SI rno)) - (set rno (regno Ps)) - (.splice - cond - (.unsplice - (.map - (.pmacro - (r) - ((eq rno (.cadr2 r)) - (cris-set-mem (.car2 r) Rd-sfield Ps))) - ((.sym cris-implemented-readable-specregs- VER)))) - (else (error "write from unimplemented special register"))) - (reset-x-p)))) - (cris-cpu-models))) -) - -; SBFS [Rs(+)] -; Instruction format: |0 0 1 1 1 m 1 1 0 1 1 1| Dest. | -(dni-cdt-attr - sbfs - "sbfs" - ((MACH crisv10)) - "sbfs [${Rd-sfield}${inc}]" - (+ (f-dest 3) INFIX_SBFS SIZE_FIXED MODEMEMP_YES inc Rd-sfield) - (error "SBFS isn't implemented") -) - -; MOVE Ss,Rd [ Ss | 11110111 | Rd ] -(dni-cdt-attr - move-ss-r - "move from support register to general register" - (MACH-V32) - "move ${Ss},${Rd-sfield}" - (+ Ss INFIX_MOVE_SS SIZE_FIXED (f-mode 3) Rd-sfield) - (sequence - () - (set Rd-sfield Ss) - (reset-x-p)) -) - -; MOVE Rs,Sd [ Sd | 10110111 | Rs ] -(dni-cdt-attr - move-r-ss - "move from general register to support register" - (MACH-V32) - "move ${Rs},${Sd}" - (+ Sd INFIX_MOVE_SS SIZE_FIXED (f-mode 2) Rs) - (sequence - () - (set Sd Rs) - (reset-x-p)) -) - -; MOVEM Rs,[Rd] [ Rs | 10111111 | Rd ] -; MOVEM Rs,[Rd+] [ Rs | 11111111 | Rd ] - -(define-pmacro (movem-to-mem-step regn) - ; Without the SI attribute, UINT is generated, which isn't supported by - ; the sim framework. - (if (ge SI (regno Rs-dfield) regn) - (sequence - ((SI tmp)) - (set tmp (reg h-gr regn)) - (set (mem SI addr) tmp) - (set addr (add addr 4)))) -) - -(dni - movem-r-m - "movem to memory" - (MACH-PRE-V32) - "movem ${Rs-dfield},[${Rd-sfield}${inc}]" - (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) - (sequence - ((SI addr) (BI postinc)) - ; FIXME: A copy of what's in cris-get-mem. - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; CGEN-FIXME: Kludge to work around a CGEN bug: it doesn't see that - ; Rs-dfield is used as an input, causing the timing model to be wrong. - (sequence ((SI dummy)) (set dummy Rs-dfield)) - - ; Get the address from somewhere. If the insn was prefixed, it's in - ; the prefix-register. - (set addr - (if SI (eq prefix-set 0) - Rd-sfield - prefixreg)) - - (.splice - sequence () - (.unsplice (.map movem-to-mem-step (.iota 16 15 -1)))) - - ; Update the source-register for post-increments. - (if (ne postinc 0) - (set Rd-sfield - (if SI (eq prefix-set 0) addr prefixreg))) - (reset-x-p)) - (simplecris-movem-timing) -) - -(dni - movem-r-m-v32 - "movem to memory" - (MACH-V32) - "movem ${Rs-dfield},[${Rd-sfield}${inc}]" - (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) - (sequence - ((SI addr) (BI postinc)) - ; FIXME: Mostly a copy of what's in cris-get-mem. - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; CGEN-FIXME: See movem-r-m. - (sequence ((SI dummy)) (set dummy Rs-dfield)) - - (set addr Rd-sfield) - - (.splice - sequence () - (.unsplice (.map movem-to-mem-step (.iota 16)))) - - ; Update the source-register for post-increments. - (if (ne postinc 0) - (set Rd-sfield addr)) - (reset-x-p)) - ; Unit u-mem must be specified before the u-movem-* for memory address - ; register stall count to be right. - ((crisv32 (unit u-mem) (unit u-movem-rtom) (unit u-exec-movem) - (unit u-mem-w))) -) - -; MOVEM [Rs],Rd [ Rd | 10111011 | Rs ] -; MOVEM [Rs+],Rd [ Rd | 11111011 | Rs ] - -(define-pmacro - (movem-to-reg-step regn) - ; Without the SI attribute, UINT is generated, which isn't supported by - ; the sim framework. - (if (ge SI (regno Rd) regn) - (sequence - ((SI tmp)) - (set tmp (mem SI addr)) - (set (reg h-gr regn) tmp) - (set addr (add addr 4)))) -) - -(dni - movem-m-r - "movem to register" - (MACH-PRE-V32) - "movem [${Rs}${inc}],${Rd}" - (+ Rd INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs) - (sequence - ((SI addr) (BI postinc)) - ; FIXME: Mostly a copy of what's in cris-get-mem. - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; Get the address from somewhere. If the insn was prefixed, it's in - ; the prefix-register. - (set addr - (if SI (eq prefix-set 0) - Rs - prefixreg)) - - ; CGEN-FIXME: See movem-r-m. - (sequence ((SI dummy)) (set dummy Rd)) - - (.splice - sequence () - ; The first movem step is left out because it can't happen; it's for - ; PC destination. See the pattern below. - (.unsplice (.map movem-to-reg-step (.iota 15 14 -1)))) - - ; Update the source-register for post-increments. - ; FIXME: No postinc-prefixed for v0 IIRC. - (if (ne postinc 0) - (set Rs (if SI (eq prefix-set 0) addr prefixreg))) - (reset-x-p)) - (simplecris-movem-timing) -) - -; (MOVEM [Rs],PC [ 1111 | 10111011 | Rs ]) -; (MOVEM [Rs+],PC [ 1111 | 11111011 | Rs ]) -; We have to special-case it for PC destination; used in longjump. -; We shouldn't *have* to special-case it; the main reason is (FIXME:) -; misgeneration of the simulator when the PC case is folded into the -; generic PRE-V32 movem; possibly related to then being a COND-CTI rather -; than an UNCOND-CTI. -(dni-cmt-attr - movem-m-pc - "movem to register, ending with PC" - (MACH-PRE-V32) - "movem [${Rs}${inc}],${Rd}" - (+ (f-dest 15) INFIX_MOVEM_M_R SIZE_FIXED Rs) - (sequence - ((SI addr) (BI postinc)) - ; FIXME: Mostly a copy of what's in cris-get-mem. - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; Get the address from somewhere. If the insn was prefixed, it's in - ; the prefix-register. - (set addr - (if SI (eq prefix-set 0) - Rs - prefixreg)) - - ; FIXME: Add kludge here too *and* a test-case. - - (.splice - sequence () - ; The first movem step is for PC destination, used in longjmp. - (set pc (mem SI addr)) - (set addr (add addr 4)) - (.unsplice - (.map - (.pmacro - (regn) - (sequence - ((SI tmp)) - (set tmp (mem SI addr)) - (set (reg h-gr regn) tmp) - (set addr (add addr 4)))) - (.iota 15 14 -1)))) - - ; Update the source-register for post-increments. - ; FIXME: No postinc-prefixed for v0. - (if (ne postinc 0) - (set Rs (if SI (eq prefix-set 0) addr prefixreg))) - (reset-x-p)) -) - -(dni - movem-m-r-v32 - "movem to register" - (MACH-V32) - "movem [${Rs}${inc}],${Rd}" - (+ INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs Rd) - (sequence - ((SI addr) (BI postinc)) - ; FIXME: A copy of what's in cris-get-mem - - ; Cache the incrementness of the operand. - (set postinc inc) - - ; Get the address from somewhere. - (set addr Rs) - - ; CGEN-FIXME: See movem-r-m. - (sequence ((SI dummy)) (set dummy Rd)) - - (.splice - sequence () - (.unsplice (.map movem-to-reg-step (.iota 16)))) - - ; Update the source-register for post-increments. - ; FIXME: No postinc-prefixed for v0 IIRC. - (if (ne postinc 0) - (set Rs addr)) - (reset-x-p)) - ; u-mem must be specified before the u-movem-* for memory source - ; register stall count to be right. - ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-movem-mtor) - (unit u-exec-movem))) -) - -; ADD.m Rs,Rd [ Rd | 011000mm | Rs ] -(dni-cdt-bwd - add "add from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_ADD Rs) - (.pmacro (BWD) (cris-arit add BWD Rd Rs)) -) - -; ADD.m [Rs],Rd [ Rd | 101000mm | Rs ] -; ADD.m [Rs+],Rd [ Rd | 111000mm | Rs ] -(dni-cmt-bwd - add-m "add from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_ADD Rs Rd) - (.pmacro (BWD) (cris-arit-3op add BWD Rd (cris-get-mem BWD Rs) Rs)) -) -; (ADD.m [PC+],Rd [ Rd | 111000mm | 1111 ]) -(dni-c-QI - addcbr "add constant byte to register" - "add.b ${sconst8}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_BYTE (f-source 15) sconst8) - (cris-arit add QI Rd sconst8) -) - -(dni-c-HI - addcwr "add constant word to register" - "add.w ${sconst16}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_WORD (f-source 15) sconst16) - (cris-arit add HI Rd sconst16) -) - -(dni-c-SI - addcdr "add constant dword to register" - "add.d ${const32}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) - (cris-arit add SI Rd const32) -) - -; (ADD.D [PC+],PC [ 1111 | 11100010 | 1111 ]) -; This insn is used for DSO-local jumps in PIC code. -(dni - addcpc "Relative jump by adding constant to PC" - (MACH-PC) - "add.d ${sconst32},PC" - (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) - (sequence - ((SI newpc) (SI oldpc) (SI offs)) - (set offs const32) - (set oldpc (add SI pc 6)) - (set newpc (add SI oldpc offs)) - (set pc newpc) - (setf-arit SI add oldpc offs newpc cbit)) - (simplecris-common-timing ((unit u-const32) (unit u-stall) (unit u-exec))) -) - -; ADDS.z Rs,Rd [ Rd | 0100001z | Rs ] -(dni-cdt-sbw - adds "add sign-extended from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_ADDX Rs) - (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -ext) (trunc BW Rs)))) -) - -; ADDS.z [Rs],Rd [ Rd | 1000001z | Rs ] -; ADDS.z [Rs+],Rd [ Rd | 1100001z | Rs ] -(dni-cmt-sbw - adds-m "add sign-extended from memory to register" - "[${Rs}${inc}],$Rd" - (+ Rd INDIR_ADDX Rs) - (.pmacro (BW) (cris-arit-3op add SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) -) - -; (ADDS.z [PC+],Rd [ Rd | 1100001z | 1111 ]) -(dni-c-QI - addscbr "add sign-extended constant byte to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_BYTE (f-source 15) sconst8) - (cris-arit add SI Rd (ext SI (trunc QI sconst8))) -) -(dni-c-HI - addscwr "add sign-extended constant word to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_WORD (f-source 15) sconst16) - (cris-arit add SI Rd (ext SI (trunc HI sconst16))) -) - -; (ADDS.w [],PC [ 1111 | 10000011 | 1111 ]) -; For a PC destination, we support only the two-operand case -; (dest == src), which is used in switch/case statements. -; FIXME: Should implement ADD.D [PC],PC and ADDS.B [PC],PC for use if/when -; implementing CASE_VECTOR_SHORTEN_MODE. -(dni - addspcpc "add sign-extended prefixed arg to PC" - (MACH-PC) - "adds.w [PC],PC" - (+ (f-dest 15) MODE_INDIRECT INDIR_ADDX SIGNED_WORD (f-source 15)) - (sequence - ((SI newpc) (SI oldpc) (HI offs)) - (if (not prefix-set) - (error "Unexpected adds.w [PC],PC without prefix")) - ; We don't use cris-get-mem but instead special-case this one, since we - ; have most instruction fields fixed where cris-get-mem expects - ; field-parametrization by certain names. - (set offs (mem HI prefixreg)) - (set oldpc (add SI pc 2)) - (set newpc (add SI oldpc offs)) - (set pc newpc) - (setf-arit SI add oldpc (ext SI offs) newpc cbit)) - (simplecris-common-timing ((unit u-mem) (unit u-stall) (unit u-exec))) -) - -; ADDU.z Rs,Rd [ Rd | 0100000z | Rs ] -(dni-cdt-ubw - addu "add zero-extended from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_ADDX Rs) - (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -zext) (trunc BW Rs)))) -) - -; ADDU.z [Rs],Rd [ Rd | 1000000z | Rs ] -; ADDU.z [Rs+],Rd [ Rd | 1100000z | Rs ] -(dni-cmt-ubw - addu-m "add zero-extended from memory to register" - "[${Rs}${inc}],$Rd" - (+ Rd INDIR_ADDX Rs) - (.pmacro (BW) - (cris-arit-3op add SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) -) - -; (ADDU.z [PC+],Rd [ Rd | 1100000z | 1111 ]) -(dni-c-QI - adducbr "add zero-extended constant byte to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_BYTE (f-source 15) sconst8) - (cris-arit add SI Rd (zext SI (trunc QI sconst8))) -) -(dni-c-HI - adducwr "add zero-extended constant word to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_WORD (f-source 15) sconst16) - (cris-arit add SI Rd (zext SI (trunc HI sconst16))) -) - -; SUB.m Rs,Rd [ Rd | 011010mm | Rs ] -(dni-cdt-bwd - sub "subtract from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_SUB Rs) - (.pmacro (BWD) (cris-arit sub BWD Rd Rs)) -) - -; SUB.m [Rs],Rd [ Rd | 101010mm | Rs ] -; SUB.m [Rs+],Rd [ Rd | 111010mm | Rs ] -(dni-cmt-bwd - sub-m "subtract from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_SUB Rs Rd) - (.pmacro (BWD) (cris-arit-3op sub BWD Rd (cris-get-mem BWD Rs) Rs)) -) - -; (SUB.m [PC+],Rd [ Rd | 111010mm | 1111 ] -(dni-c-QI - subcbr "subtract constant byte from register" - "sub.b ${sconst8}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_BYTE (f-source 15) sconst8) - (cris-arit sub QI Rd sconst8) -) - -(dni-c-HI - subcwr "subtract constant word from register" - "sub.w ${sconst16}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_WORD (f-source 15) sconst16) - (cris-arit sub HI Rd sconst16) -) - -(dni-c-SI - subcdr "subtract constant dword from register" - "sub.d ${const32}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_DWORD (f-source 15) const32) - (cris-arit sub SI Rd const32) -) - -; SUBS.z Rs,Rd [ Rd | 0100101z | Rs ] -(dni-cdt-sbw - subs "sub sign-extended from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_SUBX Rs) - (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -ext) (trunc BW Rs)))) -) - -; SUBS.z [Rs],Rd [ Rd | 1000101z | Rs ] -; SUBS.z [Rs+],Rd [ Rd | 1100101z | Rs ] -(dni-cmt-sbw - subs-m "sub sign-extended from memory to register" - "[${Rs}${inc}],$Rd" - (+ Rd INDIR_SUBX Rs) - (.pmacro (BW) - (cris-arit-3op sub SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) -) - -; (SUBS.z [PC+],Rd [ Rd | 1100101z | 1111 ]) -(dni-c-QI - subscbr "sub sign-extended constant byte to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_BYTE (f-source 15) sconst8) - (cris-arit sub SI Rd (ext SI (trunc QI sconst8))) -) -(dni-c-HI - subscwr "sub sign-extended constant word to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_WORD (f-source 15) sconst16) - (cris-arit sub SI Rd (ext SI (trunc HI sconst16))) -) - -; SUBU.z Rs,Rd [ Rd | 0100100z | Rs ] -(dni-cdt-ubw - subu "sub zero-extended from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_SUBX Rs) - (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -zext) (trunc BW Rs)))) -) - -; SUBU.z [Rs],Rd [ Rd | 1000100z | Rs ] -; SUBU.z [Rs+],Rd [ Rd | 1100100z | Rs ] -(dni-cmt-ubw - subu-m "sub zero-extended from memory to register" - "[${Rs}${inc}],$Rd" - (+ Rd INDIR_SUBX Rs) - (.pmacro (BW) - (cris-arit-3op sub SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) -) - -; (SUBU.z [PC+],Rd [ Rd | 1100100z | 1111 ]) -(dni-c-QI - subucbr "sub zero-extended constant byte to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_BYTE (f-source 15) sconst8) - (cris-arit sub SI Rd (zext SI (trunc QI sconst8))) -) -(dni-c-HI - subucwr "sub zero-extended constant word to register" - "[${Rs}${inc}],$Rd" - (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_WORD (f-source 15) sconst16) - (cris-arit sub SI Rd (zext SI (trunc HI sconst16))) -) - -; ADDC Rs,Rd [ Rd | 01010111 | Rs ] -(dni-cdt-attr - addc-r "addc from register to register" - (MACH-V32) - "addc $Rs,$Rd" - (+ Rd MODE_REGISTER RFIX_ADDC SIZE_FIXED Rs) - ; Since this is equivalent to "ax" plus "add.d Rs,Rd", we'll just do - ; that, semantically. - (sequence - () - (set-quiet xbit 1) - (cris-arit add SI Rd Rs)) -) - -; ADDC [Rs],Rd [ Rd | 10011010 | Rs ] -; ADDC [Rs+],Rd [ Rd | 11011010 | Rs ] -(dni-cmt-attr - addc-m "addc from memory to register" - (MACH-V32) - "addc [${Rs}${inc}],${Rd}" - (+ Rd INDIR_ADDC SIZE_DWORD Rs) - (sequence - () - (set-quiet xbit 1) - (cris-arit add SI Rd (cris-get-mem SI Rs))) -) - -; (ADDC [Rs+],Rd [ Rd | 11011010 | 1111 ]) -(dni-c-SI-attr - addc-c "addc constant to register" - (MACH-V32) - "addc ${const32},${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDC SIZE_DWORD (f-source 15) const32) - (sequence - () - (set-quiet xbit 1) - (cris-arit add SI Rd const32)) -) - -; LAPC [PC+],Rd [ Rd | 11010111 1111 ] -(dni-c-SI-attr - lapc-d "lapc.d" - (MACH-V32) - "lapc.d ${const32-pcrel},${Rd}" - (+ Rd MODE_AUTOINCREMENT INFIX_LAPC SIZE_FIXED (f-source 15) const32-pcrel) - (sequence - () - (set Rd const32-pcrel) - (reset-x-p)) -) - -; LAPCQ qo,Rd [ Rd | 10010111 | qo ] -(dni-cdt-attr - lapcq "lapcq" - (MACH-V32) - "lapcq ${qo},${Rd}" - (+ Rd MODE_INDIRECT INFIX_LAPC SIZE_FIXED qo) - (sequence - () - (set Rd qo) - (reset-x-p)) -) - -; ADDI Rs.m,Rd [ Rs | 010100mm | Rd ] -(dni-cdt-bwd - addi "addi" - "${Rs-dfield}.m,${Rd-sfield}" - (+ Rd-sfield MODE_REGISTER R_ADDI Rs-dfield) - (.pmacro - (BWD) - (sequence - () - (set Rd-sfield (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) - (reset-x-p))) -) - -; NEG.m Rs,Rd [ Rd | 010110mm | Rs ] -(dni-cdt-bwd - neg "neg.m Rs,Rd" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_NEG Rs) - (.pmacro (BWD) (cris-arit3 sub BWD Rd 0 Rs)) -) - -; TEST.m [Rs] [ 0000101110mm | Rs ] -; TEST.m [Rs+] [ 0000111110mm | Rs ] -(dni-cmt-bwd - test-m "test.m [Rs(+)]" - "[${Rs}${inc}]" - (+ (f-dest 0) INDIR_TEST Rs) - (.pmacro - (BWD) - (sequence - ((BWD tmpd)) - (set tmpd (cris-get-mem BWD Rs)) - ; This is supposed to be the same result as for cmpq 0,X, hence same code. - (cris-arit6-int - sub BWD (.pmacro (sz regno val) (nop)) 0 tmpd 0 cbit cbit))) -) - -; MOVE.m Rs,[Rd] [ Rs | 101111mm | Rd ] -; MOVE.m Rs,[Rd+] [ Rs | 111111mm | Rd ] - -(dni-cmwt-bwd - move-r-m "move.m R,[]" - "${Rs-dfield},[${Rd-sfield}${inc}]" - (+ Rs-dfield INDIR_MOVE_R_M Rd-sfield) - (.pmacro - (BWD) - (sequence - ((BWD tmpd)) - (set tmpd Rs-dfield) - (cris-set-mem BWD Rd-sfield tmpd) - (reset-x-p))) -) - -; MULS.m Rs,Rd [ Rd | 110100mm | Rs ] -(dni-bwd-attr - muls "muls.m Rs,Rd" - ((MACH crisv10,crisv32)) - "$Rs,$Rd" - (+ Rd MODE_MULS INDIR_MUL Rs) - (.pmacro - (BWD) - (sequence - ((DI src1) (DI src2) (DI tmpr)) - (set src1 (ext DI (trunc BWD Rs))) - (set src2 (ext DI (trunc BWD Rd))) - (set tmpr (mul src1 src2)) - (set Rd (trunc SI tmpr)) - (set mof (trunc SI (srl tmpr 32))) - (setf-arit DI muls src1 src2 tmpr cbit))) - ((crisv10 (unit u-multiply) (unit u-exec)) - (crisv32 (unit u-multiply) (unit u-exec))) -) - -; MULU.m Rs,Rd [ Rd | 100100mm | Rs ] -(dni-bwd-attr - mulu "mulu.m Rs,Rd" - ((MACH crisv10,crisv32)) - "$Rs,$Rd" - (+ Rd MODE_MULU INDIR_MUL Rs) - (.pmacro - (BWD) - (sequence - ((DI src1) (DI src2) (DI tmpr)) - (set src1 (zext DI (trunc BWD Rs))) - (set src2 (zext DI (trunc BWD Rd))) - (set tmpr (mul src1 src2)) - (set Rd (trunc SI tmpr)) - (set mof (trunc SI (srl tmpr 32))) - (setf-arit DI mulu src1 src2 tmpr cbit))) - ((crisv10 (unit u-multiply) (unit u-exec)) - (crisv32 (unit u-multiply) (unit u-exec))) -) - -; MCP Ps,Rd [ Ps | 01111111 | Rd ] -(dni-cdt-attr - mcp "Multiply Carry Propagation" - (MACH-V32) - "mcp $Ps,$Rd" - (+ Ps MODE_REGISTER RFIX_MCP SIZE_FIXED Rd-sfield) - (sequence - () - (set-quiet xbit 1) - (set-quiet zbit 1) - (cris-arit5 add SI Rd-sfield Rd-sfield Ps rbit rbit)) -) - -; MSTEP Rs,Rd [ Rd | 01111111 | Rs ] -(dni-cdt-attr - mstep "Multiply step" - (MACH-PRE-V32) - "mstep $Rs,$Rd" - (+ Rd MODE_REGISTER RFIX_MSTEP SIZE_FIXED Rs) - (sequence - ((SI tmpd) (SI tmps)) - (set tmps Rs) - (set tmpd (add (sll Rd 1) (if SI nbit tmps 0))) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; DSTEP Rs,Rd [ Rd | 01101111 | Rs ] -(dni-cdt - dstep "Division step" - "dstep $Rs,$Rd" - (+ Rd MODE_REGISTER RFIX_DSTEP SIZE_FIXED Rs) - (sequence - ((SI tmp) (SI tmps) (SI tmpd)) - (set tmps Rs) - (set tmp (sll Rd 1)) - (set tmpd (if SI (geu tmp tmps) (sub tmp tmps) tmp)) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; ABS Rs,Rd [ Rd | 01101011 | Rs ] -(dni-cdt - abs "Absolut Instruction" - "abs $Rs,$Rd" - (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs) - (sequence - ((SI tmpd)) - (set tmpd (abs Rs)) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; AND.m Rs,Rd [ Rd | 011100mm | Rs ] -(dni-cdt-bwd - and "And from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_AND Rs) - (.pmacro - (BWD) - (sequence - ((BWD tmpd)) - (set tmpd (and BWD Rd Rs)) - (set-subreg-gr BWD (regno Rd) tmpd) - (setf-move BWD tmpd))) -) - -; AND.m [Rs],Rd [ Rd | 101100mm | Rs ] -; AND.m [Rs+],Rd [ Rd | 111100mm | Rs ] -(dni-cmt-bwd - and-m "And from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_AND Rs Rd) - (.pmacro - (BWD) - (sequence - ((BWD tmpd)) - (set tmpd (and BWD Rd (cris-get-mem BWD Rs))) - (set-subreg-gr - BWD - (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) - tmpd) - (setf-move BWD tmpd))) -) - -; (AND.m [PC+],Rd [ Rd | 111100mm | 1111 ]) -(dni-c-QI - andcbr "And constant byte to register" - "and.b ${sconst8}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_BYTE (f-source 15) sconst8) - (sequence - ((QI tmpd)) - (set tmpd (and QI Rd sconst8)) - (set-subreg-gr QI (regno Rd) tmpd) - (setf-move QI tmpd)) -) - -(dni-c-HI - andcwr "And constant word to register" - "and.w ${sconst16}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_WORD (f-source 15) sconst16) - (sequence - ((HI tmpd)) - (set tmpd (and HI Rd sconst16)) - (set-subreg-gr HI (regno Rd) tmpd) - (setf-move HI tmpd)) -) - -(dni-c-SI - andcdr "And constant dword to register" - "and.d ${const32}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_DWORD (f-source 15) const32) - (sequence - ((SI tmpd)) - (set tmpd (and SI Rd const32)) - (set-subreg-gr SI (regno Rd) tmpd) - (setf-move SI tmpd)) -) - -; ANDQ i,Rd [ Rd | 001100 | i ] -(dni-cdt - andq "And quick-immediate to register" - "andq $i,$Rd" - (+ Rd MODE_QUICK_IMMEDIATE Q_ANDQ i) - (sequence - ((SI tmpd)) - (set tmpd (and SI Rd i)) - (set-subreg-gr SI (regno Rd) tmpd) - (setf-move SI tmpd)) -) - -; OR.m Rs,Rd [ Rd | 011101mm | Rs ] -(dni-cdt-bwd - orr "Or from register to register" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_OR Rs) - (.pmacro - (BWD) - (sequence - ((BWD tmpd)) - (set tmpd (or BWD Rd Rs)) - (set-subreg-gr BWD (regno Rd) tmpd) - (setf-move BWD tmpd))) -) - -; OR.m [Rs],Rd [ Rd | 101101mm | Rs ] -; OR.m [Rs+],Rd [ Rd | 111101mm | Rs ] -(dni-cmt-bwd - or-m "Or from memory to register" - "[${Rs}${inc}],${Rd}" - (+ INDIR_OR Rs Rd) - (.pmacro - (BWD) - (sequence - ((BWD tmpd)) - (set tmpd (or BWD Rd (cris-get-mem BWD Rs))) - (set-subreg-gr - BWD - (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) - tmpd) - (setf-move BWD tmpd))) -) - -; (OR.m [PC+],Rd [ Rd | 111101mm | 1111 ]) -(dni-c-QI - orcbr "Or constant byte to register" - "or.b ${sconst8}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_BYTE (f-source 15) sconst8) - (sequence - ((QI tmpd)) - (set tmpd (or QI Rd sconst8)) - (set-subreg-gr QI (regno Rd) tmpd) - (setf-move QI tmpd)) -) - -(dni-c-HI - orcwr "Or constant word to register" - "or.w ${sconst16}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_WORD (f-source 15) sconst16) - (sequence - ((HI tmpd)) - (set tmpd (or HI Rd sconst16)) - (set-subreg-gr HI (regno Rd) tmpd) - (setf-move HI tmpd)) -) - -(dni-c-SI - orcdr "Or constant dword to register" - "or.d ${const32}],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_DWORD (f-source 15) const32) - (sequence - ((SI tmpd)) - (set tmpd (or SI Rd const32)) - (set-subreg-gr SI (regno Rd) tmpd) - (setf-move SI tmpd)) -) - -; ORQ i,Rd [ Rd | 001101 | i ] -(dni-cdt - orq "Or quick-immediate to register" - "orq $i,$Rd" - (+ Rd MODE_QUICK_IMMEDIATE Q_ORQ i) - (sequence - ((SI tmpd)) - (set tmpd (or SI Rd i)) - (set-subreg-gr SI (regno Rd) tmpd) - (setf-move SI tmpd)) -) - -; XOR Rs,Rd [ Rd | 01111011 | Rs ] -(dni-cdt - xor "Xor from register to register" - "xor $Rs,$Rd" - (+ Rd MODE_REGISTER RFIX_XOR SIZE_FIXED Rs) - (sequence - ((SI tmpd)) - (set tmpd (xor SI Rd Rs)) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -(define-pmacro (swap-r x) - "Perform bit-wise swap within each byte" - (sequence - SI - ((SI tmpr)) - (set tmpr x) - (or (sll (and tmpr #x1010101) 7) - (or (sll (and tmpr #x2020202) 5) - (or (sll (and tmpr #x4040404) 3) - (or (sll (and tmpr #x8080808) 1) - (or (srl (and tmpr #x10101010) 1) - (or (srl (and tmpr #x20202020) 3) - (or (srl (and tmpr #x40404040) 5) - (srl (and tmpr #x80808080) 7))))))))) -) - -(define-pmacro (swap-b x) - "Perform byte-wise swap within each word" - (sequence - SI - ((SI tmpb)) - (set tmpb x) - (or (and (sll tmpb 8) #xff00ff00) - (and (srl tmpb 8) #xff00ff))) -) - -(define-pmacro (swap-w x) - "Perform word-wise swap within each dword" - (sequence - SI - ((SI tmpb)) - (set tmpb x) - (or (and (sll tmpb 16) #xffff0000) - (and (srl tmpb 16) #xffff))) -) - -(define-pmacro (swap-_ x) - "Do nothing swap-wise" - (error SI "SWAP without swap modifier isn't implemented") -) - -(define-pmacro (swap-n x) - "Perform bitwise not (that is, perform a not, not not perform)" - (inv x) -) - -(define-pmacro (swap-br x) "Combine swap-r and swap-b" (swap-r (swap-b x))) -(define-pmacro (swap-wr x) "Combine swap-r and swap-w" (swap-r (swap-w x))) -(define-pmacro (swap-wb x) "Combine swap-b and swap-w" (swap-b (swap-w x))) -(define-pmacro (swap-wbr x) "Combine swap-r and swap-wb" (swap-r (swap-wb x))) -(define-pmacro (swap-nr x) "Combine swap-r and swap-n" (swap-r (swap-n x))) -(define-pmacro (swap-nb x) "Combine swap-n and swap-b" (swap-b (swap-n x))) -(define-pmacro (swap-nbr x) "Combine swap-r and swap-nb" (swap-r (swap-nb x))) -(define-pmacro (swap-nw x) "Combine swap-n and swap-w" (swap-w (swap-n x))) -(define-pmacro (swap-nwr x) "Combine swap-r and swap-nw" (swap-r (swap-nw x))) -(define-pmacro (swap-nwb x) "Combine swap-b and swap-nw" (swap-b (swap-nw x))) -(define-pmacro (swap-nwbr x) "Combine swap-r and swap-nwb" (swap-r (swap-nwb x))) - -(define-pmacro (cris-swap swapcode val) - (sequence - SI - ((SI tmpcode) (SI tmpval) (SI tmpres)) - (set tmpcode swapcode) - (set tmpval val) - (.splice - cond - (.unsplice - (.map - (.pmacro - (x-swapcode x-swap) - ((eq tmpcode x-swapcode) - (set tmpres ((.sym swap- x-swap) tmpval)))) - (.iota 16) - (.splice _ (.unsplice cris-swap-codes))))) - tmpres) -) - -; NOT Rd alias for SWAPN Rd -(dni-cdt-attr - not "Not" - ((MACH crisv0,crisv3)) - "not ${Rs}" - (+ (f-dest 8) RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) - (sequence - ((SI tmp) (SI tmpd)) - (set tmp Rd-sfield) - (set tmpd (cris-swap 8 tmp)) - (set Rd-sfield tmpd) - (setf-move SI tmpd)) -) - -; SWAP<option> Rd [ N W B R | 01110111 | Rd ] -(dni-cdt-attr - swap "Swap" - ((MACH crisv8,crisv10,crisv32)) - "swap${swapoption} ${Rs}" - (+ swapoption RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) - (sequence - ((SI tmps) (SI tmpd)) - (set tmps Rd-sfield) - (set tmpd (cris-swap swapoption tmps)) - (set Rd-sfield tmpd) - (setf-move SI tmpd)) -) - -; ASR.m Rs,Rd [ Rd | 011110mm | Rs ] -(dni-cdt-bwd - asrr "Arithmetic shift right register count" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_ASR Rs) - (.pmacro - (BWD) - (sequence - ((BWD tmpd) (SI cnt1) (SI cnt2)) - (set cnt1 Rs) - (set cnt2 (if SI (ne (and cnt1 32) 0) 31 (and cnt1 31))) - (set tmpd (sra SI (ext SI (trunc BWD Rd)) cnt2)) - (set-subreg-gr BWD (regno Rd) tmpd) - (setf-move BWD tmpd))) -) - -; ASRQ c,Rd [ Rd | 0011101 | c ] -(dni-cdt - asrq "Arithmetic shift right quick-immediate count" - "asrq $c,${Rd}" - (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 1) c) - (sequence - ((SI tmpd)) - (set tmpd (sra Rd c)) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; LSR.m Rs,Rd [ Rd | 011111mm | Rs ] -(dni-cdt-bwd - lsrr "Logical shift right register count" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_LSR Rs) - (.pmacro - (BWD) - (sequence - ((SI tmpd) (SI cnt)) - (set cnt (and Rs 63)) - (set - tmpd - (if SI (ne (and cnt 32) 0) - 0 - (srl SI (zext SI (trunc BWD Rd)) (and cnt 31)))) - (set-subreg-gr BWD (regno Rd) tmpd) - (setf-move BWD tmpd))) -) - -; LSRQ c,Rd [ Rd | 0011111 | c ] -(dni-cdt - lsrq "Logical shift right quick-immediate count" - "lsrq $c,${Rd}" - (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 1) c) - (sequence - ((SI tmpd)) - (set tmpd (srl Rd c)) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; LSL.m Rs,Rd [ Rd | 010011mm | Rs ] -(dni-cdt-bwd - lslr "Logical shift left register count" - "$Rs,$Rd" - (+ Rd MODE_REGISTER R_LSL Rs) - (.pmacro - (BWD) - (sequence - ((SI tmpd) (SI cnt)) - (set cnt (and Rs 63)) - (set - tmpd - (if SI (ne (and cnt 32) 0) - 0 - (sll SI (zext SI (trunc BWD Rd)) (and cnt 31)))) - (set-subreg-gr BWD (regno Rd) tmpd) - (setf-move BWD tmpd))) -) - -; LSLQ c,Rd [ Rd | 0011110 | c ] -(dni-cdt - lslq "Logical shift left quick-immediate count" - "lslq $c,${Rd}" - (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 0) c) - (sequence - ((SI tmpd)) - (set tmpd (sll Rd c)) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; BTST Rs,Rd [ Rd | 01001111 | Rs ] -(dni-cdt - btst "Bit test register number" - "$Rs,$Rd" - (+ Rd MODE_REGISTER RFIX_BTST SIZE_FIXED Rs) - (sequence - ((SI tmpd) (SI cnt)) - (set tmpd (sll Rd (sub 31 (and Rs 31)))) - (setf-move SI tmpd)) -) - -; BTSTQ c,Rd [ Rd | 0011100 | c ] -(dni-cdt - btstq "Bit test quick-immediate number" - "btstq $c,${Rd}" - (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 0) c) - (sequence - ((SI tmpd)) - (set tmpd (sll Rd (sub 31 c))) - (setf-move SI tmpd)) -) - -; SETF <list of flags> [ P U I X | 01011011 | N Z V C ] -(dni-cdt - setf "Set condition code flags explicitly" - "setf ${list-of-flags}" - ; The zero-flags case gets flag operands wrong; there's a "_" - ; where there should have been nothing. Also, flags are in - ; assembly code allowed to be specified in any order, which - ; doesn't match the "flagbits" settings. Luckily we don't - ; use this field for assembly. - (+ RFIX_SETF MODE_REGISTER SIZE_FIXED list-of-flags) - (.splice - sequence - ((SI tmp)) - (set tmp list-of-flags) - (.unsplice - (.map - (.pmacro (ccbit) - (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0) - (set (.sym ccbit bit) 1))) - cris-flagnames)) - (set prefix-set 0) - ; Unless x was specified to be set, set it to 0. - (if (eq (and tmp (sll 1 x-bitnumber)) 0) - (set xbit 0))) -) - -; CLEARF <list of flags> [ P U I X | 01011111 | N Z V C ] -(dni-cdt - clearf "Clear condition code flags explicitly" - "clearf ${list-of-flags}" - ; The zero-flags case gets flag operands wrong; there's a "_" - ; where there should have been nothing. Also, flags are in - ; assembly code allowed to be specified in any order, which - ; doesn't match the "flagbits" settings. Luckily we don't - ; use this field for assembly. - (+ RFIX_CLEARF MODE_REGISTER SIZE_FIXED list-of-flags) - (.splice - sequence - ((SI tmp)) - (set tmp list-of-flags) - (.unsplice - (.map - (.pmacro (ccbit) - (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0) - (set (.sym ccbit bit) 0))) - cris-flagnames)) - (reset-x-p)) -) - -(define-pmacro - (rfe-rfn-guts) - "Common parts of RFE and RFN" - (sequence - ((USI oldccs) (USI samebits) (USI shiftbits) (USI keepmask) (BI p1)) - (set oldccs ccs) - ; Keeping U, S and I in user mode is handled by the CCS setter, so we - ; don't have to bother. Actually Q and M are handled too. The reason - ; to mask those out is to not have them shifted down into the second - ; flags level. - (set keepmask #xc0000000) - (set samebits (and oldccs keepmask)) - ; The P bit has its own equation. - (set shiftbits (and (srl (and oldccs #x3ffdfc00) 10) (inv keepmask))) - (set p1 (ne 0 (and oldccs #x20000))) - (set ccs (or (or samebits shiftbits) - (if SI (and rbit (not p1)) 0 #x80)))) -) - -; RFE [ 0010 10010011 0000 ] -(dni-cdt-attr - rfe - "RFE" - (MACH-V32) - "rfe" - (+ (f-dest 2) MODE_INDIRECT INFIX_RFE SIZE_FIXED (f-source 0)) - (rfe-rfn-guts) -) - -; SFE [ 0011 10010011 0000 ] -(dni-cdt-attr - sfe - "SFE" - (MACH-V32) - "sfe" - (+ (f-dest 3) MODE_INDIRECT INFIX_SFE SIZE_FIXED (f-source 0)) - (sequence - ((SI oldccs) (SI savemask)) - (set savemask #xc0000000) - (set oldccs ccs) - (set ccs - (or (and savemask oldccs) - (and (inv savemask) (sll oldccs 10))))) -) - -; RFG [ 0100 10010011 0000 ] -(dni-cdt-attr - rfg - "RFG" - (MACH-V32) - "rfg" - (+ (f-dest 4) MODE_INDIRECT INFIX_RFG SIZE_FIXED (f-source 0)) - (c-call VOID "@cpu@_rfg_handler" pc) -) - -; RFN [ 0101 10010011 0000 ] -(dni-cdt-attr - rfn - "RFN" - (MACH-V32) - "rfn" - (+ (f-dest 5) MODE_INDIRECT INFIX_RFN SIZE_FIXED (f-source 0)) - (sequence () (rfe-rfn-guts) (set mbit 1)) -) - -; HALT [ 1111 10010011 0000 ] -(dni-cdt-attr - halt - "HALT" - (MACH-V32) - "halt" - (+ (f-dest 15) MODE_INDIRECT INFIX_HALT SIZE_FIXED (f-source 0)) - (set pc (c-call USI "@cpu@_halt_handler" pc)) -) - -; Bcc o [ cc | 0000 | o ] -(dni - bcc-b "bcc byte operand" - () - "b${cc} ${o-pcrel}" - (+ cc QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel) - (sequence - ((BI truthval)) - (set truthval (cris-condition cc)) - - ; Amazing as it may seem, there's no simpler way to find out - ; whether a branch is taken or not than to mark it through a kludge - ; like this. - (c-call VOID "@cpu@_branch_taken" pc o-pcrel truthval) - - (reset-x-p) - (if truthval - (delay 1 - (set pc o-pcrel)))) - (.splice (.unsplice (simplecris-timing)) - (crisv32 (unit u-branch) (unit u-exec))) -) -(dni - ba-b "ba byte operand" - () - "ba ${o-pcrel}" - (+ (f-dest 14) QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel) - (sequence - () - (reset-x-p) - (delay 1 - (set pc o-pcrel))) - ((crisv32 (unit u-jump) (unit u-exec))) -) - -; Bcc [PC+] [ cc | 11011111 1111 ] -; (We don't implement the generic for pre-V32 but unused variant -; "Bcc [Rn(+)]" where n != 15.) -(dni - bcc-w "bcc, word operand" - () - "b${cc} ${o-word-pcrel}" - (+ cc MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel) - (sequence - ((BI truthval)) - (set truthval (cris-condition cc)) - - ; Amazing as it may seem, there's no simpler way to find out - ; whether a branch is taken or not than to mark it through a kludge - ; like this. - (c-call VOID "@cpu@_branch_taken" pc o-word-pcrel truthval) - - (reset-x-p) - (if truthval - (delay 1 - (set pc o-word-pcrel)))) - (.splice - (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec)))) - (crisv32 (unit u-const16) (unit u-branch) (unit u-exec))) -) -(dni - ba-w "ba word operand" - () - "ba ${o-word-pcrel}" - (+ (f-dest 14) MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel) - (sequence - () - (reset-x-p) - (delay 1 - (set pc o-word-pcrel))) - (.splice - (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec)))) - (crisv32 (unit u-const16) (unit u-jump) (unit u-exec))) -) - -; JAS Rs,Pd [ Pd | 10011011 | Rs ] -(dni - jas-r "JAS register" - (MACH-V32) - "jas ${Rs},${Pd}" - (+ Pd MODE_INDIRECT INFIX_JAS_R SIZE_FIXED Rs) - (sequence - () - (reset-x-p) - (if (andif (eq (regno Rs) 1) (eq (regno Pd) 11)) - ; We use this as a trigger; a normally reasonably rare instruction - ; used in the v32 trampoline. See comment at bdapqpc. - ; CGEN-FIXME: can't use (regno srp) [== (regno (reg h-sr 11))] - (c-call VOID "cris_flush_simulator_decode_cache" pc)) - (delay 1 - (sequence - () - (set Pd (add SI pc 4)) - (set pc Rs)))) - ((crisv32 (unit u-jump-r) (unit u-jump) (unit u-exec))) -) -; Same semantics in pre-V32, except no delay-slot. -; FIXME: Missing JIRC/JSRC/JBRC. -(dni-cdt-attr - jump-r "JUMP/JSR/JIR register" - (MACH-PC) - "jump/jsr/jir ${Rs}" - (+ Pd MODE_INDIRECT INFIX_JUMP_R SIZE_FIXED Rs) - (sequence - () - (set Pd (add SI pc 2)) - (set pc Rs) - (reset-x-p)) -) - -; JAS [PC+],Pd [ Pd | 11011011 1111 ] -(dni - jas-c "JAS constant" - (MACH-V32) - "jas ${const32},${Pd}" - (+ Pd MODE_AUTOINCREMENT INFIX_JAS_M SIZE_FIXED (f-source 15) const32) - (sequence - () - (reset-x-p) - (delay 1 - (sequence - () - (set Pd (add SI pc 8)) - (set pc const32)))) - ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec))) -) - -; JUMP/JSR/JIR | Special r.| 1 m| 0 1 0 0| 1 1| Source | -(dni-cmt-attr - jump-m "JUMP/JSR/JIR memory" - (MACH-PC) - "jump/jsr/jir [${Rs}${inc}]" - (+ Pd INFIX_JUMP_M SIZE_FIXED Rs) - (sequence - () - (set Pd (add SI pc 2)) - (set pc (cris-get-mem SI Rs)) - (reset-x-p)) -) -(dni-c-SI-attr - jump-c "JUMP/JSR/JIR constant" - (MACH-PC) - "jump/jsr/jir ${const32}" - (+ Pd MODE_AUTOINCREMENT INFIX_JUMP_M SIZE_FIXED (f-source 15) const32) - (sequence - () - (set Pd (add SI pc 6)) - (set pc const32) - (reset-x-p)) -) - -; JUMP Ps [ Ps | 10011111 0000 ] -(dni - jump-p "JUMP special register" - (MACH-V32) - "jump ${Ps}" - (+ Ps MODE_INDIRECT INFIX_JUMP_P SIZE_FIXED (f-source 0)) - (sequence - () - (reset-x-p) - (delay 1 - (set pc Ps))) - ((crisv32 (unit u-jump-sr) - (unit u-exec))) -) - -; BAS [PC+],Pd [ Pd | 11101011 1111 ] -(dni - bas-c "BAS constant" - (MACH-V32) - "bas ${const32},${Pd}" - (+ Pd MODE_AUTOINCREMENT INFIX_BAS SIZE_FIXED (f-source 15) const32-pcrel) - (sequence - () - (reset-x-p) - (delay 1 - (sequence - () - (set Pd (add SI pc 8)) - (set pc const32-pcrel)))) - ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec))) -) - -; JASC Rs,Pd [ Pd | 10110011 | Rs ] -(dni - jasc-r "JASC register" - (MACH-V32) - "jasc ${Rs},${Pd}" - (+ Pd MODE_INDIRECT INFIX_JASC SIZE_FIXED Rs) - (sequence - () - (reset-x-p) - (delay 1 - (sequence - () - (set Pd (add SI pc 8)) - (set pc Rs)))) - ((crisv32 (unit u-jump-r) (unit u-skip4) (unit u-jump) (unit u-exec))) -) - -; JASC [PC+],Pd [ Pd | 11110011 1111 ] -(dni - jasc-c "JASC constant" - (MACH-V32) - "jasc ${const32},${Pd}" - (+ Pd MODE_AUTOINCREMENT INFIX_JASC SIZE_FIXED (f-source 15) const32) - (sequence - () - (reset-x-p) - (delay 1 - (sequence - () - (set Pd (add SI pc 12)) - (set pc const32)))) - ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec))) -) - -; BASC [PC+],Pd [ Pd | 11101111 1111 ] -(dni - basc-c "BASC constant" - (MACH-V32) - "basc ${const32},${Pd}" - (+ Pd MODE_AUTOINCREMENT INFIX_BASC SIZE_FIXED (f-source 15) const32-pcrel) - (sequence - () - (reset-x-p) - (delay 1 - (sequence - () - (set Pd (add SI pc 12)) - (set pc const32-pcrel)))) - ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec))) -) - -; BREAK n [ 1110 | 10010011 | n ] - -(dni-cdt - break "break" - "break $n" - (+ (f-operand2 #xe) MODE_INDIRECT INFIX_BREAK SIZE_FIXED n) - (sequence () (reset-x-p) (set pc (c-call USI "@cpu@_break_handler" n pc))) -) - -; BOUND.m Rs,Rd [ Rd | 010111mm | Rs ] -(dni-cdt-bwd - bound-r "Bound register" - "${Rs},${Rd}" - (+ Rd R_BOUND MODE_REGISTER Rs) - (.pmacro - (BWD) - (sequence - ((SI tmpopd) (SI tmpops) (SI newval)) - (set tmpops ((.sym BWD -zext) (trunc BWD Rs))) - (set tmpopd Rd) - (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) - (set Rd newval) - (setf-move SI newval))) -) - -; BOUND.m [Rs],Rd [ Rd | 100111mm | Rs ] -; BOUND.m [Rs+],Rd [ Rd | 110111mm | Rs ] -(dni-cmt-bwd-attr - bound-m "Bound memory" - (MACH-PRE-V32) - "[${Rs}${inc}],${Rd}" - (+ Rd INDIR_BOUND Rs) - (.pmacro - (BWD) - (sequence - ((SI tmpopd) (SI tmpops) (SI newval)) - (set tmpops ((.sym BWD -zext) (cris-get-mem BWD Rs))) - (set tmpopd Rd) - (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) - (if (andif prefix-set (not inc)) - (set Rs newval) - (set Rd newval)) - (setf-move SI newval))) -) - -; (BOUND.m [PC+],Rd [ Rd | 110111mm | 1111 ]) -(dni-c-QI - bound-cb "Bound constant byte" - "bound.b [PC+],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_BYTE (f-source 15) uconst8) - (sequence - ((SI tmpopd) (SI tmpops) (SI newval)) - (set tmpops (zext SI (trunc QI uconst8))) - (set tmpopd Rd) - (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) - (set Rd newval) - (setf-move SI newval)) -) -(dni-c-HI - bound-cw "Bound constant word" - "bound.w [PC+],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_WORD (f-source 15) uconst16) - (sequence - ((SI tmpopd) (SI tmpops) (SI newval)) - (set tmpops (zext SI uconst16)) - (set tmpopd Rd) - (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) - (set Rd newval) - (setf-move SI newval)) -) -(dni-c-SI - bound-cd "Bound constant dword" - "bound.d [PC+],${Rd}" - (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_DWORD (f-source 15) const32) - (sequence - ((SI tmpopd) (SI tmpops) (SI newval)) - (set tmpops const32) - (set tmpopd Rd) - (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) - (set Rd newval) - (setf-move SI newval)) -) - -; Scc Rd [ cc | 01010011 | Rd ] -(dni-cdt - scc "scc" - "s${cc} ${Rd-sfield}" - (+ cc MODE_REGISTER RFIX_SCC SIZE_FIXED Rd-sfield) - (sequence - ((BI truthval)) - (set truthval (cris-condition cc)) - (set Rd-sfield (zext SI truthval)) - (reset-x-p)) -) - -; LZ Rs,Rd [ Rd | 01110011 | Rs ] -(dni-cdt-attr - lz "lz" - (MACH-V3-UP) - "lz ${Rs},${Rd}" - (+ Rd MODE_REGISTER RFIX_LZ SIZE_FIXED Rs) - (sequence - ((SI tmpd) (SI tmp)) - (set tmp Rs) - (set tmpd 0) - (.splice - sequence - () - (.unsplice - (.map - (.pmacro (n) - (if (ge tmp 0) - (sequence - () - (set tmp (sll tmp 1)) - (set tmpd (add tmpd 1))))) - (.iota 32)))) - (set Rd tmpd) - (setf-move SI tmpd)) -) - -; ADDOQ o,Rs,ACR [ Rs | 0001 | o ] -(dni-cdt - addoq "addoq" - "addoq $o,$Rs,ACR" - (+ Rs-dfield MODE_QUICK_IMMEDIATE QHI_ADDOQ o) - (sequence - () - (set prefixreg (add SI Rs-dfield o)) - (set prefix-set 1)) -) - -; (BDAPQ o,PC [ 1111 | 0001 | o ]) -; This [PC+I] prefix is used in trampolines. -(dni-cdt-attr - bdapqpc "bdapq pc operand" - (MACH-PC UNCOND-CTI) - "bdapq $o,PC" - (+ (f-dest 15) MODE_QUICK_IMMEDIATE QHI_BDAP o) - (sequence - () - (set prefixreg (add SI (add SI pc 2) o)) - (set prefix-set 1) - ; When this *rare* instruction is seen, we're may be about to write - ; into code to be executed soon, *probably* covering addresses decoded - ; and executed before. If the simulator does not implement snooping - ; and automatic decoder flush, it will execute old code. This call - ; is a kludge for such simulators, asking it to abandon such cached - ; information. Anyway, it is hopefully enough to make CGEN-sim not - ; hork on gcc trampolines. - ; We mark this insn as UNCOND-CTI so this insn will end a simulator - ; basic block (the atomic unit of translation). - (c-call VOID "cris_flush_simulator_decode_cache" pc)) -) - -; (BDAP.D [PC+],PC [ 1111 | 11010110 | 1111 ] -; This [PC+I] prefix is used for DSO-local jumps in PIC code, together with -; move-m-pcplus-p0: "move [pc=pc+N],p0" -(dni-c-SI-attr - bdap-32-pc "bdap.d [PC+],PC" - (MACH-PC) - "bdap ${sconst32},PC" - (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_BDAP_M SIZE_DWORD (f-source 15) const32) - (sequence - ((SI newpc) (SI oldpc) (SI offs)) - (set offs const32) - (set oldpc (add SI pc 6)) - (set newpc (add SI oldpc offs)) - (set prefixreg newpc) - (set prefix-set 1)) -) - -; (MOVE [PC+],P0 [ 0000 | 11100011 | 1111 ]) -; This insn is used for DSO-local jumps in PIC code. See bdap-32-pc. -(dni ; Must not use dni-cmt-* because we force MODE_AUTOINCREMENT. - move-m-pcplus-p0 "move [PC+],P0" - (MACH-PC) - "move [PC+],P0" - (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 15)) - (if prefix-set - (sequence - ((QI dummy)) - ; We model the memory read, but throw the result away, as the - ; destination register is read-only. We need to assign the result of - ; cris-get-mem though, as CGEN-FIXME: invalid C code will otherwise - ; be generated. - (set dummy (cris-get-mem QI pc)) - (reset-x-p)) - (error "move [PC+],P0 without prefix is not implemented")) - (cris-mem-timing) -) - -; This insn is used in Linux in the form "move [$sp=$sp+16],$p8"; it's -; similar to move-m-pcplus-p0 above. The same comments apply here. -(dni - move-m-spplus-p8 "move [SP+],P8" - (MACH-PC) - "move [SP+],P8" - (+ (f-dest 8) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED (f-source 14)) - (if prefix-set - (sequence - ((SI dummy)) - (set dummy (cris-get-mem SI sp)) - (reset-x-p)) - (error "move [SP+],P8 without prefix is not implemented")) - (cris-mem-timing) -) - -; ADDO.m [Rs],Rd,ACR [ Rd | 100101mm | Rs ] -; ADDO.m [Rs+],Rd,ACR [ Rd | 110101mm | Rs ] -(dni-cmt-bwd - addo-m "addo.m memory" - "[${Rs}${inc}],$Rd,ACR" - (+ Rd INDIR_ADDO Rs) - (.pmacro - (BWD) - (sequence - ((BWD tmps)) - (set tmps (cris-get-mem BWD Rs)) - (set prefixreg (add SI Rd ((.sym BWD -ext) tmps))) - (set prefix-set 1))) -) - -; (ADDO.m [PC+],Rd,ACR [ Rd | 110101mm | 1111 ] -(dni-c-QI - addo-cb "addo.b const" - "addo.b [PC+],$Rd,ACR" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_BYTE (f-source 15) sconst8) - (sequence - () - (set prefixreg (add SI Rd (ext SI (trunc QI sconst8)))) - (set prefix-set 1)) -) -(dni-c-HI - addo-cw "addo.w const" - "addo.w [PC+],$Rd,ACR" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_WORD (f-source 15) sconst16) - (sequence - () - (set prefixreg (add SI Rd (ext SI (trunc HI sconst16)))) - (set prefix-set 1)) -) -(dni-c-SI - addo-cd "addo.d const" - "addo.d [PC+],$Rd,ACR" - (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_DWORD (f-source 15) const32) - (sequence - () - (set prefixreg (add SI Rd const32)) - (set prefix-set 1)) -) - -; DIP [] | 0 0 0 0| 1 m| 0 1 0 1| 1 1| Source | - -(dni-cmt-attr - dip-m "dip mem" - (MACH-PRE-V32) - "dip [${Rs}${inc}]" - (+ (f-dest 0) INFIX_DIP SIZE_FIXED Rs) - (sequence - ((SI tmps)) - (set tmps (cris-get-mem SI Rs)) - (set prefixreg tmps) - (set prefix-set 1)) -) - -; (DIP [] | 0 0 0 0| 1 m| 0 1 0 1| 1 1| Source | ) -(dni-c-SI-attr - dip-c "dip [PC+]" - (MACH-PC) - "dip [PC+]" - (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_DIP SIZE_FIXED (f-source 15) const32) - (sequence - () - (set prefixreg const32) - (set prefix-set 1)) -) - -; ADDI Rs.m,Rd,ACR [ Rs | 010101mm | Rd ] -; a.k.a. biap -(dni-cdt-bwd - addi-acr "addi prefix" - "${Rs-dfield}.m,${Rd-sfield},ACR" - (+ Rd-sfield MODE_REGISTER R_ADDI_ACR Rs-dfield) - (.pmacro - (BWD) - (sequence - () - (set prefixreg (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) - (set prefix-set 1))) -) - -(dni-cdt-bwd-attr - biap-pc "biap.m ${Rs-dfield},PC" - (MACH-PC) - "${Rs-dfield}.m,PC" - (+ Rs-dfield MODE_REGISTER R_ADDI_ACR (f-source 15)) - (.pmacro - (BWD) - (sequence - () - (set prefixreg (add SI (add SI pc 4) (mul Rs-dfield (.sym BWD -size)))) - (set prefix-set 1))) -) - -; FIDXI [Rs] [ 0000 | 11010011 | Rs ] -(dni-cdt-attr - fidxi "fidxi [Rs]" - (MACH-V32) - "fidxi [$Rs]" - (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_FIDXI SIZE_FIXED Rs) - (set pc (c-call USI "@cpu@_fidxi_handler" pc Rs)) -) - -; FTAGI [Rs] [ 0001 | 11010011 | Rs ] -(dni-cdt-attr - ftagi "ftagi [Rs]" - (MACH-V32) - "fidxi [$Rs]" - (+ (f-dest 1) MODE_AUTOINCREMENT INFIX_FTAGI SIZE_FIXED Rs) - (set pc (c-call USI "@cpu@_ftagi_handler" pc Rs)) -) - -; FIDXD [Rs] [ 0000 | 10101011 | Rs ] -(dni-cdt-attr - fidxd "fidxd [Rs]" - (MACH-V32) - "fidxd [$Rs]" - (+ (f-dest 0) MODE_INDIRECT INFIX_FIDXD SIZE_FIXED Rs) - (set pc (c-call USI "@cpu@_fidxd_handler" pc Rs)) -) - -; FTAGD [Rs] [ 0001 | 10101011 | Rs ] -(dni-cdt-attr - ftagd "ftagd [Rs]" - (MACH-V32) - "ftagd [$Rs]" - (+ (f-dest 1) MODE_INDIRECT INFIX_FTAGD SIZE_FIXED Rs) - (set pc (c-call USI "@cpu@_ftagd_handler" pc Rs)) -) diff --git a/binutils-2.24/cpu/epiphany.cpu b/binutils-2.24/cpu/epiphany.cpu deleted file mode 100644 index 33c81d00..00000000 --- a/binutils-2.24/cpu/epiphany.cpu +++ /dev/null @@ -1,2936 +0,0 @@ -; Adapteva EPIPHANY CPU description. -*- Scheme -*- -; Copyright 1998, 1999, 2000, 2001, 2003, 2006, 2007, 2008, 2009, 2010, 2011 -; Free Software Foundation, Inc. -; -; Contributed by Embecosm on behalf of Adapteva, Inc. -; This file is part of the GNU Binutils and of GDB. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - ; define-arch must appear first - -(define-arch - (name epiphany) ; name of cpu family - (comment "Adapteva, Inc. EPIPHANY family") - (default-alignment aligned) - (insn-lsb0? #t) - - ; - a 16/32 bit instruction machine (the default) - - (machs epiphany32) - (isas epiphany) - ) - - ; Attributes. - -(define-attr - (for insn) - (type boolean) - (name SHORT-INSN) - (comment "instruction is a 16 bit form") - ) - -;; 3 bit add/sub immediate forms - useful for relaxing into 11 bit form -(define-attr - (for insn) - (type boolean) - (name IMM3) - (comment "instruction has a 3 bit immediate form") - ) - -;; 8 bit mov immediate forms - useful for relaxing into 16 bit form -(define-attr - (for insn) - (type boolean) - (name IMM8) - (comment "instruction has a 8 bit immediate form") - ) - - ; Instruction set parameters. - -(define-isa - (name epiphany) - (comment "Adapteva, Inc. EPIPHANY32 ISA") - - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) - (decode-assist (3 2 1 0)) ; CGEN can figure this out - (liw-insns 1) ; # instructions fetched at once - ) - - ; Cpu family definitions. - - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - (name epiphanybf) - (comment "Adapteva, Inc. EPIPHANY Family") - (endian little) - (word-bitsize 32) - ) - -(define-cpu - (name epiphanymf) - (comment "Adapteva, Inc. EPIPHANY Family") - (endian little) - (word-bitsize 32) - ) - - -(define-mach - (name epiphany32) - (comment "Adapteva EPIPHANY") - (cpu epiphanybf) - ) - - - ; Model descriptions. - -(define-model - (name epiphany32) (comment "Adapteva EPIPHANY 32/16") (attrs) - (mach epiphany32) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ) - - - - ; Instruction fields. - ; - ; Attributes: - ; XXX: what EPIPHANY attrs - ; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) - ; ABS-ADDR: absolute address (for reloc and disassembly purposes?) - ; RESERVED: bits are not used to decode insn, must be all 0 - ; RELOC: there is a relocation associated with this field - -(define-attr - (for ifield operand) - (type boolean) - (name RELOC) - (comment "there is a reloc associated with this field (experiment)") - ) - -;; define the fields of the instruction. -;; name description ATTR MSB LEN -(dnf f-opc "primary opcode" () 3 4) -(dnf f-opc-4-1 "secondary opcode" () 4 1) -(dnf f-opc-6-3 "secondary opcode" () 6 3) ;; -(dnf f-opc-8-5 "tertiary opcode" () 8 5) ;; -(dnf f-opc-19-4 "additional opcode bits" () 19 4) -(dnf f-condcode "condition codes" () 7 4) -(dnf f-secondary-ccs "flag for secondary ccs" () 7 1) -(dnf f-shift "shift amount" () 9 5) -(dnf f-wordsize "load/store size" () 6 2) -(dnf f-store "load/store flag" () 4 1) ;; 0==load,1==store -(dnf f-opc-8-1 "opcode bits" () 8 1) -(dnf f-opc-31-32 "all opcode set" () 31 32) - -(df f-simm8 "branch displacement" (PCREL-ADDR RELOC) 15 8 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-simm24 "branch displacement" (PCREL-ADDR RELOC) 31 24 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-sdisp3 "signed immediate 3 bit" () 9 3 INT #f #f) - -(dnf f-disp3 "address offset" () 9 3) -(dnf f-disp8 "address offset" () 23 8) - -(dnf f-imm8 "move/add/sub imm8" () 12 8) -(dnf f-imm-27-8 "move/add/sub imm16" () 27 8) -(dnf f-addsubx "+/- index address" () 20 1) -(dnf f-subd "+/- displ address" () 24 1) -(dnf f-pm "post-modify immediate" () 25 1) - -(dnf f-rm "short rm" () 9 3) ;; RM -(dnf f-rn "short rn" () 12 3) ;; RN -(dnf f-rd "short rd" () 15 3) ;; RD - -(dnf f-rm-x "extension rm" () 25 3) ;; RM -(dnf f-rn-x "extension rn" () 28 3) ;; RN -(dnf f-rd-x "extension rd" () 31 3) ;; RD - -(dnf f-dc-9-1 "DC" (RESERVED) 9 1) - -(dnf f-sn "short sn" () 12 3) ;; SN -(dnf f-sd "short sd" () 15 3) ;; SD - -(dnf f-sn-x "extension sn" () 28 3) ;; SN -(dnf f-sd-x "extension sd" () 31 3) ;; SD - - - -(dnf f-dc-7-4 "movts zeros" () 7 4) -(dnf f-trap-swi-9-1 "trap or swi" () 9 1) -(dnf f-gien-gidis-9-1 "gien or gidis" () 9 1) - - -(dnf f-dc-15-3 "DC" (RESERVED) 15 3) -(dnf f-dc-15-7 "DC" (RESERVED) 15 7) -(dnf f-dc-15-6 "DC" () 15 6) -(dnf f-trap-num "trap number" () 15 6) - -(dnf f-dc-20-1 "DC" (RESERVED) 20 1) - -(dnf f-dc-21-1 "DC" (RESERVED) 21 1) -(dnf f-dc-21-2 "DC" (RESERVED) 21 2) - -(dnf f-dc-22-3 "DC" (RESERVED) 22 3) -(dnf f-dc-22-2 "DC" (RESERVED) 22 2) -(dnf f-dc-22-1 "DC" (RESERVED) 22 1) - -(dnf f-dc-25-6 "DC" (RESERVED) 25 6) -(dnf f-dc-25-4 "DC" (RESERVED) 25 4) -(dnf f-dc-25-2 "DC" (RESERVED) 25 2) -(dnf f-dc-25-1 "DC" (RESERVED) 25 1) - -(dnf f-dc-28-1 "DC" (RESERVED) 28 1) -(dnf f-dc-31-3 "DC" (RESERVED) 31 3) - -(dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8) - (sequence () - (set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255))) - (set (ifield f-disp3) (and (ifield f-disp11) 7))) - (sequence () - (set (ifield f-disp11) (or (sll (ifield f-disp8) 3) - (ifield f-disp3))) - ) - ) - - -(dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8) - (sequence () ;encode - (set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3))) - (set (ifield f-disp3) (and SI (ifield f-sdisp11) 7))) - (sequence () ;decode - (set (ifield f-sdisp11) - (sra SI (sll SI (or SI (sll (ifield f-disp8) 3) - (ifield f-disp3)) - 21) - 21))) - ) - -(dnmf f-imm16 "Short immediate for move/add/sub" () UINT (f-imm8 f-imm-27-8) - (sequence () - (set (ifield f-imm8) (and (ifield f-imm16) #xff)) - (set (ifield f-imm-27-8) (srl (ifield f-imm16) 8))) - (sequence () - (set (ifield f-imm16) (or (sll (ifield f-imm-27-8) 8) - (ifield f-imm8)))) - ) - - -;; 32 bit instructions have the register number broken into two non-contiguous fields - -(define-pmacro (x-reg-field reg) - (define-multi-ifield - (name (.sym "f-" reg "6")) - (mode UINT) - (subfields (.sym "f-" reg "-x") (.sym "f-" reg)) - (insert (sequence () - (set (ifield (.sym "f-" reg)) (and (ifield (.sym "f-" reg "6")) - (const 7))) - (set (ifield (.sym "f-" reg "-x")) (srl (ifield (.sym "f-" reg "6")) - (const 3))) - )) - (extract (sequence () - (set (ifield (.sym "f-" reg "6")) (or (sll (ifield (.sym "f-" reg "-x")) - (const 3)) - (ifield (.sym "f-" reg)))) - )) - ) - ) - -(x-reg-field rd) ; f-rd6 -(x-reg-field rn) ; f-rn6 -(x-reg-field rm) ; f-rm6 -(x-reg-field sd) ; f-sd6 -(x-reg-field sn) ; f-sn6 - - -;;;;;;;;;; - ; Enums. ; -;;;;;;;;;; - - ; insn-opc: bits 3..0 - major family selector -(define-normal-insn-enum insn-opc "opc enums" () OP4_ f-opc - ( - BRANCH16 ;; 0000 - LDSTR16X ;; 0001 - FLOW16 ;; 0010 - IMM16 ;; 0011 - LDSTR16D ;; 0100 - LDSTR16P ;; 0101 - LSHIFT16 ;; 0110 - logical shift - DSP16 ;; 0111 - 3 reg DSP 16 bit insns - BRANCH ;; 1000 - LDSTRX ;; 1001 - ALU16 ;; 1010 - 3 reg 16 bit - IMM32 ;; 1011 - LDSTRD ;; 1100 - LDSTRP ;; 1101 - ASHIFT16 ;; 1110 ASR, BITR - MISC ;; 1111 - 32 bit shifts, 3 reg ALU, 3 reg DSP, FLOW, BITR - ) - ) - -(define-normal-insn-enum insn-wordsize "memory access width" () OPW_ f-wordsize - ; specifies the size of a memory load/store operation - (BYTE SHORT WORD DOUBLE) - ) - -(define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store - ; load=0, store=1 - (LOAD STORE) - ) - - ; enum for trap codes used by simulator -(define-normal-insn-enum trap-codes "trap instruction dispatch code" () TRAP_ f-trap-num - (write read open exit pass fail close other) - ) - - ; cond branch: bits 7..4 - ; -(define-normal-insn-enum insn-cond "branch conditions" () OPC_ f-condcode - (EQ NE GTU GTEU LTEU LTU GT GTE LT LTE BEQ BNE BLT BLTE B BL)) - - ; dsp 3 operand opcodes -(define-normal-insn-enum insn-bop "binary operator subcodes" () OPB_ f-opc-6-3 - (EOR ADD LSL SUB LSR AND ASR ORR)) - - ; dsp 3 operand opcodes -(define-normal-insn-enum insn-bopext "binary operator subcodes" () OPBE_ f-opc-6-3 - (FEXT FDEP LFSR - - - - -)) - - -(define-normal-insn-enum insn-fop "floating operators" () OPF_ f-opc-6-3 - (ADD SUB MUL MADD MSUB FLOAT FIX FABS)) - -(define-normal-insn-enum insn-fopexn "extended floating operators" () OPF_ f-opc-6-3 - (FRECIP FSQRT - - - - - -)) - - - - -; Immediate operation secondary opcodes -(define-normal-insn-enum insn-immop "immediate operators" () OPI_ f-opc-6-3 - (- ADD - SUB - - - TRAP) ; TRAP is special extension for simulator - ) - - ; don't care fields -(define-normal-insn-enum insn-dc-25-2 "don't cares" () OPI_25_2_ f-dc-25-2 - (MBZ)) - -; General Register keyword names. -(define-keyword - (name gr-names) - (print-name h-registers) - (prefix "") - (values -; some preferred aliases - (fp 11) (sp 13) (lr 14) -; the default register names - (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) - (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) (r21 21) (r22 22) (r23 23) - (r24 24) (r25 25) (r26 26) (r27 27) (r28 28) (r29 29) (r30 30) (r31 31) - (r32 32) (r33 33) (r34 34) (r35 35) (r36 36) (r37 37) (r38 38) (r39 39) - (r40 40) (r41 41) (r42 42) (r43 43) (r44 44) (r45 45) (r46 46) (r47 47) - (r48 48) (r49 49) (r50 50) (r51 51) (r52 52) (r53 53) (r54 54) (r55 55) - (r56 56) (r57 57) (r58 58) (r59 59) (r60 60) (r61 61) (r62 62) (r63 63) -; some less popular aliases - (a1 0) (a2 1) (a3 2) (a4 3) (v1 4) (v2 5) (v3 6) (v4 7) - (v5 8) (v6 9) (v7 10) (v8 11) - (sb 9) (sl 10) (ip 12) - ) - ) - -(define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC)) - -(define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST)) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Hardware pieces. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; 64 general-purpose registers -(define-hardware - (name h-registers) - (comment "all addressable registers") - (type register SI (64)) - (attrs PROFILE CACHE-ADDR) - (indices extern-keyword gr-names) - ) - - - -;; Same 64 registers as floating point registers -(define-hardware - (name h-fpregisters) - (comment "all GPRs as float values") - (type register SF (64)) - (attrs PROFILE VIRTUAL) - (indices extern-keyword gr-names) - (get (index) (subword SF (reg h-registers index) 0)) - (set (index newval) (set (reg h-registers index) (subword SI newval 0))) - ) - -;; define processor status bits as physical hardware - -(define-pmacro (psw-h-bit name cmt) - (dsh name cmt () (register BI))) - -(psw-h-bit h-zbit "integer zero bit") -(psw-h-bit h-nbit "integer neg bit") -(psw-h-bit h-cbit "integer carry bit") -(psw-h-bit h-vbit "integer overflow bit") -(psw-h-bit h-vsbit "integer overflow sticky") - - -(psw-h-bit h-bzbit "floating point zero bit") -(psw-h-bit h-bnbit "floating point neg bit") -(psw-h-bit h-bvbit "floating point ovfl bit") -(psw-h-bit h-bubit "floating point underfl bit") -(psw-h-bit h-bibit "floating point invalid bit") -(psw-h-bit h-bcbit "floating point carry bit") - -(psw-h-bit h-bvsbit "floating point overflow sticky") -(psw-h-bit h-bisbit "floating point invalid sticky") -(psw-h-bit h-busbit "floating point underflow sticky") - -(psw-h-bit h-expcause0bit "exceprion cause bit0") -(psw-h-bit h-expcause1bit "exceprion cause bit1") -(psw-h-bit h-expcause2bit "external load stalled bit") -(psw-h-bit h-extFstallbit "external fetch stalled bit") - -(psw-h-bit h-trmbit "0=round to nearest, 1=trunacte select bit") -(psw-h-bit h-invExcEnbit "invalid exception enable bit") -(psw-h-bit h-ovfExcEnbit "overflow exception enable bit") -(psw-h-bit h-unExcEnbit "underflow exception enablebit ") - -(psw-h-bit h-timer0bit0 "timer 0 mode selection 0") -(psw-h-bit h-timer0bit1 "timer 0 mode selection 1") -(psw-h-bit h-timer0bit2 "timer 0 mode selection 2") -(psw-h-bit h-timer0bit3 "timer 0 mode selection 3") -(psw-h-bit h-timer1bit0 "timer 1 mode selection 0") -(psw-h-bit h-timer1bit1 "timer 1 mode selection 1") -(psw-h-bit h-timer1bit2 "timer 1 mode selection 2") -(psw-h-bit h-timer1bit3 "timer 1 mode selection 3") - -(psw-h-bit h-mbkptEnbit "multicore bkpt enable") -(psw-h-bit h-clockGateEnbit "clock gating enable bkpt enable") - - -(psw-h-bit h-coreCfgResBit12 "core config bit 12") -(psw-h-bit h-coreCfgResBit13 "core config bit 13") -(psw-h-bit h-coreCfgResBit14 "core config bit 14") -(psw-h-bit h-coreCfgResBit15 "core config bit 15") -(psw-h-bit h-coreCfgResBit16 "core config bit 16") - - -(psw-h-bit h-coreCfgResBit20 "core config bit 20") -(psw-h-bit h-coreCfgResBit21 "core config bit 21") - -(psw-h-bit h-coreCfgResBit24 "core config bit 24") -(psw-h-bit h-coreCfgResBit25 "core config bit 25") -(psw-h-bit h-coreCfgResBit26 "core config bit 26") -(psw-h-bit h-coreCfgResBit27 "core config bit 27") -(psw-h-bit h-coreCfgResBit28 "core config bit 28") -(psw-h-bit h-coreCfgResBit29 "core config bit 29") -(psw-h-bit h-coreCfgResBit30 "core config bit 30") -(psw-h-bit h-coreCfgResBit31 "core config bit 31") - - -(psw-h-bit h-arithmetic-modebit0 "arithmetic mode bit0") -(psw-h-bit h-arithmetic-modebit1 "arithmetic mode bit1") -(psw-h-bit h-arithmetic-modebit2 "arithmetic mode bit2") - - -(psw-h-bit h-gidisablebit "global interrupt disable bit") -(psw-h-bit h-kmbit "kernel mode bit") -(psw-h-bit h-caibit "core active indicator mode bit") -(psw-h-bit h-sflagbit "sflag bit") - - - ; Define operands for each of the physical bits -(define-pmacro (psw-bit name hname cmt) - (dnop name cmt (SEM-ONLY) hname f-nil) - ) - -(psw-bit zbit h-zbit "integer zero bit") -(psw-bit nbit h-nbit "integer neg bit") -(psw-bit cbit h-cbit "integer carry bit") -(psw-bit vbit h-vbit "integer overflow bit") - -(psw-bit bzbit h-bzbit "floating point zero bit") -(psw-bit bnbit h-bnbit "floating point neg bit") -(psw-bit bvbit h-bvbit "floating point ovfl bit") -(psw-bit bcbit h-bcbit "floating point carry bit") - -(psw-bit bubit h-bubit "floating point underfl bit") -(psw-bit bibit h-bibit "floating point invalid bit") - - -(psw-bit vsbit h-vsbit "integer overflow sticky") -(psw-bit bvsbit h-bvsbit "floating point overflow sticky") -(psw-bit bisbit h-bisbit "floating point invalid sticky") -(psw-bit busbit h-busbit "floating point underflow sticky") -(psw-bit expcause0bit h-expcause0bit "exceprion cause bit0") -(psw-bit expcause1bit h-expcause1bit "exceprion cause bit1") - - -(psw-bit expcause2bit h-expcause2bit "external load stalled bit") -(psw-bit extFstallbit h-extFstallbit "external fetch stalled bit") - -(psw-bit trmbit h-trmbit "0=round to nearest, 1=trunacte selct bit") -(psw-bit invExcEnbit h-invExcEnbit "invalid exception enable bit") -(psw-bit ovfExcEnbit h-ovfExcEnbit "overflow exception enable bit") -(psw-bit unExcEnbit h-unExcEnbit "underflow exception enable bit") - -(psw-bit timer0bit0 h-timer0bit0 "timer 0 mode selection 0") -(psw-bit timer0bit1 h-timer0bit1 "timer 0 mode selection 1") -(psw-bit timer0bit2 h-timer0bit2 "timer 0 mode selection 2") -(psw-bit timer0bit3 h-timer0bit3 "timer 0 mode selection 3") - -(psw-bit timer1bit0 h-timer1bit0 "timer 1 mode selection 0") -(psw-bit timer1bit1 h-timer1bit1 "timer 1 mode selection 1") -(psw-bit timer1bit2 h-timer1bit2 "timer 1 mode selection 2") -(psw-bit timer1bit3 h-timer1bit3 "timer 1 mode selection 3") - -(psw-bit mbkptEnbit h-mbkptEnbit "multicore bkpt enable") -(psw-bit clockGateEnbit h-clockGateEnbit "clock gate enable enable") - -(psw-bit arithmetic-modebit0 h-arithmetic-modebit0 "arithmetic mode bit0") -(psw-bit arithmetic-modebit1 h-arithmetic-modebit1 "arithmetic mode bit1") -(psw-bit arithmetic-modebit2 h-arithmetic-modebit2 "arithmetic mode bit2") - -(psw-bit coreCfgResBit12 h-coreCfgResBit12 "core config bit 12") -(psw-bit coreCfgResBit13 h-coreCfgResBit13 "core config bit 13") -(psw-bit coreCfgResBit14 h-coreCfgResBit14 "core config bit 14") -(psw-bit coreCfgResBit15 h-coreCfgResBit15 "core config bit 15") -(psw-bit coreCfgResBit16 h-coreCfgResBit16 "core config bit 16") - -(psw-bit coreCfgResBit20 h-coreCfgResBit20 "core config bit 20") -(psw-bit coreCfgResBit21 h-coreCfgResBit21 "core config bit 21") - -(psw-bit coreCfgResBit24 h-coreCfgResBit24 "core config bit 24") -(psw-bit coreCfgResBit25 h-coreCfgResBit25 "core config bit 25") -(psw-bit coreCfgResBit26 h-coreCfgResBit26 "core config bit 26") -(psw-bit coreCfgResBit27 h-coreCfgResBit27 "core config bit 27") -(psw-bit coreCfgResBit28 h-coreCfgResBit28 "core config bit 28") -(psw-bit coreCfgResBit29 h-coreCfgResBit29 "core config bit 29") -(psw-bit coreCfgResBit30 h-coreCfgResBit30 "core config bit 30") -(psw-bit coreCfgResBit31 h-coreCfgResBit31 "core config bit 31") - - -(psw-bit gidisablebit h-gidisablebit "global interrupt disable bit") -(psw-bit kmbit h-kmbit "kernel mode bit") -(psw-bit caibit h-caibit "core actibe indicator bit") -(psw-bit sflagbit h-sflagbit "sflag bit") - - - - -;; Special registers - accessed via MOVTS and MOVFS. -;; -;; "Core control and status" in group MR0=0, MR1=0 - -(define-keyword - (name cr-names) - (print-name h-core-registers) - (prefix "") - (values (config 0) - (status 1) ; unified condition codes - (pc 2) ; virtualized PC - (debug 3); - (iab 4) - (lc 5);loop counter Not impemented - (ls 6);loop start address Not impemented - (le 7);loop end address Not impemented - (iret 8) - (imask 9) - (ilat 10) - (ilatst 11) - (ilatcl 12) - (ipend 13) - (ctimer0 14) - (ctimer1 15) - (hstatus 16) - ) - ) -;; DMA registers in group MR0=1, MR1=0 - -(define-keyword - (name crdma-names) - (print-name h-coredma-registers) - (prefix "") - (values - - - (dma0config 0) - (dma0stride 1) - (dma0count 2) - - (dma0srcaddr 3) - (dma0dstaddr 4) - - (dma0auto0 5) - (dma0auto1 6) - - (dma0status 7) - - (dma1config 8) - (dma1stride 9) - (dma1count 10) - - (dma1srcaddr 11) - (dma1dstaddr 12) - - (dma1auto0 13) - (dma1auto1 14) - - (dma1status 15) - - ) - ) -;; mem configuration registers in group MR0=0, MR1=1 - -(define-keyword - (name crmem-names) - (print-name h-coremem-registers) - (prefix "") - (values - (memconfig 0) - (memstatus 1) - (memprotect 2) - (memreserve 3) - ) - ) - -;; mesh configuration registers in group MR0=1, MR1=1 - -(define-keyword - (name crmesh-names) - (print-name h-coremesh-registers) - (prefix "") - - (values - - - (meshconfig 0) - (coreid 1) - (meshmulticast 2) - (swreset 3) - ) - ) - - - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; PC is a byte-addressed register -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Memory Effective Address wants to be visible -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(dnh h-memaddr "memory effective address" (PROFILE) (register SI) () () ()) -(dnop memaddr "memory effective address" (SEM-ONLY) h-memaddr f-nil) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Special Core Registers -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; STATUS -;; [0]=core active indicator -;; [1]=global interrupt disable -;; [2]=processor mode(1=user mode, 0=kernel mode) -;; [3]=wired AND global flag - -;; [4]=integer zero zbit -;; [5]=integer negative nbit -;; [6]=integer carry cbit -;; [7]=integer overflow vbit - -;; [8]=fpu zero flag bzbit -;; [9]=fpu negative flag bnbit -;; [10]=fpu overflow flag bvbit -;; [11]=fpu carry flag(not used) bcbit - -;; [12]=ialu overflow flag(sticky) vsbit -;; [13]=fpu invalid flag(sticky) bisbit -;; [14]=fpu overflow flag(sticky) bvsbit -;; [15]=fpu underflow flag(sticky) busbit - -;; [17:16]=exception cause 00=no exception 01=load-store exception 10=fpu exception 11=unimplemented instruction -;; expcause1bit -;; expcause0bit - -;; [18]=external load stalled expcause2bit -;; [19]=external fetch stalled extFstallbit - -;; [31:20]=RESERVED - - - - - -(define-hardware - (name h-core-registers) - (comment "Special Core Registers") - (type register USI (17)) - (attrs) - (indices extern-keyword cr-names) - (get (index) - (cond USI - ((eq index (const 1)) ; STATUS reg ? - (or (or (or (or (sll USI kmbit (const 2)) - (sll USI gidisablebit (const 1))) - (or (or (sll USI expcause1bit (const 17)) - (sll USI expcause0bit (const 16))) - (or (sll USI expcause2bit (const 18)) - (sll USI extFstallbit (const 19))))) - (or (or (or (sll USI busbit (const 15)) - (sll USI bisbit (const 13))) - (or (sll USI bvsbit (const 14)) - (sll USI vsbit (const 12)))) - (or (or (sll USI bvbit (const 10)) - (sll USI bcbit (const 11))) - (or (sll USI bnbit (const 9)) - (sll USI bzbit (const 8)))))) - (or (or (or (sll USI vbit (const 7)) - (sll USI cbit (const 6))) - (or (sll USI nbit (const 5)) - (sll USI zbit (const 4)))) - (or (sll USI sflagbit (const 3)) - (sll USI (const 1) (const 0)))))) ;caibit - ((eq index (const 0)) ; Config reg ? - (or (or (or (or (or (or (sll USI timer0bit2 (const 6)) - (sll USI timer0bit3 (const 7))) - (or (or (sll USI coreCfgResBit28 (const 28)) - (sll USI coreCfgResBit29 (const 29))) - (or (sll USI coreCfgResBit30 (const 30)) - (sll USI coreCfgResBit31 (const 31))))) - (or (or (sll USI coreCfgResBit24 (const 24)) - (sll USI coreCfgResBit25 (const 25))) - (or (sll USI coreCfgResBit26 (const 26)) - (sll USI coreCfgResBit27 (const 27))))) - (or (or (sll USI timer0bit0 (const 4)) - (sll USI timer0bit1 (const 5))) - (or (sll USI coreCfgResBit14 (const 14)) - (sll USI coreCfgResBit15 (const 15))))) - (or (or (or (or (sll USI timer1bit2 (const 10)) - (sll USI timer1bit3 (const 11))) - (or (sll USI coreCfgResBit12 (const 12)) - (sll USI coreCfgResBit13 (const 13)))) - (or (sll USI clockGateEnbit (const 22)) - (sll USI mbkptEnbit (const 23)))) - (or (or (sll USI timer1bit0 (const 8)) - (sll USI timer1bit1 (const 9))) - (or (sll USI coreCfgResBit20 (const 20)) - (sll USI coreCfgResBit21 (const 21)))))) - (or (or (sll USI invExcEnbit (const 1)) - (sll USI ovfExcEnbit (const 2))) - (or (or (sll USI trmbit (const 0)) - (sll USI unExcEnbit (const 3))) - (or (or (sll USI arithmetic-modebit0 (const 17)) - (sll USI arithmetic-modebit1 (const 18))) - (or (sll USI arithmetic-modebit2 (const 19)) - (sll USI coreCfgResBit16 (const 16)))))))) ;config reg - - ((eq index (const 2)) (raw-reg USI h-pc)) ;PC reg - - (else (raw-reg USI h-core-registers index)))) - - (set (index val) - (cond VOID - ((eq index (const 0)) ; CONFIG reg - (sequence () - (set trmbit (and (const 1) (srl val (const 0)))) - (set invExcEnbit (and (const 1) (srl val (const 1)))) - (set ovfExcEnbit (and (const 1) (srl val (const 2)))) - (set unExcEnbit (and (const 1) (srl val (const 3)))) - (set timer0bit0 (and (const 1) (srl val (const 4)))) - (set timer0bit1 (and (const 1) (srl val (const 5)))) - (set timer0bit2 (and (const 1) (srl val (const 6)))) - (set timer0bit3 (and (const 1) (srl val (const 7)))) - (set timer1bit0 (and (const 1) (srl val (const 8)))) - (set timer1bit1 (and (const 1) (srl val (const 9)))) - (set timer1bit2 (and (const 1) (srl val (const 10)))) - (set timer1bit3 (and (const 1) (srl val (const 11)))) - - (set coreCfgResBit12 (and (const 1) (srl val (const 12)))) - (set coreCfgResBit13 (and (const 1) (srl val (const 13)))) - (set coreCfgResBit14 (and (const 1) (srl val (const 14)))) - (set coreCfgResBit15 (and (const 1) (srl val (const 15)))) - (set coreCfgResBit16 (and (const 1) (srl val (const 16)))) - - (set arithmetic-modebit0 (and (const 1) (srl val (const 17)))) - (set arithmetic-modebit1 (and (const 1) (srl val (const 18)))) - (set arithmetic-modebit2 (and (const 1) (srl val (const 19)))) - - (set coreCfgResBit20 (and (const 1) (srl val (const 20)))) - (set coreCfgResBit21 (and (const 1) (srl val (const 21)))) - - (set clockGateEnbit (and (const 1) (srl val (const 22)))) - (set mbkptEnbit (and (const 1) (srl val (const 23)))) - - (set coreCfgResBit24 (and (const 1) (srl val (const 24)))) - (set coreCfgResBit25 (and (const 1) (srl val (const 25)))) - (set coreCfgResBit26 (and (const 1) (srl val (const 26)))) - (set coreCfgResBit27 (and (const 1) (srl val (const 27)))) - (set coreCfgResBit28 (and (const 1) (srl val (const 28)))) - (set coreCfgResBit29 (and (const 1) (srl val (const 29)))) - (set coreCfgResBit30 (and (const 1) (srl val (const 30)))) - (set coreCfgResBit31 (and (const 1) (srl val (const 31)))) - - (set (raw-reg USI h-core-registers index) val) - ;; check LSB of CONFIG for rounding mode - (c-call "epiphany_set_rounding_mode" val) - ) - ) - ((eq index (const 1)) ;STATUS reg ; TODO check which bits can be set or clear - (sequence ((USI newval)) - (set newval (and val (const #xfff2))) - (set extFstallbit (and (const 1) (srl newval (const 19)))) - (set expcause2bit (and (const 1) (srl newval (const 18)))) - (set expcause1bit (and (const 1) (srl newval (const 17)))) - (set expcause0bit (and (const 1) (srl newval (const 16)))) - (set busbit (and (const 1) (srl newval (const 15)))) - (set bisbit (and (const 1) (srl newval (const 13)))) - (set bvsbit (and (const 1) (srl newval (const 14)))) - (set vsbit (and (const 1) (srl newval (const 12)))) - (set bvbit (and (const 1) (srl newval (const 10)))) - (set bcbit (and (const 1) (srl newval (const 11)))) - (set bnbit (and (const 1) (srl newval (const 9)))) - (set bzbit (and (const 1) (srl newval (const 8)))) - (set vbit (and (const 1) (srl newval (const 7)))) - (set cbit (and (const 1) (srl newval (const 6)))) - (set nbit (and (const 1) (srl newval (const 5)))) - (set zbit (and (const 1) (srl newval (const 4)))) - (set sflagbit (and (const 1) (srl newval (const 3)))) - (set kmbit (and (const 1) (srl newval (const 2)))) - ;;(set gie (and (const 1) (srl newval (const 1)))) - (set (raw-reg SI h-core-registers (const 1)) newval) - )) - ;; causes simulator errors - ;; ((eq index (const 2)) ;PC reg - ;; (set pc val)) - - (else (set (raw-reg USI h-core-registers index) val)) - )) -) - ; (define-pmacro (hcr-config) (reg h-core-registers 0)) etc. -(.splice begin (.unsplice (.map - (.pmacro (xname xnum) - (define-pmacro ((.sym hcr- xname)) (reg h-core-registers xnum))) - - ( - config - status - pc - debug - iab - lc - ls - le - iret - imask - ilat - ilatst - ilatcl - ipend - ctimer0 - ctimer1 - hstatus - - - - ) - - (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 - ) - ))) - - - -;; DMA registers in MMR space -(define-hardware - (name h-coredma-registers) - (comment "DMA registers in MMR space") - (type register USI (16)) - (attrs) - (indices extern-keyword crdma-names) - ) - -;; MEM registers in MMR space -(define-hardware - (name h-coremem-registers) - (comment "MEM registers in MMR space") - (type register USI (4)) - (attrs) - (indices extern-keyword crmem-names) - ) - -;; MEM registers in MMR space -(define-hardware - (name h-coremesh-registers) - (comment "MESH registers in MMR space") - (type register USI (4)) - (attrs) - (indices extern-keyword crmesh-names) - ) - - - - ; Operands - - ; Branch displacements -(define-operand - (name simm24) - (comment "branch address pc-relative") - (attrs RELAX) - (type h-iaddr) - (index f-simm24) - (handlers (parse "branch_addr"))) - -(define-operand - (name simm8) - (comment "branch address pc-relative") - (attrs RELAX) - (type h-iaddr) - (index f-simm8) - (handlers (parse "branch_addr"))) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Register operands -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define-pmacro (short-regs nm group hw cmt) - (define-operand - (name nm) - (comment cmt) - (attrs) - (type hw) - (index (.sym "f-r" group)) - (handlers (parse "shortregs") (print "keyword")) - ) - ) - -(define-pmacro (short-regs-core nm group hw cmt) - (define-operand - (name nm) - (comment cmt) - (attrs) - (type hw) - (index (.sym "f-s" group)) - (handlers (parse "shortregs") (print "keyword")) - ) - ) - - - ; short regs (0-7) -(short-regs rd d h-registers "destination register") -(short-regs rn n h-registers "source register") -(short-regs rm m h-registers "source register") - -(short-regs frd d h-fpregisters "fp destination register") -(short-regs frn n h-fpregisters "fp source register") -(short-regs frm m h-fpregisters "fp source register") - - ; long regs (0-63) -(dnop rd6 "destination register" () h-registers f-rd6) -(dnop rn6 "source register" () h-registers f-rn6) -(dnop rm6 "source register" () h-registers f-rm6) - -(dnop frd6 "fp destination register" () h-fpregisters f-rd6) -(dnop frn6 "fp source register" () h-fpregisters f-rn6) -(dnop frm6 "fp source register" () h-fpregisters f-rm6) - - ; special regs (0-7) -(short-regs-core sd d h-core-registers "special destination") -(short-regs-core sn n h-core-registers "special source") - - ; special regs (long form) -(dnop sd6 "special destination register" () h-core-registers f-sd6) -(dnop sn6 "special source register" () h-core-registers f-sn6) - -(dnop sddma "dma register" () h-coredma-registers f-sd6) -(dnop sndma "dma register" () h-coredma-registers f-sn6) -(dnop sdmem "mem register" () h-coremem-registers f-sd6) -(dnop snmem "mem register" () h-coremem-registers f-sn6) -(dnop sdmesh "mesh register" () h-coremesh-registers f-sd6) -(dnop snmesh "mesh register" () h-coremesh-registers f-sn6) - - ; Immediate literals - but don't allow register names! -(define-pmacro (dimmop nm cmt hwtype idx) - (define-operand (name nm) (comment cmt) (type hwtype) (index idx) - (attrs RELAX) - (handlers (parse "simm_not_reg") - (print "simm_not_reg"))) - ) - -(dimmop simm3 "signed 3-bit literal" h-sint f-sdisp3) -(dimmop simm11 "signed 11-bit literal" h-sint f-sdisp11) -(dnop disp3 "short data displacement" () h-uint f-disp3) -(dnop trapnum6 "parameter for swi or trap" () h-uint f-trap-num) - -(define-pmacro (duimmop nm cmt hwtype idx) - (define-operand (name nm) (comment cmt) (type hwtype) (index idx) - (attrs) - (handlers (parse "uimm_not_reg") - (print "uimm_not_reg"))) - ) - -(duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num) -(duimmop disp11 "sign-magnitude data displacement" h-uint f-disp11) - -(dnop shift "immediate shift amount" () h-uint f-shift) - -(define-operand (name imm16) (comment "16-bit unsigned literal") (attrs RELAX) - (type h-addr) (index f-imm16) (handlers (parse "imm16"))) -(define-operand (name imm8) (comment "8-bit unsigned literal") (attrs RELAX) - (type h-addr) (index f-imm8) (handlers (parse "imm8"))) - -(define-operand - (name direction) - (comment "+/- indexing") - (attrs) - (type h-uint) - (index f-addsubx) - (handlers (parse "postindex") - (print "postindex"))) - -(define-operand - (name dpmi) - (comment "+/- magnitude immediate displacement") - (attrs) - (type h-uint) - (index f-subd) - (handlers (parse "postindex") - (print "postindex"))) - - - -;; call exception macro - no check for imask -(define-pmacro (call-exception vaddr bit-in-ilat) - (if (eq gidisablebit 0) - (if (eq (and (hcr-imask) bit-in-ilat) 0) - (sequence () - (set kmbit 1) - (set gidisablebit 1) - (set (hcr-iret) (add pc (const 2))) - (set (hcr-ipend) (or (hcr-ipend) (const bit-in-ilat))) - (set pc (const vaddr)) - - ) - ;; schedule interrupt - (set (hcr-ilat) (or (hcr-ilat) (const bit-in-ilat))) - ) - ) - ) - - -;; (lc 5);loop counter Not impemented -;; (ls 6);loop start address Not impemented -;; (le 7);loop end address Not impemented - -;;have callback to adjust pc in case od events ( HW loops ... ) -(define-pmacro (dni_wrapper isnid stdrdesc attr_ strassembl iopcode proceed null_b) - (begin - (dni isnid stdrdesc attr_ strassembl iopcode - (sequence () proceed - (sequence ((USI tmpPC)) - ;;(set tmpPC (c-call USI "epiphany_post_isn_callback" pc)) - - (if (eq pc (hcr-le)) - (set (hcr-lc) (sub (hcr-lc) #x1))) - (if (and - (eq pc (hcr-le)) - (not (eq (hcr-lc) #x0))) - (set pc (hcr-ls))) - ) - ) - null_b) - ) - ) - - - - - -;; Some handy macros -;; - -;; define instructions -;; Short (16 bit forms) must appear first so that instruction -;; selection can reject them and match long forms when registers -;; or immediates exceed the values in the 16 bit instructions - - -;; B<COND> SIMM8 -;; B<COND> SIMM24 - -(define-pmacro (br-insn name cond g-op) - (begin - ; the 16-bit versions of branch - (dni (.sym "b" name "16") - (.str "Conditional Branch - 16 bit" name) - (COND-CTI SHORT-INSN) - (.str "b" name ".s $simm8") - (+ OP4_BRANCH16 (.sym "OPC_" cond) simm8) - (if (g-op) - (set pc simm8) - ) - () - ) - - (dnmi (.sym "b" name "16r") "relaxable conditional branch" - (COND-CTI RELAXABLE) - (.str "b" name " $simm8") - (emit (.sym "b" name "16") simm8) - ) - - (dni (.sym "b" name) - (.str "Conditional Branch " name) - (COND-CTI) - (.str "b" name ".l $simm24") - (+ OP4_BRANCH (.sym "OPC_" cond) simm24) - (if (g-op) - (set pc simm24) - ) - () - ) - - (dnmi (.sym "b" name "32r") "relaxable conditional branch" - (COND-CTI RELAXED) - (.str "b" name " $simm24") - (emit (.sym "b" name) simm24) - ) - ) - ) - - - ; basic conditional branches for integer arithmetic -(br-insn "eq" EQ (.pmacro () (eq zbit #x1))) -(br-insn "ne" NE (.pmacro () (eq zbit #x0))) -(br-insn "gtu" GTU (.pmacro () (and BI cbit (not BI zbit)))) -(br-insn "gteu" GTEU (.pmacro () (eq cbit #x1))) -(br-insn "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit))) -(br-insn "ltu" LTU (.pmacro () (eq cbit #x0))) -(br-insn "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit)))) -(br-insn "gte" GTE (.pmacro () (eq vbit nbit))) -(br-insn "lt" LT (.pmacro () (xor BI vbit nbit))) -(br-insn "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit)))) - - - ; floating point condition codes (floating point instructions) -(br-insn "beq" BEQ (.pmacro () (or BI bzbit bzbit))) -(br-insn "bne" BNE (.pmacro () (not BI bzbit))) -(br-insn "blt" BLT (.pmacro () (and BI bnbit (not bzbit)))) -(br-insn "blte" BLTE (.pmacro () (or BI bnbit bzbit))) - - ; unconditional branches -(dni b16 "short unconditional branch" (UNCOND-CTI SHORT-INSN) - "b.s $simm8" - (+ OP4_BRANCH16 OPC_B simm8) - (set pc simm8) - () - ) - -(dnmi b16r "relaxable b16" - (UNCOND-CTI RELAXABLE) - "b $simm8" - (emit b16 simm8) - ) - -(dni b "long unconditional branch" (UNCOND-CTI) - "b.l $simm24" - (+ OP4_BRANCH OPC_B simm24) - (set pc simm24) - () - ) - -(dnmi b32r "relaxable b" - (UNCOND-CTI RELAXED) - "b $simm24" - (emit b simm24)) - -;; BL R,ADDR - -(dni bl16 "branch and link" - (UNCOND-CTI SHORT-INSN) - ("bl.s $simm8") - (+ OP4_BRANCH16 OPC_BL simm8) - (sequence () - (set (reg h-registers 14) (add pc (const 2))) - (set pc simm8)) - () - ) - -(dnmi bl16r "bl16 relaxable" - (UNCOND-CTI RELAXABLE) - "bl $simm8" - (emit bl16 simm8)) - -(dni bl "branch and link" - (UNCOND-CTI) - ("bl.l $simm24") - (+ OP4_BRANCH OPC_BL simm24) - (sequence () - (set (reg h-registers 14) (add pc (const 4))) - (set pc simm24)) - () - ) - -(dnmi blr "bl relaxable" - (UNCOND-CTI RELAXED) - "bl $simm24" - (emit bl simm24)) - -;; JUMP <RN> -(dni jr16 "unconditional jump 16" - (UNCOND-CTI SHORT-INSN) - ("jr $rn") - (+ OP4_FLOW16 (f-opc-8-5 #x14) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn) - (set pc rn) - () - ) - -;; RTS / JR -;; ??? Putting a constant into a multi-ifield does not work - -;; the constant gets inserted in full into each part. - ;(dnmi rts "return from subroutine" - ; (UNCOND-CTI) - ; ("rts") - ; (emit jr (rn6 14)) ; jr lr / jr r14 - ;) -;; RTS / JR -(dni rts "return from subroutine" - (ALIAS UNCOND-CTI) - ("rts") - (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) (f-rn 6) (f-rn-x 1) - (f-dc-9-1 #x0) - (f-dc-15-3 #x0) - (f-dc-25-6 #x0) - (f-dc-31-3 #x0) - ) - (set pc (reg h-registers 14)) - () - ) - -(dni jr "unconditional jump" - (UNCOND-CTI) - ("jr $rn6") - (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) rn6 - (f-dc-9-1 #x0) - (f-dc-15-3 #x0) - (f-dc-25-6 #x0) - (f-dc-31-3 #x0) - ) - (set pc rn6) - () - ) - - -;; JALR <RN> -(dni jalr16 "jump and link register" - (UNCOND-CTI SHORT-INSN) - ("jalr $rn") - (+ OP4_FLOW16 (f-opc-8-5 #x15) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn) - (sequence () - (set (reg h-registers 14) (add pc (const 2))) - (set pc rn) - ) - () - ) - -(dni jalr "jump and link register" - (UNCOND-CTI) - ("jalr $rn6") - (+ OP4_MISC - (f-opc-8-5 #x15) - (f-opc-19-4 #x2) - rn6 - (f-dc-9-1 #x0) - (f-dc-15-3 #x0) - (f-dc-25-6 #x0) - (f-dc-31-3 #x0) - - ) - (sequence () - (set (reg h-registers 14) (add pc (const 4))) - (set pc rn6)) - () - ) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; Load/Store Memory Instructions -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - -(define-pmacro (callMisaligmentExceptionIfNeeded sel addr isAligmentAccess) - (sequence ((BI scale)) - (set isAligmentAccess - (case BI sel - ((OPW_BYTE) (eq (and addr #x0) #x0)) - ((OPW_SHORT) (eq (and addr #x1) #x0)) - ((OPW_WORD) (eq (and addr #x3) #x0)) - (else (eq (and addr #x7) #x0)))) - (if (not BI isAligmentAccess) - (call-exception #x4 #x2)) - ) -) - - - -;; helper to convert size selector OPW_<mode> into a literal scale factor -(define-pmacro (ConvertSelectorToShift sel scale) - (set scale - (case SI sel - ((OPW_BYTE) (const 0)) - ((OPW_SHORT) (const 1)) - ((OPW_WORD) (const 2)) - (else (const 3)))) -) - -;; common load macros from effective address, handling 8/16/32/64 bits -(define-pmacro (load-double-from-ea regnum eff-addr mode sel) - (sequence ((SI loadaddr) (BI isAligmentAccess)) - (set loadaddr eff-addr) - (callMisaligmentExceptionIfNeeded sel loadaddr isAligmentAccess) - - (if (not (not BI isAligmentAccess)) - (sequence () - (set memaddr loadaddr) - (set regnum (mem SI loadaddr)) - (set loadaddr (add loadaddr (const 4))) - (set memaddr loadaddr) - (set (reg h-registers - (add (index-of regnum) - (const 1))) - (mem SI loadaddr)) - - ) - ) - ) - ) - -(define-pmacro (load-from-ea regnum eff-addr mode sel) - (sequence ((BI isAligmentAccess)) - - (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess) - (if (not (not BI isAligmentAccess)) - (sequence () - (set memaddr eff-addr) - (set regnum (zext SI (mem mode eff-addr))) - ) - ) - ) - ) ;; 8/16/32 bit cases - - -;; common store to effective address, handling 8/16/32/64 bit data -(define-pmacro (store-double-to-ea eff-addr regnum mode sel) - (sequence ((SI storeaddr) (BI isAligmentAccess)) - (set storeaddr eff-addr) - (callMisaligmentExceptionIfNeeded sel storeaddr isAligmentAccess) - (if (not (not BI isAligmentAccess)) - (sequence () - (set memaddr storeaddr) - (set (mem SI storeaddr) regnum) - (set storeaddr (add storeaddr (const 4))) - (set memaddr storeaddr) - (set (mem SI storeaddr) - (reg h-registers (add (index-of regnum) (const 1)))) - ) - ) - ) - ) - -(define-pmacro (store-to-ea eff-addr regnum mode sel) - (sequence ((BI isAligmentAccess)) - (callMisaligmentExceptionIfNeeded sel eff-addr isAligmentAccess) - (if (not (not BI isAligmentAccess)) - (sequence () - (set memaddr eff-addr) - (set (mem mode eff-addr) regnum) - ) - ) - ) - ) ;8/16/32 bit cases - - -(define-pmacro (load-insn name mode sel sem-op) - (begin - (dni_wrapper (.sym name "x16.s") - (.str "load " mode " indexed") - (SHORT-INSN) - (.str name " $rd,[$rn,$rm]") - (+ OP4_LDSTR16X sel OP_LOAD rd rn rm) - (sequence () - (sem-op rd (add rn rm) mode sel)) - () - ) - - - (dni_wrapper (.sym name "p16.s") - (.str "load " mode " postmodify") - (SHORT-INSN) - (.str name " $rd,[$rn],$rm") - (+ OP4_LDSTR16P sel OP_LOAD rd rn rm) - (sequence ((SI tmprm)) - (set tmprm rm) - (sem-op rd rn mode sel) - (set rn (add rn tmprm))) - () - ) - - - (dni_wrapper (.sym name "x.l") - (.str "load " mode " indexed") - () - (.str name " $rd6,[$rn6,$direction$rm6]") - (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6) - (sequence () - (if (ifield f-addsubx) - (sem-op rd6 (sub rn6 rm6) mode sel) - (sem-op rd6 (add rn6 rm6) mode sel))) - () - ) - - (dnmi (.sym name "x") - (.str "load " mode " indexed") - (NO-DIS) - (.str name ".l $rd6,[$rn6,$direction$rm6]") - (emit (.sym name "x.l") rd6 rn6 direction rm6) - ) - - - - (dni_wrapper (.sym name "p.l") - (.str "load " mode " postmodify") - () - (.str name " $rd6,[$rn6],$direction$rm6") - (+ OP4_LDSTRP sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6) - (sequence ((SI tmprm)) - (set tmprm rm6) - (sem-op rd6 rn6 mode sel) - (if (ifield f-addsubx) - (set rn6 (sub rn6 tmprm)) - (set rn6 (add rn6 tmprm))) - ) - () - ) - - - (dnmi (.sym name "p") - (.str "load " mode " postmodify") - (NO-DIS) - (.str name ".l $rd6,[$rn6],$direction$rm6") - (emit (.sym name "p.l") rd6 rn6 direction rm6) - ) - - - ;;immediate modes last so reg forms found first. - (dni_wrapper (.sym name "d16.s") - (.str "load " mode " displacement") - (SHORT-INSN IMM3) - (.str name " $rd,[$rn,$disp3]") - (+ OP4_LDSTR16D sel OP_LOAD rd rn disp3) ;; convert size to 'B' - (sequence ((SI effa) - (SI scale)) - (ConvertSelectorToShift sel scale) - (set effa (add rn (sll disp3 scale))) - (sem-op rd effa mode sel) - ) - () - ) - - - (dni_wrapper (.sym name "d.l") - (.str "load " mode " displacement") - () - (.str name " $rd6,[$rn6,$dpmi$disp11]") - (+ OP4_LDSTRD sel OP_LOAD PMOD_DISP rd6 rn6 dpmi disp11) - (sequence ((SI effa) - (SI scale)) - (ConvertSelectorToShift sel scale) - (if dpmi - (set effa (sub rn6 (sll disp11 scale))) - (set effa (add rn6 (sll disp11 scale))) - ) - (sem-op rd6 effa mode sel) - ) - () - ) - - (dnmi (.sym name "d") - (.str "load " mode " displacement") - (NO-DIS) - (.str name ".l $rd6,[$rn6,$dpmi$disp11]") - (emit (.sym name "d.l") rd6 rn6 dpmi disp11) - ) - - - - (dni_wrapper (.sym name "dpm.l") - (.str "load " mode " displacement post-modify") - () - (.str name " $rd6,[$rn6],$dpmi$disp11") - (+ OP4_LDSTRD sel OP_LOAD PMOD_POST rd6 rn6 dpmi disp11) - (sequence ((SI scale)) - (ConvertSelectorToShift sel scale) - (sem-op rd6 rn6 mode sel) - (if dpmi - (set rn6 (sub rn6 (sll disp11 scale))) - (set rn6 (add rn6 (sll disp11 scale))) - ) - ) - () - ) - - (dnmi (.sym name "dpm") - (.str "load " mode " displacement post-modify") - (NO-DIS) - (.str name ".l $rd6,[$rn6],$dpmi$disp11") - (emit (.sym name "dpm.l") rd6 rn6 dpmi disp11) - ) - - - ;; ;; macro form with a zero displacement - (dnmi (.sym name "ds0") "load with 0 disp" - (SHORT-INSN IMM3) - (.str name " $rd,[$rn]") - (emit (.sym name "d16.s") rd rn (disp3 0)) - ) - (dnmi (.sym name "dl0") "load with 0 disp" - (NO-DIS) - (.str name " $rd6,[$rn6]") - (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0)) - ) - (dnmi (.sym name "dl0.l") "load with 0 disp" - (NO-DIS) - (.str name ".l $rd6,[$rn6]") - (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0)) - ) - - - ) - ) - -(load-insn ldrb QI OPW_BYTE load-from-ea) -(load-insn ldrh HI OPW_SHORT load-from-ea) -(load-insn ldr SI OPW_WORD load-from-ea) -(load-insn ldrd DI OPW_DOUBLE load-double-from-ea) - - - - -;; TMP = MEM[RD+RM]; /* Copy content of memory to tmp. */ -;; if (~TMP) /* Check if memory location is zero. */ -;; MEM[RD+RM] = RD; /* If zero, write RD to memory. */ -;; RD = TMP; /* Always write tmp into RD (NOTE it's destructive). */ - - -(define-pmacro (testset-insn name mode sel) - (begin - - - (dni_wrapper (.sym name "t") - (.str "testset " mode " indexed") - () - (.str name " $rd6,[$rn6,$direction$rm6]") - (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x1) - rd6 rn6 direction rm6) - (sequence ((SI tmemaddr) (SI tmpValReg)) - - ;;back up register - (set tmpValReg rd6) - - (if (ifield f-addsubx) - (set tmemaddr (sub rn6 rm6)) - (set tmemaddr (add rn6 rm6)) - ) - ;;always update rd - (load-from-ea rd6 tmemaddr mode sel) - ;;if zero - (if rd6 - (nop) - (set (mem mode tmemaddr) tmpValReg) - ) - - ) - () - ) - - - (dnmi (.sym name "t.l") - (.str "testset " mode ".l indexed") - (NO-DIS) - (.str name ".l $rd6,[$rn6,$direction$rm6]") - (emit (.sym name "t") rd6 rn6 direction rm6) - ) - - - ) - ) - -(testset-insn testsetb QI OPW_BYTE) -(testset-insn testseth HI OPW_SHORT) -(testset-insn testset SI OPW_WORD) -;;no double mode support, since we have to send the src address, data -;;(testset-insn testsetd DI OPW_DOUBLE load-double-from-ea) - - - -;; need 16 bit forms too -(define-pmacro (store-insn name mode sel sem-op) - (begin - (dni_wrapper (.sym name "x16") - (.str "store" mode " indexed") - (SHORT-INSN) - (.str name " $rd,[$rn,$rm]") - (+ OP4_LDSTR16X sel OP_STORE rd rn rm) - (sequence () - (sem-op (add rn rm) rd mode sel) - ) - () - ) - - (dni_wrapper (.sym name "x") - (.str "store" mode " indexed") - () - (.str name " $rd6,[$rn6,$direction$rm6]") - (+ OP4_LDSTRX sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6) - (sequence () - (if (ifield f-addsubx) - (sem-op (sub rn6 rm6) rd6 mode sel) - (sem-op (add rn6 rm6) rd6 mode sel) - )) - () - ) - - (dnmi (.sym name "x.l") - (.str "store" mode " indexed") - (NO-DIS) - (.str name ".l $rd6,[$rn6,$direction$rm6]") - (emit (.sym name "x") rd6 rn6 direction rm6) - ) - - - - - - (dni_wrapper (.sym name "p16") - (.str "store " mode " postmodify") - (SHORT-INSN) - (.str name " $rd,[$rn],$rm") - (+ OP4_LDSTR16P sel OP_STORE rd rn rm) - (sequence () - (sem-op rn rd mode sel) - (set rn (add rn rm)) - ) - () - ) - - (dni_wrapper (.sym name "p") - (.str "store " mode " postmodify") - () - (.str name " $rd6,[$rn6],$direction$rm6") - (+ OP4_LDSTRP sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6) - (sequence () - (sem-op rn6 rd6 mode sel) - (if (ifield f-addsubx) - (set rn6 (sub rn6 rm6)) - (set rn6 (add rn6 rm6))) - ) - () - ) - (dnmi (.sym name "p.l") - (.str "store " mode " postmodify") - (NO-DIS) - (.str name ".l $rd6,[$rn6],$direction$rm6") - (emit (.sym name "p") rd6 rn6 direction rm6) - ) - - (dni_wrapper (.sym name "d16") - (.str "store " mode " displacement") - (SHORT-INSN IMM3) - (.str name " $rd,[$rn,$disp3]") - (+ OP4_LDSTR16D sel OP_STORE rd rn disp3) ;; convert size to 'B' - (sequence ((SI effa) - (SI scale)) - (ConvertSelectorToShift sel scale) - (set effa (add rn (sll disp3 scale))) - (sem-op effa rd mode sel) - ) - () - ) - - (dni_wrapper (.sym name "d") - (.str "store " mode " displacement") - () - (.str name " $rd6,[$rn6,$dpmi$disp11]") - (+ OP4_LDSTRD sel OP_STORE PMOD_DISP rd6 rn6 dpmi disp11) - (sequence ((SI effa) - (SI scale)) - (ConvertSelectorToShift sel scale) - (if dpmi - (set effa (sub rn6 (sll disp11 scale))) - (set effa (add rn6 (sll disp11 scale))) - ) - (sem-op effa rd6 mode sel) - ) - () - ) - - (dnmi (.sym name "d.l") - (.str "store " mode " displacement") - (NO-DIS) - (.str name ".l $rd6,[$rn6,$dpmi$disp11]") - (emit (.sym name "d") rd6 rn6 dpmi disp11) - ) - - - (dni_wrapper (.sym name "dpm") - (.str "store " mode " displacement post-modify") - () - (.str name " $rd6,[$rn6],$dpmi$disp11") - (+ OP4_LDSTRD sel OP_STORE PMOD_POST rd6 rn6 dpmi disp11) ;; convert size to 'B' - (sequence ((SI scale)) - (ConvertSelectorToShift sel scale) - (sem-op rn6 rd6 mode sel) - (if dpmi - (set rn6 (sub rn6 (sll disp11 scale))) - (set rn6 (add rn6 (sll disp11 scale))) - ) - ) - () - ) - (dnmi (.sym name "dpm.l") - (.str "store " mode " displacement post-modify") - (NO-DIS) - (.str name ".l $rd6,[$rn6],$dpmi$disp11") - (emit (.sym name "dpm") rd6 rn6 dpmi disp11) - ) - - ;; macro form with a zero displacement - (dnmi (.sym name "ds0") "store w 0 disp" - (SHORT-INSN IMM3) - (.str name " $rd,[$rn]") - (emit (.sym name "d16") rd rn (disp3 0)) - ) - - (dnmi (.sym name "dl0") "store w 0 disp" - () - (.str name " $rd6,[$rn6]") - (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0)) - ) - - (dnmi (.sym name "dl0.l") "store w 0 disp" - (NO-DIS) - (.str name ".l $rd6,[$rn6]") - (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0)) - ) - - - - ) - ) - -(store-insn strb QI OPW_BYTE store-to-ea) -(store-insn strh HI OPW_SHORT store-to-ea) -(store-insn str SI OPW_WORD store-to-ea) -(store-insn strd DI OPW_DOUBLE store-double-to-ea) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; MOV<COND> RD,RN -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define-pmacro (move-insns name cond g-op) - (begin - (dni_wrapper (.sym "cmov16" cond) - (.str "move register " cond) - (SHORT-INSN) - (.str "mov" name " $rd,$rn") - (+ OP4_FLOW16 (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) rd rn) - (if (g-op) - (set rd rn)) - () - ) - - (dni_wrapper (.sym "cmov" cond) - (.str "move register " cond) - () - (.str "mov" name " $rd6,$rn6") - (+ OP4_MISC (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-6 #x0) rd6 rn6) - (if (g-op) - (set rd6 rn6)) - () - ) - (dnmi (.sym "cmov.l" cond) - (.str "move register " cond) - (NO-DIS) - (.str "mov" name ".l $rd6,$rn6") - (emit (.sym "cmov" cond) rd6 rn6) - ) - - - - ) - ) - - ; basic conditional moves -(move-insns "eq" EQ (.pmacro () (eq zbit #x1))) -(move-insns "ne" NE (.pmacro () (eq zbit #x0))) -(move-insns "gtu" GTU (.pmacro () (and BI cbit (not BI zbit)))) -(move-insns "gteu" GTEU (.pmacro () (eq cbit #x1))) -(move-insns "lteu" LTEU (.pmacro () (or BI (not BI cbit) zbit))) -(move-insns "ltu" LTU (.pmacro () (eq cbit #x0))) -(move-insns "gt" GT (.pmacro () (and BI (not BI zbit) (eq vbit nbit)))) -(move-insns "gte" GTE (.pmacro () (eq vbit nbit))) -(move-insns "lt" LT (.pmacro () (xor BI vbit nbit))) -(move-insns "lte" LTE (.pmacro () (or BI zbit (xor vbit nbit)))) - - ; unconditional move -(move-insns "" B (.pmacro () #x1)) - - - ; floating point condition codes (floating point instructions) -(move-insns "beq" BEQ (.pmacro () (or BI bzbit bzbit))) -(move-insns "bne" BNE (.pmacro () (not BI bzbit))) -(move-insns "blt" BLT (.pmacro () (and BI bnbit (not bzbit)))) -(move-insns "blte" BLTE (.pmacro () (or BI bnbit bzbit))) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; MOVTS RD,RN -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; 16 bits form exists for group zero ( M1 and M0 equals to zero ) only - -(dni_wrapper movts16 - "move to special reg" - (SHORT-INSN) - "movts $sn,$rd" - (+ OP4_FLOW16 (f-opc-8-5 #x10) (f-dc-9-1 #x0) rd sn) ;; rd is source for movts - (set sn rd) - () - ) - -(define-pmacro (op-mmr-movts name sdreg code) - (begin - - (dni_wrapper (.sym "movts" name) - (.str "move to " name) - () - (.str "movts $" sdreg ",$rd6") - (+ OP4_MISC (f-dc-7-4 #x0) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) sdreg rd6);; rd is source for movts - (set sdreg rd6) - () - ) - - (dnmi (.sym "movts.l" name) - (.str "move to " name) - (NO-DIS) - (.str "movts.l $" sdreg ",$rd6") - (emit (.sym "movts" name) sdreg rd6) - ) - - - - - ) - ) - -(op-mmr-movts 6 sn6 #x0) -(op-mmr-movts dma sndma #x1) -(op-mmr-movts mem snmem #x2) -(op-mmr-movts mesh snmesh #x3) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; MOVFS -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper movfs16 - "move from special register" - (SHORT-INSN) - "movfs $rd,$sn" - (+ OP4_FLOW16 (f-opc-8-5 #x11) (f-dc-9-1 #x0) rd sn) - (set rd sn) - () - ) - - - -(define-pmacro (op-mmr-movfs name snreg code) - (begin - - (dni_wrapper (.sym "movfs" name) - (.str "move from " name) - () - (.str "movfs $rd6,$" snreg) - (+ OP4_MISC (f-dc-7-4 #x1) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) rd6 snreg) - (set rd6 snreg) - () - ) - - (dnmi (.sym "movfs.l" name) - (.str "move from " name) - (NO-DIS) - (.str "movfs.l $rd6,$" snreg) - (emit (.sym "movfs" name) rd6 snreg) - ) - - - - ) - ) - -(op-mmr-movfs 6 sn6 #x0) -(op-mmr-movfs dma sndma #x1) -(op-mmr-movfs mem snmem #x2) -(op-mmr-movfs mesh snmesh #x3) - - - - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; NOP 0x1a2 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper nop - "no-operation" - (SHORT-INSN) - "nop" - (+ OP4_FLOW16 (f-opc-8-5 #x1a) (f-dc-15-7 #x0)) - (nop) - () - ) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; SNOP 0x3a2 -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper snop - "no-operation" - (SHORT-INSN) - "snop" - (+ OP4_FLOW16 (f-opc-8-5 #x3a) (f-dc-15-7 #x0)) - (nop) - () - ) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; UNIMPL -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper unimpl - "not-implemented" - () - "unimpl" - (+ (f-opc-31-32 #x000F000F)) - (nop) - () - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; IDLE -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(dni idle "idle until interrupt" () "idle" - (+ OP4_FLOW16 (f-opc-8-5 #x1b) (f-dc-15-7 #x0)) - ;; (set pc pc) ;; should branch to self until interrupt, but not modeling interrupts - (sequence () - (set caibit 0) - (c-code "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, \ - pc, sim_exited, 0);")) - () - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; BKPT -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(dni bkpt - "breakpoint" - (SHORT-INSN) - "bkpt" - (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x0)) - (sequence () - (c-call "epiphany_break" pc) - (set pc pc) - ) - () - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; MBKPT -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(dni mbkpt - "multicorebreakpoint" - (SHORT-INSN) - "mbkpt" - (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x1)) - ;;;(c-call "epiphany_break" pc) - (nop) ;; ignore the multi core break point in the simulator - () - ) - -;;;;;;;;;;;;;;;; -;; RTI -;;;;;;;;;;;;;;;; - -(dni rti "return from interrupt" (SHORT-INSN UNCOND-CTI) - "rti" - (+ OP4_FLOW16 (f-opc-8-5 #x1d) (f-dc-15-7 #x0)) - (sequence () - ;; (set (hcr-ipend) - ;; (xor (hcr-ipend) - ;; (sll (const 1) - ;; (sub (c-raw-call SI "ffs" (and (hcr-ipend) (not (hcr-imask)))) - ;; (const 1))))) - - (set (hcr-ipend) - (c-call SI "epiphany_rti" (hcr-ipend) (hcr-imask))) - (set gidisablebit 0) - (set kmbit 0) - ;(set caibit 1) - (set pc (hcr-iret))) - () - ) -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; WAND is a wired flag that runs around the chip -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper wand "wand" - (SHORT-INSN) - "wand" - (+ OP4_FLOW16 (f-opc-8-5 #x18) (f-dc-15-7 #x0)) - (set sflagbit 1) - () - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Sync likes wand, but wired OR -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper sync "sync" - (SHORT-INSN) - "sync" - (+ OP4_FLOW16 (f-opc-8-5 #x1f) (f-dc-15-7 #x0)) - (nop);;TODO - () - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; GIE -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper gien "global interrupt enable" - (SHORT-INSN) - "gie" - (+ OP4_FLOW16 (f-gien-gidis-9-1 #x0) (f-opc-8-5 #x19) (f-dc-15-6 #x0)) - (set gidisablebit 0) - () - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; GIDIS -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(dni_wrapper gidis "global interrupt disable" - (SHORT-INSN) - "gid" - (+ OP4_FLOW16 (f-gien-gidis-9-1 #x1) (f-opc-8-5 #x19) (f-dc-15-6 #x0)) - (set gidisablebit 1) - () - ) - - - -;;;;;;;;;;;;;;;; -;; SWI -;;;;;;;;;;;;;;;; - -;; Model only immediate 'fire' exception, if gien cleared or masked don't fire and don't check later - no ilat like behavior -(dni swi_num "software interrupt" (SHORT-INSN UNCOND-CTI) - "swi $swi_num" - (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) swi_num) - (sequence () (call-exception #x24 #x80)) - ;; (if (eq gie 1) - ;; (sequence () - ;; (set kmbit 1) - ;; (set gie 0) - ;; (set (hcr-iret) (add pc (const 2))) - ;; (set (hcr-ipend) (or (hcr-ipend) (const #x80))) - ;; (set pc (const #x1c)) - - ;; ) - ;; ;; schedule interrupt - ;; (set (hcr-ilat) (or (hcr-ilat) (const #x80))) - ;; ) - () - ) -(dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI) - "swi" - (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) (f-dc-15-6 #x0)) - (sequence () (call-exception #x24 #x80)) - () - ) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; TRAP #disp3 - simulator only and chip as well - make the same grouop as swi -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -;; Only defining 16-bit form of this instruction. It exists to support the -;; simulator, by giving us a simple input/output mechanism beyond returning values -;; in registers or memory. -;; TRAP #N - special sw trap for simulator support; allows simple i/o using fixed arguments -;; TRAP #0 - write (r0=i/o channel, r1=addr, r2=len) returns status in r0 -;; TRAP #1 - read (r0=i/o channel, r1=addr, r2=len) returns length or -<code> on error -;; TRAP #2 - open (r0=string path, r1=mode) returns channel# or -<code> on error -;; TRAP #3 - exit (r0=status code) never returns. -;; TRAP #4 - print "pass\n" and exit -;; TRAP #5 - print "fail\n" and exit -;; TRAP #6 - close (r0=i/o channel) - -(dni trap16 "trap to simulator" - (SHORT-INSN UNCOND-CTI) - "trap $trapnum6" - (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x1) trapnum6) ;; (+ OP4_IMM16 OPI_TRAP (f-rd 0) (f-rn 0) disp3) - (set (reg SI h-registers 0) (c-call SI "epiphany_trap" pc trapnum6)) - () - ) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Integer arithmetic instructions 3 address forms -;; both 16 and 32 bit forms -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define-pmacro (op-rrr name sem-op cond-op) - (begin - (dni_wrapper (.sym name "16") - (.str name) - (SHORT-INSN) - (.str name " $rd,$rn,$rm") - (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm) - (sequence () - (cond-op rn rm) - (set rd (sem-op SI rn rm)) - (set zbit (zflag rd)) - (set nbit (nflag rd)) - ) - () - ) - - (dni_wrapper (.sym name) - (.str name) - () - (.str name " $rd6,$rn6,$rm6") - (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6) - (sequence () - (cond-op rn6 rm6) - (set rd6 (sem-op SI rn6 rm6)) - (set zbit (zflag rd6)) - (set nbit (nflag rd6)) - ) - () - ) - - (dnmi (.sym name ".l") - (.str name) - (NO-DIS) - (.str name ".l $rd6,$rn6,$rm6") - (emit (.sym name) rd6 rn6 rm6) - ) - - - - ) - ) - -;; submacros to set condition codes -;; NZ are always set to reflect the sign and value of the result -;; CV are a function of the operator -(define-pmacro (add-vc a b) (sequence () - (set cbit (add-cflag SI a b 0)) - (set vbit (add-oflag SI a b 0)) - (set vsbit (or BI vsbit vbit)) - )) - -(define-pmacro (sub-vc a b) (sequence () - (set cbit (not (sub-cflag SI a b 0))) - (set vbit (sub-oflag SI a b 0)) - (set vsbit (or vsbit vbit)) - )) - -(define-pmacro (logic-vc a b) (sequence () - (set cbit 0) - (set vbit 0) - )) - -(op-rrr add add add-vc) -(op-rrr sub sub sub-vc) -(op-rrr and and logic-vc) -(op-rrr orr or logic-vc) -(op-rrr eor xor logic-vc) - -;; Integer arithmetic immediate forms - -(define-pmacro (op-rri name code cond-op) - (begin - (dni_wrapper (.sym name "i16") - (.str name) - (SHORT-INSN IMM3) - (.str name ".s $rd,$rn,$simm3") - (+ OP4_IMM16 code rd rn simm3) - (sequence () - (cond-op rn simm3) - (set rd (name SI rn simm3)) - (set zbit (zflag rd)) - (set nbit (nflag rd)) - ) - () - ) - - - (dni_wrapper (.sym name "i") - (.str name) - () - (.str name ".l $rd6,$rn6,$simm11") - (+ OP4_IMM32 code OPI_25_2_MBZ rd6 rn6 simm11) - (sequence () - (cond-op rn6 simm11) - (set rd6 (name SI rn6 simm11)) - (set zbit (zflag rd6)) - (set nbit (nflag rd6)) - ) - () - ) - - ;; (dnmi (.sym name "ri") "relaxed arithmetic immediate" (RELAXED) - ;; (.str name " $rd6,$rn6,$simm11") - ;; (emit (.sym name "i") rd6 rn6 simm11)) - ) - ) - -(op-rri add OPI_ADD add-vc) -(op-rri sub OPI_SUB sub-vc) - -(dnmi addir "relaxable short immediate add" (RELAXABLE IMM3) - "add $rd,$rn,$simm3" - (emit addi16 rd rn simm3)) - -(dnmi addi32r "relaxed long immediate add" (RELAXED) - "add $rd6,$rn6,$simm11" - (emit addi rd6 rn6 simm11)) - -;; Again, but not relaxable so that full sized registers are handled -(dnmi addi32m "relaxed long immediate add" () - "add $rd6,$rn6,$simm11" - (emit addi rd6 rn6 simm11)) - - -(dnmi subir "relaxable short immediate sub" (RELAXABLE IMM3) - "sub $rd,$rn,$simm3" - (emit subi16 rd rn simm3)) - -(dnmi subi32r "relaxed long immediate sub" (RELAXED) - "sub $rd6,$rn6,$simm11" - (emit subi rd6 rn6 simm11)) - -(dnmi subi32m "relaxed long immediate sub" () - "sub $rd6,$rn6,$simm11" - (emit subi rd6 rn6 simm11)) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Shift instructions 3 address forms -;; both 16 and 32 bit forms -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define-pmacro (shift-rrr name sem-op) - (begin - (dni_wrapper (.sym name "16") - (.str name) - (SHORT-INSN) - (.str name " $rd,$rn,$rm") - (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm) - (sequence () - (logic-vc rn rm) - (set rd (sem-op SI rn (and rm (const 31)))) - (set zbit (zflag rd)) - (set nbit (nflag rd)) - ) - () - ) - - (dni_wrapper (.sym name) - (.str name) - () - (.str name " $rd6,$rn6,$rm6") - (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6) - (sequence () - (logic-vc rn6 rm6) - (set rd6 (sem-op SI rn6 (and rm6 (const 31)))) - (set zbit (zflag rd6)) - (set nbit (nflag rd6)) - ) - () - ) - - (dnmi (.sym name ".l") - (.str name) - (NO-DIS) - (.str name ".l $rd6,$rn6,$rm6") - (emit (.sym name) rd6 rn6 rm6) - ) - ) - ) - -(shift-rrr asr sra) -(shift-rrr lsr srl) -(shift-rrr lsl sll) - -(define-pmacro (op-shift-rri name shortcode f5 longcode sem-op) - (begin - (dni_wrapper (.sym name "i16") - (.str name) - (SHORT-INSN) - (.str name " $rd,$rn,$shift") - (+ shortcode (f-opc-4-1 f5) rd rn shift) - (sequence () - (logic-vc rn shift) - (set rd (sem-op SI rn shift)) - (set zbit (zflag rd)) - (set nbit (nflag rd)) - ) - () - ) - (dni_wrapper (.sym name "i32") - (.str name) - () - (.str name " $rd6,$rn6,$shift") - (+ OP4_MISC (f-opc-4-1 f5) (f-opc-19-4 longcode) (f-dc-25-6 0) rd6 rn6 shift) - (sequence () - (logic-vc rn6 shift) - (set rd6 (sem-op SI rn6 shift)) - (set zbit (zflag rd6)) - (set nbit (nflag rd6)) - ) - () - ) - - (dnmi (.sym name "i32.l") - (.str name) - (NO-DIS) - (.str name ".l $rd6,$rn6,$shift") - (emit (.sym name "i32") rd6 rn6 shift) - ) - - - ) - ) - -(op-shift-rri lsr OP4_LSHIFT16 0 #x6 srl) -(op-shift-rri lsl OP4_LSHIFT16 1 #x6 sll) -(op-shift-rri asr OP4_ASHIFT16 0 #xe sra) - -;; BITR - bitreversal (FFT) -;; -;; From Dr Dobbs et al. -;; -;; unsigned int v; -;; v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1); ;; swap odd-even bits -;; v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2); ;; swap pairs -;; v = ((v >> 4) & 0x0f0f0f0f) | ((v & 0x0f0f0f0f) << 4); ;; swap nibbles -;; v = ((v >> 8) & 0x00ff00ff) | ((v & 0x00ff00ff) << 8); ;; swap bytes -;; v = (v >> 16) | (v << 16); ;; swap halves -(define-pmacro (bit-reversal dest src) - (sequence ((SI v)) - (set v src) - (set v (or (and (srl v 1) #x55555555) (sll (and v #x55555555) 1))) - (set v (or (and (srl v 2) #x33333333) (sll (and v #x33333333) 2))) - (set v (or (and (srl v 4) #x0f0f0f0f) (sll (and v #x0f0f0f0f) 4))) - (set v (or (and (srl v 8) #x00ff00ff) (sll (and v #x00ff00ff) 8))) - (set v (or (srl v 16) (sll v 16))) - (set dest v) - )) - -(dni_wrapper bitr16 "bit reverse short" - (SHORT-INSN) - ("bitr $rd,$rn") - (+ OP4_ASHIFT16 (f-opc-4-1 1) rd rn (f-shift 0)) - (sequence () - (bit-reversal rd rn) - (set zbit (zflag rd)) - (set nbit (nflag rd)) - (set cbit 0) - (set vbit 0) - ) - () - ) - -(dni_wrapper bitr "bit reverse" - () - ("bitr $rd6,$rn6") - (+ OP4_MISC (f-opc-4-1 1) (f-opc-19-4 #xe) (f-dc-25-6 0) rd6 rn6 (f-shift 0)) - (sequence () - (bit-reversal rd6 rn6) - (set zbit (zflag rd6)) - (set nbit (nflag rd6)) - (set cbit 0) - (set vbit 0) - ) - () - ) -(dnmi bitrl "bit reverse l" - (NO-DIS) - ("bitr.l $rd6,$rn6") - (emit bitr rd6 rn6) - ) - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Integer arithmetic instructions -;; Extended operation -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -(define-pmacro (op-iextrrr name cond-op) - (begin - - (dni_wrapper (.sym name) - (.str name) - () - (.str name " $rd6,$rn6,$rm6") - (+ OP4_MISC (.sym "OPBE_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-2 #x0) (f-dc-20-1 #x1) - rd6 rn6 rm6) - (sequence () - ;; TODO cond operation (cond-op rn6 rm6) - ;;(set rd6 (sem-op SI rn6 rm6)) - (set zbit (zflag rd6)) - (set nbit (nflag rd6)) - ) - () - ) - - (dnmi (.sym name ".l") - (.str name) - (NO-DIS) - (.str name ".l $rd6,$rn6,$rm6") - (emit (.sym name) rd6 rn6 rm6) - ) - ) - ) - -(op-iextrrr fext sub-vc) -(op-iextrrr fdep sub-vc) -(op-iextrrr lfsr sub-vc) - - - -;; Immediate moves. The 8 bit form is relaxed if it doesn't fit or is external -;; Move RD,#IMM -(dni_wrapper mov8 - "mov imm8" - (SHORT-INSN) - "mov.b $rd,$imm8" - (+ OP4_IMM16 (f-opc-4-1 #x0) rd imm8) - (set rd (zext SI imm8)) - () - ) - -(dnmi mov8r "mov imm8 relaxable" - (RELAXABLE) - "mov $rd,$imm8" - (emit mov8 rd imm8)) - -(dni_wrapper mov16 - "mov imm16" - () - "mov.l $rd6,$imm16" - (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x0) rd6 imm16) - (set rd6 (zext SI imm16)) - () - ) - -(dnmi mov16r "mov imm16 relaxable" - () - "mov $rd6,$imm16" - (emit mov16 rd6 imm16)) - -;; MOVE TO HIGH WORD -(dni_wrapper movt - "movt imm16" - () - "movt $rd6,$imm16" - (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x1) rd6 imm16) - (set rd6 (or (and SI rd6 (const #xffff)) ; keep low bits of rd - (sll SI imm16 (const 16)))) ; replacing just high bits - () - ) -(dnmi movtl - "movt imm16" - (NO-DIS) - "movt.l $rd6,$imm16" - (emit movt rd6 imm16) - ) - - - -;; FLOATING POINT OPERATIONS -;; TWO operands -(define-pmacro (op-two_operands-float name code) - (begin - (dni_wrapper - (.sym "f_" name "f16") - (.str "f_" name) - (SHORT-INSN) - (.str "f" name " $rd,$rn,$rm") - (+ OP4_DSP16 code rd rn rm) - (sequence () - (if - (eq arithmetic-modebit2 0) - (sequence ((SF fptemp) (SI sdtmp)) - (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rm)) - - ;;All bits are calculated in C - (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp)) - (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp)) - (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) - (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) - (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - (set rd sdtmp) - (if (or (and invExcEnbit bisbit) - (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit))) - (sequence () - (set expcause0bit (const 1)) - (set expcause1bit (const 1)) - (call-exception #x4 #x2))) - )) - (if (eq arithmetic-modebit2 1) - (sequence ((SI sdtmp)) - (set sdtmp (c-call SI (.str "epiphany_i" name) rd rn rm)) - ;; carry is not connected inb the design (set bcbit bcbit) - (set bzbit (zflag sdtmp)) - (set bnbit (nflag sdtmp)) - (set rd sdtmp))) - ) - - () - ) - (dnmi (.sym "i_" name "f16") - (.str "i_" name) - (SHORT-INSN NO-DIS) - (.str "i" name " $rd,$rn,$rm") - (emit (.sym "f_" name "f16") rd rn rm) - ) - - - (dni_wrapper - (.sym "f_" name "f32") - (.str "f_" name) - () - (.str "f" name " $rd6,$rn6,$rm6") - (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rm6) - (sequence () - (if - (eq arithmetic-modebit2 0) - (sequence ((SF fptemp) (SI sdtmp)) - (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6)) - - ;;All bits are calculated in C - (set bzbit (c-call BI "get_epiphany_fzeroflag" sdtmp)) - (set bnbit (c-call BI "get_epiphany_fnegativeflag" sdtmp)) - (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) - (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) - (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd6 sdtmp) - - (if (or (and invExcEnbit bisbit) - (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit))) - (sequence () - (set expcause0bit (const 1)) - (set expcause1bit (const 1)) - (call-exception #x4 #x2))) - ) - ) - (if (eq arithmetic-modebit2 1) - (sequence ((SI sdtmp)) - (set sdtmp (c-call SI (.str "epiphany_i" name) rd6 rn6 rm6)) - ;; carry is not connected inb the design (set bcbit bcbit) - (set bzbit (zflag sdtmp)) - (set bnbit (nflag sdtmp)) - (set rd6 sdtmp) - ) - ) - ) - () - ) - - (dnmi (.sym "f_" name "f32.l") - (.str "f_" name) - (NO-DIS) - (.str "f" name ".l $rd6,$rn6,$rm6") - (emit (.sym "f_" name "f32") rd6 rn6 rm6) - ) - (dnmi (.sym "i_" name "f32") - (.str "i_" name) - (NO-DIS) - (.str "i" name " $rd6,$rn6,$rm6") - (emit (.sym "f_" name "f32") rd6 rn6 rm6) - ) - (dnmi (.sym "i_" name "f32.l") - (.str "i_" name) - (NO-DIS) - (.str "i" name ".l $rd6,$rn6,$rm6") - (emit (.sym "f_" name "f32") rd6 rn6 rm6) - ) - - - - ) - ) - -(op-two_operands-float add OPF_ADD) -(op-two_operands-float sub OPF_SUB) -(op-two_operands-float mul OPF_MUL) -(op-two_operands-float madd OPF_MADD) -(op-two_operands-float msub OPF_MSUB) - -;; ONE operands -;; FABS -(define-pmacro (op-fabs-float name code) - (begin - (dni_wrapper (.sym "f_" name "f16") - (.str "f_" name) - (SHORT-INSN) - (.str "f" name " rd,rn") - (+ OP4_DSP16 code rd rn rn) - (sequence ((SF fptemp) (SI sdtmp)) - - ;(set sdtmp (and rn #x7fffffff)) - (set sdtmp (c-call SI (.str "epiphany_fabs") rd rn rn)) - - - (set bnbit (const SI 0)) - (set bzbit (eq SI sdtmp (const SI 0))) - - ;;TODO subnormal ?? - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd sdtmp) - ) - () - ) - - (dni_wrapper (.sym "f_" name "f32") - (.str "f_" name) - () - (.str "f" name " $rd6,$rn6") - (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6) - (sequence ((SF fptemp) (SI sdtmp)) - - - ;(set sdtmp (and rn6 #x7fffffff)) - - (set sdtmp (c-call SI (.str "epiphany_fabs") rd6 rn6 rn6)) - - - (set bnbit (const SI 0)) - (set bzbit (eq SI sdtmp (const SI 0))) - - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd6 sdtmp) - - ) - () - ) - - (dnmi (.sym "f_" name "f32.l") - (.str "f_" name) - (NO-DIS) - (.str "f" name ".l $rd6,$rn6") - (emit (.sym "f_" name "f32") rd6 rn6) - ) - - - ) - ) - -(op-fabs-float abs OPF_FABS) - - -(define-pmacro (op-fix2float-float name code) - (begin - (dni_wrapper (.sym "f_" name "f16") - (.str "f_" name) - (SHORT-INSN) - (.str "f" name " $rd,$rn") - (+ OP4_DSP16 code frd frn frn) - (sequence ((SF fptemp) (SI sdtmp)) - - (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn)) - - (set bnbit (lt SI sdtmp (const SI 0))) - (set bzbit (eq SI sdtmp (const SI 0))) - - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd sdtmp) - ) - () - ) - - - (dni_wrapper (.sym "f_" name "f32") - (.str "f_" name) - () - (.str "f" name " $rd6,$rn6") - (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6) - (sequence ((SF fptemp) (SI sdtmp)) - - (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rn6)) - - (set bnbit (lt SI sdtmp (const SI 0))) - (set bzbit (eq SI sdtmp (const SI 0))) - - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd6 sdtmp) - - ) - () - ) - - (dnmi (.sym "f_" name "f32.l") - (.str "f_" name) - (NO-DIS) - (.str "f" name ".l $rd6,$rn6") - (emit (.sym "f_" name "f32") rd6 rn6) - ) - ) - ) - -(op-fix2float-float loat OPF_FLOAT) - -(define-pmacro (op-float2fix-float name code) - (begin - (dni_wrapper (.sym "f_" name "f16") - (.str "f_" name) - (SHORT-INSN) - (.str "f" name " $rd,$rn") - (+ OP4_DSP16 code rd rn rn) - (sequence ((SF fptemp) (SI sdtmp)) - - (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn)) - - (set bzbit (zflag sdtmp)) - (set bnbit (nflag sdtmp)) - - (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) - (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) - (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) - - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd6 sdtmp) - - (if (or (and invExcEnbit bisbit) - (or (and ovfExcEnbit busbit) - (and unExcEnbit bvsbit))) - (sequence () - (set expcause0bit (const 1)) - (set expcause1bit (const 1)) - (call-exception #x4 #x2))) - (set rd sdtmp) - ) - () - ) - - - - (dni_wrapper (.sym "f_" name "f32") - (.str "f_" name) - () - (.str "f" name " $rd6,$rn6") - (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6) - (sequence ((SF fptemp) (SI sdtmp)) - - (set sdtmp (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6)) - - (set bzbit (zflag sdtmp)) - (set bnbit (nflag sdtmp)) - - (set bvbit (c-call BI "get_epiphany_foverflowflag" sdtmp)) - (set bubit (c-call BI "get_epiphany_funderflowflag" sdtmp)) - (set bibit (c-call BI "get_epiphany_finvalidflag" sdtmp)) - - (set bvsbit (or bvsbit bvbit)) - (set busbit (or busbit bubit)) - (set bisbit (or bisbit bibit)) - - (set rd6 sdtmp) - - (if (or (and invExcEnbit bisbit) - (or (and ovfExcEnbit busbit) - (and unExcEnbit bvsbit))) - (sequence () - (set expcause0bit (const 1)) - (set expcause1bit (const 1)) - (call-exception #x4 #x2)) - ) - - ) - () - ) - - (dnmi (.sym "f_" name "f32.l") - (.str "f_" name) - (NO-DIS) - (.str "f" name ".l $rd6,$rn6") - (emit (.sym "f_" name "f32") rd6 rn6) - ) - - - ) - ) - - - - - -(op-float2fix-float ix OPF_FIX) - -;; MAC (Multiply and Accumulate Instructions -;; (define-pmacro (op-mac-float name code) -;; (begin -;; (dni_wrapper (.sym "fm" name "f16") -;; (.str "fm" name) -;; (SHORT-INSN) -;; (.str "fm" name " $frd,$frn,$frm") -;; (+ OP4_DSP16 code frd frn frm) -;; (sequence ((SF fptemp)) -;; (set bvbit 0) -;; (set busbit 0) -;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd frm frn)) -;; (set bnbit (lt SF fptemp (const SF 0))) -;; (set bzbit (eq SF fptemp (const SF 0))) -;; (set bvsbit (or bvsbit bvbit)) -;; (set frd fptemp) -;; ; (set rd (subword SI frd 0)) -;; ) -;; () -;; ) - -;; (dni_wrapper (.sym "fm" name "f32") -;; (.str "fm" name) -;; () -;; (.str "fm" name " $frd6,$frn6,$frm6") -;; (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) frd6 frn6 frm6) -;; (sequence ((SF fptemp)) -;; (set bvbit 0) -;; (set busbit 0) -;; (set fptemp (c-call SF (.str "epiphany_fm" name) frd6 frm6 frn6)) -;; (set bnbit (lt SF fptemp (const SF 0))) -;; (set bzbit (eq SF fptemp (const SF 0))) -;; (set bvsbit (or bvsbit bvbit)) -;; (set frd6 fptemp) -;; ; (set rd6 (subword SI frd6 0)) -;; ) -;; () -;; ) -;; ) -;; ) - - - - - - - - ; extended floating point operation - - -(define-pmacro (op-fextop-float name code) - (begin - - (dni_wrapper (.sym "f_" name "f32") - (.str "f_" name) - () - (.str "f" name " $frd6,$frn6") - (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-2 #x0) (f-dc-20-1 #x1) frd6 frn6 frn6) - (sequence ((SF fptemp)) - (set bvbit 0) - (set busbit 0) - (set fptemp (c-call SF (.str "epiphany_f" name) frn6)) - (set bnbit (lt SF fptemp (const SF 0))) - (set bzbit (eq SF fptemp (const SF 0))) - (set bvsbit (or bvsbit bvbit)) - (set frd6 fptemp) - - ) - () - ) - - - (dnmi (.sym "f_" name "f32.l") - (.str "f_" name) - (NO-DIS) - (.str "f" name ".l $frd6,$frn6") - (emit (.sym "f_" name "f32") frd6 frn6) - ) - ) - ) - -(op-fextop-float recip OPF_FRECIP) -(op-fextop-float sqrt OPF_FSQRT) - - - - - diff --git a/binutils-2.24/cpu/epiphany.opc b/binutils-2.24/cpu/epiphany.opc deleted file mode 100755 index fefb396e..00000000 --- a/binutils-2.24/cpu/epiphany.opc +++ /dev/null @@ -1,416 +0,0 @@ -/* Adapteva epiphany opcode support. -*- C -*- - - Copyright 2009, 2011 Free Software Foundation, Inc. - - Contributed by Embecosm on behalf of Adapteva, Inc. - - This file is part of the GNU Binutils and of GDB. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* enumerate relaxation types for gas. */ -typedef enum epiphany_relax_types -{ - EPIPHANY_RELAX_NONE=0, - EPIPHANY_RELAX_NEED_RELAXING, - - EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */ - EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */ - - EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */ - EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */ - - EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */ - EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */ - - EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */ - EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */ - -} EPIPHANY_RELAX_TYPES; - -/* Override disassembly hashing... */ - -/* Can only depend on instruction having 4 decode bits which gets us to the - major groups of 16/32 instructions. */ -#undef CGEN_DIS_HASH_SIZE -#if 1 - -/* hash code on the 4 LSBs */ -#define CGEN_DIS_HASH_SIZE 16 - -#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf) -#else -#define CGEN_DIS_HASH_SIZE 1 -#define CGEN_DIS_HASH(buf, value) 0 -#endif - -extern const char * parse_shortregs (CGEN_CPU_DESC cd, - const char ** strp, - CGEN_KEYWORD * keywords, - long * valuep); - -extern const char * parse_branch_addr (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - int opinfo, - enum cgen_parse_operand_result * resultp, - bfd_vma *valuep); - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - - -/* -- opc.c */ - - - -/* -- asm.c */ -const char * -parse_shortregs (CGEN_CPU_DESC cd, - const char ** strp, - CGEN_KEYWORD * keywords, - long * regno) -{ - const char * errmsg; - - /* Parse register. */ - errmsg = cgen_parse_keyword (cd, strp, keywords, regno); - - if (errmsg) - return errmsg; - - if (*regno > 7) - errmsg = _("register unavailable for short instructions"); - - return errmsg; -} - -static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int, - long *); - -static const char * -parse_uimm_not_reg (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - unsigned long * valuep) -{ - long * svalp = (void *) valuep; - return parse_simm_not_reg (cd, strp, opindex, svalp); -} - -/* Handle simm3/simm11/imm3/imm12. */ - -static const char * -parse_simm_not_reg (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - long * valuep) -{ - const char * errmsg; - - int sign = 0; - int bits = 0; - - switch (opindex) - { - case EPIPHANY_OPERAND_SIMM3: - sign = 1; bits = 3; break; - case EPIPHANY_OPERAND_SIMM11: - sign = 1; bits = 11; break; - case EPIPHANY_OPERAND_DISP3: - sign = 0; bits = 3; break; - case EPIPHANY_OPERAND_DISP11: - /* Load/store displacement is a sign-magnitude 12 bit value. */ - sign = 0; bits = 11; break; - } - - /* First try to parse as a register name and reject the operand. */ - errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep); - if (!errmsg) - return _("register name used as immediate value"); - - errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep) - : cgen_parse_unsigned_integer (cd, strp, opindex, - (unsigned long *) valuep)); - if (errmsg) - return errmsg; - - if (sign) - errmsg = cgen_validate_signed_integer (*valuep, - -((1L << bits) - 1), (1 << (bits - 1)) - 1); - else - errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1); - - return errmsg; -} - -static const char * -parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char ** strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep) -{ - if (**strp == '#') - ++*strp; /* Skip leading hashes. */ - - if (**strp == '-') - { - *valuep = 1; - ++*strp; - } - else if (**strp == '+') - { - *valuep = 0; - ++*strp; - } - else - *valuep = 0; - - return NULL; -} - -static const char * -parse_imm8 (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - bfd_reloc_code_real_type code, - enum cgen_parse_operand_result * result_type, - bfd_vma * valuep) -{ - const char * errmsg; - enum cgen_parse_operand_result rt; - long dummyval; - - if (!result_type) - result_type = &rt; - - code = BFD_RELOC_NONE; - - if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) - || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, - &dummyval)) - /* Don't treat "mov ip,ip" as a move-immediate. */ - return _("register source in immediate move"); - - errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep); - if (errmsg) - return errmsg; - - if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff); - else - errmsg = _("byte relocation unsupported"); - - *valuep &= 0xff; - return errmsg; -} - -static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'"); - -static const char * -parse_imm16 (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - bfd_reloc_code_real_type code ATTRIBUTE_UNUSED, - enum cgen_parse_operand_result * result_type, - bfd_vma * valuep) -{ - const char * errmsg; - enum cgen_parse_operand_result rt; - long dummyval; - - if (!result_type) - result_type = &rt; - - if (strncasecmp (*strp, "%high(", 6) == 0) - { - *strp += 6; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH, - result_type, valuep); - if (**strp != ')') - return MISSING_CLOSE_PARENTHESIS; - ++*strp; - *valuep >>= 16; - } - else if (strncasecmp (*strp, "%low(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW, - result_type, valuep); - if (**strp != ')') - return MISSING_CLOSE_PARENTHESIS; - ++*strp; - } - else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, - &dummyval) - || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, - &dummyval)) - /* Don't treat "mov ip,ip" as a move-immediate. */ - return _("register source in immediate move"); - else - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, - result_type, valuep); - - if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff); - - *valuep &= 0xffff; - return errmsg; -} - -const char * -parse_branch_addr (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - int opinfo ATTRIBUTE_UNUSED, - enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED, - bfd_vma *valuep ATTRIBUTE_UNUSED) -{ - const char * errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - switch (opindex) - { - case EPIPHANY_OPERAND_SIMM24: - code = BFD_RELOC_EPIPHANY_SIMM24; - break; - - case EPIPHANY_OPERAND_SIMM8: - code = BFD_RELOC_EPIPHANY_SIMM8; - break; - - default: - errmsg = _("ABORT: unknown operand"); - return errmsg; - } - - errmsg = cgen_parse_address (cd, strp, opindex, code, - &result_type, &value); - if (errmsg == NULL) - { - if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - /* Act as if we had done a PC-relative branch, ala .+num. */ - char buf[20]; - const char * bufp = (const char *) buf; - - sprintf (buf, ".+%ld", (long) value); - errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type, - &value); - } - - if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) - { - /* This will happen for things like (s2-s1) where s2 and s1 - are labels. */ - /* Nothing further to be done. */ - } - else - errmsg = _("Not a pc-relative address."); - } - return errmsg; -} - -/* -- dis.c */ - -#define CGEN_PRINT_INSN epiphany_print_insn - -static int -epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - bfd_byte buf[CGEN_MAX_INSN_SIZE]; - int buflen; - int status; - - info->bytes_per_chunk = 2; - - /* Attempt to read the base part of the insn. */ - info->bytes_per_line = buflen = cd->base_insn_bitsize / 8; - status = (*info->read_memory_func) (pc, buf, buflen, info); - - /* Try again with the minimum part, if min < base. */ - if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) - { - info->bytes_per_line = buflen = cd->min_insn_bitsize / 8; - status = (*info->read_memory_func) (pc, buf, buflen, info); - } - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - return print_insn (cd, pc, info, buf, buflen); -} - - -static void -print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, value ? "-" : "+"); -} - -static void -print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_address (cd, dis_info, value, attrs, pc, length); -} - -static void -print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - unsigned long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *)dis_info; - - if (value & 0x800) - (*info->fprintf_func) (info->stream, "-"); - - value &= 0x7ff; - print_address (cd, dis_info, value, attrs, pc, length); -} - - -/* -- */ - diff --git a/binutils-2.24/cpu/fr30.cpu b/binutils-2.24/cpu/fr30.cpu deleted file mode 100644 index 6c8e8ce2..00000000 --- a/binutils-2.24/cpu/fr30.cpu +++ /dev/null @@ -1,1861 +0,0 @@ -; Fujitsu FR30 CPU description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -; define-arch must appear first - -(define-arch - (name fr30) ; name of cpu family - (comment "Fujitsu FR30") - (default-alignment forced) - (insn-lsb0? #f) - (machs fr30) - (isas fr30) -) - -(define-isa - (name fr30) - (base-insn-bitsize 16) - (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. - (liw-insns 1) ; The fr30 fetches 1 insn at a time. - (parallel-insns 1) ; The fr30 executes 1 insn at a time. -) - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name fr30bf) - (comment "Fujitsu FR30 base family") - (endian big) - (word-bitsize 32) -) - -(define-mach - (name fr30) - (comment "Generic FR30 cpu") - (cpu fr30bf) -) - -; Model descriptions. -; -(define-model - (name fr30-1) (comment "fr30-1") (attrs) - (mach fr30) - - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - (state - ; bit mask of h-gr registers loaded from memory by previous insn - (load-regs UINT) - ; bit mask of h-gr registers loaded from memory by current insn - (load-regs-pending UINT) - ) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - ((Ri INT -1) (Rj INT -1)) ; inputs - ((Ri INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-cti "Branch Unit" () - 1 1 ; issue done - () ; state - ((Ri INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - (unit u-load "Memory Load Unit" () - 1 1 ; issue done - () ; state - ((Rj INT -1) - ;(ld-mem AI) - ) ; inputs - ((Ri INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-store "Memory Store Unit" () - 1 1 ; issue done - () ; state - ((Ri INT -1) (Rj INT -1)) ; inputs - () ; ((st-mem AI)) ; outputs - () ; profile action (default) - ) - (unit u-ldm "LDM Memory Load Unit" () - 1 1 ; issue done - () ; state - ((reglist INT)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-stm "STM Memory Store Unit" () - 1 1 ; issue done - () ; state - ((reglist INT)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; The instruction fetch/execute cycle. -; -; This is how to fetch and decode an instruction. -; Leave it out for now - -; (define-extract (const SI 0)) - -; This is how to execute a decoded instruction. -; Leave it out for now - -; (define-execute (const SI 0)) - -; Instruction fields. -; -; Attributes: -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 - -(dnf f-op1 "1st 4 bits of opcode" () 0 4) -(dnf f-op2 "2nd 4 bits of opcode" () 4 4) -(dnf f-op3 "3rd 4 bits of opcode" () 8 4) -(dnf f-op4 "4th 4 bits of opcode" () 12 4) -(dnf f-op5 "5th bit of opcode" () 4 1) -(dnf f-cc "condition code" () 4 4) -(dnf f-ccc "coprocessor calc code" () 16 8) -(dnf f-Rj "register Rj" () 8 4) -(dnf f-Ri "register Ri" () 12 4) -(dnf f-Rs1 "register Rs" () 8 4) -(dnf f-Rs2 "register Rs" () 12 4) -(dnf f-Rjc "register Rj" () 24 4) -(dnf f-Ric "register Ri" () 28 4) -(dnf f-CRj "coprocessor register" () 24 4) -(dnf f-CRi "coprocessor register" () 28 4) -(dnf f-u4 "4 bit 0 extended" () 8 4) -(dnf f-u4c "4 bit 0 extended" () 12 4) -(df f-i4 "4 bit sign extended" () 8 4 INT #f #f) -(df f-m4 "4 bit minus extended" () 8 4 UINT - ((value pc) (and WI value (const #xf))) - ; ??? On a 64 bit host this doesn't get completely sign extended - ; if the value is recorded in a long, as it is during extraction. - ; Various fixes exist, pick one. - ((value pc) (or WI value (sll WI (const -1) (const 4)))) -) -(dnf f-u8 "8 bit unsigned" () 8 8) -(dnf f-i8 "8 bit unsigned" () 4 8) - -(dnf f-i20-4 "upper 4 bits of i20" () 8 4) -(dnf f-i20-16 "lower 16 bits of i20" () 16 16) -(dnmf f-i20 "20 bit unsigned" () UINT - (f-i20-4 f-i20-16) - (sequence () ; insert - (set (ifield f-i20-4) (srl (ifield f-i20) (const 16))) - (set (ifield f-i20-16) (and (ifield f-i20) (const #xffff))) - ) - (sequence () ; extract - (set (ifield f-i20) (or (sll (ifield f-i20-4) (const 16)) - (ifield f-i20-16))) - ) -) - -(dnf f-i32 "32 bit immediate" (SIGN-OPT) 16 32) - -(df f-udisp6 "6 bit unsigned offset" () 8 4 UINT - ((value pc) (srl UWI value (const 2))) - ((value pc) (sll UWI value (const 2))) -) -(df f-disp8 "8 bit signed offset" () 4 8 INT #f #f) -(df f-disp9 "9 bit signed offset" () 4 8 INT - ((value pc) (sra WI value (const 1))) - ((value pc) (sll WI value (const 1))) -) -(df f-disp10 "10 bit signed offset" () 4 8 INT - ((value pc) (sra WI value (const 2))) - ((value pc) (sll WI value (const 2))) -) -(df f-s10 "10 bit signed offset" () 8 8 INT - ((value pc) (sra WI value (const 2))) - ((value pc) (sll WI value (const 2))) -) -(df f-u10 "10 bit unsigned offset" () 8 8 UINT - ((value pc) (srl UWI value (const 2))) - ((value pc) (sll UWI value (const 2))) -) -(df f-rel9 "9 pc relative signed offset" (PCREL-ADDR) 8 8 INT - ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) - ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2)))) -) -(dnf f-dir8 "8 bit direct address" () 8 8) -(df f-dir9 "9 bit direct address" () 8 8 UINT - ((value pc) (srl UWI value (const 1))) - ((value pc) (sll UWI value (const 1))) -) -(df f-dir10 "10 bit direct address" () 8 8 UINT - ((value pc) (srl UWI value (const 2))) - ((value pc) (sll UWI value (const 2))) -) -(df f-rel12 "12 bit pc relative signed offset" (PCREL-ADDR) 5 11 INT - ((value pc) (sra WI (sub WI value (add WI pc (const 2))) (const 1))) - ((value pc) (add WI (sll WI value (const 1)) (add WI pc (const 2)))) -) - -(dnf f-reglist_hi_st "8 bit register mask for stm" () 8 8) -(dnf f-reglist_low_st "8 bit register mask for stm" () 8 8) -(dnf f-reglist_hi_ld "8 bit register mask for ldm" () 8 8) -(dnf f-reglist_low_ld "8 bit register mask for ldm" () 8 8) - -; Enums. - -; insn-op1: bits 0-3 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op1 "insn op1 enums" () OP1_ f-op1 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "A" "B" "C" "D" "E" "F") -) - -; insn-op2: bits 4-7 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op2 "insn op2 enums" () OP2_ f-op2 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "A" "B" "C" "D" "E" "F") -) - -; insn-op3: bits 8-11 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op3 "insn op3 enums" () OP3_ f-op3 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "A" "B" "C" "D" "E" "F") -) - -; insn-op4: bits 12-15 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op4 "insn op4 enums" () OP4_ f-op4 - ("0") -) - -; insn-op5: bit 4 (5th bit origin 0) -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5 - ("0" "1") -) - -; insn-cc: condition codes -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-cc "insn cc enums" () CC_ f-cc - ("ra" "no" "eq" "ne" "c" "nc" "n" "p" "v" "nv" "lt" "ge" "le" "gt" "ls" "hi") -) - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. - -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -(define-keyword - (name gr-names) - (enum-prefix H-GR-) - (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15) - (ac 13) (fp 14) (sp 15)) -) - -(define-hardware - (name h-gr) - (comment "general registers") - (attrs PROFILE CACHE-ADDR) - (type register WI (16)) - (indices extern-keyword gr-names) -) - -(define-keyword - (name cr-names) - (enum-prefix H-CR-) - (values (cr0 0) (cr1 1) (cr2 2) (cr3 3) - (cr4 4) (cr5 5) (cr6 6) (cr7 7) - (cr8 8) (cr9 9) (cr10 10) (cr11 11) - (cr12 12) (cr13 13) (cr14 14) (cr15 15)) -) - -(define-hardware - (name h-cr) - (comment "coprocessor registers") - (attrs) - (type register WI (16)) - (indices extern-keyword cr-names) -) - -(define-keyword - (name dr-names) - (enum-prefix H-DR-) - (values (tbr 0) (rp 1) (ssp 2) (usp 3) (mdh 4) (mdl 5)) -) - -(define-hardware - (name h-dr) - (comment "dedicated registers") - (type register WI (6)) - (indices extern-keyword dr-names) - (get (index) (c-call WI "@cpu@_h_dr_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_dr_set_handler" index newval)) -) - -(define-hardware - (name h-ps) - (comment "processor status") - (type register UWI) - (indices keyword "" ((ps 0))) - (get () (c-call UWI "@cpu@_h_ps_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_ps_set_handler" newval)) -) - -(dnh h-r13 "General Register 13 explicitly required" - () - (register WI) - (keyword "" ((r13 0))) - () () -) - -(dnh h-r14 "General Register 14 explicitly required" - () - (register WI) - (keyword "" ((r14 0))) - () () -) - -(dnh h-r15 "General Register 15 explicitly required" - () - (register WI) - (keyword "" ((r15 0))) - () () -) - -; These bits are actually part of the PS register but are accessed more -; often than the entire register, so define them directly. We can assemble -; the PS register from its components when necessary. - -(dsh h-nbit "negative bit" () (register BI)) -(dsh h-zbit "zero bit" () (register BI)) -(dsh h-vbit "overflow bit" () (register BI)) -(dsh h-cbit "carry bit" () (register BI)) -(dsh h-ibit "interrupt enable bit" () (register BI)) -(define-hardware - (name h-sbit) - (comment "stack bit") - (type register BI) - (get () (c-call BI "@cpu@_h_sbit_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_sbit_set_handler" newval)) -) -(dsh h-tbit "trace trap bit" () (register BI)) -(dsh h-d0bit "division 0 bit" () (register BI)) -(dsh h-d1bit "division 1 bit" () (register BI)) - -; These represent sub-registers within the program status register - -(define-hardware - (name h-ccr) - (comment "condition code bits") - (type register UQI) - (get () (c-call UQI "@cpu@_h_ccr_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_ccr_set_handler" newval)) -) -(define-hardware - (name h-scr) - (comment "system condition bits") - (type register UQI) - (get () (c-call UQI "@cpu@_h_scr_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_scr_set_handler" newval)) -) -(define-hardware - (name h-ilm) - (comment "interrupt level mask") - (type register UQI) - (get () (c-call UQI "@cpu@_h_ilm_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_ilm_set_handler" newval)) -) - -; Instruction Operands. -; These entries provide a layer between the assembler and the raw hardware -; description, and are used to refer to hardware elements in the semantic -; code. Usually there's a bit of over-specification, but in more complicated -; instruction sets there isn't. - -; FR30 specific operand attributes: - -(define-attr - (for operand) - (type boolean) - (name HASH-PREFIX) - (comment "immediates have an optional '#' prefix") -) - -; ??? Convention says this should be o-sr, but then the insn definitions -; should refer to o-sr which is clumsy. The "o-" could be implicit, but -; then it should be implicit for all the symbols here, but then there would -; be confusion between (f-)simm8 and (h-)simm8. -; So for now the rule is exactly as it appears here. - -(dnop Ri "destination register" () h-gr f-Ri) -(dnop Rj "source register" () h-gr f-Rj) -(dnop Ric "target register coproc insn" () h-gr f-Ric) -(dnop Rjc "source register coproc insn" () h-gr f-Rjc) -(dnop CRi "coprocessor register" () h-cr f-CRi) -(dnop CRj "coprocessor register" () h-cr f-CRj) -(dnop Rs1 "dedicated register" () h-dr f-Rs1) -(dnop Rs2 "dedicated register" () h-dr f-Rs2) -(dnop R13 "General Register 13" () h-r13 f-nil) -(dnop R14 "General Register 14" () h-r14 f-nil) -(dnop R15 "General Register 15" () h-r15 f-nil) -(dnop ps "Program Status register" () h-ps f-nil) -(dnop u4 "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4) -(dnop u4c "4 bit unsigned immediate" (HASH-PREFIX) h-uint f-u4c) -(dnop u8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-u8) -(dnop i8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-i8) -(dnop udisp6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-udisp6) -(dnop disp8 "8 bit signed immediate" (HASH-PREFIX) h-sint f-disp8) -(dnop disp9 "9 bit signed immediate" (HASH-PREFIX) h-sint f-disp9) -(dnop disp10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-disp10) - -(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) -(dnop u10 "10 bit unsigned immediate" (HASH-PREFIX) h-uint f-u10) -(dnop i32 "32 bit immediate" (HASH-PREFIX) h-uint f-i32) - -(define-operand - (name m4) - (comment "4 bit negative immediate") - (attrs HASH-PREFIX) - (type h-sint) - (index f-m4) - (handlers (print "m4")) -) - -(define-operand - (name i20) - (comment "20 bit immediate") - (attrs HASH-PREFIX) - (type h-uint) - (index f-i20) -) - -(dnop dir8 "8 bit direct address" () h-uint f-dir8) -(dnop dir9 "9 bit direct address" () h-uint f-dir9) -(dnop dir10 "10 bit direct address" () h-uint f-dir10) - -(dnop label9 "9 bit pc relative address" () h-iaddr f-rel9) -(dnop label12 "12 bit pc relative address" () h-iaddr f-rel12) - -(define-operand - (name reglist_low_ld) - (comment "8 bit low register mask for ldm") - (attrs) - (type h-uint) - (index f-reglist_low_ld) - (handlers (parse "low_register_list_ld") - (print "low_register_list_ld")) -) - -(define-operand - (name reglist_hi_ld) - (comment "8 bit high register mask for ldm") - (attrs) - (type h-uint) - (index f-reglist_hi_ld) - (handlers (parse "hi_register_list_ld") - (print "hi_register_list_ld")) -) - -(define-operand - (name reglist_low_st) - (comment "8 bit low register mask for stm") - (attrs) - (type h-uint) - (index f-reglist_low_st) - (handlers (parse "low_register_list_st") - (print "low_register_list_st")) -) - -(define-operand - (name reglist_hi_st) - (comment "8 bit high register mask for stm") - (attrs) - (type h-uint) - (index f-reglist_hi_st) - (handlers (parse "hi_register_list_st") - (print "hi_register_list_st")) -) - -(dnop cc "condition codes" () h-uint f-cc) -(dnop ccc "coprocessor calc" (HASH-PREFIX) h-uint f-ccc) - -(dnop nbit "negative bit" (SEM-ONLY) h-nbit f-nil) -(dnop vbit "overflow bit" (SEM-ONLY) h-vbit f-nil) -(dnop zbit "zero bit" (SEM-ONLY) h-zbit f-nil) -(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil) -(dnop ibit "interrupt bit" (SEM-ONLY) h-ibit f-nil) -(dnop sbit "stack bit" (SEM-ONLY) h-sbit f-nil) -(dnop tbit "trace trap bit" (SEM-ONLY) h-tbit f-nil) -(dnop d0bit "division 0 bit" (SEM-ONLY) h-d0bit f-nil) -(dnop d1bit "division 1 bit" (SEM-ONLY) h-d1bit f-nil) - -(dnop ccr "condition code bits" (SEM-ONLY) h-ccr f-nil) -(dnop scr "system condition bits" (SEM-ONLY) h-scr f-nil) -(dnop ilm "interrupt level mask" (SEM-ONLY) h-ilm f-nil) - -; Instruction definitions. -; -; Notes: -; - dni is short for "define-normal-instruction" - -; FR30 specific insn attributes: - -(define-attr - (for insn) - (type boolean) - (name NOT-IN-DELAY-SLOT) - (comment "insn can't go in delay slot") -) - -; Sets zbit and nbit based on the value of x -; -(define-pmacro (set-z-and-n x) - (sequence () - (set zbit (eq x (const 0))) - (set nbit (lt x (const 0)))) -) - -; Binary integer instruction which sets status bits -; -(define-pmacro (binary-int-op name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence () - (set vbit ((.sym op -oflag) arg2 arg1 (const 0))) - (set cbit ((.sym op -cflag) arg2 arg1 (const 0))) - (set arg2 (op arg2 arg1)) - (set-z-and-n arg2)) - () - ) -) - -; Binary integer instruction which does *not* set status bits -; -(define-pmacro (binary-int-op-n name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 (op arg2 arg1)) - () - ) -) - -; Binary integer instruction with carry which sets status bits -; -(define-pmacro (binary-int-op-c name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI tmp)) - (set tmp ((.sym op c) arg2 arg1 cbit)) - (set vbit ((.sym op -oflag) arg2 arg1 cbit)) - (set cbit ((.sym op -cflag) arg2 arg1 cbit)) - (set arg2 tmp) - (set-z-and-n arg2)) - () - ) -) - -(binary-int-op add add "reg/reg" OP1_A OP2_6 add Rj Ri) -(binary-int-op addi add "immed/reg" OP1_A OP2_4 add u4 Ri) -(binary-int-op add2 add2 "immed/reg" OP1_A OP2_5 add m4 Ri) -(binary-int-op-c addc addc "reg/reg" OP1_A OP2_7 add Rj Ri) -(binary-int-op-n addn addn "reg/reg" OP1_A OP2_2 add Rj Ri) -(binary-int-op-n addni addn "immed/reg" OP1_A OP2_0 add u4 Ri) -(binary-int-op-n addn2 addn2 "immed/reg" OP1_A OP2_1 add m4 Ri) - -(binary-int-op sub sub "reg/reg" OP1_A OP2_C sub Rj Ri) -(binary-int-op-c subc subc "reg/reg" OP1_A OP2_D sub Rj Ri) -(binary-int-op-n subn subn "reg/reg" OP1_A OP2_E sub Rj Ri) - -; Integer compare instruction -; -(define-pmacro (int-cmp name insn comment opc1 opc2 arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI tmp1)) - (set vbit (sub-oflag arg2 arg1 (const 0))) - (set cbit (sub-cflag arg2 arg1 (const 0))) - (set tmp1 (sub arg2 arg1)) - (set-z-and-n tmp1) - ) - () - ) -) - -(int-cmp cmp cmp "reg/reg" OP1_A OP2_A Rj Ri) -(int-cmp cmpi cmp "immed/reg" OP1_A OP2_8 u4 Ri) -(int-cmp cmp2 cmp2 "immed/reg" OP1_A OP2_9 m4 Ri) - -; Binary logical instruction -; -(define-pmacro (binary-logical-op name insn comment opc1 opc2 op arg1 arg2) - (dni name - (.str insn " " comment) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence () - (set arg2 (op arg2 arg1)) - (set-z-and-n arg2)) - () - ) -) - -(binary-logical-op and and "reg/reg" OP1_8 OP2_2 and Rj Ri) -(binary-logical-op or or "reg/reg" OP1_9 OP2_2 or Rj Ri) -(binary-logical-op eor eor "reg/reg" OP1_9 OP2_A xor Rj Ri) - -(define-pmacro (les-units model) ; les: load-exec-store - (model (unit u-exec) (unit u-load) (unit u-store)) -) - -; Binary logical instruction to memory -; -(define-pmacro (binary-logical-op-m name insn comment opc1 opc2 mode op arg1 arg2) - (dni name - (.str insn " " comment) - (NOT-IN-DELAY-SLOT) - (.str insn " $" arg1 ",@$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((mode tmp)) - (set mode tmp (op mode (mem mode arg2) arg1)) - (set-z-and-n tmp) - (set mode (mem mode arg2) tmp)) - ((les-units fr30-1)) - ) -) - -(binary-logical-op-m andm and "reg/mem" OP1_8 OP2_4 WI and Rj Ri) -(binary-logical-op-m andh andh "reg/mem" OP1_8 OP2_5 HI and Rj Ri) -(binary-logical-op-m andb andb "reg/mem" OP1_8 OP2_6 QI and Rj Ri) -(binary-logical-op-m orm or "reg/mem" OP1_9 OP2_4 WI or Rj Ri) -(binary-logical-op-m orh orh "reg/mem" OP1_9 OP2_5 HI or Rj Ri) -(binary-logical-op-m orb orb "reg/mem" OP1_9 OP2_6 QI or Rj Ri) -(binary-logical-op-m eorm eor "reg/mem" OP1_9 OP2_C WI xor Rj Ri) -(binary-logical-op-m eorh eorh "reg/mem" OP1_9 OP2_D HI xor Rj Ri) -(binary-logical-op-m eorb eorb "reg/mem" OP1_9 OP2_E QI xor Rj Ri) - -; Binary logical instruction to low half of byte in memory -; -(dni bandl - "bandl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "bandl $u4,@$Ri" - (+ OP1_8 OP2_0 u4 Ri) - (set QI (mem QI Ri) - (and QI - (or QI u4 (const #xf0)) - (mem QI Ri))) - ((les-units fr30-1)) -) - -(dni borl - "borl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "borl $u4,@$Ri" - (+ OP1_9 OP2_0 u4 Ri) - (set QI (mem QI Ri) (or QI u4 (mem QI Ri))) - ((les-units fr30-1)) -) - -(dni beorl - "beorl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "beorl $u4,@$Ri" - (+ OP1_9 OP2_8 u4 Ri) - (set QI (mem QI Ri) (xor QI u4 (mem QI Ri))) - ((les-units fr30-1)) -) - -; Binary logical instruction to high half of byte in memory -; -(dni bandh - "bandh #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "bandh $u4,@$Ri" - (+ OP1_8 OP2_1 u4 Ri) - (set QI (mem QI Ri) - (and QI - (or QI (sll QI u4 (const 4)) (const #x0f)) - (mem QI Ri))) - ((les-units fr30-1)) -) - -(define-pmacro (binary-or-op-mh name insn opc1 opc2 op arg1 arg2) - (dni name - (.str name " #" arg1 ",@" args) - (NOT-IN-DELAY-SLOT) - (.str name " $" arg1 ",@$" arg2) - (+ opc1 opc2 arg1 arg2) - (set QI (mem QI arg2) - (insn QI - (sll QI arg1 (const 4)) - (mem QI arg2))) - ((les-units fr30-1)) - ) -) - -(binary-or-op-mh borh or OP1_9 OP2_1 or u4 Ri) -(binary-or-op-mh beorh xor OP1_9 OP2_9 xor u4 Ri) - -(dni btstl - "btstl #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "btstl $u4,@$Ri" - (+ OP1_8 OP2_8 u4 Ri) - (sequence ((QI tmp)) - (set tmp (and QI u4 (mem QI Ri))) - (set zbit (eq tmp (const 0))) - (set nbit (const 0))) - ((fr30-1 (unit u-load) (unit u-exec (cycles 2)))) -) - -(dni btsth - "btsth #u4,@Ri" - (NOT-IN-DELAY-SLOT) - "btsth $u4,@$Ri" - (+ OP1_8 OP2_9 u4 Ri) - (sequence ((QI tmp)) - (set tmp (and QI (sll QI u4 (const 4)) (mem QI Ri))) - (set zbit (eq tmp (const 0))) - (set nbit (lt tmp (const 0)))) - ((fr30-1 (unit u-load) (unit u-exec (cycles 2)))) -) - -(dni mul - "mul Rj,Ri" - (NOT-IN-DELAY-SLOT) - "mul $Rj,$Ri" - (+ OP1_A OP2_F Rj Ri) - (sequence ((DI tmp)) - (set tmp (mul DI (ext DI Rj) (ext DI Ri))) - (set (reg h-dr 5) (trunc WI tmp)) - (set (reg h-dr 4) (trunc WI (srl tmp (const 32)))) - (set nbit (lt (reg h-dr 5) (const 0))) - (set zbit (eq tmp (const DI 0))) - (set vbit (orif - (gt tmp (const DI #x7fffffff)) - (lt tmp (neg (const DI #x80000000)))))) - ((fr30-1 (unit u-exec (cycles 5)))) -) - -(dni mulu - "mulu Rj,Ri" - (NOT-IN-DELAY-SLOT) - "mulu $Rj,$Ri" - (+ OP1_A OP2_B Rj Ri) - (sequence ((DI tmp)) - (set tmp (mul DI (zext DI Rj) (zext DI Ri))) - (set (reg h-dr 5) (trunc WI tmp)) - (set (reg h-dr 4) (trunc WI (srl tmp (const 32)))) - (set nbit (lt (reg h-dr 4) (const 0))) - (set zbit (eq (reg h-dr 5) (const 0))) - (set vbit (ne (reg h-dr 4) (const 0)))) - ((fr30-1 (unit u-exec (cycles 5)))) -) - -(dni mulh - "mulh Rj,Ri" - (NOT-IN-DELAY-SLOT) - "mulh $Rj,$Ri" - (+ OP1_B OP2_F Rj Ri) - (sequence () - (set (reg h-dr 5) (mul (trunc HI Rj) (trunc HI Ri))) - (set nbit (lt (reg h-dr 5) (const 0))) - (set zbit (ge (reg h-dr 5) (const 0)))) - ((fr30-1 (unit u-exec (cycles 3)))) -) - -(dni muluh - "muluh Rj,Ri" - (NOT-IN-DELAY-SLOT) - "muluh $Rj,$Ri" - (+ OP1_B OP2_B Rj Ri) - (sequence () - (set (reg h-dr 5) (mul (and Rj (const #xffff)) - (and Ri (const #xffff)))) - (set nbit (lt (reg h-dr 5) (const 0))) - (set zbit (ge (reg h-dr 5) (const 0)))) - ((fr30-1 (unit u-exec (cycles 3)))) -) - -(dni div0s - "div0s Ri" - () - "div0s $Ri" - (+ OP1_9 OP2_7 OP3_4 Ri) - (sequence () - (set d0bit (lt (reg h-dr 5) (const 0))) - (set d1bit (xor d0bit (lt Ri (const 0)))) - (if (ne d0bit (const 0)) - (set (reg h-dr 4) (const #xffffffff)) - (set (reg h-dr 4) (const 0)))) - () -) - -(dni div0u - "div0u Ri" - () - "div0u $Ri" - (+ OP1_9 OP2_7 OP3_5 Ri) - (sequence () - (set d0bit (const 0)) - (set d1bit (const 0)) - (set (reg h-dr 4) (const 0))) - () -) - -(dni div1 - "div1 Ri" - () - "div1 $Ri" - (+ OP1_9 OP2_7 OP3_6 Ri) - (sequence ((WI tmp)) - (set (reg h-dr 4) (sll (reg h-dr 4) (const 1))) - (if (lt (reg h-dr 5) (const 0)) - (set (reg h-dr 4) (add (reg h-dr 4) (const 1)))) - (set (reg h-dr 5) (sll (reg h-dr 5) (const 1))) - (if (eq d1bit (const 1)) - (sequence () - (set tmp (add (reg h-dr 4) Ri)) - (set cbit (add-cflag (reg h-dr 4) Ri (const 0)))) - (sequence () - (set tmp (sub (reg h-dr 4) Ri)) - (set cbit (sub-cflag (reg h-dr 4) Ri (const 0))))) - (if (not (xor (xor d0bit d1bit) cbit)) - (sequence () - (set (reg h-dr 4) tmp) - (set (reg h-dr 5) (or (reg h-dr 5) (const 1))))) - (set zbit (eq (reg h-dr 4) (const 0)))) - () -) - -(dni div2 - "div2 Ri" - () - "div2 $Ri" - (+ OP1_9 OP2_7 OP3_7 Ri) - (sequence ((WI tmp)) - (if (eq d1bit (const 1)) - (sequence () - (set tmp (add (reg h-dr 4) Ri)) - (set cbit (add-cflag (reg h-dr 4) Ri (const 0)))) - (sequence () - (set tmp (sub (reg h-dr 4) Ri)) - (set cbit (sub-cflag (reg h-dr 4) Ri (const 0))))) - (if (eq tmp (const 0)) - (sequence () - (set zbit (const 1)) - (set (reg h-dr 4) (const 0))) - (set zbit (const 0)))) - () -) - -(dni div3 - "div3" - () - "div3" - (+ OP1_9 OP2_F OP3_6 OP4_0) - (if (eq zbit (const 1)) - (set (reg h-dr 5) (add (reg h-dr 5) (const 1)))) - () -) - -(dni div4s - "div4s" - () - "div4s" - (+ OP1_9 OP2_F OP3_7 OP4_0) - (if (eq d1bit (const 1)) - (set (reg h-dr 5) (neg (reg h-dr 5)))) - () -) - -(define-pmacro (leftshift-op name insn opc1 opc2 arg1 arg2 shift-expr) - (dni name - (.str insn " " arg1 "," arg2) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI shift)) - (set shift shift-expr) - (if (ne shift (const 0)) - (sequence () - (set cbit (ne (and arg2 - (sll (const 1) - (sub (const 32) shift))) - (const 0))) - (set arg2 (sll arg2 shift))) - (set cbit (const 0))) - (set nbit (lt arg2 (const 0))) - (set zbit (eq arg2 (const 0)))) - () - ) -) -(leftshift-op lsl lsl OP1_B OP2_6 Rj Ri (and Rj (const #x1f))) -(leftshift-op lsli lsl OP1_B OP2_4 u4 Ri u4) -(leftshift-op lsl2 lsl2 OP1_B OP2_5 u4 Ri (add u4 (const #x10))) - -(define-pmacro (rightshift-op name insn opc1 opc2 op arg1 arg2 shift-expr) - (dni name - (.str insn " " arg1 "," arg2) - () - (.str insn " $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (sequence ((WI shift)) - (set shift shift-expr) - (if (ne shift (const 0)) - (sequence () - (set cbit (ne (and arg2 - (sll (const 1) - (sub shift (const 1)))) - (const 0))) - (set arg2 (op arg2 shift))) - (set cbit (const 0))) - (set nbit (lt arg2 (const 0))) - (set zbit (eq arg2 (const 0)))) - () - ) -) -(rightshift-op lsr lsr OP1_B OP2_2 srl Rj Ri (and Rj (const #x1f))) -(rightshift-op lsri lsr OP1_B OP2_0 srl u4 Ri u4) -(rightshift-op lsr2 lsr2 OP1_B OP2_1 srl u4 Ri (add u4 (const #x10))) -(rightshift-op asr asr OP1_B OP2_A sra Rj Ri (and Rj (const #x1f))) -(rightshift-op asri asr OP1_B OP2_8 sra u4 Ri u4) -(rightshift-op asr2 asr2 OP1_B OP2_9 sra u4 Ri (add u4 (const #x10))) - -(dni ldi8 - "load 8 bit unsigned immediate" - () - "ldi:8 $i8,$Ri" - (+ OP1_C i8 Ri) - (set Ri i8) - () -) - -; Typing ldi:8 in in emacs is a pain. -(dnmi ldi8m "ldi:8 without the colon" - (NO-DIS) - "ldi8 $i8,$Ri" - (emit ldi8 i8 Ri) -) - -(dni ldi20 - "load 20 bit unsigned immediate" - (NOT-IN-DELAY-SLOT) - "ldi:20 $i20,$Ri" - (+ OP1_9 OP2_B Ri i20) - (set Ri i20) - ((fr30-1 (unit u-exec (cycles 2)))) -) - -; Typing ldi:20 in in emacs is a pain. -(dnmi ldi20m "ldi:20 without the colon" - (NO-DIS) - "ldi20 $i20,$Ri" - (emit ldi20 i20 Ri) -) - -(dni ldi32 - "load 32 bit immediate" - (NOT-IN-DELAY-SLOT) - "ldi:32 $i32,$Ri" - (+ OP1_9 OP2_F OP3_8 Ri i32) - (set Ri i32) - ((fr30-1 (unit u-exec (cycles 3)))) -) - -; Typing ldi:32 in in emacs is a pain. -(dnmi ldi32m "ldi:32 without the colon" - (NO-DIS) - "ldi32 $i32,$Ri" - (emit ldi32 i32 Ri) -) - -(define-pmacro (basic-ld name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str name " @" arg1 "," arg2) - () - (.str name " @$" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 (mem mode arg1)) - ((fr30-1 (unit u-load))) - ) -) - -(basic-ld ld ld OP1_0 OP2_4 WI Rj Ri) -(basic-ld lduh lduh OP1_0 OP2_5 UHI Rj Ri) -(basic-ld ldub ldub OP1_0 OP2_6 UQI Rj Ri) - -(define-pmacro (r13base-ld name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str insn " @(R13," arg1 ")," arg2) - () - (.str insn " @($R13,$" arg1 "),$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 (mem mode (add arg1 (reg h-gr 13)))) - ((fr30-1 (unit u-load))) - ) -) - -(r13base-ld ldr13 ld OP1_0 OP2_0 WI Rj Ri) -(r13base-ld ldr13uh lduh OP1_0 OP2_1 UHI Rj Ri) -(r13base-ld ldr13ub ldub OP1_0 OP2_2 UQI Rj Ri) - -(define-pmacro (r14base-ld name insn opc1 mode arg1 arg2) - (dni name - (.str insn " @(R14," arg1 ")," arg2) - () - (.str insn " @($R14,$" arg1 "),$" arg2) - (+ opc1 arg1 arg2) - (set arg2 (mem mode (add arg1 (reg h-gr 14)))) - ((fr30-1 (unit u-load))) - ) -) - -(r14base-ld ldr14 ld OP1_2 WI disp10 Ri) -(r14base-ld ldr14uh lduh OP1_4 UHI disp9 Ri) -(r14base-ld ldr14ub ldub OP1_6 UQI disp8 Ri) - -(dni ldr15 - "ld @(R15,udisp6),Ri mem/reg" - () - "ld @($R15,$udisp6),$Ri" - (+ OP1_0 OP2_3 udisp6 Ri) - (set Ri (mem WI (add udisp6 (reg h-gr 15)))) - ((fr30-1 (unit u-load))) -) - -(dni ldr15gr - "ld @R15+,Ri" - () - "ld @$R15+,$Ri" - (+ OP1_0 OP2_7 OP3_0 Ri) - (sequence () - (set Ri (mem WI (reg h-gr 15))) - (if (ne (ifield f-Ri) (const 15)) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - ((fr30-1 (unit u-load))) -) - -; This insn loads a value from where r15 points into the target register and -; then increments r15. If the target register is also r15, then the post -; increment is not performed. -; -(dni ldr15dr - "ld @R15+,Rs2" - () - "ld @$R15+,$Rs2" - (+ OP1_0 OP2_7 OP3_8 Rs2) -; This seems more straight forward, but doesn't work due to a problem in -; cgen. We're trying to not increment r15 if it is the target register. -; (sequence () -; (set Rs2 (mem WI (reg h-gr 15))) -; (if (not (or (and (eq (ifield f-Rs2) (const 2)) -; (eq sbit (const 0))) -; (and (eq (ifield f-Rs2) (const 3)) -; (eq sbit (const 1))))) -; (set (reg h-gr 15) (add (reg h-gr 15) (const 4))) -; ) -; ) - (sequence ((WI tmp)) - (set tmp (mem WI (reg h-gr 15))) ; save in case target is r15 - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))) - (set Rs2 tmp)) - ((fr30-1 (unit u-load))) -) - -(dni ldr15ps - "ld @R15+,ps mem/reg" - (NOT-IN-DELAY-SLOT) - "ld @$R15+,$ps" - (+ OP1_0 OP2_7 OP3_9 OP4_0) - (sequence () - (set ps (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))) - ((fr30-1 (unit u-load))) -) - -(define-pmacro (basic-st name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str name " " arg1 ",@" arg2) - () - (.str name " $" arg1 ",@$" arg2) - (+ opc1 opc2 arg1 arg2) - (set (mem mode arg2) arg1) - ((fr30-1 (unit u-store))) - ) -) - -(basic-st st st OP1_1 OP2_4 WI Ri Rj) -(basic-st sth sth OP1_1 OP2_5 HI Ri Rj) -(basic-st stb stb OP1_1 OP2_6 QI Ri Rj) - -(define-pmacro (r13base-st name insn opc1 opc2 mode arg1 arg2) - (dni name - (.str insn " " arg1 ",@(R13," arg2 ")") - () - (.str insn " $" arg1 ",@($R13,$" arg2 ")") - (+ opc1 opc2 arg1 arg2) - (set (mem mode (add arg2 (reg h-gr 13))) arg1) - ((fr30-1 (unit u-store))) - ) -) - -(r13base-st str13 st OP1_1 OP2_0 WI Ri Rj) -(r13base-st str13h sth OP1_1 OP2_1 HI Ri Rj) -(r13base-st str13b stb OP1_1 OP2_2 QI Ri Rj) - -(define-pmacro (r14base-st name insn opc1 mode arg1 arg2) - (dni name - (.str insn " " arg1 ",@(R14," arg2 ")") - () - (.str insn " $" arg1 ",@($R14,$" arg2 ")") - (+ opc1 arg1 arg2) - (set (mem mode (add arg2 (reg h-gr 14))) arg1) - ((fr30-1 (unit u-store))) - ) -) - -(r14base-st str14 st OP1_3 WI Ri disp10) -(r14base-st str14h sth OP1_5 HI Ri disp9) -(r14base-st str14b stb OP1_7 QI Ri disp8) - -(dni str15 - "st Ri,@(R15,udisp6) reg/mem" - () - "st $Ri,@($R15,$udisp6)" - (+ OP1_1 OP2_3 udisp6 Ri) - (set (mem WI (add (reg h-gr 15) udisp6)) Ri) - ((fr30-1 (unit u-store))) -) - -; These store insns predecrement r15 and then store the contents of the source -; register where r15 then points. If the source register is also r15, then the -; original value of r15 is stored. -; -(dni str15gr - "st Ri,@-R15 reg/mem" - () - "st $Ri,@-$R15" - (+ OP1_1 OP2_7 OP3_0 Ri) - (sequence ((WI tmp)) - (set tmp Ri) ; save in case it's r15 - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) tmp)) - ((fr30-1 (unit u-store))) -) - -(dni str15dr - "st Rs,@-R15 reg/mem" - () - "st $Rs2,@-$R15" - (+ OP1_1 OP2_7 OP3_8 Rs2) - (sequence ((WI tmp)) - (set tmp Rs2) ; save in case it's r15 - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) tmp)) - ((fr30-1 (unit u-store))) -) - -(dni str15ps - "st ps,@-R15 reg/mem" - () - "st $ps,@-$R15" - (+ OP1_1 OP2_7 OP3_9 OP4_0) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) ps)) - ((fr30-1 (unit u-store))) -) - -(define-pmacro (mov2gr name opc1 opc2 arg1 arg2) - (dni name - (.str "mov " arg1 "," arg2) - () - (.str "mov $" arg1 ",$" arg2) - (+ opc1 opc2 arg1 arg2) - (set arg2 arg1) - () - ) -) - -(mov2gr mov OP1_8 OP2_B Rj Ri) -(mov2gr movdr OP1_B OP2_7 Rs1 Ri) - -(dni movps - "mov ps,Ri reg/reg" - () - "mov $ps,$Ri" - (+ OP1_1 OP2_7 OP3_1 Ri) - (set Ri ps) - () -) - -(dni mov2dr - "mov Ri,Rs reg/reg" - () - "mov $Ri,$Rs1" - (+ OP1_B OP2_3 Rs1 Ri) - (set Rs1 Ri) - () -) - -(dni mov2ps - "mov Ri,ps reg/reg" - () - "mov $Ri,$ps" - (+ OP1_0 OP2_7 OP3_1 Ri) - (set ps Ri) - () -) - -(dni jmp - "jmp with no delay slot" - (NOT-IN-DELAY-SLOT) - "jmp @$Ri" - (+ OP1_9 OP2_7 OP3_0 Ri) - (set pc Ri) - ((fr30-1 (unit u-cti))) -) - -(dni jmpd "jmp with delay slot" - (NOT-IN-DELAY-SLOT) - "jmp:d @$Ri" - (+ OP1_9 OP2_F OP3_0 Ri) - (delay (const 1) - (set pc Ri)) - ((fr30-1 (unit u-cti))) -) - -; These versions which use registers must appear before the other -; versions which use relative addresses due to a problem in cgen -; - DB. -(dni callr - "call @Ri" - (NOT-IN-DELAY-SLOT) - "call @$Ri" - (+ OP1_9 OP2_7 OP3_1 Ri) - (sequence () - (set (reg h-dr 1) (add pc (const 2))) - (set pc Ri)) - ((fr30-1 (unit u-cti))) -) -(dni callrd - "call:d @Ri" - (NOT-IN-DELAY-SLOT) - "call:d @$Ri" - (+ OP1_9 OP2_F OP3_1 Ri) - (delay (const 1) - (sequence () - (set (reg h-dr 1) (add pc (const 4))) - (set pc Ri))) - ((fr30-1 (unit u-cti))) -) -; end of reordered insns - -(dni call - "call relative to pc" - (NOT-IN-DELAY-SLOT) - "call $label12" - (+ OP1_D OP5_0 label12) - (sequence () - (set (reg h-dr 1) (add pc (const 2))) - (set pc label12)) - ((fr30-1 (unit u-cti))) -) -(dni calld - "call relative to pc" - (NOT-IN-DELAY-SLOT) - "call:d $label12" - (+ OP1_D OP5_1 label12) - (delay (const 1) - (sequence () - (set (reg h-dr 1) (add pc (const 4))) - (set pc label12))) - ((fr30-1 (unit u-cti))) -) - -(dni ret - "return from subroutine" - (NOT-IN-DELAY-SLOT) - "ret" - (+ OP1_9 OP2_7 OP3_2 OP4_0) - (set pc (reg h-dr 1)) - ((fr30-1 (unit u-cti))) -) - -(dni ret:d - "return from subroutine with delay slot" - (NOT-IN-DELAY-SLOT) - "ret:d" - (+ OP1_9 OP2_F OP3_2 OP4_0) - (delay (const 1) - (set pc (reg h-dr 1))) - ((fr30-1 (unit u-cti))) -) - -(dni int - "interrupt" - (NOT-IN-DELAY-SLOT) - "int $u8" - (+ OP1_1 OP2_F u8) - (sequence () - ; This is defered to fr30_int because for the breakpoint case - ; we want to change as little of the machine state as possible. - ; Push PS onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) ps) - ; Push the return address onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2))) - ; Set status bits - ;(set ibit (const 0)) - ;(set sbit (const 0)) - - ; We still should indicate what is modified by this insn. - (clobber (reg h-dr 2)) - (clobber ibit) - (clobber sbit) - ; ??? (clobber memory)? - - ; fr30_int handles operating vs user mode - (set WI pc (c-call WI "fr30_int" pc u8)) - ) - ; This is more properly a cti, but branch stall calculation is different. - ((fr30-1 (unit u-exec (cycles 6)))) -) - -(dni inte - "interrupt for emulator" - (NOT-IN-DELAY-SLOT) - "inte" - (+ OP1_9 OP2_F OP3_3 OP4_0) - (sequence () - ; This is defered to fr30_inte because for the breakpoint case - ; we want to change as little of the machine state as possible. - ; Push PS onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) ps) - ; Push the return address onto the system stack - ;(set (reg h-dr 2) (sub (reg h-dr 2) (const 4))) - ;(set UWI (mem UWI (reg h-dr 2)) (add pc (const 2))) - ; Set status bits - ;(set ibit (const 0)) - ;(set ilm (const 4)) - - ; We still should indicate what is modified by this insn. - (clobber (reg h-dr 2)) - (clobber ibit) - (clobber ilm) - ; ??? (clobber memory)? - - ; fr30_int handles operating vs user mode - (set WI pc (c-call WI "fr30_inte" pc)) - ) - ; This is more properly a cti, but branch stall calculation is different. - ((fr30-1 (unit u-exec (cycles 6)))) -) - -(dni reti - "return from interrupt" - (NOT-IN-DELAY-SLOT) - "reti" - (+ OP1_9 OP2_7 OP3_3 OP4_0) - (if (eq sbit (const 0)) - (sequence () - ; Pop the return address from the system stack - (set UWI pc (mem UWI (reg h-dr 2))) - (set (reg h-dr 2) (add (reg h-dr 2) (const 4))) - ; Pop PS from the system stack - (set UWI ps (mem UWI (reg h-dr 2))) - (set (reg h-dr 2) (add (reg h-dr 2) (const 4))) - ) - (sequence () - ; Pop the return address from the user stack - (set UWI pc (mem UWI (reg h-dr 3))) - (set (reg h-dr 3) (add (reg h-dr 3) (const 4))) - ; Pop PS from the user stack - (set UWI ps (mem UWI (reg h-dr 3))) - (set (reg h-dr 3) (add (reg h-dr 3) (const 4))) - ) - ) - ; This is more properly a cti, but branch stall calculation is different. - ((fr30-1 (unit u-exec (cycles 4)))) -) - -; Conditional branches with and without delay slots -; -(define-pmacro (cond-branch cc condition) - (begin - (dni (.sym b cc d) - (.str (.sym b cc :d) " label9") - (NOT-IN-DELAY-SLOT) - (.str (.sym b cc :d) " $label9") - (+ OP1_F (.sym CC_ cc) label9) - (delay (const 1) - (if condition (set pc label9))) - ((fr30-1 (unit u-cti))) - ) - (dni (.sym b cc) - (.str (.sym b cc) " label9") - (NOT-IN-DELAY-SLOT) - (.str (.sym b cc) " $label9") - (+ OP1_E (.sym CC_ cc) label9) - (if condition (set pc label9)) - ((fr30-1 (unit u-cti))) - ) - ) -) - -(cond-branch ra (const BI 1)) -(cond-branch no (const BI 0)) -(cond-branch eq zbit) -(cond-branch ne (not zbit)) -(cond-branch c cbit) -(cond-branch nc (not cbit)) -(cond-branch n nbit) -(cond-branch p (not nbit)) -(cond-branch v vbit) -(cond-branch nv (not vbit)) -(cond-branch lt (xor vbit nbit)) -(cond-branch ge (not (xor vbit nbit))) -(cond-branch le (or (xor vbit nbit) zbit)) -(cond-branch gt (not (or (xor vbit nbit) zbit))) -(cond-branch ls (or cbit zbit)) -(cond-branch hi (not (or cbit zbit))) - -(define-pmacro (dir2r13 name insn opc1 opc2 mode arg1) - (dni name - (.str insn " @" arg1 ",R13") - () - (.str insn " @$" arg1 ",$R13") - (+ opc1 opc2 arg1) - (set (reg h-gr 13) (mem mode arg1)) - ((fr30-1 (unit u-load))) - ) -) - -(define-pmacro (dir2r13-postinc name insn opc1 opc2 mode arg1 incr) - (dni name - (.str insn " @" arg1 ",@R13+") - (NOT-IN-DELAY-SLOT) - (.str insn " @$" arg1 ",@$R13+") - (+ opc1 opc2 arg1) - (sequence () - (set (mem mode (reg h-gr 13)) (mem mode arg1)) - (set (reg h-gr 13) (add (reg h-gr 13) incr))) - ((fr30-1 (unit u-load) (unit u-store))) - ) -) - -(define-pmacro (r132dir name insn opc1 opc2 mode arg1) - (dni name - (.str insn " R13,@" arg1) - () - (.str insn " $R13,@$" arg1) - (+ opc1 opc2 arg1) - (set (mem mode arg1) (reg h-gr 13)) - ((fr30-1 (unit u-store))) - ) -) - -(define-pmacro (r13-postinc2dir name insn opc1 opc2 mode arg1 incr) - (dni name - (.str insn " @R13+,@" arg1) - (NOT-IN-DELAY-SLOT) - (.str insn " @$R13+,@$" arg1) - (+ opc1 opc2 arg1) - (sequence () - (set (mem mode arg1) (mem mode (reg h-gr 13))) - (set (reg h-gr 13) (add (reg h-gr 13) incr))) - ((fr30-1 (unit u-load) (unit u-store))) - ) -) - -; These versions which move from reg to mem must appear before the other -; versions which use immediate addresses due to a problem in cgen -; - DB. -(r132dir dmovr13 dmov OP1_1 OP2_8 WI dir10) -(r132dir dmovr13h dmovh OP1_1 OP2_9 HI dir9) -(r132dir dmovr13b dmovb OP1_1 OP2_A QI dir8) - -(r13-postinc2dir dmovr13pi dmov OP1_1 OP2_C WI dir10 (const 4)) -(r13-postinc2dir dmovr13pih dmovh OP1_1 OP2_D HI dir9 (const 2)) -(r13-postinc2dir dmovr13pib dmovb OP1_1 OP2_E QI dir8 (const 1)) - -(dni dmovr15pi - "dmov @R15+,@dir10" - (NOT-IN-DELAY-SLOT) - "dmov @$R15+,@$dir10" - (+ OP1_1 OP2_B dir10) - (sequence () - (set (mem WI dir10) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4)))) - ((fr30-1 (unit u-load) (unit u-store))) -) -; End of reordered insns. - -(dir2r13 dmov2r13 dmov OP1_0 OP2_8 WI dir10) -(dir2r13 dmov2r13h dmovh OP1_0 OP2_9 HI dir9) -(dir2r13 dmov2r13b dmovb OP1_0 OP2_A QI dir8) - -(dir2r13-postinc dmov2r13pi dmov OP1_0 OP2_C WI dir10 (const 4)) -(dir2r13-postinc dmov2r13pih dmovh OP1_0 OP2_D HI dir9 (const 2)) -(dir2r13-postinc dmov2r13pib dmovb OP1_0 OP2_E QI dir8 (const 1)) - -(dni dmov2r15pd - "dmov @dir10,@-R15" - (NOT-IN-DELAY-SLOT) - "dmov @$dir10,@-$R15" - (+ OP1_0 OP2_B dir10) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (mem WI dir10))) - ((fr30-1 (unit u-load) (unit u-store))) -) - -; Leave these insns as stubs for now, except for the increment of $Ri -; -(dni ldres - "ldres @Ri+,#u4" - () - "ldres @$Ri+,$u4" - (+ OP1_B OP2_C u4 Ri) - (set Ri (add Ri (const 4))) - () -) - -(dni stres - "stres #u4,@Ri+" - () - "stres $u4,@$Ri+" - (+ OP1_B OP2_D u4 Ri) - (set Ri (add Ri (const 4))) - () -) - -; Leave the coprocessor insns as stubs for now. -; -(define-pmacro (cop-stub name insn opc1 opc2 opc3 arg1 arg2) - (dni name - (.str insn " u4c,ccc,CRj," arg1 "," arg2) - (NOT-IN-DELAY-SLOT) - (.str insn " $u4c,$ccc,$" arg1 ",$" arg2) - (+ opc1 opc2 opc3 u4c ccc arg1 arg2) - (nop) ; STUB - () - ) -) - -(cop-stub copop copop OP1_9 OP2_F OP3_C CRj CRi) -(cop-stub copld copld OP1_9 OP2_F OP3_D Rjc CRi) -(cop-stub copst copst OP1_9 OP2_F OP3_E CRj Ric) -(cop-stub copsv copsv OP1_9 OP2_F OP3_F CRj Ric) - -(dni nop - "nop" - () - "nop" - (+ OP1_9 OP2_F OP3_A OP4_0) - (nop) - () -) - -(dni andccr - "andccr #u8" - () - "andccr $u8" - (+ OP1_8 OP2_3 u8) - (set ccr (and ccr u8)) - () -) - -(dni orccr - "orccr #u8" - () - "orccr $u8" - (+ OP1_9 OP2_3 u8) - (set ccr (or ccr u8)) - () -) - -(dni stilm - "stilm #u8" - () - "stilm $u8" - (+ OP1_8 OP2_7 u8) - (set ilm (and u8 (const #x1f))) - () -) - -(dni addsp - "addsp #s10" - () - "addsp $s10" - (+ OP1_A OP2_3 s10) - (set (reg h-gr 15) (add (reg h-gr 15) s10)) - () -) - -(define-pmacro (ext-op name opc1 opc2 opc3 op mode mask) - (dni name - (.str name " Ri") - () - (.str name " $Ri") - (+ opc1 opc2 opc3 Ri) - (set Ri (op WI (and mode Ri mask))) - () - ) -) - -(ext-op extsb OP1_9 OP2_7 OP3_8 ext QI (const #xff)) -(ext-op extub OP1_9 OP2_7 OP3_9 zext UQI (const #xff)) -(ext-op extsh OP1_9 OP2_7 OP3_A ext HI (const #xffff)) -(ext-op extuh OP1_9 OP2_7 OP3_B zext UHI (const #xffff)) - -(dni ldm0 - "ldm0 (reglist_low_ld)" - (NOT-IN-DELAY-SLOT) - "ldm0 ($reglist_low_ld)" - (+ OP1_8 OP2_C reglist_low_ld) - (sequence () - (if (and reglist_low_ld (const #x1)) - (sequence () - (set (reg h-gr 0) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x2)) - (sequence () - (set (reg h-gr 1) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x4)) - (sequence () - (set (reg h-gr 2) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x8)) - (sequence () - (set (reg h-gr 3) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x10)) - (sequence () - (set (reg h-gr 4) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x20)) - (sequence () - (set (reg h-gr 5) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x40)) - (sequence () - (set (reg h-gr 6) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_low_ld (const #x80)) - (sequence () - (set (reg h-gr 7) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - ) - ((fr30-1 (unit u-ldm))) -) - -(dni ldm1 - "ldm1 (reglist_hi_ld)" - (NOT-IN-DELAY-SLOT) - "ldm1 ($reglist_hi_ld)" - (+ OP1_8 OP2_D reglist_hi_ld) - (sequence () - (if (and reglist_hi_ld (const #x1)) - (sequence () - (set (reg h-gr 8) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x2)) - (sequence () - (set (reg h-gr 9) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x4)) - (sequence () - (set (reg h-gr 10) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x8)) - (sequence () - (set (reg h-gr 11) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x10)) - (sequence () - (set (reg h-gr 12) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x20)) - (sequence () - (set (reg h-gr 13) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x40)) - (sequence () - (set (reg h-gr 14) (mem WI (reg h-gr 15))) - (set (reg h-gr 15) (add (reg h-gr 15) (const 4))))) - (if (and reglist_hi_ld (const #x80)) - (set (reg h-gr 15) (mem WI (reg h-gr 15)))) - ) - ((fr30-1 (unit u-ldm))) -) - -(dni stm0 - "stm0 (reglist_low_st)" - (NOT-IN-DELAY-SLOT) - "stm0 ($reglist_low_st)" - (+ OP1_8 OP2_E reglist_low_st) - (sequence () - (if (and reglist_low_st (const #x1)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 7)))) - (if (and reglist_low_st (const #x2)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 6)))) - (if (and reglist_low_st (const #x4)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 5)))) - (if (and reglist_low_st (const #x8)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 4)))) - (if (and reglist_low_st (const #x10)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 3)))) - (if (and reglist_low_st (const #x20)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 2)))) - (if (and reglist_low_st (const #x40)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 1)))) - (if (and reglist_low_st (const #x80)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 0)))) - ) - ((fr30-1 (unit u-stm))) -) - -(dni stm1 - "stm1 (reglist_hi_st)" - (NOT-IN-DELAY-SLOT) - "stm1 ($reglist_hi_st)" - (+ OP1_8 OP2_F reglist_hi_st) - (sequence () - (if (and reglist_hi_st (const #x1)) - (sequence ((WI save-r15)) - (set save-r15 (reg h-gr 15)) - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) save-r15))) - (if (and reglist_hi_st (const #x2)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 14)))) - (if (and reglist_hi_st (const #x4)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 13)))) - (if (and reglist_hi_st (const #x8)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 12)))) - (if (and reglist_hi_st (const #x10)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 11)))) - (if (and reglist_hi_st (const #x20)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 10)))) - (if (and reglist_hi_st (const #x40)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 9)))) - (if (and reglist_hi_st (const #x80)) - (sequence () - (set (reg h-gr 15) (sub (reg h-gr 15) (const 4))) - (set (mem WI (reg h-gr 15)) (reg h-gr 8)))) - ) - ((fr30-1 (unit u-stm))) -) - -(dni enter - "enter #u10" - (NOT-IN-DELAY-SLOT) - "enter $u10" - (+ OP1_0 OP2_F u10) - (sequence ((WI tmp)) - (set tmp (sub (reg h-gr 15) (const 4))) - (set (mem WI tmp) (reg h-gr 14)) - (set (reg h-gr 14) tmp) - (set (reg h-gr 15) (sub (reg h-gr 15) u10))) - ((fr30-1 (unit u-exec (cycles 2)))) -) - -(dni leave - "leave" - () - "leave" - (+ OP1_9 OP2_F OP3_9 OP4_0) - (sequence () - (set (reg h-gr 15) (add (reg h-gr 14) (const 4))) - (set (reg h-gr 14) (mem WI (sub (reg h-gr 15) (const 4))))) - () -) - -(dni xchb - "xchb @Rj,Ri" - (NOT-IN-DELAY-SLOT) - "xchb @$Rj,$Ri" - (+ OP1_8 OP2_A Rj Ri) - (sequence ((WI tmp)) - (set tmp Ri) - (set Ri (mem UQI Rj)) - (set (mem UQI Rj) tmp)) - ((fr30-1 (unit u-load) (unit u-store))) -) diff --git a/binutils-2.24/cpu/fr30.opc b/binutils-2.24/cpu/fr30.opc deleted file mode 100644 index b09148e1..00000000 --- a/binutils-2.24/cpu/fr30.opc +++ /dev/null @@ -1,253 +0,0 @@ -/* FR30 opcode support. -*- C -*- - Copyright 2011 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* This file is an addendum to fr30.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* ??? This can be improved upon. */ -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 16 -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 4) - -/* -- */ - -/* -- asm.c */ -/* Handle register lists for LDMx and STMx. */ - -static int -parse_register_number (const char **strp) -{ - int regno; - - if (**strp < '0' || **strp > '9') - return -1; /* Error. */ - regno = **strp - '0'; - ++*strp; - - if (**strp >= '0' && **strp <= '9') - { - regno = regno * 10 + (**strp - '0'); - ++*strp; - } - - return regno; -} - -static const char * -parse_register_list (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep, - int high_low, /* 0 == high, 1 == low. */ - int load_store) /* 0 == load, 1 == store. */ -{ - *valuep = 0; - while (**strp && **strp != ')') - { - int regno; - - if (**strp != 'R' && **strp != 'r') - break; - ++*strp; - - regno = parse_register_number (strp); - if (regno == -1) - return _("Register number is not valid"); - if (regno > 7 && !high_low) - return _("Register must be between r0 and r7"); - if (regno < 8 && high_low) - return _("Register must be between r8 and r15"); - - if (high_low) - regno -= 8; - - if (load_store) /* Mask is reversed for store. */ - *valuep |= 0x80 >> regno; - else - *valuep |= 1 << regno; - - if (**strp == ',') - { - if (*(*strp + 1) == ')') - break; - ++*strp; - } - } - - if (!*strp || **strp != ')') - return _("Register list is not valid"); - - return NULL; -} - -static const char * -parse_low_register_list_ld (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 0 /* Low. */, 0 /* Load. */); -} - -static const char * -parse_hi_register_list_ld (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 1 /* High. */, 0 /* Load. */); -} - -static const char * -parse_low_register_list_st (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 0 /* Low. */, 1 /* Store. */); -} - -static const char * -parse_hi_register_list_st (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_register_list (cd, strp, opindex, valuep, - 1 /* High. */, 1 /* Store. */); -} - -/* -- */ - -/* -- dis.c */ -static void -print_register_list (void * dis_info, - long value, - long offset, - int load_store) /* 0 == load, 1 == store. */ -{ - disassemble_info *info = dis_info; - int mask; - int reg_index = 0; - char * comma = ""; - - if (load_store) - mask = 0x80; - else - mask = 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "r%li", reg_index + offset); - comma = ","; - } - - for (reg_index = 1; reg_index <= 7; ++reg_index) - { - if (load_store) - mask >>= 1; - else - mask <<= 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "%sr%li", comma, reg_index + offset); - comma = ","; - } - } -} - -static void -print_hi_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 8, 0 /* Load. */); -} - -static void -print_low_register_list_ld (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 0, 0 /* Load. */); -} - -static void -print_hi_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 8, 1 /* Store. */); -} - -static void -print_low_register_list_st (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_register_list (dis_info, value, 0, 1 /* Store. */); -} - -static void -print_m4 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "%ld", value); -} -/* -- */ diff --git a/binutils-2.24/cpu/frv.cpu b/binutils-2.24/cpu/frv.cpu deleted file mode 100644 index b6c4f809..00000000 --- a/binutils-2.24/cpu/frv.cpu +++ /dev/null @@ -1,9803 +0,0 @@ -; Fujitsu FRV opcode support, for GNU Binutils. -*- Scheme -*- -; -; Copyright 2000, 2001, 2003, 2004, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Fujitsu. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -; define-arch must appear first - -(define-arch - (name frv) ; name of cpu architecture - (comment "Fujitsu FRV") - (insn-lsb0? #t) - (machs frv fr550 fr500 fr450 fr400 tomcat simple) - (isas frv) -) - -(define-isa - (name frv) - (base-insn-bitsize 32) - ; Initial bitnumbers to decode insns by. - (decode-assist (24 23 22 21 20 19 18)) - (liw-insns 1) ; The frv fetches up to 1 insns at a time. - (parallel-insns 8) ; The frv executes up to 8 insns at a time. -) - -; Cpu family definitions. -; -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name frvbf) - (comment "Fujitsu FRV base family") - (endian big) - (word-bitsize 32) -) - -; Generic FR-V machine. Supports the entire architecture -(define-mach - (name frv) - (comment "Generic FRV cpu") - (cpu frvbf) -) -(define-model - (name frv) (comment "Generic FRV model") (attrs) - (mach frv) - - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - ; (state) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; FR550 machine -(define-mach - (name fr550) - (comment "FR550 cpu") - (cpu frvbf) -) -(define-model - (name fr550) (comment "FR550 model") (attrs) - (mach fr550) - - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - (state - ; State items - ; These are all masks with each bit representing one register. - (prev-fr-load DI) ; Previous use of FR register was target of a load - (prev-fr-complex-1 DI) ; Previous use of FR register has variable latency - (prev-fr-complex-2 DI) ; Previous use of FR register has variable latency - (prev-ccr-complex DI) ; Previous use of CCR register has variable latency - (prev-acc-mmac DI) ; Previous use of ACC register was a MMAC category - (cur-fr-load DI) ; Current use of FR register was target of a load - (cur-fr-complex-1 DI) ; Current use of FR register has variable latency - (cur-fr-complex-2 DI) ; Current use of FR register has variable latency - (cur-ccr-complex SI) ; Current use of CCR register has variable latency - (cur-acc-mmac DI) ; Current use of ACC register was a MMAC category - ) - ; Basic unit for instructions with no latency penalties - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Basic integer insn unit - (unit u-integer "Integer Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer multiplication unit - (unit u-imul "Integer Multiplication Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer division unit - (unit u-idiv "Integer Division Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Branch unit - (unit u-branch "Branch Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - ; Trap unit - (unit u-trap "Trap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Condition code check unit - (unit u-check "Check Unit" () - 1 1 ; issue done - () ; state - ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Float Arithmetic unit - (unit u-float-arith "Float Arithmetic unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1) ; inputs - (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Dual Arithmetic unit - (unit u-float-dual-arith "Float Arithmetic unit" () - ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI - 1 3 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1) ; inputs - (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Div unit - (unit u-float-div "Float Div unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1)) ; inputs - ((FRk INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Square Root unit - (unit u-float-sqrt "Float Square Root unit" () - 1 1 ; issue done - () ; state - ((FRj INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Compare unit - (unit u-float-compare "Float Compare unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1) - (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs - ((FCCi_2 INT -1)) ; outputs - () ; profile action (default) - ) - ; Dual Float Compare unit - (unit u-float-dual-compare "Float Dual Compare unit" () - ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI - 1 3 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1)) ; inputs - ((FCCi_2 INT -1)) ; outputs - () ; profile action (default) - ) - ; FR Move to GR unit - (unit u-fr2gr "FR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((FRintk INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to FR unit - (unit u-gr2fr "GR Move to FR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; SPR Move to GR unit - (unit u-spr2gr "SPR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((spr INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to SPR unit - (unit u-gr2spr "GR Move to SPR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((spr INT -1)) ; outputs - () ; profile action (default) - ) - ; GR set half unit - (unit u-set-hilo "GR Set Half" () - 1 1 ; issue done - () ; state - () ; inputs - ((GRkhi INT -1) (GRklo INT -1)) ; outputs - () ; profile action (default) - ) - ; GR load unit - (unit u-gr-load "GR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (GRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; GR store unit - (unit u-gr-store "GR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; FR load unit - (unit u-fr-load "FR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((FRintk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; FR store unit - (unit u-fr-store "FR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Swap unit - (unit u-swap "Swap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1)) ; outputs - () ; profile action (default) - ) - ; FR Move to FR unit - (unit u-fr2fr "FR Move to FR Unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1)) ; inputs - ((FRk INT -1)) ; outputs - () ; profile action (default) - ) - ; Clrgr unit - (unit u-clrgr "Clrgr Unit" () - 1 1 ; issue done - () ; state - ((GRk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Clrfr unit - (unit u-clrfr "Clrfr Unit" () - 1 1 ; issue done - () ; state - ((FRk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache invalidate unit - (unit u-ici "Insn cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache invalidate unit - (unit u-dci "Data cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache flush unit - (unit u-dcf "Data cache flush unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache preload unit - (unit u-icpl "Insn cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache preload unit - (unit u-dcpl "Data cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache unlock unit - (unit u-icul "Insn cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache unlock unit - (unit u-dcul "Data cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; commit unit - (unit u-commit "Commit Unit" () - 1 1 ; issue done - () ; state - ((GRk INT -1) (FRk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Float Conversion unit - (unit u-float-convert "Float Conversion unit" () - 1 1 ; issue done - () ; state - ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Media units - (unit u-media "Media unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-quad "Media-quad unit" () - 1 1 ; issue done - () ; state - ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs - ((FRintkeven INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-dual-expand "Media Dual Expand unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintkeven INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-dual "Media-3-dual unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-acc "Media unit for M-3 using ACC" () - 1 1 ; issue done - () ; state - ((FRintj INT -1) (ACC40Si INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-acc-dual "Media-3-acc-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((FRintkeven INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-wtacc "Media-3-wtacc unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (ACC40Sk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-media-3-mclracc "Media-3-mclracc unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-media-set "Media set" () - 1 1 ; issue done - () ; state - () ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4 "Media-4 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-acc "Media-4-acc unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-acc-dual "Media-4-acc-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-add-sub "Media-4-add-sub unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-add-sub-dual "Media-4-add-sub-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-quad "Media-4-quad unit" () - 1 1 ; issue done - () ; state - ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) -) - -; FR500 machine. -(define-mach - (name fr500) - (comment "FR500 cpu") - (cpu frvbf) -) -(define-model - (name fr500) (comment "FR500 model") (attrs) - (mach fr500) - - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - (state - ; State items - ; These are all masks with each bit representing one register. - (prev-fpop DI) ; Previous use of FR register was floating point insn - (prev-media DI) ; Previous use of FR register was a media insn - (prev-cc-complex DI) ; Previous use of ICC register was not simple - (cur-fpop DI) ; Current use of FR register was floating point insn - (cur-media DI) ; Current use of FR register was a media insn - (cur-cc-complex DI) ; Current use of ICC register was not simple - ) - ; Basic unit for instructions with no latency penalties - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Basic integer insn unit - (unit u-integer "Integer Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer multiplication unit - (unit u-imul "Integer Multiplication Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer division unit - (unit u-idiv "Integer Division Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Branch unit - (unit u-branch "Branch Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - ; Trap unit - (unit u-trap "Trap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Condition code check unit - (unit u-check "Check Unit" () - 1 1 ; issue done - () ; state - ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Clrgr unit - (unit u-clrgr "Clrgr Unit" () - 1 1 ; issue done - () ; state - ((GRk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Clrfr unit - (unit u-clrfr "Clrfr Unit" () - 1 1 ; issue done - () ; state - ((FRk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; GR set half unit - (unit u-set-hilo "GR Set Half" () - 1 1 ; issue done - () ; state - () ; inputs - ((GRkhi INT -1) (GRklo INT -1)) ; outputs - () ; profile action (default) - ) - ; GR load unit -- TODO doesn't handle quad - (unit u-gr-load "GR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (GRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; GR store unit -- TODO doesn't handle quad - (unit u-gr-store "GR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; GR recovering store unit -- TODO doesn't handle quad - (unit u-gr-r-store "GR Recovering Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; FR load unit -- TODO doesn't handle quad - (unit u-fr-load "FR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((FRintk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; FR store unit -- TODO doesn't handle quad - (unit u-fr-store "FR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; FR recovering store unit -- TODO doesn't handle quad - (unit u-fr-r-store "FR Recovering Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Swap unit - (unit u-swap "Swap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1)) ; outputs - () ; profile action (default) - ) - ; FR Move to FR unit - (unit u-fr2fr "FR Move to FR Unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1)) ; inputs - ((FRk INT -1)) ; outputs - () ; profile action (default) - ) - ; FR Move to GR unit - (unit u-fr2gr "FR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((FRintk INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; SPR Move to GR unit - (unit u-spr2gr "SPR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((spr INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to FR unit - (unit u-gr2fr "GR Move to FR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to SPR unit - (unit u-gr2spr "GR Move to SPR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((spr INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Arithmetic unit - (unit u-float-arith "Float Arithmetic unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1) ; inputs - (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Dual Arithmetic unit - (unit u-float-dual-arith "Float Arithmetic unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1) ; inputs - (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Div unit - (unit u-float-div "Float Div unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1)) ; inputs - ((FRk INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Square Root unit - (unit u-float-sqrt "Float Square Root unit" () - 1 1 ; issue done - () ; state - ((FRj INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Dual Square Root unit - (unit u-float-dual-sqrt "Float Dual Square Root unit" () - 1 1 ; issue done - () ; state - ((FRj INT -1)) ; inputs - ((FRk INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Compare unit - (unit u-float-compare "Float Compare unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1) - (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs - ((FCCi_2 INT -1)) ; outputs - () ; profile action (default) - ) - ; Dual Float Compare unit - (unit u-float-dual-compare "Float Dual Compare unit" () - 1 1 ; issue done - () ; state - ((FRi INT -1) (FRj INT -1)) ; inputs - ((FCCi_2 INT -1)) ; outputs - () ; profile action (default) - ) - ; Float Conversion unit - (unit u-float-convert "Float Conversion unit" () - 1 1 ; issue done - () ; state - ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs - ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; Dual Float Conversion unit - (unit u-float-dual-convert "Float Dual Conversion unit" () - 1 1 ; issue done - () ; state - ((FRj INT -1) (FRintj INT -1)) ; inputs - ((FRk INT -1) (FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit - (unit u-media "Media unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1) (ACC40Si INT -1) (ACCGi INT -1)) ; inputs - ((FRintk INT -1) (ACC40Sk INT -1) (ACC40Uk INT -1) (ACCGk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Quad Arithmetic unit - (unit u-media-quad-arith "Media Quad Arithmetic unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual Multiplication unit - (unit u-media-dual-mul "Media Dual Multiplication unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Quad Multiplication unit - (unit u-media-quad-mul "Media Quad Multiplication unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Quad Complex unit - (unit u-media-quad-complex "Media Quad Complex unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual Expand unit - (unit u-media-dual-expand "Media Dual Expand unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual Unpack unit - (unit u-media-dual-unpack "Media Dual Unpack unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual byte to half unit - (unit u-media-dual-btoh "Media Byte to byte" () - 1 1 ; issue done - () ; state - ((FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual half to byte unit - (unit u-media-dual-htob "Media Half to byte" () - 1 1 ; issue done - () ; state - ((FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual byte to half unit extended - (unit u-media-dual-btohe "Media Byte to byte extended" () - 1 1 ; issue done - () ; state - ((FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Barrier unit - (unit u-barrier "Barrier unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Memory Barrier unit - (unit u-membar "Memory Barrier unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache invalidate unit - (unit u-ici "Insn cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache invalidate unit - (unit u-dci "Data cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache flush unit - (unit u-dcf "Data cache flush unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache preload unit - (unit u-icpl "Insn cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache preload unit - (unit u-dcpl "Data cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache unlock unit - (unit u-icul "Insn cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache unlock unit - (unit u-dcul "Data cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; commit unit - (unit u-commit "Commit Unit" () - 1 1 ; issue done - () ; state - ((GRk INT -1) (FRk INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; Tomcat machine. Early version of fr500 machine -(define-mach - (name tomcat) - (comment "Tomcat -- early version of fr500") - (cpu frvbf) -) -(define-model - (name tomcat) (comment "Tomcat model") (attrs) - (mach tomcat) - - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - ; (state) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; FR400 machine -(define-mach - (name fr400) - (comment "FR400 cpu") - (cpu frvbf) -) -(define-model - (name fr400) (comment "FR400 model") (attrs) - (mach fr400) - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - ; `state' is a list of variables for recording model state - (state - ; State items - ; These are all masks with each bit representing one register. - (prev-fp-load DI) ; Previous use of FR register was floating point load - (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 - (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 - (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 - (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 - (cur-fp-load DI) ; Current use of FR register is floating point load - (cur-fr-p4 DI) ; Current use of FR register is media unit 4 - (cur-fr-p6 DI) ; Current use of FR register is media unit 6 - (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 - (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 - ) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Basic integer insn unit - (unit u-integer "Integer Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer multiplication unit - (unit u-imul "Integer Multiplication Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer division unit - (unit u-idiv "Integer Division Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Branch unit - (unit u-branch "Branch Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - ; Trap unit - (unit u-trap "Trap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Condition code check unit - (unit u-check "Check Unit" () - 1 1 ; issue done - () ; state - ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; GR set half unit - (unit u-set-hilo "GR Set Half" () - 1 1 ; issue done - () ; state - () ; inputs - ((GRkhi INT -1) (GRklo INT -1)) ; outputs - () ; profile action (default) - ) - ; GR load unit -- TODO doesn't handle quad - (unit u-gr-load "GR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (GRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; GR store unit -- TODO doesn't handle quad - (unit u-gr-store "GR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; FR load unit -- TODO doesn't handle quad - (unit u-fr-load "FR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((FRintk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; FR store unit -- TODO doesn't handle quad - (unit u-fr-store "FR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Swap unit - (unit u-swap "Swap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1)) ; outputs - () ; profile action (default) - ) - ; FR Move to GR unit - (unit u-fr2gr "FR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((FRintk INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; SPR Move to GR unit - (unit u-spr2gr "SPR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((spr INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to FR unit - (unit u-gr2fr "GR Move to FR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to SPR unit - (unit u-gr2spr "GR Move to SPR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((spr INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M1 -- see table 13-8 in the fr400 LSI - (unit u-media-1 "Media-1 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-1-quad "Media-1-quad unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () - 1 1 ; issue done - () ; state - () ; inputs - ((FRkhi INT -1) (FRklo INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M2 -- see table 13-8 in the fr400 LSI - (unit u-media-2 "Media-2 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-quad "Media-2-quad unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-acc "Media-2-acc unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-acc-dual "Media-2-acc-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-add-sub "Media-2-add-sub unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M3 -- see table 13-8 in the fr400 LSI - (unit u-media-3 "Media-3 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-dual "Media-3-dual unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-quad "Media-3-quad unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M4 -- see table 13-8 in the fr400 LSI - (unit u-media-4 "Media-4 unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-accg "Media-4-accg unit" () - 1 1 ; issue done - () ; state - ((ACCGi INT -1) (FRinti INT -1)) ; inputs - ((ACCGk INT -1) (FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-acc-dual "Media-4-acc-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M6 -- see table 13-8 in the fr400 LSI - (unit u-media-6 "Media-6 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M7 -- see table 13-8 in the fr400 LSI - (unit u-media-7 "Media-1 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FCCk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual Expand unit - (unit u-media-dual-expand "Media Dual Expand unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual half to byte unit - (unit u-media-dual-htob "Media Half to byte" () - 1 1 ; issue done - () ; state - ((FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Barrier unit - (unit u-barrier "Barrier unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Memory Barrier unit - (unit u-membar "Memory Barrier unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache invalidate unit - (unit u-ici "Insn cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache invalidate unit - (unit u-dci "Data cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache flush unit - (unit u-dcf "Data cache flush unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache preload unit - (unit u-icpl "Insn cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache preload unit - (unit u-dcpl "Data cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache unlock unit - (unit u-icul "Insn cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache unlock unit - (unit u-dcul "Data cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; FR450 machine -(define-mach - (name fr450) - (comment "FR450 cpu") - (cpu frvbf) -) -(define-model - (name fr450) (comment "FR450 model") (attrs) - (mach fr450) - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - ; `state' is a list of variables for recording model state - (state - ; State items - ; These are all masks with each bit representing one register. - (prev-fp-load DI) ; Previous use of FR register was floating point load - (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 - (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 - (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 - (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 - (cur-fp-load DI) ; Current use of FR register is floating point load - (cur-fr-p4 DI) ; Current use of FR register is media unit 4 - (cur-fr-p6 DI) ; Current use of FR register is media unit 6 - (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 - (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 - ) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Basic integer insn unit - (unit u-integer "Integer Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer multiplication unit - (unit u-imul "Integer Multiplication Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Integer division unit - (unit u-idiv "Integer Division Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (ICCi_1 INT -1)) ; outputs - () ; profile action (default) - ) - ; Branch unit - (unit u-branch "Branch Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - ; Trap unit - (unit u-trap "Trap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) - (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Condition code check unit - (unit u-check "Check Unit" () - 1 1 ; issue done - () ; state - ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; GR set half unit - (unit u-set-hilo "GR Set Half" () - 1 1 ; issue done - () ; state - () ; inputs - ((GRkhi INT -1) (GRklo INT -1)) ; outputs - () ; profile action (default) - ) - ; GR load unit -- TODO doesn't handle quad - (unit u-gr-load "GR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1) (GRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; GR store unit -- TODO doesn't handle quad - (unit u-gr-store "GR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; FR load unit -- TODO doesn't handle quad - (unit u-fr-load "FR Load Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((FRintk INT -1) (FRdoublek INT -1)) ; outputs - () ; profile action (default) - ) - ; FR store unit -- TODO doesn't handle quad - (unit u-fr-store "FR Store Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Swap unit - (unit u-swap "Swap Unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - ((GRk INT -1)) ; outputs - () ; profile action (default) - ) - ; FR Move to GR unit - (unit u-fr2gr "FR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((FRintk INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; SPR Move to GR unit - (unit u-spr2gr "SPR Move to GR Unit" () - 1 1 ; issue done - () ; state - ((spr INT -1)) ; inputs - ((GRj INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to FR unit - (unit u-gr2fr "GR Move to FR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; GR Move to SPR unit - (unit u-gr2spr "GR Move to SPR Unit" () - 1 1 ; issue done - () ; state - ((GRj INT -1)) ; inputs - ((spr INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M1 -- see table 14-8 in the fr450 LSI - (unit u-media-1 "Media-1 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-1-quad "Media-1-quad unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () - 1 1 ; issue done - () ; state - () ; inputs - ((FRkhi INT -1) (FRklo INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M2 -- see table 14-8 in the fr450 LSI - (unit u-media-2 "Media-2 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-quad "Media-2-quad unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-acc "Media-2-acc unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-acc-dual "Media-2-acc-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-add-sub "Media-2-add-sub unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((ACC40Sk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M3 -- see table 14-8 in the fr450 LSI - (unit u-media-3 "Media-3 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-dual "Media-3-dual unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-3-quad "Media-3-quad unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M4 -- see table 14-8 in the fr450 LSI - (unit u-media-4 "Media-4 unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1) (FRintj INT -1)) ; inputs - ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-accg "Media-4-accg unit" () - 1 1 ; issue done - () ; state - ((ACCGi INT -1) (FRinti INT -1)) ; inputs - ((ACCGk INT -1) (FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-acc-dual "Media-4-acc-dual unit" () - 1 1 ; issue done - () ; state - ((ACC40Si INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-media-4-mclracca "Media-4 unit for MCLRACC with #A=1" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Media unit M6 -- see table 14-8 in the fr450 LSI - (unit u-media-6 "Media-6 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media unit M7 -- see table 14-8 in the fr450 LSI - (unit u-media-7 "Media-1 unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1) (FRintj INT -1)) ; inputs - ((FCCk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual Expand unit - (unit u-media-dual-expand "Media Dual Expand unit" () - 1 1 ; issue done - () ; state - ((FRinti INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Media Dual half to byte unit - (unit u-media-dual-htob "Media Half to byte" () - 1 1 ; issue done - () ; state - ((FRintj INT -1)) ; inputs - ((FRintk INT -1)) ; outputs - () ; profile action (default) - ) - ; Barrier unit - (unit u-barrier "Barrier unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Memory Barrier unit - (unit u-membar "Memory Barrier unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache invalidate unit - (unit u-ici "Insn cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache invalidate unit - (unit u-dci "Data cache invalidate unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache flush unit - (unit u-dcf "Data cache flush unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache preload unit - (unit u-icpl "Insn cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache preload unit - (unit u-dcpl "Data cache preload unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Insn cache unlock unit - (unit u-icul "Insn cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - ; Data cache unlock unit - (unit u-dcul "Data cache unlock unit" () - 1 1 ; issue done - () ; state - ((GRi INT -1) (GRj INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; Simple machine - single issue integer machine -(define-mach - (name simple) - (comment "Simple single issue integer cpu") - (cpu frvbf) -) -(define-model - (name simple) (comment "Simple model") (attrs) - (mach simple) - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - ; `state' is a list of variables for recording model state - (state) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; The instruction fetch/execute cycle. -; -; This is how to fetch and decode an instruction. -; Leave it out for now - -; (define-extract (const SI 0)) - -; This is how to execute a decoded instruction. -; Leave it out for now - -; (define-execute (const SI 0)) - -; An attribute to describe which unit an insn runs in. -(define-attr - (for insn) - (type enum) - (name UNIT) - (comment "parallel execution pipeline selection") - ; The order of declaration is significant. - ; See the *_unit_mapping tables in frv.opc - ; Keep variations on the same unit together. - ; Keep the '01' variant immediately after the '1' variant in each unit. - ; Keep the 'ALL' variations immediately after the last numbered variant in each unit. - (values NIL - I0 I1 I01 I2 I3 IALL - FM0 FM1 FM01 FM2 FM3 FMALL FMLOW - B0 B1 B01 - C - MULT-DIV ; multiply/division slotted differently on different machines - IACC ; iacc multiply slotted differently on different machines - LOAD ; loads slotted differently on different machines - STORE ; store slotted differently on different machines - SCAN ; scan, scani slotted differently on different machines - DCPL ; dcpl slotted differently on different machines - MDUALACC ; media dual acc slotted differently on different machines - MDCUTSSI ; mdcutssi insn slotted differently on different machines - MCLRACC-1; mclracc A==1 slotted differently on different machines - NUM_UNITS - ) -) -; Attributes to describe major categories of insns -(define-attr - (for insn) - (type enum) - (name FR400-MAJOR) - (comment "fr400 major insn categories") - ; The order of declaration is significant. Keep variations on the same major - ; together. - (values NONE - I-1 I-2 I-3 I-4 I-5 - B-1 B-2 B-3 B-4 B-5 B-6 - C-1 C-2 - M-1 M-2 - ) -) -(define-attr - (for insn) - (type enum) - (name FR450-MAJOR) - (comment "fr450 major insn categories") - ; The order of declaration is significant. Keep variations on the same major - ; together. - (values NONE - I-1 I-2 I-3 I-4 I-5 - B-1 B-2 B-3 B-4 B-5 B-6 - C-1 C-2 - M-1 M-2 M-3 M-4 M-5 M-6 - ) -) -(define-attr - (for insn) - (type enum) - (name FR500-MAJOR) - (comment "fr500 major insn categories") - ; The order of declaration is significant. Keep variations on the same major - ; together. - (values NONE - I-1 I-2 I-3 I-4 I-5 I-6 - B-1 B-2 B-3 B-4 B-5 B-6 - C-1 C-2 - F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8 - M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8 - ) -) -(define-attr - (for insn) - (type enum) - (name FR550-MAJOR) - (comment "fr550 major insn categories") - ; The order of declaration is significant. Keep variations on the same major - ; together. - (values NONE - I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8 - B-1 B-2 B-3 B-4 B-5 B-6 - C-1 C-2 - F-1 F-2 F-3 F-4 - M-1 M-2 M-3 M-4 M-5 - ) -) -; Privileged insn -(define-attr - (for insn) - (type boolean) - (name PRIVILEGED) - (comment "insn only allowed in supervisor mode") -) -; Non-Excepting insn -(define-attr - (for insn) - (type boolean) - (name NON-EXCEPTING) - (comment "non-excepting insn") -) -; Conditional insn -(define-attr - (for insn) - (type boolean) - (name CONDITIONAL) - (comment "conditional insn") -) -; insn accesses FR registers -(define-attr - (for insn) - (type boolean) - (name FR-ACCESS) - (comment "insn accesses FR registers") -) -; insn preserves MSR.OVF -(define-attr - (for insn) - (type boolean) - (name PRESERVE-OVF) - (comment "Preserve value of MSR.OVF") -) -; "Audio" instruction provided by the fr405 but not the original fr400 core. -(define-attr - (for insn) - (type boolean) - (name AUDIO) - (comment "Audio instruction added with FR405") -) -; null attribute -- used as a place holder for where an attribue is required. -(define-attr - (for insn) - (type boolean) - (name NA) - (comment "placeholder attribute") - (attrs META) ; do not define in any generated file for now -) - -; IDOC attribute for instruction documentation. - -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MEM - () "Memory") - (ALU - () "ALU") - (FPU - () "FPU") - (BR - () "Branch") - (PRIV - () "Priviledged") - (MISC - () "Miscellaneous") - ) -) - -; Instruction fields. -; -; Attributes: -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 -(dnf f-pack "packing bit" () 31 1) -(dnf f-op "primary opcode" () 24 7) -(dnf f-ope1 "extended opcode" () 11 6) -(dnf f-ope2 "extended opcode" () 9 4) -(dnf f-ope3 "extended opcode" () 15 3) -(dnf f-ope4 "extended opcode" () 7 2) - -(dnf f-GRi "source register 1" () 17 6) -(dnf f-GRj "source register 2" () 5 6) -(dnf f-GRk "destination register" () 30 6) - -(dnf f-FRi "source register 1" () 17 6) -(dnf f-FRj "source register 2" () 5 6) -(dnf f-FRk "destination register" () 30 6) - -(dnf f-CPRi "source register 1" () 17 6) -(dnf f-CPRj "source register 2" () 5 6) -(dnf f-CPRk "destination register" () 30 6) - -(dnf f-ACCGi "source register" () 17 6) -(dnf f-ACCGk "destination register" () 30 6) - -(dnf f-ACC40Si "40 bit signed accumulator" () 17 6) -(dnf f-ACC40Ui "40 bit unsigned accumulator" () 17 6) -(dnf f-ACC40Sk "40 bit accumulator" () 30 6) -(dnf f-ACC40Uk "40 bit accumulator" () 30 6) - -(dnf f-CRi "source register" () 14 3) -(dnf f-CRj "source register" () 2 3) -(dnf f-CRk "destination register" () 27 3) -(dnf f-CCi "condition register" () 11 3) - -(df f-CRj_int "target cr for ck insns" () 26 2 UINT - ((value pc) (sub WI value 4)) - ((value pc) (add WI value 4)) -) -(dnf f-CRj_float "target cr for fck insns" () 26 2) - -(dnf f-ICCi_1 "condition register" () 11 2) -(dnf f-ICCi_2 "condition register" () 26 2) -(dnf f-ICCi_3 "condition register" () 1 2) -(dnf f-FCCi_1 "condition register" () 11 2) -(dnf f-FCCi_2 "condition register" () 26 2) -(dnf f-FCCi_3 "condition register" () 1 2) -(dnf f-FCCk "condition register" () 26 2) -(dnf f-eir "exception insn register" () 17 6) - -(df f-s10 "10 bit sign extended" () 9 10 INT #f #f) -(df f-s12 "12 bit sign extended" () 11 12 INT #f #f) -(df f-d12 "12 bit sign extended" () 11 12 INT #f #f) -(df f-u16 "16 bit unsigned" () 15 16 UINT #f #f) -(df f-s16 "16 bit sign extended" () 15 16 INT #f #f) -(df f-s6 "6 bit signed" () 5 6 INT #f #f) -(df f-s6_1 "6 bit signed" () 11 6 INT #f #f) -(df f-u6 "6 bit unsigned" () 5 6 UINT #f #f) -(df f-s5 "5 bit signed" () 4 5 INT #f #f) - -(df f-u12-h "upper 6 bits of u12" () 17 6 INT #f #f) -(df f-u12-l "lower 6 bits of u12" () 5 6 UINT #f #f) -(dnmf f-u12 "12 bit signed immediate" () INT - (f-u12-h f-u12-l) - (sequence () ; insert - (set (ifield f-u12-h) (sra SI (ifield f-u12) 6)) - (set (ifield f-u12-l) (and (ifield f-u12) #x3f)) - ) - (sequence () ; extract - (set (ifield f-u12) (or (sll (ifield f-u12-h) 6) - (ifield f-u12-l))) - ) -) - -(dnf f-int-cc "integer branch conditions" () 30 4) -(dnf f-flt-cc "floating branch conditions" () 30 4) -(df f-cond "conditional arithmetic" () 8 1 UINT #f #f) -(df f-ccond "lr branch condition" () 12 1 UINT #f #f) -(df f-hint "2 bit branch prediction hint" () 17 2 UINT #f #f) -(df f-LI "link indicator" () 25 1 UINT #f #f) -(df f-lock "cache lock indicator" () 25 1 UINT #f #f) -(df f-debug "debug mode indicator" () 25 1 UINT #f #f) -(df f-A "all accumulator bit" () 17 1 UINT #f #f) -(df f-ae "cache all entries indicator" () 25 1 UINT #f #f) - -(dnf f-spr-h "upper 6 bits of spr" () 30 6) -(dnf f-spr-l "lower 6 bits of spr" () 17 6) -(dnmf f-spr "special purpose register" () UINT - (f-spr-h f-spr-l) - (sequence () ; insert - (set (ifield f-spr-h) (srl (ifield f-spr) (const 6))) - (set (ifield f-spr-l) (and (ifield f-spr) (const #x3f))) - ) - (sequence () ; extract - (set (ifield f-spr) (or (sll (ifield f-spr-h) (const 6)) - (ifield f-spr-l))) - ) -) - -(df f-label16 "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT - ((value pc) (sra WI (sub WI value pc) (const 2))) - ((value pc) (add WI (sll WI value (const 2)) pc)) -) - -(df f-labelH6 "upper 6 bits of label24" () 30 6 INT #f #f) -(dnf f-labelL18 "lower 18 bits of label24" () 17 18) -(dnmf f-label24 "26 bit signed offset" (PCREL-ADDR) INT - (f-labelH6 f-labelL18) - ; insert - (sequence () - (set (ifield f-labelH6) - (sra WI (sub (ifield f-label24) pc) (const 20))) - (set (ifield f-labelL18) - (and (srl (sub (ifield f-label24) pc) (const 2)) - (const #x3ffff))) - ) - ; extract - (sequence () - (set (ifield f-label24) - (add (sll (or (sll (ifield f-labelH6) (const 18)) - (ifield f-labelL18)) - (const 2)) - pc))) -) - -(dnf f-LRAE "Load Real Address E flag" () 5 1) -(dnf f-LRAD "Load Real Address D flag" () 4 1) -(dnf f-LRAS "Load Real Address S flag" () 3 1) - -(dnf f-TLBPRopx "TLB Probe operation number" () 28 3) -(dnf f-TLBPRL "TLB Probe L flag" () 25 1) - -(dnf f-ICCi_1-null "null field" (RESERVED) 11 2) -(dnf f-ICCi_2-null "null field" (RESERVED) 26 2) -(dnf f-ICCi_3-null "null field" (RESERVED) 1 2) -(dnf f-FCCi_1-null "null field" (RESERVED) 11 2) -(dnf f-FCCi_2-null "null field" (RESERVED) 26 2) -(dnf f-FCCi_3-null "null field" (RESERVED) 1 2) -(dnf f-rs-null "null field" (RESERVED) 17 6) -(dnf f-GRi-null "null field" (RESERVED) 17 6) -(dnf f-GRj-null "null field" (RESERVED) 5 6) -(dnf f-GRk-null "null field" (RESERVED) 30 6) -(dnf f-FRi-null "null field" (RESERVED) 17 6) -(dnf f-FRj-null "null field" (RESERVED) 5 6) -(dnf f-ACCj-null "null field" (RESERVED) 5 6) -(dnf f-rd-null "null field" (RESERVED) 30 6) -(dnf f-cond-null "null field" (RESERVED) 30 4) -(dnf f-ccond-null "null field" (RESERVED) 12 1) -(dnf f-s12-null "null field" (RESERVED) 11 12) -(dnf f-label16-null "null field" (RESERVED) 15 16) -(dnf f-misc-null-1 "null field" (RESERVED) 30 5) -(dnf f-misc-null-2 "null field" (RESERVED) 11 6) -(dnf f-misc-null-3 "null field" (RESERVED) 11 4) -(dnf f-misc-null-4 "null field" (RESERVED) 17 2) -(dnf f-misc-null-5 "null field" (RESERVED) 17 16) -(dnf f-misc-null-6 "null field" (RESERVED) 30 3) -(dnf f-misc-null-7 "null field" (RESERVED) 17 3) -(dnf f-misc-null-8 "null field" (RESERVED) 5 3) -(dnf f-misc-null-9 "null field" (RESERVED) 5 4) -(dnf f-misc-null-10 "null field" (RESERVED) 16 5) -(dnf f-misc-null-11 "null field" (RESERVED) 5 1) - -(dnf f-LRA-null "null field" (RESERVED) 2 3) -(dnf f-TLBPR-null "null field" (RESERVED) 30 2) - -(dnf f-LI-off "null field" (RESERVED) 25 1) -(dnf f-LI-on "null field" (RESERVED) 25 1) - -; Relocation annotations. -(dsh h-reloc-ann "relocation annotation" () (register BI)) -(dnf f-reloc-ann "relocation annotation" () 0 0) - -(define-pmacro (dann xname xcomment xmode xparse xprint) - (define-operand - (name xname) - (comment xcomment) - (type h-reloc-ann) - (index f-reloc-ann) - (mode xmode) - (handlers (parse xparse) (print xprint)) - ) - ) - - -; Enums. - -; insn-op: -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op "insn op enums" () OP_ f-op - ( - "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" - "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" - "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" - "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" - "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4A" "4B" "4C" "4D" "4E" "4F" - "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5A" "5B" "5C" "5D" "5E" "5F" - "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6A" "6B" "6C" "6D" "6E" "6F" - "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7A" "7B" "7C" "7D" "7E" "7F" - ) -) - -(define-normal-insn-enum insn-ope1 "insn ope enums" () OPE1_ f-ope1 - ( - "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" - "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" - "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" - "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" - ) -) - -(define-normal-insn-enum insn-ope2 "insn ope enums" () OPE2_ f-ope2 - ( - "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" - ) -) - -(define-normal-insn-enum insn-ope3 "insn ope enums" () OPE3_ f-ope3 - ( - "00" "01" "02" "03" "04" "05" "06" "07" - ) -) - -(define-normal-insn-enum insn-ope4 "insn ope enums" () OPE4_ f-ope4 - ( - "0" "1" "2" "3" - ) -) - -; int-cc: integer branch conditions -; FIXME: should use die macro or some such -(define-normal-insn-enum int-cc "integer branch cond enums" () ICC_ f-int-cc - ( - "nev" "c" "v" "lt" "eq" "ls" "n" "le" - "ra" "nc" "nv" "ge" "ne" "hi" "p" "gt" - ) -) - -; flt-cc: floating-point/media branch conditions -; FIXME: should use die macro or some such -(define-normal-insn-enum flt-cc "float branch cond enums" () FCC_ f-flt-cc - ("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne" - "eq" "ue" "ge" "uge" "le" "ule" "o" "ra") -) - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -; The PSR. The individual fields are referenced more than the entire -; register, so reference them directly. We can assemble the -; entire register contents when necessary. -; -(dsh h-psr_imple "PSR.IMPLE" () (register UQI)) -(dsh h-psr_ver "PSR.VER" () (register UQI)) -(dsh h-psr_ice "PSR.ICE bit" () (register BI)) -(dsh h-psr_nem "PSR.NEM bit" () (register BI)) -(dsh h-psr_cm "PSR.CM bit" () (register BI)) -(dsh h-psr_be "PSR.BE bit" () (register BI)) -(dsh h-psr_esr "PSR.ESR bit" () (register BI)) -(dsh h-psr_ef "PSR.EF bit" () (register BI)) -(dsh h-psr_em "PSR.EM bit" () (register BI)) -(dsh h-psr_pil "PSR.PIL " () (register UQI)) -(dsh h-psr_ps "PSR.PS bit" () (register BI)) -(dsh h-psr_et "PSR.ET bit" () (register BI)) - -; PSR.S requires special handling because the shadow registers (SR0-SR4) must -; be switched with GR4-GR7 when changing from user to supervisor mode or -; vice-versa. -(define-hardware - (name h-psr_s) - (comment "PSR.S bit") - (attrs) - (type register BI) - (get) - (set (newval) (c-call VOID "@cpu@_h_psr_s_set_handler" newval)) -) - -; The TBR. The individual bits are referenced more than the entire -; register, so reference them directly. We can assemble the -; entire register contents when necessary. -; -(dsh h-tbr_tba "TBR.TBA" () (register UWI)) -(dsh h-tbr_tt "TBR.TT" () (register UQI)) - -; The BPSR. The individual bits are referenced more than the entire -; register, so reference them directly. We can assemble the -; entire register contents when necessary. -; -(dsh h-bpsr_bs "PSR.S bit" () (register BI)) -(dsh h-bpsr_bet "PSR.ET bit" () (register BI)) - -; General registers -; -(define-keyword - (name gr-names) - (print-name h-gr) - (prefix "") - (values - (sp 1) (fp 2) - (gr0 0)(gr1 1)(gr2 2)(gr3 3)(gr4 4)(gr5 5)(gr6 6)(gr7 7) - (gr8 8)(gr9 9)(gr10 10)(gr11 11)(gr12 12)(gr13 13)(gr14 14)(gr15 15) - (gr16 16)(gr17 17)(gr18 18)(gr19 19)(gr20 20)(gr21 21)(gr22 22)(gr23 23) - (gr24 24)(gr25 25)(gr26 26)(gr27 27)(gr28 28)(gr29 29)(gr30 30)(gr31 31) - (gr32 32)(gr33 33)(gr34 34)(gr35 35)(gr36 36)(gr37 37)(gr38 38)(gr39 39) - (gr40 40)(gr41 41)(gr42 42)(gr43 43)(gr44 44)(gr45 45)(gr46 46)(gr47 47) - (gr48 48)(gr49 49)(gr50 50)(gr51 51)(gr52 52)(gr53 53)(gr54 54)(gr55 55) - (gr56 56)(gr57 57)(gr58 58)(gr59 59)(gr60 60)(gr61 61)(gr62 62)(gr63 63) - ) -) - -(define-hardware - (name h-gr) - (comment "general registers") - (attrs PROFILE) - (type register USI (64)) - (indices extern-keyword gr-names) - (get (index) (c-call WI "@cpu@_h_gr_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_gr_set_handler" index newval)) -) - -; General Registers as double words -; These registers are shadowed onto h-gr -(define-hardware - (name h-gr_double) - (comment "general registers as double words") - (attrs PROFILE VIRTUAL) - (type register DI (32)) - ; FIXME: Need constraint to prohibit odd numbers. - (indices extern-keyword gr-names) - (get (index) - (c-call DI "@cpu@_h_gr_double_get_handler" index)) - (set (index newval) - (c-call VOID "@cpu@_h_gr_double_set_handler" index newval)) -) - -; General Registers as high and low half words -; These registers are shadowed onto h-gr -(define-hardware - (name h-gr_hi) - (comment "general registers as high half word") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword gr-names) - (get (index) (c-call UHI "@cpu@_h_gr_hi_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_gr_hi_set_handler" index newval)) -) -(define-hardware - (name h-gr_lo) - (comment "general registers as low half word") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword gr-names) - (get (index) (c-call UHI "@cpu@_h_gr_lo_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_gr_lo_set_handler" index newval)) -) - -; Floating Point Registers -(define-keyword - (name fr-names) - (print-name h-fr) - (prefix "") - (values - (fr0 0)(fr1 1)(fr2 2)(fr3 3)(fr4 4)(fr5 5)(fr6 6)(fr7 7) - (fr8 8)(fr9 9)(fr10 10)(fr11 11)(fr12 12)(fr13 13)(fr14 14)(fr15 15) - (fr16 16)(fr17 17)(fr18 18)(fr19 19)(fr20 20)(fr21 21)(fr22 22)(fr23 23) - (fr24 24)(fr25 25)(fr26 26)(fr27 27)(fr28 28)(fr29 29)(fr30 30)(fr31 31) - (fr32 32)(fr33 33)(fr34 34)(fr35 35)(fr36 36)(fr37 37)(fr38 38)(fr39 39) - (fr40 40)(fr41 41)(fr42 42)(fr43 43)(fr44 44)(fr45 45)(fr46 46)(fr47 47) - (fr48 48)(fr49 49)(fr50 50)(fr51 51)(fr52 52)(fr53 53)(fr54 54)(fr55 55) - (fr56 56)(fr57 57)(fr58 58)(fr59 59)(fr60 60)(fr61 61)(fr62 62)(fr63 63) - ) -) - -(define-hardware - (name h-fr) - (comment "floating point registers") - (attrs PROFILE) - (type register SF (64)) - (indices extern-keyword fr-names) - (get (index) (c-call SF "@cpu@_h_fr_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_fr_set_handler" index newval)) -) - -; Floating Point Registers as double precision -; These registers are shadowed onto h-fr - -(define-hardware - (name h-fr_double) - (comment "floating point registers as double precision") - (attrs PROFILE VIRTUAL) - (type register DF (32)) - ; FIXME: Need constraint to prohibit odd numbers. - (indices extern-keyword fr-names) - (get (index) - (c-call DF "@cpu@_h_fr_double_get_handler" index)) - (set (index newval) - (c-call VOID "@cpu@_h_fr_double_set_handler" index newval)) -) - -; Floating Point Registers as integer words. -; These registers are shadowed onto h-fr - -(define-hardware - (name h-fr_int) - (comment "floating point registers as integers") - (attrs PROFILE VIRTUAL) - (type register USI (64)) - (indices extern-keyword fr-names) - (get (index) - (c-call USI "@cpu@_h_fr_int_get_handler" index)) - (set (index newval) - (c-call VOID "@cpu@_h_fr_int_set_handler" index newval)) -) - -; Floating Point Registers as high and low half words -; These registers are shadowed onto h-fr -(define-hardware - (name h-fr_hi) - (comment "floating point registers as unsigned high half word") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword fr-names) - (get (regno) (srl (reg h-fr_int regno) 16)) - (set (regno newval) (set (reg h-fr_int regno) - (or (and (reg h-fr_int regno) #xffff) - (sll newval 16)))) -) -(define-hardware - (name h-fr_lo) - (comment "floating point registers as unsigned low half word") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword fr-names) - (get (regno) (and (reg h-fr_int regno) #xffff)) - (set (regno newval) (set (reg h-fr_int regno) - (or (and (reg h-fr_int regno) #xffff0000) - (and newval #xffff)))) -) - -; Floating Point Registers as unsigned bytes -; These registers are shadowed onto h-fr -(define-hardware - (name h-fr_0) - (comment "floating point registers as unsigned byte 0") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword fr-names) - (get (regno) (and (reg h-fr_int regno) #xff)) - (set (regno newval) - (sequence () - (if (gt USI newval #xff) - (set newval #xff)) - (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffffff00) - newval)))) -) -(define-hardware - (name h-fr_1) - (comment "floating point registers as unsigned byte 1") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword fr-names) - (get (regno) (and (srl (reg h-fr_int regno) 8) #xff)) - (set (regno newval) - (sequence () - (if (gt USI newval #xff) - (set newval #xff)) - (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffff00ff) - (sll newval 8))))) -) -(define-hardware - (name h-fr_2) - (comment "floating point registers as unsigned byte 2") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword fr-names) - (get (regno) (and (srl (reg h-fr_int regno) 16) #xff)) - (set (regno newval) - (sequence () - (if (gt USI newval #xff) - (set newval #xff)) - (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xff00ffff) - (sll newval 16))))) -) -(define-hardware - (name h-fr_3) - (comment "floating point registers as unsigned byte 3") - (attrs PROFILE VIRTUAL) - (type register UHI (64)) - (indices extern-keyword fr-names) - (get (regno) (and (srl (reg h-fr_int regno) 24) #xff)) - (set (regno newval) - (sequence () - (if (gt USI newval #xff) - (set newval #xff)) - (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #x00ffffff) - (sll newval 24))))) -) -; Coprocessor Registers -; -(define-keyword - (name cpr-names) - (print-name h-cpr) - (prefix "") - (values -(cpr0 0)(cpr1 1)(cpr2 2)(cpr3 3)(cpr4 4)(cpr5 5)(cpr6 6)(cpr7 7) -(cpr8 8)(cpr9 9)(cpr10 10)(cpr11 11)(cpr12 12)(cpr13 13)(cpr14 14)(cpr15 15) -(cpr16 16)(cpr17 17)(cpr18 18)(cpr19 19)(cpr20 20)(cpr21 21)(cpr22 22)(cpr23 23) -(cpr24 24)(cpr25 25)(cpr26 26)(cpr27 27)(cpr28 28)(cpr29 29)(cpr30 30)(cpr31 31) -(cpr32 32)(cpr33 33)(cpr34 34)(cpr35 35)(cpr36 36)(cpr37 37)(cpr38 38)(cpr39 39) -(cpr40 40)(cpr41 41)(cpr42 42)(cpr43 43)(cpr44 44)(cpr45 45)(cpr46 46)(cpr47 47) -(cpr48 48)(cpr49 49)(cpr50 50)(cpr51 51)(cpr52 52)(cpr53 53)(cpr54 54)(cpr55 55) -(cpr56 56)(cpr57 57)(cpr58 58)(cpr59 59)(cpr60 60)(cpr61 61)(cpr62 62)(cpr63 63) - ) -) - -(define-hardware - (name h-cpr) - (comment "coprocessor registers") - (attrs PROFILE (MACH frv)) - (type register WI (64)) - (indices extern-keyword cpr-names) -) - -; Coprocessor Registers as double words -; These registers are shadowed onto h-cpr -(define-hardware - (name h-cpr_double) - (comment "coprocessor registers as double words") - (attrs PROFILE VIRTUAL (MACH frv)) - (type register DI (32)) - ; FIXME: Need constraint to prohibit odd numbers. - (indices extern-keyword cpr-names) - (get (index) - (c-call DI "@cpu@_h_cpr_double_get_handler" index)) - (set (index newval) - (c-call VOID "@cpu@_h_cpr_double_set_handler" index newval)) -) - -; Special Purpose Registers -; -(define-keyword - (name spr-names) - (print-name h-spr) - (prefix "") - (values - (psr 0) (pcsr 1) (bpcsr 2) (tbr 3) (bpsr 4) - - (hsr0 16) (hsr1 17) (hsr2 18) (hsr3 19) - (hsr4 20) (hsr5 21) (hsr6 22) (hsr7 23) - (hsr8 24) (hsr9 25) (hsr10 26) (hsr11 27) - (hsr12 28) (hsr13 29) (hsr14 30) (hsr15 31) - (hsr16 32) (hsr17 33) (hsr18 34) (hsr19 35) - (hsr20 36) (hsr21 37) (hsr22 38) (hsr23 39) - (hsr24 40) (hsr25 41) (hsr26 42) (hsr27 43) - (hsr28 44) (hsr29 45) (hsr30 46) (hsr31 47) - (hsr32 48) (hsr33 49) (hsr34 50) (hsr35 51) - (hsr36 52) (hsr37 53) (hsr38 54) (hsr39 55) - (hsr40 56) (hsr41 57) (hsr42 58) (hsr43 59) - (hsr44 60) (hsr45 61) (hsr46 62) (hsr47 63) - (hsr48 64) (hsr49 65) (hsr50 66) (hsr51 67) - (hsr52 68) (hsr53 69) (hsr54 70) (hsr55 71) - (hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75) - (hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79) - - (ccr 256) (cccr 263) (lr 272) (lcr 273) (iacc0h 280) (iacc0l 281) (isr 288) - - (neear0 352) (neear1 353) (neear2 354) (neear3 355) - (neear4 356) (neear5 357) (neear6 358) (neear7 359) - (neear8 360) (neear9 361) (neear10 362) (neear11 363) - (neear12 364) (neear13 365) (neear14 366) (neear15 367) - (neear16 368) (neear17 369) (neear18 370) (neear19 371) - (neear20 372) (neear21 373) (neear22 374) (neear23 375) - (neear24 376) (neear25 377) (neear26 378) (neear27 379) - (neear28 380) (neear29 381) (neear30 382) (neear31 383) - - (nesr0 384) (nesr1 385) (nesr2 386) (nesr3 387) - (nesr4 388) (nesr5 389) (nesr6 390) (nesr7 391) - (nesr8 392) (nesr9 393) (nesr10 394) (nesr11 395) - (nesr12 396) (nesr13 397) (nesr14 398) (nesr15 399) - (nesr16 400) (nesr17 401) (nesr18 402) (nesr19 403) - (nesr20 404) (nesr21 405) (nesr22 406) (nesr23 407) - (nesr24 408) (nesr25 409) (nesr26 410) (nesr27 411) - (nesr28 412) (nesr29 413) (nesr30 414) (nesr31 415) - - (necr 416) - - (gner0 432) (gner1 433) - - (fner0 434) (fner1 435) - - (epcr0 512) (epcr1 513) (epcr2 514) (epcr3 515) - (epcr4 516) (epcr5 517) (epcr6 518) (epcr7 519) - (epcr8 520) (epcr9 521) (epcr10 522) (epcr11 523) - (epcr12 524) (epcr13 525) (epcr14 526) (epcr15 527) - (epcr16 528) (epcr17 529) (epcr18 530) (epcr19 531) - (epcr20 532) (epcr21 533) (epcr22 534) (epcr23 535) - (epcr24 536) (epcr25 537) (epcr26 538) (epcr27 539) - (epcr28 540) (epcr29 541) (epcr30 542) (epcr31 543) - (epcr32 544) (epcr33 545) (epcr34 546) (epcr35 547) - (epcr36 548) (epcr37 549) (epcr38 550) (epcr39 551) - (epcr40 552) (epcr41 553) (epcr42 554) (epcr43 555) - (epcr44 556) (epcr45 557) (epcr46 558) (epcr47 559) - (epcr48 560) (epcr49 561) (epcr50 562) (epcr51 563) - (epcr52 564) (epcr53 565) (epcr54 566) (epcr55 567) - (epcr56 568) (epcr57 569) (epcr58 570) (epcr59 571) - (epcr60 572) (epcr61 573) (epcr62 574) (epcr63 575) - - (esr0 576) (esr1 577) (esr2 578) (esr3 579) - (esr4 580) (esr5 581) (esr6 582) (esr7 583) - (esr8 584) (esr9 585) (esr10 586) (esr11 587) - (esr12 588) (esr13 589) (esr14 590) (esr15 591) - (esr16 592) (esr17 593) (esr18 594) (esr19 595) - (esr20 596) (esr21 597) (esr22 598) (esr23 599) - (esr24 600) (esr25 601) (esr26 602) (esr27 603) - (esr28 604) (esr29 605) (esr30 606) (esr31 607) - (esr32 608) (esr33 609) (esr34 610) (esr35 611) - (esr36 612) (esr37 613) (esr38 614) (esr39 615) - (esr40 616) (esr41 617) (esr42 618) (esr43 619) - (esr44 620) (esr45 621) (esr46 622) (esr47 623) - (esr48 624) (esr49 625) (esr50 626) (esr51 627) - (esr52 628) (esr53 629) (esr54 630) (esr55 631) - (esr56 632) (esr57 633) (esr58 634) (esr59 635) - (esr60 636) (esr61 637) (esr62 638) (esr63 639) - - (eir0 640) (eir1 641) (eir2 642) (eir3 643) - (eir4 644) (eir5 645) (eir6 646) (eir7 647) - (eir8 648) (eir9 649) (eir10 650) (eir11 651) - (eir12 652) (eir13 653) (eir14 654) (eir15 655) - (eir16 656) (eir17 657) (eir18 658) (eir19 659) - (eir20 660) (eir21 661) (eir22 662) (eir23 663) - (eir24 664) (eir25 665) (eir26 666) (eir27 667) - (eir28 668) (eir29 669) (eir30 670) (eir31 671) - - (esfr0 672) (esfr1 673) - - (sr0 768) (sr1 769) (sr2 770) (sr3 771) - - (scr0 832) (scr1 833) (scr2 834) (scr3 835) - - (fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027) - (fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031) - (fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035) - (fsr12 1036) (fsr13 1037) (fsr14 1038) (fsr15 1039) - (fsr16 1040) (fsr17 1041) (fsr18 1042) (fsr19 1043) - (fsr20 1044) (fsr21 1045) (fsr22 1046) (fsr23 1047) - (fsr24 1048) (fsr25 1049) (fsr26 1050) (fsr27 1051) - (fsr28 1052) (fsr29 1053) (fsr30 1054) (fsr31 1055) - (fsr32 1056) (fsr33 1057) (fsr34 1058) (fsr35 1059) - (fsr36 1060) (fsr37 1061) (fsr38 1062) (fsr39 1063) - (fsr40 1064) (fsr41 1065) (fsr42 1066) (fsr43 1067) - (fsr44 1068) (fsr45 1069) (fsr46 1070) (fsr47 1071) - (fsr48 1072) (fsr49 1073) (fsr50 1074) (fsr51 1075) - (fsr52 1076) (fsr53 1077) (fsr54 1078) (fsr55 1079) - (fsr56 1080) (fsr57 1081) (fsr58 1082) (fsr59 1083) - (fsr60 1084) (fsr61 1085) (fsr62 1086) (fsr63 1087) - - ; FQ0-FQ31 are 64 bit registers. - ; These names allow access to the upper 32 bits of the FQ registers. - (fqop0 1088) (fqop1 1090) (fqop2 1092) (fqop3 1094) - (fqop4 1096) (fqop5 1098) (fqop6 1100) (fqop7 1102) - (fqop8 1104) (fqop9 1106) (fqop10 1108) (fqop11 1110) - (fqop12 1112) (fqop13 1114) (fqop14 1116) (fqop15 1118) - (fqop16 1120) (fqop17 1122) (fqop18 1124) (fqop19 1126) - (fqop20 1128) (fqop21 1130) (fqop22 1132) (fqop23 1134) - (fqop24 1136) (fqop25 1138) (fqop26 1140) (fqop27 1142) - (fqop28 1144) (fqop29 1146) (fqop30 1148) (fqop31 1150) - ; These names allow access to the lower 32 bits of the FQ registers. - (fqst0 1089) (fqst1 1091) (fqst2 1093) (fqst3 1095) - (fqst4 1097) (fqst5 1099) (fqst6 1101) (fqst7 1103) - (fqst8 1105) (fqst9 1107) (fqst10 1109) (fqst11 1111) - (fqst12 1113) (fqst13 1115) (fqst14 1117) (fqst15 1119) - (fqst16 1121) (fqst17 1123) (fqst18 1125) (fqst19 1127) - (fqst20 1129) (fqst21 1131) (fqst22 1133) (fqst23 1135) - (fqst24 1137) (fqst25 1139) (fqst26 1141) (fqst27 1143) - (fqst28 1145) (fqst29 1147) (fqst30 1149) (fqst31 1151) - ; These also access the lower 32 bits of the FQ registers. - ; These are not accessible as spr registers (see LSI appendix - section 13.4) -; (fq0 1089) (fq1 1091) (fq2 1093) (fq3 1095) -; (fq4 1097) (fq5 1099) (fq6 1101) (fq7 1103) -; (fq8 1105) (fq9 1107) (fq10 1109) (fq11 1111) -; (fq12 1113) (fq13 1115) (fq14 1117) (fq15 1119) -; (fq16 1121) (fq17 1123) (fq18 1125) (fq19 1127) -; (fq20 1129) (fq21 1131) (fq22 1133) (fq23 1135) -; (fq24 1137) (fq25 1139) (fq26 1141) (fq27 1143) -; (fq28 1145) (fq29 1147) (fq30 1149) (fq31 1151) - - (mcilr0 1272) (mcilr1 1273) - - (msr0 1280) (msr1 1281) (msr2 1282) (msr3 1283) - (msr4 1284) (msr5 1285) (msr6 1286) (msr7 1287) - (msr8 1288) (msr9 1289) (msr10 1290) (msr11 1291) - (msr12 1292) (msr13 1293) (msr14 1294) (msr15 1295) - (msr16 1296) (msr17 1297) (msr18 1298) (msr19 1299) - (msr20 1300) (msr21 1301) (msr22 1302) (msr23 1303) - (msr24 1304) (msr25 1305) (msr26 1306) (msr27 1307) - (msr28 1308) (msr29 1309) (msr30 1310) (msr31 1311) - (msr32 1312) (msr33 1313) (msr34 1314) (msr35 1315) - (msr36 1316) (msr37 1317) (msr38 1318) (msr39 1319) - (msr40 1320) (msr41 1321) (msr42 1322) (msr43 1323) - (msr44 1324) (msr45 1325) (msr46 1326) (msr47 1327) - (msr48 1328) (msr49 1329) (msr50 1330) (msr51 1331) - (msr52 1332) (msr53 1333) (msr54 1334) (msr55 1335) - (msr56 1336) (msr57 1337) (msr58 1338) (msr59 1339) - (msr60 1340) (msr61 1341) (msr62 1342) (msr63 1343) - - ; MQ0-MQ31 are 64 bit registers. - ; These names allow access to the upper 32 bits of the MQ registers. - (mqop0 1344) (mqop1 1346) (mqop2 1348) (mqop3 1350) - (mqop4 1352) (mqop5 1354) (mqop6 1356) (mqop7 1358) - (mqop8 1360) (mqop9 1362) (mqop10 1364) (mqop11 1366) - (mqop12 1368) (mqop13 1370) (mqop14 1372) (mqop15 1374) - (mqop16 1376) (mqop17 1378) (mqop18 1380) (mqop19 1382) - (mqop20 1384) (mqop21 1386) (mqop22 1388) (mqop23 1390) - (mqop24 1392) (mqop25 1394) (mqop26 1396) (mqop27 1398) - (mqop28 1400) (mqop29 1402) (mqop30 1404) (mqop31 1406) - ; These names allow access to the lower 32 bits of the MQ registers. - (mqst0 1345) (mqst1 1347) (mqst2 1349) (mqst3 1351) - (mqst4 1353) (mqst5 1355) (mqst6 1357) (mqst7 1359) - (mqst8 1361) (mqst9 1363) (mqst10 1365) (mqst11 1367) - (mqst12 1369) (mqst13 1371) (mqst14 1373) (mqst15 1375) - (mqst16 1377) (mqst17 1379) (mqst18 1381) (mqst19 1383) - (mqst20 1385) (mqst21 1387) (mqst22 1389) (mqst23 1391) - (mqst24 1393) (mqst25 1395) (mqst26 1397) (mqst27 1399) - (mqst28 1401) (mqst29 1403) (mqst30 1405) (mqst31 1407) - ; These also access the lower 32 bits of the MQ registers. - ; These are not accessible as spr registers (see LSI appendix - section 13.4) -; (mq0 1345) (mq1 1347) (mq2 1349) (mq3 1351) -; (mq4 1353) (mq5 1355) (mq6 1357) (mq7 1359) -; (mq8 1361) (mq9 1363) (mq10 1365) (mq11 1367) -; (mq12 1369) (mq13 1371) (mq14 1373) (mq15 1375) -; (mq16 1377) (mq17 1379) (mq18 1381) (mq19 1383) -; (mq20 1385) (mq21 1387) (mq22 1389) (mq23 1391) -; (mq24 1393) (mq25 1395) (mq26 1397) (mq27 1399) -; (mq28 1401) (mq29 1403) (mq30 1405) (mq31 1407) - - ; These are not accessible as spr registers (see LSI appendix - section 13.4) -; (acc0 1408) (acc1 1409) (acc2 1410) (acc3 1411) -; (acc4 1412) (acc5 1413) (acc6 1414) (acc7 1415) -; (acc8 1416) (acc9 1417) (acc10 1418) (acc11 1419) -; (acc12 1420) (acc13 1421) (acc14 1422) (acc15 1423) -; (acc16 1424) (acc17 1425) (acc18 1426) (acc19 1427) -; (acc20 1428) (acc21 1429) (acc22 1430) (acc23 1431) -; (acc24 1432) (acc25 1433) (acc26 1434) (acc27 1435) -; (acc28 1436) (acc29 1437) (acc30 1438) (acc31 1439) -; (acc32 1440) (acc33 1441) (acc34 1442) (acc35 1443) -; (acc36 1444) (acc37 1445) (acc38 1446) (acc39 1447) -; (acc40 1448) (acc41 1449) (acc42 1450) (acc43 1451) -; (acc44 1452) (acc45 1453) (acc46 1454) (acc47 1455) -; (acc48 1456) (acc49 1457) (acc50 1458) (acc51 1459) -; (acc52 1460) (acc53 1461) (acc54 1462) (acc55 1463) -; (acc56 1464) (acc57 1465) (acc58 1466) (acc59 1467) -; (acc60 1468) (acc61 1469) (acc62 1470) (acc63 1471) - -; (accg0 1472) (accg1 1473) (accg2 1474) (accg3 1475) -; (accg4 1476) (accg5 1477) (accg6 1478) (accg7 1479) -; (accg8 1480) (accg9 1481) (accg10 1482) (accg11 1483) -; (accg12 1484) (accg13 1485) (accg14 1486) (accg15 1487) -; (accg16 1488) (accg17 1489) (accg18 1490) (accg19 1491) -; (accg20 1492) (accg21 1493) (accg22 1494) (accg23 1495) -; (accg24 1496) (accg25 1497) (accg26 1498) (accg27 1499) -; (accg28 1500) (accg29 1501) (accg30 1502) (accg31 1503) -; (accg32 1504) (accg33 1505) (accg34 1506) (accg35 1507) -; (accg36 1508) (accg37 1509) (accg38 1510) (accg39 1511) -; (accg40 1512) (accg41 1513) (accg42 1514) (accg43 1515) -; (accg44 1516) (accg45 1517) (accg46 1518) (accg47 1519) -; (accg48 1520) (accg49 1521) (accg50 1522) (accg51 1523) -; (accg52 1524) (accg53 1525) (accg54 1526) (accg55 1527) -; (accg56 1528) (accg57 1529) (accg58 1530) (accg59 1531) -; (accg60 1532) (accg61 1533) (accg62 1534) (accg63 1535) - - (ear0 1536) (ear1 1537) (ear2 1538) (ear3 1539) - (ear4 1540) (ear5 1541) (ear6 1542) (ear7 1543) - (ear8 1544) (ear9 1545) (ear10 1546) (ear11 1547) - (ear12 1548) (ear13 1549) (ear14 1550) (ear15 1551) - (ear16 1552) (ear17 1553) (ear18 1554) (ear19 1555) - (ear20 1556) (ear21 1557) (ear22 1558) (ear23 1559) - (ear24 1560) (ear25 1561) (ear26 1562) (ear27 1563) - (ear28 1564) (ear29 1565) (ear30 1566) (ear31 1567) - (ear32 1568) (ear33 1569) (ear34 1570) (ear35 1571) - (ear36 1572) (ear37 1573) (ear38 1574) (ear39 1575) - (ear40 1576) (ear41 1577) (ear42 1578) (ear43 1579) - (ear44 1580) (ear45 1581) (ear46 1582) (ear47 1583) - (ear48 1584) (ear49 1585) (ear50 1586) (ear51 1587) - (ear52 1588) (ear53 1589) (ear54 1590) (ear55 1591) - (ear56 1592) (ear57 1593) (ear58 1594) (ear59 1595) - (ear60 1596) (ear61 1597) (ear62 1598) (ear63 1599) - - (edr0 1600) (edr1 1601) (edr2 1602) (edr3 1603) - (edr4 1604) (edr5 1605) (edr6 1606) (edr7 1607) - (edr8 1608) (edr9 1609) (edr10 1610) (edr11 1611) - (edr12 1612) (edr13 1613) (edr14 1614) (edr15 1615) - (edr16 1616) (edr17 1617) (edr18 1618) (edr19 1619) - (edr20 1620) (edr21 1621) (edr22 1622) (edr23 1623) - (edr24 1624) (edr25 1625) (edr26 1626) (edr27 1627) - (edr28 1628) (edr29 1629) (edr30 1630) (edr31 1631) - (edr32 1632) (edr33 1636) (edr34 1634) (edr35 1635) - (edr36 1636) (edr37 1637) (edr38 1638) (edr39 1639) - (edr40 1640) (edr41 1641) (edr42 1642) (edr43 1643) - (edr44 1644) (edr45 1645) (edr46 1646) (edr47 1647) - (edr48 1648) (edr49 1649) (edr50 1650) (edr51 1651) - (edr52 1652) (edr53 1653) (edr54 1654) (edr55 1655) - (edr56 1656) (edr57 1657) (edr58 1658) (edr59 1659) - (edr60 1660) (edr61 1661) (edr62 1662) (edr63 1663) - - (iamlr0 1664) (iamlr1 1665) (iamlr2 1666) (iamlr3 1667) - (iamlr4 1668) (iamlr5 1669) (iamlr6 1670) (iamlr7 1671) - (iamlr8 1672) (iamlr9 1673) (iamlr10 1674) (iamlr11 1675) - (iamlr12 1676) (iamlr13 1677) (iamlr14 1678) (iamlr15 1679) - (iamlr16 1680) (iamlr17 1681) (iamlr18 1682) (iamlr19 1683) - (iamlr20 1684) (iamlr21 1685) (iamlr22 1686) (iamlr23 1687) - (iamlr24 1688) (iamlr25 1689) (iamlr26 1690) (iamlr27 1691) - (iamlr28 1692) (iamlr29 1693) (iamlr30 1694) (iamlr31 1695) - (iamlr32 1696) (iamlr33 1697) (iamlr34 1698) (iamlr35 1699) - (iamlr36 1700) (iamlr37 1701) (iamlr38 1702) (iamlr39 1703) - (iamlr40 1704) (iamlr41 1705) (iamlr42 1706) (iamlr43 1707) - (iamlr44 1708) (iamlr45 1709) (iamlr46 1710) (iamlr47 1711) - (iamlr48 1712) (iamlr49 1713) (iamlr50 1714) (iamlr51 1715) - (iamlr52 1716) (iamlr53 1717) (iamlr54 1718) (iamlr55 1719) - (iamlr56 1720) (iamlr57 1721) (iamlr58 1722) (iamlr59 1723) - (iamlr60 1724) (iamlr61 1725) (iamlr62 1726) (iamlr63 1727) - - (iampr0 1728) (iampr1 1729) (iampr2 1730) (iampr3 1731) - (iampr4 1732) (iampr5 1733) (iampr6 1734) (iampr7 1735) - (iampr8 1736) (iampr9 1737) (iampr10 1738) (iampr11 1739) - (iampr12 1740) (iampr13 1741) (iampr14 1742) (iampr15 1743) - (iampr16 1744) (iampr17 1745) (iampr18 1746) (iampr19 1747) - (iampr20 1748) (iampr21 1749) (iampr22 1750) (iampr23 1751) - (iampr24 1752) (iampr25 1753) (iampr26 1754) (iampr27 1755) - (iampr28 1756) (iampr29 1757) (iampr30 1758) (iampr31 1759) - (iampr32 1760) (iampr33 1761) (iampr34 1762) (iampr35 1763) - (iampr36 1764) (iampr37 1765) (iampr38 1766) (iampr39 1767) - (iampr40 1768) (iampr41 1769) (iampr42 1770) (iampr43 1771) - (iampr44 1772) (iampr45 1773) (iampr46 1774) (iampr47 1775) - (iampr48 1776) (iampr49 1777) (iampr50 1778) (iampr51 1779) - (iampr52 1780) (iampr53 1781) (iampr54 1782) (iampr55 1783) - (iampr56 1784) (iampr57 1785) (iampr58 1786) (iampr59 1787) - (iampr60 1788) (iampr61 1789) (iampr62 1790) (iampr63 1791) - - (damlr0 1792) (damlr1 1793) (damlr2 1794) (damlr3 1795) - (damlr4 1796) (damlr5 1797) (damlr6 1798) (damlr7 1799) - (damlr8 1800) (damlr9 1801) (damlr10 1802) (damlr11 1803) - (damlr12 1804) (damlr13 1805) (damlr14 1806) (damlr15 1807) - (damlr16 1808) (damlr17 1809) (damlr18 1810) (damlr19 1811) - (damlr20 1812) (damlr21 1813) (damlr22 1814) (damlr23 1815) - (damlr24 1816) (damlr25 1817) (damlr26 1818) (damlr27 1819) - (damlr28 1820) (damlr29 1821) (damlr30 1822) (damlr31 1823) - (damlr32 1824) (damlr33 1825) (damlr34 1826) (damlr35 1827) - (damlr36 1828) (damlr37 1829) (damlr38 1830) (damlr39 1831) - (damlr40 1832) (damlr41 1833) (damlr42 1834) (damlr43 1835) - (damlr44 1836) (damlr45 1837) (damlr46 1838) (damlr47 1839) - (damlr48 1840) (damlr49 1841) (damlr50 1842) (damlr51 1843) - (damlr52 1844) (damlr53 1845) (damlr54 1846) (damlr55 1847) - (damlr56 1848) (damlr57 1849) (damlr58 1850) (damlr59 1851) - (damlr60 1852) (damlr61 1853) (damlr62 1854) (damlr63 1855) - - (dampr0 1856) (dampr1 1857) (dampr2 1858) (dampr3 1859) - (dampr4 1860) (dampr5 1861) (dampr6 1862) (dampr7 1863) - (dampr8 1864) (dampr9 1865) (dampr10 1866) (dampr11 1867) - (dampr12 1868) (dampr13 1869) (dampr14 1870) (dampr15 1871) - (dampr16 1872) (dampr17 1873) (dampr18 1874) (dampr19 1875) - (dampr20 1876) (dampr21 1877) (dampr22 1878) (dampr23 1879) - (dampr24 1880) (dampr25 1881) (dampr26 1882) (dampr27 1883) - (dampr28 1884) (dampr29 1885) (dampr30 1886) (dampr31 1887) - (dampr32 1888) (dampr33 1889) (dampr34 1890) (dampr35 1891) - (dampr36 1892) (dampr37 1893) (dampr38 1894) (dampr39 1895) - (dampr40 1896) (dampr41 1897) (dampr42 1898) (dampr43 1899) - (dampr44 1900) (dampr45 1901) (dampr46 1902) (dampr47 1903) - (dampr48 1904) (dampr49 1905) (dampr50 1906) (dampr51 1907) - (dampr52 1908) (dampr53 1909) (dampr54 1910) (dampr55 1911) - (dampr56 1912) (dampr57 1913) (dampr58 1914) (dampr59 1915) - (dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919) - - (amcr 1920) (stbar 1921) (mmcr 1922) - (iamvr1 1925) (damvr1 1927) - (cxnr 1936) (ttbr 1937) (tplr 1938) (tppr 1939) - (tpxr 1940) - (timerh 1952) (timerl 1953) (timerd 1954) - (dcr 2048) (brr 2049) (nmar 2050) (btbr 2051) - - (ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055) - (dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059) - - (dbdr00 2060) (dbdr01 2061) (dbdr02 2062) (dbdr03 2063) - (dbdr10 2064) (dbdr11 2065) (dbdr12 2066) (dbdr13 2067) - (dbdr20 2068) (dbdr21 2069) (dbdr22 2070) (dbdr23 2071) - (dbdr30 2072) (dbdr31 2073) (dbdr32 2074) (dbdr33 2075) - - (dbmr00 2076) (dbmr01 2077) (dbmr02 2078) (dbmr03 2079) - (dbmr10 2080) (dbmr11 2081) (dbmr12 2082) (dbmr13 2083) - (dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087) - (dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091) - - (cpcfr 2304) (cpcr 2305) (cpsr 2306) (cptr 2307) - (cphsr0 2308) (cphsr1 2309) (cpesr0 2320) (cpesr1 2321) - (cpemr0 2322) (cpemr1 2323) - - (iperr0 2324) (iperr1 2325) (ipjsr 2326) (ipjrr 2327) - (ipcsr0 2336) (ipcsr1 2337) (ipcwer0 2338) (ipcwer1 2339) - (ipcwr 2340) - - (mbhsr 2352) (mbssr 2353) (mbrsr 2354) (mbsdr 2355) - (mbrdr 2356) (mbsmr 2357) (mbstr0 2359) (mbstr1 2360) - - (slpr 2368) (sldr 2369) (slhsr 2370) (sltr 2371) - (slwr 2372) - - (ihsr8 3848) (ihsr9 3849) (ihsr10 3850) - ) -) - -(define-hardware - (name h-spr) - (comment "special purpose registers") - (attrs PROFILE) - (type register UWI (4096)) - (indices extern-keyword spr-names) - (get (index) (c-call UWI "@cpu@_h_spr_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_spr_set_handler" index newval)) -) - -(define-pmacro (spr-pcsr) (reg h-spr 1)) -(define-pmacro (spr-bpcsr) (reg h-spr 2)) -(define-pmacro (spr-lr) (reg h-spr 272)) -(define-pmacro (spr-lcr) (reg h-spr 273)) -(define-pmacro (spr-iacc0h) (reg h-spr 280)) -(define-pmacro (spr-iacc0l) (reg h-spr 281)) -(define-pmacro (spr-sr0) (reg h-spr 768)) -(define-pmacro (spr-sr1) (reg h-spr 769)) -(define-pmacro (spr-sr2) (reg h-spr 770)) -(define-pmacro (spr-sr3) (reg h-spr 771)) - -; Accumulator guard. Actually a subset of the SPR registers, but those SPRs -; are read-only in most insns. This hardware element is used by those insns -; which have direct access (mwtaccg, mrdaccg). -(define-keyword - (name accg-names) - (print-name h-accg) - (prefix "") - (values - (accg0 0)(accg1 1)(accg2 2)(accg3 3) - (accg4 4)(accg5 5)(accg6 6)(accg7 7) - (accg8 8)(accg9 9)(accg10 10)(accg11 11) - (accg12 12)(accg13 13)(accg14 14)(accg15 15) - (accg16 16)(accg17 17)(accg18 18)(accg19 19) - (accg20 20)(accg21 21)(accg22 22)(accg23 23) - (accg24 24)(accg25 25)(accg26 26)(accg27 27) - (accg28 28)(accg29 29)(accg30 30)(accg31 31) - (accg32 32)(accg33 33)(accg34 34)(accg35 35) - (accg36 36)(accg37 37)(accg38 38)(accg39 39) - (accg40 40)(accg41 41)(accg42 42)(accg43 43) - (accg44 44)(accg45 45)(accg46 46)(accg47 47) - (accg48 48)(accg49 49)(accg50 50)(accg51 51) - (accg52 52)(accg53 53)(accg54 54)(accg55 55) - (accg56 56)(accg57 57)(accg58 58)(accg59 59) - (accg60 60)(accg61 61)(accg62 62)(accg63 63) - ) -) - -(define-hardware - (name h-accg) - (comment "accumulator guard") - (attrs PROFILE VIRTUAL) - (type register UWI (64)) - (indices extern-keyword accg-names) - (get (index) - (and (reg h-spr (add index 1472)) #xff)) - (set (index newval) - (set (raw-reg UWI h-spr (add index 1472)) (and newval #xff))) -) - -; 40 bit accumulator. Composed of ACCG and ACC registers concatenated, but -; referenced more often as the composed 40 bits. -(define-keyword - (name acc-names) - (print-name h-acc40) - (prefix "") - (values -(acc0 0)(acc1 1)(acc2 2)(acc3 3)(acc4 4)(acc5 5)(acc6 6)(acc7 7) -(acc8 8)(acc9 9)(acc10 10)(acc11 11)(acc12 12)(acc13 13)(acc14 14)(acc15 15) -(acc16 16)(acc17 17)(acc18 18)(acc19 19)(acc20 20)(acc21 21)(acc22 22)(acc23 23) -(acc24 24)(acc25 25)(acc26 26)(acc27 27)(acc28 28)(acc29 29)(acc30 30)(acc31 31) -(acc32 32)(acc33 33)(acc34 34)(acc35 35)(acc36 36)(acc37 37)(acc38 38)(acc39 39) -(acc40 40)(acc41 41)(acc42 42)(acc43 43)(acc44 44)(acc45 45)(acc46 46)(acc47 47) -(acc48 48)(acc49 49)(acc50 50)(acc51 51)(acc52 52)(acc53 53)(acc54 54)(acc55 55) -(acc56 56)(acc57 57)(acc58 58)(acc59 59)(acc60 60)(acc61 61)(acc62 62)(acc63 63) - ) -) - -(define-hardware - (name h-acc40S) - (comment "40 bit signed accumulator") - (attrs PROFILE VIRTUAL) - (type register DI (64)) - (indices extern-keyword acc-names) - ; The accumlator is made up of two 32 bit registers, accgi/acci. - ; We want to extract this as a combined 40 signed bits - (get (index) - (or DI - (sll DI (ext DI (trunc QI (reg h-spr (add index 1472)))) - 32) - (zext DI (reg h-spr (add index 1408))))) - ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions - ; on ACC and ACCG registers - (set (index newval) - (sequence () - (c-call VOID "frv_check_spr_write_access" (add index 1408)) - (set (raw-reg UWI h-spr - (add index 1472)) (and (srl newval 32) #xff)) - (set (raw-reg UWI h-spr - (add index 1408)) (trunc USI newval)))) -) - -(define-hardware - (name h-acc40U) - (comment "40 bit unsigned accumulator") - (attrs PROFILE VIRTUAL) - (type register UDI (64)) - (indices extern-keyword acc-names) - ; The accumlator is made up of two 32 bit registers, accgi/acci. - ; We want to extract this as a combined 40 unsigned bits - (get (index) - (or DI - (sll DI (zext DI (reg h-spr (add index 1472))) 32) - (zext DI (reg h-spr (add index 1408))))) - ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions - ; on ACC and ACCG registers - (set (index newval) - (sequence () - (c-call VOID "frv_check_spr_write_access" (add index 1408)) - (set (raw-reg UWI h-spr - (add index 1472)) (and (srl newval 32) #xff)) - (set (raw-reg UWI h-spr - (add index 1408)) (trunc USI newval)))) -) -; 64-bit signed accumulator. Composed of iacc0h and iacc0l registers -; concatenated, but referenced more often as the composed 64 bits. -(define-keyword - ; This is totally hokey -- I have to have an index! - (name iacc0-names) - (print-name h-iacc0) - (prefix "") - (values (iacc0 0)) -) - -(define-hardware - (name h-iacc0) - (comment "64 bit signed accumulator") - (attrs PROFILE VIRTUAL (MACH fr400,fr450)) - (type register DI (1)) - (indices extern-keyword iacc0-names) - ; The single 64-bit integer accumulator is made up of two 32 bit - ; registers, iacc0h and iacc0l. We want to extract this as a - ; combined 64 signed bits. - (get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l)))) - (set (idx newval) - (sequence () - (set (spr-iacc0h) (trunc SI (srl newval 32))) - (set (spr-iacc0l) (trunc SI newval)))) -) - -; Integer condition code registers (CCR) -; -; The individual sub registers bits of the CCR are referenced more often than -; the entire register so set them directly. We can assemble the -; entire register when necessary. -; -(define-keyword - (name iccr-names) - (print-name h-iccr) - (prefix "") - (values (icc0 0) (icc1 1) (icc2 2) (icc3 3)) -) - -(define-hardware - (name h-iccr) - (comment "Integer condition code registers") - (attrs PROFILE) - (type register UQI (4)) - (indices extern-keyword iccr-names) -) - -; Floating point condition code registers (CCR) -; -; The individual sub registers bits of the CCR are referenced more often than -; the entire register so set them directly. We can assemble the -; entire register when necessary. -; -(define-keyword - (name fccr-names) - (print-name h-fccr) - (prefix "") - (values (fcc0 0) (fcc1 1) (fcc2 2) (fcc3 3)) -) - -(define-hardware - (name h-fccr) - (comment "Floating point condition code registers") - (attrs PROFILE) - (type register UQI (4)) - (indices extern-keyword fccr-names) -) - -; C condition code registers (CCCR) -; -(define-keyword - (name cccr-names) - (print-name h-cccr) - (prefix "") - (values (cc0 0) (cc1 1) (cc2 2) (cc3 3) (cc4 4) (cc5 5) (cc6 6) (cc7 7)) -) - -(define-hardware - (name h-cccr) - (comment "Condition code registers") - (attrs PROFILE) - (type register UQI (8)) - (indices extern-keyword cccr-names) -) - -; Dummy hardware used to define packing bit on insns -; -(define-hardware - (name h-pack) - (comment "Packing bit dummy hardware") - (type immediate (UINT 1)) - (values keyword "" (("" 1) (".p" 0) (".P" 0))) -) -; Dummy hardware used to define hint field for branches always taken -; -(define-hardware - (name h-hint-taken) - (comment "Branch taken hint dummy hardware") - (type immediate (UINT 1)) - ; The order of these is important. We want '2' to get written by default, - ; but we also want the docoder/disassembler to allow the values '0', '1' and - ; '3'. - (values keyword "" (("" 2) ("" 0) ("" 1) ("" 3))) -) -; Dummy hardware used to define hint field for branches never taken -; -(define-hardware - (name h-hint-not-taken) - (comment "Branch not taken hint dummy hardware") - (type immediate (UINT 1)) - ; The order of these is important. We want '0' to get written by default, - ; but we also want the docoder/disassembler to allow the values '1', '2' and - ; '3'. - (values keyword "" (("" 0) ("" 1) ("" 2) ("" 3))) -) - -; Instruction Operands. -; These entries provide a layer between the assembler and the raw hardware -; description, and are used to refer to hardware elements in the semantic -; code. Usually there's a bit of over-specification, but in more complicated -; instruction sets there isn't. - -; FRV specific operand attributes: - -(define-attr - (for operand) - (type boolean) - (name HASH-PREFIX) - (comment "immediates have an optional '#' prefix") -) - -; ??? Convention says this should be o-sr, but then the insn definitions -; should refer to o-sr which is clumsy. The "o-" could be implicit, but -; then it should be implicit for all the symbols here, but then there would -; be confusion between (f-)simm8 and (h-)simm8. -; So for now the rule is exactly as it appears here. - -; dnmop: define-normal-mode-operand: temporary, pending potential removal -; of modes from h/w. -(define-pmacro (dnmop xname xcomment xattrs xtype xindex xmode) - (define-operand - (name xname) - (comment xcomment) - (.splice attrs (.unsplice xattrs)) - (type xtype) - (index xindex) - (mode xmode) - ) -) - -; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler -(define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse) - (define-operand - (name xname) - (comment xcomment) - (.splice attrs (.unsplice xattrs)) - (type xtype) - (index xindex) - (mode xmode) - (handlers (parse xparse)) - ) -) - -(dnop pack "packing bit" () h-pack f-pack) - -(dnmop GRi "source register 1" () h-gr f-GRi SI) -(dnmop GRj "source register 2" () h-gr f-GRj SI) -(dnmop GRk "destination register" () h-gr f-GRk SI) -(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI) -(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI) -(dnpmop GRdoublek "destination register" () h-gr_double f-GRk DI "even_register") -(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI) -(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI) -(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI) -(dnmop ACC40Uk "target accumulator" () h-acc40U f-ACC40Uk UDI) -(dnmop ACCGi "source register" () h-accg f-ACCGi UWI) -(dnmop ACCGk "target register" () h-accg f-ACCGk UWI) - -(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI) -(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI) -(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI) -(dnpmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI "even_register") - -; floating point operands -(dnmop FRinti "source register 1" () h-fr_int f-FRi SI) -(dnmop FRintj "source register 2" () h-fr_int f-FRj SI) -(dnmop FRintk "target register" () h-fr_int f-FRk SI) -(dnmop FRi "source register 1" () h-fr f-FRi SF) -(dnmop FRj "source register 2" () h-fr f-FRj SF) -(dnmop FRk "destination register" () h-fr f-FRk SF) -(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI) -(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI) -(dnpmop FRdoublei "source register 1" () h-fr_double f-FRi DF "even_register") -(dnpmop FRdoublej "source register 2" () h-fr_double f-FRj DF "even_register") -(dnpmop FRdoublek "target register" () h-fr_double f-FRk DF "even_register") - -(dnop CRi "source register 1" () h-cccr f-CRi) -(dnop CRj "source register 2" () h-cccr f-CRj) -(dnop CRj_int "destination register" () h-cccr f-CRj_int) -(dnop CRj_float "destination register" () h-cccr f-CRj_float) -(dnop CRk "destination register" () h-cccr f-CRk) -(dnop CCi "condition register" () h-cccr f-CCi) - -(dnop ICCi_1 "condition register" () h-iccr f-ICCi_1) -(dnop ICCi_2 "condition register" () h-iccr f-ICCi_2) -(dnop ICCi_3 "condition register" () h-iccr f-ICCi_3) -(dnop FCCi_1 "condition register" () h-fccr f-FCCi_1) -(dnop FCCi_2 "condition register" () h-fccr f-FCCi_2) -(dnop FCCi_3 "condition register" () h-fccr f-FCCi_3) -(dnop FCCk "condition register" () h-fccr f-FCCk) - -(dnop eir "exception insn reg" () h-uint f-eir) -(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) -(dnop u16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16) -(dnop s16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-s16) -(dnop s6 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6) -(dnop s6_1 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6_1) -(dnop u6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-u6) -(dnop s5 "5 bit signed immediate" (HASH-PREFIX) h-sint f-s5) -(dnop cond "conditional arithmetic" (HASH-PREFIX) h-uint f-cond) -(dnop ccond "lr branch condition" (HASH-PREFIX) h-uint f-ccond) -(dnop hint "2 bit branch predictor" (HASH-PREFIX) h-uint f-hint) -(dnop hint_taken "2 bit branch predictor" () h-hint-taken f-hint) -(dnop hint_not_taken "2 bit branch predictor" () h-hint-not-taken f-hint) - -(dnop LI "link indicator" () h-uint f-LI) -(dnop lock "cache lock indicator" (HASH-PREFIX) h-uint f-lock) -(dnop debug "debug mode indicator" (HASH-PREFIX) h-uint f-debug) -(dnop ae "all entries indicator" (HASH-PREFIX) h-uint f-ae) - -(dnop label16 "18 bit pc relative address" () h-iaddr f-label16) - -(dnop LRAE "Load Real Address E flag" () h-uint f-LRAE) -(dnop LRAD "Load Real Address D flag" () h-uint f-LRAD) -(dnop LRAS "Load Real Address S flag" () h-uint f-LRAS) - -(dnop TLBPRopx "TLB Probe operation number" () h-uint f-TLBPRopx) -(dnop TLBPRL "TLB Probe L flag" () h-uint f-TLBPRL) - -(define-operand - (name A0) - (comment "A==0 operand of mclracc") - (attrs) - (type h-uint) - (index f-A) - (mode USI) - (handlers (parse "A0")) -) - -(define-operand - (name A1) - (comment "A==1 operand of mclracc") - (attrs) - (type h-uint) - (index f-A) - (mode USI) - (handlers (parse "A1")) -) - -(define-operand - (name FRintieven) - (comment "(even) source register 1") - (attrs) - (type h-fr_int) - (index f-FRi) - (mode SI) - (handlers (parse "even_register")) -) - -(define-operand - (name FRintjeven) - (comment "(even) source register 2") - (attrs) - (type h-fr_int) - (index f-FRj) - (mode SI) - (handlers (parse "even_register")) -) - -(define-operand - (name FRintkeven) - (comment "(even) target register") - (attrs) - (type h-fr_int) - (index f-FRk) - (mode SI) - (handlers (parse "even_register")) -) - -(define-operand - (name d12) - (comment "12 bit signed immediate") - (attrs) - (type h-sint) - (index f-d12) - (handlers (parse "d12")) -) - -(define-operand - (name s12) - (comment "12 bit signed immediate") - (attrs HASH-PREFIX) - (type h-sint) - (index f-d12) - (handlers (parse "s12")) -) - -(define-operand - (name u12) - (comment "12 bit signed immediate") - (attrs HASH-PREFIX) - (type h-sint) - (index f-u12) - (handlers (parse "u12")) -) - -(define-operand - (name spr) - (comment "special purpose register") - (attrs) - (type h-spr) - (index f-spr) - (handlers (parse "spr") (print "spr")) -) - -(define-operand - (name ulo16) - (comment "16 bit unsigned immediate, for #lo()") - (attrs) - (type h-uint) - (index f-u16) - (handlers (parse "ulo16") (print "lo")) -) - -(define-operand - (name slo16) - (comment "16 bit unsigned immediate, for #lo()") - (attrs) - (type h-sint) - (index f-s16) - (handlers (parse "uslo16") (print "lo")) -) - -(define-operand - (name uhi16) - (comment "16 bit unsigned immediate, for #hi()") - (attrs) - (type h-uint) - (index f-u16) - (handlers (parse "uhi16") (print "hi")) -) - -(define-operand - (name label24) - (comment "26 bit pc relative address") - (attrs) - (type h-iaddr) - (index f-label24) - (mode SI) - (handlers (parse "call_label")) -) - -; operands representing hardware -; -(dnop psr_esr "PSR.ESR bit" (SEM-ONLY) h-psr_esr f-nil) -(dnop psr_s "PSR.S bit" (SEM-ONLY) h-psr_s f-nil) -(dnop psr_ps "PSR.PS bit" (SEM-ONLY) h-psr_ps f-nil) -(dnop psr_et "PSR.ET bit" (SEM-ONLY) h-psr_et f-nil) - -(dnop bpsr_bs "BPSR.BS bit" (SEM-ONLY) h-bpsr_bs f-nil) -(dnop bpsr_bet "BPSR.BET bit" (SEM-ONLY) h-bpsr_bet f-nil) - -(dnop tbr_tba "TBR.TBA" (SEM-ONLY) h-tbr_tba f-nil) -(dnop tbr_tt "TBR.TT" (SEM-ONLY) h-tbr_tt f-nil) - -; Null operands -; -(define-pmacro (ICCi_1-null) (f-ICCi_1-null 0)) -(define-pmacro (ICCi_2-null) (f-ICCi_2-null 0)) -(define-pmacro (ICCi_3-null) (f-ICCi_3-null 0)) -(define-pmacro (FCCi_1-null) (f-FCCi_1-null 0)) -(define-pmacro (FCCi_2-null) (f-FCCi_2-null 0)) -(define-pmacro (FCCi_3-null) (f-FCCi_3-null 0)) -(define-pmacro (rs-null) (f-rs-null 0)) -(define-pmacro (GRi-null) (f-GRi-null 0)) -(define-pmacro (GRj-null) (f-GRj-null 0)) -(define-pmacro (GRk-null) (f-GRk-null 0)) -(define-pmacro (FRi-null) (f-FRi-null 0)) -(define-pmacro (FRj-null) (f-FRj-null 0)) -(define-pmacro (ACCj-null) (f-ACCj-null 0)) -(define-pmacro (rd-null) (f-rd-null 0)) -(define-pmacro (cond-null) (f-cond-null 0)) -(define-pmacro (ccond-null) (f-ccond-null 0)) -(define-pmacro (s12-null) (f-s12-null 0)) -(define-pmacro (label16-null) (f-label16-null 0)) -(define-pmacro (misc-null-1) (f-misc-null-1 0)) -(define-pmacro (misc-null-2) (f-misc-null-2 0)) -(define-pmacro (misc-null-3) (f-misc-null-3 0)) -(define-pmacro (misc-null-4) (f-misc-null-4 0)) -(define-pmacro (misc-null-5) (f-misc-null-5 0)) -(define-pmacro (misc-null-6) (f-misc-null-6 0)) -(define-pmacro (misc-null-7) (f-misc-null-7 0)) -(define-pmacro (misc-null-8) (f-misc-null-8 0)) -(define-pmacro (misc-null-9) (f-misc-null-9 0)) -(define-pmacro (misc-null-10) (f-misc-null-10 0)) -(define-pmacro (misc-null-11) (f-misc-null-11 0)) - -(define-pmacro (LRA-null) (f-LRA-null 0)) -(define-pmacro (TLBPR-null) (f-TLBPR-null 0)) - -(define-pmacro (LI-on) (f-LI-on 1)) -(define-pmacro (LI-off) (f-LI-off 0)) - -; Instruction definitions. -; -; Notes: -; - dni is short for "define-normal-instruction" -; - Macros are used to represent each insn format. These should be used as much -; as possible unless an insn has exceptional behaviour -; - -; Commonly used Macros -; -; Specific registers -; - -; Integer condition code manipulation -; -(define-pmacro (set-z-and-n icc x) - (if (eq x 0) - (set icc (or (and icc #x7) #x4)) - (if (lt x 0) - (set icc (or (and icc #xb) #x8)) - (set icc (and icc #x3)))) -) - -(define-pmacro (set-n icc val) - (if (eq val 0) - (set icc (and icc #x7)) - (set icc (or icc #x8))) -) - -(define-pmacro (set-z icc val) - (if (eq val 0) - (set icc (and icc #xb)) - (set icc (or icc #x4))) -) - -(define-pmacro (set-v icc val) - (if (eq val 0) - (set icc (and icc #xd)) - (set icc (or icc #x2))) -) - -(define-pmacro (set-c icc val) - (if (eq val 0) - (set icc (and icc #xe)) - (set icc (or icc #x1))) -) - -(define-pmacro (nbit icc) - (trunc BI (srl (and icc #x8) 3)) -) - -(define-pmacro (zbit icc) - (trunc BI (srl (and icc #x4) 2)) -) - -(define-pmacro (vbit icc) - (trunc BI (srl (and icc #x2) 1)) -) - -(define-pmacro (cbit icc) - (trunc BI (and icc #x1)) -) - -(define-pmacro (ebit icc) - (trunc BI (srl (and icc #x8) 3)) -) - -(define-pmacro (lbit icc) - (trunc BI (srl (and icc #x4) 2)) -) - -(define-pmacro (gbit icc) - (trunc BI (srl (and icc #x2) 1)) -) - -(define-pmacro (ubit icc) - (trunc BI (and icc #x1)) -) - -; FRV insns -; -; -; Format: INT, Logic, Shift r-r -; -(define-pmacro (int-logic-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRk") - (+ pack GRk op GRi (ICCi_1-null) ope GRj) - (set GRk (operation GRi GRj)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-logic-r-r add add OP_00 OPE2_00 "add reg/reg") -(int-logic-r-r sub sub OP_00 OPE2_04 "sub reg/reg") -(int-logic-r-r and and OP_01 OPE2_00 "and reg/reg") -(int-logic-r-r or or OP_01 OPE2_02 "or reg/reg") -(int-logic-r-r xor xor OP_01 OPE2_04 "xor reg/reg") - -(dni not - ("not") - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - ("not$pack $GRj,$GRk") - (+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj) - (set GRk (inv GRj)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) -) - -(dni sdiv - "signed division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "sdiv$pack $GRi,$GRj,$GRk" - (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj) - (sequence () - (c-call VOID "@cpu@_signed_integer_divide" - GRi GRj (index-of GRk) 0) - (clobber GRk)) - ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni nsdiv - "non excepting signed division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - "nsdiv$pack $GRi,$GRj,$GRk" - (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0E GRj) - (sequence () - (c-call VOID "@cpu@_signed_integer_divide" - GRi GRj (index-of GRk) 1) - (clobber GRk)) - ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni udiv - "unsigned division reg/reg" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "udiv$pack $GRi,$GRj,$GRk" - (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj) - (sequence () - (c-call VOID "@cpu@_unsigned_integer_divide" - GRi GRj (index-of GRk) 0) - (clobber GRk)) - ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni nudiv - "non excepting unsigned division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - "nudiv$pack $GRi,$GRj,$GRk" - (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0F GRj) - (sequence () - (c-call VOID "@cpu@_unsigned_integer_divide" - GRi GRj (index-of GRk) 1) - (clobber GRk)) - ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -; Multiplication -; -(define-pmacro (multiply-r-r name signop op ope comment) - (dni name - (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRdoublek") - (+ pack GRdoublek op GRi (ICCi_1-null) ope GRj) - (set GRdoublek (mul DI (signop DI GRi) (signop DI GRj))) - ((fr400 (unit u-imul)) (fr450 (unit u-imul)) - (fr500 (unit u-imul)) (fr550 (unit u-imul))) - ) -) - -(multiply-r-r smul ext OP_00 OPE2_08 "signed multiply reg/reg") -(multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg") - -; Multiplication with integer accumulator IACC -; - -(define-pmacro (iacc-set value) - (set (reg h-iacc0 0) value)) - -(define-pmacro (iacc-add value) - (set (reg h-iacc0 0) - (cond DI - ((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0)) - (lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0))) - ; Positive overflow - (const DI #x7fffffffffffffff)) - ((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0)) - (gt (sub DI #x8000000000000000 value) (reg h-iacc0 0))) - ; Negative overflow - (const DI #x8000000000000000)) - (else - (add DI (reg h-iacc0 0) value)))) -) - -(define-pmacro (iacc-sub value) - (set (reg h-iacc0 0) - (cond DI - ((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0)) - (lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0))) - ; Positive overflow - (const DI #x7fffffffffffffff)) - ((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0)) - (gt (add DI #x8000000000000000 value) (reg h-iacc0 0))) - ; Negative overflow - (const DI #x8000000000000000)) - (else - (sub DI (reg h-iacc0 0) value)))) -) - -(define-pmacro (iacc-multiply-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT IACC) (MACH fr400,fr450) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) - (.str name "$pack $GRi,$GRj") - (+ pack (rd-null) op GRi ope GRj) - ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer))) - ) -) - -(iacc-multiply-r-r smu set OP_46 OPE1_05 "Signed multiply reg/reg/iacc") -(iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc") -(iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc") - -(define-pmacro (int-shift-r-r name op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRk") - (+ pack GRk op GRi (ICCi_1-null) ope GRj) - (set GRk (name GRi (and GRj #x1f))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-shift-r-r sll OP_01 OPE2_08 "shift left logical reg/reg") -(int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg") -(int-shift-r-r sra OP_01 OPE2_0C "shift right arith reg/reg") - -(dni slass - "shift left arith reg/reg with saturation" - ((UNIT IALL) (MACH fr400,fr450) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) - "slass$pack $GRi,$GRj,$GRk" - (+ pack GRk OP_46 GRi OPE1_02 GRj) - (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj)) - () -) - -(dni scutss - "Integer accumulator cut with saturation" - ((UNIT I0) (MACH fr400,fr450) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) - "scutss$pack $GRj,$GRk" - (+ pack GRk OP_46 (rs-null) OPE1_04 GRj) - (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj)) - () -) - -(define-pmacro (scan-semantics arg1 arg2 targ) - (sequence ((WI tmp1) (WI tmp2)) - (set tmp1 arg1) - (set tmp2 (sra arg2 1)) - (set targ (c-call WI "@cpu@_scan_result" (xor tmp1 tmp2)))) -) - -(dni scan - "scan" - ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "scan$pack $GRi,$GRj,$GRk" - (+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj) - (scan-semantics GRi GRj GRk) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) -) - -; Format: conditional INT, Logic, Shift r-r -; -(define-pmacro (conditional-int-logic name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") - (+ pack GRk op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (set GRk (operation GRi GRj))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(conditional-int-logic cadd add OP_58 OPE4_0 "conditional add") -(conditional-int-logic csub sub OP_58 OPE4_1 "conditional sub") -(conditional-int-logic cand and OP_5A OPE4_0 "conditional and") -(conditional-int-logic cor or OP_5A OPE4_1 "conditional or") -(conditional-int-logic cxor xor OP_5A OPE4_2 "conditional xor") - -(dni cnot - "conditional not" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "cnot$pack $GRj,$GRk,$CCi,$cond" - (+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj) - (if (eq CCi (or cond 2)) - (set GRk (inv GRj))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) -) - -(dni csmul - "conditional signed multiply" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" - (+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (set GRdoublek (mul DI (ext DI GRi) (ext DI GRj)))) - ((fr400 (unit u-imul)) (fr450 (unit u-imul)) - (fr500 (unit u-imul)) (fr550 (unit u-imul))) -) - -(dni csdiv - "conditional signed division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond" - (+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj) - (if (eq CCi (or cond 2)) - (sequence () - (c-call VOID "@cpu@_signed_integer_divide" - GRi GRj (index-of GRk) 0) - (clobber GRk))) - ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni cudiv - "conditional unsigned division" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond" - (+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj) - (if (eq CCi (or cond 2)) - (sequence () - (c-call VOID "@cpu@_unsigned_integer_divide" - GRi GRj (index-of GRk) 0) - (clobber GRk))) - ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(define-pmacro (conditional-shift name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") - (+ pack GRk op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (set GRk (operation GRi (and GRj #x1f)))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(conditional-shift csll sll OP_5C OPE4_0 "conditional shift left logical") -(conditional-shift csrl srl OP_5C OPE4_1 "conditional shift right logical") -(conditional-shift csra sra OP_5C OPE4_2 "conditional shift right arith") - -(dni cscan - "conditional scan" - ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "cscan$pack $GRi,$GRj,$GRk,$CCi,$cond" - (+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj) - (if (eq CCi (or cond 2)) - (scan-semantics GRi GRj GRk)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) -) - -; Format: INT, Logic, Shift, cc r-r -; -(define-pmacro (int-arith-cc-semantics operation icc) - (sequence ((BI tmp) (QI cc) (SI result)) - (set cc icc) - (set tmp ((.sym operation -oflag) GRi GRj (const 0))) - (set-v cc tmp) - (set tmp ((.sym operation -cflag) GRi GRj (const 0))) - (set-c cc tmp) - (set result (operation GRi GRj)) - (set-z-and-n cc result) - (set GRk result) - (set icc cc)) -) - -(define-pmacro (int-arith-cc-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 ope GRj) - (int-arith-cc-semantics operation ICCi_1) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-arith-cc-r-r addcc add OP_00 OPE2_01 "add reg/reg, set icc") -(int-arith-cc-r-r subcc sub OP_00 OPE2_05 "sub reg/reg, set icc") - -(define-pmacro (int-logic-cc-semantics op icc) - (sequence ((SI tmp)) - (set tmp (op GRi GRj)) - (set GRk tmp) - (set-z-and-n icc tmp)) -) - -(define-pmacro (int-logic-cc-r-r name op ope comment) - (dni (.sym name cc) - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 ope GRj) - (int-logic-cc-semantics name ICCi_1) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-logic-cc-r-r and OP_01 OPE2_01 "and reg/reg, set icc") -(int-logic-cc-r-r or OP_01 OPE2_03 "or reg/reg, set icc") -(int-logic-cc-r-r xor OP_01 OPE2_05 "xor reg/reg, set icc") - -(define-pmacro (int-shift-cc-semantics op l-r icc) - (sequence ((WI shift) (SI tmp) (QI cc)) - (set shift (and GRj #x1f)) - (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) - GRi shift icc)) - (set tmp (op GRi shift)) - (set GRk tmp) - (set-z-and-n cc tmp) - (set icc cc)) -) - -(define-pmacro (int-shift-cc-r-r name l-r op ope comment) - (dni (.sym name cc) - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 ope GRj) - (int-shift-cc-semantics name l-r ICCi_1) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-shift-cc-r-r sll left OP_01 OPE2_09 "shift left logical reg/reg,set icc") -(int-shift-cc-r-r srl right OP_01 OPE2_0B "shift right logical reg/reg,set icc") -(int-shift-cc-r-r sra right OP_01 OPE2_0D "shift right arith reg/reg,set icc") - -(define-pmacro (multiply-cc-semantics signop arg1 arg2 targ icc) - (sequence ((DI tmp) (QI cc)) - (set cc icc) - (set tmp (mul DI (signop DI arg1) (signop DI arg2))) - (set-n cc (srl DI tmp 63)) - (set-z cc (eq tmp 0)) - (set targ tmp) - (set icc cc)) -) - -(define-pmacro (multiply-cc-r-r name signop op ope comment) - (dni name - (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1") - (+ pack GRdoublek op GRi ICCi_1 ope GRj) - (multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1) - ((fr400 (unit u-imul)) (fr450 (unit u-imul)) - (fr500 (unit u-imul)) (fr550 (unit u-imul))) - ) -) - -(multiply-cc-r-r smulcc ext OP_00 OPE2_09 "signed multiply reg/reg") -(multiply-cc-r-r umulcc zext OP_00 OPE2_0B "unsigned multiply reg/reg") - - -; Format: conditional INT, Logic, Shift, cc r-r -; -(define-pmacro (conditional-int-arith-cc name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") - (+ pack GRk op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (int-arith-cc-semantics operation - (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(conditional-int-arith-cc caddcc add OP_59 OPE4_0 "add, set icc") -(conditional-int-arith-cc csubcc sub OP_59 OPE4_1 "sub, set icc") - -(dni csmulcc - "conditional signed multiply and set condition code" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" - (+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (multiply-cc-semantics ext GRi GRj GRdoublek - (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-imul)) (fr450 (unit u-imul)) - (fr500 (unit u-imul)) (fr550 (unit u-imul))) -) - -(define-pmacro (conditional-int-logic-cc name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") - (+ pack GRk op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (int-logic-cc-semantics operation - (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(conditional-int-logic-cc candcc and OP_5B OPE4_0 "conditional and, set icc") -(conditional-int-logic-cc corcc or OP_5B OPE4_1 "conditional or , set icc") -(conditional-int-logic-cc cxorcc xor OP_5B OPE4_2 "conditional xor, set icc") - -(define-pmacro (conditional-int-shift-cc name l-r op ope comment) - (dni (.sym c name cc) - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - (.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond") - (+ pack GRk op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (int-shift-cc-semantics name l-r - (reg h-iccr (and (index-of CCi) 3)))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(conditional-int-shift-cc sll left OP_5D OPE4_0 "shift left logical, set icc") -(conditional-int-shift-cc srl right OP_5D OPE4_1 "shift right logical, set icc") -(conditional-int-shift-cc sra right OP_5D OPE4_2 "shift right arith , set icc") - -; Add and subtract with carry -; -(define-pmacro (int-arith-x-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 ope GRj) - (set GRk ((.sym operation c) GRi GRj (cbit ICCi_1))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-arith-x-r-r addx add OP_00 OPE2_02 "Add reg/reg, with carry") -(int-arith-x-r-r subx sub OP_00 OPE2_06 "Sub reg/reg, with carry") - -(define-pmacro (int-arith-x-cc-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 ope GRj) - (sequence ((WI tmp) (QI cc)) - (set cc ICCi_1) - (set tmp ((.sym operation c) GRi GRj (cbit cc))) - (set-v cc ((.sym operation -oflag) GRi GRj (cbit cc))) - (set-c cc ((.sym operation -cflag) GRi GRj (cbit cc))) - (set-z-and-n cc tmp) - (set GRk tmp) - (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry") -(int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry") -; Add and subtract with saturation -; -(define-pmacro (int-arith-ss-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT IALL) (MACH fr400,fr450) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) - (.str name "$pack $GRi,$GRj,$GRk") - (+ pack GRk op GRi ope GRj) - (sequence () - (set GRk (operation GRi GRj)) - (if ((.sym operation -oflag) GRi GRj (const 0)) - ; Overflow, saturate. - ; Sign of result will be - ; same as sign of first operand. - (set GRk - (cond SI - ((gt GRi 0) (const #x7fffffff)) - ((lt GRi 0) (const #x80000000)) - (else (const 0))))) - ) - ((fr400 (unit u-integer)) (fr450 (unit u-integer))) - ) -) - -(int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation") -(int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation") - -; Format: INT, Logic, Shift r-simm -; -(define-pmacro (int-logic-r-simm name operation op comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$s12,$GRk") - (+ pack GRk op GRi s12) - (set GRk (operation GRi s12)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-logic-r-simm addi add OP_10 "add reg/immed") -(int-logic-r-simm subi sub OP_14 "sub reg/immed") -(int-logic-r-simm andi and OP_20 "and reg/immed") -(int-logic-r-simm ori or OP_22 "or reg/immed") -(int-logic-r-simm xori xor OP_24 "xor reg/immed") - -(dni sdivi - "signed division reg/immed" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "sdivi$pack $GRi,$s12,$GRk" - (+ pack GRk OP_1E GRi s12) - (sequence () - (c-call VOID "@cpu@_signed_integer_divide" - GRi s12 (index-of GRk) 0) - (clobber GRk)) - ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni nsdivi - "non excepting signed division reg/immed" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - "nsdivi$pack $GRi,$s12,$GRk" - (+ pack GRk OP_2E GRi s12) - (sequence () - (c-call VOID "@cpu@_signed_integer_divide" - GRi s12 (index-of GRk) 1) - (clobber GRk)) - ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni udivi - "unsigned division reg/immed" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "udivi$pack $GRi,$s12,$GRk" - (+ pack GRk OP_1F GRi s12) - (sequence () - (c-call VOID "@cpu@_unsigned_integer_divide" - GRi s12 (index-of GRk) 0) - (clobber GRk)) - ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) - (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(dni nudivi - "non excepting unsigned division reg/immed" - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - "nudivi$pack $GRi,$s12,$GRk" - (+ pack GRk OP_2F GRi s12) - (sequence () - (c-call VOID "@cpu@_unsigned_integer_divide" - GRi s12 (index-of GRk) 1) - (clobber GRk)) - ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) -) - -(define-pmacro (multiply-r-simm name signop op comment) - (dni name - (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$s12,$GRdoublek") - (+ pack GRdoublek op GRi s12) - (set GRdoublek (mul DI (signop DI GRi) (signop DI s12))) - ((fr400 (unit u-imul)) (fr450 (unit u-imul)) - (fr500 (unit u-imul)) (fr550 (unit u-imul))) - ) -) - -(multiply-r-simm smuli ext OP_18 "signed multiply reg/immed") -(multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed") - -(define-pmacro (int-shift-r-simm name op comment) - (dni (.sym name i) - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str (.sym name i) "$pack $GRi,$s12,$GRk") - (+ pack GRk op GRi s12) - (set GRk (name GRi (and s12 #x1f))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-shift-r-simm sll OP_28 "shift left logical reg/immed") -(int-shift-r-simm srl OP_2A "shift right logical reg/immed") -(int-shift-r-simm sra OP_2C "shift right arith reg/immed") - -(dni scani - "scan immediate" - ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "scani$pack $GRi,$s12,$GRk" - (+ pack GRk OP_47 GRi s12) - (scan-semantics GRi s12 GRk) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) -) - -; Format: INT, Logic, Shift cc r-simm -; -(define-pmacro (int-arith-cc-r-simm name operation op comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 s10) - (sequence ((BI tmp) (QI cc) (SI result)) - (set cc ICCi_1) - (set tmp ((.sym operation -oflag) GRi s10 (const 0))) - (set-v cc tmp) - (set tmp ((.sym operation -cflag) GRi s10 (const 0))) - (set-c cc tmp) - (set result (operation GRi s10)) - (set-z-and-n cc result) - (set GRk result) - (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-arith-cc-r-simm addicc add OP_11 "add reg/immed, set icc") -(int-arith-cc-r-simm subicc sub OP_15 "sub reg/immed, set icc") - -(define-pmacro (int-logic-cc-r-simm name op comment) - (dni (.sym name icc) - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 s10) - (sequence ((SI tmp)) - (set tmp (name GRi s10)) - (set GRk tmp) - (set-z-and-n ICCi_1 tmp)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-logic-cc-r-simm and OP_21 "and reg/immed, set icc") -(int-logic-cc-r-simm or OP_23 "or reg/immed, set icc") -(int-logic-cc-r-simm xor OP_25 "xor reg/immed, set icc") - -(define-pmacro (multiply-cc-r-simm name signop op comment) - (dni name - (comment) - ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1") - (+ pack GRdoublek op GRi ICCi_1 s10) - (multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1) - ((fr400 (unit u-imul)) (fr450 (unit u-imul)) - (fr500 (unit u-imul)) (fr550 (unit u-imul))) - ) -) - -(multiply-cc-r-simm smulicc ext OP_19 "signed multiply reg/immed") -(multiply-cc-r-simm umulicc zext OP_1B "unsigned multiply reg/immed") - -(define-pmacro (int-shift-cc-r-simm name l-r op comment) - (dni (.sym name icc) - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 s10) - (sequence ((WI shift) (SI tmp) (QI cc)) - (set shift (and s10 #x1f)) - (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) - GRi shift ICCi_1)) - (set tmp (name GRi shift)) - (set GRk tmp) - (set-z-and-n cc tmp) - (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-shift-cc-r-simm sll left OP_29 "shift left logical reg/immed, set icc") -(int-shift-cc-r-simm srl right OP_2B "shift right logical reg/immed, set icc") -(int-shift-cc-r-simm sra right OP_2D "shift right arith reg/immed, set icc") - -(define-pmacro (int-arith-x-r-simm name operation op comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 s10) - (set GRk ((.sym operation c) GRi s10 (cbit ICCi_1))) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-arith-x-r-simm addxi add OP_12 "Add reg/immed, with carry") -(int-arith-x-r-simm subxi sub OP_16 "Sub reg/immed, with carry") - -(define-pmacro (int-arith-x-cc-r-simm name operation op comment) - (dni name - (comment) - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") - (+ pack GRk op GRi ICCi_1 s10) - (sequence ((WI tmp) (QI cc)) - (set cc ICCi_1) - (set tmp ((.sym operation c) GRi s10 (cbit cc))) - (set-v cc ((.sym operation -oflag) GRi s10 (cbit cc))) - (set-c cc ((.sym operation -cflag) GRi s10 (cbit cc))) - (set-z-and-n cc tmp) - (set GRk tmp) - (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) - ) -) - -(int-arith-x-cc-r-simm addxicc add OP_13 "Add reg/immed, with carry") -(int-arith-x-cc-r-simm subxicc sub OP_17 "Sub reg/immed, with carry") - -; Byte compare insns - -(dni cmpb - "Compare bytes" - ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "cmpb$pack $GRi,$GRj,$ICCi_1" - (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj) - (sequence ((QI cc)) - (set-n cc (eq (and GRi #xff000000) (and GRj #xff000000))) - (set-z cc (eq (and GRi #x00ff0000) (and GRj #x00ff0000))) - (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00))) - (set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff))) - (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr550 (unit u-integer))) -) - -(dni cmpba - "OR of Compare bytes" - ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "cmpba$pack $GRi,$GRj,$ICCi_1" - (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj) - (sequence ((QI cc)) - (set cc 0) - (set-c cc - (orif (eq (and GRi #xff000000) (and GRj #xff000000)) - (orif (eq (and GRi #x00ff0000) (and GRj #x00ff0000)) - (orif (eq (and GRi #x0000ff00) - (and GRj #x0000ff00)) - (eq (and GRi #x000000ff) - (and GRj #x000000ff)))))) - (set ICCi_1 cc)) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr550 (unit u-integer))) -) - -; Format: Load immediate -; -(dni setlo - "set low order bits" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "setlo$pack $ulo16,$GRklo" - (+ pack GRk OP_3D (misc-null-4) u16) - (set GRklo u16) - ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo)) - (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) -) - -(dni sethi - "set high order bits" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "sethi$pack $uhi16,$GRkhi" - (+ pack GRkhi OP_3E (misc-null-4) u16) - (set GRkhi u16) - ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo)) - (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) -) - -(dni setlos - "set low order bits and extend sign" - ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "setlos$pack $slo16,$GRk" - (+ pack GRk OP_3F (misc-null-4) s16) - (set GRk s16) - ((fr400 (unit u-integer)) (fr450 (unit u-integer)) - (fr500 (unit u-integer)) (fr550 (unit u-integer))) -) - -(define-pmacro (load-gr-r name mode op ope comment ann) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2)) - (.str name "$pack " ann "($GRi,$GRj),$GRk") - (+ pack GRk op GRi ope GRj) - (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - ) -) - -(dann ldann "ld annotation" SI "ld_annotation" "at") - -(load-gr-r ldsb QI OP_02 OPE1_00 "Load signed byte" "@") -(load-gr-r ldub UQI OP_02 OPE1_01 "Load unsigned byte" "@") -(load-gr-r ldsh HI OP_02 OPE1_02 "Load signed half" "@") -(load-gr-r lduh UHI OP_02 OPE1_03 "Load unsigned half" "@") -(load-gr-r ld SI OP_02 OPE1_04 "Load word" "$ldann") - -(define-pmacro (load-fr-r name mode op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS) - (.str name "$pack @($GRi,$GRj),$FRintk") - (+ pack FRintk op GRi ope GRj) - (set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - ) -) - -(load-fr-r ldbf UQI OP_02 OPE1_08 "Load byte float") -(load-fr-r ldhf UHI OP_02 OPE1_09 "Load half float") -(load-fr-r ldf SI OP_02 OPE1_0A "Load word float") - -(define-pmacro (load-cpr-r name mode op ope reg attr comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) attr) - (.str name "$pack @($GRi,$GRj),$" reg "k") - (+ pack (.sym reg k) op GRi ope GRj) - (set (.sym reg k) - (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) - () - ) -) - -(load-cpr-r ldc SI OP_02 OPE1_0D CPR (MACH frv) "Load coprocessor word") - -; These correspond to enumerators in frv-sim.h -(define-pmacro (ne-UQI-size) 0) -(define-pmacro (ne-QI-size) 1) -(define-pmacro (ne-UHI-size) 2) -(define-pmacro (ne-HI-size) 3) -(define-pmacro (ne-SI-size) 4) -(define-pmacro (ne-DI-size) 5) -(define-pmacro (ne-XI-size) 6) - -(define-pmacro (ne-load-semantics base dispix targ idisp size is_float action) - (sequence ((BI do_op)) - (set do_op - (c-call BI "@cpu@_check_non_excepting_load" - (index-of base) dispix (index-of targ) - idisp size is_float)) - (if do_op action)) -) - -(define-pmacro (ne-load-gr-r name mode op ope size comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$GRk") - (+ pack GRk op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 - (set GRk - (c-call mode (.str "@cpu@_read_mem_" mode) - pc (add GRi GRj)))) - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - ) -) - -(ne-load-gr-r nldsb QI OP_02 OPE1_20 (ne-QI-size) "Load signed byte") -(ne-load-gr-r nldub UQI OP_02 OPE1_21 (ne-UQI-size) "Load unsigned byte") -(ne-load-gr-r nldsh HI OP_02 OPE1_22 (ne-HI-size) "Load signed half") -(ne-load-gr-r nlduh UHI OP_02 OPE1_23 (ne-UHI-size) "Load unsigned half") -(ne-load-gr-r nld SI OP_02 OPE1_24 (ne-SI-size) "Load word") - -(define-pmacro (ne-load-fr-r name mode op ope size comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$FRintk") - (+ pack FRintk op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) FRintk 0 size 1 - (set FRintk - (c-call mode (.str "@cpu@_read_mem_" mode) - pc (add GRi GRj)))) - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - ) -) - -(ne-load-fr-r nldbf UQI OP_02 OPE1_28 (ne-UQI-size) "Load byte float") -(ne-load-fr-r nldhf UHI OP_02 OPE1_29 (ne-UHI-size) "Load half float") -(ne-load-fr-r nldf SI OP_02 OPE1_2A (ne-SI-size) "Load word float") - -; Semantics for a load-double insn -; -(define-pmacro (load-double-semantics not_gr mode regtype address arg) - (if (orif not_gr (ne (index-of (.sym regtype doublek)) 0)) - (sequence () - (set address (add GRi arg)) - (set (.sym regtype doublek) - (c-call mode (.str "@cpu@_read_mem_" mode) pc address)))) -) - -(define-pmacro (load-double-r-r - name not_gr mode op ope regtype attr profile comment ann) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) - (.str name "$pack " ann "($GRi,$GRj),$" regtype "doublek") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (sequence ((WI address)) - (load-double-semantics not_gr mode regtype address GRj)) - profile - ) -) - -(dann lddann "ldd annotation" SI "ldd_annotation" "at") - -(load-double-r-r ldd 0 DI OP_02 OPE1_05 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load double word" "$lddann") -(load-double-r-r lddf 1 DF OP_02 OPE1_0B FR FR-ACCESS - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load double float" "@") -(load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) () - "Load coprocessor double" "@") - -(define-pmacro (ne-load-double-r-r - name not_gr mode op ope regtype size is_float attr profile - comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$" regtype "doublek") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (sequence ((WI address)) - (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) - 0 size is_float - (load-double-semantics not_gr mode - regtype - address GRj))) - profile - ) -) - -(ne-load-double-r-r nldd 0 DI OP_02 OPE1_25 GR (ne-DI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") -(ne-load-double-r-r nlddf 1 DF OP_02 OPE1_2B FR (ne-DI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") - -; Semantics for a load-quad insn -; -(define-pmacro (load-quad-semantics regtype address arg) - (sequence () - (set address (add GRi arg)) - (c-call VOID (.str "@cpu@_load_quad_" regtype) - pc address (index-of (.sym regtype k)))) -) - -(define-pmacro (load-quad-r-r name op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) - (.str name "$pack @($GRi,$GRj),$" regtype "k") - (+ pack (.sym regtype k) op GRi ope GRj) - (sequence ((WI address)) - (load-quad-semantics regtype address GRj)) - ; TODO regtype-k not referenced for profiling - profile - ) -) - -(load-quad-r-r ldq OP_02 OPE1_06 GR NA ((fr500 (unit u-gr-load))) - "Load quad word") -(load-quad-r-r ldqf OP_02 OPE1_0C FRint FR-ACCESS ((fr500 (unit u-fr-load))) - "Load quad float") -(load-quad-r-r ldqc OP_02 OPE1_0F CPR NA () "Load coprocessor quad") - -(define-pmacro (ne-load-quad-r-r - name op ope regtype size is_float attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) - (.str name "$pack @($GRi,$GRj),$" regtype "k") - (+ pack (.sym regtype k) op GRi ope GRj) - (sequence ((WI address)) - (ne-load-semantics GRi (index-of GRj) (.sym regtype k) - 0 size is_float - (load-quad-semantics regtype address GRj))) - ; TODO regtype-k not referenced for profiling - profile - ) -) - -(ne-load-quad-r-r nldq OP_02 OPE1_26 GR (ne-XI-size) 0 NA - ((fr500 (unit u-gr-load))) "Load quad word") -(ne-load-quad-r-r nldqf OP_02 OPE1_2C FRint (ne-XI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load))) "Load quad float") - -(define-pmacro (load-gr-u-semantics mode) - (sequence ((UWI address)) - (set address (add GRi GRj)) - (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) - (if (ne (index-of GRi) (index-of GRk)) - (sequence () - (set GRi address) - (c-call VOID "@cpu@_force_update")))) -) - -(define-pmacro (load-gr-u name mode op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2)) - (.str name "$pack @($GRi,$GRj),$GRk") - (+ pack GRk op GRi ope GRj) - (load-gr-u-semantics mode) - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - ) -) - -(load-gr-u ldsbu QI OP_02 OPE1_10 "Load signed byte, update index") -(load-gr-u ldubu UQI OP_02 OPE1_11 "Load unsigned byte, update index") -(load-gr-u ldshu HI OP_02 OPE1_12 "Load signed half, update index") -(load-gr-u lduhu UHI OP_02 OPE1_13 "Load unsigned half, update index") -(load-gr-u ldu SI OP_02 OPE1_14 "Load word, update index") - -(define-pmacro (ne-load-gr-u name mode op ope size comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$GRk") - (+ pack GRk op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 (load-gr-u-semantics mode)) - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - ) -) - -(ne-load-gr-u nldsbu QI OP_02 OPE1_30 (ne-QI-size) "Load signed byte, update index") -(ne-load-gr-u nldubu UQI OP_02 OPE1_31 (ne-UQI-size) "Load unsigned byte, update index") -(ne-load-gr-u nldshu HI OP_02 OPE1_32 (ne-HI-size) "Load signed half, update index") -(ne-load-gr-u nlduhu UHI OP_02 OPE1_33 (ne-UHI-size) "Load unsigned half, update index") -(ne-load-gr-u nldu SI OP_02 OPE1_34 (ne-SI-size) "Load word, update index") - -(define-pmacro (load-non-gr-u-semantics mode regtype) - (sequence ((UWI address)) - (set address (add GRi GRj)) - (set (.sym regtype k) - (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) - (set GRi address) - (c-call VOID "@cpu@_force_update")) -) - -(define-pmacro (load-fr-u name mode op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS) - (.str name "$pack @($GRi,$GRj),$FRintk") - (+ pack FRintk op GRi ope GRj) - (load-non-gr-u-semantics mode FRint) - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - ) -) - -(load-fr-u ldbfu UQI OP_02 OPE1_18 "Load byte float, update index") -(load-fr-u ldhfu UHI OP_02 OPE1_19 "Load half float, update index") -(load-fr-u ldfu SI OP_02 OPE1_1A "Load word float, update index") - -(define-pmacro (load-cpr-u name mode op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) - (.str name "$pack @($GRi,$GRj),$CPRk") - (+ pack CPRk op GRi ope GRj) - (load-non-gr-u-semantics mode CPR) - () - ) -) - -(load-cpr-u ldcu SI OP_02 OPE1_1D "Load coprocessor word float,update index") - -(define-pmacro (ne-load-non-gr-u name mode op ope regtype size comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$" regtype "k") - (+ pack (.sym regtype k) op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 - (load-non-gr-u-semantics mode regtype)) - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - ) -) - -(ne-load-non-gr-u nldbfu UQI OP_02 OPE1_38 FRint (ne-UQI-size) "Load byte float, update index") -(ne-load-non-gr-u nldhfu UHI OP_02 OPE1_39 FRint (ne-UHI-size) "Load half float, update index") -(ne-load-non-gr-u nldfu SI OP_02 OPE1_3A FRint (ne-SI-size) "Load word float, update index") - -(define-pmacro (load-double-gr-u-semantics) - (sequence ((WI address)) - (load-double-semantics 0 DI GR address GRj) - (if (ne (index-of GRi) (index-of GRdoublek)) - (sequence () - (set GRi address) - (c-call VOID "@cpu@_force_update")))) -) - -(define-pmacro (load-double-gr-u name op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2)) - (.str name "$pack @($GRi,$GRj),$GRdoublek") - (+ pack GRdoublek op GRi ope GRj) - (load-double-gr-u-semantics) - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - ) -) - -(load-double-gr-u lddu OP_02 OPE1_15 "Load double word, update index") - -(define-pmacro (ne-load-double-gr-u name op ope size comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$GRdoublek") - (+ pack GRdoublek op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) GRdoublek 0 size 0 - (load-double-gr-u-semantics)) - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - - ) -) - -(ne-load-double-gr-u nlddu OP_02 OPE1_35 (ne-DI-size) "Load double word, update index") - -(define-pmacro (load-double-non-gr-u-semantics mode regtype) - (sequence ((WI address)) - (load-double-semantics 1 mode regtype address GRj) - (set GRi address) - (c-call VOID "@cpu@_force_update")) -) - -(define-pmacro (load-double-non-gr-u - name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) - (.str name "$pack @($GRi,$GRj),$" regtype "doublek") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (load-double-non-gr-u-semantics mode regtype) - profile - ) -) - -(load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR FR-ACCESS - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load double float, update index") -(load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv) - () "Load coprocessor double float, update index") - -(define-pmacro (ne-load-double-non-gr-u name mode op ope regtype size comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$GRj),$" regtype "doublek") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 0 size 1 - (load-double-non-gr-u-semantics mode regtype)) - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - ) -) - -(ne-load-double-non-gr-u nlddfu DF OP_02 OPE1_3B FR (ne-DI-size) "Load double float, update index") - -(define-pmacro (load-quad-gr-u-semantics) - (sequence ((WI address)) - (load-quad-semantics GR address GRj) - (if (ne (index-of GRi) (index-of GRk)) - (sequence () - (set GRi address) - (c-call VOID "@cpu@_force_update")))) -) - -(define-pmacro (load-quad-gr-u name op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) - (.str name "$pack @($GRi,$GRj),$GRk") - (+ pack GRk op GRi ope GRj) - (load-quad-gr-u-semantics) - ; TODO - GRk not referenced here for profiling - ((fr500 (unit u-gr-load))) - ) -) - -(load-quad-gr-u ldqu OP_02 OPE1_16 "Load quad word, update index") - -(define-pmacro (ne-load-quad-gr-u name op ope size comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING) - (.str name "$pack @($GRi,$GRj),$GRk") - (+ pack GRk op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 - (load-quad-gr-u-semantics)) - ; TODO - GRk not referenced here for profiling - ((fr500 (unit u-gr-load))) - ) -) - -(ne-load-quad-gr-u nldqu OP_02 OPE1_36 (ne-XI-size) "Load quad word, update index") - -(define-pmacro (load-quad-non-gr-u-semantics regtype) - (sequence ((WI address)) - (load-quad-semantics regtype address GRj) - (set GRi address) - (c-call VOID "@cpu@_force_update")) -) - -(define-pmacro (load-quad-non-gr-u name op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) - (.str name "$pack @($GRi,$GRj),$" regtype "k") - (+ pack (.sym regtype k) op GRi ope GRj) - (load-quad-non-gr-u-semantics regtype) - profile - ) -) - -(load-quad-non-gr-u ldqfu OP_02 OPE1_1C FRint FR-ACCESS - ((fr500 (unit u-fr-load))) "Load quad float, update index") -(load-quad-non-gr-u ldqcu OP_02 OPE1_1F CPR NA - () "Load coprocessor quad word, update index") - -(define-pmacro (ne-load-quad-non-gr-u name op ope regtype size comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING FR-ACCESS) - (.str name "$pack @($GRi,$GRj),$" regtype "k") - (+ pack (.sym regtype k) op GRi ope GRj) - (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 - (load-quad-non-gr-u-semantics regtype)) - ((fr500 (unit u-fr-load))) - ) -) - -(ne-load-quad-non-gr-u nldqfu OP_02 OPE1_3C FRint (ne-XI-size) "Load quad float,update index") - -(define-pmacro (load-r-simm name mode op regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) - (.str name "$pack @($GRi,$d12),$" regtype "k") - (+ pack (.sym regtype k) op GRi d12) - (set (.sym regtype k) - (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi d12))) - profile - ) -) - -(load-r-simm ldsbi QI OP_30 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load signed byte") -(load-r-simm ldshi HI OP_31 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load signed half") -(load-r-simm ldi SI OP_32 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load word") -(load-r-simm ldubi UQI OP_35 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load unsigned byte") -(load-r-simm lduhi UHI OP_36 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load unsigned half") - -(load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load byte float") -(load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load half float") -(load-r-simm ldfi SI OP_3A FRint FR-ACCESS - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load word float") - -(define-pmacro (ne-load-r-simm - name mode op regtype size is_float attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$d12),$" regtype "k") - (+ pack (.sym regtype k) op GRi d12) - (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float - (set (.sym regtype k) - (c-call mode (.str "@cpu@_read_mem_" mode) - pc (add GRi d12)))) - profile - ) -) - -(ne-load-r-simm nldsbi QI OP_40 GR (ne-QI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed byte") -(ne-load-r-simm nldubi UQI OP_41 GR (ne-UQI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte") -(ne-load-r-simm nldshi HI OP_42 GR (ne-HI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed half") -(ne-load-r-simm nlduhi UHI OP_43 GR (ne-UHI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half") -(ne-load-r-simm nldi SI OP_44 GR (ne-SI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load word") - -(ne-load-r-simm nldbfi UQI OP_48 FRint (ne-UQI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float") -(ne-load-r-simm nldhfi UHI OP_49 FRint (ne-UHI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float") -(ne-load-r-simm nldfi SI OP_4A FRint (ne-SI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float") - -(define-pmacro (load-double-r-simm - name not_gr mode op regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) - (.str name "$pack @($GRi,$d12),$" regtype "doublek") - (+ pack (.sym regtype doublek) op GRi d12) - (sequence ((WI address)) - (load-double-semantics not_gr mode regtype address d12)) - profile - ) -) - -(load-double-r-simm lddi 0 DI OP_33 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load double word") -(load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load double float") - -(define-pmacro (ne-load-double-r-simm - name not_gr mode op regtype size is_float attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr - (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack @($GRi,$d12),$" regtype "doublek") - (+ pack (.sym regtype doublek) op GRi d12) - (sequence ((WI address)) - (ne-load-semantics GRi -1 (.sym regtype doublek) - d12 size is_float - (load-double-semantics not_gr mode - regtype - address d12))) - profile - ) -) - -(ne-load-double-r-simm nlddi 0 DI OP_45 GR (ne-DI-size) 0 NA - ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") -(ne-load-double-r-simm nlddfi 1 DF OP_4B FR (ne-DI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") - -(define-pmacro (load-quad-r-simm name op regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) - (.str name "$pack @($GRi,$d12),$" regtype "k") - (+ pack (.sym regtype k) op GRi d12) - (sequence ((WI address)) - (load-quad-semantics regtype address d12)) - profile - ) -) - -(load-quad-r-simm ldqi OP_34 GR NA - ((fr500 (unit u-gr-load))) "Load quad word") -(load-quad-r-simm ldqfi OP_3C FRint FR-ACCESS - ((fr500 (unit u-fr-load))) "Load quad float") - -(define-pmacro (ne-load-quad-r-simm - name op regtype size is_float attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) - (.str name "$pack @($GRi,$d12),$" regtype "k") - (+ pack (.sym regtype k) op GRi d12) - (sequence ((WI address)) - (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float - (load-quad-semantics regtype address d12))) - profile - ) -) - -(ne-load-quad-r-simm nldqfi OP_4C FRint (ne-XI-size) 1 FR-ACCESS - ((fr500 (unit u-fr-load))) "Load quad float") - -(define-pmacro (store-r-r name mode op ope reg attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) - (.str name "$pack $" reg "k,@($GRi,$GRj)") - (+ pack (.sym reg k) op GRi ope GRj) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc (add GRi GRj) (.sym reg k)) - profile - ) -) - -(store-r-r stb QI OP_03 OPE1_00 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned byte") -(store-r-r sth HI OP_03 OPE1_01 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned half") -(store-r-r st SI OP_03 OPE1_02 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store word") - -(store-r-r stbf QI OP_03 OPE1_08 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store byte float") -(store-r-r sthf HI OP_03 OPE1_09 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store half float") -(store-r-r stf SI OP_03 OPE1_0A FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store word float") - -(store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word") - -; Semantics for a store-double insn -; -(define-pmacro (store-double-semantics mode regtype address arg) - (sequence () - (set address (add GRi arg)) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc address (.sym regtype doublek))) -) - -(define-pmacro (store-double-r-r name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) - (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (sequence ((WI address)) - (store-double-semantics mode regtype address GRj)) - profile - ) -) - -(store-double-r-r std DI OP_03 OPE1_03 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store double word") -(store-double-r-r stdf DF OP_03 OPE1_0B FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store double float") - -(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv) - () "Store coprocessor double word") - -; Semantics for a store-quad insn -; -(define-pmacro (store-quad-semantics regtype address arg) - (sequence () - (set address (add GRi arg)) - (c-call VOID (.str "@cpu@_store_quad_" regtype) - pc address (index-of (.sym regtype k)))) -) - -(define-pmacro (store-quad-r-r name op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) - (.str name "$pack $" regtype "k,@($GRi,$GRj)") - (+ pack (.sym regtype k) op GRi ope GRj) - (sequence ((WI address)) - (store-quad-semantics regtype address GRj)) - profile - ) -) - -(store-quad-r-r stq OP_03 OPE1_04 GR NA - ((fr500 (unit u-gr-store))) "Store quad word") -(store-quad-r-r stqf OP_03 OPE1_0C FRint FR-ACCESS - ((fr500 (unit u-fr-store))) - "Store quad float") -(store-quad-r-r stqc OP_03 OPE1_27 CPR NA - () "Store coprocessor quad word") - -(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) - (.str name "$pack $" regtype "k,@($GRi,$GRj)") - (+ pack (.sym regtype k) op GRi ope GRj) - (sequence ((UWI address)) - (set address (add GRi GRj)) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc address (.sym regtype k)) - (set GRi address)) - profile - ) -) - -(store-r-r-u stbu QI OP_03 OPE1_10 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned byte, update index") -(store-r-r-u sthu HI OP_03 OPE1_11 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned half, update index") -(store-r-r-u stu WI OP_03 OPE1_12 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store word, update index") - -(store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store byte float, update index") -(store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store half float, update index") -(store-r-r-u stfu SI OP_03 OPE1_1A FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store word float, update index") - -(store-r-r-u stcu SI OP_03 OPE1_2D CPR (MACH frv) () - "Store coprocessor word, update index") - -(define-pmacro (store-double-r-r-u - name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) - (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") - (+ pack (.sym regtype doublek) op GRi ope GRj) - (sequence ((WI address)) - (store-double-semantics mode regtype address GRj) - (set GRi address)) - profile - ) -) - -(store-double-r-r-u stdu DI OP_03 OPE1_13 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store double word, update index") -(store-double-r-r-u stdfu DF OP_03 OPE1_1B FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store double float,update index") -(store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) () - "Store coprocessor double word, update index") - -(define-pmacro (store-quad-r-r-u name op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) - (.str name "$pack $" regtype "k,@($GRi,$GRj)") - (+ pack (.sym regtype k) op GRi ope GRj) - (sequence ((WI address)) - (store-quad-semantics regtype address GRj) - (set GRi address)) - profile - ) -) - -(store-quad-r-r-u stqu OP_03 OPE1_14 GR NA - ((fr500 (unit u-gr-store))) - "Store quad word, update index") -(store-quad-r-r-u stqfu OP_03 OPE1_1C FRint FR-ACCESS - ((fr500 (unit u-fr-store))) - "Store quad float, update index") -(store-quad-r-r-u stqcu OP_03 OPE1_2F CPR NA () - "Store coprocessor quad word, update index") - -(define-pmacro (conditional-load name mode op ope regtype profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) - (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") - (+ pack (.sym regtype k) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (set (.sym regtype k) - (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))) - profile - ) -) - -(conditional-load cldsb QI OP_5E OPE4_0 GR - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load signed byte") -(conditional-load cldub UQI OP_5E OPE4_1 GR - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load unsigned byte") -(conditional-load cldsh HI OP_5E OPE4_2 GR - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load signed half") -(conditional-load clduh UHI OP_5E OPE4_3 GR - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load unsigned half") -(conditional-load cld SI OP_5F OPE4_0 GR - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load word") - -(conditional-load cldbf UQI OP_60 OPE4_0 FRint - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load byte float") -(conditional-load cldhf UHI OP_60 OPE4_1 FRint - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load half float") -(conditional-load cldf SI OP_60 OPE4_2 FRint - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - "Load word float") - -(define-pmacro (conditional-load-double - name not_gr mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL attr) - (.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond") - (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (load-double-semantics not_gr mode regtype address GRj))) - profile - ) -) - -(conditional-load-double cldd 0 DI OP_5F OPE4_1 GR NA - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - "Load double word") -(conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load))) - "Load double float") - -(dni cldq - "conditional load quad integer" - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) - "cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond" - (+ pack GRk OP_5F GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (load-quad-semantics GR address GRj))) - ((fr500 (unit u-gr-load))) -) - -(define-pmacro (conditional-load-gr-u name mode op ope comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) - (.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond") - (+ pack GRk op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (set address (add GRi GRj)) - (set GRk - (c-call mode (.str "@cpu@_read_mem_" mode) - pc address)) - (if (ne (index-of GRi) (index-of GRk)) - (set GRi address)))) - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) - ) -) - -(conditional-load-gr-u cldsbu QI OP_61 OPE4_0 "Load signed byte, update") -(conditional-load-gr-u cldubu UQI OP_61 OPE4_1 "Load unsigned byte, update") -(conditional-load-gr-u cldshu HI OP_61 OPE4_2 "Load signed half, update") -(conditional-load-gr-u clduhu UHI OP_61 OPE4_3 "Load unsigned half, update") -(conditional-load-gr-u cldu SI OP_62 OPE4_0 "Load word, update") - -(define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment) - (dni name - (comment) - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS) - (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") - (+ pack (.sym regtype k) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (set address (add GRi GRj)) - (set (.sym regtype k) - (c-call mode (.str "@cpu@_read_mem_" mode) - pc address)) - (set GRi address))) - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) - ) -) - -(conditional-load-non-gr-u cldbfu UQI OP_63 OPE4_0 FRint "Load byte float, update") -(conditional-load-non-gr-u cldhfu UHI OP_63 OPE4_1 FRint "Load half float, update") -(conditional-load-non-gr-u cldfu SI OP_63 OPE4_2 FRint "Load word float, update") - - -(dni clddu - "Load double word, update" - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) - "clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond" - (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (load-double-semantics 0 DI GR address GRj) - (if (ne (index-of GRi) (index-of GRdoublek)) - (set GRi address)))) - ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) - (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) -) - -(dni clddfu - "Load double float, update" - ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) - (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS) - "clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond" - (+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (load-double-semantics 1 DF FR address GRj) - (set GRi address))) - ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) - (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) -) - -(dni cldqu - "conditional load quad integer and update index" - ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) - "cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond" - (+ pack GRk OP_62 GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (load-quad-semantics GR address GRj) - (if (ne (index-of GRi) (index-of GRk)) - (set GRi address)))) - ((fr500 (unit u-gr-load))) -) - -(define-pmacro (conditional-store name mode op ope regtype profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL) - (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") - (+ pack (.sym regtype k) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc (add GRi GRj) (.sym regtype k))) - profile - ) -) - -(conditional-store cstb QI OP_64 OPE4_0 GR - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned byte") -(conditional-store csth HI OP_64 OPE4_1 GR - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned half") -(conditional-store cst SI OP_64 OPE4_2 GR - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store word") - -(conditional-store cstbf QI OP_66 OPE4_0 FRint - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store byte float") -(conditional-store csthf HI OP_66 OPE4_1 FRint - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store half float") -(conditional-store cstf SI OP_66 OPE4_2 FRint - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store word float") - -(define-pmacro (conditional-store-double - name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) - (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") - (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (store-double-semantics mode regtype address GRj))) - profile - ) -) - -(conditional-store-double cstd DI OP_64 OPE4_3 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store double word") -(conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store double float") - -(dni cstq - "conditionally store quad word" - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) CONDITIONAL) - "cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond" - (+ pack GRk OP_65 GRi CCi cond OPE4_0 GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (store-quad-semantics GR address GRj))) - ((fr500 (unit u-gr-store))) -) - -(define-pmacro (conditional-store-u - name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) - (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") - (+ pack (.sym regtype k) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (set address (add GRi GRj)) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc address (.sym regtype k)) - (set GRi address))) - profile - ) -) - -(conditional-store-u cstbu QI OP_67 OPE4_0 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned byte, update index") -(conditional-store-u csthu HI OP_67 OPE4_1 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned half, update index") -(conditional-store-u cstu SI OP_67 OPE4_2 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store word, update index") - -(conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store byte float, update index") -(conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store half float, update index") -(conditional-store-u cstfu SI OP_68 OPE4_2 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store word float, update index") - -(define-pmacro (conditional-store-double-u - name mode op ope regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) - (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") - (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) - (if (eq CCi (or cond 2)) - (sequence ((WI address)) - (store-double-semantics mode regtype address GRj) - (set GRi address))) - profile - ) -) - -(conditional-store-double-u cstdu DI OP_67 OPE4_3 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store double word, update index") -(conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store double float, update index") - -(define-pmacro (store-r-simm name mode op regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) - (.str name "$pack $" regtype "k,@($GRi,$d12)") - (+ pack (.sym regtype k) op GRi d12) - (c-call VOID (.str "@cpu@_write_mem_" mode) - pc (add GRi d12) (.sym regtype k)) - profile - ) -) - -(store-r-simm stbi QI OP_50 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned byte") -(store-r-simm sthi HI OP_51 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store unsigned half") -(store-r-simm sti SI OP_52 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store word") - -(store-r-simm stbfi QI OP_4E FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store byte float") -(store-r-simm sthfi HI OP_4F FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store half float") -(store-r-simm stfi SI OP_55 FRint FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store word float") - -(define-pmacro (store-double-r-simm name mode op regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) - (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) - (.str name "$pack $" regtype "doublek,@($GRi,$d12)") - (+ pack (.sym regtype doublek) op GRi d12) - (sequence ((WI address)) - (store-double-semantics mode regtype address d12)) - profile - ) -) - -(store-double-r-simm stdi DI OP_53 GR NA - ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) - (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) - "Store double word") -(store-double-r-simm stdfi DF OP_56 FR FR-ACCESS - ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) - (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) - "Store double float") - -(define-pmacro (store-quad-r-simm name op regtype attr profile comment) - (dni name - (comment) - ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) - (.str name "$pack $" regtype "k,@($GRi,$d12)") - (+ pack (.sym regtype k) op GRi d12) - (sequence ((WI address)) - (store-quad-semantics regtype address d12)) - profile - ) -) - -(store-quad-r-simm stqi OP_54 GR NA ((fr500 (unit u-gr-store))) - "Store quad word") -(store-quad-r-simm stqfi OP_57 FRint FR-ACCESS () - "Store quad float") - -(define-pmacro (swap-semantics base offset arg) - (sequence ((WI tmp) (WI address)) - (set tmp arg) - (set address (add base offset)) - (c-call VOID "@cpu@_check_swap_address" address) - (set arg (c-call WI "@cpu@_read_mem_WI" pc address)) - (c-call VOID "@cpu@_write_mem_WI" pc address tmp)) -) - -(dni swap - "Swap contents of memory with GR" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - "swap$pack @($GRi,$GRj),$GRk" - (+ pack GRk OP_03 GRi OPE1_05 GRj) - (swap-semantics GRi GRj GRk) - ((fr400 (unit u-swap)) (fr450 (unit u-swap)) - (fr500 (unit u-swap)) (fr550 (unit u-swap))) -) - -(dni "swapi" - "Swap contents of memory with GR" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - ("swapi$pack @($GRi,$d12),$GRk") - (+ pack GRk OP_4D GRi d12) - (swap-semantics GRi d12 GRk) - ((fr400 (unit u-swap)) (fr450 (unit u-swap)) - (fr500 (unit u-swap)) (fr550 (unit u-swap))) -) - -(dni cswap - "Conditionally swap contents of memory with GR" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2) CONDITIONAL) - "cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond" - (+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (swap-semantics GRi GRj GRk)) - ((fr400 (unit u-swap)) (fr450 (unit u-swap)) - (fr500 (unit u-swap)) (fr550 (unit u-swap))) -) - -(define-pmacro (register-transfer - name op ope reg_src reg_targ pipe attrs profile comment) - (dni name - (comment) - (.splice (UNIT pipe) (.unsplice attrs)) - (.str name "$pack $" reg_src ",$" reg_targ) - (+ pack reg_targ op (rs-null) ope reg_src) - (set reg_targ reg_src) - profile - ) -) - -(register-transfer movgf OP_03 OPE1_15 - GRj FRintk I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) - ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) - (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) - "transfer gr to fr") -(register-transfer movfg OP_03 OPE1_0D - FRintk GRj I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) - ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) - (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) - "transfer fr to gr") - -(define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset))) - -(define-pmacro (register-transfer-double-from-gr-semantics cond) - (if cond - (if (eq (index-of GRj) 0) - (sequence () - (set FRintk 0) - (set (nextreg h-fr_int FRintk 1) 0)) - (sequence () - (set FRintk GRj) - (set (nextreg h-fr_int FRintk 1) (nextreg h-gr GRj 1))))) -) - -(dni movgfd - "move GR for FR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) - "movgfd$pack $GRj,$FRintk" - (+ pack FRintk OP_03 (rs-null) OPE1_16 GRj) - (register-transfer-double-from-gr-semantics 1) - ; TODO -- doesn't handle second register in the pair - ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) - (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) -) - -(define-pmacro (register-transfer-double-to-gr-semantics cond) - (if (andif (ne (index-of GRj) 0) cond) - (sequence () - (set GRj FRintk) - (set (nextreg h-gr GRj 1) (nextreg h-fr_int FRintk 1)))) -) - -(dni movfgd - "move FR for GR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) - "movfgd$pack $FRintk,$GRj" - (+ pack FRintk OP_03 (rs-null) OPE1_0E GRj) - (register-transfer-double-to-gr-semantics 1) - ; TODO -- doesn't handle second register in the pair - ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) - (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) -) - -(dni movgfq - "move GR for FR quad" - ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) - "movgfq$pack $GRj,$FRintk" - (+ pack FRintk OP_03 (rs-null) OPE1_17 GRj) - (if (eq (index-of GRj) 0) - (sequence () - (set FRintk 0) - (set (reg h-fr_int (add (index-of FRintk) 1)) 0) - (set (reg h-fr_int (add (index-of FRintk) 2)) 0) - (set (reg h-fr_int (add (index-of FRintk) 3)) 0)) - (sequence () - (set FRintk GRj) - (set (reg h-fr_int (add (index-of FRintk) 1)) - (reg h-gr (add (index-of GRj) 1))) - (set (reg h-fr_int (add (index-of FRintk) 2)) - (reg h-gr (add (index-of GRj) 2))) - (set (reg h-fr_int (add (index-of FRintk) 3)) - (reg h-gr (add (index-of GRj) 3))))) - () -) - -(dni movfgq - "move FR for GR quad" - ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) - "movfgq$pack $FRintk,$GRj" - (+ pack FRintk OP_03 (rs-null) OPE1_0F GRj) - (if (ne (index-of GRj) 0) - (sequence () - (set GRj FRintk) - (set (reg h-gr (add (index-of GRj) 1)) - (reg h-fr_int (add (index-of FRintk) 1))) - (set (reg h-gr (add (index-of GRj) 2)) - (reg h-fr_int (add (index-of FRintk) 2))) - (set (reg h-gr (add (index-of GRj) 3)) - (reg h-fr_int (add (index-of FRintk) 3))))) - () -) - -(define-pmacro (conditional-register-transfer - name op ope reg_src reg_targ pipe attrs profile comment) - (dni name - (comment) - (.splice (UNIT pipe) CONDITIONAL FR-ACCESS (.unsplice attrs)) - (.str name "$pack $" reg_src ",$" reg_targ ",$CCi,$cond") - (+ pack reg_targ op (rs-null) CCi cond ope reg_src) - (if (eq CCi (or cond 2)) - (set reg_targ reg_src)) - profile - ) -) - -(conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4)) - ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) - (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) - "transfer gr to fr") -(conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0 - ((FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4)) - ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) - (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) - "transfer fr to gr") - - -(dni cmovgfd - "Conditional move GR to FR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS) - "cmovgfd$pack $GRj,$FRintk,$CCi,$cond" - (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj) - (register-transfer-double-from-gr-semantics (eq CCi (or cond 2))) - ; TODO -- doesn't handle extra registers in double - ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) - (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) -) - -(dni cmovfgd - "Conditional move FR to GR double" - ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) - (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS) - "cmovfgd$pack $FRintk,$GRj,$CCi,$cond" - (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj) - (register-transfer-double-to-gr-semantics (eq CCi (or cond 2))) - ; TODO -- doesn't handle second register in the pair - ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) - (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) -) - -(define-pmacro (register-transfer-spr - name op ope reg_src reg_targ unitname comment) - (dni name - (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - (.str name "$pack $" reg_src ",$" reg_targ) - (+ pack reg_targ op ope reg_src) - (set reg_targ reg_src) - ((fr400 (unit unitname)) (fr450 (unit unitname)) - (fr500 (unit unitname)) (fr550 (unit unitname))) - ) -) - -(register-transfer-spr movgs OP_03 OPE1_06 GRj spr u-gr2spr "transfer gr->spr") -(register-transfer-spr movsg OP_03 OPE1_07 spr GRj u-spr2gr "transfer spr->gr") - -; Integer Branch Conditions -(define-pmacro (Inev cc) (const BI 0)) -(define-pmacro (Ira cc) (const BI 1)) -(define-pmacro (Ieq cc) ( zbit cc)) -(define-pmacro (Ine cc) (not (zbit cc))) -(define-pmacro (Ile cc) ( orif (zbit cc) (xor (nbit cc) (vbit cc)))) -(define-pmacro (Igt cc) (not (orif (zbit cc) (xor (nbit cc) (vbit cc))))) -(define-pmacro (Ilt cc) ( xor (nbit cc) (vbit cc))) -(define-pmacro (Ige cc) (not (xor (nbit cc) (vbit cc)))) -(define-pmacro (Ils cc) ( orif (cbit cc) (zbit cc))) -(define-pmacro (Ihi cc) (not (orif (cbit cc) (zbit cc)))) -(define-pmacro (Ic cc) ( cbit cc)) -(define-pmacro (Inc cc) (not (cbit cc))) -(define-pmacro (In cc) ( nbit cc)) -(define-pmacro (Ip cc) (not (nbit cc))) -(define-pmacro (Iv cc) ( vbit cc)) -(define-pmacro (Inv cc) (not (vbit cc))) - -; Float Branch Conditions -(define-pmacro (Fnev cc) (const BI 0)) -(define-pmacro (Fra cc) (const BI 1)) -(define-pmacro (Fne cc) (orif (lbit cc) (orif (gbit cc) (ubit cc)))) -(define-pmacro (Feq cc) (ebit cc)) -(define-pmacro (Flg cc) (orif (lbit cc) (gbit cc))) -(define-pmacro (Fue cc) (orif (ebit cc) (ubit cc))) -(define-pmacro (Ful cc) (orif (lbit cc) (ubit cc))) -(define-pmacro (Fge cc) (orif (ebit cc) (gbit cc))) -(define-pmacro (Flt cc) (lbit cc)) -(define-pmacro (Fuge cc) (orif (ebit cc) (orif (gbit cc) (ubit cc)))) -(define-pmacro (Fug cc) (orif (gbit cc) (ubit cc))) -(define-pmacro (Fle cc) (orif (ebit cc) (lbit cc))) -(define-pmacro (Fgt cc) (gbit cc)) -(define-pmacro (Fule cc) (orif (ebit cc) (orif (lbit cc) (ubit cc)))) -(define-pmacro (Fu cc) (ubit cc)) -(define-pmacro (Fo cc) (orif (ebit cc) (orif (lbit cc) (gbit cc)))) - -(define-pmacro (conditional-branch-i prefix cc op cond comment) - (dni (.sym prefix cc) - (comment) - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) - (FR400-MAJOR B-1) (FR450-MAJOR B-1)) - (.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16") - (+ pack (.sym ICC_ cc) ICCi_2 op hint label16) - (sequence () - (c-call VOID "@cpu@_model_branch" label16 hint) - (if (cond ICCi_2) - (set pc label16))) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) - ) -) - -(dni bra - "integer branch equal" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) - (FR400-MAJOR B-1) (FR450-MAJOR B-1)) - "bra$pack $hint_taken$label16" - (+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16) - (sequence () - (c-call VOID "@cpu@_model_branch" label16 hint_taken) - (set pc label16)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni bno - "integer branch never" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) - (FR400-MAJOR B-1) (FR450-MAJOR B-1)) - "bno$pack$hint_not_taken" - (+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null)) - (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(conditional-branch-i b eq OP_06 Ieq "integer branch equal") -(conditional-branch-i b ne OP_06 Ine "integer branch not equal") -(conditional-branch-i b le OP_06 Ile "integer branch less or equal") -(conditional-branch-i b gt OP_06 Igt "integer branch greater") -(conditional-branch-i b lt OP_06 Ilt "integer branch less") -(conditional-branch-i b ge OP_06 Ige "integer branch greater or equal") -(conditional-branch-i b ls OP_06 Ils "integer branch less or equal unsigned") -(conditional-branch-i b hi OP_06 Ihi "integer branch greater unsigned") -(conditional-branch-i b c OP_06 Ic "integer branch carry set") -(conditional-branch-i b nc OP_06 Inc "integer branch carry clear") -(conditional-branch-i b n OP_06 In "integer branch negative") -(conditional-branch-i b p OP_06 Ip "integer branch positive") -(conditional-branch-i b v OP_06 Iv "integer branch overflow set") -(conditional-branch-i b nv OP_06 Inv "integer branch overflow clear") - -(define-pmacro (conditional-branch-f prefix cc op cond comment) - (dni (.sym prefix cc) - (comment) - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) - (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) - (.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16") - (+ pack (.sym FCC_ cc) FCCi_2 op hint label16) - (sequence () - (c-call VOID "@cpu@_model_branch" label16 hint) - (if (cond FCCi_2) (set pc label16))) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) - ) -) - -(dni fbra - "float branch equal" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) - (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) - "fbra$pack $hint_taken$label16" - (+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16) - (sequence () - (c-call VOID "@cpu@_model_branch" label16 hint_taken) - (set pc label16)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni fbno - "float branch never" - ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) - (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) - "fbno$pack$hint_not_taken" - (+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null)) - (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(conditional-branch-f fb ne OP_07 Fne "float branch not equal") -(conditional-branch-f fb eq OP_07 Feq "float branch equal") -(conditional-branch-f fb lg OP_07 Flg "float branch less or greater") -(conditional-branch-f fb ue OP_07 Fue "float branch unordered or equal") -(conditional-branch-f fb ul OP_07 Ful "float branch unordered or less") -(conditional-branch-f fb ge OP_07 Fge "float branch greater or equal") -(conditional-branch-f fb lt OP_07 Flt "float branch less") -(conditional-branch-f fb uge OP_07 Fuge "float branch unordered, greater,equal") -(conditional-branch-f fb ug OP_07 Fug "float branch unordered or greater") -(conditional-branch-f fb le OP_07 Fle "float branch less or equal") -(conditional-branch-f fb gt OP_07 Fgt "float branch greater") -(conditional-branch-f fb ule OP_07 Fule "float branch unordered, less or equal") -(conditional-branch-f fb u OP_07 Fu "float branch unordered") -(conditional-branch-f fb o OP_07 Fo "float branch ordered") - -(define-pmacro (ctrlr-branch-semantics cond ccond) - (sequence ((SI tmp)) - (set tmp (sub (spr-lcr) 1)) - (set (spr-lcr) tmp) - (if cond - (if (eq ccond 0) - (if (ne tmp 0) - (set pc (spr-lr))) - (if (eq tmp 0) - (set pc (spr-lr)))))) -) - -(dni bctrlr - "LCR conditional branch to lr" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) - (FR400-MAJOR B-2) (FR450-MAJOR B-2)) - ("bctrlr$pack $ccond,$hint") - (+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint) - (ctrlr-branch-semantics (const BI 1) ccond)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment) - (dni (.sym prefix cc lr) - (comment) - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) - (FR400-MAJOR B-3) (FR450-MAJOR B-3) attr) - (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint") - (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope - (ccond-null) (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint) - (if (cond (.sym i-f CCi_2)) (set pc (spr-lr)))) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) - ) -) - -(dni bralr - "integer cclr branch always" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) - (FR400-MAJOR B-3) (FR450-MAJOR B-3)) - "bralr$pack$hint_taken" - (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) - (set pc (spr-lr))) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni bnolr - "integer cclr branch never" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) - (FR400-MAJOR B-3) (FR450-MAJOR B-3)) - "bnolr$pack$hint_not_taken" - (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null)) - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(conditional-branch-cclr b eq I OP_0E OPE3_02 Ieq NA "integer cclr branch equal") -(conditional-branch-cclr b ne I OP_0E OPE3_02 Ine NA "integer cclr branch not equal") -(conditional-branch-cclr b le I OP_0E OPE3_02 Ile NA "integer cclr branch less or equal") -(conditional-branch-cclr b gt I OP_0E OPE3_02 Igt NA "integer cclr branch greater") -(conditional-branch-cclr b lt I OP_0E OPE3_02 Ilt NA "integer cclr branch less") -(conditional-branch-cclr b ge I OP_0E OPE3_02 Ige NA "integer cclr branch greater or equal") -(conditional-branch-cclr b ls I OP_0E OPE3_02 Ils NA "integer cclr branch less or equal unsigned") -(conditional-branch-cclr b hi I OP_0E OPE3_02 Ihi NA "integer cclr branch greater unsigned") -(conditional-branch-cclr b c I OP_0E OPE3_02 Ic NA "integer cclr branch carry set") -(conditional-branch-cclr b nc I OP_0E OPE3_02 Inc NA "integer cclr branch carry clear") -(conditional-branch-cclr b n I OP_0E OPE3_02 In NA "integer cclr branch negative") -(conditional-branch-cclr b p I OP_0E OPE3_02 Ip NA "integer cclr branch positive") -(conditional-branch-cclr b v I OP_0E OPE3_02 Iv NA "integer cclr branch overflow set") -(conditional-branch-cclr b nv I OP_0E OPE3_02 Inv NA "integer cclr branch overflow clear") - -(dni fbralr - "float cclr branch always" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) - (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS) - "fbralr$pack$hint_taken" - (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) - (set pc (spr-lr))) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni fbnolr - "float cclr branch never" - ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) - (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS) - "fbnolr$pack$hint_not_taken" - (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null)) - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(conditional-branch-cclr fb eq F OP_0E OPE3_06 Feq FR-ACCESS "float cclr branch equal") -(conditional-branch-cclr fb ne F OP_0E OPE3_06 Fne FR-ACCESS "float cclr branch not equal") -(conditional-branch-cclr fb lg F OP_0E OPE3_06 Flg FR-ACCESS "float branch less or greater") -(conditional-branch-cclr fb ue F OP_0E OPE3_06 Fue FR-ACCESS "float branch unordered or equal") -(conditional-branch-cclr fb ul F OP_0E OPE3_06 Ful FR-ACCESS "float branch unordered or less") -(conditional-branch-cclr fb ge F OP_0E OPE3_06 Fge FR-ACCESS "float branch greater or equal") -(conditional-branch-cclr fb lt F OP_0E OPE3_06 Flt FR-ACCESS "float branch less") -(conditional-branch-cclr fb uge F OP_0E OPE3_06 Fuge FR-ACCESS "float branch unordered, greater, equal") -(conditional-branch-cclr fb ug F OP_0E OPE3_06 Fug FR-ACCESS "float branch unordered or greater") -(conditional-branch-cclr fb le F OP_0E OPE3_06 Fle FR-ACCESS "float branch less or equal") -(conditional-branch-cclr fb gt F OP_0E OPE3_06 Fgt FR-ACCESS "float branch greater") -(conditional-branch-cclr fb ule F OP_0E OPE3_06 Fule FR-ACCESS "float branch unordered, less or equal") -(conditional-branch-cclr fb u F OP_0E OPE3_06 Fu FR-ACCESS "float branch unordered") -(conditional-branch-cclr fb o F OP_0E OPE3_06 Fo FR-ACCESS "float branch ordered") - -(define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment) - (dni (.sym prefix cc lr) - (comment) - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) - (FR400-MAJOR B-2) (FR450-MAJOR B-2) attr) - (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint") - (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint) - (ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) - ) -) - -(dni bcralr - "integer ctrlr branch always" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) - (FR400-MAJOR B-2) (FR450-MAJOR B-2)) - "bcralr$pack $ccond$hint_taken" - (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) - (ctrlr-branch-semantics (const BI 1) ccond)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni bcnolr - "integer ctrlr branch never" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) - (FR400-MAJOR B-2) (FR450-MAJOR B-2)) - "bcnolr$pack$hint_not_taken" - (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) - (ctrlr-branch-semantics (const BI 0) ccond)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(conditional-branch-ctrlr bc eq I OP_0E OPE3_03 Ieq NA "integer ctrlr branch equal") -(conditional-branch-ctrlr bc ne I OP_0E OPE3_03 Ine NA "integer ctrlr branch not equal") -(conditional-branch-ctrlr bc le I OP_0E OPE3_03 Ile NA "integer ctrlr branch less equal") -(conditional-branch-ctrlr bc gt I OP_0E OPE3_03 Igt NA "integer ctrlr branch greater") -(conditional-branch-ctrlr bc lt I OP_0E OPE3_03 Ilt NA "integer ctrlr branch less") -(conditional-branch-ctrlr bc ge I OP_0E OPE3_03 Ige NA "integer ctrlr branch greater equal") -(conditional-branch-ctrlr bc ls I OP_0E OPE3_03 Ils NA "integer ctrlr branch less equal unsigned") -(conditional-branch-ctrlr bc hi I OP_0E OPE3_03 Ihi NA "integer ctrlr branch greater unsigned") -(conditional-branch-ctrlr bc c I OP_0E OPE3_03 Ic NA "integer ctrlr branch carry set") -(conditional-branch-ctrlr bc nc I OP_0E OPE3_03 Inc NA "integer ctrlr branch carry clear") -(conditional-branch-ctrlr bc n I OP_0E OPE3_03 In NA "integer ctrlr branch negative") -(conditional-branch-ctrlr bc p I OP_0E OPE3_03 Ip NA "integer ctrlr branch positive") -(conditional-branch-ctrlr bc v I OP_0E OPE3_03 Iv NA "integer ctrlr branch overflow set") -(conditional-branch-ctrlr bc nv I OP_0E OPE3_03 Inv NA "integer ctrlr branch overflow clear") - -(dni fcbralr - "float ctrlr branch always" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) - (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS) - "fcbralr$pack $ccond$hint_taken" - (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) - (ctrlr-branch-semantics (const BI 1) ccond)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni fcbnolr - "float ctrlr branch never" - ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) - (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS) - "fcbnolr$pack$hint_not_taken" - (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null)) - (sequence () - (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) - (ctrlr-branch-semantics (const BI 0) ccond)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(conditional-branch-ctrlr fcb eq F OP_0E OPE3_07 Feq FR-ACCESS "float cclr branch equal") -(conditional-branch-ctrlr fcb ne F OP_0E OPE3_07 Fne FR-ACCESS "float cclr branch not equal") -(conditional-branch-ctrlr fcb lg F OP_0E OPE3_07 Flg FR-ACCESS "float branch less or greater") -(conditional-branch-ctrlr fcb ue F OP_0E OPE3_07 Fue FR-ACCESS "float branch unordered or equal") -(conditional-branch-ctrlr fcb ul F OP_0E OPE3_07 Ful FR-ACCESS "float branch unordered or less") -(conditional-branch-ctrlr fcb ge F OP_0E OPE3_07 Fge FR-ACCESS "float branch greater or equal") -(conditional-branch-ctrlr fcb lt F OP_0E OPE3_07 Flt FR-ACCESS "float branch less") -(conditional-branch-ctrlr fcb uge F OP_0E OPE3_07 Fuge FR-ACCESS "float branch unordered, greater, equal") -(conditional-branch-ctrlr fcb ug F OP_0E OPE3_07 Fug FR-ACCESS "float branch unordered or greater") -(conditional-branch-ctrlr fcb le F OP_0E OPE3_07 Fle FR-ACCESS "float branch less or equal") -(conditional-branch-ctrlr fcb gt F OP_0E OPE3_07 Fgt FR-ACCESS "float branch greater") -(conditional-branch-ctrlr fcb ule F OP_0E OPE3_07 Fule FR-ACCESS "float branch unordered, less or equal") -(conditional-branch-ctrlr fcb u F OP_0E OPE3_07 Fu FR-ACCESS "float branch unordered") -(conditional-branch-ctrlr fcb o F OP_0E OPE3_07 Fo FR-ACCESS "float branch ordered") - -(define-pmacro (jump-and-link-semantics base offset LI) - (sequence () - (if (eq LI 1) - (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1)) - ; Target address gets aligned here - (set pc (and (add base offset) #xfffffffc)) - (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken -) - -(dni jmpl - "jump and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) - (FR400-MAJOR I-5) (FR450-MAJOR I-5)) - "jmpl$pack @($GRi,$GRj)" - (+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj) - (jump-and-link-semantics GRi GRj LI) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dann callann "call annotation" SI "call_annotation" "at") - -(dni calll - "call and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) - (FR400-MAJOR I-5) (FR450-MAJOR I-5)) - "calll$pack $callann($GRi,$GRj)" - (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj) - (jump-and-link-semantics GRi GRj LI) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni jmpil - "jump immediate and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) - (FR400-MAJOR I-5) (FR450-MAJOR I-5)) - "jmpil$pack @($GRi,$s12)" - (+ pack (misc-null-1) (LI-off) OP_0D GRi s12) - (jump-and-link-semantics GRi s12 LI) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni callil - "call immediate and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) - (FR400-MAJOR I-5) (FR450-MAJOR I-5)) - "callil$pack @($GRi,$s12)" - (+ pack (misc-null-1) (LI-on) OP_0D GRi s12) - (jump-and-link-semantics GRi s12 LI) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni call - "call and link" - ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) - (FR400-MAJOR B-4) (FR450-MAJOR B-4)) - "call$pack $label24" - (+ pack OP_0F label24) - (sequence () - (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1) - (set pc label24) - (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni rett - "return from trap" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2) PRIVILEGED) - "rett$pack $debug" - (+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null)) - ; frv_rett handles operating vs user mode - (sequence () - (set pc (c-call UWI "frv_rett" pc debug)) - (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken - () -) - -(dni rei - "run exception instruction" - ((UNIT C) (FR500-MAJOR C-1) (MACH frv) PRIVILEGED) - "rei$pack $eir" - (+ pack (rd-null) OP_37 eir (s12-null)) - (nop) ; for now - () -) - -(define-pmacro (trap-semantics cond base offset) - (if cond - (sequence () - ; This is defered to frv_itrap because for the breakpoint - ; case we want to change as little of the machine state as - ; possible. - ; - ; PCSR=PC - ; PSR.PS=PSR.S - ; PSR.ET=0 - ; if PSR.ESR==1 - ; SR0 through SR3=GR4 through GR7 - ; TBR.TT=0x80 + ((GRi + s12) & 0x7f) - ; PC=TBR - ; We still should indicate what is modified by this insn. - (clobber (spr-pcsr)) - (clobber psr_ps) - (clobber psr_et) - (clobber tbr_tt) - (if (ne psr_esr (const 0)) - (sequence () - (clobber (spr-sr0)) - (clobber (spr-sr1)) - (clobber (spr-sr2)) - (clobber (spr-sr3)))) - ; frv_itrap handles operating vs user mode - (c-call VOID "frv_itrap" pc base offset))) -) - -(define-pmacro (trap-r prefix cc i-f op ope cond attr comment) - (dni (.sym prefix cc) - (comment) - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr) - (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj") - (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj) - (trap-semantics (cond (.sym i-f CCi_2)) GRi GRj) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) - ) -) - -(dni tra - "integer trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1)) - "tra$pack $GRi,$GRj" - (+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj) - (trap-semantics (const BI 1) GRi GRj) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(dni tno - "integer trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1)) - "tno$pack" - (+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null)) - (trap-semantics (const BI 0) GRi GRj) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(trap-r t eq I OP_04 OPE4_0 Ieq NA "integer trap equal") -(trap-r t ne I OP_04 OPE4_0 Ine NA "integer trap not equal") -(trap-r t le I OP_04 OPE4_0 Ile NA "integer trap less or equal") -(trap-r t gt I OP_04 OPE4_0 Igt NA "integer trap greater") -(trap-r t lt I OP_04 OPE4_0 Ilt NA "integer trap less") -(trap-r t ge I OP_04 OPE4_0 Ige NA "integer trap greater or equal") -(trap-r t ls I OP_04 OPE4_0 Ils NA "integer trap less or equal unsigned") -(trap-r t hi I OP_04 OPE4_0 Ihi NA "integer trap greater unsigned") -(trap-r t c I OP_04 OPE4_0 Ic NA "integer trap carry set") -(trap-r t nc I OP_04 OPE4_0 Inc NA "integer trap carry clear") -(trap-r t n I OP_04 OPE4_0 In NA "integer trap negative") -(trap-r t p I OP_04 OPE4_0 Ip NA "integer trap positive") -(trap-r t v I OP_04 OPE4_0 Iv NA "integer trap overflow set") -(trap-r t nv I OP_04 OPE4_0 Inv NA "integer trap overflow clear") - -(dni ftra - "float trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) - "ftra$pack $GRi,$GRj" - (+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj) - (trap-semantics (const BI 1) GRi GRj) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(dni ftno - "flost trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) - "ftno$pack" - (+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null)) - (trap-semantics (const BI 0) GRi GRj) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(trap-r ft ne F OP_04 OPE4_1 Fne FR-ACCESS "float trap not equal") -(trap-r ft eq F OP_04 OPE4_1 Feq FR-ACCESS "float trap equal") -(trap-r ft lg F OP_04 OPE4_1 Flg FR-ACCESS "float trap greater or less") -(trap-r ft ue F OP_04 OPE4_1 Fue FR-ACCESS "float trap unordered or equal") -(trap-r ft ul F OP_04 OPE4_1 Ful FR-ACCESS "float trap unordered or less") -(trap-r ft ge F OP_04 OPE4_1 Fge FR-ACCESS "float trap greater or equal") -(trap-r ft lt F OP_04 OPE4_1 Flt FR-ACCESS "float trap less") -(trap-r ft uge F OP_04 OPE4_1 Fuge FR-ACCESS "float trap unordered greater or equal") -(trap-r ft ug F OP_04 OPE4_1 Fug FR-ACCESS "float trap unordered or greater") -(trap-r ft le F OP_04 OPE4_1 Fle FR-ACCESS "float trap less or equal") -(trap-r ft gt F OP_04 OPE4_1 Fgt FR-ACCESS "float trap greater") -(trap-r ft ule F OP_04 OPE4_1 Fule FR-ACCESS "float trap unordered less or equal") -(trap-r ft u F OP_04 OPE4_1 Fu FR-ACCESS "float trap unordered") -(trap-r ft o F OP_04 OPE4_1 Fo FR-ACCESS "float trap ordered") - -(define-pmacro (trap-immed prefix cc i-f op cond attr comment) - (dni (.sym prefix cc) - (comment) - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr) - (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12") - (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12) - (trap-semantics (cond (.sym i-f CCi_2)) GRi s12) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) - ) -) - -(dni tira - "integer trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1)) - "tira$pack $GRi,$s12" - (+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12) - (trap-semantics (const BI 1) GRi s12) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(dni tino - "integer trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1)) - "tino$pack" - (+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null)) - (trap-semantics (const BI 0) GRi s12) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(trap-immed ti eq I OP_1C Ieq NA "integer trap equal") -(trap-immed ti ne I OP_1C Ine NA "integer trap not equal") -(trap-immed ti le I OP_1C Ile NA "integer trap less or equal") -(trap-immed ti gt I OP_1C Igt NA "integer trap greater") -(trap-immed ti lt I OP_1C Ilt NA "integer trap less") -(trap-immed ti ge I OP_1C Ige NA "integer trap greater or equal") -(trap-immed ti ls I OP_1C Ils NA "integer trap less or equal unsigned") -(trap-immed ti hi I OP_1C Ihi NA "integer trap greater unsigned") -(trap-immed ti c I OP_1C Ic NA "integer trap carry set") -(trap-immed ti nc I OP_1C Inc NA "integer trap carry clear") -(trap-immed ti n I OP_1C In NA "integer trap negative") -(trap-immed ti p I OP_1C Ip NA "integer trap positive") -(trap-immed ti v I OP_1C Iv NA "integer trap overflow set") -(trap-immed ti nv I OP_1C Inv NA "integer trap overflow clear") - -(dni ftira - "float trap always" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) - "ftira$pack $GRi,$s12" - (+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12) - (trap-semantics (const BI 1) GRi s12) - ((fr400 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(dni ftino - "float trap never" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) - "ftino$pack" - (+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null)) - (trap-semantics (const BI 0) GRi s12) - ((fr400 (unit u-trap)) (fr450 (unit u-trap)) - (fr500 (unit u-trap)) (fr550 (unit u-trap))) -) - -(trap-immed fti ne F OP_1D Fne FR-ACCESS "float trap not equal") -(trap-immed fti eq F OP_1D Feq FR-ACCESS "float trap equal") -(trap-immed fti lg F OP_1D Flg FR-ACCESS "float trap greater or less") -(trap-immed fti ue F OP_1D Fue FR-ACCESS "float trap unordered or equal") -(trap-immed fti ul F OP_1D Ful FR-ACCESS "float trap unordered or less") -(trap-immed fti ge F OP_1D Fge FR-ACCESS "float trap greater or equal") -(trap-immed fti lt F OP_1D Flt FR-ACCESS "float trap less") -(trap-immed fti uge F OP_1D Fuge FR-ACCESS "float trap unordered greater or equal") -(trap-immed fti ug F OP_1D Fug FR-ACCESS "float trap unordered or greater") -(trap-immed fti le F OP_1D Fle FR-ACCESS "float trap less or equal") -(trap-immed fti gt F OP_1D Fgt FR-ACCESS "float trap greater") -(trap-immed fti ule F OP_1D Fule FR-ACCESS "float trap unordered less or equal") -(trap-immed fti u F OP_1D Fu FR-ACCESS "float trap unordered") -(trap-immed fti o F OP_1D Fo FR-ACCESS "float trap ordered") - -(dni break - "break trap" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1)) - "break$pack" - (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null)) - (sequence () - ; This is defered to frv_break because for the breakpoint - ; case we want to change as little of the machine state as - ; possible. - ; - ; BPCSR=PC - ; BPSR.BS=PSR.S - ; BPSR.BET=PSR.ET - ; PSR.S=1 - ; PSR.ET=0 - ; TBR.TT=0xff - ; PC=TBR - ; We still should indicate what is modified by this insn. - (clobber (spr-bpcsr)) - (clobber bpsr_bs) - (clobber bpsr_bet) - (clobber psr_s) - (clobber psr_et) - (clobber tbr_tt) - (c-call VOID "frv_break")) - () -) - -(dni mtrap - "media trap" - ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) - (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) - "mtrap$pack" - (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null)) - (c-call VOID "frv_mtrap") - () -) - -(define-pmacro (condition-code-logic name operation ope comment) - (dni name - (comment) - ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) - (FR400-MAJOR B-6) (FR450-MAJOR B-6)) - (.str name "$pack $CRi,$CRj,$CRk") - (+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj) - (set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj)) - () - ) -) -(define-pmacro (op-andcr) 0) -(define-pmacro (op-orcr) 1) -(define-pmacro (op-xorcr) 2) -(define-pmacro (op-nandcr) 3) -(define-pmacro (op-norcr) 4) -(define-pmacro (op-andncr) 5) -(define-pmacro (op-orncr) 6) -(define-pmacro (op-nandncr) 7) -(define-pmacro (op-norncr) 8) - -(define-pmacro (cr-true) 3) -(define-pmacro (cr-false) 2) -(define-pmacro (cr-undefined) 0) - -(condition-code-logic andcr (op-andcr) OPE1_08 "and condition code regs") -(condition-code-logic orcr (op-orcr) OPE1_09 "or condition code regs") -(condition-code-logic xorcr (op-xorcr) OPE1_0A "xor condition code regs") -(condition-code-logic nandcr (op-nandcr) OPE1_0C "nand condition code regs") -(condition-code-logic norcr (op-norcr) OPE1_0D "nor condition code regs") -(condition-code-logic andncr (op-andncr) OPE1_10 "andn condition code regs") -(condition-code-logic orncr (op-orncr) OPE1_11 "orn condition code regs") -(condition-code-logic nandncr (op-nandncr) OPE1_14 "nandn condition code regs") -(condition-code-logic norncr (op-norncr) OPE1_15 "norn condition code regs") - -(dni notcr - ("not cccr register") - ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) - (FR400-MAJOR B-6) (FR450-MAJOR B-6)) - (.str notcr "$pack $CRj,$CRk") - (+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj) - (set CRk (xor CRj 1)) - () -) - -(define-pmacro (check-semantics cond cr) - (if cond (set cr (cr-true)) (set cr (cr-false))) -) - -(define-pmacro (check-int-condition-code prefix cc op cond comment) - (dni (.sym prefix cc) - (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5)) - (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int") - (+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3) - (check-semantics (cond ICCi_3) CRj_int) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) - ) -) - -(dni ckra - "check integer cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5)) - "ckra$pack $CRj_int" - (+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null)) - (check-semantics (const BI 1) CRj_int) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(dni ckno - "check integer cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5)) - "ckno$pack $CRj_int" - (+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null)) - (check-semantics (const BI 0) CRj_int) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(check-int-condition-code ck eq OP_08 Ieq "check integer cc equal") -(check-int-condition-code ck ne OP_08 Ine "check integer cc not equal") -(check-int-condition-code ck le OP_08 Ile "check integer cc less or equal") -(check-int-condition-code ck gt OP_08 Igt "check integer cc greater") -(check-int-condition-code ck lt OP_08 Ilt "check integer cc less") -(check-int-condition-code ck ge OP_08 Ige "check integer cc greater or equal") -(check-int-condition-code ck ls OP_08 Ils "check integer cc less or equal unsigned") -(check-int-condition-code ck hi OP_08 Ihi "check integer cc greater unsigned") -(check-int-condition-code ck c OP_08 Ic "check integer cc carry set") -(check-int-condition-code ck nc OP_08 Inc "check integer cc carry clear") -(check-int-condition-code ck n OP_08 In "check integer cc negative") -(check-int-condition-code ck p OP_08 Ip "check integer cc positive") -(check-int-condition-code ck v OP_08 Iv "check integer cc overflow set") -(check-int-condition-code ck nv OP_08 Inv "check integer cc overflow clear") - -(define-pmacro (check-float-condition-code prefix cc op cond comment) - (dni (.sym prefix cc) - (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) - (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float") - (+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3) - (check-semantics (cond FCCi_3) CRj_float) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) - ) -) - -(dni fckra - "check float cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) - "fckra$pack $CRj_float" - (+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3) - (check-semantics (const BI 1) CRj_float) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(dni fckno - "check float cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) - "fckno$pack $CRj_float" - (+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3) - (check-semantics (const BI 0) CRj_float) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(check-float-condition-code fck ne OP_09 Fne "check float cc not equal") -(check-float-condition-code fck eq OP_09 Feq "check float cc equal") -(check-float-condition-code fck lg OP_09 Flg "check float cc greater or less") -(check-float-condition-code fck ue OP_09 Fue "check float cc unordered or equal") -(check-float-condition-code fck ul OP_09 Ful "check float cc unordered or less") -(check-float-condition-code fck ge OP_09 Fge "check float cc greater or equal") -(check-float-condition-code fck lt OP_09 Flt "check float cc less") -(check-float-condition-code fck uge OP_09 Fuge "check float cc unordered greater or equal") -(check-float-condition-code fck ug OP_09 Fug "check float cc unordered or greater") -(check-float-condition-code fck le OP_09 Fle "check float cc less or equal") -(check-float-condition-code fck gt OP_09 Fgt "check float cc greater") -(check-float-condition-code fck ule OP_09 Fule "check float cc unordered less or equal") -(check-float-condition-code fck u OP_09 Fu "check float cc unordered") -(check-float-condition-code fck o OP_09 Fo "check float cc ordered") - -(define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment) - (dni (.sym prefix cc) - (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) - (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond") - (+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope - (misc-null-9) ICCi_3) - (if (eq CCi (or cond 2)) - (check-semantics (test ICCi_3) CRj_int) - (set CRj_int (cr-undefined))) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) - ) -) - -(dni cckra - "conditional check integer cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) - "cckra$pack $CRj_int,$CCi,$cond" - (+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0 - (misc-null-9) (ICCi_3-null)) - (if (eq CCi (or cond 2)) - (check-semantics (const BI 1) CRj_int) - (set CRj_int (cr-undefined))) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(dni cckno - "conditional check integer cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) - "cckno$pack $CRj_int,$CCi,$cond" - (+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0 - (misc-null-9) (ICCi_3-null)) - (if (eq CCi (or cond 2)) - (check-semantics (const BI 0) CRj_int) - (set CRj_int (cr-undefined))) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(conditional-check-int-condition-code cck eq OP_6A OPE4_0 Ieq "check integer cc equal") -(conditional-check-int-condition-code cck ne OP_6A OPE4_0 Ine "check integer cc not equal") -(conditional-check-int-condition-code cck le OP_6A OPE4_0 Ile "check integer cc less or equal") -(conditional-check-int-condition-code cck gt OP_6A OPE4_0 Igt "check integer cc greater") -(conditional-check-int-condition-code cck lt OP_6A OPE4_0 Ilt "check integer cc less") -(conditional-check-int-condition-code cck ge OP_6A OPE4_0 Ige "check integer cc greater or equal") -(conditional-check-int-condition-code cck ls OP_6A OPE4_0 Ils "check integer cc less or equal unsigned") -(conditional-check-int-condition-code cck hi OP_6A OPE4_0 Ihi "check integer cc greater unsigned") -(conditional-check-int-condition-code cck c OP_6A OPE4_0 Ic "check integer cc carry set") -(conditional-check-int-condition-code cck nc OP_6A OPE4_0 Inc "check integer cc carry clear") -(conditional-check-int-condition-code cck n OP_6A OPE4_0 In "check integer cc negative") -(conditional-check-int-condition-code cck p OP_6A OPE4_0 Ip "check integer cc positive") -(conditional-check-int-condition-code cck v OP_6A OPE4_0 Iv "check integer cc overflow set") -(conditional-check-int-condition-code cck nv OP_6A OPE4_0 Inv "check integer cc overflow clear") - -(define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment) - (dni (.sym prefix cc) - (comment) - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) - (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond") - (+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope - (misc-null-9) FCCi_3) - (if (eq CCi (or cond 2)) - (check-semantics (test FCCi_3) CRj_float) - (set CRj_float (cr-undefined))) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) - ) -) - -(dni cfckra - "conditional check float cc always" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) - "cfckra$pack $CRj_float,$CCi,$cond" - (+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1 - (misc-null-9) (FCCi_3-null)) - (if (eq CCi (or cond 2)) - (check-semantics (const BI 1) CRj_float) - (set CRj_float (cr-undefined))) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(dni cfckno - "conditional check float cc never" - ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) - (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) - "cfckno$pack $CRj_float,$CCi,$cond" - (+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1 - (misc-null-9) (FCCi_3-null)) - (if (eq CCi (or cond 2)) - (check-semantics (const BI 0) CRj_float) - (set CRj_float (cr-undefined))) - ((fr400 (unit u-check)) (fr450 (unit u-check)) - (fr500 (unit u-check)) (fr550 (unit u-check))) -) - -(conditional-check-float-condition-code cfck ne OP_6A OPE4_1 Fne "check float cc not equal") -(conditional-check-float-condition-code cfck eq OP_6A OPE4_1 Feq "check float cc equal") -(conditional-check-float-condition-code cfck lg OP_6A OPE4_1 Flg "check float cc greater or less") -(conditional-check-float-condition-code cfck ue OP_6A OPE4_1 Fue "check float cc unordered or equal") -(conditional-check-float-condition-code cfck ul OP_6A OPE4_1 Ful "check float cc unordered or less") -(conditional-check-float-condition-code cfck ge OP_6A OPE4_1 Fge "check float cc greater or equal") -(conditional-check-float-condition-code cfck lt OP_6A OPE4_1 Flt "check float cc less") -(conditional-check-float-condition-code cfck uge OP_6A OPE4_1 Fuge "check float cc unordered greater or equal") -(conditional-check-float-condition-code cfck ug OP_6A OPE4_1 Fug "check float cc unordered or greater") -(conditional-check-float-condition-code cfck le OP_6A OPE4_1 Fle "check float cc less or equal") -(conditional-check-float-condition-code cfck gt OP_6A OPE4_1 Fgt "check float cc greater") -(conditional-check-float-condition-code cfck ule OP_6A OPE4_1 Fule "check float cc unordered less or equal") -(conditional-check-float-condition-code cfck u OP_6A OPE4_1 Fu "check float cc unordered") -(conditional-check-float-condition-code cfck o OP_6A OPE4_1 Fo "check float cc ordered") - -(dni cjmpl - "conditional jump and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) - (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL) - "cjmpl$pack @($GRi,$GRj),$CCi,$cond" - (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (jump-and-link-semantics GRi GRj LI)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(dni ccalll - "conditional call and link" - ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) - (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL) - "ccalll$pack @($GRi,$GRj),$CCi,$cond" - (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj) - (if (eq CCi (or cond 2)) - (jump-and-link-semantics GRi GRj LI)) - ((fr400 (unit u-branch)) (fr450 (unit u-branch)) - (fr500 (unit u-branch)) (fr550 (unit u-branch))) -) - -(define-pmacro (cache-invalidate name cache all op ope profile comment) - (dni name - (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - (.str name "$pack @($GRi,$GRj)") - (+ pack (rd-null) op GRi ope GRj) - (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all) - profile - ) -) - -(cache-invalidate ici insn 0 OP_03 OPE1_38 - ((fr400 (unit u-ici)) (fr450 (unit u-ici)) - (fr500 (unit u-ici)) (fr550 (unit u-ici))) - "invalidate insn cache") -(cache-invalidate dci data 0 OP_03 OPE1_3C - ((fr400 (unit u-dci)) (fr450 (unit u-dci)) - (fr500 (unit u-dci)) (fr550 (unit u-dci))) - "invalidate data cache") - -(define-pmacro (cache-invalidate-entry name cache op ope profile comment) - (dni name - (comment) - ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - (.str name "$pack @($GRi,$GRj),$ae") - (+ pack (misc-null-1) ae op GRi ope GRj) - (if (eq ae 0) - (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) -1) ; Invalid ae setting for this insn - (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) ae)) - profile - ) -) - -(cache-invalidate-entry icei insn OP_03 OPE1_39 - ((fr400 (unit u-ici)) (fr450 (unit u-ici)) - (fr550 (unit u-ici))) - "invalidate insn cache entry") -(cache-invalidate-entry dcei data OP_03 OPE1_3A - ((fr400 (unit u-dci)) (fr450 (unit u-dci)) - (fr550 (unit u-dci))) - "invalidate data cache entry") - -(dni dcf - "Data cache flush" - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - "dcf$pack @($GRi,$GRj)" - (+ pack (rd-null) OP_03 GRi OPE1_3D GRj) - (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0) - ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) - (fr500 (unit u-dcf)) (fr550 (unit u-dcf))) -) - -(dni dcef - "Data cache entry flush" - ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - "dcef$pack @($GRi,$GRj),$ae" - (+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj) - (if (eq ae 0) - (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1) - (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae)) - ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) (fr550 (unit u-dcf))) -) - -(define-pmacro (write-TLB name insn op ope comment) - (dni name - (comment) - ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) - (.str insn "$pack $GRk,@($GRi,$GRj)") - (+ pack GRk op GRi ope GRj) - (nop) ; for now - () - ) -) - -(write-TLB witlb witlb OP_03 OPE1_32 "write for insn TLB") -(write-TLB wdtlb wdtlb OP_03 OPE1_36 "write for data TLB") - -(define-pmacro (invalidate-TLB name insn op ope comment) - (dni name - (comment) - ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) - (.str insn "$pack @($GRi,$GRj)") - (+ pack (rd-null) op GRi ope GRj) - (nop) ; for now - () - ) -) - -(invalidate-TLB itlbi itlbi OP_03 OPE1_33 "invalidate insn TLB") -(invalidate-TLB dtlbi dtlbi OP_03 OPE1_37 "invalidate data TLB") - -(define-pmacro (cache-preload name cache pipe attrs op ope profile comment) - (dni name - (comment) - (.splice (UNIT pipe) (FR500-MAJOR C-2) - (FR400-MAJOR C-2) (.unsplice attrs)) - (.str name "$pack $GRi,$GRj,$lock") - (+ pack (misc-null-1) lock op GRi ope GRj) - (c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock) - profile - ) -) - -(cache-preload icpl insn C ((FR550-MAJOR C-2) (FR450-MAJOR C-2)) OP_03 OPE1_30 - ((fr400 (unit u-icpl)) (fr450 (unit u-icpl)) - (fr500 (unit u-icpl)) (fr550 (unit u-icpl))) - "preload insn cache") -(cache-preload dcpl data DCPL ((FR550-MAJOR I-8) (FR450-MAJOR I-2)) OP_03 OPE1_34 - ((fr400 (unit u-dcpl)) (fr450 (unit u-dcpl)) - (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl))) - "preload data cache") - -(define-pmacro (cache-unlock name cache op ope profile comment) - (dni name - (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - (.str name "$pack $GRi") - (+ pack (rd-null) op GRi ope (GRj-null)) - (c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi) - profile - ) -) - -(cache-unlock icul insn OP_03 OPE1_31 - ((fr400 (unit u-icul)) (fr450 (unit u-icul)) - (fr500 (unit u-icul)) (fr550 (unit u-icul))) - "unlock insn cache") -(cache-unlock dcul data OP_03 OPE1_35 - ((fr400 (unit u-dcul)) (fr450 (unit u-dcul)) - (fr500 (unit u-dcul)) (fr550 (unit u-dcul))) - "unlock data cache") - -(define-pmacro (barrier name insn op ope profile comment) - (dni name - (comment) - ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) - (FR400-MAJOR C-2) (FR450-MAJOR C-2)) - (.str insn "$pack") - (+ pack (rd-null) op (rs-null) ope (GRj-null)) - (nop) ; sufficient implementation - profile - ) -) - -(barrier bar bar OP_03 OPE1_3E - ((fr400 (unit u-barrier)) (fr450 (unit u-barrier)) - (fr500 (unit u-barrier))) - "barrier") -(barrier membar membar OP_03 OPE1_3F - ((fr400 (unit u-membar)) (fr450 (unit u-membar)) - (fr500 (unit u-membar))) - "memory barrier") - -; Load real address instructions -(define-pmacro (load-real-address name insn what op ope) - (dni name - (.str "Load real address of " what) - ((UNIT C) (FR450-MAJOR C-2) (MACH fr450)) - (.str insn "$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS") - (+ pack GRk op GRi ope LRAE LRAD LRAS (LRA-null)) - (nop) ; not simulated - () - ) -) - -(load-real-address lrai "lrai" "instruction" OP_03 OPE1_20) -(load-real-address lrad "lrad" "data" OP_03 OPE1_21) - -(dni tlbpr - "TLB Probe" - ((UNIT C) (FR450-MAJOR C-2) (MACH fr450)) - "tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL" - (+ pack (TLBPR-null) TLBPRopx TLBPRL OP_03 GRi OPE1_24 GRj) - (nop) ; not simulated - () -) - -; Coprocessor operations -(define-pmacro (cop-op num op) - (dni (.sym cop num) - "Coprocessor operation" - ((UNIT C) (FR500-MAJOR C-2) (MACH frv)) - (.str "cop" num "$pack $s6_1,$CPRi,$CPRj,$CPRk") - (+ pack CPRk op CPRi s6_1 CPRj) - (nop) ; sufficient implementation - () - ) -) - -(cop-op 1 OP_7E) -(cop-op 2 OP_7F) - -(define-pmacro (clear-ne-flag-semantics target_index is_float) - (c-call VOID "@cpu@_clear_ne_flags" target_index is_float) -) - -(define-pmacro (clear-ne-flag-r name op ope reg is_float attr profile comment) - (dni name - (comment) - ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) - (.str name "$pack $" reg "k") - (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) - (sequence () - ; hack to get this referenced for profiling - (c-raw-call VOID "frv_ref_SI" (.sym reg k)) - (clear-ne-flag-semantics (index-of (.sym reg k)) is_float)) - profile - ) -) - -(clear-ne-flag-r clrgr OP_0A OPE1_00 GR 0 NA - ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) - "Clear GR NE flag") -(clear-ne-flag-r clrfr OP_0A OPE1_02 FR 1 FR-ACCESS - ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) - "Clear FR NE flag") - -(define-pmacro (clear-ne-flag-all name op ope is_float attr profile comment) - (dni name - (comment) - ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) - (.str name "$pack") - (+ pack (rd-null) op (rs-null) ope (GRj-null)) - (clear-ne-flag-semantics -1 is_float) - profile - ) -) - -(clear-ne-flag-all clrga OP_0A OPE1_01 0 NA - ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) - "Clear GR NE flag ALL") -(clear-ne-flag-all clrfa OP_0A OPE1_03 1 FR-ACCESS - ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) - "Clear FR NE flag ALL") - -(define-pmacro (commit-semantics target_index is_float) - (c-call VOID "@cpu@_commit" target_index is_float) -) - -(define-pmacro (commit-r name op ope reg is_float attr comment) - (dni name - (comment) - ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) - (.str name "$pack $" reg "k") - (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) - (commit-semantics (index-of (.sym reg k)) is_float) - ((fr500 (unit u-commit)) (fr550 (unit u-commit))) - ) -) - -(commit-r commitgr OP_0A OPE1_04 GR 0 NA "commit exceptions, specific GR") -(commit-r commitfr OP_0A OPE1_06 FR 1 FR-ACCESS "commit exceptions, specific FR") - -(define-pmacro (commit name op ope is_float attr comment) - (dni name - (comment) - ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) - (.str name "$pack") - (+ pack (rd-null) op (rs-null) ope (GRj-null)) - (commit-semantics -1 is_float) - ((fr500 (unit u-commit)) (fr550 (unit u-commit))) - ) -) - -(commit commitga OP_0A OPE1_05 0 NA "commit exceptions, any GR") -(commit commitfa OP_0A OPE1_07 1 FR-ACCESS "commit exceptions, any FR") - -(define-pmacro (floating-point-conversion - name op ope conv mode src targ attr comment) - (dni name - (comment) - (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) - (.str name "$pack $" src ",$" targ) - (+ pack targ op (rs-null) ope src) - (set targ (conv mode FPCONV-DEFAULT src)) - ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) - ) -) - -(floating-point-conversion fitos OP_79 OPE1_00 float SF FRintj FRk - ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - "Convert Integer to Single") -(floating-point-conversion fstoi OP_79 OPE1_01 fix SI FRj FRintk - ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - "Convert Single to Integer") -(floating-point-conversion fitod OP_7A OPE1_00 float DF FRintj FRdoublek - ((MACH frv)) - "Convert Integer to Double") -(floating-point-conversion fdtoi OP_7A OPE1_01 fix SI FRdoublej FRintk - ((MACH frv)) - "Convert Double to Integer") - -(define-pmacro (floating-point-dual-conversion - name op ope conv mode src src_hw targ targ_hw attr comment) - (dni name - (comment) - ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) attr) - (.str name "$pack $" src ",$" targ) - (+ pack targ op (rs-null) ope src) - (sequence () - (set targ (conv mode FPCONV-DEFAULT src)) - (set (nextreg targ_hw targ 1) - (conv mode FPCONV-DEFAULT (nextreg src_hw src 1)))) - ((fr500 (unit u-float-dual-convert))) - ) -) - -(floating-point-dual-conversion fditos OP_79 OPE1_10 float SF FRintj h-fr_int FRk h-fr NA "Dual Convert Integer to Single") -(floating-point-dual-conversion fdstoi OP_79 OPE1_11 fix SI FRj h-fr FRintk h-fr_int NA "Dual Convert Single to Integer") - -(define-pmacro (ne-floating-point-dual-conversion - name op ope conv mode src src_hw targ targ_hw attr comment) - (dni name - (comment) - ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) NON-EXCEPTING attr) - (.str name "$pack $" src ",$" targ) - (+ pack targ op (rs-null) ope src) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of targ)) - (set targ (conv mode FPCONV-DEFAULT src)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) - (set (nextreg targ_hw targ 1) - (conv mode FPCONV-DEFAULT (nextreg src_hw src 1)))) - ((fr500 (unit u-float-dual-convert))) - ) -) - -(ne-floating-point-dual-conversion nfditos OP_79 OPE1_30 float SF FRintj h-fr_int FRk h-fr NA "Non excepting dual Convert Integer to Single") -(ne-floating-point-dual-conversion nfdstoi OP_79 OPE1_31 fix SI FRj h-fr FRintk h-fr_int NA "Non excepting dual Convert Single to Integer") - -(define-pmacro (conditional-floating-point-conversion - name op ope conv mode src targ comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack $" src ",$" targ ",$CCi,$cond") - (+ pack targ op (rs-null) CCi cond ope src) - (if (eq CCi (or cond 2)) - (set targ (conv mode FPCONV-DEFAULT src))) - ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) - ) -) - -(conditional-floating-point-conversion cfitos OP_6B OPE4_0 float SF FRintj FRk "Conditional convert Integer to Single") -(conditional-floating-point-conversion cfstoi OP_6B OPE4_1 fix SI FRj FRintk "Conditional convert Single to Integer") - -(define-pmacro (ne-floating-point-conversion - name op ope conv mode src targ comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack $" src ",$" targ) - (+ pack targ op (rs-null) ope src) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of targ)) - (set targ (conv mode FPCONV-DEFAULT src))) - ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) - ) -) - -(ne-floating-point-conversion nfitos OP_79 OPE1_20 float SF FRintj FRk "NE convert Integer to Single") -(ne-floating-point-conversion nfstoi OP_79 OPE1_21 fix SI FRj FRintk "NE convert Single to Integer") - -(register-transfer fmovs OP_79 OPE1_02 - FRj FRk FMALL - ((FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - ((fr500 (unit u-fr2fr))) - "Move Single Float") -(register-transfer fmovd OP_7A OPE1_02 - ; TODO -- unit doesn't handle extra register - FRdoublej FRdoublek FM01 - ((FR500-MAJOR F-1) (MACH frv)) - ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) - "Move Double Float") - -(dni fdmovs - "Dual move single float" - ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) - "fdmovs$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_12 FRj) - (sequence () - (set FRk FRj) - (set (nextreg h-fr FRk 1) (nextreg h-fr FRj 1))) - ; TODO -- unit doesn't handle extra register - ((fr500 (unit u-fr2fr))) -) - -(conditional-register-transfer cfmovs OP_6C OPE4_0 FRj FRk FMALL - ((FR500-MAJOR F-1) (FR550-MAJOR F-2) - (MACH simple,tomcat,fr500,fr550,frv)) - ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) - "Conditional move Single Float") - -(define-pmacro (floating-point-neg name src targ op ope attr comment) - (dni name - (comment) - (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) - (.str name "$pack $" src ",$" targ) - (+ pack src op (rs-null) ope targ) - (set targ (neg src)) - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - ) -) - -(floating-point-neg fnegs FRj FRk OP_79 OPE1_03 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Floating point negate, single") -(floating-point-neg fnegd FRdoublej FRdoublek OP_7A OPE1_03 ((MACH frv)) "Floating point negate, double") - -(dni fdnegs - "Floating point dual negate, single" - ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) - "fdnegs$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_13 FRj) - (sequence () - (set FRk (neg FRj)) - (set (nextreg h-fr FRk 1) (neg (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-arith))) -) - -(dni cfnegs - "Conditional floating point negate, single" - ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - "cfnegs$pack $FRj,$FRk,$CCi,$cond" - (+ pack FRj OP_6C (rs-null) CCi cond OPE4_1 FRk) - (if (eq CCi (or cond 2)) - (set FRk (neg FRj))) - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) -) - -(define-pmacro (float-abs name src targ op ope attr comment) - (dni name - (comment) - (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) - (.str name "$pack $" src ",$" targ ) - (+ pack targ op (rs-null) ope src) - (set targ (abs src)) - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - ) -) - -(float-abs fabss FRj FRk OP_79 OPE1_04 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Float absolute value, single") -(float-abs fabsd FRdoublej FRdoublek OP_7A OPE1_04 ((MACH frv)) "Float absolute value, double") - -(dni fdabss - "Floating point dual absolute value, single" - ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) - "fdabss$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_14 FRj) - (sequence () - (set FRk (abs FRj)) - (set (nextreg h-fr FRk 1) (abs (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-arith))) -) - -(dni cfabss - "Conditional floating point absolute value, single" - ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - "cfabss$pack $FRj,$FRk,$CCi,$cond" - (+ pack FRj OP_6C (rs-null) CCi cond OPE4_2 FRk) - (if (eq CCi (or cond 2)) - (set FRk (abs FRj))) - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) -) - -(dni fsqrts - "Square root single" - ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) - "fsqrts$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_05 FRj) - (set FRk (sqrt SF FRj)) - ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) -) - -(dni fdsqrts - "Dual square root single" - ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4)) - "fdsqrts$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_15 FRj) - (sequence () - (set FRk (sqrt SF FRj)) - (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-sqrt))) -) - -(dni nfdsqrts - "Non excepting Dual square root single" - ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4) NON-EXCEPTING) - "nfdsqrts$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_35 FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (sqrt SF FRj)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) - (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-sqrt))) -) - -(dni fsqrtd - "Square root double" - ((UNIT FM01) (FR500-MAJOR F-4) (MACH frv)) - "fsqrtd$pack $FRdoublej,$FRdoublek" - (+ pack FRdoublek OP_7A (rs-null) OPE1_05 FRdoublej) - (set FRdoublek (sqrt DF FRdoublej)) - ((fr500 (unit u-float-sqrt))) -) - -(dni cfsqrts - "Conditional square root single" - ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) - "cfsqrts$pack $FRj,$FRk,$CCi,$cond" - (+ pack FRk OP_6E (rs-null) CCi cond OPE4_2 FRj) - (if (eq CCi (or cond 2)) - (set FRk (sqrt SF FRj))) - ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) -) - -(dni nfsqrts - "Non exception square root, single" - ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) - "nfsqrts$pack $FRj,$FRk" - (+ pack FRk OP_79 (rs-null) OPE1_25 FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (sqrt SF FRj))) - ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) -) - -(define-pmacro (float-binary-op-s name pipe attr operation op ope comment) - (dni name - (comment) - (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) (.unsplice attr)) - (.str name "$pack $FRi,$FRj,$FRk") - (+ pack FRk op FRi ope FRj) - (set FRk (operation FRi FRj)) - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - ) -) - -(float-binary-op-s fadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_06 "add single float") -(float-binary-op-s fsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_07 "sub single float") -(float-binary-op-s fmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_08 "mul single float") - -(dni fdivs - "div single float" - ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) - "fdivs$pack $FRi,$FRj,$FRk" - (+ pack FRk OP_79 FRi OPE1_09 FRj) - (set FRk (div FRi FRj)) - ((fr500 (unit u-float-div)) - (fr550 (unit u-float-div))) -) - -(define-pmacro (float-binary-op-d name operation op ope major comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR major) (MACH frv)) - (.str name "$pack $FRdoublei,$FRdoublej,$FRdoublek") - (+ pack FRdoublek op FRdoublei ope FRdoublej) - (set FRdoublek (operation FRdoublei FRdoublej)) - ((fr500 (unit u-float-arith))) - ) -) - -(float-binary-op-d faddd add OP_7A OPE1_06 F-2 "add double float") -(float-binary-op-d fsubd sub OP_7A OPE1_07 F-2 "sub double float") -(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float") -(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float") - -(define-pmacro (conditional-float-binary-op name pipe attr operation op ope profile comment) - (dni name - (comment) - (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) - (.unsplice attr)) - (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") - (+ pack FRk op FRi CCi cond ope FRj) - (if (eq CCi (or cond 2)) - (set FRk (operation FRi FRj))) - profile - ) -) - -(conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_6D OPE4_0 - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - "cond add single") -(conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_6D OPE4_1 - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - "cond sub single") -(conditional-float-binary-op cfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_6E OPE4_0 - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - "cond mul single") -(conditional-float-binary-op cfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_6E OPE4_1 - ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) - "cond div single") - -(define-pmacro (ne-float-binary-op name pipe attr operation op ope profile comment) - (dni name - (comment) - (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) - (.unsplice attr)) - (.str name "$pack $FRi,$FRj,$FRk") - (+ pack FRk op FRi ope FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (operation FRi FRj))) - profile - ) -) - -(ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_26 - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - "ne add single") -(ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_27 - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - "ne sub single") -(ne-float-binary-op nfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_28 - ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) - "ne mul single") -(ne-float-binary-op nfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_79 OPE1_29 - ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) - "ne div single") - -(define-pmacro (fcc-eq) 8) -(define-pmacro (fcc-lt) 4) -(define-pmacro (fcc-gt) 2) -(define-pmacro (fcc-uo) 1) - -(define-pmacro (compare-and-set-fcc arg1 arg2 fcc) - (if (gt arg1 arg2) - (set fcc (fcc-gt)) - (if (eq arg1 arg2) - (set fcc (fcc-eq)) - (if (lt arg1 arg2) - (set fcc (fcc-lt)) - (set fcc (fcc-uo))))) -) - -(dni fcmps - "compare single float" - ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - "fcmps$pack $FRi,$FRj,$FCCi_2" - (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_0A FRj) - (compare-and-set-fcc FRi FRj FCCi_2) - ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) -) - -(dni fcmpd - "compare double float" - ((UNIT FMALL) (FR500-MAJOR F-2) (MACH frv)) - "fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2" - (+ pack (cond-null) FCCi_2 OP_7A FRdoublei OPE1_0A FRdoublej) - (compare-and-set-fcc FRdoublei FRdoublej FCCi_2) - ((fr500 (unit u-float-compare))) -) - -(dni cfcmps - "Conditional compare single, float" - ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) - "cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond" - (+ pack (cond-null) FCCi_2 OP_6D FRi CCi cond OPE4_2 FRj) - (if (eq CCi (or cond 2)) - (compare-and-set-fcc FRi FRj FCCi_2)) - ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) -) - -(dni fdcmps - "float dual compare single" - ((UNIT FMALL) (FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) - "fdcmps$pack $FRi,$FRj,$FCCi_2" - (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_1A FRj) - (sequence () - (compare-and-set-fcc FRi FRj FCCi_2) - (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) - (nextreg h-fccr FCCi_2 1))) - ((fr500 (unit u-float-dual-compare)) (fr550 (unit u-float-dual-compare))) -) - -(define-pmacro (float-mul-with-add name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) - (.str name "$pack $" arg1 ",$" arg2 ",$" targ) - (+ pack targ op arg1 ope arg2) - (set targ (add_sub (mul arg1 arg2) targ)) - ((fr500 (unit u-float-dual-arith))) - ) -) - -(float-mul-with-add fmadds add FRi FRj FRk OP_79 OPE1_0B "mul with add, single") -(float-mul-with-add fmsubs sub FRi FRj FRk OP_79 OPE1_0C "mul with sub, single") - -(float-mul-with-add fmaddd add FRdoublei FRdoublej FRdoublek OP_7A OPE1_0B "mul with add, double") -(float-mul-with-add fmsubd sub FRdoublei FRdoublej FRdoublek OP_7A OPE1_0C "mul with sub, double") - -(dni fdmadds - "Float dual multiply with add" - ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) - "fdmadds$pack $FRi,$FRj,$FRk" - (+ pack FRk OP_79 FRi OPE1_1B FRj) - (sequence () - (set FRk (add (mul FRi FRj) FRk)) - (set (nextreg h-fr FRk 1) - (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) - (nextreg h-fr FRk 1)))) - ; TODO dual registers not referenced for profiling - ((fr500 (unit u-float-dual-arith))) -) - -(dni nfdmadds - "Non excepting float dual multiply with add" - ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) - "nfdmadds$pack $FRi,$FRj,$FRk" - (+ pack FRk OP_79 FRi OPE1_3B FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (add (mul FRi FRj) FRk)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) - (set (nextreg h-fr FRk 1) - (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) - (nextreg h-fr FRk 1)))) - ; TODO dual registers not referenced for profiling - ((fr500 (unit u-float-dual-arith))) -) - -(define-pmacro (conditional-float-mul-with-add - name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) CONDITIONAL) - (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") - (+ pack FRk op FRi CCi cond ope FRj) - (if (eq CCi (or cond 2)) - (set targ (add_sub (mul arg1 arg2) targ))) - ((fr500 (unit u-float-dual-arith))) - ) -) - -(conditional-float-mul-with-add cfmadds add FRi FRj FRk OP_6F OPE4_0 "conditional mul with add, single") -(conditional-float-mul-with-add cfmsubs sub FRi FRj FRk OP_6F OPE4_1 "conditional mul with sub, single") - -(define-pmacro (ne-float-mul-with-add name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) NON-EXCEPTING) - (.str name "$pack $" arg1 ",$" arg2 ",$" targ) - (+ pack targ op arg1 ope arg2) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of targ)) - (set targ (add_sub (mul arg1 arg2) targ))) - ((fr500 (unit u-float-dual-arith))) - ) -) - -(ne-float-mul-with-add nfmadds add FRi FRj FRk OP_79 OPE1_2B "non excepting mul with add, single") -(ne-float-mul-with-add nfmsubs sub FRi FRj FRk OP_79 OPE1_2C "non excepting mul with sub, single") - -(define-pmacro (float-parallel-mul-add-semantics cond add_sub arg1 arg2 targ) - (if cond - (sequence () - (set targ (mul arg1 arg2)) - (set (nextreg h-fr targ 1) - (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))))) -) - -(define-pmacro (float-parallel-mul-add - name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack $" arg1 ",$" arg2 ",$" targ) - (+ pack targ op arg1 ope arg2) - (float-parallel-mul-add-semantics 1 add_sub arg1 arg2 targ) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) - ) -) - -(float-parallel-mul-add fmas add FRi FRj FRk OP_79 OPE1_0E "parallel mul/add, single") -(float-parallel-mul-add fmss sub FRi FRj FRk OP_79 OPE1_0F "parallel mul/sub, single") - -(define-pmacro (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) - (sequence () - (set targ (mul arg1 arg2)) - (set (nextreg h-fr targ 1) - (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) - (set (nextreg h-fr targ 2) - (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) - (set (nextreg h-fr targ 3) - (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) -) - -(define-pmacro (float-dual-parallel-mul-add - name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) - (.str name "$pack $" arg1 ",$" arg2 ",$" targ) - (+ pack targ op arg1 ope arg2) - (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) - () - ) -) - -(float-dual-parallel-mul-add fdmas add FRi FRj FRk OP_79 OPE1_1C "dual parallel mul/add, single") -(float-dual-parallel-mul-add fdmss sub FRi FRj FRk OP_79 OPE1_1D "dual parallel mul/sub, single") - -(define-pmacro (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of targ)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 2)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 3)) - (set targ (mul arg1 arg2)) - (set (nextreg h-fr targ 1) - (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) - (set (nextreg h-fr targ 2) - (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) - (set (nextreg h-fr targ 3) - (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) -) - -(define-pmacro (ne-float-dual-parallel-mul-add - name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) - (.str name "$pack $" arg1 ",$" arg2 ",$" targ) - (+ pack targ op arg1 ope arg2) - (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) - () - ) -) - -(ne-float-dual-parallel-mul-add nfdmas add FRi FRj FRk OP_79 OPE1_3C "non excepting dual parallel mul/add, single") -(ne-float-dual-parallel-mul-add nfdmss sub FRi FRj FRk OP_79 OPE1_3D "non excepting dual parallel mul/sub, single") - -(define-pmacro (conditional-float-parallel-mul-add name add_sub op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) CONDITIONAL (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") - (+ pack FRk op FRi CCi cond ope FRj) - (float-parallel-mul-add-semantics (eq CCi (or cond 2)) - add_sub FRi FRj FRk) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) - ) -) - -(conditional-float-parallel-mul-add cfmas add OP_6F OPE4_2 "conditional parallel mul/add, single") -(conditional-float-parallel-mul-add cfmss sub OP_6F OPE4_3 "conditional parallel mul/sub, single") - -(define-pmacro (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) - (sequence () - (set targ (ftrunc SF FPCONV-DEFAULT - (mul DF - (fext DF FPCONV-DEFAULT arg1) - (fext DF FPCONV-DEFAULT arg2)))) - (set (nextreg h-fr targ 1) - (ftrunc SF FPCONV-DEFAULT - (add_sub DF - (fext DF FPCONV-DEFAULT (nextreg h-fr arg1 1)) - (fext DF FPCONV-DEFAULT (nextreg h-fr arg2 1)))))) -) - -(define-pmacro (float-parallel-mul-add-double - name add_sub arg1 arg2 targ op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) - (.str name "$pack $" arg1 ",$" arg2 ",$" targ) - (+ pack targ op arg1 ope arg2) - (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) - () - ) -) - -(float-parallel-mul-add-double fmad add FRi FRj FRk OP_7A OPE1_0E "parallel mul/add, double") -(float-parallel-mul-add-double fmsd sub FRi FRj FRk OP_7A OPE1_0F "parallel mul/sub, double") - -(define-pmacro (ne-float-parallel-mul-add name add_sub op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) - (.str name "$pack $FRi,$FRj,$FRk") - (+ pack FRk op FRi ope FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (mul FRi FRj)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) - (set (nextreg h-fr FRk 1) - (add_sub (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) - ) -) - -(ne-float-parallel-mul-add nfmas add OP_79 OPE1_2E "ne parallel mul/add,single") -(ne-float-parallel-mul-add nfmss sub OP_79 OPE1_2F "ne parallel mul/sub,single") - -(define-pmacro (float-dual-arith name attr oper1 oper2 op ope comment) - (dni name - (comment) - (.splice (UNIT FM01) (.unsplice attr)) - (.str name "$pack $FRi,$FRj,$FRk") - (+ pack FRk op FRi ope FRj) - (sequence () - (set FRk (oper1 FRi FRj)) - (set (nextreg h-fr FRk 1) - (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) - ) -) - -(float-dual-arith fdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_16 "dual add, single") -(float-dual-arith fdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_17 "dual sub, single") -(float-dual-arith fdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_18 "dual mul, single") -(float-dual-arith fddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_19 "dual div,single") -(float-dual-arith fdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_1E "dual add/sub, single") - -(dni fdmulcs - "Float dual cross multiply single" - ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) - "fdmulcs$pack $FRi,$FRj,$FRk" - (+ pack FRk OP_79 FRi OPE1_1F FRj) - (sequence () - (set FRk (mul FRi (nextreg h-fr FRj 1))) - (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) -) - -(dni nfdmulcs - "NE float dual cross multiply single" - ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) - "nfdmulcs$pack $FRi,$FRj,$FRk" - (+ pack FRk OP_79 FRi OPE1_3F FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (mul FRi (nextreg h-fr FRj 1))) - (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) - (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) -) - -(define-pmacro (ne-float-dual-arith name attr oper1 oper2 op ope comment) - (dni name - (comment) - (.splice (UNIT FM01) (.unsplice attr)) - (.str name "$pack $FRi,$FRj,$FRk") - (+ pack FRk op FRi ope FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (set FRk (oper1 FRi FRj)) - (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) - (set (nextreg h-fr FRk 1) - (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) - ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) - ) -) - -(ne-float-dual-arith nfdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_36 "ne dual add, single") -(ne-float-dual-arith nfdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_37 "ne dual sub, single") -(ne-float-dual-arith nfdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_38 "ne dual mul, single") -(ne-float-dual-arith nfddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_39 "ne dual div,single") -(ne-float-dual-arith nfdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_3E "ne dual add/sub, single") - -(dni nfdcmps - "non-excepting dual float compare" - ((UNIT FM01) (FR500-MAJOR F-6) (MACH simple,tomcat,frv)) - "nfdcmps$pack $FRi,$FRj,$FCCi_2" - (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_3A FRj) - (sequence () - (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) - (compare-and-set-fcc FRi FRj FCCi_2) - (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) - (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) - (nextreg h-fccr FCCi_2 1))) - ((fr500 (unit u-float-dual-compare))) -) - -; Media Instructions -; -(define-pmacro (halfword hilo arg offset) - (reg (.sym h-fr_ hilo) (add (index-of arg) offset))) - -(dni mhsetlos - "Media set lower signed 12 bits" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mhsetlos$pack $u12,$FRklo" - (+ pack FRklo OP_78 OPE1_20 u12) - (set FRklo u12) - ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) - (fr550 (unit u-media-set (out FRintk FRklo)))) -) - -(dni mhsethis - "Media set upper signed 12 bits" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mhsethis$pack $u12,$FRkhi" - (+ pack FRkhi OP_78 OPE1_22 u12) - (set FRkhi u12) - ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) - (fr550 (unit u-media-set (out FRintk FRkhi)))) -) - -(dni mhdsets - "Media dual set halfword signed 12 bits" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mhdsets$pack $u12,$FRintk" - (+ pack FRintk OP_78 OPE1_24 u12) - (sequence () - ; hack to get FRintk passed to modelling functions - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (set (halfword hi FRintk 0) u12) - (set (halfword lo FRintk 0) u12)) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr550 (unit u-media-set))) -) - -(define-pmacro (set-5-semantics target value) - (sequence ((HI tmp)) - (set tmp target) - (set tmp (and tmp #x07ff)) - (set tmp (or tmp (sll (and s5 #x1f) 11))) - (set target tmp)) -) - -(define-pmacro (media-set-5 name hilo op ope comment) - (dni name - (comment) - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - (.str name "$pack $s5,$FRk" hilo) - (+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5) - (set-5-semantics (.sym FRk hilo) s5) - ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) - (fr550 (unit u-media-set (out FRintk (.sym FRk hilo))))) - ) -) - -(media-set-5 mhsetloh lo OP_78 OPE1_21 "Media set upper 5 bits lo") -(media-set-5 mhsethih hi OP_78 OPE1_23 "Media set upper 5 bits hi") - -(dni mhdseth - "Media dual set halfword upper 5 bits" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mhdseth$pack $s5,$FRintk" - (+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5) - (sequence () - ; hack to get FRintk passed to modelling functions - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (set-5-semantics (halfword hi FRintk 0) s5) - (set-5-semantics (halfword lo FRintk 0) s5)) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr550 (unit u-media-set))) -) - -(define-pmacro (media-logic-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - (.str name "$pack $FRinti,$FRintj,$FRintk") - (+ pack FRintk op FRinti ope FRintj) - (set FRintk (operation FRinti FRintj)) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(media-logic-r-r mand and OP_7B OPE1_00 "and reg/reg") -(media-logic-r-r mor or OP_7B OPE1_01 "or reg/reg") -(media-logic-r-r mxor xor OP_7B OPE1_02 "xor reg/reg") - -(define-pmacro (conditional-media-logic name operation op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) - (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") - (+ pack FRintk op FRinti CCi cond ope FRintj) - (if (eq CCi (or cond 2)) - (set FRintk (operation FRinti FRintj))) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(conditional-media-logic cmand and OP_70 OPE4_0 "conditional and reg/reg") -(conditional-media-logic cmor or OP_70 OPE4_1 "conditional or reg/reg") -(conditional-media-logic cmxor xor OP_70 OPE4_2 "conditional xor reg/reg") - -(dni mnot - ("mnot") - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - ("mnot$pack $FRintj,$FRintk") - (+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj) - (set FRintk (inv FRintj)) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(dni cmnot - ("cmnot") - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) - ("cmnot$pack $FRintj,$FRintk,$CCi,$cond") - (+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj) - (if (eq CCi (or cond 2)) - (set FRintk (inv FRintj))) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(define-pmacro (media-rotate-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - (.str name "$pack $FRinti,$u6,$FRintk") - (+ pack FRintk op FRinti ope u6) - (set FRintk (operation FRinti (and u6 #x1f))) - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(media-rotate-r-r mrotli rol OP_7B OPE1_04 "rotate left reg/reg") -(media-rotate-r-r mrotri ror OP_7B OPE1_05 "rotate right reg/reg") - -(define-pmacro (media-cut-r-r name arg op ope comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - (.str name "$pack $FRinti,$" arg ",$FRintk") - (+ pack FRintk op FRinti ope arg) - (set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg)) - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(media-cut-r-r mwcut FRintj OP_7B OPE1_06 "media cut") -(media-cut-r-r mwcuti u6 OP_7B OPE1_07 "media cut") - -(define-pmacro (media-cut-acc name arg op ope fr450-major comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR fr450-major)) - (.str name "$pack $ACC40Si,$" arg ",$FRintk") - (+ pack FRintk op ACC40Si ope arg) - (set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg)) - ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) - ) -) - -(media-cut-acc mcut FRintj OP_7B OPE1_2C M-1 "media accumulator cut reg") -(media-cut-acc mcuti s6 OP_7B OPE1_2E M-5 "media accumulator cut immed") - -(define-pmacro (media-cut-acc-ss name arg op ope fr450-major comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR fr450-major)) - (.str name "$pack $ACC40Si,$" arg ",$FRintk") - (+ pack FRintk op ACC40Si ope arg) - (set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg)) - ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) - ) -) - -(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D M-1 "media accumulator cut reg with saturation") -(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F M-5 "media accumulator cut immed with saturation") - -; Dual Media Instructions -; -(define-pmacro (register-unaligned register alignment) - (and (index-of register) (sub alignment 1)) -) - -(dni mdcutssi - "Media dual cut with signed saturation" - ((UNIT MDCUTSSI) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-6)) - "mdcutssi$pack $ACC40Si,$s6,$FRintkeven" - (+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6) - (if (register-unaligned ACC40Si 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (register-unaligned FRintkeven 2) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence () - (set FRintkeven (c-call SI "@cpu@_media_cut_ss" ACC40Si s6)) - (set (nextreg h-fr_int FRintkeven 1) - (c-call SI "@cpu@_media_cut_ss" - (nextreg h-acc40S ACC40Si 1) s6))))) - ((fr400 (unit u-media-4-acc-dual - (out FRintk FRintkeven))) - (fr450 (unit u-media-4-acc-dual - (out FRintk FRintkeven))) - (fr550 (unit u-media-3-acc-dual))) -) - -; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated -; so it will be passed to the unit modelers. YUCK!!!!! -(define-pmacro (extract-hilo reg1 off1 reg2 off2 arg1hi arg1lo arg2hi arg2lo) - (sequence () - (set arg1hi (add (halfword hi reg1 off1) (mul reg1 0))) - (set arg1lo (add (halfword lo reg1 off1) (mul reg1 0))) - (set arg2hi (add (halfword hi reg2 off2) (mul reg2 0))) - (set arg2lo (add (halfword lo reg2 off2) (mul reg2 0)))) -) - -(dni maveh - "Media dual average" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "maveh$pack $FRinti,$FRintj,$FRintk" - (+ pack FRintk OP_7B FRinti OPE1_08 FRintj) - (set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj)) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(define-pmacro (media-dual-shift name operation op ope profile comment) - (dni name - (comment) - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - (.str name "$pack $FRinti,$u6,$FRintk") - (+ pack FRintk op FRinti ope u6) - (sequence () - ; hack to get these referenced for profiling - (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (set (halfword hi FRintk 0) - (operation (halfword hi FRinti 0) (and u6 #xf))) - (set (halfword lo FRintk 0) - (operation (halfword lo FRinti 0) (and u6 #xf)))) - profile - ) -) - -(media-dual-shift msllhi sll OP_7B OPE1_09 - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - "Media dual shift left logical") -(media-dual-shift msrlhi srl OP_7B OPE1_0A - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - "Media dual shift right logical") -(media-dual-shift msrahi sra OP_7B OPE1_0B - ((fr400 (unit u-media-6)) (fr450 (unit u-media-6)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - "Media dual shift right arithmetic") - -(define-pmacro (media-dual-word-rotate-r-r name operation op ope comment) - (dni name - (comment) - ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - (.str name "$pack $FRintieven,$s6,$FRintkeven") - (+ pack FRintkeven op FRintieven ope s6) - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintkeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence () - (set FRintkeven (operation FRintieven (and s6 #x1f))) - (set (nextreg h-fr_int FRintkeven 1) - (operation (nextreg h-fr_int FRintieven 1) - (and s6 #x1f))))) - ((fr400 (unit u-media-3-quad - (in FRinti FRintieven) - (out FRintk FRintkeven))) - (fr450 (unit u-media-3-quad - (in FRinti FRintieven) - (out FRintk FRintkeven))) - (fr550 (unit u-media-quad))) - ) -) - -(media-dual-word-rotate-r-r mdrotli rol OP_78 OPE1_0B "rotate left reg/reg") - -(dni mcplhi - "Media bit concatenate, halfword" - ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mcplhi$pack $FRinti,$u6,$FRintk" - (+ pack FRintk OP_78 FRinti OPE1_0C u6) - (sequence ((HI arg1) (HI arg2) (HI shift)) - (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (set shift (and u6 #xf)) - (set arg1 (sll (halfword hi FRinti 0) shift)) - (if (ne shift 0) - (sequence () - (set arg2 (halfword hi FRinti 1)) - (set arg2 (srl HI (sll HI arg2 (sub 15 shift)) - (sub 15 shift))) - (set arg1 (or HI arg1 arg2)))) - (set (halfword hi FRintk 0) arg1)) - ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual)) - (fr550 (unit u-media-3-dual))) -) - -(dni mcpli - "Media bit concatenate, word" - ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mcpli$pack $FRinti,$u6,$FRintk" - (+ pack FRintk OP_78 FRinti OPE1_0D u6) - (sequence ((SI tmp) (SI shift)) - (set shift (and u6 #x1f)) - (set tmp (sll FRinti shift)) - (if (ne shift 0) - (sequence ((SI tmp1)) - (set tmp1 (srl (sll (nextreg h-fr_int FRinti 1) - (sub 31 shift)) - (sub 31 shift))) - (set tmp (or tmp tmp1)))) - (set FRintk tmp)) - ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual)) - (fr550 (unit u-media-3-dual))) -) - -(define-pmacro (saturate arg max min result) - (if (gt arg max) - (set result max) - (if (lt arg min) - (set result min) - (set result arg))) -) - -(dni msaths - "Media dual saturation signed" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "msaths$pack $FRinti,$FRintj,$FRintk" - (+ pack FRintk OP_7B FRinti OPE1_0C FRintj) - (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) - (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) - (saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0)) - (saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0))) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(dni mqsaths - "Media quad saturation signed" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven" - (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven) - (if (orif (register-unaligned FRintieven 2) - (orif (register-unaligned FRintjeven 2) - (register-unaligned FRintkeven 2))) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) - ; hack to get FRintkeven referenced as a target for profiling - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (extract-hilo FRintieven 0 FRintjeven 0 argihi argilo argjhi argjlo) - (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 0)) - (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 0)) - (extract-hilo FRintieven 1 FRintjeven 1 argihi argilo argjhi argjlo) - (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 1)) - (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 1)))) - ((fr400 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr450 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr550 (unit u-media-quad))) -) - -(define-pmacro (saturate-unsigned arg max result) - (if (gt arg max) - (set result max) - (set result arg)) -) - -(dni msathu - "Media dual saturation unsigned" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "msathu$pack $FRinti,$FRintj,$FRintk" - (+ pack FRintk OP_7B FRinti OPE1_0D FRintj) - (sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo)) - (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) - (saturate-unsigned argihi argjhi (halfword hi FRintk 0)) - (saturate-unsigned argilo argjlo (halfword lo FRintk 0))) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(define-pmacro (media-dual-compare name mode op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - (.str name "$pack $FRinti,$FRintj,$FCCk") - (+ pack (cond-null) FCCk op FRinti ope FRintj) - (if (register-unaligned FCCk 2) - (c-call VOID "@cpu@_media_cr_not_aligned") - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - (extract-hilo FRinti 0 FRintj 0 - argihi argilo argjhi argjlo) - (compare-and-set-fcc argihi argjhi FCCk) - (compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1)))) - ; TODO - doesn't handle second FCC - ((fr400 (unit u-media-7)) (fr450 (unit u-media-7)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(media-dual-compare mcmpsh HI OP_7B OPE1_0E "Media dual compare signed") -(media-dual-compare mcmpuh UHI OP_7B OPE1_0F "Media dual compare unsigned") - -; Bits for the MSR.SIE field -(define-pmacro (msr-sie-nil) 0) -(define-pmacro (msr-sie-fri-hi) 8) -(define-pmacro (msr-sie-fri-lo) 4) -(define-pmacro (msr-sie-fri-1-hi) 2) -(define-pmacro (msr-sie-fri-1-lo) 1) -(define-pmacro (msr-sie-acci) 8) -(define-pmacro (msr-sie-acci-1) 4) -(define-pmacro (msr-sie-acci-2) 2) -(define-pmacro (msr-sie-acci-3) 1) - -(define-pmacro (saturate-v arg max min sie result) - (if (gt DI arg max) - (sequence () - (set result max) - (c-call VOID "@cpu@_media_overflow" sie)) - (if (lt DI arg min) - (sequence () - (set result min) - (c-call VOID "@cpu@_media_overflow" sie)) - (set result arg))) -) - -(dni mabshs - "Media dual absolute value, halfword" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mabshs$pack $FRintj,$FRintk" - (+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj) - (sequence ((HI arghi) (HI arglo)) - (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (set arghi (halfword hi FRintj 0)) - (set arglo (halfword lo FRintj 0)) - ; We extend the argument before the abs operation so we can - ; notice -32768 overflowing as 32768. - (saturate-v (abs (ext DI arghi)) 32767 -32768 (msr-sie-fri-hi) - (halfword hi FRintk 0)) - (saturate-v (abs (ext DI arglo)) 32767 -32768 (msr-sie-fri-lo) - (halfword lo FRintk 0))) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr550 (unit u-media))) -) - -; How to extend from a mode to get the intended signedness. -(define-pmacro (DI-ext-HI x) (ext DI x)) -(define-pmacro (DI-ext-UHI x) (zext DI x)) -(define-pmacro (DI-ext-DI x) x) - -(define-pmacro (media-arith-sat-semantics - operation arg1 arg2 res mode max min sie) - (sequence ((DI tmp)) - ; Make sure we saturate at max/min against a value that is - ; sign- or zero-extended appropriately from "mode". - (set tmp (operation DI - ((.sym DI-ext- mode) arg1) ((.sym DI-ext- mode) arg2))) - (saturate-v tmp max min sie res)) -) - -(define-pmacro (media-dual-arith-sat-semantics operation mode max min) - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) - (media-arith-sat-semantics operation argihi argjhi - (halfword hi FRintk 0) mode max min - (msr-sie-fri-hi)) - (media-arith-sat-semantics operation argilo argjlo - (halfword lo FRintk 0) mode max min - (msr-sie-fri-lo))) -) - -(define-pmacro (media-dual-arith-sat name operation mode max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - (.str name "$pack $FRinti,$FRintj,$FRintk") - (+ pack FRintk op FRinti ope FRintj) - (media-dual-arith-sat-semantics operation mode max min) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(media-dual-arith-sat maddhss add HI 32767 -32768 OP_7B OPE1_10 "Media dual add signed with saturation") -(media-dual-arith-sat maddhus add UHI 65535 0 OP_7B OPE1_11 "Media dual add unsigned with saturation") - -(media-dual-arith-sat msubhss sub HI 32767 -32768 OP_7B OPE1_12 "Media dual sub signed with saturation") -(media-dual-arith-sat msubhus sub UHI 65535 0 OP_7B OPE1_13 "Media dual sub unsigned with saturation") - -(define-pmacro (conditional-media-dual-arith-sat - name operation mode max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) - (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") - (+ pack FRintk op FRinti CCi cond ope FRintj) - (if (eq CCi (or cond 2)) - (media-dual-arith-sat-semantics operation mode max min)) - ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) - (fr500 (unit u-media)) (fr550 (unit u-media))) - ) -) - -(conditional-media-dual-arith-sat cmaddhss add HI 32767 -32768 OP_71 OPE4_0 "Conditional Media dual add signed with saturation") -(conditional-media-dual-arith-sat cmaddhus add UHI 65535 0 OP_71 OPE4_1 "Conditional Media dual add unsigned with saturation") - -(conditional-media-dual-arith-sat cmsubhss sub HI 32767 -32768 OP_71 OPE4_2 "Conditional Media dual sub signed with saturation") -(conditional-media-dual-arith-sat cmsubhus sub UHI 65535 0 OP_71 OPE4_3 "Conditional Media dual sub unsigned with saturation") - -(define-pmacro (media-quad-arith-sat-semantics cond operation mode max min) - (if (orif (register-unaligned FRintieven 2) - (orif (register-unaligned FRintjeven 2) - (register-unaligned FRintkeven 2))) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - ; hack to get FRintkeven referenced as a target for profiling - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-arith-sat-semantics operation argihi argjhi - (halfword hi FRintkeven 0) mode - max min (msr-sie-fri-hi)) - (media-arith-sat-semantics operation argilo argjlo - (halfword lo FRintkeven 0) mode - max min (msr-sie-fri-lo)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-arith-sat-semantics operation argihi argjhi - (halfword hi FRintkeven 1) mode - max min (msr-sie-fri-1-hi)) - (media-arith-sat-semantics operation argilo argjlo - (halfword lo FRintkeven 1) mode - max min (msr-sie-fri-1-lo))))) -) - -(define-pmacro (media-quad-arith-sat name operation mode max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") - (+ pack FRintkeven op FRintieven ope FRintjeven) - (media-quad-arith-sat-semantics 1 operation mode max min) - ((fr400 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr450 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr500 (unit u-media-quad-arith - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) - ) -) - -(media-quad-arith-sat mqaddhss add HI 32767 -32768 OP_7B OPE1_18 "Media quad add signed with saturation") -(media-quad-arith-sat mqaddhus add UHI 65535 0 OP_7B OPE1_19 "Media quad add unsigned with saturation") - -(media-quad-arith-sat mqsubhss sub HI 32767 -32768 OP_7B OPE1_1A "Media quad sub signed with saturation") -(media-quad-arith-sat mqsubhus sub UHI 65535 0 OP_7B OPE1_1B "Media quad sub unsigned with saturation") - -(define-pmacro (conditional-media-quad-arith-sat - name operation mode max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) - (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) - (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond") - (+ pack FRintkeven op FRintieven CCi cond ope FRintjeven) - (media-quad-arith-sat-semantics (eq CCi (or cond 2)) - operation mode max min) - ((fr400 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr450 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr500 (unit u-media-quad-arith - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) - ) -) - -(conditional-media-quad-arith-sat cmqaddhss add HI 32767 -32768 OP_73 OPE4_0 "Conditional Media quad add signed with saturation") -(conditional-media-quad-arith-sat cmqaddhus add UHI 65535 0 OP_73 OPE4_1 "Conditional Media quad add unsigned with saturation") - -(conditional-media-quad-arith-sat cmqsubhss sub HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation") -(conditional-media-quad-arith-sat cmqsubhus sub UHI 65535 0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation") - -;; Return A if |A| > |B| and B is positive. Return -A if |A| > |B| and -;; B is negative, saturating 0x8000 as 0x7fff. Return 0 otherwise. -(define-pmacro (media-low-clear-semantics a b) - (cond HI - ((le UHI (abs a) (abs b)) 0) - ((le HI 0 b) a) - ((eq HI a -32768) 32767) - (else (neg a)))) - -;; Return A if -|B| < A < |B|. Return -B if A <= -|B|, saturating 0x8000 -;; as 0x7fff. Return B if A >= |B|. -(define-pmacro (media-scope-limit-semantics a b) - (cond HI - ((andif (gt HI b -32768) - (ge HI a (abs b))) b) - ((gt HI a (neg (abs b))) a) - ((eq HI b -32768) 32767) - (else (neg b)))) - -(define-pmacro (media-quad-limit name operation op ope comment) - (dni name - comment - ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2)) - (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") - (+ pack FRintkeven op FRintieven ope FRintjeven) - (if (orif (register-unaligned FRintieven 2) - (orif (register-unaligned FRintjeven 2) - (register-unaligned FRintkeven 2))) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence ((HI a1) (HI a2) (HI a3) (HI a4) - (HI b1) (HI b2) (HI b3) (HI b4)) - ; hack to get FRintkeven referenced as a target - ; for profiling - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (extract-hilo FRintieven 0 FRintjeven 0 a1 a2 b1 b2) - (extract-hilo FRintieven 1 FRintjeven 1 a3 a4 b3 b4) - (set (halfword hi FRintkeven 0) (operation a1 b1)) - (set (halfword lo FRintkeven 0) (operation a2 b2)) - (set (halfword hi FRintkeven 1) (operation a3 b3)) - (set (halfword lo FRintkeven 1) (operation a4 b4)))) - ((fr450 (unit u-media-1-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven)))) - ) -) - -(media-quad-limit mqlclrhs media-low-clear-semantics OP_78 OPE1_10 - "Media quad low clear") -(media-quad-limit mqlmths media-scope-limit-semantics OP_78 OPE1_14 - "Media quad scope limitation") - -(define-pmacro (media-quad-shift name operation op ope comment) - (dni name - (comment) - ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2)) - (.str name "$pack $FRintieven,$u6,$FRintkeven") - (+ pack FRintkeven op FRintieven ope u6) - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintkeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence () - ; hack to get these referenced for profiling - (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (set (halfword hi FRintkeven 0) - (operation HI (halfword hi FRintieven 0) - (and u6 #xf))) - (set (halfword lo FRintkeven 0) - (operation HI (halfword lo FRintieven 0) - (and u6 #xf))) - (set (halfword hi FRintkeven 1) - (operation HI (halfword hi FRintieven 1) - (and u6 #xf))) - (set (halfword lo FRintkeven 1) - (operation HI (halfword lo FRintieven 1) - (and u6 #xf))))) - ((fr450 (unit u-media-3-quad - (in FRinti FRintieven) - (in FRintj FRintieven) - (out FRintk FRintkeven)))) - ) -) - -(media-quad-shift mqsllhi sll OP_78 OPE1_11 "Media quad left shift") -(media-quad-shift mqsrahi sra OP_78 OPE1_13 "Media quad right shift") - -(define-pmacro (media-acc-arith-sat name operation mode max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - (.str name "$pack $ACC40Si,$ACC40Sk") - (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Si 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (media-arith-sat-semantics operation ACC40Si - (nextreg h-acc40S ACC40Si 1) - ACC40Sk mode max min (msr-sie-acci))))) - ((fr400 (unit u-media-2-acc)) (fr450 (unit u-media-2-acc)) - (fr550 (unit u-media-4-acc))) - ) -) - -(media-acc-arith-sat maddaccs add DI #x7fffffffff (inv DI #x7fffffffff) - OP_78 OPE1_04 "Media accumulator addition") -(media-acc-arith-sat msubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) - OP_78 OPE1_05 "Media accumulator subtraction") - -(define-pmacro (media-dual-acc-arith-sat name operation mode max min op ope - comment) - (dni name - (comment) - ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $ACC40Si,$ACC40Sk") - (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Si 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (register-unaligned ACC40Sk 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (sequence () - (media-arith-sat-semantics operation ACC40Si - (nextreg h-acc40S ACC40Si 1) - ACC40Sk mode max min - (msr-sie-acci)) - (media-arith-sat-semantics operation - (nextreg h-acc40S ACC40Si 2) - (nextreg h-acc40S ACC40Si 3) - (nextreg h-acc40S ACC40Sk 1) - mode max min - (msr-sie-acci-1))))))) - ((fr400 (unit u-media-2-acc-dual)) (fr450 (unit u-media-2-acc-dual)) - (fr550 (unit u-media-4-acc-dual))) - ) -) - -(media-dual-acc-arith-sat mdaddaccs add DI #x7fffffffff (inv DI #x7fffffffff) - OP_78 OPE1_06 "Media accumulator addition") -(media-dual-acc-arith-sat mdsubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) - OP_78 OPE1_07 "Media accumulator subtraction") - -(dni masaccs - "Media add and subtract signed accumulator with saturation" - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - "masaccs$pack $ACC40Si,$ACC40Sk" - (+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Si 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (register-unaligned ACC40Sk 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (sequence () - (media-arith-sat-semantics add ACC40Si - (nextreg h-acc40S ACC40Si 1) - ACC40Sk DI - #x7fffffffff - (inv DI #x7fffffffff) - (msr-sie-acci)) - (media-arith-sat-semantics sub ACC40Si - (nextreg h-acc40S ACC40Si 1) - (nextreg h-acc40S ACC40Sk 1) - DI - #x7fffffffff - (inv DI #x7fffffffff) - (msr-sie-acci-1))))))) - ((fr400 (unit u-media-2-add-sub)) (fr450 (unit u-media-2-add-sub)) - (fr550 (unit u-media-4-add-sub))) - ) - -(dni mdasaccs - "Media add and subtract signed accumulator with saturation" - ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - "mdasaccs$pack $ACC40Si,$ACC40Sk" - (+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Si 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (register-unaligned ACC40Sk 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (sequence () - (media-arith-sat-semantics add ACC40Si - (nextreg h-acc40S ACC40Si 1) - ACC40Sk DI - #x7fffffffff - (inv DI #x7fffffffff) - (msr-sie-acci)) - (media-arith-sat-semantics sub ACC40Si - (nextreg h-acc40S ACC40Si 1) - (nextreg h-acc40S ACC40Sk 1) - DI - #x7fffffffff - (inv DI #x7fffffffff) - (msr-sie-acci-1)) - (media-arith-sat-semantics add - (nextreg h-acc40S ACC40Si 2) - (nextreg h-acc40S ACC40Si 3) - (nextreg h-acc40S ACC40Sk 2) - DI - #x7fffffffff - (inv DI #x7fffffffff) - (msr-sie-acci-2)) - (media-arith-sat-semantics sub - (nextreg h-acc40S ACC40Si 2) - (nextreg h-acc40S ACC40Si 3) - (nextreg h-acc40S ACC40Sk 3) - DI - #x7fffffffff - (inv DI #x7fffffffff) - (msr-sie-acci-3))))))) - ((fr400 (unit u-media-2-add-sub-dual)) - (fr450 (unit u-media-2-add-sub-dual)) - (fr550 (unit u-media-4-add-sub-dual))) - ) - -(define-pmacro (media-multiply-semantics conv arg1 arg2 res) - (set res (mul DI (conv DI arg1) (conv DI arg2))) -) - -(define-pmacro (media-dual-multiply-semantics cond mode conv rhs1 rhs2) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Sk 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - (extract-hilo FRinti 0 FRintj 0 - argihi argilo argjhi argjlo) - (media-multiply-semantics conv argihi rhs1 ACC40Sk) - (media-multiply-semantics conv argilo rhs2 - (nextreg h-acc40S ACC40Sk 1)))))) -) - -(define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3) PRESERVE-OVF) - (.str name "$pack $FRinti,$FRintj,$ACC40Sk") - (+ pack ACC40Sk op FRinti ope FRintj) - (media-dual-multiply-semantics 1 mode conv rhs1 rhs2) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(media-dual-multiply mmulhs HI ext argjhi argjlo OP_7B OPE1_14 "Media dual multiply signed") -(media-dual-multiply mmulhu UHI zext argjhi argjlo OP_7B OPE1_15 "Media dual multiply unsigned") - -(media-dual-multiply mmulxhs HI ext argjlo argjhi OP_7B OPE1_28 "Media dual cross multiply signed") -(media-dual-multiply mmulxhu UHI zext argjlo argjhi OP_7B OPE1_29 "Media dual cross multiply unsigned") - -(define-pmacro (conditional-media-dual-multiply - name mode conv rhs1 rhs2 op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3) - PRESERVE-OVF CONDITIONAL) - (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") - (+ pack ACC40Sk op FRinti CCi cond ope FRintj) - (media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(conditional-media-dual-multiply cmmulhs HI ext argjhi argjlo OP_72 OPE4_0 "Conditional Media dual multiply signed") -(conditional-media-dual-multiply cmmulhu UHI zext argjhi argjlo OP_72 OPE4_1 "Conditional Media dual multiply unsigned") - -(define-pmacro (media-quad-multiply-semantics cond mode conv rhs1 rhs2) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Sk 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-multiply-semantics conv argihi rhs1 ACC40Sk) - (media-multiply-semantics conv argilo rhs2 - (nextreg h-acc40S ACC40Sk 1)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-multiply-semantics conv argihi rhs1 - (nextreg h-acc40S ACC40Sk 2)) - (media-multiply-semantics conv argilo rhs2 - (nextreg h-acc40S ACC40Sk 3))))))) -) - -(define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4) PRESERVE-OVF) - (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") - (+ pack ACC40Sk op FRintieven ope FRintjeven) - (media-quad-multiply-semantics 1 mode conv rhs1 rhs2) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr500 (unit u-media-quad-mul - (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) - ) -) - -(media-quad-multiply mqmulhs HI ext argjhi argjlo OP_7B OPE1_1C "Media quad multiply signed") -(media-quad-multiply mqmulhu UHI zext argjhi argjlo OP_7B OPE1_1D "Media quad multiply unsigned") - -(media-quad-multiply mqmulxhs HI ext argjlo argjhi OP_7B OPE1_2A "Media quad cross multiply signed") -(media-quad-multiply mqmulxhu UHI zext argjlo argjhi OP_7B OPE1_2B "Media quad cross multiply unsigned") - -(define-pmacro (conditional-media-quad-multiply - name mode conv rhs1 rhs2 op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4) - PRESERVE-OVF CONDITIONAL) - (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond") - (+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven) - (media-quad-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr500 (unit u-media-quad-mul - (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) - ) -) - -(conditional-media-quad-multiply cmqmulhs HI ext argjhi argjlo OP_74 OPE4_0 "Conditional Media quad multiply signed") -(conditional-media-quad-multiply cmqmulhu UHI zext argjhi argjlo OP_74 OPE4_1 "Conditional Media quad multiply unsigned") - -(define-pmacro (media-multiply-acc-semantics - conv arg1 addop arg2 res max min sie) - (sequence ((DI tmp)) - (set tmp (addop res (mul DI (conv DI arg1) (conv DI arg2)))) - (saturate-v tmp max min sie res)) -) - -(define-pmacro (media-dual-multiply-acc-semantics - cond mode conv addop rhw res max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of res)) - (if (register-unaligned res 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - (extract-hilo FRinti 0 FRintj 0 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjhi - res - max min (msr-sie-acci)) - (media-multiply-acc-semantics conv argilo addop argjlo - (nextreg rhw res 1) - max min (msr-sie-acci-1)))))) -) - -(define-pmacro (media-dual-multiply-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - (.str name "$pack $FRinti,$FRintj,$" res) - (+ pack res op FRinti ope FRintj) - (media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(media-dual-multiply-acc mmachs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_16 - "Media dual multiply and accumulate signed") - -(media-dual-multiply-acc mmachu UHI zext add h-acc40U ACC40Uk - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_17 - "Media dual multiply and accumulate unsigned") - -(media-dual-multiply-acc mmrdhs HI ext sub h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_30 - "Media dual multiply and reduce signed") - -(media-dual-multiply-acc mmrdhu UHI zext sub h-acc40U ACC40Uk - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_31 - "Media dual multiply and reduce unsigned") - -(define-pmacro (conditional-media-dual-multiply-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) - (.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond") - (+ pack res op FRinti CCi cond ope FRintj) - (media-dual-multiply-acc-semantics (eq CCi (or cond 2)) - mode conv addop rhw res max min) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(conditional-media-dual-multiply-acc cmmachs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_72 OPE4_2 - "Conditional Media dual multiply and accumulate signed") - -(conditional-media-dual-multiply-acc cmmachu UHI zext add h-acc40U ACC40Uk - (const DI #xffffffffff) (const DI 0) - OP_72 OPE4_3 - "Conditional Media dual multiply and accumulate unsigned") - -(define-pmacro (media-quad-multiply-acc-semantics - cond mode conv addop rhw res max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of res)) - (if (register-unaligned res 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjhi - res - max min (msr-sie-acci)) - (media-multiply-acc-semantics conv argilo addop argjlo - (nextreg rhw res 1) - max min (msr-sie-acci-1)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjhi - (nextreg rhw res 2) - max min (msr-sie-acci-2)) - (media-multiply-acc-semantics conv argilo addop argjlo - (nextreg rhw res 3) - max min - (msr-sie-acci-3))))))) -) - -(define-pmacro (media-quad-multiply-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $FRintieven,$FRintjeven,$" res) - (+ pack res op FRintieven ope FRintjeven) - (media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr500 (unit u-media-quad-mul - (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) - ) -) - -(media-quad-multiply-acc mqmachs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_1E - "Media quad multiply and accumulate signed") - -(media-quad-multiply-acc mqmachu UHI zext add h-acc40U ACC40Uk - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_1F - "Media quad multiply and accumulate unsigned") - -(define-pmacro (conditional-media-quad-multiply-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4) CONDITIONAL) - (.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond") - (+ pack res op FRintieven CCi cond ope FRintjeven) - (media-quad-multiply-acc-semantics (eq CCi (or cond 2)) - mode conv addop rhw res max min) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr500 (unit u-media-quad-mul - (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) - ) -) - -(conditional-media-quad-multiply-acc cmqmachs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_74 OPE4_2 - "Conditional Media quad multiply and accumulate signed") - -(conditional-media-quad-multiply-acc cmqmachu UHI zext add h-acc40U ACC40Uk - (const DI #xffffffffff) (const DI 0) - OP_74 OPE4_3 - "Conditional media quad multiply and accumulate unsigned") - -(define-pmacro (media-quad-multiply-cross-acc-semantics - cond mode conv addop rhw res max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of res)) - (if (register-unaligned res 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjhi - (nextreg rhw res 2) - max min (msr-sie-acci-2)) - (media-multiply-acc-semantics conv argilo addop argjlo - (nextreg rhw res 3) - max min (msr-sie-acci-3)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjhi - res - max min (msr-sie-acci)) - (media-multiply-acc-semantics conv argilo addop argjlo - (nextreg rhw res 1) - max min - (msr-sie-acci-1))))))) -) - -(define-pmacro (media-quad-multiply-cross-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $FRintieven,$FRintjeven,$" res) - (+ pack res op FRintieven ope FRintjeven) - (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res - max min) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr550 (unit u-media-4-quad))) - ) -) - -(media-quad-multiply-cross-acc mqxmachs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_78 OPE1_00 - "Media quad multiply and cross accumulate signed") - -(define-pmacro (media-quad-cross-multiply-cross-acc-semantics - cond mode conv addop rhw res max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of res)) - (if (register-unaligned res 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjlo - (nextreg rhw res 2) - max min (msr-sie-acci-2)) - (media-multiply-acc-semantics conv argilo addop argjhi - (nextreg rhw res 3) - max min (msr-sie-acci-3)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjlo - res - max min (msr-sie-acci)) - (media-multiply-acc-semantics conv argilo addop argjhi - (nextreg rhw res 1) - max min - (msr-sie-acci-1))))))) -) - -(define-pmacro (media-quad-cross-multiply-cross-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $FRintieven,$FRintjeven,$" res) - (+ pack res op FRintieven ope FRintjeven) - (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res - max min) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr550 (unit u-media-4-quad))) - ) -) - -(media-quad-cross-multiply-cross-acc mqxmacxhs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_78 OPE1_01 - "Media quad cross multiply and cross accumulate signed") - -(define-pmacro (media-quad-cross-multiply-acc-semantics - cond mode conv addop rhw res max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of res)) - (if (register-unaligned res 4) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjlo - res - max min (msr-sie-acci)) - (media-multiply-acc-semantics conv argilo addop argjhi - (nextreg rhw res 1) - max min (msr-sie-acci-1)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-multiply-acc-semantics conv argihi addop argjlo - (nextreg rhw res 2) - max min (msr-sie-acci-2)) - (media-multiply-acc-semantics conv argilo addop argjhi - (nextreg rhw res 3) - max min - (msr-sie-acci-3))))))) -) - -(define-pmacro (media-quad-cross-multiply-acc - name mode conv addop rhw res max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $FRintieven,$FRintjeven,$" res) - (+ pack res op FRintieven ope FRintjeven) - (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res - max min) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr550 (unit u-media-4-quad))) - ) -) - -(media-quad-cross-multiply-acc mqmacxhs HI ext add h-acc40S ACC40Sk - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_78 OPE1_02 - "Media quad cross multiply and accumulate signed") - -(define-pmacro (media-complex-semantics - conv lhs1 rhs1 lhs2 rhs2 res max min sie) - (sequence ((DI tmp1) (DI tmp2)) - (media-multiply-semantics conv lhs1 rhs1 tmp1) - (media-multiply-semantics conv lhs2 rhs2 tmp2) - (set tmp1 (sub tmp1 tmp2)) - (saturate-v tmp1 max min sie res)) -) - -(define-pmacro (media-complex-semantics-i - conv lhs1 rhs1 lhs2 rhs2 res max min sie) - (sequence ((DI tmp1) (DI tmp2)) - (media-multiply-semantics conv lhs1 rhs1 tmp1) - (media-multiply-semantics conv lhs2 rhs2 tmp2) - (set tmp1 (add tmp1 tmp2)) - (saturate-v tmp1 max min sie res)) -) - -(define-pmacro (media-dual-complex-semantics mode conv rhs1 rhs2 max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) - (media-complex-semantics conv argihi rhs1 argilo rhs2 ACC40Sk - max min (msr-sie-acci)))) -) - -(define-pmacro (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) - (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) - (media-complex-semantics-i conv argihi rhs1 argilo rhs2 ACC40Sk - max min (msr-sie-acci)))) -) - -(define-pmacro (media-dual-complex - name mode conv rhs1 rhs2 max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - (.str name "$pack $FRinti,$FRintj,$ACC40Sk") - (+ pack ACC40Sk op FRinti ope FRintj) - (media-dual-complex-semantics mode conv rhs1 rhs2 max min) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(define-pmacro (media-dual-complex-i - name mode conv rhs1 rhs2 max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - (.str name "$pack $FRinti,$FRintj,$ACC40Sk") - (+ pack ACC40Sk op FRinti ope FRintj) - (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(media-dual-complex mcpxrs HI ext argjhi argjlo - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_20 - "Media dual complex real signed with saturation") - -(media-dual-complex mcpxru UHI zext argjhi argjlo - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_21 - "Media dual complex real unsigned with saturation") - -(media-dual-complex-i mcpxis HI ext argjlo argjhi - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_22 - "Media dual complex imaginary signed with saturation") - -(media-dual-complex-i mcpxiu UHI zext argjlo argjhi - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_23 - "Media dual complex imaginary unsigned with saturation") - -(define-pmacro (conditional-media-dual-complex - name mode conv rhs1 rhs2 max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) - (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") - (+ pack ACC40Sk op FRinti CCi cond ope FRintj) - (if (eq CCi (or cond 2)) - (media-dual-complex-semantics mode conv rhs1 rhs2 max min)) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(define-pmacro (conditional-media-dual-complex-i - name mode conv rhs1 rhs2 max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) - (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") - (+ pack ACC40Sk op FRinti CCi cond ope FRintj) - (if (eq CCi (or cond 2)) - (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)) - ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) - (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) - ) -) - -(conditional-media-dual-complex cmcpxrs HI ext argjhi argjlo - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_75 OPE4_0 - "Conditional Media dual complex real signed with saturation") - -(conditional-media-dual-complex cmcpxru UHI zext argjhi argjlo - (const DI #xffffffffff) (const DI 0) - OP_75 OPE4_1 - "Conditional Media dual complex real unsigned with saturation") - -(conditional-media-dual-complex-i cmcpxis HI ext argjlo argjhi - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_75 OPE4_2 - "Conditional Media dual complex imaginary signed with saturation") - -(conditional-media-dual-complex-i cmcpxiu UHI zext argjlo argjhi - (const DI #xffffffffff) (const DI 0) - OP_75 OPE4_3 - "Conditional Media dual complex imaginary unsigned with saturation") - -(define-pmacro (media-quad-complex - name mode conv rhs1 rhs2 max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") - (+ pack ACC40Sk op FRintieven ope FRintjeven) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Sk 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-complex-semantics conv argihi rhs1 argilo rhs2 - ACC40Sk - max min (msr-sie-acci)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-complex-semantics conv argihi rhs1 argilo rhs2 - (nextreg h-acc40S ACC40Sk 1) - max min (msr-sie-acci-1)))))) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr500 (unit u-media-quad-complex - (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) - ) -) - -(define-pmacro (media-quad-complex-i - name mode conv rhs1 rhs2 max min op ope comment) - (dni name - (comment) - ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") - (+ pack ACC40Sk op FRintieven ope FRintjeven) - (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) - (if (register-unaligned ACC40Sk 2) - (c-call VOID "@cpu@_media_acc_not_aligned") - (if (orif (register-unaligned FRintieven 2) - (register-unaligned FRintjeven 2)) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence ((mode argihi) (mode argilo) - (mode argjhi) (mode argjlo)) - (extract-hilo FRintieven 0 FRintjeven 0 - argihi argilo argjhi argjlo) - (media-complex-semantics-i conv argihi rhs1 argilo rhs2 - ACC40Sk - max min (msr-sie-acci)) - (extract-hilo FRintieven 1 FRintjeven 1 - argihi argilo argjhi argjlo) - (media-complex-semantics-i conv argihi rhs1 argilo rhs2 - (nextreg h-acc40S ACC40Sk 1) - max min (msr-sie-acci-1)))))) - ((fr400 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr450 (unit u-media-2-quad - (in FRinti FRintieven) - (in FRintj FRintjeven))) - (fr500 (unit u-media-quad-complex - (in FRinti FRintieven) - (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) - ) -) - -(media-quad-complex mqcpxrs HI ext argjhi argjlo - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_24 - "Media quad complex real signed with saturation") - -(media-quad-complex mqcpxru UHI zext argjhi argjlo - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_25 - "Media quad complex real unsigned with saturation") - -(media-quad-complex-i mqcpxis HI ext argjlo argjhi - (const DI #x7fffffffff) (const DI #xffffff8000000000) - OP_7B OPE1_26 - "Media quad complex imaginary signed with saturation") - -(media-quad-complex-i mqcpxiu UHI zext argjlo argjhi - (const DI #xffffffffff) (const DI 0) - OP_7B OPE1_27 - "Media quad complex imaginary unsigned with saturation") - -(define-pmacro (media-pack src1 src2 targ offset) - (sequence () - (set (halfword hi targ offset) (halfword lo src1 offset)) - (set (halfword lo targ offset) (halfword lo src2 offset))) -) - -(define-pmacro (media-expand-halfword-to-word-semantics cond) - (if cond - (sequence ((UHI tmp)) - (if (and u6 1) - (set tmp (halfword lo FRinti 0)) - (set tmp (halfword hi FRinti 0))) - (set (halfword hi FRintk 0) tmp) - (set (halfword lo FRintk 0) tmp))) -) - -(dni mexpdhw - "Media expand halfword to word" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mexpdhw$pack $FRinti,$u6,$FRintk" - (+ pack FRintk OP_7B FRinti OPE1_32 u6) - (media-expand-halfword-to-word-semantics 1) - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(dni cmexpdhw - "Conditional media expand halfword to word" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) - "cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond" - (+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6) - (media-expand-halfword-to-word-semantics (eq CCi (or cond 2))) - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(define-pmacro (media-expand-halfword-to-double-semantics cond) - (if (register-unaligned FRintkeven 2) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence ((UHI tmp)) - ; a hack to get FRintkeven referenced for profiling - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (if (and u6 1) - (set tmp (halfword lo FRinti 0)) - (set tmp (halfword hi FRinti 0))) - (set (halfword hi FRintkeven 0) tmp) - (set (halfword lo FRintkeven 0) tmp) - (set (halfword hi FRintkeven 1) tmp) - (set (halfword lo FRintkeven 1) tmp)))) -) - -(dni mexpdhd - "Media expand halfword to double" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mexpdhd$pack $FRinti,$u6,$FRintkeven" - (+ pack FRintkeven OP_7B FRinti OPE1_33 u6) - (media-expand-halfword-to-double-semantics 1) - ((fr400 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr450 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr500 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr550 (unit u-media-dual-expand))) -) - -(dni cmexpdhd - "Conditional media expand halfword to double" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) - "cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond" - (+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6) - (media-expand-halfword-to-double-semantics (eq CCi (or cond 2))) - ((fr400 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr450 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr500 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr550 (unit u-media-dual-expand))) -) - -(dni mpackh - "Media halfword pack" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mpackh$pack $FRinti,$FRintj,$FRintk" - (+ pack FRintk OP_7B FRinti OPE1_34 FRintj) - (media-pack FRinti FRintj FRintk 0) - ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) - (fr500 (unit u-media)) (fr550 (unit u-media))) -) - -(dni mdpackh - "Media dual pack" - ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven" - (+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven) - (if (orif (register-unaligned FRintieven 2) - (orif (register-unaligned FRintjeven 2) - (register-unaligned FRintkeven 2))) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence () - ; hack to get these referenced for profiling - (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) - (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (media-pack FRintieven FRintjeven FRintkeven 0) - (media-pack FRintieven FRintjeven FRintkeven 1))) - ((fr400 (unit u-media-3-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr450 (unit u-media-3-quad - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr500 (unit u-media-quad-arith - (in FRinti FRintieven) - (in FRintj FRintjeven) - (out FRintk FRintkeven))) - (fr550 (unit u-media-quad))) -) - -(define-pmacro (media-unpack src soff targ toff) - (sequence () - (set (halfword hi targ toff) (halfword hi src soff)) - (set (halfword lo targ toff) (halfword hi src soff)) - (set (halfword hi targ (add toff 1)) (halfword lo src soff)) - (set (halfword lo targ (add toff 1)) (halfword lo src soff))) -) - -(dni munpackh - "Media halfword unpack" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "munpackh$pack $FRinti,$FRintkeven" - (+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null)) - (if (register-unaligned FRintkeven 2) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence () - ; hack to get these referenced for profiling - (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (media-unpack FRinti 0 FRintkeven 0))) - ((fr400 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr450 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr500 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr550 (unit u-media-dual-expand))) -) - -(dni mdunpackh - "Media dual unpack" - ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) - "mdunpackh$pack $FRintieven,$FRintk" - (+ pack FRintk OP_7B FRintieven OPE1_37 (FRj-null)) - (if (orif (register-unaligned FRintieven 2) (register-unaligned FRintk 4)) - (c-call VOID "@cpu@_media_register_not_aligned") - (sequence () - ; hack to get these referenced for profiling - (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (media-unpack FRintieven 0 FRintk 0) - (media-unpack FRintieven 1 FRintk 2))) - ((fr500 (unit u-media-dual-unpack - (in FRinti FRintieven)))) -) - -(define-pmacro (ubyte num arg offset) - (reg (.sym h-fr_ num) (add (index-of arg) offset))) - -(define-pmacro (mbtoh-semantics cond) - (if (register-unaligned FRintkeven 2) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence () - (set (halfword hi FRintkeven 0) (ubyte 3 FRintj 0)) - (set (halfword lo FRintkeven 0) (ubyte 2 FRintj 0)) - (set (halfword hi FRintkeven 1) (ubyte 1 FRintj 0)) - (set (halfword lo FRintkeven 1) (ubyte 0 FRintj 0))))) -) - -(dni mbtoh - "Media convert byte to halfword" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mbtoh$pack $FRintj,$FRintkeven" - (+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj) - (sequence () - ; hack to get these referenced for profiling - (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (mbtoh-semantics 1)) - ((fr400 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr450 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr500 (unit u-media-dual-btoh - (out FRintk FRintkeven))) - (fr550 (unit u-media-dual-expand))) -) - -(dni cmbtoh - "Conditional media convert byte to halfword" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) - "cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond" - (+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj) - (sequence () - ; hack to get these referenced for profiling - (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) - (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) - (mbtoh-semantics (eq CCi (or cond 2)))) - ((fr400 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr450 (unit u-media-dual-expand - (out FRintk FRintkeven))) - (fr500 (unit u-media-dual-btoh - (out FRintk FRintkeven))) - (fr550 (unit u-media-dual-expand - (in FRinti FRintj)))) -) - -(define-pmacro (mhtob-semantics cond) - (if (register-unaligned FRintjeven 2) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence () - (set (ubyte 3 FRintk 0) (halfword hi FRintjeven 0)) - (set (ubyte 2 FRintk 0) (halfword lo FRintjeven 0)) - (set (ubyte 1 FRintk 0) (halfword hi FRintjeven 1)) - (set (ubyte 0 FRintk 0) (halfword lo FRintjeven 1))))) -) - -(dni mhtob - "Media convert halfword to byte" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2)) - "mhtob$pack $FRintjeven,$FRintk" - (+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven) - (sequence () - ; hack to get these referenced for profiling - (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (mhtob-semantics 1)) - ((fr400 (unit u-media-dual-htob - (in FRintj FRintjeven))) - (fr450 (unit u-media-dual-htob - (in FRintj FRintjeven))) - (fr500 (unit u-media-dual-htob - (in FRintj FRintjeven))) - (fr550 (unit u-media-3-dual - (in FRinti FRintjeven)))) -) - -(dni cmhtob - "Conditional media convert halfword to byte" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) - "cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond" - (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven) - (sequence () - ; hack to get these referenced for profiling - (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (mhtob-semantics (eq CCi (or cond 2)))) - ((fr400 (unit u-media-dual-htob - (in FRintj FRintjeven))) - (fr450 (unit u-media-dual-htob - (in FRintj FRintjeven))) - (fr500 (unit u-media-dual-htob - (in FRintj FRintjeven))) - (fr550 (unit u-media-3-dual - (in FRinti FRintjeven)))) -) - -(define-pmacro (mbtohe-semantics cond) - (if (register-unaligned FRintk 4) - (c-call VOID "@cpu@_media_register_not_aligned") - (if cond - (sequence () - (set (halfword hi FRintk 0) (ubyte 3 FRintj 0)) - (set (halfword lo FRintk 0) (ubyte 3 FRintj 0)) - (set (halfword hi FRintk 1) (ubyte 2 FRintj 0)) - (set (halfword lo FRintk 1) (ubyte 2 FRintj 0)) - (set (halfword hi FRintk 2) (ubyte 1 FRintj 0)) - (set (halfword lo FRintk 2) (ubyte 1 FRintj 0)) - (set (halfword hi FRintk 3) (ubyte 0 FRintj 0)) - (set (halfword lo FRintk 3) (ubyte 0 FRintj 0))))) -) - -(dni mbtohe - "Media convert byte to halfword extended" - ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) - "mbtohe$pack $FRintj,$FRintk" - (+ pack FRintk OP_7B (FRi-null) OPE1_3A FRintj) - (sequence () - ; hack to get these referenced for profiling - (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (mbtohe-semantics 1)) - ((fr500 (unit u-media-dual-btohe))) -) - -(dni cmbtohe - "Conditional media convert byte to halfword extended" - ((UNIT FM01) (FR500-MAJOR M-7) CONDITIONAL (MACH simple,tomcat,frv)) - "cmbtohe$pack $FRintj,$FRintk,$CCi,$cond" - (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_2 FRintj) - (sequence () - ; hack to get these referenced for profiling - (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) - (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) - (mbtohe-semantics (eq CCi (or cond 2)))) - ((fr500 (unit u-media-dual-btohe))) -) - -; Media NOP -; A special case of mclracc -(dni mnop "Media nop" - ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) - (FR400-MAJOR M-1) (FR450-MAJOR M-1)) - "mnop$pack" - (+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) - (nop) - () -) - -; mclracc with #A==0 -(dni mclracc-0 - "Media clear accumulator(s)" - ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - "mclracc$pack $ACC40Sk,$A0" - (+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null)) - (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0) - ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) -) - -; mclracc with #A==1 -(dni mclracc-1 - "Media clear accumulator(s)" - ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) - (FR400-MAJOR M-2) (FR450-MAJOR M-4)) - "mclracc$pack $ACC40Sk,$A1" - (+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) - (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1) - ((fr400 (unit u-media-4)) (fr450 (unit u-media-4-mclracca)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) -) - -(dni mrdacc - "Media read accumulator" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-5)) - "mrdacc$pack $ACC40Si,$FRintk" - (+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null)) - (set FRintk ACC40Si) - ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) -) - -(dni mrdaccg - "Media read accumulator guard" - ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-5)) - "mrdaccg$pack $ACCGi,$FRintk" - (+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null)) - (set FRintk ACCGi) - ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi)))) -) - -(dni mwtacc - "Media write accumulator" - ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - "mwtacc$pack $FRinti,$ACC40Sk" - (+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null)) - (set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000)) - FRinti)) - ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc))) -) - -(dni mwtaccg - "Media write accumulator guard" - ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) - (FR400-MAJOR M-1) (FR450-MAJOR M-3)) - "mwtaccg$pack $FRinti,$ACCGk" - (+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null)) - (sequence () - ; hack to get these referenced for profiling - (c-raw-call VOID "frv_ref_SI" ACCGk) - (set ACCGk FRinti)) - ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg)) - (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk)))) -) - -(define-pmacro (media-cop num op) - (dni (.sym mcop num) - "Media custom instruction" - ((UNIT FM01) (FR500-MAJOR M-1) (MACH frv)) - (.str "mcop" num "$pack $FRi,$FRj,$FRk") - (+ pack FRk op FRi OPE1_00 FRj) - (c-call VOID "@cpu@_media_cop" num) - () - ) -) - -(media-cop 1 OP_7C) -(media-cop 2 OP_7D) - -; nop -; A nop is defined to be a "ori gr0,0,gr0" -; This needn't be a macro-insn, but making it one greatly simplifies decode.c -; On the other hand spending a little time in the decoder is often worth it. -; -(dnmi nop "nop" - ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "nop$pack" - (emit ori pack (GRi 0) (s12 0) (GRk 0)) -) - -; Floating point NOP -(dni fnop - "Floating point nop" - ((UNIT FMALL) (FR500-MAJOR F-8) (FR550-MAJOR F-1) (MACH simple,tomcat,fr500,fr550,frv)) - "fnop$pack" - (+ pack (rd-null) OP_79 (FRi-null) OPE1_0D (FRj-null)) - (nop) - () -) - -; A return instruction -(dnmi ret "return" - (NO-DIS (UNIT B01) (FR500-MAJOR B-3) - (FR400-MAJOR B-3) (FR450-MAJOR B-3)) - "ret$pack" - (emit bralr pack (hint_taken 2)) -) - -(dnmi cmp "compare" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "cmp$pack $GRi,$GRj,$ICCi_1" - (emit subcc pack GRi GRj (GRk 0) ICCi_1) -) - -(dnmi cmpi "compare immediate" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "cmpi$pack $GRi,$s10,$ICCi_1" - (emit subicc pack GRi s10 (GRk 0) ICCi_1) -) - -(dnmi ccmp "conditional compare" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "ccmp$pack $GRi,$GRj,$CCi,$cond" - (emit csubcc pack GRi GRj (GRk 0) CCi cond) -) - -(dnmi mov "move" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1)) - "mov$pack $GRi,$GRk" - (emit ori pack GRi (s12 0) GRk) -) - -(dnmi cmov "conditional move" - (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) - (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) - "cmov$pack $GRi,$GRk,$CCi,$cond" - (emit cor pack GRi (GRj 0) GRk CCi cond) -) diff --git a/binutils-2.24/cpu/frv.opc b/binutils-2.24/cpu/frv.opc deleted file mode 100644 index 869155d6..00000000 --- a/binutils-2.24/cpu/frv.opc +++ /dev/null @@ -1,1921 +0,0 @@ -/* Fujitsu FRV opcode support, for GNU Binutils. -*- C -*- - - Copyright 2000, 2001, 2003, 2004, 2005, 2007, 2009 - Free Software Foundation, Inc. - - Contributed by Red Hat Inc; developed under contract from Fujitsu. - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* This file is an addendum to frv.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 128 -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Vliw support. */ -#define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ -#define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL - -typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; - -typedef struct -{ - int next_slot; - int constraint_violation; - unsigned long mach; - unsigned long elf_flags; - CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping; - VLIW_COMBO * current_vliw; - CGEN_ATTR_VALUE_ENUM_TYPE major[FRV_VLIW_SIZE]; - const CGEN_INSN * insn[FRV_VLIW_SIZE]; -} FRV_VLIW; - -int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); -int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); -int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); -int frv_is_branch_insn (const CGEN_INSN *); -int frv_is_float_insn (const CGEN_INSN *); -int frv_is_media_insn (const CGEN_INSN *); -void frv_vliw_reset (FRV_VLIW *, unsigned long, unsigned long); -int frv_vliw_add_insn (FRV_VLIW *, const CGEN_INSN *); -int spr_valid (long); -/* -- */ - -/* -- opc.c */ -#include "elf/frv.h" -#include <stdio.h> - -/* DEBUG appears below as argument of OP macro. */ -#undef DEBUG - -/* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV - development tree. */ - -bfd_boolean -frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) -{ - switch (mach) - { - case bfd_mach_fr400: - if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6) - return TRUE; - break; - case bfd_mach_fr450: - if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6) - return TRUE; - break; - default: - if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6) - return TRUE; - break; - } - - return FALSE; -} - -/* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ - -bfd_boolean -frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) -{ - switch (mach) - { - case bfd_mach_fr400: - case bfd_mach_fr450: - return FALSE; - default: - if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8) - return TRUE; - break; - } - - return FALSE; -} - -/* Returns TRUE if {MAJOR,MACH} supports media insns. */ - -bfd_boolean -frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) -{ - switch (mach) - { - case bfd_mach_fr400: - if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2) - return TRUE; - break; - case bfd_mach_fr450: - if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6) - return TRUE; - break; - default: - if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8) - return TRUE; - break; - } - - return FALSE; -} - -bfd_boolean -frv_is_branch_insn (const CGEN_INSN *insn) -{ - if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), - bfd_mach_fr400)) - return TRUE; - if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), - bfd_mach_fr450)) - return TRUE; - if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), - bfd_mach_fr500)) - return TRUE; - - return FALSE; -} - -bfd_boolean -frv_is_float_insn (const CGEN_INSN *insn) -{ - if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), - bfd_mach_fr400)) - return TRUE; - if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), - bfd_mach_fr450)) - return TRUE; - if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), - bfd_mach_fr500)) - return TRUE; - - return FALSE; -} - -bfd_boolean -frv_is_media_insn (const CGEN_INSN *insn) -{ - if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR), - bfd_mach_fr400)) - return TRUE; - if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR), - bfd_mach_fr450)) - return TRUE; - if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR), - bfd_mach_fr500)) - return TRUE; - - return FALSE; -} - -/* This table represents the allowable packing for vliw insns for the fr400. - The fr400 has only 2 vliw slots. Represent this by not allowing any insns - in the extra slots. - Subsets of any given row are also allowed. */ -static VLIW_COMBO fr400_allowed_vliw[] = -{ - /* slot0 slot1 slot2 slot3 */ - { UNIT_I0, UNIT_I1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_FM0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_B0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_FM0, UNIT_FM1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_FM0, UNIT_B0, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_B0, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO } -}; - -/* This table represents the allowable packing for vliw insns for the fr500. - The fr500 has only 4 vliw slots. Represent this by not allowing any insns - in the extra slots. - Subsets of any given row are also allowed. */ -static VLIW_COMBO fr500_allowed_vliw[] = -{ - /* slot0 slot1 slot2 slot3 */ - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1 PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0 PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0 PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, - { UNIT_I0, UNIT_B0, UNIT_B1, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1 PAD_VLIW_COMBO }, - { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO }, - { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL PAD_VLIW_COMBO } -}; - -/* This table represents the allowable packing for vliw insns for the fr550. - Subsets of any given row are also allowed. */ -static VLIW_COMBO fr550_allowed_vliw[] = -{ - /* slot0 slot1 slot2 slot3 slot4 slot5 slot6 slot7 */ - { UNIT_I0, UNIT_I1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_I1, UNIT_I2, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_I1, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_B0, UNIT_B1 , UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_I3, UNIT_FM3 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_I3, UNIT_B0 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_FM3, UNIT_B0 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_FM2, UNIT_B0, UNIT_B1 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_I2, UNIT_B0, UNIT_B1, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1 }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_I2, UNIT_I3, UNIT_B0, UNIT_B1, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_I2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_I1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_I0, UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_C, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_FM3, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL }, - { UNIT_FM0, UNIT_FM1, UNIT_FM2, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_FM0, UNIT_FM1, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_FM0, UNIT_B0, UNIT_B1, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL }, - { UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL, UNIT_NIL } -}; - -/* Some insns are assigned specialized implementation units which map to - different actual implementation units on different machines. These - tables perform that mapping. */ -static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] = -{ -/* unit in insn actual unit */ -/* NIL */ UNIT_NIL, -/* I0 */ UNIT_I0, -/* I1 */ UNIT_I1, -/* I01 */ UNIT_I01, -/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ -/* I3 */ UNIT_NIL, -/* IALL */ UNIT_I01, /* only I0 and I1 units */ -/* FM0 */ UNIT_FM0, -/* FM1 */ UNIT_FM1, -/* FM01 */ UNIT_FM01, -/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ -/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ -/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ -/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ -/* B0 */ UNIT_B0, /* branches only in B0 unit. */ -/* B1 */ UNIT_B0, -/* B01 */ UNIT_B0, -/* C */ UNIT_C, -/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ -/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ -/* LOAD */ UNIT_I0, /* load only in I0 unit. */ -/* STORE */ UNIT_I0, /* store only in I0 unit. */ -/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ -/* DCPL */ UNIT_C, /* dcpl only in C unit. */ -/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ -/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ -/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ -}; - -/* Some insns are assigned specialized implementation units which map to - different actual implementation units on different machines. These - tables perform that mapping. */ -static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] = -{ -/* unit in insn actual unit */ -/* NIL */ UNIT_NIL, -/* I0 */ UNIT_I0, -/* I1 */ UNIT_I1, -/* I01 */ UNIT_I01, -/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ -/* I3 */ UNIT_NIL, -/* IALL */ UNIT_I01, /* only I0 and I1 units */ -/* FM0 */ UNIT_FM0, -/* FM1 */ UNIT_FM1, -/* FM01 */ UNIT_FM01, -/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ -/* FM3 */ UNIT_NIL, /* no F3 or M3 units */ -/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ -/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ -/* B0 */ UNIT_B0, /* branches only in B0 unit. */ -/* B1 */ UNIT_B0, -/* B01 */ UNIT_B0, -/* C */ UNIT_C, -/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ -/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */ -/* LOAD */ UNIT_I0, /* load only in I0 unit. */ -/* STORE */ UNIT_I0, /* store only in I0 unit. */ -/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ -/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ -/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ -/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */ -/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ -}; - -static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] = -{ -/* unit in insn actual unit */ -/* NIL */ UNIT_NIL, -/* I0 */ UNIT_I0, -/* I1 */ UNIT_I1, -/* I01 */ UNIT_I01, -/* I2 */ UNIT_NIL, /* no I2 or I3 unit */ -/* I3 */ UNIT_NIL, -/* IALL */ UNIT_I01, /* only I0 and I1 units */ -/* FM0 */ UNIT_FM0, -/* FM1 */ UNIT_FM1, -/* FM01 */ UNIT_FM01, -/* FM2 */ UNIT_NIL, /* no F2 or M2 units */ -/* FM3 */ UNIT_NIL, /* no F3 or M2 units */ -/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ -/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ -/* B0 */ UNIT_B0, -/* B1 */ UNIT_B1, -/* B01 */ UNIT_B01, -/* C */ UNIT_C, -/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ -/* IACC */ UNIT_NIL, /* iacc multiply not implemented */ -/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ -/* STORE */ UNIT_I0, /* store only in I0 unit. */ -/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ -/* DCPL */ UNIT_C, /* dcpl only in C unit. */ -/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ -/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */ -/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ -}; - -static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] = -{ -/* unit in insn actual unit */ -/* NIL */ UNIT_NIL, -/* I0 */ UNIT_I0, -/* I1 */ UNIT_I1, -/* I01 */ UNIT_I01, -/* I2 */ UNIT_I2, -/* I3 */ UNIT_I3, -/* IALL */ UNIT_IALL, -/* FM0 */ UNIT_FM0, -/* FM1 */ UNIT_FM1, -/* FM01 */ UNIT_FM01, -/* FM2 */ UNIT_FM2, -/* FM3 */ UNIT_FM3, -/* FMALL */ UNIT_FMALL, -/* FMLOW */ UNIT_FM01, /* Only F0,F1,M0,M1 units */ -/* B0 */ UNIT_B0, -/* B1 */ UNIT_B1, -/* B01 */ UNIT_B01, -/* C */ UNIT_C, -/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ -/* IACC */ UNIT_NIL, /* iacc multiply not implemented. */ -/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ -/* STORE */ UNIT_I01, /* store in I0 or I1 unit. */ -/* SCAN */ UNIT_IALL, /* scan in any integer unit. */ -/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */ -/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */ -/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */ -/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ -}; - -void -frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) -{ - vliw->next_slot = 0; - vliw->constraint_violation = 0; - vliw->mach = mach; - vliw->elf_flags = elf_flags; - - switch (mach) - { - case bfd_mach_fr400: - vliw->current_vliw = fr400_allowed_vliw; - vliw->unit_mapping = fr400_unit_mapping; - break; - case bfd_mach_fr450: - vliw->current_vliw = fr400_allowed_vliw; - vliw->unit_mapping = fr450_unit_mapping; - break; - case bfd_mach_fr550: - vliw->current_vliw = fr550_allowed_vliw; - vliw->unit_mapping = fr550_unit_mapping; - break; - default: - vliw->current_vliw = fr500_allowed_vliw; - vliw->unit_mapping = fr500_unit_mapping; - break; - } -} - -/* Return TRUE if unit1 is a match for unit2. - Unit1 comes from the insn's UNIT attribute. unit2 comes from one of the - *_allowed_vliw tables above. */ -static bfd_boolean -match_unit (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2) -{ - /* Map any specialized implementation units to actual ones. */ - unit1 = vliw->unit_mapping[unit1]; - - if (unit1 == unit2) - return TRUE; - if (unit1 < unit2) - return FALSE; - - switch (unit1) - { - case UNIT_I01: - case UNIT_FM01: - case UNIT_B01: - /* The 01 versions of these units are within 2 enums of the 0 or 1 - versions. */ - if (unit1 - unit2 <= 2) - return TRUE; - break; - case UNIT_IALL: - case UNIT_FMALL: - /* The ALL versions of these units are within 5 enums of the 0, 1, 2 or 3 - versions. */ - if (unit1 - unit2 <= 5) - return TRUE; - break; - default: - break; - } - - return FALSE; -} - -/* Return TRUE if the vliws match, FALSE otherwise. */ - -static bfd_boolean -match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) -{ - int i; - - for (i = 0; i < vliw_size; ++i) - if ((*vliw1)[i] != (*vliw2)[i]) - return FALSE; - - return TRUE; -} - -/* Find the next vliw vliw in the table that can accomodate the new insn. - If one is found then return it. Otherwise return NULL. */ - -static VLIW_COMBO * -add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) -{ - int next = vliw->next_slot; - VLIW_COMBO *current = vliw->current_vliw; - VLIW_COMBO *potential; - - if (next <= 0) - { - fprintf (stderr, "frv-opc.c line %d: bad vliw->next_slot value.\n", - __LINE__); - abort (); /* Should never happen. */ - } - - /* The table is sorted by units allowed within slots, so vliws with - identical starting sequences are together. */ - potential = current; - do - { - if (match_unit (vliw, unit, (*potential)[next])) - return potential; - ++potential; - } - while (match_vliw (potential, current, next)); - - return NULL; -} - -/* Look for the given major insn type in the given vliw. - Returns TRUE if found, FALSE otherwise. */ - -static bfd_boolean -find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) -{ - int i; - - for (i = 0; i < vliw->next_slot; ++i) - if (vliw->major[i] == major) - return TRUE; - - return FALSE; -} - -/* Check for constraints between the insns in the vliw due to major insn - types. */ - -static bfd_boolean -fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) -{ - /* In the cpu file, all media insns are represented as being allowed in - both media units. This makes it easier since this is the case for fr500. - Catch the invalid combinations here. Insns of major class FR400_MAJOR_M_2 - cannot coexist with any other media insn in a vliw. */ - switch (major) - { - case FR400_MAJOR_M_2: - return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1) - && ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); - case FR400_MAJOR_M_1: - return ! find_major_in_vliw (vliw, FR400_MAJOR_M_2); - default: - break; - } - return TRUE; -} - -static bfd_boolean -fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) -{ - CGEN_ATTR_VALUE_ENUM_TYPE other_major; - - /* Our caller guarantees there's at least one other instruction. */ - other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); - - /* (M4, M5) and (M4, M6) are allowed. */ - if (other_major == FR450_MAJOR_M_4) - if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6) - return TRUE; - - /* Otherwise, instructions in even-numbered media categories cannot be - executed in parallel with other media instructions. */ - switch (major) - { - case FR450_MAJOR_M_2: - case FR450_MAJOR_M_4: - case FR450_MAJOR_M_6: - return !(other_major >= FR450_MAJOR_M_1 - && other_major <= FR450_MAJOR_M_6); - - case FR450_MAJOR_M_1: - case FR450_MAJOR_M_3: - case FR450_MAJOR_M_5: - return !(other_major == FR450_MAJOR_M_2 - || other_major == FR450_MAJOR_M_4 - || other_major == FR450_MAJOR_M_6); - - default: - return TRUE; - } -} - -static bfd_boolean -find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) -{ - int i; - - for (i = 0; i < vliw->next_slot; ++i) - if (CGEN_INSN_ATTR_VALUE (vliw->insn[i], CGEN_INSN_UNIT) == unit) - return TRUE; - - return FALSE; /* Not found. */ -} - -static bfd_boolean -find_major_in_slot (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_ENUM_TYPE major, - CGEN_ATTR_VALUE_ENUM_TYPE slot) -{ - int i; - - for (i = 0; i < vliw->next_slot; ++i) - if (vliw->major[i] == major && (*vliw->current_vliw)[i] == slot) - return TRUE; - - return FALSE; -} - -static bfd_boolean -fr550_find_media_in_vliw (FRV_VLIW *vliw) -{ - int i; - - for (i = 0; i < vliw->next_slot; ++i) - { - if (vliw->major[i] < FR550_MAJOR_M_1 || vliw->major[i] > FR550_MAJOR_M_5) - continue; - - /* Found a media insn, however, MNOP and MCLRACC don't count. */ - if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MNOP - || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_0 - || CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_MCLRACC_1) - continue; - - return TRUE; /* Found one. */ - } - - return FALSE; -} - -static bfd_boolean -fr550_find_float_in_vliw (FRV_VLIW *vliw) -{ - int i; - - for (i = 0; i < vliw->next_slot; ++i) - { - if (vliw->major[i] < FR550_MAJOR_F_1 || vliw->major[i] > FR550_MAJOR_F_4) - continue; - - /* Found a floating point insn, however, FNOP doesn't count. */ - if (CGEN_INSN_NUM (vliw->insn[i]) == FRV_INSN_FNOP) - continue; - - return TRUE; /* Found one. */ - } - - return FALSE; -} - -static bfd_boolean -fr550_check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_ENUM_TYPE major, - const CGEN_INSN *insn) -{ - CGEN_ATTR_VALUE_ENUM_TYPE unit; - CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; - switch (slot) - { - case UNIT_I2: - /* If it's a store, then there must be another store in I1 */ - unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); - if (unit == UNIT_STORE) - return find_unit_in_vliw (vliw, UNIT_STORE); - break; - case UNIT_FM2: - case UNIT_FM3: - /* Floating point insns other than FNOP in slot f2 or f3 cannot coexist - with media insns. */ - if (major >= FR550_MAJOR_F_1 && major <= FR550_MAJOR_F_4 - && CGEN_INSN_NUM (insn) != FRV_INSN_FNOP) - return ! fr550_find_media_in_vliw (vliw); - /* Media insns other than MNOP in slot m2 or m3 cannot coexist with - floating point insns. */ - if (major >= FR550_MAJOR_M_1 && major <= FR550_MAJOR_M_5 - && CGEN_INSN_NUM (insn) != FRV_INSN_MNOP) - return ! fr550_find_float_in_vliw (vliw); - /* F-2 in slot f2 or f3 cannot coexist with F-2 or F-4 in slot f1 or f2 - respectively. */ - if (major == FR550_MAJOR_F_2) - return ! find_major_in_slot (vliw, FR550_MAJOR_F_2, - slot - (UNIT_FM2 - UNIT_FM0)) - && ! find_major_in_slot (vliw, FR550_MAJOR_F_4, - slot - (UNIT_FM2 - UNIT_FM0)); - /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2 - respectively. */ - if (major == FR550_MAJOR_M_2 || major == FR550_MAJOR_M_5) - return ! find_major_in_slot (vliw, FR550_MAJOR_M_2, - slot - (UNIT_FM2 - UNIT_FM0)); - /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2 - respectively. */ - if (major == FR550_MAJOR_M_4) - return ! find_major_in_slot (vliw, FR550_MAJOR_M_4, - slot - (UNIT_FM2 - UNIT_FM0)); - break; - default: - break; - } - return TRUE; /* All OK. */ -} - -static bfd_boolean -fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) -{ - /* TODO: A table might be faster for some of the more complex instances - here. */ - switch (major) - { - case FR500_MAJOR_I_1: - case FR500_MAJOR_I_4: - case FR500_MAJOR_I_5: - case FR500_MAJOR_I_6: - case FR500_MAJOR_B_1: - case FR500_MAJOR_B_2: - case FR500_MAJOR_B_3: - case FR500_MAJOR_B_4: - case FR500_MAJOR_B_5: - case FR500_MAJOR_B_6: - case FR500_MAJOR_F_4: - case FR500_MAJOR_F_8: - case FR500_MAJOR_M_8: - return TRUE; /* OK */ - case FR500_MAJOR_I_2: - /* Cannot coexist with I-3 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_I_3); - case FR500_MAJOR_I_3: - /* Cannot coexist with I-2 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_I_2); - case FR500_MAJOR_F_1: - case FR500_MAJOR_F_2: - /* Cannot coexist with F-5, F-6, or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_F_3: - /* Cannot coexist with F-7, or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_F_5: - /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_F_6: - /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_F_7: - /* Cannot coexist with F-3, F-5, F-7, or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_M_1: - /* Cannot coexist with M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_M_2: - case FR500_MAJOR_M_3: - /* Cannot coexist with M-5, M-6 or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_M_4: - /* Cannot coexist with M-6 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_M_6); - case FR500_MAJOR_M_5: - /* Cannot coexist with M-2, M-3, M-5, M-6 or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_M_6: - /* Cannot coexist with M-2, M-3, M-4, M-5, M-6 or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_4) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7); - case FR500_MAJOR_M_7: - /* Cannot coexist with M-1, M-2, M-3, M-5, M-6 or M-7 insn. */ - return ! find_major_in_vliw (vliw, FR500_MAJOR_M_1) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_2) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_3) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_M_7) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_1) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_2) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_3) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_5) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_6) - && ! find_major_in_vliw (vliw, FR500_MAJOR_F_7); - default: - fprintf (stderr, "frv-opc.c, line %d: bad major code, aborting.\n", - __LINE__); - abort (); - break; - } - return TRUE; -} - -static bfd_boolean -check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_ENUM_TYPE major, - const CGEN_INSN *insn) -{ - switch (vliw->mach) - { - case bfd_mach_fr400: - return fr400_check_insn_major_constraints (vliw, major); - - case bfd_mach_fr450: - return fr450_check_insn_major_constraints (vliw, major); - - case bfd_mach_fr550: - return fr550_check_insn_major_constraints (vliw, major, insn); - - default: - return fr500_check_insn_major_constraints (vliw, major); - } -} - -/* Add in insn to the VLIW vliw if possible. - Return 0 if successful, non-zero otherwise. */ - -int -frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) -{ - int slot_index; - CGEN_ATTR_VALUE_ENUM_TYPE major; - CGEN_ATTR_VALUE_ENUM_TYPE unit; - VLIW_COMBO *new_vliw; - - if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) - return 1; - - slot_index = vliw->next_slot; - if (slot_index >= FRV_VLIW_SIZE) - return 1; - - unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); - if (unit == UNIT_NIL) - { - fprintf (stderr, "frv-opc.c line %d: bad insn unit.\n", - __LINE__); - abort (); /* No UNIT specified for this insn in frv.cpu. */ - } - - switch (vliw->mach) - { - case bfd_mach_fr400: - major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); - break; - case bfd_mach_fr450: - major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR); - break; - case bfd_mach_fr550: - major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR); - break; - default: - major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); - break; - } - - if (slot_index <= 0) - { - /* Any insn can be added to slot 0. */ - while (! match_unit (vliw, unit, (*vliw->current_vliw)[0])) - ++vliw->current_vliw; - vliw->major[0] = major; - vliw->insn[0] = insn; - vliw->next_slot = 1; - return 0; - } - - /* If there are already insns in the vliw(s) check to see that - this one can be added. Do this by finding an allowable vliw - combination that can accept the new insn. */ - if (! (vliw->elf_flags & EF_FRV_NOPACK)) - { - new_vliw = add_next_to_vliw (vliw, unit); - if (new_vliw && check_insn_major_constraints (vliw, major, insn)) - { - vliw->current_vliw = new_vliw; - vliw->major[slot_index] = major; - vliw->insn[slot_index] = insn; - vliw->next_slot++; - return 0; - } - - /* The frv machine supports all packing conbinations. If we fail, - to add the insn, then it could not be handled as if it was the fr500. - Just return as if it was handled ok. */ - if (vliw->mach == bfd_mach_frv) - return 0; - } - - vliw->constraint_violation = 1; - return 1; -} - -bfd_boolean -spr_valid (long regno) -{ - if (regno < 0) return FALSE; - if (regno <= 4095) return TRUE; - return FALSE; -} -/* -- */ - -/* -- asm.c */ -inline static const char * -parse_symbolic_address (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - int opinfo, - enum cgen_parse_operand_result *resultp, - bfd_vma *valuep) -{ - enum cgen_parse_operand_result result_type; - const char *errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_SYMBOLIC, strp, opindex, opinfo, - &result_type, valuep); - - if (errmsg == NULL - && result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED) - return "symbolic expression required"; - - if (resultp) - *resultp = result_type; - - return errmsg; -} - -static const char * -parse_ldd_annotation (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "tlsdesc(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSDESC_RELAX, - &result_type, &value); - if (**strp != ')') - return "missing ')'"; - if (valuep) - *valuep = value; - ++*strp; - if (errmsg) - return errmsg; - } - } - - while (**strp == ' ' || **strp == '\t') - ++*strp; - - if (**strp != '@') - return "missing `@'"; - - ++*strp; - - return NULL; -} - -static const char * -parse_call_annotation (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "gettlsoff(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GETTLSOFF_RELAX, - &result_type, &value); - if (**strp != ')') - return "missing ')'"; - if (valuep) - *valuep = value; - ++*strp; - if (errmsg) - return errmsg; - } - } - - while (**strp == ' ' || **strp == '\t') - ++*strp; - - if (**strp != '@') - return "missing `@'"; - - ++*strp; - - return NULL; -} - -static const char * -parse_ld_annotation (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "tlsoff(", 7) == 0) - { - *strp += 8; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSOFF_RELAX, - &result_type, &value); - if (**strp != ')') - return "missing ')'"; - if (valuep) - *valuep = value; - ++*strp; - if (errmsg) - return errmsg; - } - } - - while (**strp == ' ' || **strp == '\t') - ++*strp; - - if (**strp != '@') - return "missing `@'"; - - ++*strp; - - return NULL; -} - -static const char * -parse_ulo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "lo(", 3) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, - & result_type, & value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - if (strncasecmp (*strp + 1, "gprello(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GPRELLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0) - { - *strp += 7; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0) - { - *strp += 15; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0) - { - *strp += 10; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0) - { - *strp += 18; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsdesclo(", 13) == 0) - { - *strp += 14; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSDESCLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "tlsmofflo(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSMOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsofflo(", 12) == 0) - { - *strp += 13; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - } - return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -} - -static const char * -parse_uslo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - signed long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "lo(", 3) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_LO16, - & result_type, & value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gprello(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GPRELLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotlo(", 6) == 0) - { - *strp += 7; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotfuncdesclo(", 14) == 0) - { - *strp += 15; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofflo(", 9) == 0) - { - *strp += 10; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofffuncdesclo(", 17) == 0) - { - *strp += 18; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsdesclo(", 13) == 0) - { - *strp += 14; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSDESCLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "tlsmofflo(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSMOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsofflo(", 12) == 0) - { - *strp += 13; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSOFFLO, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - } - return cgen_parse_signed_integer (cd, strp, opindex, valuep); -} - -static const char * -parse_uhi16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "hi(", 3) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_FRV_HI16, - & result_type, & value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - /* If value is wider than 32 bits then be - careful about how we extract bits 16-31. */ - if (sizeof (value) > 4) - value &= (((bfd_vma)1 << 16) << 16) - 1; - - value >>= 16; - } - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gprelhi(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GPRELHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gothi(", 6) == 0) - { - *strp += 7; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotfuncdeschi(", 14) == 0) - { - *strp += 15; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotoffhi(", 9) == 0) - { - *strp += 10; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTOFFHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofffuncdeschi(", 17) == 0) - { - *strp += 18; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTOFFHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsdeschi(", 13) == 0) - { - *strp += 14; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSDESCHI, - &result_type, &value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "tlsmoffhi(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSMOFFHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsoffhi(", 12) == 0) - { - *strp += 13; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSOFFHI, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - } - return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -} - -static long -parse_register_number (const char **strp) -{ - int regno; - - if (**strp < '0' || **strp > '9') - return -1; /* error */ - - regno = **strp - '0'; - for (++*strp; **strp >= '0' && **strp <= '9'; ++*strp) - regno = regno * 10 + (**strp - '0'); - - return regno; -} - -static const char * -parse_spr (CGEN_CPU_DESC cd, - const char **strp, - CGEN_KEYWORD * table, - long *valuep) -{ - const char *save_strp; - long regno; - - /* Check for spr index notation. */ - if (strncasecmp (*strp, "spr[", 4) == 0) - { - *strp += 4; - regno = parse_register_number (strp); - if (**strp != ']') - return _("missing `]'"); - ++*strp; - if (! spr_valid (regno)) - return _("Special purpose register number is out of range"); - *valuep = regno; - return NULL; - } - - save_strp = *strp; - regno = parse_register_number (strp); - if (regno != -1) - { - if (! spr_valid (regno)) - return _("Special purpose register number is out of range"); - *valuep = regno; - return NULL; - } - - *strp = save_strp; - return cgen_parse_keyword (cd, strp, table, valuep); -} - -static const char * -parse_d12 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - /* Check for small data reference. */ - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GPREL12, - & result_type, & value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "got12(", 6) == 0) - { - *strp += 7; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOT12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0) - { - *strp += 15; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOT12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0) - { - *strp += 10; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0) - { - *strp += 18; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsdesc12(", 13) == 0) - { - *strp += 14; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSDESC12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "tlsmoff12(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSMOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsoff12(", 12) == 0) - { - *strp += 13; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - } - return cgen_parse_signed_integer (cd, strp, opindex, valuep); -} - -static const char * -parse_s12 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - /* Check for small data reference. */ - if (**strp == '#' || **strp == '%') - { - if (strncasecmp (*strp + 1, "gprel12(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GPREL12, - & result_type, & value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "got12(", 6) == 0) - { - *strp += 7; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOT12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotfuncdesc12(", 14) == 0) - { - *strp += 15; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOT12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotoff12(", 9) == 0) - { - *strp += 10; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gotofffuncdesc12(", 17) == 0) - { - *strp += 18; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_FUNCDESC_GOTOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsdesc12(", 13) == 0) - { - *strp += 14; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSDESC12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "tlsmoff12(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_TLSMOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp + 1, "gottlsoff12(", 12) == 0) - { - *strp += 13; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GOTTLSOFF12, - & result_type, & value); - if (**strp != ')') - return "missing ')'"; - ++*strp; - *valuep = value; - return errmsg; - } - } - - if (**strp == '#') - ++*strp; - return cgen_parse_signed_integer (cd, strp, opindex, valuep); -} - -static const char * -parse_u12 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - /* Check for small data reference. */ - if ((**strp == '#' || **strp == '%') - && strncasecmp (*strp + 1, "gprel12(", 8) == 0) - { - *strp += 9; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GPRELU12, - & result_type, & value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - *valuep = value; - return errmsg; - } - else - { - if (**strp == '#') - ++*strp; - return cgen_parse_signed_integer (cd, strp, opindex, valuep); - } -} - -static const char * -parse_A (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep, - unsigned long A) -{ - const char *errmsg; - - if (**strp == '#') - ++*strp; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - if (errmsg) - return errmsg; - - if (*valuep != A) - return _("Value of A operand must be 0 or 1"); - - return NULL; -} - -static const char * -parse_A0 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_A (cd, strp, opindex, valuep, 0); -} - -static const char * -parse_A1 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_A (cd, strp, opindex, valuep, 1); -} - -static const char * -parse_even_register (CGEN_CPU_DESC cd, - const char ** strP, - CGEN_KEYWORD * tableP, - long * valueP) -{ - const char * errmsg; - const char * saved_star_strP = * strP; - - errmsg = cgen_parse_keyword (cd, strP, tableP, valueP); - - if (errmsg == NULL && ((* valueP) & 1)) - { - errmsg = _("register number must be even"); - * strP = saved_star_strP; - } - - return errmsg; -} - -static const char * -parse_call_label (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - int opinfo, - enum cgen_parse_operand_result *resultp, - bfd_vma *valuep) -{ - const char *errmsg; - bfd_vma value; - - /* Check for small data reference. */ - if (opinfo == 0 && (**strp == '#' || **strp == '%')) - { - if (strncasecmp (*strp + 1, "gettlsoff(", 10) == 0) - { - *strp += 11; - errmsg = parse_symbolic_address (cd, strp, opindex, - BFD_RELOC_FRV_GETTLSOFF, - resultp, &value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - *valuep = value; - return errmsg; - } - } - - return cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep); -} - -/* -- */ - -/* -- dis.c */ -static void -print_at (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long reloc_ann ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "@"); -} - -static void -print_spr (CGEN_CPU_DESC cd, - void * dis_info, - CGEN_KEYWORD *names, - long regno, - unsigned int attrs) -{ - /* Use the register index format for any unnamed registers. */ - if (cgen_keyword_lookup_value (names, regno) == NULL) - { - disassemble_info *info = (disassemble_info *) dis_info; - (*info->fprintf_func) (info->stream, "spr[%ld]", regno); - } - else - print_keyword (cd, dis_info, names, regno, attrs); -} - -static void -print_hi (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, value ? "0x%lx" : "hi(0x%lx)", value); -} - -static void -print_lo (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - if (value) - (*info->fprintf_func) (info->stream, "0x%lx", value); - else - (*info->fprintf_func) (info->stream, "lo(0x%lx)", value); -} - -/* -- */ diff --git a/binutils-2.24/cpu/ip2k.cpu b/binutils-2.24/cpu/ip2k.cpu deleted file mode 100644 index f329eab4..00000000 --- a/binutils-2.24/cpu/ip2k.cpu +++ /dev/null @@ -1,1480 +0,0 @@ -; Ubicom IP2K CPU description. -*- Scheme -*- -; Copyright (C) 2002, 2009, 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -; define-arch must appear first - -(define-arch - (name ip2k) ; name of cpu family - (comment "Ubicom IP2000 family") - (default-alignment aligned) - (insn-lsb0? #t) - (machs ip2022 ip2022ext) - (isas ip2k) -) - -; Attributes. - -(define-attr - (for insn) - (type boolean) - (name EXT-SKIP-INSN) - (comment "instruction is a PAGE, LOADL, LOADH or BREAKX instruction") -) - -(define-attr - (for insn) - (type boolean) - (name SKIPA) - (comment "instruction is a SKIP instruction") -) - -; Instruction set parameters. - -(define-isa - (name ip2k) - (comment "Ubicom IP2000 ISA") - - (default-insn-word-bitsize 16) - (default-insn-bitsize 16) - (base-insn-bitsize 16) -) - -; Cpu family definitions. - - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - (name ip2kbf) - (comment "Ubicom IP2000 Family") - (endian big) - (word-bitsize 16) -) - -(define-mach - (name ip2022) - (comment "Ubicom IP2022") - (cpu ip2kbf) -) - -(define-mach - (name ip2022ext) - (comment "Ubicom IP2022 extended") - (cpu ip2kbf) -) - - -; Model descriptions. - -(define-model - (name ip2k) (comment "VPE 2xxx") (attrs) - (mach ip2022ext) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - - -; FIXME: It might simplify things to separate the execute process from the -; one that updates the PC. - -; Instruction fields. -; -; Attributes: -; XXX: what VPE attrs -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 -; RELOC: there is a relocation associated with this field (experiment) - - -(dnf f-imm8 "imm8" () 7 8) -(dnf f-reg "reg" (ABS-ADDR) 8 9) -(dnf f-addr16cjp "addr16cjp" (ABS-ADDR) 12 13) -(dnf f-dir "dir" () 9 1) -(dnf f-bitno "bit number" () 11 3) -(dnf f-op3 "op3" () 15 3) -(dnf f-op4 "op4" () 15 4) -(dnf f-op4mid "op4mid" () 11 4) -(dnf f-op6 "op6" () 15 6) -(dnf f-op8 "op8" () 15 8) -(dnf f-op6-10low "op6-10low" () 9 10) -(dnf f-op6-7low "op6-7low" () 9 7) -(dnf f-reti3 "reti3" () 2 3) -(dnf f-skipb "sb/snb" (ABS-ADDR) 12 1) -(dnf f-page3 "page3" () 2 3) -;(define-ifield (name f-page3) (comment "page3") (attrs) (start 2) (length 3) -; (encode (value pc) (srl WI value 13)) -; (decode (value pc) (sll WI value 13)) -;) -; To fix the page/call asymmetry -;(define-ifield (name f-page3) (comment "page3") (attrs) (start 2) (length 3) -; (encode (value pc) (srl WI value 13)) -; (decode (value pc) (sll WI value 13)) -;) - - - -; Enums. - -; insn-op6: bits 15-10 -(define-normal-insn-enum insn-op6 "op6 enums" () OP6_ f-op6 - (OTHER1 OTHER2 SUB DEC OR AND XOR ADD - TEST NOT INC DECSZ RR RL SWAP INCSZ - CSE POP SUBC DECSNZ MULU MULS INCSNZ ADDC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ) -) - -; insn-dir: bit 9 -(define-normal-insn-enum insn-dir "dir enums" () DIR_ f-dir - ; This bit specifies the polarity of many two-operand instructions: - ; TO_W writes result to W regiser (eg. ADDC W,$fr) - ; NOTTO_W writes result in general register (eg. ADDC $fr,W) - (TO_W NOTTO_W) -) - - -; insn-op4: bits 15-12 -(define-normal-insn-enum insn-op4 "op4 enums" () OP4_ f-op4 - (- - - - - - - LITERAL - CLRB SETB SNB SB - - - - - ) -) - -; insn-op4mid: bits 11-8 -; used for f-op4=LITERAL -(define-normal-insn-enum insn-op4mid "op4mid enums" () OP4MID_ f-op4mid - (LOADH_L LOADL_L MULU_L MULS_L PUSH_L - CSNE_L CSE_L - RETW_L CMP_L SUB_L ADD_L MOV_L OR_L AND_L XOR_L) -) - -; insn-op3: bits 15-13 -(define-normal-insn-enum insn-op3 "op3 enums" () OP3_ f-op3 - (- - - - - - CALL JMP) -) - - - -; Hardware pieces. - -; Bank-relative general purpose registers - -; (define-pmacro (build-reg-name n) (.splice (.str "$" n) n)) - -(define-keyword - (name register-names) - (enum-prefix H-REGISTERS-) - (values - ; These are the "Special Purpose Registers" that are not reserved - ("ADDRSEL" #x2) ("ADDRX" #x3) - ("IPH" #x4) ("IPL" #x5) ("SPH" #x6) ("SPL" #x7) - ("PCH" #x8) ("PCL" #x9) ("WREG" #xA) ("STATUS" #xB) - ("DPH" #xC) ("DPL" #xD) ("SPDREG" #xE) ("MULH" #xF) - ("ADDRH" #x10) ("ADDRL" #x11) ("DATAH" #x12) ("DATAL" #x13) - ("INTVECH" #x14) ("INTVECL" #x15) ("INTSPD" #x16) ("INTF" #x17) - ("INTE" #x18) ("INTED" #x19) ("FCFG" #x1A) ("TCTRL" #x1B) - ("XCFG" #x1C) ("EMCFG" #x1D) ("IPCH" #x1E) ("IPCL" #x1F) - ("RAIN" #x20) ("RAOUT" #x21) ("RADIR" #x22) ("LFSRH" #x23) - ("RBIN" #x24) ("RBOUT" #x25) ("RBDIR" #x26) ("LFSRL" #x27) - ("RCIN" #x28) ("RCOUT" #x29) ("RCDIR" #x2A) ("LFSRA" #x2B) - ("RDIN" #x2C) ("RDOUT" #x2D) ("RDDIR" #x2E) - ("REIN" #x30) ("REOUT" #x31) ("REDIR" #x32) - ("RFIN" #x34) ("RFOUT" #x35) ("RFDIR" #x36) - ("RGOUT" #x39) ("RGDIR" #x3A) - ("RTTMR" #x40) ("RTCFG" #x41) ("T0TMR" #x42) ("T0CFG" #x43) - ("T1CNTH" #x44) ("T1CNTL" #x45) ("T1CAP1H" #x46) ("T1CAP1L" #x47) - ("T1CAP2H" #x48) ("T1CMP2H" #x48) ("T1CAP2L" #x49) ("T1CMP2L" #x49) ; note aliases - ("T1CMP1H" #x4A) ("T1CMP1L" #x4B) - ("T1CFG1H" #x4C) ("T1CFG1L" #x4D) ("T1CFG2H" #x4E) ("T1CFG2L" #x4F) - ("ADCH" #x50) ("ADCL" #x51) ("ADCCFG" #x52) ("ADCTMR" #x53) - ("T2CNTH" #x54) ("T2CNTL" #x55) ("T2CAP1H" #x56) ("T2CAP1L" #x57) - ("T2CAP2H" #x58) ("T2CMP2H" #x58) ("T2CAP2L" #x59) ("T2CMP2L" #x59) ; note aliases - ("T2CMP1H" #x5A) ("T2CMP1L" #x5B) - ("T2CFG1H" #x5C) ("T2CFG1L" #x5D) ("T2CFG2H" #x5E) ("T2CFG2L" #x5F) - ("S1TMRH" #x60) ("S1TMRL" #x61) ("S1TBUFH" #x62) ("S1TBUFL" #x63) - ("S1TCFG" #x64) ("S1RCNT" #x65) ("S1RBUFH" #x66) ("S1RBUFL" #x67) - ("S1RCFG" #x68) ("S1RSYNC" #x69) ("S1INTF" #x6A) ("S1INTE" #x6B) - ("S1MODE" #x6C) ("S1SMASK" #x6D) ("PSPCFG" #x6E) ("CMPCFG" #x6F) - ("S2TMRH" #x70) ("S2TMRL" #x71) ("S2TBUFH" #x72) ("S2TBUFL" #x73) - ("S2TCFG" #x74) ("S2RCNT" #x75) ("S2RBUFH" #x76) ("S2RBUFL" #x77) - ("S2RCFG" #x78) ("S2RSYNC" #x79) ("S2INTF" #x7A) ("S2INTE" #x7B) - ("S2MODE" #x7C) ("S2SMASK" #x7D) ("CALLH" #x7E) ("CALLL" #x7F)) - ) - -(define-hardware - (name h-spr) - (comment "special-purpose registers") - (type register QI (128)) - (get (index) (c-call QI "get_spr" index )) - (set (index newval) (c-call VOID "set_spr" index newval )) -) - - -;;(define-hardware -;; (name h-gpr-global) -;; (comment "gpr registers - global") -;; (type register QI (128)) -;;) - -; The general register - -(define-hardware - (name h-registers) - (comment "all addressable registers") - (attrs VIRTUAL) - (type register QI (512)) - (get (index) (c-call QI "get_h_registers" index )) - (set (index newval) (c-call VOID "set_h_registers" index newval )) -) - -; The hardware stack. -; Use {push,pop}_pc_stack c-calls to operate on this hardware element. - -(define-hardware - (name h-stack) - (comment "hardware stack") - (type register UHI (16)) -) - -(dsh h-pabits "page bits" () (register QI)) -(dsh h-zbit "zero bit" () (register BI)) -(dsh h-cbit "carry bit" () (register BI)) -(dsh h-dcbit "digit-carry bit" () (register BI)) -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - - -; Operands - -(define-operand (name addr16cjp) (comment "13-bit address") (attrs) - (type h-uint) (index f-addr16cjp) (handlers (parse "addr16_cjp") (print "dollarhex_cj"))) ; overload lit8 printer -(define-operand (name fr) (comment "register") (attrs) - (type h-registers) (index f-reg) (handlers (parse "fr") (print "fr"))) -(define-operand (name lit8) (comment "8-bit signed literal") (attrs) - (type h-sint) (index f-imm8) (handlers (parse "lit8") (print "dollarhex8"))) -(define-operand (name bitno) (comment "bit number") (attrs) - (type h-uint) (index f-bitno) (handlers (parse "bit3")(print "decimal"))) -(define-operand (name addr16p) (comment "page number") (attrs) - (type h-uint) (index f-page3) (handlers (parse "addr16_cjp") (print "dollarhex_p"))) -(define-operand (name addr16h) (comment "high 8 bits of address") (attrs) - (type h-uint) (index f-imm8) (handlers (parse "addr16") (print "dollarhex_addr16h"))) -(define-operand (name addr16l) (comment "low 8 bits of address") (attrs) - (type h-uint) (index f-imm8) (handlers (parse "addr16") (print "dollarhex_addr16l"))) -(define-operand (name reti3) (comment "reti flags") (attrs) - (type h-uint) (index f-reti3) (handlers (print "dollarhex"))) -(dnop pabits "page bits" () h-pabits f-nil) -(dnop zbit "zero bit" () h-zbit f-nil) -(dnop cbit "carry bit" () h-cbit f-nil) -(dnop dcbit "digit carry bit" () h-dcbit f-nil) -;;(dnop bank "bank register" () h-bank-no f-nil) - -(define-pmacro w (reg h-spr #x0A)) -(define-pmacro mulh (reg h-spr #x0F)) -(define-pmacro dph (reg h-spr #x0C)) -(define-pmacro dpl (reg h-spr #x0D)) -(define-pmacro sph (reg h-spr #x06)) -(define-pmacro spl (reg h-spr #x07)) -(define-pmacro iph (reg h-spr #x04)) -(define-pmacro ipl (reg h-spr #x05)) -(define-pmacro addrh (reg h-spr #x10)) -(define-pmacro addrl (reg h-spr #x11)) - - - -; Pseudo-RTL for DC flag calculations -; "DC" = "digit carry", ie carry between nibbles -(define-pmacro (add-dcflag a b c) - (add-cflag (sll QI a 4) (sll QI b 4) c) -) - -(define-pmacro (sub-dcflag a b c) - (sub-cflag (sll QI a 4) (sll QI b 4) c) -) - -; Check to see if an fr is one of IPL, SPL, DPL, ADDRL, PCL. -(define-pmacro (LregCheck isLreg fr9bit) - (sequence() - (set isLreg #x0) ;; Assume it's not an Lreg - (if (or (or (eq fr9bit #x5) (eq fr9bit #x7)) - (or (eq fr9bit #x9) - (or (eq fr9bit #xd) (eq fr9bit #x11)))) - (set isLreg #x1) - ) - ) -) - - -; Instructions, in order of the "Instruction Set Map" table on -; pp 19-20 of IP2022 spec V1.09 - -(dni jmp "Jump" - () - "jmp $addr16cjp" - (+ OP3_JMP addr16cjp) - (set pc (or (sll pabits 13) addr16cjp)) - () -) - -; note that in call, we push pc instead of pc + 1 because the ip2k increments -; the pc prior to execution of the instruction -(dni call "Call" - () - "call $addr16cjp" - (+ OP3_CALL addr16cjp) - (sequence () - (c-call "push_pc_stack" pc) - (set pc (or (sll pabits 13) addr16cjp))) - () -) - -(dni sb "Skip if bit set" - () - "sb $fr,$bitno" - (+ OP4_SB bitno fr) - (if (and fr (sll 1 bitno)) - (skip 1)) - () -) - -(dni snb "Skip if bit clear" - () - "snb $fr,$bitno" - (+ OP4_SNB bitno fr) - (if (not (and fr (sll 1 bitno))) - (skip 1)) - () -) - -(dni setb "Set bit" - () - "setb $fr,$bitno" - (+ OP4_SETB bitno fr) - (set fr (or fr (sll 1 bitno))) - () -) - -(dni clrb "Clear bit" - () - "clrb $fr,$bitno" - (+ OP4_CLRB bitno fr) - (set fr (and fr (inv (sll 1 bitno)))) - () -) - -(dni xorw_l "XOR W,literal" - () - "xor W,#$lit8" - (+ OP4_LITERAL OP4MID_XOR_L lit8) - (sequence () - (set w (xor w lit8)) - (set zbit (zflag w))) - () -) - -(dni andw_l "AND W,literal" - () - "and W,#$lit8" - (+ OP4_LITERAL OP4MID_AND_L lit8) - (sequence () - (set w (and w lit8)) - (set zbit (zflag w))) - () -) - -(dni orw_l "OR W,literal" - () - "or W,#$lit8" - (+ OP4_LITERAL OP4MID_OR_L lit8) - (sequence () - (set w (or w lit8)) - (set zbit (zflag w))) - () -) - -(dni addw_l "ADD W,literal" - () - "add W,#$lit8" - (+ OP4_LITERAL OP4MID_ADD_L lit8) - (sequence () - (set cbit (add-cflag w lit8 0)) - (set dcbit (add-dcflag w lit8 0)) - (set w (add w lit8)) - (set zbit (zflag w))) - () -) - -(dni subw_l "SUB W,literal" - () - "sub W,#$lit8" - (+ OP4_LITERAL OP4MID_SUB_L lit8) - (sequence () - (set cbit (not (sub-cflag lit8 w 0))) - (set dcbit (not (sub-dcflag lit8 w 0))) - (set zbit (zflag (sub w lit8))) - (set w (sub lit8 w))) - () -) - -(dni cmpw_l "CMP W,literal" - () - "cmp W,#$lit8" - (+ OP4_LITERAL OP4MID_CMP_L lit8) - (sequence () - (set cbit (not (sub-cflag lit8 w 0))) - (set dcbit (not (sub-dcflag lit8 w 0))) - (set zbit (zflag (sub w lit8)))) - () -) - -(dni retw_l "RETW literal" - () - "retw #$lit8" - (+ OP4_LITERAL OP4MID_RETW_L lit8) - (sequence ((USI new_pc)) - (set w lit8) - (set new_pc (c-call UHI "pop_pc_stack")) - (set pabits (srl new_pc 13)) - (set pc new_pc)) - () -) - -(dni csew_l "CSE W,literal" - () - "cse W,#$lit8" - (+ OP4_LITERAL OP4MID_CSE_L lit8) - (if (eq w lit8) - (skip 1)) - () -) - -(dni csnew_l "CSNE W,literal" - () - "csne W,#$lit8" - (+ OP4_LITERAL OP4MID_CSNE_L lit8) - (if (not (eq w lit8)) - (skip 1)) - () -) - -(dni push_l "Push #lit8" - () - "push #$lit8" - (+ OP4_LITERAL OP4MID_PUSH_L lit8) - (sequence () - (c-call "push" lit8) - (c-call VOID "adjuststackptr" (const -1)) - - ) - () -) - -(dni mulsw_l "Multiply W,literal (signed)" - () - "muls W,#$lit8" - (+ OP4_LITERAL OP4MID_MULS_L lit8) - (sequence ((SI tmp)) - (set tmp (mul (ext SI w) (ext SI (and UQI #xff lit8)))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni muluw_l "Multiply W,literal (unsigned)" - () - "mulu W,#$lit8" - (+ OP4_LITERAL OP4MID_MULU_L lit8) - (sequence ((USI tmp)) - (set tmp (and #xFFFF (mul (zext USI w) (zext USI lit8)))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni loadl_l "LoadL literal" - (EXT-SKIP-INSN) - "loadl #$lit8" - (+ OP4_LITERAL OP4MID_LOADL_L lit8) - (set dpl (and lit8 #x00FF)) - () -) - -(dni loadh_l "LoadH literal" - (EXT-SKIP-INSN) - "loadh #$lit8" - (+ OP4_LITERAL OP4MID_LOADH_L lit8) - (set dph (and lit8 #x00FF)) - () -) - -(dni loadl_a "LoadL addr16l" - (EXT-SKIP-INSN) - "loadl $addr16l" - (+ OP4_LITERAL OP4MID_LOADL_L addr16l) - (set dpl (and addr16l #x00FF)) - () -) - -(dni loadh_a "LoadH addr16h" - (EXT-SKIP-INSN) - "loadh $addr16h" - (+ OP4_LITERAL OP4MID_LOADH_L addr16h) - (set dph (and addr16l #x0FF00)) - () -) - -;; THIS NO LONGER EXISTS -> Now LOADL -;;(dni bank_l "Bank literal" -;; () -;; "bank #$lit8" -;; (+ OP4_LITERAL OP4MID_BANK_L lit8) -;; (set bank lit8) -;; () -;;) - -(dni addcfr_w "Add w/carry fr,W" - () - "addc $fr,W" - (+ OP6_ADDC DIR_NOTTO_W fr) - (sequence ((QI result) (BI newcbit) (QI isLreg) (HI 16bval)) - (set newcbit (add-cflag w fr cbit)) - (set dcbit (add-dcflag w fr cbit)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (LregCheck isLreg (ifield f-reg)) - (if (eq isLreg #x1) - (sequence() - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - (set 16bval (addc HI 16bval w cbit)) - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - (set result (addc w fr cbit)) ;; else part - ) - - (set zbit (zflag result)) - (set cbit newcbit) - (set fr result)) - () -) - -(dni addcw_fr "Add w/carry W,fr" - () - "addc W,$fr" - (+ OP6_ADDC DIR_TO_W fr) - (sequence ((QI result) (BI newcbit)) - (set newcbit (add-cflag w fr cbit)) - (set dcbit (add-dcflag w fr cbit)) - (set result (addc w fr cbit)) - (set zbit (zflag result)) - (set cbit newcbit) - (set w result)) - () -) - - -(dni incsnz_fr "Skip if fr++ not zero" - () - "incsnz $fr" - (+ OP6_INCSNZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; Do 16 bit arithmetic. - (set 16bval (add HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - (set fr (add fr 1)) ; Do 8 bit arithmetic. - ) - (if (not (zflag fr)) - (skip 1))) - () -) - -(dni incsnzw_fr "Skip if W=fr+1 not zero" - () - "incsnz W,$fr" - (+ OP6_INCSNZ DIR_TO_W fr) - (sequence () - (set w (add fr 1)) - (if (not (zflag w)) - (skip 1))) - () -) - -(dni mulsw_fr "Multiply W,fr (signed)" - () - "muls W,$fr" - (+ OP6_MULS DIR_TO_W fr) - (sequence ((SI tmp)) - (set tmp (mul (ext SI w) (ext SI fr))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni muluw_fr "Multiply W,fr (unsigned)" - () - "mulu W,$fr" - (+ OP6_MULU DIR_TO_W fr) - (sequence ((USI tmp)) - (set tmp (and #xFFFF (mul (zext USI w) (zext USI fr)))) - (set w (and tmp #xFF)) - (set mulh (srl tmp 8))) - () -) - -(dni decsnz_fr "Skip if fr-- not zero" - () - "decsnz $fr" - (+ OP6_DECSNZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (sub fr 1)) - ) - (if (not (zflag fr)) - (skip 1))) - () -) - -(dni decsnzw_fr "Skip if W=fr-1 not zero" - () - "decsnz W,$fr" - (+ OP6_DECSNZ DIR_TO_W fr) - (sequence () - (set w (sub fr 1)) - (if (not (zflag w)) - (skip 1))) - () -) - -(dni subcw_fr "Subract w/carry W,fr" - () - "subc W,$fr" - (+ OP6_SUBC DIR_TO_W fr) - (sequence ((QI result) (BI newcbit)) - (set newcbit (not (sub-cflag fr w (not cbit)))) - (set dcbit (not (sub-dcflag fr w (not cbit)))) - (set result (subc fr w (not cbit))) - (set zbit (zflag result)) - (set cbit newcbit) - (set w result)) - () -) - -(dni subcfr_w "Subtract w/carry fr,W" - () - "subc $fr,W" - (+ OP6_SUBC DIR_NOTTO_W fr) - (sequence ((QI result) (BI newcbit) (QI isLreg) (HI 16bval)) - (set newcbit (not (sub-cflag fr w (not cbit)))) - (set dcbit (not (sub-dcflag fr w (not cbit)))) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (subc HI 16bval w (not cbit))) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set result (subc fr w (not cbit))) - ) - - - (set zbit (zflag result)) - (set cbit newcbit) - (set fr result)) - () -) - - -(dni pop_fr "Pop fr" - () - "pop $fr" - (+ OP6_POP (f-dir 1) fr) - (sequence() - (set fr (c-call QI "pop")) - (c-call VOID "adjuststackptr" (const 1)) - ) - () -) - -(dni push_fr "Push fr" - () - "push $fr" - (+ OP6_POP (f-dir 0) fr) - (sequence() - (c-call "push" fr) - (c-call VOID "adjuststackptr" (const -1)) - ) - () -) - -(dni csew_fr "Skip if equal W,fr" - () - "cse W,$fr" - (+ OP6_CSE (f-dir 1) fr) - (if (eq w fr) - (skip 1)) - () -) - -(dni csnew_fr "Skip if not-equal W,fr" - () - "csne W,$fr" - (+ OP6_CSE (f-dir 0) fr) - (if (not (eq w fr)) - (skip 1)) - () -) - -;;(dni csaw_fr "Skip if W above fr" -;; ((MACH ip2022ext)) -;; "csa W,$fr" -;; (+ OP6_CSAB (f-dir 1) fr) -;; (if (gt w fr) -;; (skip 1)) -;; () -;;) - -;;(dni csbw_fr "Skip if W below fr" -;; ((MACH ip2022ext)) -;; "csb W,$fr" -;; (+ OP6_CSAB (f-dir 0) fr) -;; (if (lt w fr) -;; (skip 1)) -;; () -;;) - -(dni incsz_fr "Skip if fr++ zero" - () - "incsz $fr" - (+ OP6_INCSZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (add HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (add fr 1)) - ) - (if (zflag fr) - (skip 1))) - () -) - -(dni incszw_fr "Skip if W=fr+1 zero" - () - "incsz W,$fr" - (+ OP6_INCSZ DIR_TO_W fr) - (sequence () - (set w (add fr 1)) - (if (zflag w) - (skip 1))) - () -) - -(dni swap_fr "Swap fr nibbles" - () - "swap $fr" - (+ OP6_SWAP DIR_NOTTO_W fr) - (set fr (or (and (sll fr 4) #xf0) - (and (srl fr 4) #x0f))) - () -) - -(dni swapw_fr "Swap fr nibbles into W" - () - "swap W,$fr" - (+ OP6_SWAP DIR_TO_W fr) - (set w (or (and (sll fr 4) #xf0) - (and (srl fr 4) #x0f))) - () -) - -(dni rl_fr "Rotate fr left with carry" - () - "rl $fr" - (+ OP6_RL DIR_NOTTO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x80)) - (set newfr (or (sll fr 1) (if QI cbit 1 0))) - (set cbit (if QI newc 1 0)) - (set fr newfr)) - () -) - -(dni rlw_fr "Rotate fr left with carry into W" - () - "rl W,$fr" - (+ OP6_RL DIR_TO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x80)) - (set newfr (or (sll fr 1) (if QI cbit 1 0))) - (set cbit (if QI newc 1 0)) - (set w newfr)) - () -) - -(dni rr_fr "Rotate fr right with carry" - () - "rr $fr" - (+ OP6_RR DIR_NOTTO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x01)) - (set newfr (or (srl fr 1) (if QI cbit #x80 #x00))) - (set cbit (if QI newc 1 0)) - (set fr newfr)) - () -) - -(dni rrw_fr "Rotate fr right with carry into W" - () - "rr W,$fr" - (+ OP6_RR DIR_TO_W fr) - (sequence ((QI newfr) (BI newc)) - (set newc (and fr #x01)) - (set newfr (or (srl fr 1) (if QI cbit #x80 #x00))) - (set cbit (if QI newc 1 0)) - (set w newfr)) - () -) - -(dni decsz_fr "Skip if fr-- zero" - () - "decsz $fr" - (+ OP6_DECSZ DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (sub fr 1)) - ) - (if (zflag fr) - (skip 1))) - () -) - -(dni decszw_fr "Skip if W=fr-1 zero" - () - "decsz W,$fr" - (+ OP6_DECSZ DIR_TO_W fr) - (sequence () - (set w (sub fr 1)) - (if (zflag w) - (skip 1))) - () -) - -(dni inc_fr "Increment fr" - () - "inc $fr" - (+ OP6_INC DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (add HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (add fr 1)) - ) - (set zbit (zflag fr))) - () -) - -(dni incw_fr "Increment fr into w" - () - "inc W,$fr" - (+ OP6_INC DIR_TO_W fr) - (sequence () - (set w (add fr 1)) - (set zbit (zflag w))) - () -) - -(dni not_fr "Invert fr" - () - "not $fr" - (+ OP6_NOT DIR_NOTTO_W fr) - (sequence () - (set fr (inv fr)) - (set zbit (zflag fr))) - () -) - -(dni notw_fr "Invert fr into w" - () - "not W,$fr" - (+ OP6_NOT DIR_TO_W fr) - (sequence () - (set w (inv fr)) - (set zbit (zflag w))) - () -) - -(dni test_fr "Test fr" - () - "test $fr" - (+ OP6_TEST DIR_NOTTO_W fr) - (sequence () - (set zbit (zflag fr))) - () -) - -(dni movw_l "MOV W,literal" - () - "mov W,#$lit8" - (+ OP4_LITERAL OP4MID_MOV_L lit8) - (set w lit8) - () -) - -(dni movfr_w "Move/test w into fr" - () - "mov $fr,W" - (+ OP6_OTHER1 DIR_NOTTO_W fr) - (set fr w) - () -) - -(dni movw_fr "Move/test fr into w" - () - "mov W,$fr" - (+ OP6_TEST DIR_TO_W fr) - (sequence () - (set w fr) - (set zbit (zflag w))) - () -) - - -(dni addfr_w "Add fr,W" - () - "add $fr,W" - (+ OP6_ADD DIR_NOTTO_W fr) - (sequence ((QI result) (QI isLreg) (HI 16bval)) - (set cbit (add-cflag w fr 0)) - (set dcbit (add-dcflag w fr 0)) - (LregCheck isLreg (ifield f-reg)) - - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - (set 16bval (add HI (and w #xFF) 16bval)) - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - (set result (addc w fr 0)) ;; else part - ) - (set zbit (zflag result)) - (set fr result)) - () -) - -(dni addw_fr "Add W,fr" - () - "add W,$fr" - (+ OP6_ADD DIR_TO_W fr) - (sequence ((QI result)) - (set cbit (add-cflag w fr 0)) - (set dcbit (add-dcflag w fr 0)) - (set result (addc w fr 0)) - (set zbit (zflag result)) - (set w result)) - () -) - -(dni xorfr_w "XOR fr,W" - () - "xor $fr,W" - (+ OP6_XOR DIR_NOTTO_W fr) - (sequence () - (set fr (xor w fr)) - (set zbit (zflag fr))) - () -) - -(dni xorw_fr "XOR W,fr" - () - "xor W,$fr" - (+ OP6_XOR DIR_TO_W fr) - (sequence () - (set w (xor fr w)) - (set zbit (zflag w))) - () -) - -(dni andfr_w "AND fr,W" - () - "and $fr,W" - (+ OP6_AND DIR_NOTTO_W fr) - (sequence () - (set fr (and w fr)) - (set zbit (zflag fr))) - () -) - -(dni andw_fr "AND W,fr" - () - "and W,$fr" - (+ OP6_AND DIR_TO_W fr) - (sequence () - (set w (and fr w)) - (set zbit (zflag w))) - () -) - -(dni orfr_w "OR fr,W" - () - "or $fr,W" - (+ OP6_OR DIR_NOTTO_W fr) - (sequence () - (set fr (or w fr)) - (set zbit (zflag fr))) - () -) - -(dni orw_fr "OR W,fr" - () - "or W,$fr" - (+ OP6_OR DIR_TO_W fr) - (sequence () - (set w (or fr w)) - (set zbit (zflag w))) - () -) - -(dni dec_fr "Decrement fr" - () - "dec $fr" - (+ OP6_DEC DIR_NOTTO_W fr) - (sequence ((QI isLreg) (HI 16bval)) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval 1)) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set fr (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set fr (sub fr 1)) - ) - (set zbit (zflag fr))) - () -) - -(dni decw_fr "Decrement fr into w" - () - "dec W,$fr" - (+ OP6_DEC DIR_TO_W fr) - (sequence () - (set w (sub fr 1)) - (set zbit (zflag w))) - () -) - -(dni subfr_w "Sub fr,W" - () - "sub $fr,W" - (+ OP6_SUB DIR_NOTTO_W fr) - (sequence ((QI result) (QI isLreg) (HI 16bval)) - (set cbit (not (sub-cflag fr w 0))) - (set dcbit (not (sub-dcflag fr w 0))) - (LregCheck isLreg (ifield f-reg)) - ;; If fr is an Lreg, then we have to do 16-bit arithmetic. - ;; We can take advantage of the fact that by a lucky - ;; coincidence, the address of register xxxH is always - ;; one lower than the address of register xxxL. - (if (eq isLreg #x1) - (sequence() - ; Create the 16 bit value - (set 16bval (reg h-spr (sub (ifield f-reg) 1))) - (set 16bval (sll 16bval 8)) - (set 16bval (or 16bval (and (reg h-spr (ifield f-reg)) #xFF))) - ; New 16 bit instruction - (set 16bval (sub HI 16bval (and w #xFF))) - ; Separate the 16 bit values into the H and L regs - (set (reg h-spr (ifield f-reg)) (and 16bval #xFF)) - (set (reg h-spr (sub (ifield f-reg) 1)) - (and (srl 16bval 8) #xFF)) - (set result (reg h-spr (ifield f-reg))) - ) - ; Original instruction - (set result (subc fr w 0)) - ) - (set zbit (zflag result)) - (set fr result)) - () -) - -(dni subw_fr "Sub W,fr" - () - "sub W,$fr" - (+ OP6_SUB DIR_TO_W fr) - (sequence ((QI result)) - (set cbit (not (sub-cflag fr w 0))) - (set dcbit (not (sub-dcflag fr w 0))) - (set result (subc fr w 0)) - (set zbit (zflag result)) - (set w result)) - () -) - -(dni clr_fr "Clear fr" - () - "clr $fr" - (+ OP6_OTHER2 (f-dir 1) fr) - (sequence () - (set fr 0) - (set zbit (zflag fr))) - () -) - -(dni cmpw_fr "CMP W,fr" - () - "cmp W,$fr" - (+ OP6_OTHER2 (f-dir 0) fr) - (sequence () - (set cbit (not (sub-cflag fr w 0))) - (set dcbit (not (sub-dcflag fr w 0))) - (set zbit (zflag (sub w fr)))) - () -) - -(dni speed "Set speed" - () - "speed #$lit8" - (+ (f-op8 1) lit8) - (set (reg h-registers #x0E) lit8) - () -) - -(dni ireadi "Insn memory read with increment" - () - "ireadi" - (+ OP6_OTHER1 (f-op6-10low #x1D)) - (c-call "do_insn_read") - () -) - -(dni iwritei "Insn memory write with increment" - () - "iwritei" - (+ OP6_OTHER1 (f-op6-10low #x1C)) - (c-call "do_insn_write") - () -) - -(dni fread "Flash read" - () - "fread" - (+ OP6_OTHER1 (f-op6-10low #x1B)) - (c-call "do_flash_read") - () -) - -(dni fwrite "Flash write" - () - "fwrite" - (+ OP6_OTHER1 (f-op6-10low #x1A)) - (c-call "do_flash_write") - () -) - -(dni iread "Insn memory read" - () - "iread" - (+ OP6_OTHER1 (f-op6-10low #x19)) - (c-call "do_insn_read") - () -) - -(dni iwrite "Insn memory write" - () - "iwrite" - (+ OP6_OTHER1 (f-op6-10low #x18)) - (c-call "do_insn_write") - () -) - -(dni page "Set insn page" - (EXT-SKIP-INSN) - ;"page $page3" - "page $addr16p" - ;(+ OP6_OTHER1 (f-op6-7low #x2) page3) - ;(set pabits (srl page3 13)) - (+ OP6_OTHER1 (f-op6-7low #x2) addr16p) - (set pabits addr16p) - () -) - -(dni system "System call" - () - "system" - (+ OP6_OTHER1 (f-op6-10low #xff)) - (c-call "do_system") - () -) - -(dni reti "Return from interrupt" - () - "reti #$reti3" - (+ OP6_OTHER1 (f-op6-7low #x1) reti3) - (c-call "do_reti" reti3) - () -) - -(dni ret "Return" - () - "ret" - (+ OP6_OTHER1 (f-op6-10low #x07)) - (sequence ((USI new_pc)) - (set new_pc (c-call UHI "pop_pc_stack")) - (set pabits (srl new_pc 13)) - (set pc new_pc)) - () -) - -(dni int "Software interrupt" - () - "int" - (+ OP6_OTHER1 (f-op6-10low #x6)) - (nop) - () -) - -(dni breakx "Breakpoint with extended skip" - (EXT-SKIP-INSN) - "breakx" - (+ OP6_OTHER1 (f-op6-10low #x5)) - (c-call "do_break" pc) - () -) - -(dni cwdt "Clear watchdog timer" - () - "cwdt" - (+ OP6_OTHER1 (f-op6-10low #x4)) - (c-call "do_clear_wdt") - () -) - -(dni ferase "Flash erase" - () - "ferase" - (+ OP6_OTHER1 (f-op6-10low #x3)) - (c-call "do_flash_erase") - () -) - -(dni retnp "Return, no page" - () - "retnp" - (+ OP6_OTHER1 (f-op6-10low #x2)) - (sequence ((USI new_pc)) - (set new_pc (c-call UHI "pop_pc_stack")) - (set pc new_pc)) - () -) - -(dni break "Breakpoint" - () - "break" - (+ OP6_OTHER1 (f-op6-10low #x1)) - (c-call "do_break" pc) - () -) - -(dni nop "No operation" - () - "nop" - (+ OP6_OTHER1 (f-op6-10low #x0)) - (nop) - () -) - - -; Macro instructions -(dnmi sc "Skip on carry" - () - "sc" - (emit sb (bitno 0) (fr #xB)) ; sb status.0 -) - -(dnmi snc "Skip on no carry" - () - "snc" - (emit snb (bitno 0) (fr #xB)) ; snb status.0 -) - -(dnmi sz "Skip on zero" - () - "sz" - (emit sb (bitno 2) (fr #xB)) ; sb status.2 -) - -(dnmi snz "Skip on no zero" - () - "snz" - (emit snb (bitno 2) (fr #xB)) ; snb status.2 -) - -(dnmi skip "Skip always" - (SKIPA) - "skip" - (emit snb (bitno 0) (fr 9)) ; snb pcl.0 | (pcl&1)<<12 -) - -(dnmi skipb "Skip always" - (SKIPA) - "skip" - (emit sb (bitno 0) (fr 9)) ; sb pcl.0 | (pcl&1)<<12 -) - diff --git a/binutils-2.24/cpu/ip2k.opc b/binutils-2.24/cpu/ip2k.opc deleted file mode 100644 index 512c3f3a..00000000 --- a/binutils-2.24/cpu/ip2k.opc +++ /dev/null @@ -1,633 +0,0 @@ -/* IP2K opcode support. -*- C -*- - Copyright 2002, 2005, 2011 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* Check applicability of instructions against machines. */ -#define CGEN_VALIDATE_INSN_SUPPORTED - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Override disassembly hashing - there are variable bits in the top - byte of these instructions. */ -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf, value) \ - (((* (unsigned char*) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) - -#define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(insn) ip2k_asm_hash (insn) - -extern unsigned int ip2k_asm_hash (const char *); -extern int ip2k_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); - -/* -- opc.c */ - -#include "safe-ctype.h" - -/* A better hash function for instruction mnemonics. */ -unsigned int -ip2k_asm_hash (const char* insn) -{ - unsigned int hash; - const char* m = insn; - - for (hash = 0; *m && ! ISSPACE (*m); m++) - hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); - - /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ - - return hash % CGEN_ASM_HASH_SIZE; -} - - -/* Special check to ensure that instruction exists for given machine. */ - -int -ip2k_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ - int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - - /* No mach attribute? Assume it's supported for all machs. */ - if (machs == 0) - return 1; - - return (machs & cd->machs) != 0; -} - - -/* -- asm.c */ - -static const char * -parse_fr (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - const char *old_strp; - char *afteroffset; - enum cgen_parse_operand_result result_type; - bfd_vma value; - extern CGEN_KEYWORD ip2k_cgen_opval_register_names; - bfd_vma tempvalue; - - old_strp = *strp; - afteroffset = NULL; - - /* Check here to see if you're about to try parsing a w as the first arg - and return an error if you are. */ - if ((strncmp (*strp, "w", 1) == 0) || (strncmp (*strp, "W", 1) == 0)) - { - (*strp)++; - - if ((strncmp (*strp, ",", 1) == 0) || ISSPACE (**strp)) - { - /* We've been passed a w. Return with an error message so that - cgen will try the next parsing option. */ - errmsg = _("W keyword invalid in FR operand slot."); - return errmsg; - } - *strp = old_strp; - } - - /* Attempt parse as register keyword. */ - errmsg = cgen_parse_keyword (cd, strp, & ip2k_cgen_opval_register_names, - (long *) valuep); - if (*strp != NULL - && errmsg == NULL) - return errmsg; - - /* Attempt to parse for "(IP)". */ - afteroffset = strstr (*strp, "(IP)"); - - if (afteroffset == NULL) - /* Make sure it's not in lower case. */ - afteroffset = strstr (*strp, "(ip)"); - - if (afteroffset != NULL) - { - if (afteroffset != *strp) - { - /* Invalid offset present. */ - errmsg = _("offset(IP) is not a valid form"); - return errmsg; - } - else - { - *strp += 4; - *valuep = 0; - errmsg = NULL; - return errmsg; - } - } - - /* Attempt to parse for DP. ex: mov w, offset(DP) - mov offset(DP),w */ - - /* Try parsing it as an address and see what comes back. */ - afteroffset = strstr (*strp, "(DP)"); - - if (afteroffset == NULL) - /* Maybe it's in lower case. */ - afteroffset = strstr (*strp, "(dp)"); - - if (afteroffset != NULL) - { - if (afteroffset == *strp) - { - /* No offset present. Use 0 by default. */ - tempvalue = 0; - errmsg = NULL; - } - else - errmsg = cgen_parse_address (cd, strp, opindex, - BFD_RELOC_IP2K_FR_OFFSET, - & result_type, & tempvalue); - - if (errmsg == NULL) - { - if (tempvalue <= 127) - { - /* Value is ok. Fix up the first 2 bits and return. */ - *valuep = 0x0100 | tempvalue; - *strp += 4; /* Skip over the (DP) in *strp. */ - return errmsg; - } - else - { - /* Found something there in front of (DP) but it's out - of range. */ - errmsg = _("(DP) offset out of range."); - return errmsg; - } - } - } - - - /* Attempt to parse for SP. ex: mov w, offset(SP) - mov offset(SP), w. */ - afteroffset = strstr (*strp, "(SP)"); - - if (afteroffset == NULL) - /* Maybe it's in lower case. */ - afteroffset = strstr (*strp, "(sp)"); - - if (afteroffset != NULL) - { - if (afteroffset == *strp) - { - /* No offset present. Use 0 by default. */ - tempvalue = 0; - errmsg = NULL; - } - else - errmsg = cgen_parse_address (cd, strp, opindex, - BFD_RELOC_IP2K_FR_OFFSET, - & result_type, & tempvalue); - - if (errmsg == NULL) - { - if (tempvalue <= 127) - { - /* Value is ok. Fix up the first 2 bits and return. */ - *valuep = 0x0180 | tempvalue; - *strp += 4; /* Skip over the (SP) in *strp. */ - return errmsg; - } - else - { - /* Found something there in front of (SP) but it's out - of range. */ - errmsg = _("(SP) offset out of range."); - return errmsg; - } - } - } - - /* Attempt to parse as an address. */ - *strp = old_strp; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IP2K_FR9, - & result_type, & value); - if (errmsg == NULL) - { - *valuep = value; - - /* If a parenthesis is found, warn about invalid form. */ - if (**strp == '(') - errmsg = _("illegal use of parentheses"); - - /* If a numeric value is specified, ensure that it is between - 1 and 255. */ - else if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - if (value < 0x1 || value > 0xff) - errmsg = _("operand out of range (not between 1 and 255)"); - } - } - return errmsg; -} - -static const char * -parse_addr16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16H) - code = BFD_RELOC_IP2K_HI8DATA; - else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16L) - code = BFD_RELOC_IP2K_LO8DATA; - else - { - /* Something is very wrong. opindex has to be one of the above. */ - errmsg = _("parse_addr16: invalid opindex."); - return errmsg; - } - - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if (errmsg == NULL) - { - /* We either have a relocation or a number now. */ - if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - /* We got a number back. */ - if (code == BFD_RELOC_IP2K_HI8DATA) - value >>= 8; - else - /* code = BFD_RELOC_IP2K_LOW8DATA. */ - value &= 0x00FF; - } - *valuep = value; - } - - return errmsg; -} - -static const char * -parse_addr16_cjp (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) - code = BFD_RELOC_IP2K_ADDR16CJP; - else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) - code = BFD_RELOC_IP2K_PAGE3; - - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if (errmsg == NULL) - { - if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - if ((value & 0x1) == 0) /* If the address is even .... */ - { - if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16CJP) - *valuep = (value >> 1) & 0x1FFF; /* Should mask be 1FFF? */ - else if (opindex == (CGEN_OPERAND_TYPE) IP2K_OPERAND_ADDR16P) - *valuep = (value >> 14) & 0x7; - } - else - errmsg = _("Byte address required. - must be even."); - } - else if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) - { - /* This will happen for things like (s2-s1) where s2 and s1 - are labels. */ - *valuep = value; - } - else - errmsg = _("cgen_parse_address returned a symbol. Literal required."); - } - return errmsg; -} - -static const char * -parse_lit8 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - /* Parse %OP relocating operators. */ - if (strncmp (*strp, "%bank", 5) == 0) - { - *strp += 5; - code = BFD_RELOC_IP2K_BANK; - } - else if (strncmp (*strp, "%lo8data", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_LO8DATA; - } - else if (strncmp (*strp, "%hi8data", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_HI8DATA; - } - else if (strncmp (*strp, "%ex8data", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_EX8DATA; - } - else if (strncmp (*strp, "%lo8insn", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_LO8INSN; - } - else if (strncmp (*strp, "%hi8insn", 8) == 0) - { - *strp += 8; - code = BFD_RELOC_IP2K_HI8INSN; - } - - /* Parse %op operand. */ - if (code != BFD_RELOC_NONE) - { - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if ((errmsg == NULL) && - (result_type != CGEN_PARSE_OPERAND_RESULT_QUEUED)) - errmsg = _("percent-operator operand is not a symbol"); - - *valuep = value; - } - /* Parse as a number. */ - else - { - errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); - - /* Truncate to eight bits to accept both signed and unsigned input. */ - if (errmsg == NULL) - *valuep &= 0xFF; - } - - return errmsg; -} - -static const char * -parse_bit3 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - char mode = 0; - long count = 0; - unsigned long value; - - if (strncmp (*strp, "%bit", 4) == 0) - { - *strp += 4; - mode = 1; - } - else if (strncmp (*strp, "%msbbit", 7) == 0) - { - *strp += 7; - mode = 1; - } - else if (strncmp (*strp, "%lsbbit", 7) == 0) - { - *strp += 7; - mode = 2; - } - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - if (errmsg) - return errmsg; - - if (mode) - { - value = * valuep; - if (value == 0) - { - errmsg = _("Attempt to find bit index of 0"); - return errmsg; - } - - if (mode == 1) - { - count = 31; - while ((value & 0x80000000) == 0) - { - count--; - value <<= 1; - } - } - else if (mode == 2) - { - count = 0; - while ((value & 0x00000001) == 0) - { - count++; - value >>= 1; - } - } - - *valuep = count; - } - - return errmsg; -} - -/* -- dis.c */ - -static void -print_fr (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - const CGEN_KEYWORD_ENTRY *ke; - extern CGEN_KEYWORD ip2k_cgen_opval_register_names; - long offsettest; - long offsetvalue; - - if (value == 0) /* This is (IP). */ - { - (*info->fprintf_func) (info->stream, "%s", "(IP)"); - return; - } - - offsettest = value >> 7; - offsetvalue = value & 0x7F; - - /* Check to see if first two bits are 10 -> (DP). */ - if (offsettest == 2) - { - if (offsetvalue == 0) - (*info->fprintf_func) (info->stream, "%s","(DP)"); - else - (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue, "(DP)"); - return; - } - - /* Check to see if first two bits are 11 -> (SP). */ - if (offsettest == 3) - { - if (offsetvalue == 0) - (*info->fprintf_func) (info->stream, "%s", "(SP)"); - else - (*info->fprintf_func) (info->stream, "$%lx%s", offsetvalue,"(SP)"); - return; - } - - /* Attempt to print as a register keyword. */ - ke = cgen_keyword_lookup_value (& ip2k_cgen_opval_register_names, value); - - if (ke != NULL) - (*info->fprintf_func) (info->stream, "%s", ke->name); - else - /* Print as an address literal. */ - (*info->fprintf_func) (info->stream, "$%02lx", value); -} - -static void -print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$%lx", value); -} - -static void -print_dollarhex8 (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$%02lx", value); -} - -static void -print_dollarhex_addr16h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - /* This is a loadh instruction. Shift the value to the left - by 8 bits so that disassembled code will reassemble properly. */ - value = ((value << 8) & 0xFF00); - - (*info->fprintf_func) (info->stream, "$%04lx", value); -} - -static void -print_dollarhex_addr16l (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$%04lx", value); -} - -static void -print_dollarhex_p (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - value = ((value << 14) & 0x1C000); - ;value = (value & 0x1FFFF); - (*info->fprintf_func) (info->stream, "$%05lx", value); -} - -static void -print_dollarhex_cj (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - value = ((value << 1) & 0x1FFFF); - (*info->fprintf_func) (info->stream, "$%05lx", value); -} - -static void -print_decimal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "%ld", value); -} - - - -/* -- */ - diff --git a/binutils-2.24/cpu/iq10.cpu b/binutils-2.24/cpu/iq10.cpu deleted file mode 100644 index 252cf534..00000000 --- a/binutils-2.24/cpu/iq10.cpu +++ /dev/null @@ -1,1112 +0,0 @@ -; IQ10-only CPU description. -*- Scheme -*- -; -; Copyright 2001, 2002, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Vitesse. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - - -; Instructions. - -(dni andoui-q10 "iq10 and upper ones immediate" (MACH10 USES-RS USES-RT) - "andoui $rt,$rs,$hi16" - (+ OP10_ANDOUI rs rt hi16) - (set rt (and rs (or (sll hi16 16) #xFFFF))) - ()) - -(dni andoui2-q10 "iq10 and upper ones immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT) - "andoui ${rt-rs},$hi16" - (+ OP10_ANDOUI rt-rs hi16) - (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF))) - ()) - -(dni orui-q10 "or upper immediate" (MACH10 USES-RS USES-RT) - "orui $rt,$rs,$hi16" - (+ OP10_ORUI rs rt hi16) - (set rt (or rs (sll hi16 16))) - ()) - -(dni orui2-q10 "or upper immediate" (ALIAS NO-DIS MACH10 USES-RS USES-RT) - "orui ${rt-rs},$hi16" - (+ OP10_ORUI rt-rs hi16) - (set rt-rs (or rt-rs (sll hi16 16))) - ()) - -(dni mrgbq10 "merge bytes" (MACH10 USES-RD USES-RS USES-RT) - "mrgb $rd,$rs,$rt,$maskq10" - (+ OP_SPECIAL rs rt rd maskq10 FUNC_MRGB) - (sequence ((SI temp)) - (if (bitclear? mask 0) - (set temp (and rs #xFF)) - (set temp (and rt #xFF))) - (if (bitclear? mask 1) - (set temp (or temp (and rs #xFF00))) - (set temp (or temp (and rt #xFF00)))) - (if (bitclear? mask 2) - (set temp (or temp (and rs #xFF0000))) - (set temp (or temp (and rt #xFF0000)))) - (if (bitclear? mask 3) - (set temp (or temp (and rs #xFF000000))) - (set temp (or temp (and rt #xFF000000)))) - (set rd temp)) - ()) - -(dni mrgbq102 "merge bytes" (ALIAS NO-DIS MACH10 USES-RD USES-RS USES-RT) - "mrgb ${rd-rs},$rt,$maskq10" - (+ OP_SPECIAL rt rd-rs maskq10 FUNC_MRGB) - (sequence ((SI temp)) - (if (bitclear? mask 0) - (set temp (and rd-rs #xFF)) - (set temp (and rt #xFF))) - (if (bitclear? mask 1) - (set temp (or temp (and rd-rs #xFF00))) - (set temp (or temp (and rt #xFF00)))) - (if (bitclear? mask 2) - (set temp (or temp (and rd-rs #xFF0000))) - (set temp (or temp (and rt #xFF0000)))) - (if (bitclear? mask 3) - (set temp (or temp (and rd-rs #xFF000000))) - (set temp (or temp (and rt #xFF000000)))) - (set rd-rs temp)) - ()) - -; In the future, we'll want the j & jal to use the 21 bit target, with -; the upper five bits shifted up. For now, give 'em the 16 bit target. - -(dni jq10 "jump" (MACH10) - "j $jmptarg" - (+ OP_J (f-rs 0) (f-rt 0) jmptarg) -; "j $jmptargq10" -; (+ OP_J upper-5-jmptargq10 (f-rt 0) lower-16-jmptargq10) - (delay 1 (set pc jmptarg)) - ()) - -(dni jalq10 "jump and link" (MACH10 USES-RT) - "jal $rt,$jmptarg" - (+ OP_JAL (f-rs 0) rt jmptarg) -; "jal $rt,$jmptargq10" -; (+ OP_JAL upper-5-jmptargq10 rt lower-16-jmptargq10) - (delay 1 - (sequence () - (set rt (add pc 8)) - (set pc jmptarg))) - ()) - -(dni jalq10-2 "jump and link, implied r31" (MACH10 USES-RT) - "jal $jmptarg" - (+ OP_JAL (f-rs 0) (f-rt 31) jmptarg) - (delay 1 - (sequence () - (set rt (add pc 8)) - (set pc jmptarg))) - ()) - -; Branch instructions. - -(dni bbil "branch bit immediate likely" (MACH10 USES-RS) - "bbil $rs($bitnum),$offset" - (+ OP10_BBIL rs bitnum offset) - (if (bitset? rs bitnum) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bbinl "branch bit immediate negated likely" (MACH10 USES-RS) - "bbinl $rs($bitnum),$offset" - (+ OP10_BBINL rs bitnum offset) - (if (bitclear? rs bitnum) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bbvl "branch bit variable likely" (MACH10 USES-RS USES-RT) - "bbvl $rs,$rt,$offset" - (+ OP10_BBVL rs rt offset) - (if (bitset? rs (and rt #x1F)) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bbvnl "branch bit variable negated likely" (MACH10 USES-RS USES-RT) - "bbvnl $rs,$rt,$offset" - (+ OP10_BBVNL rs rt offset) - (if (bitclear? rs (and rt #x1F)) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bgtzal "branch if greater than zero and link" (MACH10 USES-RS USES-R31) - "bgtzal $rs,$offset" - (+ OP_REGIMM rs FUNC_BGTZAL offset) - (if (gt rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset)))) - ()) - -(dni bgtzall - "branch if greater than zero and link likely" (MACH10 USES-RS USES-R31) - "bgtzall $rs,$offset" - (+ OP_REGIMM rs FUNC_BGTZALL offset) - (if (gt rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset))) - (skip 1)) - ()) - -(dni blezal "branch if less than or equal to zero and link" (MACH10 USES-RS USES-R31) - "blezal $rs,$offset" - (+ OP_REGIMM rs FUNC_BLEZAL offset) - (if (le rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset)))) - ()) - -(dni blezall - "branch if less than or equal to zero and link likely" (MACH10 USES-RS USES-R31) - "blezall $rs,$offset" - (+ OP_REGIMM rs FUNC_BLEZALL offset) - (if (le rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset))) - (skip 1)) - ()) - -(dni bgtz-q10 "branch if greater than zero" (MACH10 USES-RS) - "bgtz $rs,$offset" - (+ OP_REGIMM rs FUNC_BGTZ offset) - (if (gt rs 0) - (delay 1 (set pc offset))) - ()) - -(dni bgtzl-q10 "branch if greater than zero likely" (MACH10 USES-RS) - "bgtzl $rs,$offset" - (+ OP_REGIMM rs FUNC_BGTZL offset) - (if (gt rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - - -(dni blez-q10 "branch if less than or equal to zero" (MACH10 USES-RS) - "blez $rs,$offset" - (+ OP_REGIMM rs FUNC_BLEZ offset) - (if (le rs 0) - (delay 1 (set pc offset))) - ()) - -(dni blezl-q10 "branch if less than or equal to zero likely" (MACH10 USES-RS) - "blezl $rs,$offset" - (+ OP_REGIMM rs FUNC_BLEZL offset) - (if (le rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bmb-q10 "branch if matching byte-lane" (MACH10 USES-RS USES-RT) - "bmb $rs,$rt,$offset" - (+ OP10_BMB rs rt offset) - (sequence ((BI branch?)) - (set branch? 0) - (if (eq (and rs #xFF) (and rt #xFF)) - (set branch? 1)) - (if (eq (and rs #xFF00) (and rt #xFF00)) - (set branch? 1)) - (if (eq (and rs #xFF0000) (and rt #xFF0000)) - (set branch? 1)) - (if (eq (and rs #xFF000000) (and rt #xFF000000)) - (set branch? 1)) - (if branch? - (delay 1 (set pc offset)))) - ()) - -(dni bmbl "branch if matching byte-lane likely" (MACH10 USES-RS USES-RT) - "bmbl $rs,$rt,$offset" - (+ OP10_BMBL rs rt offset) - (sequence ((BI branch?)) - (set branch? 0) - (if (eq (and rs #xFF) (and rt #xFF)) - (set branch? 1)) - (if (eq (and rs #xFF00) (and rt #xFF00)) - (set branch? 1)) - (if (eq (and rs #xFF0000) (and rt #xFF0000)) - (set branch? 1)) - (if (eq (and rs #xFF000000) (and rt #xFF000000)) - (set branch? 1)) - (if branch? - (delay 1 (set pc offset)) - (skip 1))) - ()) - -(dni bri "branch if register invalid" (MACH10 USES-RS) - "bri $rs,$offset" - (+ OP_REGIMM rs FUNC_BRI offset) - (if (gt rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni brv "branch if register invalid" (MACH10 USES-RS) - "brv $rs,$offset" - (+ OP_REGIMM rs FUNC_BRV offset) - (if (gt rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -; debug instructions - -(dni bctx "branch if the current context == instruction[21]" (MACH10 USES-RS) - "bctx $rs,$offset" - (+ OP_REGIMM rs FUNC_BCTX offset) - (delay 1 (set pc offset)) - ()) - -(dni yield "unconditional yield to the other context" (MACH10) - "yield" - (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC10_YIELD) - (unimp yield) - ()) - -; Special instructions. - -(dni crc32 "CRC, 32 bit input" (MACH10 USES-RD USES-RS USES-RT) - "crc32 $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32) - (unimp crc32) - ()) - -(dni crc32b "CRC, 8 bit input" (MACH10 USES-RD USES-RS USES-RT) - "crc32b $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_CRC32B) - (unimp crc32b) - ()) - -(dni cnt1s "Count ones" (MACH10 USES-RD USES-RS) - "cnt1s $rd,$rs" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC10_CNT1S) - (unimp crcp) - ()) - - -; Special Instructions - -(dni avail "Mark Header Buffer Available" (MACH10 USES-RD) - "avail $rd" - (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_AVAIL) - (unimp avail) - ()) - -(dni free "Mark Header Buffer Free" (MACH10 USES-RS USES-RD) - "free $rd,$rs" - (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_FREE) - (unimp free) - ()) - -(dni tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD) - "tstod $rd,$rs" - (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_TSTOD) - (unimp tstod) - ()) - -(dni cmphdr "Get a Complete Header" (MACH10 USES-RD) - "cmphdr $rd" - (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_CMPHDR) - (unimp cmphdr) - ()) - -(dni mcid "Allocate a Multicast ID" (MACH10 USES-RD USES-RT) - "mcid $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_MCID) - (unimp mcid) - ()) - -(dni dba "Allocate a Data Buffer Pointer" (MACH10 USES-RD) - "dba $rd" - (+ OP_COP3 (f-rs 0) (f-rt 0) rd (f-shamt 0) FUNC10_DBA) - (unimp dba) - ()) - -(dni dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RS USES-RT USES-RD) - "dbd $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_DBD) - (unimp dbd) - ()) - -(dni dpwt "DSTN_PORT Write" (MACH10 USES-RS USES-RD) - "dpwt $rd,$rs" - (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_DPWT) - (unimp dpwt) - ()) - -; Architectural and coprocessor instructions. - -(dni chkhdrq10 "" (MACH10 USES-RS USES-RD) - "chkhdr $rd,$rs" - (+ OP_COP3 rs (f-rt 0) rd (f-shamt 0) FUNC10_CHKHDR) - (unimp chkhdr) - ()) - -; Coprocessor DMA Instructions (IQ10) - -(dni rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD) - "rba $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBA) - (unimp rba) - ()) - -(dni rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD) - "rbal $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAL) - (unimp rbal) - ()) - -(dni rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD) - "rbar $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_RBAR) - (unimp rbar) - ()) - -(dni wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD) - "wba $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBA) - (unimp wba) - ()) - -(dni wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD) - "wbau $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAU) - (unimp wbau) - ()) - -(dni wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD) - "wbac $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_WBAC) - (unimp wbac) - ()) - -(dni rbi "Read Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT) - "rbi $rd,$rs,$rt,$bytecount" - (+ OP_COP3 rs rt rd FUNC10_RBI bytecount) - (unimp rbi) - ()) - -(dni rbil "Read Bytes Immediate and Lock" (MACH10 USES-RD USES-RS USES-RT) - "rbil $rd,$rs,$rt,$bytecount" - (+ OP_COP3 rs rt rd FUNC10_RBIL bytecount) - (unimp rbil) - ()) - -(dni rbir "Read Bytes Immediate and Release" (MACH10 USES-RD USES-RS USES-RT) - "rbir $rd,$rs,$rt,$bytecount" - (+ OP_COP3 rs rt rd FUNC10_RBIR bytecount) - (unimp rbir) - ()) - -(dni wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT) - "wbi $rd,$rs,$rt,$bytecount" - (+ OP_COP3 rs rt rd FUNC10_WBI bytecount) - (unimp wbi) - ()) - -(dni wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT) - "wbic $rd,$rs,$rt,$bytecount" - (+ OP_COP3 rs rt rd FUNC10_WBIC bytecount) - (unimp wbic) - ()) - -(dni wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT) - "wbiu $rd,$rs,$rt,$bytecount" - (+ OP_COP3 rs rt rd FUNC10_WBIU bytecount) - (unimp wbiu) - ()) - -(dni pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT) - "pkrli $rd,$rs,$rt,$bytecount" - (+ OP_COP2 rs rt rd FUNC10_PKRLI bytecount) - (unimp pkrli) - ()) - -(dni pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT) - "pkrlih $rd,$rs,$rt,$bytecount" - (+ OP_COP2 rs rt rd FUNC10_PKRLIH bytecount) - (unimp pkrlih) - ()) - -(dni pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT) - "pkrliu $rd,$rs,$rt,$bytecount" - (+ OP_COP2 rs rt rd FUNC10_PKRLIU bytecount) - (unimp pkrliu) - ()) - -(dni pkrlic "Packet Release Immediate Continue" (MACH10 USES-RD USES-RS USES-RT) - "pkrlic $rd,$rs,$rt,$bytecount" - (+ OP_COP2 rs rt rd FUNC10_PKRLIC bytecount) - (unimp pkrlic) - ()) - -(dni pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD) - "pkrla $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLA) - (unimp pkrla) - ()) - -(dni pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD) - "pkrlau $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAU) - (unimp pkrlau) - ()) - -(dni pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD) - "pkrlah $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAH) - (unimp pkrlah) - ()) - -(dni pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD) - "pkrlac $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_PKRLAC) - (unimp pkrlac) - ()) - -; Main Memory Access Instructions - -(dni lock "lock memory" (MACH10 USES-RD USES-RT) - "lock $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_LOCK) - (unimp lock) - ()) - -(dni unlk "unlock memory" (MACH10 USES-RT USES-RD) - "unlk $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_UNLK) - (unimp unlk) - ()) - -(dni swrd "Single Word Read" (MACH10 USES-RT USES-RD) - "swrd $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRD) - (unimp swrd) - ()) - -(dni swrdl "Single Word Read and Lock" (MACH10 USES-RT USES-RD) - "swrdl $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_SWRDL) - (unimp swrdl) - ()) - -(dni swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD) - "swwr $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWR) - (unimp swwr) - ()) - -(dni swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD) - "swwru $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 0) FUNC10_SWWRU) - (unimp swwru) - ()) - -(dni dwrd "Double Word Read" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "dwrd $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRD) - (unimp dwrd) - ()) - -(dni dwrdl "Double Word Read and Lock" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "dwrdl $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_DWRDL) - (unimp dwrdl) - ()) - -; CAM access instructions (IQ10) - -(dni cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD) - "cam36 $rd,$rt,${cam-z},${cam-y}" - (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM36 cam-z cam-y) - (unimp cam36) - ()) - -(dni cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD) - "cam72 $rd,$rt,${cam-y},${cam-z}" - (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM72 cam-z cam-y) - (unimp cam72) - ()) - -(dni cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD) - "cam144 $rd,$rt,${cam-y},${cam-z}" - (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM144 cam-z cam-y) - (unimp cam144) - ()) - -(dni cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD) - "cam288 $rd,$rt,${cam-y},${cam-z}" - (+ OP_COP3 (f-rs 0) rt rd FUNC10_CAM288 cam-z cam-y) - (unimp cam288) - ()) - -; Counter manager instructions (IQ10) - -(dni cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD) - "cm32and $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32AND) - (unimp cm32and) - ()) - -(dni cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD) - "cm32andn $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32ANDN) - (unimp cm32andn) - ()) - -(dni cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD) - "cm32or $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32OR) - (unimp cm32or) - ()) - -(dni cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD) - "cm32ra $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RA) - (unimp cm32ra) - ()) - -(dni cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD) - "cm32rd $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RD) - (unimp cm32rd) - ()) - -(dni cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD) - "cm32ri $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32RI) - (unimp cm32ri) - ()) - -(dni cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD) - "cm32rs $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-shamt 2) FUNC10_CM32RS) - (unimp cm32rs) - ()) - -(dni cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD) - "cm32sa $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SA) - (unimp cm32sa) - ()) - -(dni cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD) - "cm32sd $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SD) - (unimp cm32sd) - ()) - -(dni cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD) - "cm32si $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SI) - (unimp cm32si) - ()) - -(dni cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD) - "cm32ss $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32SS) - (unimp cm32ss) - ()) - -(dni cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD) - "cm32xor $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM32XOR) - (unimp cm32xor) - ()) - -(dni cm64clr "Counter Manager Clear" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "cm64clr $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64CLR) - (unimp cm64clr) - ()) - -(dni cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm64ra $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RA) - (unimp cm64ra) - ()) - -(dni cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "cm64rd $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RD) - (unimp cm64rd) - ()) - -(dni cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "cm64ri $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RI) - (unimp cm64ri) - ()) - -(dni cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm64ria2 $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RIA2) - (unimp cm64ria2) - ()) - -(dni cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm64rs $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64RS) - (unimp cm64rs) - ()) - -(dni cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm64sa $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SA) - (unimp cm64sa) - ()) - -(dni cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "cm64sd $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SD) - (unimp cm64sd) - ()) - -(dni cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 EVEN-REG-NUM USES-RT USES-RD) - "cm64si $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SI) - (unimp cm64si) - ()) - -(dni cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm64sia2 $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SIA2) - (unimp cm64sia2) - ()) - -(dni cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm64ss $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM64SS) - (unimp cm64ss) - ()) - -(dni cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm128ria2 $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA2) - (unimp cm128ria2) - ()) - -(dni cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm128ria3 $rd,$rs,$rt,${cm-3z}" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA3 cm-3z) - (unimp cm128ria3) - ()) - -(dni cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD) - "cm128ria4 $rd,$rs,$rt,${cm-4z}" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128RIA4 cm-4z) - (unimp cm128ria4) - ()) - -(dni cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm128sia2 $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA2) - (unimp cm128sia2) - ()) - -(dni cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 EVEN-REG-NUM USES-RS USES-RT USES-RD) - "cm128sia3 $rd,$rs,$rt,${cm-3z}" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA3 cm-3z) - (unimp cm128sia3) - ()) - -(dni cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD) - "cm128sia4 $rd,$rs,$rt,${cm-4z}" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128SIA4 cm-4z) - (unimp cm128sia4) - ()) - -(dni cm128vsa "Counter Manager Continuous State Dual Leaky Token Bucket Policing" (MACH10 USES-RS USES-RT USES-RD) - "cm128vsa $rd,$rs,$rt" - (+ OP_COP3 rs rt rd (f-cp-op 0) (f-cp-grp 2) FUNC10_CM128VSA) - (unimp cm128vsa) - ()) - -; Coprocessor Data Movement Instructions - -; Note that we don't set the USES-RD or USES-RT attributes for many of the following -; instructions, as it's the COP register that's being specified. - -; ??? Is YIELD-INSN the right attribute for IQ10? The IQ2000 used the attribute to warn about -; yielding instructions in a delay slot, but that's not relevant in IQ10. What *is* relevant -; (and unique to IQ10) is instructions that yield if the destination register is accessed -; before the value is there, causing a yield. - -(dni cfc "copy from coprocessor control register" (MACH10 LOAD-DELAY USES-RD YIELD-INSN) - "cfc $rd,$rt" - (+ OP_COP3 (f-rs 0) rt rd (f-shamt 0) FUNC10_CFC) - (unimp cfc) - ()) - -(dni ctc "copy to coprocessor control register" (MACH10 USES-RS) - "ctc $rs,$rt" - (+ OP_COP3 rs rt (f-rd 0) (f-shamt 0) FUNC10_CTC) - (unimp ctc) - ()) - -; Macros - -(dnmi m-avail "Mark Header Buffer Available" (MACH10 NO-DIS) - "avail" - (emit avail (f-rd 0)) -) - -(dnmi m-cam36 "CAM Access in 36-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) - "cam36 $rd,$rt,${cam-z}" - (emit cam36 rd rt cam-z (f-cam-y 0)) -) - -(dnmi m-cam72 "CAM Access in 72-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) - "cam72 $rd,$rt,${cam-z}" - (emit cam72 rd rt cam-z (f-cam-y 0)) -) - -(dnmi m-cam144 "CAM Access in 144-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) - "cam144 $rd,$rt,${cam-z}" - (emit cam144 rd rt cam-z (f-cam-y 0)) -) - -(dnmi m-cam288 "CAM Access in 288-bit Mode" (MACH10 USES-RT USES-RD NO-DIS) - "cam288 $rd,$rt,${cam-z}" - (emit cam288 rd rt cam-z (f-cam-y 0)) -) - -(dnmi m-cm32read "Counter Manager 32-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS) - "cm32read $rd,$rt" - (emit cm32ra rd (f-rs 0) rt) -) - -(dnmi m-cm64read "Counter Manager 64-bit Rolling Add R0" (MACH10 USES-RT USES-RD NO-DIS) - "cm64read $rd,$rt" - (emit cm64ra rd (f-rs 0) rt) -) - -(dnmi m-cm32mlog "Counter Manager 32-bit or R0" (MACH10 USES-RS USES-RT NO-DIS) - "cm32mlog $rs,$rt" - (emit cm32or (f-rd 0) rs rt) -) - -(dnmi m-cm32and "Counter Manager And" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32and $rs,$rt" - (emit cm32and (f-rd 0) rs rt) -) - -(dnmi m-cm32andn "Counter Manager And With Inverse" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32andn $rs,$rt" - (emit cm32andn (f-rd 0) rs rt) -) - -(dnmi m-cm32or "Counter Manager Or" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32or $rs,$rt" - (emit cm32or (f-rd 0) rs rt) -) - -(dnmi m-cm32ra "Counter Manager 32-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32ra $rs,$rt" - (emit cm32ra (f-rd 0) rs rt) -) - -(dnmi m-cm32rd "Counter Manager 32-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS) - "cm32rd $rt" - (emit cm32rd (f-rd 0) rt) -) - -(dnmi m-cm32ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS) - "cm32ri $rt" - (emit cm32ri (f-rd 0) rt) -) - -(dnmi m-cm32rs "Counter Manager 32-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32rs $rs,$rt" - (emit cm32rs (f-rd 0) rs rt) -) - -(dnmi m-cm32sa "Counter Manager 32-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32sa $rs,$rt" - (emit cm32sa (f-rd 0) rs rt) -) - -(dnmi m-cm32sd "Counter Manager 32-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS) - "cm32sd $rt" - (emit cm32sd (f-rd 0) rt) -) - -(dnmi m-cm32si "Counter Manager 32-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS) - "cm32si $rt" - (emit cm32si (f-rd 0) rt) -) - -(dnmi m-cm32ss "Counter Manager 32-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32ss $rs,$rt" - (emit cm32ss (f-rd 0) rs rt) -) - -(dnmi m-cm32xor "Counter Manager Xor" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm32xor $rs,$rt" - (emit cm32xor (f-rd 0) rs rt) -) - -(dnmi m-cm64clr "Counter Manager Clear" (MACH10 USES-RT USES-RD NO-DIS) - "cm64clr $rt" - (emit cm64clr (f-rd 0) rt) -) - -(dnmi m-cm64ra "Counter Manager 64-bit Rolling Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm64ra $rs,$rt" - (emit cm64ra (f-rd 0) rs rt) -) - -(dnmi m-cm64rd "Counter Manager 64-bit Rolling Decrement" (MACH10 USES-RT USES-RD NO-DIS) - "cm64rd $rt" - (emit cm64rd (f-rd 0) rt) -) - -(dnmi m-cm64ri "Counter Manager 32-bit Rolling Increment" (MACH10 USES-RT USES-RD NO-DIS) - "cm64ri $rt" - (emit cm64ri (f-rd 0) rt) -) - -(dnmi m-cm64ria2 "Counter Manager 32/32 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm64ria2 $rs,$rt" - (emit cm64ria2 (f-rd 0) rs rt) -) - -(dnmi m-cm64rs "Counter Manager 64-bit Rolling Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm64rs $rs,$rt" - (emit cm64rs (f-rd 0) rs rt) -) - -(dnmi m-cm64sa "Counter Manager 64-bit Saturating Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm64sa $rs,$rt" - (emit cm64sa (f-rd 0) rs rt) -) - -(dnmi m-cm64sd "Counter Manager 64-bit Saturating Decrement" (MACH10 USES-RT USES-RD NO-DIS) - "cm64sd $rt" - (emit cm64sd (f-rd 0) rt) -) - -(dnmi m-cm64si "Counter Manager 64-bit Saturating Increment" (MACH10 USES-RT USES-RD NO-DIS) - "cm64si $rt" - (emit cm64si (f-rd 0) rt) -) - -(dnmi m-cm64sia2 "Counter Manager 32/32 Saturating Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm64sia2 $rs,$rt" - (emit cm64sia2 (f-rd 0) rs rt) -) - -(dnmi m-cm64ss "Counter Manager 64-bit Saturating Subtract" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm64ss $rs,$rt" - (emit cm64ss (f-rd 0) rs rt) -) - -(dnmi m-cm128ria2 "Counter Manager 128-bit 64/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm128ria2 $rs,$rt" - (emit cm128ria2 (f-rd 0) rs rt) -) - -(dnmi m-cm128ria3 "Counter Manager 128-bit 32/32/64 Rolling Increment/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm128ria3 $rs,$rt,${cm-3z}" - (emit cm128ria3 (f-rd 0) rs rt cm-3z) -) - -(dnmi m-cm128ria4 "Counter Manager 128-bit 32/32/32/32 Rolling Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm128ria4 $rs,$rt,${cm-4z}" - (emit cm128ria4 (f-rd 0) rs rt cm-4z) -) - -(dnmi m-cm128sia2 "Counter Manager 128-bit 64/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm128sia2 $rs,$rt" - (emit cm128sia2 (f-rd 0) rs rt) -) - -(dnmi m-cm128sia3 "Counter Manager 128-bit 32/32/64 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm128sia3 $rs,$rt,${cm-3z}" - (emit cm128sia3 (f-rd 0) rs rt cm-3z) -) - -(dnmi m-cm128sia4 "Counter Manager 128-bit 32/32/32/32 Saturating Inc/Add" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "cm128sia4 $rs,$rt,${cm-4z}" - (emit cm128sia4 (f-rd 0) rs rt cm-4z) -) - -(dnmi m-cmphdr "Get a Complete Header" (MACH10 NO-DIS) - "cmphdr" - (emit cmphdr (f-rd 0)) -) - -(dnmi m-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RD USES-RT NO-DIS) - "dbd $rd,$rt" - (emit dbd rd (f-rs 0) rt) -) - -(dnmi m2-dbd "Deallocate a Data Buffer Pointer" (MACH10 USES-RT NO-DIS) - "dbd $rt" - (emit dbd (f-rd 0) (f-rs 0) rt) -) - -(dnmi m-dpwt "DSTN_PORT Write" (MACH10 USES-RS NO-DIS) - "dpwt $rs" - (emit dpwt (f-rd 0) rs) -) - -(dnmi m-free "" (MACH10 USES-RS USES-RD NO-DIS) - "free $rs" - (emit free (f-rd 0) rs) -) - -;(dnmi m-jal "jump and link, implied r31" (MACH10 USES-RT NO-DIS) -; "jal $jmptarg" -; (emit jal (f-rt 31) jmptarg) -;) - -(dnmi m-lock "lock memory" (MACH10 USES-RT NO-DIS) - "lock $rt" - (emit lock (f-rd 0) rt) -) - -(dnmi m-pkrla "Packet Release Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "pkrla $rs,$rt" - (emit pkrla (f-rd 0) rs rt) -) - -(dnmi m-pkrlac "Packet Release Absolute Continue" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "pkrlac $rs,$rt" - (emit pkrlac (f-rd 0) rs rt) -) - -(dnmi m-pkrlah "Packet Release Absolute and Hold" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "pkrlah $rs,$rt" - (emit pkrlah (f-rd 0) rs rt) -) - -(dnmi m-pkrlau "Packet Release Absolute Unconditional" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "pkrlau $rs,$rt" - (emit pkrlau (f-rd 0) rs rt) -) - -(dnmi m-pkrli "Packet Release Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS) - "pkrli $rs,$rt,$bytecount" - (emit pkrli (f-rd 0) rs rt bytecount) -) - -(dnmi m-pkrlic "Packet Release Immediate Continue" (MACH10 USES-RS USES-RT NO-DIS) - "pkrlic $rs,$rt,$bytecount" - (emit pkrlic (f-rd 0) rs rt bytecount) -) - -(dnmi m-pkrlih "Packet Release Immediate and Hold" (MACH10 USES-RD USES-RS USES-RT NO-DIS) - "pkrlih $rs,$rt,$bytecount" - (emit pkrlih (f-rd 0) rs rt bytecount) -) - -(dnmi m-pkrliu "Packet Release Immediate Unconditional" (MACH10 USES-RD USES-RS USES-RT NO-DIS) - "pkrliu $rs,$rt,$bytecount" - (emit pkrliu (f-rd 0) rs rt bytecount) -) - -(dnmi m-rba "Read Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "rba $rs,$rt" - (emit rba (f-rd 0) rs rt) -) - -(dnmi m-rbal "Read Bytes Absolute and Lock" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "rbal $rs,$rt" - (emit rbal (f-rd 0) rs rt) -) - -(dnmi m-rbar "Read Bytes Absolute and Release" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "rbar $rs,$rt" - (emit rbar (f-rd 0) rs rt) -) - -(dnmi m-rbi "Read Bytes Immediate" (MACH10 USES-RS USES-RT NO-DIS) - "rbi $rs,$rt,$bytecount" - (emit rbi (f-rd 0) rs rt bytecount) -) - -(dnmi m-rbil "Read Bytes Immediate and Lock" (MACH10 USES-RS USES-RT NO-DIS) - "rbil $rs,$rt,$bytecount" - (emit rbil (f-rd 0) rs rt bytecount) -) - -(dnmi m-rbir "Read Bytes Immediate and Release" (MACH10 USES-RS USES-RT NO-DIS) - "rbir $rs,$rt,$bytecount" - (emit rbir (f-rd 0) rs rt bytecount) -) - -(dnmi m-swwr "Single Word Write" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "swwr $rs,$rt" - (emit swwr (f-rd 0) rs rt) -) - -(dnmi m-swwru "Single Word Write and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "swwru $rs,$rt" - (emit swwru (f-rd 0) rs rt) -) - -(dnmi m-tstod "Test Header Buffer Order Dependency" (MACH10 USES-RS USES-RD NO-DIS) - "tstod $rs" - (emit tstod (f-rd 0) rs) -) - -(dnmi m-unlk "" (MACH10 USES-RT USES-RD NO-DIS) - "unlk $rt" - (emit unlk (f-rd 0) rt) -) - -(dnmi m-wba "Write Bytes Absolute" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "wba $rs,$rt" - (emit wba (f-rd 0) rs rt) -) - -(dnmi m-wbac "Write Bytes Absolute Cacheable" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "wbac $rs,$rt" - (emit wbac (f-rd 0) rs rt) -) - -(dnmi m-wbau "Write Bytes Absolute and Unlock" (MACH10 USES-RS USES-RT USES-RD NO-DIS) - "wbau $rs,$rt" - (emit wbau (f-rd 0) rs rt) -) - -(dnmi m-wbi "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS) - "wbi $rs,$rt,$bytecount" - (emit wbi (f-rd 0) rs rt bytecount) -) - -(dnmi m-wbic "Write Bytes Immediate Cacheable" (MACH10 USES-RD USES-RS USES-RT NO-DIS) - "wbic $rs,$rt,$bytecount" - (emit wbic (f-rd 0) rs rt bytecount) -) - -(dnmi m-wbiu "Write Bytes Immediate" (MACH10 USES-RD USES-RS USES-RT NO-DIS) - "wbiu $rs,$rt,$bytecount" - (emit wbiu (f-rd 0) rs rt bytecount) -) - diff --git a/binutils-2.24/cpu/iq2000.cpu b/binutils-2.24/cpu/iq2000.cpu deleted file mode 100644 index e25ba693..00000000 --- a/binutils-2.24/cpu/iq2000.cpu +++ /dev/null @@ -1,1196 +0,0 @@ -; IQ2000/IQ10 Common CPU description. -*- Scheme -*- -; Copyright 2001, 2002, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Fujitsu. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -(define-arch - (name iq2000) - (comment "IQ2000 architecture") - (insn-lsb0? #t) - (machs iq2000 iq10) - (isas iq2000) -) - -(define-isa - (name iq2000) - (comment "Basic IQ2000 instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) - (decode-assist (31 30 29 28 27 26)) -) - -(define-cpu - (name iq2000bf) - (comment "IQ2000 family") - (endian big) - (word-bitsize 32) - (file-transform "") -) - -(define-cpu - (name iq10bf) - (comment "IQ10 coprocessor family") - (endian big) - (word-bitsize 32) - (file-transform "") - -) - -(define-mach - (name iq2000) - (comment "IQ2000 packet processing engine") - (cpu iq2000bf) - (isas iq2000) -) - -(define-mach - (name iq10) - (comment "IQ10 coprocessor") - (cpu iq10bf) - (isas iq2000) -) - -(define-model - (name iq2000) - (comment "IQ2000 microprocessor") - (mach iq2000) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () () () ()) -) - -(define-model - (name iq10) - (comment "IQ10 coprocessor") - (mach iq10) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () () () ()) -) - -; Macros to simplify MACH attribute specification. - -(define-pmacro MACH2000 (MACH iq2000)) -(define-pmacro MACH10 (MACH iq10)) - - -; Hardware elements. - -(define-hardware - (name h-pc) - (comment "program counter") - (attrs PC PROFILE (ISA iq2000)) - (type pc) - (get () (c-call USI "get_h_pc")) - (set (newval) (c-call VOID "set_h_pc" newval)) -) -; FIXME: it would be nice if the hardwired zero in R0 could be -; specified as a virtual hardware element, with one less register in -; the register file proper. - -(define-keyword - (name gr-names) - (print-name h-gr) - (values (r0 0) (%0 0) (r1 1) (%1 1) (r2 2) (%2 2) (r3 3) (%3 3) - (r4 4) (%4 4) (r5 5) (%5 5) (r6 6) (%6 6) (r7 7) (%7 7) - (r8 8) (%8 8) (r9 9) (%9 9) (r10 10) (%10 10) (r11 11) (%11 11) - (r12 12) (%12 12) (r13 13) (%13 13) (r14 14) (%14 14) (r15 15) (%15 15) - (r16 16) (%16 16) (r17 17) (%17 17) (r18 18) (%18 18) (r19 19) (%19 19) - (r20 20) (%20 20) (r21 21) (%21 21) (r22 22) (%22 22) (r23 23) (%23 23) - (r24 24) (%24 24) (r25 25) (%25 25) (r26 26) (%26 26) (r27 27) (%27 27) - (r28 28) (%28 28) (r29 29) (%29 29) (r30 30) (%30 30) (r31 31) (%31 31)) -) - -(define-hardware - (name h-gr) - (comment "General purpose registers") -; (attrs (ISA iq2000) CACHE-ADDR) - (type register SI (32)) - (indices extern-keyword gr-names) - (get (idx) - (cond SI - ((eq idx 0) (const 0)) - (else (raw-reg h-gr idx)))) - (set (idx newval) - (cond VOID - ((eq idx 0) (nop)) - (else (set (raw-reg h-gr idx) newval)))) -) - - -; Instruction fields. - -(dnf f-opcode "opcode field" () 31 6) -(dnf f-rs "register field Rs" () 25 5) -(dnf f-rt "register field Rt" () 20 5) -(dnf f-rd "register field Rd" () 15 5) -(dnf f-shamt "shift amount field" () 10 5) -(dnf f-cp-op "coprocessor op field" () 10 3) -(dnf f-cp-op-10 "coprocessor op field for CAM" () 10 5) -(dnf f-cp-grp "coprocessor group field" () 7 2) -(dnf f-func "function field" () 5 6) -(dnf f-imm "immediate field" () 15 16) - -(define-multi-ifield - (name f-rd-rs) - (comment "register Rd implied from Rs") - (attrs) - (mode UINT) - (subfields f-rd f-rs) - (insert (sequence () - (set (ifield f-rd) (ifield f-rd-rs)) - (set (ifield f-rs) (ifield f-rd-rs)) - )) - (extract (sequence () - (set (ifield f-rd-rs) (ifield f-rs)) - )) -) - -(define-multi-ifield - (name f-rd-rt) - (comment "register Rd implied from Rt") - (attrs) - (mode UINT) - (subfields f-rd f-rt) - (insert (sequence () - (set (ifield f-rd) (ifield f-rd-rt)) - (set (ifield f-rt) (ifield f-rd-rt)) - )) - (extract (sequence () - (set (ifield f-rd-rt) (ifield f-rt)) - )) -) - -(define-multi-ifield - (name f-rt-rs) - (comment "register Rt implied from Rs") - (attrs) - (mode UINT) - (subfields f-rt f-rs) - (insert (sequence () - (set (ifield f-rt) (ifield f-rt-rs)) - (set (ifield f-rs) (ifield f-rt-rs)) - )) - (extract (sequence () - (set (ifield f-rd-rs) (ifield f-rs)) - )) -) - -(df f-jtarg "jump target field" (ABS-ADDR) 15 16 UINT - ((value pc) (srl USI (and USI value #x03FFFF) 2)) - ((value pc) (or USI (and USI pc #xF0000000) (sll USI value 2)))) - -(df f-jtargq10 "iq10 jump target field" (ABS-ADDR) 20 21 UINT - ((value pc) (srl SI (and SI value #x7FFFFF) 2)) - ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2)))) - -(df f-offset "pc offset field" (PCREL-ADDR) 15 16 INT - ; Actually, this is relative to the address of the delay slot. - ((value pc) (sra SI (sub SI value pc) 2)) - ((value pc) (add SI (sll SI value 2) (add pc 4)))) - -; Instruction fields that scarcely appear in instructions. - -(dnf f-count "count field" () 15 7) -(dnf f-bytecount "byte count field" () 7 8) -(dnf f-index "index field" () 8 9) -(dnf f-mask "mask field" () 9 4) -(dnf f-maskq10 "iq10 mask field" () 10 5) -(dnf f-maskl "mask left field" () 4 5) -(dnf f-excode "execcode field" () 25 20) -(dnf f-rsrvd "reserved field" () 25 10) -(dnf f-10-11 "bits 10:0" () 10 11) -(dnf f-24-19 "bits 24:6" () 24 19) -(dnf f-5 "bit 5" () 5 1) -(dnf f-10 "bit 10" () 10 1) -(dnf f-25 "bit 25" () 25 1) -(dnf f-cam-z "cam global mask z" () 5 3) -(dnf f-cam-y "cam operation y" () 2 3) -(dnf f-cm-3func "CM 3 bit fn field" () 5 3) -(dnf f-cm-4func "CM 4 bit fn field" () 5 4) -(dnf f-cm-3z "CM 3Z field" () 1 2) -(dnf f-cm-4z "CM 4Z field" () 2 3) - - -; Enumerations. - -(define-normal-insn-enum - opcodes "primary opcodes" () OP_ f-opcode - (("SPECIAL" 0) ("REGIMM" 1) ("J" 2) ("JAL" 3) ("BEQ" 4) ("BNE" 5) ("BLEZ" 6) ("BGTZ" 7) - ("ADDI" 8) ("ADDIU" 9) ("SLTI" 10) ("SLTIU" 11) ("ANDI" 12) ("ORI" 13) ("XORI" 14) ("LUI" 15) - ("COP0" 16) ("COP1" 17) ("COP2" 18) ("COP3" 19) ("BEQL" 20) ("BNEL" 21) ("BLEZL" 22) ("BGTZL" 23) - ("BMB0" 24) ("BMB1" 25) ("BMB2" 26) ("BMB3" 27) ("BBI" 28) ("BBV" 29) ("BBIN" 30) ("BBVN" 31) - ("LB" 32) ("LH" 33) ("LW" 35) ("LBU" 36) ("LHU" 37) ("RAM" 39) - ("SB" 40) ("SH" 41) ("SW" 43) ("ANDOI" 44) ("BMB" 45) ("ORUI" 47) - ("LDW" 48) - ("SDW" 56) ("ANDOUI" 63)) -) - -(define-normal-insn-enum - q10_opcodes "iq10-only primary opcodes" () OP10_ f-opcode - (("BMB" 6) ("ORUI" 15) ("BMBL" 22) ("ANDOUI" 47) ("BBIL" 60) ("BBVL" 61) ("BBINL" 62) ("BBVNL" 63)) -) - -(define-normal-insn-enum - regimm-functions "branch sub-opcodes" () FUNC_ f-rt - (("BLTZ" 0) ("BGEZ" 1) ("BLTZL" 2) ("BGEZL" 3) ("BLEZ" 4) ("BGTZ" 5) ("BLEZL" 6) ("BGTZL" 7) - ("BRI" 8) ("BRV" 9) ("BCTX" 12) - ("BLTZAL" 16) ("BGEZAL" 17) ("BLTZALL" 18) ("BGEZALL" 19) ("BLEZAL" 20) ("BGTZAL" 21) ("BLEZALL" 22) ("BGTZALL" 23)) -) - -(define-normal-insn-enum - functions "function sub-opcodes" () FUNC_ f-func - (("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7) - ("JR" 8) ("JALR" 9) ("JCR" 10) ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14) - ("ADD" 32) ("ADDU" 33) ("SUB" 34) ("SUBU" 35) ("AND" 36) ("OR" 37) ("XOR" 38) ("NOR" 39) - ("ADO16" 41) ("SLT" 42) ("SLTU" 43) ("MRGB" 45)) -) - -; iq10 special function sub-opcodes -(define-normal-insn-enum - q10s_functions "iq10-only special function sub-opcodes" () FUNC10_ f-func - (("YIELD" 14) ("CNT1S" 46)) -) - -; coprocessor opcodes in concert with f-cp-grp -(define-normal-insn-enum - cop_functions "iq10 function sub-opcodes" () FUNC10_ f-func - (("CFC" 0) ("LOCK" 1) ("CTC" 2) ("UNLK" 3) ("SWRD" 4) ("SWRDL" 5) ("SWWR" 6) ("SWWRU" 7) - ("RBA" 8) ("RBAL" 9) ("RBAR" 10) ("DWRD" 12) ("DWRDL" 13) - ("WBA" 16) ("WBAU" 17) ("WBAC" 18) ("CRC32" 20) ("CRC32B" 21) - ("MCID" 32) ("DBD" 33) ("DBA" 34) ("DPWT" 35) ("AVAIL" 36) ("FREE" 37) ("CHKHDR" 38) ("TSTOD" 39) - ("PKRLA" 40) ("PKRLAU" 41) ("PKRLAH" 42) ("PKRLAC" 43) ("CMPHDR" 44) - - ("CM64RS" 0) ("CM64RD" 1) ("CM64RI" 4) ("CM64CLR" 5) - ("CM64SS" 8) ("CM64SD" 9) ("CM64SI" 12) - ("CM64RA" 16) ("CM64RIA2" 20) ("CM128RIA2" 21) - ("CM64SA" 24) ("CM64SIA2" 28) ("CM128SIA2" 29) - ("CM32RS" 32) ("CM32RD" 33) ("CM32XOR" 34) ("CM32ANDN" 35) ("CM32RI" 36) ("CM128VSA" 38) - ("CM32SS" 40) ("CM32SD" 41) ("CM32OR" 42) ("CM32AND" 43) ("CM32SI" 44) - ("CM32RA" 48) - ("CM32SA" 56) ) -) - -; coprocessor opcodes in concert with f-cp-grp -(define-normal-insn-enum - cop_cm128_4functions "iq10 function sub-opcodes" () FUNC10_ f-cm-4func - (("CM128RIA3" 4) ("CM128SIA3" 6)) -) - -(define-normal-insn-enum - cop_cm128_3functions "iq10 function sub-opcodes" () FUNC10_ f-cm-3func - (("CM128RIA4" 6) ("CM128SIA4" 7)) -) - -(define-normal-insn-enum - cop2_functions "iq10 coprocessor sub-opcodes" () FUNC10_ f-cp-op - (("PKRLI" 0) ("PKRLIU" 1) ("PKRLIH" 2) ("PKRLIC" 3) ("RBIR" 1) ("RBI" 2) ("RBIL" 3) ("WBIC" 5) ("WBI" 6) ("WBIU" 7)) -) - -(define-normal-insn-enum - cop3_cam_functions "iq10 coprocessor cam sub-opcodes" () FUNC10_ f-cp-op-10 - (("CAM36" 16) ("CAM72" 17) ("CAM144" 18) ("CAM288" 19)) -) - - -; Attributes. - -(define-attr - (for insn) - (type boolean) - (name YIELD-INSN) - (comment "insn generates a context yield") -) - -(define-attr - (for insn) - (type boolean) - (name LOAD-DELAY) - (comment "insn has a load delay") -) - -(define-attr - (for insn) - (type boolean) - (name EVEN-REG-NUM) - (comment "insn requires an even numbered register in rt(2000) or rd(10)") -) - -(define-attr - (for insn) - (type boolean) - (name UNSUPPORTED) - (comment "insn is unsupported") -) - -(define-pmacro (define-reg-use-attr regfield) - (define-attr - (for insn) - (type boolean) - (name (.sym USES- (.upcase regfield))) - (comment ("insn accesses register operand " regfield)))) - -(define-reg-use-attr "rd") -(define-reg-use-attr "rs") -(define-reg-use-attr "rt") -(define-reg-use-attr "r31") - - -; Operands. - -(dnop rs "register Rs" () h-gr f-rs) -(dnop rt "register Rt" () h-gr f-rt) -(dnop rd "register Rd" () h-gr f-rd) -(dnop rd-rs "register Rd from Rs" () h-gr f-rd-rs) -(dnop rd-rt "register Rd from Rt" () h-gr f-rd-rt) -(dnop rt-rs "register Rt from Rs" () h-gr f-rt-rs) -(dnop shamt "shift amount" () h-uint f-shamt) -(define-operand (name imm) (comment "immediate") (attrs) - (type h-uint) (index f-imm) (handlers (parse "imm"))) -(dnop offset "pc-relative offset" () h-iaddr f-offset) -(dnop baseoff "base register offset" () h-iaddr f-imm) -(dnop jmptarg "jump target" () h-iaddr f-jtarg) -(dnop mask "mask" () h-uint f-mask) -(dnop maskq10 "iq10 mask" () h-uint f-maskq10) -(dnop maskl "mask left" () h-uint f-maskl) -(dnop count "count" () h-uint f-count) -(dnop _index "index" () h-uint f-index) -(dnop execode "execcode" () h-uint f-excode) -(dnop bytecount "byte count" () h-uint f-bytecount) -(dnop cam-y "cam global opn y" () h-uint f-cam-y) -(dnop cam-z "cam global mask z" () h-uint f-cam-z) -(dnop cm-3func "CM 3 bit fn field" () h-uint f-cm-3func) -(dnop cm-4func "CM 4 bit fn field" () h-uint f-cm-4func) -(dnop cm-3z "CM 3 bit Z field" () h-uint f-cm-3z) -(dnop cm-4z "CM 4 bit Z field" () h-uint f-cm-4z) - -; Aliases for the rs and rt operands. This just makes the load/store -; insns easier to compare with the instruction set documentation. - -(dnop base "base register" () h-gr f-rs) -(dnop maskr "mask right" () h-uint f-rs) -(dnop bitnum "bit number" () h-uint f-rt) - -; For high(foo). -(define-operand - (name hi16) - (comment "high 16 bit immediate") - (attrs) - (type h-uint) - (index f-imm) - (handlers (parse "hi16")) -) - -; For low(foo). -(define-operand - (name lo16) - (comment "16 bit signed immediate, for low") - (attrs) - (type h-uint) - (index f-imm) - (handlers (parse "lo16")) -) - -; For negated imm. -(define-operand - (name mlo16) - (comment "negated 16 bit signed immediate") - (attrs) - (type h-uint) - (index f-imm) - (handlers (parse "mlo16")) -) - -; For iq10 jmps -; In the future, we'll want the j & jal to use the 21 bit target, with -; the upper five bits shifted up. For now, don't use this. -(define-operand - (name jmptargq10) - (comment "iq10 21-bit jump offset") - (attrs) - (type h-iaddr) - (index f-jtargq10) - (handlers (parse "jtargq10")) -) - - -; Instructions. - -; A pmacro for use in semantic bodies of unimplemented insns. -(define-pmacro (unimp mnemonic) (nop)) - -(define-pmacro (bitset? value bit-num) - (and value (sll 1 bit-num))) - -(define-pmacro (bitclear? value bit-num) - (not (bitset? value bit-num))) - -; Arithmetic/logic instructions. - -(dni add2 "add registers" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "add ${rd-rs},$rt" - (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_ADD) - (set rd-rs (add rt rd-rs)) - ()) - -(dni add "add registers" (USES-RD USES-RS USES-RT) - "add $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADD) - (set rd (add rs rt)) - ()) - - -(dni addi2 "add immediate" (ALIAS NO-DIS USES-RS USES-RT) - "addi ${rt-rs},$lo16" - (+ OP_ADDI rt-rs lo16) - (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) - ()) - -(dni addi "add immediate" (USES-RS USES-RT) - "addi $rt,$rs,$lo16" - (+ OP_ADDI rs rt lo16) - (set rt (add rs (ext SI (trunc HI lo16)))) - ()) - -(dni addiu2 "add immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) - "addiu ${rt-rs},$lo16" - (+ OP_ADDIU rt-rs lo16) - (set rt-rs (add rt-rs (ext SI (trunc HI lo16)))) - ()) - -(dni addiu "add immediate unsigned" (USES-RS USES-RT) - "addiu $rt,$rs,$lo16" - (+ OP_ADDIU rs rt lo16) - (set rt (add rs (ext SI (trunc HI lo16)))) - ()) - -(dni addu2 "add unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "addu ${rd-rs},$rt" - (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADDU) - (set rd-rs (add rd-rs rt)) - ()) - -(dni addu "add unsigned" (USES-RD USES-RS USES-RT) - "addu $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADDU) - (set rd (add rs rt)) - ()) - -(dni ado162 "add 16, ones complement" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "ado16 ${rd-rs},$rt" - (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_ADO16) - (sequence ((HI high) (HI low)) - (set low (add HI (and HI rd-rs #xFFFF) (and HI rt #xFFFF))) - (set high (add HI (srl rd-rs 16) (srl rt 16))) - (set rd-rs (or SI (sll SI high 16) low))) - ()) - -(dni ado16 "add 16, ones complement" (USES-RD USES-RS USES-RT) - "ado16 $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_ADO16) - (sequence ((HI high) (HI low)) - (set low (add HI (and HI rs #xFFFF) (and HI rt #xFFFF))) - (set high (add HI (srl rs 16) (srl rt 16))) - (set rd (or SI (sll SI high 16) low))) - ()) - -(dni and2 "and register" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "and ${rd-rs},$rt" - (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_AND) - (set rd-rs (and rd-rs rt)) - ()) - -(dni and "and register" (USES-RD USES-RS USES-RT) - "and $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_AND) - (set rd (and rs rt)) - ()) - -(dni andi2 "and immediate" (ALIAS NO-DIS USES-RS USES-RT) - "andi ${rt-rs},$lo16" - (+ OP_ANDI rt-rs lo16) - (set rt-rs (and rt-rs (zext SI lo16))) - ()) - -(dni andi "and immediate" (USES-RS USES-RT) - "andi $rt,$rs,$lo16" - (+ OP_ANDI rs rt lo16) - (set rt (and rs (zext SI lo16))) - ()) - -(dni andoi2 "and ones immediate" (ALIAS NO-DIS USES-RS USES-RT) - "andoi ${rt-rs},$lo16" - (+ OP_ANDOI rt-rs lo16) - (set rt-rs (and rt-rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) - ()) - -(dni andoi "and ones immediate" (USES-RS USES-RT) - "andoi $rt,$rs,$lo16" - (+ OP_ANDOI rs rt lo16) - (set rt (and rs (or #xFFFF0000 (ext SI (trunc HI lo16))))) - ()) - -(dni nor2 "nor" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "nor ${rd-rs},$rt" - (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_NOR) - (set rd-rs (inv (or rd-rs rt))) - ()) - -(dni nor "nor" (USES-RD USES-RS USES-RT) - "nor $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_NOR) - (set rd (inv (or rs rt))) - ()) - -(dni or2 "or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "or ${rd-rs},$rt" - (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_OR) - (set rd-rs (or rd-rs rt)) - ()) - -(dni or "or" (USES-RD USES-RS USES-RT) - "or $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_OR) - (set rd (or rs rt)) - ()) - -(dni ori2 "or immediate" (ALIAS NO-DIS USES-RS USES-RT) - "ori ${rt-rs},$lo16" - (+ OP_ORI rt-rs lo16) - (set rt-rs (or rt-rs (zext SI lo16))) - ()) - -(dni ori "or immediate" (USES-RS USES-RT) - "ori $rt,$rs,$lo16" - (+ OP_ORI rs rt lo16) - (set rt (or rs (zext SI lo16))) - ()) - -(dni ram "rotate and mask" (USES-RD USES-RT) - "ram $rd,$rt,$shamt,$maskl,$maskr" - (+ OP_RAM maskr rt rd shamt (f-5 0) maskl) - (sequence () - (set rd (ror rt shamt)) - (set rd (and rd (srl #xFFFFFFFF maskl))) - (set rd (and rd (sll #xFFFFFFFF maskr)))) - ()) - -(dni sll "shift left logical" (USES-RD USES-RT) - "sll $rd,$rt,$shamt" - (+ OP_SPECIAL (f-rs 0) rt rd shamt (f-func 0)) - (set rd (sll rt shamt)) - ()) - -(dni sllv2 "shift left logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "sllv ${rd-rt},$rs" - (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SLLV) - (set rd-rt (sll rd-rt (and rs #x1F))) - ()) - -(dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT) - "sllv $rd,$rt,$rs" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLLV) - (set rd (sll rt (and rs #x1F))) - ()) - -(dni slmv2 "shift left and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "slmv ${rd-rt},$rs,$shamt" - (+ OP_SPECIAL rs rd-rt shamt FUNC_SLMV) - (set rd-rt (and (sll rd-rt shamt) (srl #xFFFFFFFF rs))) - ()) - -(dni slmv "shift left and mask variable" (USES-RD USES-RS USES-RT) - "slmv $rd,$rt,$rs,$shamt" - (+ OP_SPECIAL rs rt rd shamt FUNC_SLMV) - (set rd (and (sll rt shamt) (srl #xFFFFFFFF rs))) - ()) - -(dni slt2 "set if less than" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "slt ${rd-rs},$rt" - (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SLT) - (if (lt rd-rs rt) - (set rd-rs 1) - (set rd-rs 0)) - ()) - -(dni slt "set if less than" (USES-RD USES-RS USES-RT) - "slt $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLT) - (if (lt rs rt) - (set rd 1) - (set rd 0)) - ()) - -(dni slti2 "set if less than immediate" (ALIAS NO-DIS USES-RS USES-RT) - "slti ${rt-rs},$imm" - (+ OP_SLTI rt-rs imm) - (if (lt rt-rs (ext SI (trunc HI imm))) - (set rt-rs 1) - (set rt-rs 0)) - ()) - -(dni slti "set if less than immediate" (USES-RS USES-RT) - "slti $rt,$rs,$imm" - (+ OP_SLTI rs rt imm) - (if (lt rs (ext SI (trunc HI imm))) - (set rt 1) - (set rt 0)) - ()) - -(dni sltiu2 "set if less than immediate unsigned" (ALIAS NO-DIS USES-RS USES-RT) - "sltiu ${rt-rs},$imm" - (+ OP_SLTIU rt-rs imm) - (if (ltu rt-rs (ext SI (trunc HI imm))) - (set rt-rs 1) - (set rt-rs 0)) - ()) - -(dni sltiu "set if less than immediate unsigned" (USES-RS USES-RT) - "sltiu $rt,$rs,$imm" - (+ OP_SLTIU rs rt imm) - (if (ltu rs (ext SI (trunc HI imm))) - (set rt 1) - (set rt 0)) - ()) - -(dni sltu2 "set if less than unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "sltu ${rd-rs},$rt" - (+ OP_SPECIAL rd-rs rt (f-shamt 0) FUNC_SLTU) - (if (ltu rd-rs rt) - (set rd-rs 1) - (set rd-rs 0)) - ()) - -(dni sltu "set if less than unsigned" (USES-RD USES-RS USES-RT) - "sltu $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SLTU) - (if (ltu rs rt) - (set rd 1) - (set rd 0)) - ()) - -(dni sra2 "shift right arithmetic" (ALIAS NO-DIS USES-RD USES-RT) - "sra ${rd-rt},$shamt" - (+ OP_SPECIAL (f-rs 0) rd-rt shamt FUNC_SRA) - (set rd-rt (sra rd-rt shamt)) - ()) - -(dni sra "shift right arithmetic" (USES-RD USES-RT) - "sra $rd,$rt,$shamt" - (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRA) - (set rd (sra rt shamt)) - ()) - -(dni srav2 "shift right arithmetic variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "srav ${rd-rt},$rs" - (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRAV) - (set rd-rt (sra rd-rt (and rs #x1F))) - ()) - -(dni srav "shift right arithmetic variable" (USES-RD USES-RS USES-RT) - "srav $rd,$rt,$rs" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRAV) - (set rd (sra rt (and rs #x1F))) - ()) - -(dni srl "shift right logical" (USES-RD USES-RT) - "srl $rd,$rt,$shamt" - (+ OP_SPECIAL (f-rs 0) rt rd shamt FUNC_SRL) - (set rd (srl rt shamt)) - ()) - -(dni srlv2 "shift right logical variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "srlv ${rd-rt},$rs" - (+ OP_SPECIAL rs rd-rt (f-shamt 0) FUNC_SRLV) - (set rd-rt (srl rd-rt (and rs #x1F))) - ()) - -(dni srlv "shift right logical variable" (USES-RD USES-RS USES-RT) - "srlv $rd,$rt,$rs" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SRLV) - (set rd (srl rt (and rs #x1F))) - ()) - -(dni srmv2 "shift right and mask variable" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "srmv ${rd-rt},$rs,$shamt" - (+ OP_SPECIAL rs rd-rt shamt FUNC_SRMV) - (set rd-rt (and (srl rd-rt shamt) (sll #xFFFFFFFF rs))) - ()) - -(dni srmv "shift right and mask variable" (USES-RD USES-RS USES-RT) - "srmv $rd,$rt,$rs,$shamt" - (+ OP_SPECIAL rs rt rd shamt FUNC_SRMV) - (set rd (and (srl rt shamt) (sll #xFFFFFFFF rs))) - ()) - -(dni sub2 "subtract" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "sub ${rd-rs},$rt" - (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUB) - (set rd-rs (sub rd-rs rt)) - ()) - -(dni sub "subtract" (USES-RD USES-RS USES-RT) - "sub $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUB) - (set rd (sub rs rt)) - ()) - -(dni subu2 "subtract unsigned" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "subu ${rd-rs},$rt" - (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_SUBU) - (set rd-rs (sub rd-rs rt)) - ()) - -(dni subu "subtract unsigned" (USES-RD USES-RS USES-RT) - "subu $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_SUBU) - (set rd (sub rs rt)) - ()) - -(dni xor2 "exclusive or" (ALIAS NO-DIS USES-RD USES-RS USES-RT) - "xor ${rd-rs},$rt" - (+ OP_SPECIAL rt rd-rs (f-shamt 0) FUNC_XOR) - (set rd-rs (xor rd-rs rt)) - ()) - -(dni xor "exclusive or" (USES-RD USES-RS USES-RT) - "xor $rd,$rs,$rt" - (+ OP_SPECIAL rs rt rd (f-shamt 0) FUNC_XOR) - (set rd (xor rs rt)) - ()) - -(dni xori2 "exclusive or immediate" (ALIAS NO-DIS USES-RS USES-RT) - "xori ${rt-rs},$lo16" - (+ OP_XORI rt-rs lo16) - (set rt-rs (xor rt-rs (zext SI lo16))) - ()) - -(dni xori "exclusive or immediate" (USES-RS USES-RT) - "xori $rt,$rs,$lo16" - (+ OP_XORI rs rt lo16) - (set rt (xor rs (zext SI lo16))) - ()) - - -; Branch instructions. - -(dni bbi "branch bit immediate" (USES-RS) - "bbi $rs($bitnum),$offset" - (+ OP_BBI rs bitnum offset) - (if (bitset? rs bitnum) - (delay 1 (set pc offset))) - ()) - -(dni bbin "branch bit immediate negated" (USES-RS) - "bbin $rs($bitnum),$offset" - (+ OP_BBIN rs bitnum offset) - (if (bitclear? rs bitnum) - (delay 1 (set pc offset))) - ()) - -(dni bbv "branch bit variable" (USES-RS USES-RT) - "bbv $rs,$rt,$offset" - (+ OP_BBV rs rt offset) - (if (bitset? rs (and rt #x1F)) - (delay 1 (set pc offset))) - ()) - -(dni bbvn "branch bit variable negated" (USES-RS USES-RT) - "bbvn $rs,$rt,$offset" - (+ OP_BBVN rs rt offset) - (if (bitclear? rs (and rt #x1F)) - (delay 1 (set pc offset))) - ()) - -(dni beq "branch if equal" (USES-RS USES-RT) - "beq $rs,$rt,$offset" - (+ OP_BEQ rs rt offset) - (if (eq rs rt) - (delay 1 (set pc offset))) - ()) - -(dni beql "branch if equal likely" (USES-RS USES-RT) - "beql $rs,$rt,$offset" - (+ OP_BEQL rs rt offset) - (if (eq rs rt) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bgez "branch if greater than or equal to zero" (USES-RS) - "bgez $rs,$offset" - (+ OP_REGIMM rs FUNC_BGEZ offset) - (if (ge rs 0) - (delay 1 (set pc offset))) - ()) - -(dni bgezal "branch if greater than or equal to zero and link" (USES-RS USES-R31) - "bgezal $rs,$offset" - (+ OP_REGIMM rs FUNC_BGEZAL offset) - (if (ge rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset)))) - ()) - -(dni bgezall - "branch if greater than equal to zero and link likely" (USES-RS USES-R31) - "bgezall $rs,$offset" - (+ OP_REGIMM rs FUNC_BGEZALL offset) - (if (ge rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset))) - (skip 1)) - ()) - -(dni bgezl "branch if greater or equal to zero likely" (USES-RS) - "bgezl $rs,$offset" - (+ OP_REGIMM rs FUNC_BGEZL offset) - (if (ge rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bltz "branch if less than zero" (USES-RS) - "bltz $rs,$offset" - (+ OP_REGIMM rs FUNC_BLTZ offset) - (if (lt rs 0) - (delay 1 (set pc offset))) - ()) - -(dni bltzl "branch if less than zero likely" (USES-RS) - "bltzl $rs,$offset" - (+ OP_REGIMM rs FUNC_BLTZL offset) - (if (lt rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni bltzal "branch if less than zero and link" (USES-RS USES-R31) - "bltzal $rs,$offset" - (+ OP_REGIMM rs FUNC_BLTZAL offset) - (if (lt rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset)))) - ()) - -(dni bltzall "branch if less than zero and link likely" (USES-RS USES-R31) - "bltzall $rs,$offset" - (+ OP_REGIMM rs FUNC_BLTZALL offset) - (if (lt rs 0) - (sequence () - (set (reg h-gr 31) (add pc 8)) - (delay 1 (set pc offset))) - (skip 1)) - ()) - -(dni bmb0 "branch if matching byte-lane 0" (USES-RS USES-RT) - "bmb0 $rs,$rt,$offset" - (+ OP_BMB0 rs rt offset) - (if (eq (and rs #xFF) (and rt #xFF)) - (delay 1 (set pc offset))) - ()) - -(dni bmb1 "branch if matching byte-lane 1" (USES-RS USES-RT) - "bmb1 $rs,$rt,$offset" - (+ OP_BMB1 rs rt offset) - (if (eq (and rs #xFF00) (and rt #xFF00)) - (delay 1 (set pc offset))) - ()) - -(dni bmb2 "branch if matching byte-lane 2" (USES-RS USES-RT) - "bmb2 $rs,$rt,$offset" - (+ OP_BMB2 rs rt offset) - (if (eq (and rs #xFF0000) (and rt #xFF0000)) - (delay 1 (set pc offset))) - ()) - -(dni bmb3 "branch if matching byte-lane 3" (USES-RS USES-RT) - "bmb3 $rs,$rt,$offset" - (+ OP_BMB3 rs rt offset) - (if (eq (and rs #xFF000000) (and rt #xFF000000)) - (delay 1 (set pc offset))) - ()) - -(dni bne "branch if not equal" (USES-RS USES-RT) - "bne $rs,$rt,$offset" - (+ OP_BNE rs rt offset) - (if (ne rs rt) - (delay 1 (set pc offset))) - ()) - -(dni bnel "branch if not equal likely" (USES-RS USES-RT) - "bnel $rs,$rt,$offset" - (+ OP_BNEL rs rt offset) - (if (ne rs rt) - (delay 1 (set pc offset)) - (skip 1)) - ()) - - - - -; Jump instructions. -; Might as well jump! - -(dni jalr "jump and link register" (USES-RD USES-RS) - "jalr $rd,$rs" - (+ OP_SPECIAL rs (f-rt 0) rd (f-shamt 0) FUNC_JALR) - (delay 1 - (sequence () - (set rd (add pc 8)) - (set pc rs))) - ()) - -(dni jr "jump register" (USES-RS) - "jr $rs" - (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JR) - (delay 1 (set pc rs)) - ()) - - -; Load instructions. - -(dni lb "load byte" (LOAD-DELAY USES-RS USES-RT) - "lb $rt,$lo16($base)" - (+ OP_LB base rt lo16) - (set rt (ext WI (mem QI (add base (ext SI (trunc HI lo16)))))) -; (sequence ((SI addr) (SI word)) -; (set addr (add base lo16)) -; (set word (mem SI (and addr (inv 3)))) -; (set word (srl word (sll (and addr 2) 3))) -; (set rt (ext SI word))) - ()) - -(dni lbu "load byte unsigned" (LOAD-DELAY USES-RS USES-RT) - "lbu $rt,$lo16($base)" - (+ OP_LBU base rt lo16) - (set rt (zext WI (mem QI (add base (ext SI (trunc HI lo16)))))) -; (sequence ((SI addr) (SI word)) -; (set addr (add base lo16)) -; (set word (mem SI (and addr (inv 3)))) -; (set rt (srl word (sll (and addr 2) 3)))) - ()) - -(dni lh "load half word" (LOAD-DELAY USES-RS USES-RT) - "lh $rt,$lo16($base)" - (+ OP_LH base rt lo16) - (set rt (ext WI (mem HI (add base (ext SI (trunc HI lo16)))))) -; (sequence ((SI addr) (HI word)) -; (set addr (add base lo16)) -; (set word (mem SI (and addr (inv 3)))) -; (set word (srl word (sll (and addr 1) 4))) -; (set rt (ext SI word))) - ()) - -(dni lhu "load half word unsigned" (LOAD-DELAY USES-RS USES-RT) - "lhu $rt,$lo16($base)" - (+ OP_LHU base rt lo16) - (set rt (zext WI (mem HI (add base (ext SI (trunc HI lo16)))))) -; (sequence ((SI addr) (SI word)) -; (set addr (add base lo16)) -; (set word (mem SI (and addr (inv 3)))) -; (set rt (srl word (sll (and addr 1) 4)))) - ()) - -(dni lui "load upper immediate" (USES-RT) - "lui $rt,$hi16" - (+ OP_LUI (f-rs 0) rt hi16) - (set rt (sll hi16 16)) - ()) - -(dni lw "load word" (LOAD-DELAY USES-RS USES-RT) - "lw $rt,$lo16($base)" - (+ OP_LW base rt lo16) - (set rt (mem SI (add base (ext SI (trunc HI lo16))))) - ()) - - -; Store instructions. - -(dni sb "store byte" (USES-RS USES-RT) - "sb $rt,$lo16($base)" - (+ OP_SB base rt lo16) - (set (mem QI (add base (ext SI (trunc HI lo16)))) (and QI rt #xFF)) - ()) - -(dni sh "store half word" (USES-RS USES-RT) - "sh $rt,$lo16($base)" - (+ OP_SH base rt lo16) - (set (mem HI (add base (ext SI (trunc HI lo16)))) (and HI rt #xFFFF)) - ()) - -(dni sw "store word" (USES-RS USES-RT) - "sw $rt,$lo16($base)" - (+ OP_SW base rt lo16) - (set (mem SI (add base (ext SI (trunc HI lo16)))) rt) - ()) - - -; Special instructions for simulation/debugging -(dni break "breakpoint" () - "break" - (+ OP_SPECIAL (f-rs 0) (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_BREAK) - (c-call VOID "do_break" pc) - ()) - -(dni syscall "system call" (YIELD-INSN) - "syscall" - (+ OP_SPECIAL execode (f-func 12)) - (c-call VOID "do_syscall") - ()) - -; Macro instructions, common to iq10 & iq2000 - -(dnmi nop "nop" () - "nop" - (emit sll (rd 0) (rt 0) (shamt 0)) -) - -(dnmi li "load immediate" (USES-RS NO-DIS) - "li $rs,$imm" - (emit ori (rt 0) rs imm) -) - -(dnmi move "move" (USES-RD USES-RT NO-DIS) - "move $rd,$rt" - (emit or rd (rs 0) rt) -) - -(dnmi lb-base-0 "load byte - implied base 0" (USES-RT NO-DIS) - "lb $rt,$lo16" - (emit lb rt lo16 (base 0)) -) - -(dnmi lbu-base-0 "load byte unsigned - implied base 0" (USES-RT NO-DIS) - "lbu $rt,$lo16" - (emit lbu rt lo16 (base 0)) -) - -(dnmi lh-base-0 "load half - implied base 0" (USES-RT NO-DIS) - "lh $rt,$lo16" - (emit lh rt lo16 (base 0)) -) - -(dnmi lw-base-0 "load word - implied base 0" (USES-RT NO-DIS) - "lw $rt,$lo16" - (emit lw rt lo16 (base 0)) -) - -(dnmi m-add "add immediate" (USES-RS USES-RT NO-DIS) - "add $rt,$rs,$lo16" - (emit addi rt rs lo16)) - -(dnmi m-addu "add immediate unsigned" (USES-RS USES-RT NO-DIS) - "addu $rt,$rs,$lo16" - (emit addiu rt rs lo16) -) - -(dnmi m-and "and immediate" (USES-RS USES-RT NO-DIS) - "and $rt,$rs,$lo16" - (emit andi rt rs lo16) -) - -(dnmi m-j "jump register" (USES-RS NO-DIS) - "j $rs" - (emit jr rs) -) - -(dnmi m-or "or immediate" (USES-RS USES-RT NO-DIS) - "or $rt,$rs,$lo16" - (emit ori rt rs lo16) -) - -(dnmi m-sll "shift left logical" (USES-RD USES-RT USES-RS NO-DIS) - "sll $rd,$rt,$rs" - (emit sllv rd rt rs) -) - -(dnmi m-slt "slt immediate" (USES-RS USES-RT NO-DIS) - "slt $rt,$rs,$imm" - (emit slti rt rs imm) -) - -(dnmi m-sltu "sltu immediate" (USES-RS USES-RT NO-DIS) - "sltu $rt,$rs,$imm" - (emit sltiu rt rs imm) -) - -(dnmi m-sra "shift right arithmetic" (USES-RD USES-RT USES-RS NO-DIS) - "sra $rd,$rt,$rs" - (emit srav rd rt rs) -) - -(dnmi m-srl "shift right logical" (USES-RD USES-RT USES-RS NO-DIS) - "srl $rd,$rt,$rs" - (emit srlv rd rt rs) -) - -(dnmi not "not" (USES-RD USES-RT NO-DIS) - "not $rd,$rt" - (emit nor rd (rs 0) rt) -) - -(dnmi subi "sub immediate" (USES-RS USES-RT NO-DIS) - "subi $rt,$rs,$mlo16" - (emit addiu rt rs mlo16) -) - -(dnmi m-sub "subtract immediate" (USES-RS USES-RT NO-DIS) - "sub $rt,$rs,$mlo16" - (emit addiu rt rs mlo16) -) - -(dnmi m-subu "subtract unsigned" (USES-RS USES-RT NO-DIS) - "subu $rt,$rs,$mlo16" - (emit addiu rt rs mlo16) -) - -(dnmi sb-base-0 "store byte - implied base 0" (USES-RT NO-DIS) - "sb $rt,$lo16" - (emit sb rt lo16 (base 0)) -) - -(dnmi sh-base-0 "store half - implied base 0" (USES-RT NO-DIS) - "sh $rt,$lo16" - (emit sh rt lo16 (base 0)) -) - -(dnmi sw-base-0 "store word - implied base 0" (USES-RT NO-DIS) - "sw $rt,$lo16" - (emit sw rt lo16 (base 0)) -) - -(dnmi m-xor "xor immediate" (USES-RS USES-RT NO-DIS) - "xor $rt,$rs,$lo16" - (emit xori rt rs lo16) -) - - -(if (keep-mach? (iq2000)) -(include "iq2000m.cpu")) - -(if (keep-mach? (iq10)) -(include "iq10.cpu")) diff --git a/binutils-2.24/cpu/iq2000.opc b/binutils-2.24/cpu/iq2000.opc deleted file mode 100644 index f1803737..00000000 --- a/binutils-2.24/cpu/iq2000.opc +++ /dev/null @@ -1,320 +0,0 @@ -/* IQ2000 opcode support. -*- C -*- - - Copyright 2000, 2001, 2002, 2005, 2007, 2009 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; developed under contract from Fujitsu. - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* This file is an addendum to iq2000.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Override disassembly hashing - there are variable bits in the top - byte of these instructions. */ -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) - -/* following activates check beyond hashing since some iq2000 and iq10 - instructions have same mnemonics but different functionality. */ -#define CGEN_VALIDATE_INSN_SUPPORTED - -extern int iq2000_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); - -/* -- asm.c */ - -#include "safe-ctype.h" - -static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); - -/* Special check to ensure that instruction exists for given machine. */ - -int -iq2000_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ - int machs = cd->machs; - - return (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH) & machs) != 0; -} - -static int -iq2000_cgen_isa_register (const char **strp) -{ - int len; - int ch1, ch2; - - if (**strp == 'r' || **strp == 'R') - { - len = strlen (*strp); - if (len == 2) - { - ch1 = (*strp)[1]; - if ('0' <= ch1 && ch1 <= '9') - return 1; - } - else if (len == 3) - { - ch1 = (*strp)[1]; - ch2 = (*strp)[2]; - if (('1' <= ch1 && ch1 <= '2') && ('0' <= ch2 && ch2 <= '9')) - return 1; - if ('3' == ch1 && (ch2 == '0' || ch2 == '1')) - return 1; - } - } - if (**strp == '%' - && TOLOWER ((*strp)[1]) != 'l' - && TOLOWER ((*strp)[1]) != 'h') - return 1; - return 0; -} - -/* Handle negated literal. */ - -static const char * -parse_mimm (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - - /* Verify this isn't a register. */ - if (iq2000_cgen_isa_register (strp)) - errmsg = _("immediate value cannot be register"); - else - { - long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg == NULL) - { - long x = (-value) & 0xFFFF0000; - - if (x != 0 && x != (long) 0xFFFF0000) - errmsg = _("immediate value out of range"); - else - *valuep = (-value & 0xFFFF); - } - } - return errmsg; -} - -/* Handle signed/unsigned literal. */ - -static const char * -parse_imm (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - - if (iq2000_cgen_isa_register (strp)) - errmsg = _("immediate value cannot be register"); - else - { - long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg == NULL) - { - long x = value & 0xFFFF0000; - - if (x != 0 && x != (long) 0xFFFF0000) - errmsg = _("immediate value out of range"); - else - *valuep = (value & 0xFFFF); - } - } - return errmsg; -} - -/* Handle iq10 21-bit jmp offset. */ - -static const char * -parse_jtargq10 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - int reloc ATTRIBUTE_UNUSED, - enum cgen_parse_operand_result *type_addr ATTRIBUTE_UNUSED, - bfd_vma *valuep) -{ - const char *errmsg; - bfd_vma value; - enum cgen_parse_operand_result result_type = CGEN_PARSE_OPERAND_RESULT_NUMBER; - - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_OFFSET_21, - & result_type, & value); - if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - /* Check value is within 23-bits - (remembering that 2-bit shift right will occur). */ - if (value > 0x7fffff) - return _("21-bit offset out of range"); - } - *valuep = (value & 0x7FFFFF); - return errmsg; -} - -/* Handle high(). */ - -static const char * -parse_hi16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (strncasecmp (*strp, "%hi(", 4) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma value; - const char *errmsg; - - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - /* If value has top-bit of %lo on, then it will - sign-propagate and so we compensate by adding - 1 to the resultant %hi value. */ - if (value & 0x8000) - value += 0x10000; - value >>= 16; - value &= 0xffff; - } - *valuep = value; - - return errmsg; - } - - /* We add %uhi in case a user just wants the high 16-bits or is using - an insn like ori for %lo which does not sign-propagate. */ - if (strncasecmp (*strp, "%uhi(", 5) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma value; - const char *errmsg; - - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_IQ2000_UHI16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value >>= 16; - - value &= 0xffff; - *valuep = value; - - return errmsg; - } - - return parse_imm (cd, strp, opindex, valuep); -} - -/* Handle %lo in a signed context. - The signedness of the value doesn't matter to %lo(), but this also - handles the case where %lo() isn't present. */ - -static const char * -parse_lo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (strncasecmp (*strp, "%lo(", 4) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return parse_imm (cd, strp, opindex, valuep); -} - -/* Handle %lo in a negated signed context. - The signedness of the value doesn't matter to %lo(), but this also - handles the case where %lo() isn't present. */ - -static const char * -parse_mlo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (strncasecmp (*strp, "%lo(", 4) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = (-value) & 0xffff; - *valuep = value; - return errmsg; - } - - return parse_mimm (cd, strp, opindex, valuep); -} - -/* -- */ diff --git a/binutils-2.24/cpu/iq2000m.cpu b/binutils-2.24/cpu/iq2000m.cpu deleted file mode 100644 index 59422415..00000000 --- a/binutils-2.24/cpu/iq2000m.cpu +++ /dev/null @@ -1,631 +0,0 @@ -; IQ2000-only CPU description. -*- Scheme -*- -; -; Copyright 2000, 2001, 2002, 2004, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Vitesse. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(dni andoui "and upper ones immediate" (MACH2000 USES-RS USES-RT) - "andoui $rt,$rs,$hi16" - (+ OP_ANDOUI rs rt hi16) - (set rt (and rs (or (sll hi16 16) #xFFFF))) - ()) - -(dni andoui2 "and upper ones immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT) - "andoui ${rt-rs},$hi16" - (+ OP_ANDOUI rt-rs hi16) - (set rt-rs (and rt-rs (or (sll hi16 16) #xFFFF))) - ()) - -(dni orui2 "or upper immediate" (ALIAS NO-DIS MACH2000 USES-RS USES-RT) - "orui ${rt-rs},$hi16" - (+ OP_ORUI rt-rs hi16) - (set rt-rs (or rt-rs (sll hi16 16))) - ()) - -(dni orui "or upper immediate" (MACH2000 USES-RS USES-RT) - "orui $rt,$rs,$hi16" - (+ OP_ORUI rs rt hi16) - (set rt (or rs (sll hi16 16))) - ()) - -(dni bgtz "branch if greater than zero" (MACH2000 USES-RS) - "bgtz $rs,$offset" - (+ OP_BGTZ rs (f-rt 0) offset) - (if (gt rs 0) - (delay 1 (set pc offset))) - ()) - - -(dni bgtzl "branch if greater than zero likely" (MACH2000 USES-RS) - "bgtzl $rs,$offset" - (+ OP_BGTZL rs (f-rt 0) offset) - (if (gt rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - -(dni blez "branch if less than or equal to zero" (MACH2000 USES-RS) - "blez $rs,$offset" - (+ OP_BLEZ rs (f-rt 0) offset) - (if (le rs 0) - (delay 1 (set pc offset))) - ()) - -(dni blezl "branch if less than or equal to zero likely" (MACH2000 USES-RS) - "blezl $rs,$offset" - (+ OP_BLEZL rs (f-rt 0) offset) - (if (le rs 0) - (delay 1 (set pc offset)) - (skip 1)) - ()) - - -(dni mrgb "merge bytes" (MACH2000 USES-RD USES-RS USES-RT) - "mrgb $rd,$rs,$rt,$mask" - (+ OP_SPECIAL rs rt rd (f-10 0) mask FUNC_MRGB) - (sequence ((SI temp)) - (if (bitclear? mask 0) - (set temp (and rs #xFF)) - (set temp (and rt #xFF))) - (if (bitclear? mask 1) - (set temp (or temp (and rs #xFF00))) - (set temp (or temp (and rt #xFF00)))) - (if (bitclear? mask 2) - (set temp (or temp (and rs #xFF0000))) - (set temp (or temp (and rt #xFF0000)))) - (if (bitclear? mask 3) - (set temp (or temp (and rs #xFF000000))) - (set temp (or temp (and rt #xFF000000)))) - (set rd temp)) - ()) - -(dni mrgb2 "merge bytes" (ALIAS NO-DIS MACH2000 USES-RD USES-RS USES-RT) - "mrgb ${rd-rs},$rt,$mask" - (+ OP_SPECIAL rt rd-rs (f-10 0) mask FUNC_MRGB) - (sequence ((SI temp)) - (if (bitclear? mask 0) - (set temp (and rd-rs #xFF)) - (set temp (and rt #xFF))) - (if (bitclear? mask 1) - (set temp (or temp (and rd-rs #xFF00))) - (set temp (or temp (and rt #xFF00)))) - (if (bitclear? mask 2) - (set temp (or temp (and rd-rs #xFF0000))) - (set temp (or temp (and rt #xFF0000)))) - (if (bitclear? mask 3) - (set temp (or temp (and rd-rs #xFF000000))) - (set temp (or temp (and rt #xFF000000)))) - (set rd-rs temp)) - ()) - -; NOTE: None of these instructions' semantics are specified, so they -; will not work in a simulator. -; -; Architectural and coprocessor instructions. -; BREAK and SYSCALL are implemented with escape hatches to the C -; code. These are used by the test suite to indicate pass/failures. - -(dni bctxt "branch and switch context" (MACH2000 DELAY-SLOT COND-CTI USES-RS) - "bctxt $rs,$offset" - (+ OP_REGIMM rs (f-rt 6) offset) - (unimp bctxt) - ()) - -(dni bc0f "branch if copro 0 condition false" (MACH2000 DELAY-SLOT COND-CTI) - "bc0f $offset" - (+ OP_COP0 (f-rs 8) (f-rt 0) offset) - (unimp bc0f) - ()) - -(dni bc0fl "branch if copro 0 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) - "bc0fl $offset" - (+ OP_COP0 (f-rs 8) (f-rt 2) offset) - (unimp bc0fl) - ()) - -(dni bc3f "branch if copro 3 condition false" (MACH2000 DELAY-SLOT COND-CTI) - "bc3f $offset" - (+ OP_COP3 (f-rs 8) (f-rt 0) offset) - (unimp bc3f) - ()) - -(dni bc3fl "branch if copro 3 condition false likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) - "bc3fl $offset" - (+ OP_COP3 (f-rs 8) (f-rt 2) offset) - (unimp bc3fl) - ()) - -(dni bc0t "branch if copro 0 condition true" (MACH2000 DELAY-SLOT COND-CTI) - "bc0t $offset" - (+ OP_COP0 (f-rs 8) (f-rt 1) offset) - (unimp bc0t) - ()) - -(dni bc0tl "branch if copro 0 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) - "bc0tl $offset" - (+ OP_COP0 (f-rs 8) (f-rt 3) offset) - (unimp bc0tl) - ()) - -(dni bc3t "branch if copro 3 condition true" (MACH2000 DELAY-SLOT COND-CTI) - "bc3t $offset" - (+ OP_COP3 (f-rs 8) (f-rt 1) offset) - (unimp bc3t) - ()) - -(dni bc3tl "branch if copro 3 condition true likely" (MACH2000 DELAY-SLOT COND-CTI SKIP-CTI) - "bc3tl $offset" - (+ OP_COP3 (f-rs 8) (f-rt 3) offset) - (unimp bc3tl) - ()) - -; Note that we don't set the USES-RD or USES-RT attributes for many of the following -; instructions, as it's the COP register that's being specified. - -(dni cfc0 "control from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT) - "cfc0 $rt,$rd" - (+ OP_COP0 (f-rs 2) rt rd (f-10-11 0)) - (unimp cfc0) - ()) - -(dni cfc1 "control from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT) - "cfc1 $rt,$rd" - (+ OP_COP1 (f-rs 2) rt rd (f-10-11 0)) - (unimp cfc1) - ()) - -(dni cfc2 "control from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) - "cfc2 $rt,$rd" - (+ OP_COP2 (f-rs 2) rt rd (f-10-11 0)) - (unimp cfc2) - ()) - -(dni cfc3 "control from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) - "cfc3 $rt,$rd" - (+ OP_COP3 (f-rs 2) rt rd (f-10-11 0)) - (unimp cfc3) - ()) - -; COPz instructions are an instruction form, not real instructions -; with associated assembly mnemonics. Therefore, they are omitted -; from the ISA description. - -(dni chkhdr "check header" (MACH2000 LOAD-DELAY USES-RD YIELD-INSN) - "chkhdr $rd,$rt" - (+ OP_COP3 (f-rs 9) rt rd (f-shamt 0) (f-func 0)) - (unimp chkhdr) - ()) - -(dni ctc0 "control to coprocessor 0" (MACH2000 USES-RT) - "ctc0 $rt,$rd" - (+ OP_COP0 (f-rs 6) rt rd (f-10-11 0)) - (unimp ctc0) - ()) - -(dni ctc1 "control to coprocessor 1" (MACH2000 USES-RT) - "ctc1 $rt,$rd" - (+ OP_COP1 (f-rs 6) rt rd (f-10-11 0)) - (unimp ctc1) - ()) - -(dni ctc2 "control to coprocessor 2" (MACH2000 USES-RT) - "ctc2 $rt,$rd" - (+ OP_COP2 (f-rs 6) rt rd (f-10-11 0)) - (unimp ctc2) - ()) - -(dni ctc3 "control to coprocessor 3" (MACH2000 USES-RT) - "ctc3 $rt,$rd" - (+ OP_COP3 (f-rs 6) rt rd (f-10-11 0)) - (unimp ctc3) - ()) - -(dni jcr "jump context register" (MACH2000 DELAY-SLOT UNCOND-CTI USES-RS) - "jcr $rs" - (+ OP_SPECIAL rs (f-rt 0) (f-rd 0) (f-shamt 0) FUNC_JCR) - (unimp jcr) - ()) - -(dni luc32 "lookup chain 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) - "luc32 $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 3)) - (unimp luc32) - ()) - -(dni luc32l "lookup chain 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "luc32l $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) - (unimp luc32l) - ()) - -(dni luc64 "lookup chain 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) - "luc64 $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 11)) - (unimp luc64) - ()) - -(dni luc64l "lookup chain 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "luc64l $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 15)) - (unimp luc64l) - ()) - -(dni luk "lookup key" (MACH2000 USES-RD USES-RT) - "luk $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 8)) - (unimp luk) - ()) - -(dni lulck "lookup lock" (MACH2000 USES-RT YIELD-INSN) - "lulck $rt" - (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 4)) - (unimp lulck) - ()) - -(dni lum32 "lookup match 32 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) - "lum32 $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 2)) - (unimp lum32) - ()) - -(dni lum32l "lookup match 32 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "lum32l $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 6)) - (unimp lum32l) - ()) - -(dni lum64 "lookup match 64 bits" (MACH2000 USES-RD USES-RT YIELD-INSN) - "lum64 $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 10)) - (unimp lum64) - ()) - -(dni lum64l "lookup match 64 bits and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "lum64l $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 14)) - (unimp lum64l) - ()) - -(dni lur "lookup read" (MACH2000 USES-RD USES-RT YIELD-INSN) - "lur $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 1)) - (unimp lur) - ()) - -(dni lurl "lookup read and lock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "lurl $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 5)) - (unimp lurl) - ()) - -(dni luulck "lookup unlock" (MACH2000 USES-RT YIELD-INSN) - "luulck $rt" - (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 0)) - (unimp luulck) - ()) - -(dni mfc0 "move from coprocessor 0" (MACH2000 LOAD-DELAY USES-RT) - "mfc0 $rt,$rd" - (+ OP_COP0 (f-rs 0) rt rd (f-10-11 0)) - (unimp mfc0) - ()) - -(dni mfc1 "move from coprocessor 1" (MACH2000 LOAD-DELAY USES-RT) - "mfc1 $rt,$rd" - (+ OP_COP1 (f-rs 0) rt rd (f-10-11 0)) - (unimp mfc1) - ()) - -(dni mfc2 "move from coprocessor 2" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) - "mfc2 $rt,$rd" - (+ OP_COP2 (f-rs 0) rt rd (f-10-11 0)) - (unimp mfc2) - ()) - -(dni mfc3 "move from coprocessor 3" (MACH2000 LOAD-DELAY USES-RT YIELD-INSN) - "mfc3 $rt,$rd" - (+ OP_COP3 (f-rs 0) rt rd (f-10-11 0)) - (unimp mfc3) - ()) - -(dni mtc0 "move to coprocessor 0" (MACH2000 USES-RT) - "mtc0 $rt,$rd" - (+ OP_COP0 (f-rs 4) rt rd (f-10-11 0)) - (unimp mtc0) - ()) - -(dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT) - "mtc1 $rt,$rd" - (+ OP_COP1 (f-rs 4) rt rd (f-10-11 0)) - (unimp mtc1) - ()) - -(dni mtc2 "move to coprocessor 2" (MACH2000 USES-RT) - "mtc2 $rt,$rd" - (+ OP_COP2 (f-rs 4) rt rd (f-10-11 0)) - (unimp mtc2) - ()) - -(dni mtc3 "move to coprocessor 3" (MACH2000 USES-RT) - "mtc3 $rt,$rd" - (+ OP_COP3 (f-rs 4) rt rd (f-10-11 0)) - (unimp mtc3) - ()) - -(dni pkrl "pkrl" (MACH2000 USES-RD USES-RT YIELD-INSN) - "pkrl $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 7)) - (unimp pkrl) - ()) - -(dni pkrlr1 "pkrlr1" (MACH2000 USES-RT YIELD-INSN) - "pkrlr1 $rt,$_index,$count" - (+ OP_COP3 (f-rs 29) rt count _index) - (unimp pkrlr1) - ()) - -(dni pkrlr30 "pkrlr30" (MACH2000 USES-RT YIELD-INSN) - "pkrlr30 $rt,$_index,$count" - (+ OP_COP3 (f-rs 31) rt count _index) - (unimp pkrlr30) - ()) - -(dni rb "dma read bytes" (MACH2000 USES-RD USES-RT YIELD-INSN) - "rb $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 4)) - (unimp rb) - ()) - -(dni rbr1 "dma read bytes using r1" (MACH2000 USES-RT YIELD-INSN) - "rbr1 $rt,$_index,$count" - (+ OP_COP3 (f-rs 24) rt count _index) - (unimp rbr1) - ()) - -(dni rbr30 "dma read bytes using r30" (MACH2000 USES-RT YIELD-INSN) - "rbr30 $rt,$_index,$count" - (+ OP_COP3 (f-rs 26) rt count _index) - (unimp rbr30) - ()) - -(dni rfe "restore from exception" (MACH2000) - "rfe" - (+ OP_COP0 (f-25 1) (f-24-19 0) (f-func 16)) - (unimp rfe) - ()) - -(dni rx "dma read word64s" (MACH2000 USES-RD USES-RT YIELD-INSN) - "rx $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 6)) - (unimp rx) - ()) - -(dni rxr1 "dma read word64s using r1" (MACH2000 USES-RT YIELD-INSN) - "rxr1 $rt,$_index,$count" - (+ OP_COP3 (f-rs 28) rt count _index) - (unimp rxr1) - ()) - -(dni rxr30 "dma read word 64s using r30" (MACH2000 USES-RT YIELD-INSN) - "rxr30 $rt,$_index,$count" - (+ OP_COP3 (f-rs 30) rt count _index) - (unimp rxr30) - ()) - -(dni sleep "sleep" (MACH2000 YIELD-INSN) - "sleep" - (+ OP_SPECIAL execode FUNC_SLEEP) - (unimp sleep) - ()) - -(dni srrd "sram read" (MACH2000 USES-RT YIELD-INSN) - "srrd $rt" - (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 16)) - (unimp srrd) - ()) - -(dni srrdl "sram read and lock" (MACH2000 USES-RT YIELD-INSN) - "srrdl $rt" - (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 20)) - (unimp srrdl) - ()) - -(dni srulck "sram unlock" (MACH2000 USES-RT YIELD-INSN) - "srulck $rt" - (+ OP_COP2 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 22)) - (unimp srulck) - ()) - -(dni srwr "sram write" (MACH2000 USES-RD USES-RT YIELD-INSN) - "srwr $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 17)) - (unimp srwr) - ()) - -(dni srwru "sram write and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "srwru $rt,$rd" - (+ OP_COP2 (f-rs 1) rt rd (f-shamt 0) (f-func 21)) - (unimp srwru) - ()) - -(dni trapqfl "yield if dma queue full" (MACH2000 YIELD-INSN) - "trapqfl" - (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 8)) - (unimp trapqfl) - ()) - -(dni trapqne "yield if dma queue not empty" (MACH2000 YIELD-INSN) - "trapqne" - (+ OP_COP3 (f-rs 1) (f-rt 0) (f-rd 0) (f-shamt 0) (f-func 9)) - (unimp trapqne) - ()) - -(dni traprel "traprel" (MACH2000 USES-RT YIELD-INSN) - "traprel $rt" - (+ OP_COP3 (f-rs 1) rt (f-rd 0) (f-shamt 0) (f-func 10)) - (unimp traprel) - ()) - -(dni wb "dma write bytes" (MACH2000 USES-RD USES-RT YIELD-INSN) - "wb $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 0)) - (unimp wb) - ()) - -(dni wbu "dma write bytes and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "wbu $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 1)) - (unimp wbu) - ()) - -(dni wbr1 "dma write bytes using r1" (MACH2000 USES-RT YIELD-INSN) - "wbr1 $rt,$_index,$count" - (+ OP_COP3 (f-rs 16) rt count _index) - (unimp wbr1) - ()) - -(dni wbr1u "dma write bytes using r1 and unlock" (MACH2000 USES-RT YIELD-INSN) - "wbr1u $rt,$_index,$count" - (+ OP_COP3 (f-rs 17) rt count _index) - (unimp wbr1u) - ()) - -(dni wbr30 "dma write bytes using r30" (MACH2000 USES-RT YIELD-INSN) - "wbr30 $rt,$_index,$count" - (+ OP_COP3 (f-rs 18) rt count _index) - (unimp wbr30) - ()) - -(dni wbr30u "dma write bytes using r30 and unlock" (MACH2000 USES-RT YIELD-INSN) - "wbr30u $rt,$_index,$count" - (+ OP_COP3 (f-rs 19) rt count _index) - (unimp wbr30u) - ()) - -(dni wx "dma write word64s" (MACH2000 USES-RD USES-RT YIELD-INSN) - "wx $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 2)) - (unimp wx) - ()) - -(dni wxu "dma write word64s and unlock" (MACH2000 USES-RD USES-RT YIELD-INSN) - "wxu $rd,$rt" - (+ OP_COP3 (f-rs 1) rt rd (f-shamt 0) (f-func 3)) - (unimp wxu) - ()) - -(dni wxr1 "dma write word64s using r1" (MACH2000 USES-RT YIELD-INSN) - "wxr1 $rt,$_index,$count" - (+ OP_COP3 (f-rs 20) rt count _index) - (unimp wxr1) - ()) - -(dni wxr1u "dma write word64s using r1 and unlock" (MACH2000 USES-RT YIELD-INSN) - "wxr1u $rt,$_index,$count" - (+ OP_COP3 (f-rs 21) rt count _index) - (unimp wxr1u) - ()) - -(dni wxr30 "dma write word64s using r30" (MACH2000 USES-RT YIELD-INSN) - "wxr30 $rt,$_index,$count" - (+ OP_COP3 (f-rs 22) rt count _index) - (unimp wxr30) - ()) - -(dni wxr30u "dma write word64s using r30 and unlock" (MACH2000 USES-RT YIELD-INSN) - "wxr30u $rt,$_index,$count" - (+ OP_COP3 (f-rs 23) rt count _index) - (unimp wxr30u) - ()) - - -; Load/Store instructions. - -(dni ldw "load double word" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT) - "ldw $rt,$lo16($base)" - (+ OP_LDW base rt lo16) - (sequence ((SI addr)) - (set addr (and (add base lo16) (inv 3))) - (set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr)) - (set rt (mem SI (add addr 4)))) - ()) - -(dni sdw "store double word" (MACH2000 EVEN-REG-NUM USES-RT) - "sdw $rt,$lo16($base)" - (+ OP_SDW base rt lo16) - (sequence ((SI addr)) - (set addr (and (add base lo16) (inv 3))) - (set (mem SI (add addr 4)) rt) - (set (mem SI addr) (reg h-gr (add (ifield f-rt) 1)))) - ()) - - -; Jump instructions - -(dni j "jump" (MACH2000) - "j $jmptarg" - (+ OP_J (f-rsrvd 0) jmptarg) - (delay 1 (set pc jmptarg)) - ()) - -(dni jal "jump and link" (MACH2000 USES-R31) - "jal $jmptarg" - (+ OP_JAL (f-rsrvd 0) jmptarg) - (delay 1 - (sequence () - (set (reg h-gr 31) (add pc 8)) - (set pc jmptarg))) - ()) - -(dni bmb "branch if matching byte-lane" (MACH2000 USES-RS USES-RT) - "bmb $rs,$rt,$offset" - (+ OP_BMB rs rt offset) - (sequence ((BI branch?)) - (set branch? 0) - (if (eq (and rs #xFF) (and rt #xFF)) - (set branch? 1)) - (if (eq (and rs #xFF00) (and rt #xFF00)) - (set branch? 1)) - (if (eq (and rs #xFF0000) (and rt #xFF0000)) - (set branch? 1)) - (if (eq (and rs #xFF000000) (and rt #xFF000000)) - (set branch? 1)) - (if branch? - (delay 1 (set pc offset)))) - ()) - - -; Macros - -(dnmi ldw-base-0 "load double word - implied base 0" (MACH2000 EVEN-REG-NUM LOAD-DELAY USES-RT USES-RS NO-DIS) - "ldw $rt,$lo16" - (emit ldw rt lo16 (base 0)) -) - -(dnmi sdw-base-0 "store double word - implied base 0" (MACH2000 EVEN-REG-NUM USES-RT NO-DIS) - "sdw $rt,$lo16" - (emit sdw rt lo16 (base 0)) -) - - - - - - diff --git a/binutils-2.24/cpu/lm32.cpu b/binutils-2.24/cpu/lm32.cpu deleted file mode 100644 index 83c839f3..00000000 --- a/binutils-2.24/cpu/lm32.cpu +++ /dev/null @@ -1,934 +0,0 @@ -; Lattice Mico32 CPU description. -*- Scheme -*- -; Copyright 2008-2013 Free Software Foundation, Inc. -; Contributed by Jon Beniston <jon@beniston.com> -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -(define-arch - (name lm32) ; name of cpu family - (comment "Lattice Mico32") - (default-alignment aligned) - (insn-lsb0? #t) - (machs lm32) - (isas lm32) -) - - -; Instruction sets. - -(define-isa - (name lm32) - (comment "Lattice Mico32 ISA") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) - (decode-assist (31 30 29 28 27 26)) -) - - -; Cpu family definitions. - -(define-cpu - ; cpu names must be distinct from the architecture name and machine name - (name lm32bf) - (comment "Lattice Mico32 CPU") - (endian big) - (word-bitsize 32) -) - -(define-mach - (name lm32) - (comment "Lattice Mico32 MACH") - (cpu lm32bf) -) - -(define-model - (name lm32) - (comment "Lattice Mico32 reference implementation") - (mach lm32) - (unit u-exec "Execution unit" () - 1 1 () () () ()) -) - - -; Hardware elements. - -(dnh h-pc "Program counter" (PC) (pc) () () ()) - -(dnh h-gr "General purpose registers" - () - (register SI (32)) - (keyword "" ( - (gp 26) (fp 27) (sp 28) (ra 29) (ea 30) (ba 31) - (r0 0) (r1 1) (r2 2) (r3 3) - (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) - (r12 12) (r13 13) (r14 14) (r15 15) - (r16 16) (r17 17) (r18 18) (r19 19) - (r20 20) (r21 21) (r22 22) (r23 23) - (r24 24) (r25 25) (r26 26) (r27 27) - (r28 28) (r29 29) (r30 30) (r31 31) - ) - ) - () () -) - -(dnh h-csr "Control and status registers" - () - (register SI (32)) - (keyword "" ( - (IE 0) (IM 1) (IP 2) - (ICC 3) (DCC 4) - (CC 5) - (CFG 6) - (EBA 7) - (DC 8) - (DEBA 9) - (CFG2 10) - (JTX 14) (JRX 15) - (BP0 16) (BP1 17) (BP2 18) (BP3 19) - (WP0 24) (WP1 25) (WP2 26) (WP3 27) - (PSW 29) (TLBVADDR 30) (TLBPADDR 31) (TLBBADVADDR 31) - ) - ) - () () -) - - -; Instruction fields. - -(dnf f-opcode "opcode field" () 31 6) -(dnf f-r0 "register index 0 field" () 25 5) -(dnf f-r1 "register index 1 field" () 20 5) -(dnf f-r2 "register index 2 field" () 15 5) -(dnf f-resv0 "reserved" (RESERVED) 10 11) -(dnf f-shift "shift amount field" () 4 5) -(df f-imm "signed immediate field" () 15 16 INT #f #f) -(dnf f-uimm "unsigned immediate field" () 15 16) -(dnf f-csr "csr field" () 25 5) -(dnf f-user "user defined field" () 10 11) -(dnf f-exception "exception field" () 25 26) - -(df f-branch "branch offset field" (PCREL-ADDR) 15 16 INT - ((value pc) (sra SI (sub SI value pc) 2)) - ((value pc) (add SI pc (sra SI (sll SI value 16) 14))) -) -(df f-call "call offset field" (PCREL-ADDR) 25 26 INT - ((value pc) (sra SI (sub SI value pc) 2)) - ((value pc) (add SI pc (sra SI (sll SI value 6) 4))) -) - - -; Operands. - -(dnop r0 "register 0" () h-gr f-r0) -(dnop r1 "register 1" () h-gr f-r1) -(dnop r2 "register 2" () h-gr f-r2) -(dnop shift "shift amout" () h-uint f-shift) -(dnop imm "signed immediate" () h-sint f-imm) -(dnop uimm "unsigned immediate" () h-uint f-uimm) -(dnop branch "branch offset" () h-iaddr f-branch) -(dnop call "call offset" () h-iaddr f-call) -(dnop csr "csr" () h-csr f-csr) -(dnop user "user" () h-uint f-user) -(dnop exception "exception" () h-uint f-exception) - -(define-operand - (name hi16) - (comment "high 16-bit immediate") - (attrs) - (type h-uint) - (index f-uimm) - (handlers (parse "hi16")) -) - -(define-operand - (name lo16) - (comment "low 16-bit immediate") - (attrs) - (type h-uint) - (index f-uimm) - (handlers (parse "lo16")) -) - -(define-operand - (name gp16) - (comment "gp relative 16-bit immediate") - (attrs) - (type h-sint) - (index f-imm) - (handlers (parse "gp16")) -) - -(define-operand - (name got16) - (comment "got 16-bit immediate") - (attrs) - (type h-sint) - (index f-imm) - (handlers (parse "got16")) -) - -(define-operand - (name gotoffhi16) - (comment "got offset high 16-bit immediate") - (attrs) - (type h-sint) - (index f-imm) - (handlers (parse "gotoff_hi16")) -) - -(define-operand - (name gotofflo16) - (comment "got offset low 16-bit immediate") - (attrs) - (type h-sint) - (index f-imm) - (handlers (parse "gotoff_lo16")) -) - - -; Enumerations. - -(define-normal-insn-enum - opcodes "opcodes" () OP_ f-opcode - (("ADD" 45) - ("ADDI" 13) - ("AND" 40) - ("ANDI" 8) - ("ANDHI" 24) - ("B" 48) - ("BI" 56) - ("BE" 17) - ("BG" 18) - ("BGE" 19) - ("BGEU" 20) - ("BGU" 21) - ("BNE" 23) - ("CALL" 54) - ("CALLI" 62) - ("CMPE" 57) - ("CMPEI" 25) - ("CMPG" 58) - ("CMPGI" 26) - ("CMPGE" 59) - ("CMPGEI" 27) - ("CMPGEU" 60) - ("CMPGEUI" 28) - ("CMPGU" 61) - ("CMPGUI" 29) - ("CMPNE" 63) - ("CMPNEI" 31) - ("DIVU" 35) - ("LB" 4) - ("LBU" 16) - ("LH" 7) - ("LHU" 11) - ("LW" 10) - ("MODU" 49) - ("MUL" 34) - ("MULI" 2) - ("NOR" 33) - ("NORI" 1) - ("OR" 46) - ("ORI" 14) - ("ORHI" 30) - ("RAISE" 43) - ("RCSR" 36) - ("SB" 12) - ("SEXTB" 44) - ("SEXTH" 55) - ("SH" 3) - ("SL" 47) - ("SLI" 15) - ("SR" 37) - ("SRI" 5) - ("SRU" 32) - ("SRUI" 0) - ("SUB" 50) - ("SW" 22) - ("USER" 51) - ("WCSR" 52) - ("XNOR" 41) - ("XNORI" 9) - ("XOR" 38) - ("XORI" 6) - ) -) - - -; Instructions. Note: Reg-reg must come before reg-imm. - -(dni add "add" () - "add $r2,$r0,$r1" - (+ OP_ADD r0 r1 r2 (f-resv0 0)) - (set r2 (add r0 r1)) - () -) - -(dni addi "add immediate" () - "addi $r1,$r0,$imm" - (+ OP_ADDI r0 r1 imm) - (set r1 (add r0 (ext SI (trunc HI imm)))) - () -) - -(dni and "and" () - "and $r2,$r0,$r1" - (+ OP_AND r0 r1 r2 (f-resv0 0)) - (set r2 (and r0 r1)) - () -) - -(dni andi "and immediate" () - "andi $r1,$r0,$uimm" - (+ OP_ANDI r0 r1 uimm) - (set r1 (and r0 (zext SI uimm))) - () -) - -(dni andhii "and high immediate" () - "andhi $r1,$r0,$hi16" - (+ OP_ANDHI r0 r1 hi16) - (set r1 (and r0 (sll SI hi16 16))) - () -) - -(dni b "branch" () - "b $r0" - (+ OP_B r0 (f-r1 0) (f-r2 0) (f-resv0 0)) - (set pc (c-call USI "@cpu@_b_insn" r0 f-r0)) - () -) - -(dni bi "branch immediate" () - "bi $call" - (+ OP_BI call) - (set pc (ext SI call)) - () -) - -(dni be "branch equal" () - "be $r0,$r1,$branch" - (+ OP_BE r0 r1 branch) - (if (eq r0 r1) - (set pc branch) - ) - () -) - -(dni bg "branch greater" () - "bg $r0,$r1,$branch" - (+ OP_BG r0 r1 branch) - (if (gt r0 r1) - (set pc branch) - ) - () -) - -(dni bge "branch greater or equal" () - "bge $r0,$r1,$branch" - (+ OP_BGE r0 r1 branch) - (if (ge r0 r1) - (set pc branch) - ) - () -) - -(dni bgeu "branch greater or equal unsigned" () - "bgeu $r0,$r1,$branch" - (+ OP_BGEU r0 r1 branch) - (if (geu r0 r1) - (set pc branch) - ) - () -) - -(dni bgu "branch greater unsigned" () - "bgu $r0,$r1,$branch" - (+ OP_BGU r0 r1 branch) - (if (gtu r0 r1) - (set pc branch) - ) - () -) - -(dni bne "branch not equal" () - "bne $r0,$r1,$branch" - (+ OP_BNE r0 r1 branch) - (if (ne r0 r1) - (set pc branch) - ) - () -) - -(dni call "call" () - "call $r0" - (+ OP_CALL r0 (f-r1 0) (f-r2 0) (f-resv0 0)) - (sequence () - (set (reg h-gr 29) (add pc 4)) - (set pc r0) - ) - () -) - -(dni calli "call immediate" () - "calli $call" - (+ OP_CALLI call) - (sequence () - (set (reg h-gr 29) (add pc 4)) - (set pc (ext SI call)) - ) - () -) - -(dni cmpe "compare equal" () - "cmpe $r2,$r0,$r1" - (+ OP_CMPE r0 r1 r2 (f-resv0 0)) - (set r2 (eq SI r0 r1)) - () -) - -(dni cmpei "compare equal immediate" () - "cmpei $r1,$r0,$imm" - (+ OP_CMPEI r0 r1 imm) - (set r1 (eq SI r0 (ext SI (trunc HI imm)))) - () -) - -(dni cmpg "compare greater than" () - "cmpg $r2,$r0,$r1" - (+ OP_CMPG r0 r1 r2 (f-resv0 0)) - (set r2 (gt SI r0 r1)) - () -) - -(dni cmpgi "compare greater than immediate" () - "cmpgi $r1,$r0,$imm" - (+ OP_CMPGI r0 r1 imm) - (set r1 (gt SI r0 (ext SI (trunc HI imm)))) - () -) - -(dni cmpge "compare greater or equal" () - "cmpge $r2,$r0,$r1" - (+ OP_CMPGE r0 r1 r2 (f-resv0 0)) - (set r2 (ge SI r0 r1)) - () -) - -(dni cmpgei "compare greater or equal immediate" () - "cmpgei $r1,$r0,$imm" - (+ OP_CMPGEI r0 r1 imm) - (set r1 (ge SI r0 (ext SI (trunc HI imm)))) - () -) - -(dni cmpgeu "compare greater or equal unsigned" () - "cmpgeu $r2,$r0,$r1" - (+ OP_CMPGEU r0 r1 r2 (f-resv0 0)) - (set r2 (geu SI r0 r1)) - () -) - -(dni cmpgeui "compare greater or equal unsigned immediate" () - "cmpgeui $r1,$r0,$uimm" - (+ OP_CMPGEUI r0 r1 uimm) - (set r1 (geu SI r0 (zext SI uimm))) - () -) - -(dni cmpgu "compare greater than unsigned" () - "cmpgu $r2,$r0,$r1" - (+ OP_CMPGU r0 r1 r2 (f-resv0 0)) - (set r2 (gtu SI r0 r1)) - () -) - -(dni cmpgui "compare greater than unsigned immediate" () - "cmpgui $r1,$r0,$uimm" - (+ OP_CMPGUI r0 r1 uimm) - (set r1 (gtu SI r0 (zext SI uimm))) - () -) - -(dni cmpne "compare not equal" () - "cmpne $r2,$r0,$r1" - (+ OP_CMPNE r0 r1 r2 (f-resv0 0)) - (set r2 (ne SI r0 r1)) - () -) - -(dni cmpnei "compare not equal immediate" () - "cmpnei $r1,$r0,$imm" - (+ OP_CMPNEI r0 r1 imm) - (set r1 (ne SI r0 (ext SI (trunc HI imm)))) - () -) - -(dni divu "unsigned divide" () - "divu $r2,$r0,$r1" - (+ OP_DIVU r0 r1 r2 (f-resv0 0)) - (set pc (c-call USI "@cpu@_divu_insn" pc f-r0 f-r1 f-r2)) - () -) - -(dni lb "load byte" () - "lb $r1,($r0+$imm)" - (+ OP_LB r0 r1 imm) - (set r1 (ext SI (mem QI (add r0 (ext SI (trunc HI imm)))))) - () -) - -(dni lbu "load byte unsigned" () - "lbu $r1,($r0+$imm)" - (+ OP_LBU r0 r1 imm) - (set r1 (zext SI (mem QI (add r0 (ext SI (trunc HI imm)))))) - () -) - -(dni lh "load halfword" () - "lh $r1,($r0+$imm)" - (+ OP_LH r0 r1 imm) - (set r1 (ext SI (mem HI (add r0 (ext SI (trunc HI imm)))))) - () -) - -(dni lhu "load halfword unsigned" () - "lhu $r1,($r0+$imm)" - (+ OP_LHU r0 r1 imm) - (set r1 (zext SI (mem HI (add r0 (ext SI (trunc HI imm)))))) - () -) - -(dni lw "load word" () - "lw $r1,($r0+$imm)" - (+ OP_LW r0 r1 imm) - (set r1 (mem SI (add r0 (ext SI (trunc HI imm))))) - () -) - -(dni modu "unsigned modulus" () - "modu $r2,$r0,$r1" - (+ OP_MODU r0 r1 r2 (f-resv0 0)) - (set pc (c-call USI "@cpu@_modu_insn" pc f-r0 f-r1 f-r2)) - () -) - -(dni mul "mulitply" () - "mul $r2,$r0,$r1" - (+ OP_MUL r0 r1 r2 (f-resv0 0)) - (set r2 (mul r0 r1)) - () -) - -(dni muli "multiply immediate" () - "muli $r1,$r0,$imm" - (+ OP_MULI r0 r1 imm) - (set r1 (mul r0 (ext SI (trunc HI imm)))) - () -) - -(dni nor "nor" () - "nor $r2,$r0,$r1" - (+ OP_NOR r0 r1 r2 (f-resv0 0)) - (set r2 (inv (or r0 r1))) - () -) - -(dni nori "nor immediate" () - "nori $r1,$r0,$uimm" - (+ OP_NORI r0 r1 uimm) - (set r1 (inv (or r0 (zext SI uimm)))) - () -) - -(dni or "or" () - "or $r2,$r0,$r1" - (+ OP_OR r0 r1 r2 (f-resv0 0)) - (set r2 (or r0 r1)) - () -) - -(dni ori "or immediate" () - "ori $r1,$r0,$lo16" - (+ OP_ORI r0 r1 lo16) - (set r1 (or r0 (zext SI lo16))) - () -) - -(dni orhii "or high immediate" () - "orhi $r1,$r0,$hi16" - (+ OP_ORHI r0 r1 hi16) - (set r1 (or r0 (sll SI hi16 16))) - () -) - -(dni rcsr "read control or status register" () - "rcsr $r2,$csr" - (+ OP_RCSR csr (f-r1 0) r2 (f-resv0 0)) - (set r2 csr) - () -) - -(dni sb "store byte" () - "sb ($r0+$imm),$r1" - (+ OP_SB r0 r1 imm) - (set (mem QI (add r0 (ext SI (trunc HI imm)))) r1) - () -) - -(dni sextb "sign extend byte" () - "sextb $r2,$r0" - (+ OP_SEXTB r0 (f-r1 0) r2 (f-resv0 0)) - (set r2 (ext SI (trunc QI r0))) - () -) - -(dni sexth "sign extend half-word" () - "sexth $r2,$r0" - (+ OP_SEXTH r0 (f-r1 0) r2 (f-resv0 0)) - (set r2 (ext SI (trunc HI r0))) - () -) - -(dni sh "store halfword" () - "sh ($r0+$imm),$r1" - (+ OP_SH r0 r1 imm) - (set (mem HI (add r0 (ext SI (trunc HI imm)))) r1) - () -) - -(dni sl "shift left" () - "sl $r2,$r0,$r1" - (+ OP_SL r0 r1 r2 (f-resv0 0)) - (set r2 (sll SI r0 r1)) - () -) - -(dni sli "shift left immediate" () - "sli $r1,$r0,$imm" - (+ OP_SLI r0 r1 imm) - (set r1 (sll SI r0 imm)) - () -) - -(dni sr "shift right" () - "sr $r2,$r0,$r1" - (+ OP_SR r0 r1 r2 (f-resv0 0)) - (set r2 (sra SI r0 r1)) - () -) - -(dni sri "shift right immediate" () - "sri $r1,$r0,$imm" - (+ OP_SRI r0 r1 imm) - (set r1 (sra SI r0 imm)) - () -) - -(dni sru "shift right unsigned" () - "sru $r2,$r0,$r1" - (+ OP_SRU r0 r1 r2 (f-resv0 0)) - (set r2 (srl SI r0 r1)) - () -) - -(dni srui "shift right unsigned immediate" () - "srui $r1,$r0,$imm" - (+ OP_SRUI r0 r1 imm) - (set r1 (srl SI r0 imm)) - () -) - -(dni sub "subtract" () - "sub $r2,$r0,$r1" - (+ OP_SUB r0 r1 r2 (f-resv0 0)) - (set r2 (sub r0 r1)) - () -) - -(dni sw "store word" () - "sw ($r0+$imm),$r1" - (+ OP_SW r0 r1 imm) - (set (mem SI (add r0 (ext SI (trunc HI imm)))) r1) - () -) - -(dni user "user defined instruction" () - "user $r2,$r0,$r1,$user" - (+ OP_USER r0 r1 r2 user) - (set r2 (c-call SI "@cpu@_user_insn" r0 r1 user)) - () -) - -(dni wcsr "write control or status register" () - "wcsr $csr,$r1" - (+ OP_WCSR csr r1 (f-r2 0) (f-resv0 0)) - (c-call VOID "@cpu@_wcsr_insn" f-csr r1) - () -) - -(dni xor "xor" () - "xor $r2,$r0,$r1" - (+ OP_XOR r0 r1 r2 (f-resv0 0)) - (set r2 (xor r0 r1)) - () -) - -(dni xori "xor immediate" () - "xori $r1,$r0,$uimm" - (+ OP_XORI r0 r1 uimm) - (set r1 (xor r0 (zext SI uimm))) - () -) - -(dni xnor "xnor" () - "xnor $r2,$r0,$r1" - (+ OP_XNOR r0 r1 r2 (f-resv0 0)) - (set r2 (inv (xor r0 r1))) - () -) - -(dni xnori "xnor immediate" () - "xnori $r1,$r0,$uimm" - (+ OP_XNORI r0 r1 uimm) - (set r1 (inv (xor r0 (zext SI uimm)))) - () -) - -; Pseudo instructions - -(dni break "breakpoint" () - "break" - (+ OP_RAISE (f-exception 2)) - (set pc (c-call USI "@cpu@_break_insn" pc)) - () -) - -(dni scall "system call" () - "scall" - (+ OP_RAISE (f-exception 7)) - (set pc (c-call USI "@cpu@_scall_insn" pc)) - () -) - -(dni bret "return from breakpoint" (ALIAS) - "bret" - (+ OP_B (f-r0 31) (f-r1 0) (f-r2 0) (f-resv0 0)) - (set pc (c-call USI "@cpu@_bret_insn" r0)) - () -) - -(dni eret "return from exception" (ALIAS) - "eret" - (+ OP_B (f-r0 30) (f-r1 0) (f-r2 0) (f-resv0 0)) - (set pc (c-call USI "@cpu@_eret_insn" r0)) - () -) - -(dni ret "return" (ALIAS) - "ret" - (+ OP_B (f-r0 29) (f-r1 0) (f-r2 0) (f-resv0 0)) - (set pc r0) - () -) - -(dni mv "move" (ALIAS) - "mv $r2,$r0" - (+ OP_OR r0 (f-r1 0) r2 (f-resv0 0)) - (set r2 r0) - () -) - -(dni mvi "move immediate" (ALIAS) - "mvi $r1,$imm" - (+ OP_ADDI (f-r0 0) r1 imm) - (set r1 (add r0 (ext SI (trunc HI imm)))) - () -) - -(dni mvui "move unsigned immediate" (ALIAS) - "mvu $r1,$lo16" - (+ OP_ORI (f-r0 0) r1 lo16) - (set r1 (zext SI lo16)) - () -) - -(dni mvhi "move high immediate" (ALIAS) - "mvhi $r1,$hi16" - (+ OP_ORHI (f-r0 0) r1 hi16) - (set r1 (or r0 (sll SI hi16 16))) - () -) - -(dni mva "move address" (ALIAS) - "mva $r1,$gp16" - (+ OP_ADDI (f-r0 26) r1 gp16) - (set r1 (add r0 (ext SI (trunc HI gp16)))) - () -) - -(dni not "not" (ALIAS) - "not $r2,$r0" - (+ OP_XNOR r0 (f-r1 0) r2 (f-resv0 0)) - (set r2 (inv r0)) - () -) - -(dni nop "nop" (ALIAS) - "nop" - (+ OP_ADDI (f-r0 0) (f-r1 0) (f-imm 0)) - (set r0 r0) - () -) - -(dni lbgprel "load byte gp relative" (ALIAS) - "lb $r1,$gp16" - (+ OP_LB (f-r0 26) r1 gp16) - (set r1 (ext SI (mem QI (add r0 (ext SI (trunc HI gp16)))))) - () -) - -(dni lbugprel "load byte unsigned gp relative" (ALIAS) - "lbu $r1,$gp16" - (+ OP_LBU (f-r0 26) r1 gp16) - (set r1 (zext SI (mem QI (add r0 (ext SI (trunc HI gp16)))))) - () -) - -(dni lhgprel "load halfword gp relative" (ALIAS) - "lh $r1,$gp16" - (+ OP_LH (f-r0 26) r1 gp16) - (set r1 (ext SI (mem HI (add r0 (ext SI (trunc HI gp16)))))) - () -) - -(dni lhugprel "load halfword unsigned gp relative" (ALIAS) - "lhu $r1,$gp16" - (+ OP_LHU (f-r0 26) r1 gp16) - (set r1 (zext SI (mem HI (add r0 (ext SI (trunc HI gp16)))))) - () -) - -(dni lwgprel "load word gp relative" (ALIAS) - "lw $r1,$gp16" - (+ OP_LW (f-r0 26) r1 gp16) - (set r1 (mem SI (add r0 (ext SI (trunc HI gp16))))) - () -) - -(dni sbgprel "store byte gp relative" (ALIAS) - "sb $gp16,$r1" - (+ OP_SB (f-r0 26) r1 gp16) - (set (mem QI (add r0 (ext SI (trunc HI gp16)))) r1) - () -) - -(dni shgprel "store halfword gp relative" (ALIAS) - "sh $gp16,$r1" - (+ OP_SH (f-r0 26) r1 gp16) - (set (mem HI (add r0 (ext SI (trunc HI gp16)))) r1) - () -) - -(dni swgprel "store word gp relative" (ALIAS) - "sw $gp16,$r1" - (+ OP_SW (f-r0 26) r1 gp16) - (set (mem SI (add r0 (ext SI (trunc HI gp16)))) r1) - () -) - -(dni lwgotrel "load word got relative" (ALIAS) - "lw $r1,(gp+$got16)" - (+ OP_LW (f-r0 26) r1 got16) - (set r1 (mem SI (add r0 (ext SI (trunc HI got16))))) - () -) - -(dni orhigotoffi "or high got offset immediate" (ALIAS) - "orhi $r1,$r0,$gotoffhi16" - (+ OP_ORHI r0 r1 gotoffhi16) - (set r1 (or r0 (sll SI gotoffhi16 16))) - () -) - -(dni addgotoff "add got offset" (ALIAS) - "addi $r1,$r0,$gotofflo16" - (+ OP_ADDI r0 r1 gotofflo16) - (set r1 (add r0 (ext SI (trunc HI gotofflo16)))) - () -) - -(dni swgotoff "store word got offset" (ALIAS) - "sw ($r0+$gotofflo16),$r1" - (+ OP_SW r0 r1 gotofflo16) - (set (mem SI (add r0 (ext SI (trunc HI gotofflo16)))) r1) - () -) - -(dni lwgotoff "load word got offset" (ALIAS) - "lw $r1,($r0+$gotofflo16)" - (+ OP_LW r0 r1 gotofflo16) - (set r1 (mem SI (add r0 (ext SI (trunc HI gotofflo16))))) - () -) - -(dni shgotoff "store half word got offset" (ALIAS) - "sh ($r0+$gotofflo16),$r1" - (+ OP_SH r0 r1 gotofflo16) - (set (mem HI (add r0 (ext SI (trunc HI gotofflo16)))) r1) - () -) - -(dni lhgotoff "load half word got offset" (ALIAS) - "lh $r1,($r0+$gotofflo16)" - (+ OP_LH r0 r1 gotofflo16) - (set r1 (ext SI (mem HI (add r0 (ext SI (trunc HI gotofflo16)))))) - () -) - -(dni lhugotoff "load half word got offset unsigned" (ALIAS) - "lhu $r1,($r0+$gotofflo16)" - (+ OP_LHU r0 r1 gotofflo16) - (set r1 (zext SI (mem HI (add r0 (ext SI (trunc HI gotofflo16)))))) - () -) - -(dni sbgotoff "store byte got offset" (ALIAS) - "sb ($r0+$gotofflo16),$r1" - (+ OP_SB r0 r1 gotofflo16) - (set (mem QI (add r0 (ext SI (trunc HI gotofflo16)))) r1) - () -) - -(dni lbgotoff "load byte got offset" (ALIAS) - "lb $r1,($r0+$gotofflo16)" - (+ OP_LB r0 r1 gotofflo16) - (set r1 (ext SI (mem QI (add r0 (ext SI (trunc HI gotofflo16)))))) - () -) - -(dni lbugotoff "load byte got offset unsigned" (ALIAS) - "lbu $r1,($r0+$gotofflo16)" - (+ OP_LBU r0 r1 gotofflo16) - (set r1 (zext SI (mem QI (add r0 (ext SI (trunc HI gotofflo16)))))) - () -) diff --git a/binutils-2.24/cpu/lm32.opc b/binutils-2.24/cpu/lm32.opc deleted file mode 100644 index 3a814c2e..00000000 --- a/binutils-2.24/cpu/lm32.opc +++ /dev/null @@ -1,235 +0,0 @@ -/* Lattice Mico32 opcode support. -*- C -*- - Copyright 2008, 2009 Free Software Foundation, Inc. - Contributed by Jon Beniston <jon@beniston.com> - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* -- opc.h */ - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -#define CGEN_DIS_HASH_SIZE 64 -#define CGEN_DIS_HASH(buf,value) ((value >> 26) & 0x3f) - -/* -- asm.c */ - -/* Handle signed/unsigned literal. */ - -static const char * -parse_imm (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg == NULL) - { - unsigned long x = value & 0xFFFF0000; - if (x != 0 && x != 0xFFFF0000) - errmsg = _("immediate value out of range"); - else - *valuep = (value & 0xFFFF); - } - return errmsg; -} - -/* Handle hi() */ - -static const char * -parse_hi16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (strncasecmp (*strp, "hi(", 3) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma value; - const char *errmsg; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - &result_type, &value); - if (**strp != ')') - return _("missing `)'"); - - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = (value >> 16) & 0xffff; - *valuep = value; - - return errmsg; - } - - return parse_imm (cd, strp, opindex, valuep); -} - -/* Handle lo() */ - -static const char * -parse_lo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (strncasecmp (*strp, "lo(", 3) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - &result_type, &value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return parse_imm (cd, strp, opindex, valuep); -} - -/* Handle gp() */ - -static const char * -parse_gp16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - if (strncasecmp (*strp, "gp(", 3) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_GPREL16, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return _("expecting gp relative address: gp(symbol)"); -} - -/* Handle got() */ - -static const char * -parse_got16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - if (strncasecmp (*strp, "got(", 4) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_16_GOT, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return _("expecting got relative address: got(symbol)"); -} - -/* Handle gotoffhi16() */ - -static const char * -parse_gotoff_hi16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - if (strncasecmp (*strp, "gotoffhi16(", 11) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 11; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_GOTOFF_HI16, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return _("expecting got relative address: gotoffhi16(symbol)"); -} - -/* Handle gotofflo16() */ - -static const char * -parse_gotoff_lo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - if (strncasecmp (*strp, "gotofflo16(", 11) == 0) - { - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - *strp += 11; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LM32_GOTOFF_LO16, - &result_type, &value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return _("expecting got relative address: gotofflo16(symbol)"); -} diff --git a/binutils-2.24/cpu/m32c.cpu b/binutils-2.24/cpu/m32c.cpu deleted file mode 100644 index bcc36161..00000000 --- a/binutils-2.24/cpu/m32c.cpu +++ /dev/null @@ -1,10521 +0,0 @@ -; Renesas M32C CPU description. -*- Scheme -*- -; -; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Renesas. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -(define-arch - (name m32c) - (comment "Renesas M32C") - (default-alignment forced) - (insn-lsb0? #f) - (machs m16c m32c) - (isas m16c m32c) -) - -(define-isa - (name m16c) - - (default-insn-bitsize 32) - - ; Number of bytes of insn we can initially fetch. - (base-insn-bitsize 32) - - ; Used in computing bit numbers. - (default-insn-word-bitsize 32) - - (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. - - ; fetches 1 insn at a time. - (liw-insns 1) - - ; executes 1 insn at a time. - (parallel-insns 1) - ) - -(define-isa - (name m32c) - - (default-insn-bitsize 32) - - ; Number of bytes of insn we can initially fetch. - (base-insn-bitsize 32) - - ; Used in computing bit numbers. - (default-insn-word-bitsize 32) - - (decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by. - - ; fetches 1 insn at a time. - (liw-insns 1) - - ; executes 1 insn at a time. - (parallel-insns 1) - ) - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name m16cbf) - (comment "Renesas M16C base family") - (insn-endian big) - (data-endian little) - (word-bitsize 16) -) - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name m32cbf) - (comment "Renesas M32C base family") - (insn-endian big) - (data-endian little) - (word-bitsize 16) -) - -(define-mach - (name m16c) - (comment "Generic M16C cpu") - (cpu m32cbf) -) - -(define-mach - (name m32c) - (comment "Generic M32C cpu") - (cpu m32cbf) -) - -; Model descriptions. - -(define-model - (name m16c) - (comment "m16c") (attrs) - (mach m16c) - - ; `state' is a list of variables for recording model state - ; (state) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -(define-model - (name m32c) - (comment "m32c") (attrs) - (mach m32c) - - ; `state' is a list of variables for recording model state - ; (state) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -(define-attr - (type enum) - (name RL_TYPE) - (values NONE JUMP 1ADDR 2ADDR) - (default NONE) - ) - -; Macros to simplify MACH attribute specification. - -(define-pmacro all-isas () (ISA m16c,m32c)) -(define-pmacro m16c-isa () (ISA m16c)) -(define-pmacro m32c-isa () (ISA m32c)) - -(define-pmacro MACH16 (MACH m16c)) -(define-pmacro MACH32 (MACH m32c)) - -(define-pmacro (machine size) - (MACH (.sym m size c)) (ISA (.sym m size c))) - -(define-pmacro RL_JUMP (RL_TYPE JUMP)) -(define-pmacro RL_1ADDR (RL_TYPE 1ADDR)) -(define-pmacro RL_2ADDR (RL_TYPE 2ADDR)) - - -;============================================================= -; Fields -;------------------------------------------------------------- -; Main opcodes -; -(dnf f-0-1 "opcode" (all-isas) 0 1) -(dnf f-0-2 "opcode" (all-isas) 0 2) -(dnf f-0-3 "opcode" (all-isas) 0 3) -(dnf f-0-4 "opcode" (all-isas) 0 4) -(dnf f-1-3 "opcode" (all-isas) 1 3) -(dnf f-2-2 "opcode" (all-isas) 2 2) -(dnf f-3-4 "opcode" (all-isas) 3 4) -(dnf f-3-1 "opcode" (all-isas) 3 1) -(dnf f-4-1 "opcode" (all-isas) 4 1) -(dnf f-4-3 "opcode" (all-isas) 4 3) -(dnf f-4-4 "opcode" (all-isas) 4 4) -(dnf f-4-6 "opcode" (all-isas) 4 6) -(dnf f-5-1 "opcode" (all-isas) 5 1) -(dnf f-5-3 "opcode" (all-isas) 5 3) -(dnf f-6-2 "opcode" (all-isas) 6 2) -(dnf f-7-1 "opcode" (all-isas) 7 1) -(dnf f-8-1 "opcode" (all-isas) 8 1) -(dnf f-8-2 "opcode" (all-isas) 8 2) -(dnf f-8-3 "opcode" (all-isas) 8 3) -(dnf f-8-4 "opcode" (all-isas) 8 4) -(dnf f-8-8 "opcode" (all-isas) 8 8) -(dnf f-9-3 "opcode" (all-isas) 9 3) -(dnf f-9-1 "opcode" (all-isas) 9 1) -(dnf f-10-1 "opcode" (all-isas) 10 1) -(dnf f-10-2 "opcode" (all-isas) 10 2) -(dnf f-10-3 "opcode" (all-isas) 10 3) -(dnf f-11-1 "opcode" (all-isas) 11 1) -(dnf f-12-1 "opcode" (all-isas) 12 1) -(dnf f-12-2 "opcode" (all-isas) 12 2) -(dnf f-12-3 "opcode" (all-isas) 12 3) -(dnf f-12-4 "opcode" (all-isas) 12 4) -(dnf f-12-6 "opcode" (all-isas) 12 6) -(dnf f-13-3 "opcode" (all-isas) 13 3) -(dnf f-14-1 "opcode" (all-isas) 14 1) -(dnf f-14-2 "opcode" (all-isas) 14 2) -(dnf f-15-1 "opcode" (all-isas) 15 1) -(dnf f-16-1 "opcode" (all-isas) 16 1) -(dnf f-16-2 "opcode" (all-isas) 16 2) -(dnf f-16-4 "opcode" (all-isas) 16 4) -(dnf f-16-8 "opcode" (all-isas) 16 8) -(dnf f-18-1 "opcode" (all-isas) 18 1) -(dnf f-18-2 "opcode" (all-isas) 18 2) -(dnf f-18-3 "opcode" (all-isas) 18 3) -(dnf f-20-1 "opcode" (all-isas) 20 1) -(dnf f-20-3 "opcode" (all-isas) 20 3) -(dnf f-20-2 "opcode" (all-isas) 20 2) -(dnf f-20-4 "opcode" (all-isas) 20 4) -(dnf f-21-3 "opcode" (all-isas) 21 3) -(dnf f-24-2 "opcode" (all-isas) 24 2) -(dnf f-24-8 "opcode" (all-isas) 24 8) -(dnf f-32-16 "opcode" (all-isas) 32 16) - -;------------------------------------------------------------- -; Registers -;------------------------------------------------------------- - -(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2) -(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1) - -(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1) -(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1) - -; QI mode gr encoding for m32c is different than for m16c. The hardware -; is indexed using the m16c encoding, so perform the transformation here. -; register m16c m32c -; ---------------------- -; r0l 00'b 10'b -; r0h 01'b 00'b -; r1l 10'b 11'b -; r1h 11'b 01'b -(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert - ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract -) -; QI mode gr encoding for m32c is different than for m16c. The hardware -; is indexed using the m16c encoding, so perform the transformation here. -; register m16c m32c -; ---------------------- -; r0l 00'b 10'b -; r0h 01'b 00'b -; r1l 10'b 11'b -; r1h 11'b 01'b -(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert - ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract -) -; HI mode gr encoding for m32c is different than for m16c. The hardware -; is indexed using the m16c encoding, so perform the transformation here. -; register m16c m32c -; ---------------------- -; r0 00'b 10'b -; r1 01'b 11'b -; r2 10'b 00'b -; r3 11'b 01'b -(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT - ((value pc) (mod USI (add value 2) 4)) ; insert - ((value pc) (mod USI (add value 2) 4)) ; extract -) - -; HI mode gr encoding for m32c is different than for m16c. The hardware -; is indexed using the m16c encoding, so perform the transformation here. -; register m16c m32c -; ---------------------- -; r0 00'b 10'b -; r1 01'b 11'b -; r2 10'b 00'b -; r3 11'b 01'b -(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT - ((value pc) (mod USI (add value 2) 4)) ; insert - ((value pc) (mod USI (add value 2) 4)) ; extract -) - -; SI mode gr encoding for m32c is as follows: -; register encoding index -; ------------------------- -; r2r0 10'b 0 -; r3r1 11'b 1 -(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT - ((value pc) (add USI value 2)) ; insert - ((value pc) (sub USI value 2)) ; extract -) -(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT - ((value pc) (add USI value 2)) ; insert - ((value pc) (sub USI value 2)) ; extract -) - -(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1) - -(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2) -(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1) -(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1) - -(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1) -(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1) - -(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1) -(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1) - -; QI mode gr encoding for m32c is different than for m16c. The hardware -; is indexed using the m16c encoding, so perform the transformation here. -; register m16c m32c -; ---------------------- -; r0l 00'b 10'b -; r0h 01'b 00'b -; r1l 10'b 11'b -; r1h 11'b 01'b -(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert - ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract -) -(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert - ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract -) -; HI mode gr encoding for m32c is different than for m16c. The hardware -; is indexed using the m16c encoding, so perform the transformation here. -; register m16c m32c -; ---------------------- -; r0 00'b 10'b -; r1 01'b 11'b -; r2 10'b 00'b -; r3 11'b 01'b -(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT - ((value pc) (mod USI (add value 2) 4)) ; insert - ((value pc) (mod USI (add value 2) 4)) ; extract -) -(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT - ((value pc) (mod USI (add value 2) 4)) ; insert - ((value pc) (mod USI (add value 2) 4)) ; extract -) -; SI mode gr encoding for m32c is as follows: -; register encoding index -; ------------------------- -; r2r0 10'b 0 -; r3r1 11'b 1 -(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT - ((value pc) (add USI value 2)) ; insert - ((value pc) (sub USI value 2)) ; extract -) -(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT - ((value pc) (add USI value 2)) ; insert - ((value pc) (sub USI value 2)) ; extract -) - -(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1) - -;------------------------------------------------------------- -; Immediates embedded in the base insn -;------------------------------------------------------------- - -(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f) -(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f) -(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f) -(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f) - -(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT - ((value pc) (sub USI value 1)) ; insert - ((value pc) (add USI value 1)) ; extract -) - -(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT - (f-2-2 f-7-1) - (sequence () ; insert - (set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1)) - (set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3)) - ) - (sequence () ; extract - (set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1) - (ifield f-7-1)) - 1)) - ) -) - -;------------------------------------------------------------- -; Immediates and displacements beyond the base insn -;------------------------------------------------------------- - -(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f) -(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f) -(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f) -(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f) -(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f) -(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f) -(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f) -(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f) -(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f) -(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f) -(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f) -(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f) -(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f) -(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f) -(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f) -(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f) -(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f) -(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f) - -; Insn opcode endianness is big, but the immediate fields are stored -; in little endian. Handle this here at the field level for all immediate -; fields longer that 1 byte. -; -; CGEN can't handle a field which spans a 32 bit word boundary, so -; handle those as multi ifields. -; -; Take care in expressions using 'srl' or 'sll' as part of some larger -; expression meant to yield sign-extended values. CGEN translates -; uses of those operators into C expressions whose type is 'unsigned -; int', which tends to make the whole expression 'unsigned int'. -; Expressions like (set (ifield foo) X), however, just take X and -; store it in some member of 'struct cgen_fields', all of whose -; members are 'long'. On machines where 'long' is larger than -; 'unsigned int', assigning a "sign-extended" unsigned int to a long -; just produces a very large positive value. insert_normal will -; range-check the field's value and produce odd error messages like -; this: -; -; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]' -; -; Annoyingly, the code will work fine on machines where 'long' and -; 'unsigned int' are the same size: the assignment will produce a -; negative number. -; -; Just tell yourself over and over: overflow detection is expensive, -; and you're glad C doesn't do it, because it never happens in real -; life. - -(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT - ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert - ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) - -(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract -) - -(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT - ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert - ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) - -(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract -) - -(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT - (f-dsp-24-u8 f-dsp-32-u8) - (sequence () ; insert - (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff)) - (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff)) - ) - (sequence () ; extract - (set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8) - (ifield f-dsp-24-u8))) - ) -) - -(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT - (f-dsp-24-u8 f-dsp-32-u8) - (sequence () ; insert - (set (ifield f-dsp-24-u8) - (and (ifield f-dsp-24-s16) #xff)) - (set (ifield f-dsp-32-u8) - (and (srl (ifield f-dsp-24-s16) 8) #xff)) - ) - (sequence () ; extract - (set (ifield f-dsp-24-s16) - (ext INT - (trunc HI (or (sll (ifield f-dsp-32-u8) 8) - (ifield f-dsp-24-u8))))) - ) -) - -(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT - ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert - ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) - -(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract -) - -(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT - ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert - ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) - -(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract -) - -(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT - ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert - ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) - -(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract -) - -(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT - ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert - ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) -(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT - ((value pc) (or SI - (or (and (srl value 16) #xff) (and value #xff00)) - (sll (ext INT (trunc QI (and value #xff))) 16))) - ((value pc) (or SI - (or (and (srl value 16) #xff) (and value #xff00)) - (sll (ext INT (trunc QI (and value #xff))) 16))) - ) - -(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT - ((value pc) (or SI - (or (srl value 16) (and value #xff00)) - (sll (and value #xff) 16))) - ((value pc) (or SI - (or (srl value 16) (and value #xff00)) - (sll (and value #xff) 16))) - ) - -(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT - (f-dsp-16-u16 f-dsp-32-u8) - (sequence () ; insert - (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff)) - (set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff)) - ) - (sequence () ; extract - (set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16) - (ifield f-dsp-16-u16))) - ) -) - -(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT - (f-dsp-24-u8 f-dsp-32-u16) - (sequence () ; insert - (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff)) - (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8) - (ifield f-dsp-24-u8))) - ) -) - -(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT - ((value pc) (or USI - (or USI - (and (srl value 16) #x0000ff) - (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert - ((value pc) (or USI - (or USI - (and USI (srl value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll value 16) #xff0000))) ; extract -) - -(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT - ((value pc) (or USI - (or USI - (and (srl value 16) #x0000ff) - (and value #x00ff00)) - (and (sll value 16) #x0f0000))) ; insert - ((value pc) (or USI - (or USI - (and USI (srl value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll value 16) #x0f0000))) ; extract -) - -(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT - ((value pc) (or USI - (or USI - (and (srl value 16) #x0000ff) - (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert - ((value pc) (or USI - (or USI - (and USI (srl value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll value 16) #xff0000))) ; extract -) - -(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT - (f-dsp-40-u24 f-dsp-64-u8) - (sequence () ; insert - (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff)) - (set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff) - (and (sll (ifield f-dsp-64-u8) 24) #xff000000))) - ) -) - -(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT - (f-dsp-48-u16 f-dsp-64-u8) - (sequence () ; insert - (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) - (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) - ) -) -(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT - (f-dsp-48-u16 f-dsp-64-u8) - (sequence () ; insert - (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff)) - (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u8) 16) #xff0000))) - ) -) - -(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT - (f-dsp-16-u16 f-dsp-32-u16) - (sequence () ; insert - (set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff)) - (set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff) - (and (sll (ifield f-dsp-32-u16) 16) #xffff0000))) - ) -) - -(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT - (f-dsp-24-u8 f-dsp-32-u24) - (sequence () ; insert - (set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff)) - (set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff)) - ) - (sequence () ; extract - (set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff) - (and (sll (ifield f-dsp-32-u24) 8) #xffffff00))) - ) -) - -(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT - ((value pc) - - ;; insert - (ext INT - (or SI - (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) - (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) - - ;; extract - ((value pc) - (ext INT - (or SI - (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) - (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) -) - -(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT - (f-dsp-48-u16 f-dsp-64-u16) - (sequence () ; insert - (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff)) - (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) - ) -) - -(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT - (f-dsp-48-u16 f-dsp-64-u16) - (sequence () ; insert - (set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff)) - (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff)) - ) - (sequence () ; extract - (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) - ) -) - -(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT - (f-dsp-56-u8 f-dsp-64-u8) - (sequence () ; insert - (set (ifield f-dsp-56-u8) - (and (ifield f-dsp-56-s16) #xff)) - (set (ifield f-dsp-64-u8) - (and (srl (ifield f-dsp-56-s16) 8) #xff)) - ) - (sequence () ; extract - (set (ifield f-dsp-56-s16) - (ext INT - (trunc HI (or (sll (ifield f-dsp-64-u8) 8) - (ifield f-dsp-56-u8))))) - ) -) - -(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert - ((value pc) (ext INT - (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract -) - -;------------------------------------------------------------- -; Bit indices -;------------------------------------------------------------- - -(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3) -(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3) -(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3) - -(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT - (f-bitno16-S f-dsp-8-u8) - (sequence () ; insert - (set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7)) - (set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff)) - ) - (sequence () ; extract - (set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3) - (ifield f-bitno16-S))) - ) -) - -(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT - (f-bitno32-unprefixed f-dsp-16-u8) - (sequence () ; insert - (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7)) - (set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3) - (ifield f-bitno32-unprefixed))) - ) -) -(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT - (f-bitno32-unprefixed f-dsp-16-s8) - (sequence () ; insert - (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7)) - (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3) - (ifield f-bitno32-unprefixed))) - ) -) -(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT - (f-bitno32-unprefixed f-dsp-16-u16) - (sequence () ; insert - (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7)) - (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) - (ifield f-bitno32-unprefixed))) - ) -) -(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT - (f-bitno32-unprefixed f-dsp-16-s16) - (sequence () ; insert - (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7)) - (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3) - (ifield f-bitno32-unprefixed))) - ) -) -; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( -(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT - (f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8) - (sequence () ; insert - (set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7)) - (set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff)) - (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3) - (or (sll (ifield f-dsp-32-u8) 19) - (ifield f-bitno32-unprefixed)))) - ) -) -(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT - (f-bitno32-prefixed f-dsp-24-u8) - (sequence () ; insert - (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7)) - (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (ifield f-bitno32-prefixed))) - ) -) -(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT - (f-bitno32-prefixed f-dsp-24-s8) - (sequence () ; insert - (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7)) - (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3) - (ifield f-bitno32-prefixed))) - ) -) -; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( -(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT - (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8) - (sequence () ; insert - (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7)) - (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff)) - (set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (or (sll (ifield f-dsp-32-u8) 11) - (ifield f-bitno32-prefixed)))) - ) -) -; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( -(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT - (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8) - (sequence () ; insert - (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7)) - (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff)) - (set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (or (sll (ifield f-dsp-32-s8) 11) - (ifield f-bitno32-prefixed)))) - ) -) -; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-( -(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT - (f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16) - (sequence () ; insert - (set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7)) - (set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff)) - (set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff)) - ) - (sequence () ; extract - (set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (or (sll (ifield f-dsp-32-u16) 11) - (ifield f-bitno32-prefixed)))) - ) -) - -;------------------------------------------------------------- -; Labels -;------------------------------------------------------------- - -(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT - ((value pc) (sub SI value (add SI pc 2))) ; insert - ((value pc) (add SI value (add SI pc 2))) ; extract -) -(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT - (f-2-2 f-7-1) - (sequence ((SI val)) ; insert - (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2)) - (set (ifield f-7-1) (and val #x1)) - (set (ifield f-2-2) (srl val 1)) - ) - (sequence () ; extract - (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1) - (ifield f-7-1)) - 2))) - ) -) -(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT - ((value pc) (sub SI value (add SI pc 1))) ; insert - ((value pc) (add SI value (add SI pc 1))) ; extract -) -(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT - ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) - (srl (and (sub value (add pc 1)) #xffff) 8))) - ((value pc) (add SI (or (srl (and value #xffff) 8) - (sra (sll (and value #xff) 24) 16)) (add pc 1))) - ) -(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT - ((value pc) (or SI - (or (srl value 16) (and value #xff00)) - (sll (and value #xff) 16))) - ((value pc) (or SI - (or (srl value 16) (and value #xff00)) - (sll (and value #xff) 16))) - ) -(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT - ((value pc) (sub SI value (add SI pc 2))) ; insert - ((value pc) (add SI value (add SI pc 2))) ; extract -) -(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT - ((value pc) (sub SI value (add SI pc 2))) ; insert - ((value pc) (add SI value (add SI pc 2))) ; extract -) -(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT - ((value pc) (sub SI value (add SI pc 2))) ; insert - ((value pc) (add SI value (add SI pc 2))) ; extract -) -(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT - ((value pc) (sub SI value (add SI pc 2))) ; insert - ((value pc) (add SI value (add SI pc 2))) ; extract -) - -;------------------------------------------------------------- -; Condition codes -;------------------------------------------------------------- - -(dnf f-cond16 "condition code" (all-isas) 12 4) -(dnf f-cond16j-5 "condition code" (all-isas) 5 3) - -(dnmf f-cond32 "condition code" (all-isas) UINT - (f-9-1 f-13-3) - (sequence () ; insert - (set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1)) - (set (ifield f-13-3) (and (ifield f-cond32) #x7)) - ) - (sequence () ; extract - (set (ifield f-cond32) (or (sll (ifield f-9-1) 3) - (ifield f-13-3))) - ) -) - -(dnmf f-cond32j "condition code" (all-isas) UINT - (f-1-3 f-7-1) - (sequence () ; insert - (set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7)) - (set (ifield f-7-1) (and (ifield f-cond32j) #x1)) - ) - (sequence () ; extract - (set (ifield f-cond32j) (or (sll (ifield f-1-3) 1) - (ifield f-7-1))) - ) -) - -;============================================================= -; Hardware -; -(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ()) - -;------------------------------------------------------------- -; General registers -; The actual registers are 16 bits -;------------------------------------------------------------- - -(define-hardware - (name h-gr) - (comment "general 16 bit registers") - (attrs all-isas CACHE-ADDR) - (type register HI (4)) - (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))) - -; Define different views of the grs as VIRTUAL with getter/setter specs -; -(define-hardware - (name h-gr-QI) - (comment "general 8 bit registers") - (attrs all-isas VIRTUAL) - (type register QI (4)) - (indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3))) - (get (index) (and (if SI (mod index 2) - (srl (reg h-gr (div index 2)) 8) - (reg h-gr (div index 2))) - #xff)) - (set (index newval) (set (reg h-gr (div index 2)) - (if SI (mod index 2) - (or (and (reg h-gr (div index 2)) #xff) - (sll (and newval #xff) 8)) - (or (and (reg h-gr (div index 2)) #xff00) - (and newval #xff)))))) - -(define-hardware - (name h-gr-HI) - (comment "general 16 bit registers") - (attrs all-isas VIRTUAL) - (type register HI (4)) - (indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))) - (get (index) (reg h-gr index)) - (set (index newval) (set (reg h-gr index) newval))) - -(define-hardware - (name h-gr-SI) - (comment "general 32 bit registers") - (attrs all-isas VIRTUAL) - (type register SI (2)) - (indices keyword "" (("r2r0" 0) ("r3r1" 1))) - (get (index) (or SI - (and (reg h-gr index) #xffff) - (and (sll (reg h-gr (add index 2)) 16) #xffff0000))) - (set (index newval) (sequence () - (set (reg h-gr index) (and newval #xffff)) - (set (reg h-gr (add index 2)) (srl newval 16))))) - -(define-hardware - (name h-gr-ext-QI) - (comment "general 16 bit registers") - (attrs all-isas VIRTUAL) - (type register HI (2)) - (indices keyword "" (("r0l" 0) ("r1l" 1))) - (get (index) (reg h-gr-QI (mul index 2))) - (set (index newval) (set (reg h-gr (mul index 2)) newval))) - -(define-hardware - (name h-gr-ext-HI) - (comment "general 16 bit registers") - (attrs all-isas VIRTUAL) - (type register SI (2)) - (indices keyword "" (("r0" 0) ("r1" 1))) - (get (index) (reg h-gr (mul index 2))) - (set (index newval) (set (reg h-gr-SI index) newval))) - -(define-hardware - (name h-r0l) - (comment "r0l register") - (attrs all-isas VIRTUAL) - (type register QI) - (indices keyword "" (("r0l" 0))) - (get () (reg h-gr-QI 0)) - (set (newval) (set (reg h-gr-QI 0) newval))) - -(define-hardware - (name h-r0h) - (comment "r0h register") - (attrs all-isas VIRTUAL) - (type register QI) - (indices keyword "" (("r0h" 0))) - (get () (reg h-gr-QI 1)) - (set (newval) (set (reg h-gr-QI 1) newval))) - -(define-hardware - (name h-r1l) - (comment "r1l register") - (attrs all-isas VIRTUAL) - (type register QI) - (indices keyword "" (("r1l" 0))) - (get () (reg h-gr-QI 2)) - (set (newval) (set (reg h-gr-QI 2) newval))) - -(define-hardware - (name h-r1h) - (comment "r1h register") - (attrs all-isas VIRTUAL) - (type register QI) - (indices keyword "" (("r1h" 0))) - (get () (reg h-gr-QI 3)) - (set (newval) (set (reg h-gr-QI 3) newval))) - -(define-hardware - (name h-r0) - (comment "r0 register") - (attrs all-isas VIRTUAL) - (type register HI) - (indices keyword "" (("r0" 0))) - (get () (reg h-gr 0)) - (set (newval) (set (reg h-gr 0) newval))) - -(define-hardware - (name h-r1) - (comment "r1 register") - (attrs all-isas VIRTUAL) - (type register HI) - (indices keyword "" (("r1" 0))) - (get () (reg h-gr 1)) - (set (newval) (set (reg h-gr 1) newval))) - -(define-hardware - (name h-r2) - (comment "r2 register") - (attrs all-isas VIRTUAL) - (type register HI) - (indices keyword "" (("r2" 0))) - (get () (reg h-gr 2)) - (set (newval) (set (reg h-gr 2) newval))) - -(define-hardware - (name h-r3) - (comment "r3 register") - (attrs all-isas VIRTUAL) - (type register HI) - (indices keyword "" (("r3" 0))) - (get () (reg h-gr 3)) - (set (newval) (set (reg h-gr 3) newval))) - -(define-hardware - (name h-r0l-r0h) - (comment "r0l or r0h") - (attrs all-isas VIRTUAL) - (type register QI (2)) - (indices keyword "" (("r0l" 0) ("r0h" 1))) - (get (index) (reg h-gr-QI index)) - (set (index newval) (set (reg h-gr-QI index) newval))) - -(define-hardware - (name h-r2r0) - (comment "r2r0 register") - (attrs all-isas VIRTUAL) - (type register SI) - (indices keyword "" (("r2r0" 0))) - (get () (or (sll (reg h-gr 2) 16) (reg h-gr 0))) - (set (newval) - (sequence () - (set (reg h-gr 0) newval) - (set (reg h-gr 2) (sra newval 16))))) - -(define-hardware - (name h-r3r1) - (comment "r3r1 register") - (attrs all-isas VIRTUAL) - (type register SI) - (indices keyword "" (("r3r1" 0))) - (get () (or (sll (reg h-gr 3) 16) (reg h-gr 1))) - (set (newval) - (sequence () - (set (reg h-gr 1) newval) - (set (reg h-gr 3) (sra newval 16))))) - -(define-hardware - (name h-r1r2r0) - (comment "r1r2r0 register") - (attrs all-isas VIRTUAL) - (type register DI) - (indices keyword "" (("r1r2r0" 0))) - (get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0)))) - (set (newval) - (sequence () - (set (reg h-gr 0) newval) - (set (reg h-gr 2) (sra newval 16)) - (set (reg h-gr 1) (sra newval 32))))) - -;------------------------------------------------------------- -; Address registers -;------------------------------------------------------------- - -(define-hardware - (name h-ar) - (comment "address registers") - (attrs all-isas) - (type register USI (2)) - (indices keyword "" (("a0" 0) ("a1" 1))) - (get (index) (c-call USI "h_ar_get_handler" index)) - (set (index newval) (c-call VOID "h_ar_set_handler" index newval))) - -; Define different views of the ars as VIRTUAL with getter/setter specs -(define-hardware - (name h-ar-QI) - (comment "8 bit view of address register") - (attrs all-isas VIRTUAL) - (type register QI (2)) - (indices keyword "" (("a0" 0) ("a1" 1))) - (get (index) (reg h-ar index)) - (set (index newval) (set (reg h-ar index) newval))) - -(define-hardware - (name h-ar-HI) - (comment "16 bit view of address register") - (attrs all-isas VIRTUAL) - (type register HI (2)) - (indices keyword "" (("a0" 0) ("a1" 1))) - (get (index) (reg h-ar index)) - (set (index newval) (set (reg h-ar index) newval))) - -(define-hardware - (name h-ar-SI) - (comment "32 bit view of address register") - (attrs all-isas VIRTUAL) - (type register SI) - (indices keyword "" (("a1a0" 0))) - (get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0)))) - (set (newval) (sequence () - (set (reg h-ar 0) (and newval #xffff)) - (set (reg h-ar 1) (and (srl newval 16) #xffff))))) - -(define-hardware - (name h-a0) - (comment "16 bit view of address register") - (attrs all-isas VIRTUAL) - (type register HI) - (indices keyword "" (("a0" 0))) - (get () (reg h-ar 0)) - (set (newval) (set (reg h-ar 0) newval))) - -(define-hardware - (name h-a1) - (comment "16 bit view of address register") - (attrs all-isas VIRTUAL) - (type register HI) - (indices keyword "" (("a1" 1))) - (get () (reg h-ar 1)) - (set (newval) (set (reg h-ar 1) newval))) - -; SB Register -(define-hardware - (name h-sb) - (comment "SB register") - (attrs all-isas) - (type register USI) - (get () (c-call USI "h_sb_get_handler")) - (set (newval) (c-call VOID "h_sb_set_handler" newval)) -) - -; FB Register -(define-hardware - (name h-fb) - (comment "FB register") - (attrs all-isas) - (type register USI) - (get () (c-call USI "h_fb_get_handler")) - (set (newval) (c-call VOID "h_fb_set_handler" newval)) -) - -; SP Register -(define-hardware - (name h-sp) - (comment "SP register") - (attrs all-isas) - (type register USI) - (get () (c-call USI "h_sp_get_handler")) - (set (newval) (c-call VOID "h_sp_set_handler" newval)) -) - -;------------------------------------------------------------- -; condition-code bits -;------------------------------------------------------------- - -(define-hardware - (name h-sbit) - (comment "sign bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-zbit) - (comment "zero bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-obit) - (comment "overflow bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-cbit) - (comment "carry bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-ubit) - (comment "stack pointer select bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-ibit) - (comment "interrupt enable bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-bbit) - (comment "register bank select bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-dbit) - (comment "debug bit") - (attrs all-isas) - (type register BI) -) - -(define-hardware - (name h-dct0) - (comment "dma transfer count 000") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-dct1) - (comment "dma transfer count 001") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-svf) - (comment "save flag 011") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-drc0) - (comment "dma transfer count reload 100") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-drc1) - (comment "dma transfer count reload 101") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-dmd0) - (comment "dma mode 110") - (attrs all-isas) - (type register UQI) -) -(define-hardware - (name h-dmd1) - (comment "dma mode 111") - (attrs all-isas) - (type register UQI) -) -(define-hardware - (name h-intb) - (comment "interrupt table 000") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-svp) - (comment "save pc 100") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-vct) - (comment "vector 101") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-isp) - (comment "interrupt stack ptr 111") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-dma0) - (comment "dma mem addr 010") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-dma1) - (comment "dma mem addr 011") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-dra0) - (comment "dma mem addr reload 100") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-dra1) - (comment "dma mem addr reload 101") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-dsa0) - (comment "dma sfr addr 110") - (attrs all-isas) - (type register USI) -) -(define-hardware - (name h-dsa1) - (comment "dma sfr addr 111") - (attrs all-isas) - (type register USI) -) - -;------------------------------------------------------------- -; Condition code operand hardware -;------------------------------------------------------------- - -(define-hardware - (name h-cond16) - (comment "condition code hardware for m16c") - (attrs m16c-isa MACH16) - (type immediate UQI) - (values keyword "" - (("geu" #x00) ("c" #x00) - ("gtu" #x01) - ("eq" #x02) ("z" #x02) - ("n" #x03) - ("le" #x04) - ("o" #x05) - ("ge" #x06) - ("ltu" #xf8) ("nc" #xf8) - ("leu" #xf9) - ("ne" #xfa) ("nz" #xfa) - ("pz" #xfb) - ("gt" #xfc) - ("no" #xfd) - ("lt" #xfe) - ) - ) -) -(define-hardware - (name h-cond16c) - (comment "condition code hardware for m16c") - (attrs m16c-isa MACH16) - (type immediate UQI) - (values keyword "" - (("geu" #x00) ("c" #x00) - ("gtu" #x01) - ("eq" #x02) ("z" #x02) - ("n" #x03) - ("ltu" #x04) ("nc" #x04) - ("leu" #x05) - ("ne" #x06) ("nz" #x06) - ("pz" #x07) - ("le" #x08) - ("o" #x09) - ("ge" #x0a) - ("gt" #x0c) - ("no" #x0d) - ("lt" #x0e) - ) - ) -) -(define-hardware - (name h-cond16j) - (comment "condition code hardware for m16c") - (attrs m16c-isa MACH16) - (type immediate UQI) - (values keyword "" - (("le" #x08) - ("o" #x09) - ("ge" #x0a) - ("gt" #x0c) - ("no" #x0d) - ("lt" #x0e) - ) - ) -) -(define-hardware - (name h-cond16j-5) - (comment "condition code hardware for m16c") - (attrs m16c-isa MACH16) - (type immediate UQI) - (values keyword "" - (("geu" #x00) ("c" #x00) - ("gtu" #x01) - ("eq" #x02) ("z" #x02) - ("n" #x03) - ("ltu" #x04) ("nc" #x04) - ("leu" #x05) - ("ne" #x06) ("nz" #x06) - ("pz" #x07) - ) - ) -) - -(define-hardware - (name h-cond32) - (comment "condition code hardware for m32c") - (attrs m32c-isa MACH32) - (type immediate UQI) - (values keyword "" - (("ltu" #x00) ("nc" #x00) - ("leu" #x01) - ("ne" #x02) ("nz" #x02) - ("pz" #x03) - ("no" #x04) - ("gt" #x05) - ("ge" #x06) - ("geu" #x08) ("c" #x08) - ("gtu" #x09) - ("eq" #x0a) ("z" #x0a) - ("n" #x0b) - ("o" #x0c) - ("le" #x0d) - ("lt" #x0e) - ) - ) -) - -(define-hardware - (name h-cr1-32) - (comment "control registers") - (attrs m32c-isa MACH32) - (type immediate UQI) - (values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4) - ("drc1" 5) ("dmd0" 6) ("dmd1" 7)))) -(define-hardware - (name h-cr2-32) - (comment "control registers") - (attrs m32c-isa MACH32) - (type immediate UQI) - (values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4) - ("vct" 5) ("isp" 7)))) - -(define-hardware - (name h-cr3-32) - (comment "control registers") - (attrs m32c-isa MACH32) - (type immediate UQI) - (values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4) - ("dra1" 5) ("dsa0" 6) ("dsa1" 7)))) -(define-hardware - (name h-cr-16) - (comment "control registers") - (attrs m16c-isa MACH16) - (type immediate UQI) - (values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4) - ("sp" 5) ("sb" 6) ("fb" 7)))) - -(define-hardware - (name h-flags) - (comment "flag hardware for m32c") - (attrs all-isas) - (type immediate UQI) - (values keyword "" - (("c" #x0) - ("d" #x1) - ("z" #x2) - ("s" #x3) - ("b" #x4) - ("o" #x5) - ("i" #x6) - ("u" #x7) - ) - ) -) - -;------------------------------------------------------------- -; Misc helper hardware -;------------------------------------------------------------- - -(define-hardware - (name h-shimm) - (comment "shift immediate") - (attrs all-isas) - (type immediate (INT 4)) - (values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6) - ("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4) - ("-6" -3) ("-7" -2) ("-8" -1) - ))) -(define-hardware - (name h-bit-index) - (comment "bit index for the next insn") - (attrs m32c-isa MACH32) - (type register UHI) -) -(define-hardware - (name h-src-index) - (comment "source index for the next insn") - (attrs m32c-isa MACH32) - (type register UHI) -) -(define-hardware - (name h-dst-index) - (comment "destination index for the next insn") - (attrs m32c-isa MACH32) - (type register UHI) -) -(define-hardware - (name h-src-indirect) - (comment "indirect src for the next insn") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-dst-indirect) - (comment "indirect dst for the next insn") - (attrs all-isas) - (type register UHI) -) -(define-hardware - (name h-none) - (comment "for storing unused values") - (attrs m32c-isa MACH32) - (type register SI) -) - -;============================================================= -; Operands -;------------------------------------------------------------- -; Source Registers -;------------------------------------------------------------- - -(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn) -(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn) - -(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI) -(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI) -(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI) - -(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI) -(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI) -(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI) - -(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an) -(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an) -(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an) - -(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) -(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed) -(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed) -(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed) - -(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) -(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed) -(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed) -(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed) - -; Destination Registers -; -(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn) -(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) -(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn) -(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext) - -(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil) -(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil) - -(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) -(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI) -(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI) -(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed) -(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed) - -(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) -(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI) -(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI) - -(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s) - -(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s) - -(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn) - -(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI) -(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI) - -(dnop R0 "r0" (all-isas) h-r0 f-nil) -(dnop R1 "r1" (all-isas) h-r1 f-nil) -(dnop R2 "r2" (all-isas) h-r2 f-nil) -(dnop R3 "r3" (all-isas) h-r3 f-nil) -(dnop R0l "r0l" (all-isas) h-r0l f-nil) -(dnop R0h "r0h" (all-isas) h-r0h f-nil) -(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil) -(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil) -(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil) - -(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an) -(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an) -(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an) -(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an) -(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s) - -(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) -(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed) -(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed) -(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) - -(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) - -(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) -(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed) -(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed) -(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) - -(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an) - -(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed) -(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed) - -(dnop A0 "a0" (all-isas) h-a0 f-nil) -(dnop A1 "a1" (all-isas) h-a1 f-nil) - -(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil) -(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil) -(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil) - -(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa) - h-sint DFLT f-5-1 - ((parse "r0l_r0h") (print "r0l_r0h")) () () -) - -(define-full-operand Regsetpop "popm regset" (all-isas) h-uint - DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ()) -(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint - DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ()) - -(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1) -(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1) - -;------------------------------------------------------------- -; Offsets and absolutes -;------------------------------------------------------------- - -(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas) - h-uint DFLT f-dsp-8-u6 - ((parse "unsigned6")) () () -) -(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas) - h-uint DFLT f-dsp-8-u8 - ((parse "unsigned8")) () () -) -(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas) - h-uint DFLT f-dsp-8-u16 - ((parse "unsigned16")) () () -) -(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas) - h-sint DFLT f-dsp-8-s8 - ((parse "signed8")) () () -) -(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas) - h-sint DFLT f-dsp-8-s24 - ((parse "signed24")) () () -) -(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas) - h-uint DFLT f-dsp-8-u24 - ((parse "unsigned24")) () () -) -(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas) - h-uint DFLT f-dsp-10-u6 - ((parse "unsigned6")) () () -) -(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas) - h-uint DFLT f-dsp-16-u8 - ((parse "unsigned8")) () () -) -(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas) - h-uint DFLT f-dsp-16-u16 - ((parse "unsigned16")) () () -) -(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas) - h-uint DFLT f-dsp-16-u24 - ((parse "unsigned20")) () () -) -(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas) - h-uint DFLT f-dsp-16-u24 - ((parse "unsigned24")) () () -) -(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas) - h-sint DFLT f-dsp-16-s8 - ((parse "signed8")) () () -) -(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas) - h-sint DFLT f-dsp-16-s16 - ((parse "signed16")) () () -) -(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas) - h-uint DFLT f-dsp-24-u8 - ((parse "unsigned8")) () () -) -(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas) - h-uint DFLT f-dsp-24-u16 - ((parse "unsigned16")) () () -) -(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas) - h-uint DFLT f-dsp-24-u24 - ((parse "unsigned20")) () () -) -(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas) - h-uint DFLT f-dsp-24-u24 - ((parse "unsigned24")) () () -) -(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas) - h-sint DFLT f-dsp-24-s8 - ((parse "signed8")) () () -) -(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas) - h-sint DFLT f-dsp-24-s16 - ((parse "signed16")) () () -) -(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas) - h-uint DFLT f-dsp-32-u8 - ((parse "unsigned8")) () () -) -(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas) - h-uint DFLT f-dsp-32-u16 - ((parse "unsigned16")) () () -) -(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas) - h-uint DFLT f-dsp-32-u24 - ((parse "unsigned24")) () () -) -(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas) - h-uint DFLT f-dsp-32-u24 - ((parse "unsigned20")) () () -) -(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas) - h-sint DFLT f-dsp-32-s8 - ((parse "signed8")) () () -) -(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas) - h-sint DFLT f-dsp-32-s16 - ((parse "signed16")) () () -) -(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-40-u8 - ((parse "unsigned8")) () () -) -(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas) - h-sint DFLT f-dsp-40-s8 - ((parse "signed8")) () () -) -(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-40-u16 - ((parse "unsigned16")) () () -) -(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas) - h-sint DFLT f-dsp-40-s16 - ((parse "signed16")) () () -) -(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-40-u20 - ((parse "unsigned20")) () () -) -(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-40-u24 - ((parse "unsigned24")) () () -) -(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas) - h-uint DFLT f-dsp-48-u8 - ((parse "unsigned8")) () () -) -(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas) - h-sint DFLT f-dsp-48-s8 - ((parse "signed8")) () () -) -(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas) - h-uint DFLT f-dsp-48-u16 - ((parse "unsigned16")) () () -) -(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas) - h-sint DFLT f-dsp-48-s16 - ((parse "signed16")) () () -) -(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-48-u20 - ((parse "unsigned24")) () () -) -(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) - h-uint DFLT f-dsp-48-u24 - ((parse "unsigned24")) () () -) - -(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas) - h-sint DFLT f-imm-8-s4 - ((parse "signed4")) () () -) -(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) - h-sint DFLT f-imm-8-s4 - ((parse "signed4n") (print "signed4n")) () () -) -(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) - h-shimm DFLT f-imm-8-s4 - () () () -) -(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas) - h-sint DFLT f-dsp-8-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas) - h-sint DFLT f-dsp-8-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas) - h-sint DFLT f-imm-12-s4 - ((parse "signed4")) () () -) -(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas) - h-sint DFLT f-imm-12-s4 - ((parse "signed4n") (print "signed4n")) () () -) -(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) - h-shimm DFLT f-imm-12-s4 - () () () -) -(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas) - h-sint DFLT f-imm-13-u3 - ((parse "signed4")) () () -) -(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas) - h-sint DFLT f-imm-20-s4 - ((parse "signed4")) () () -) -(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) - h-shimm DFLT f-imm-20-s4 - () () () -) -(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas) - h-sint DFLT f-dsp-16-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas) - h-sint DFLT f-dsp-16-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas) - h-sint DFLT f-dsp-16-s32 - ((parse "signed32")) () () -) -(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas) - h-sint DFLT f-dsp-24-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas) - h-sint DFLT f-dsp-24-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas) - h-sint DFLT f-dsp-24-s32 - ((parse "signed32")) () () -) -(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas) - h-sint DFLT f-dsp-32-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas) - h-sint DFLT f-dsp-32-s32 - ((parse "signed32")) () () -) -(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas) - h-sint DFLT f-dsp-32-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas) - h-sint DFLT f-dsp-40-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas) - h-sint DFLT f-dsp-40-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas) - h-sint DFLT f-dsp-40-s32 - ((parse "signed32")) () () -) -(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas) - h-sint DFLT f-dsp-48-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas) - h-sint DFLT f-dsp-48-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas) - h-sint DFLT f-dsp-48-s32 - ((parse "signed32")) () () -) -(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas) - h-sint DFLT f-dsp-56-s8 - ((parse "signed8")) () () -) -(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas) - h-sint DFLT f-dsp-56-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas) - h-sint DFLT f-dsp-64-s16 - ((parse "signed16")) () () -) -(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa) - h-sint DFLT f-imm1-S - ((parse "imm1_S")) () () -) -(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa) - h-sint DFLT f-imm3-S - ((parse "imm3_S")) () () -) -(define-full-operand Bit3-S "3 bit bit number" (m32c-isa) - h-sint DFLT f-imm3-S - ((parse "bit3_S")) () () -) - -;------------------------------------------------------------- -; Bit numbers -;------------------------------------------------------------- - -(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa) - h-uint DFLT f-dsp-16-u8 - ((parse "Bitno16R")) () () -) -(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed) -(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed) - -(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa) - h-uint DFLT f-dsp-16-u8 - ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa) - h-sint DFLT f-dsp-16-s8 - ((parse "signed_bitbase8") (print "signed_bitbase")) () () -) -(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa) - h-uint DFLT f-dsp-16-u16 - ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa) - h-uint DFLT f-bitbase16-u11-S - ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () -) - -(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa) - h-uint DFLT f-bitbase32-16-u11-unprefixed - ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa) - h-sint DFLT f-bitbase32-16-s11-unprefixed - ((parse "signed_bitbase11") (print "signed_bitbase")) () () -) -(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa) - h-uint DFLT f-bitbase32-16-u19-unprefixed - ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa) - h-sint DFLT f-bitbase32-16-s19-unprefixed - ((parse "signed_bitbase19") (print "signed_bitbase")) () () -) -(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa) - h-uint DFLT f-bitbase32-16-u27-unprefixed - ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa) - h-uint DFLT f-bitbase32-24-u11-prefixed - ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa) - h-sint DFLT f-bitbase32-24-s11-prefixed - ((parse "signed_bitbase11") (print "signed_bitbase")) () () -) -(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa) - h-uint DFLT f-bitbase32-24-u19-prefixed - ((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () () -) -(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa) - h-sint DFLT f-bitbase32-24-s19-prefixed - ((parse "signed_bitbase19") (print "signed_bitbase")) () () -) -(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa) - h-uint DFLT f-bitbase32-24-u27-prefixed - ((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () () -) -;------------------------------------------------------------- -; Labels -;------------------------------------------------------------- - -(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX) - h-iaddr DFLT f-lab-5-3 - ((parse "lab_5_3")) () () ) - -(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX) - h-iaddr DFLT f-lab32-jmp-s - ((parse "lab_5_3")) () () ) - -(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8) -(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) -(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24) -(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) -(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8) -(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8) -(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8) - -;------------------------------------------------------------- -; Condition code bits -;------------------------------------------------------------- - -(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil) -(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil) -(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil) -(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil) -(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil) -(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil) -(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil) -(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil) - -;------------------------------------------------------------- -; Condition operands -;------------------------------------------------------------- - -(define-pmacro (cond-operand mach offset) - (dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8)) -) - -(cond-operand 16 16) -(cond-operand 16 24) -(cond-operand 16 32) -(cond-operand 32 16) -(cond-operand 32 24) -(cond-operand 32 32) -(cond-operand 32 40) - -(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16) -(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16) -(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5) -(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32) -(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j) -(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16) -(dnop flags16 "flags" (m16c-isa) h-flags f-9-3) -(dnop flags32 "flags" (m32c-isa) h-flags f-13-3) -(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3) -(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3) -(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3) -(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3) -(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3) -(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3) - -;------------------------------------------------------------- -; Suffixes -;------------------------------------------------------------- - -(define-full-operand Z "Suffix for zero format insns" (all-isas) - h-sint DFLT f-nil - ((parse "Z") (print "Z")) () () -) -(define-full-operand S "Suffix for short format insns" (all-isas) - h-sint DFLT f-nil - ((parse "S") (print "S")) () () -) -(define-full-operand Q "Suffix for quick format insns" (all-isas) - h-sint DFLT f-nil - ((parse "Q") (print "Q")) () () -) -(define-full-operand G "Suffix for general format insns" (all-isas) - h-sint DFLT f-nil - ((parse "G") (print "G")) () () -) -(define-full-operand X "Empty suffix" (all-isas) - h-sint DFLT f-nil - ((parse "X") (print "X")) () () -) -(define-full-operand size "any size specifier" (all-isas) - h-sint DFLT f-nil - ((parse "size") (print "size")) () () -) -;------------------------------------------------------------- -; Misc -;------------------------------------------------------------- - -(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil) -(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil) -(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil) -(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil) - -;============================================================= -; Derived Operands - -; Memory reference macros that clip addresses appropriately. Refer to -; memory at ADDRESS in MODE, clipped appropriately for either the m16c -; or m32c. -(define-pmacro (mem16 mode address) - (mem mode (and #xffff address))) - -(define-pmacro (mem20 mode address) - (mem mode (and #xfffff address))) - -(define-pmacro (mem32 mode address) - (mem mode (and #xffffff address))) - -; Like mem16 and mem32, but takes MACH as a parameter. MACH must be -; either 16 or 32. -(define-pmacro (mem-mach mach mode address) - ((.sym mem mach) mode address)) - -;------------------------------------------------------------- -; Source -;------------------------------------------------------------- -; Rn direct -;------------------------------------------------------------- - -(define-pmacro (src16-Rn-direct-operand xmode) - (begin - (define-derived-operand - (name (.sym src16-Rn-direct- xmode)) - (comment (.str "m16c Rn direct source " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Src16Rn xmode))) - (syntax (.str "$Src16Rn" xmode)) - (base-ifield f-8-4) - (encoding (+ (f-8-2 0) (.sym Src16Rn xmode))) - (ifield-assertion (eq f-8-2 0)) - (getter (trunc xmode (.sym Src16Rn xmode))) - (setter (set (.sym Src16Rn xmode) newval)) - ) - ) -) -(src16-Rn-direct-operand QI) -(src16-Rn-direct-operand HI) - -(define-pmacro (src32-Rn-direct-operand group base xmode) - (begin - (define-derived-operand - (name (.sym src32-Rn-direct- group - xmode)) - (comment (.str "m32c Rn direct source " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Src32Rn group xmode))) - (syntax (.str "$Src32Rn" group xmode)) - (base-ifield (.sym f- base -11)) - (encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode))) - (ifield-assertion (eq (.sym f- base -3) 4)) - (getter (trunc xmode (.sym Src32Rn group xmode))) - (setter (set (.sym Src32Rn group xmode) newval)) - ) - ) -) - -(src32-Rn-direct-operand Unprefixed 1 QI) -(src32-Rn-direct-operand Prefixed 9 QI) -(src32-Rn-direct-operand Unprefixed 1 HI) -(src32-Rn-direct-operand Prefixed 9 HI) -(src32-Rn-direct-operand Unprefixed 1 SI) -(src32-Rn-direct-operand Prefixed 9 SI) - -;------------------------------------------------------------- -; An direct -;------------------------------------------------------------- - -(define-pmacro (src16-An-direct-operand xmode) - (begin - (define-derived-operand - (name (.sym src16-An-direct- xmode)) - (comment (.str "m16c An direct destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Src16An xmode))) - (syntax (.str "$Src16An" xmode)) - (base-ifield f-8-4) - (encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode))) - (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0))) - (getter (trunc xmode (.sym Src16An xmode))) - (setter (set (.sym Src16An xmode) newval)) - ) - ) -) -(src16-An-direct-operand QI) -(src16-An-direct-operand HI) - -(define-pmacro (src32-An-direct-operand group base1 base2 xmode) - (begin - (define-derived-operand - (name (.sym src32-An-direct- group - xmode)) - (comment (.str "m32c An direct destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Src32An group xmode))) - (syntax (.str "$Src32An" group xmode)) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) - (getter (trunc xmode (.sym Src32An group xmode))) - (setter (set (.sym Src32An group xmode) newval)) - ) - ) -) - -(src32-An-direct-operand Unprefixed 1 10 QI) -(src32-An-direct-operand Unprefixed 1 10 HI) -(src32-An-direct-operand Unprefixed 1 10 SI) -(src32-An-direct-operand Prefixed 9 18 QI) -(src32-An-direct-operand Prefixed 9 18 HI) -(src32-An-direct-operand Prefixed 9 18 SI) - -;------------------------------------------------------------- -; An indirect -;------------------------------------------------------------- - -(define-pmacro (src16-An-indirect-operand xmode) - (begin - (define-derived-operand - (name (.sym src16-An-indirect- xmode)) - (comment (.str "m16c An indirect destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Src16An)) - (syntax "[$Src16An]") - (base-ifield f-8-4) - (encoding (+ (f-8-2 1) (f-10-1 1) Src16An)) - (ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1))) - (getter (mem16 xmode Src16An)) - (setter (set (mem16 xmode Src16An) newval)) - ) - ) -) -(src16-An-indirect-operand QI) -(src16-An-indirect-operand HI) - -(define-pmacro (src32-An-indirect-operand group base1 base2 xmode) - (begin - (define-derived-operand - (name (.sym src32-An-indirect- group - xmode)) - (comment (.str "m32c An indirect destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Src32An group))) - (syntax (.str "[$Src32An" group "]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) - (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) - (const 0))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval - (.sym Src32An group) (const 0))) -; (getter (mem32 xmode (.sym Src32An group))) -; (setter (set (mem32 xmode (.sym Src32An group)) newval)) - ) - ) -) - -(src32-An-indirect-operand Unprefixed 1 10 QI) -(src32-An-indirect-operand Unprefixed 1 10 HI) -(src32-An-indirect-operand Unprefixed 1 10 SI) -(src32-An-indirect-operand Prefixed 9 18 QI) -(src32-An-indirect-operand Prefixed 9 18 HI) -(src32-An-indirect-operand Prefixed 9 18 SI) - -;------------------------------------------------------------- -; dsp:d[r] relative -;------------------------------------------------------------- - -(define-pmacro (src16-relative-operand xmode) - (begin - (define-derived-operand - (name (.sym src16-16-8-SB-relative- xmode)) - (comment (.str "m16c dsp:8[sb] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dsp-16-u8)) - (syntax "${Dsp-16-u8}[sb]") - (base-ifield f-8-4) - (encoding (+ (f-8-4 #xA) Dsp-16-u8)) - (ifield-assertion (eq f-8-4 #xA)) - (getter (mem16 xmode (add Dsp-16-u8 (reg h-sb)))) - (setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym src16-16-16-SB-relative- xmode)) - (comment (.str "m16c dsp:16[sb] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}[sb]") - (base-ifield f-8-4) - (encoding (+ (f-8-4 #xE) Dsp-16-u16)) - (ifield-assertion (eq f-8-4 #xE)) - (getter (mem16 xmode (add Dsp-16-u16 (reg h-sb)))) - (setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym src16-16-8-FB-relative- xmode)) - (comment (.str "m16c dsp:8[fb] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dsp-16-s8)) - (syntax "${Dsp-16-s8}[fb]") - (base-ifield f-8-4) - (encoding (+ (f-8-4 #xB) Dsp-16-s8)) - (ifield-assertion (eq f-8-4 #xB)) - (getter (mem16 xmode (add Dsp-16-s8 (reg h-fb)))) - (setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym src16-16-8-An-relative- xmode)) - (comment (.str "m16c dsp:8[An] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Src16An Dsp-16-u8)) - (syntax "${Dsp-16-u8}[$Src16An]") - (base-ifield f-8-4) - (encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An)) - (ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0))) - (getter (mem16 xmode (add Dsp-16-u8 Src16An))) - (setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval)) - ) - (define-derived-operand - (name (.sym src16-16-16-An-relative- xmode)) - (comment (.str "m16c dsp:16[An] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Src16An Dsp-16-u16)) - (syntax "${Dsp-16-u16}[$Src16An]") - (base-ifield f-8-4) - (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An)) - (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) - (getter (mem16 xmode (add Dsp-16-u16 Src16An))) - (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) - ) - (define-derived-operand - (name (.sym src16-16-20-An-relative- xmode)) - (comment (.str "m16c dsp:20[An] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Src16An Dsp-16-u20)) - (syntax "${Dsp-16-u20}[$Src16An]") - (base-ifield f-8-4) - (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) - (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) - (getter (mem20 xmode (add Dsp-16-u20 Src16An))) - (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) - ) - ) -) - -(src16-relative-operand QI) -(src16-relative-operand HI) - -(define-pmacro (src32-relative-operand offset group base1 base2 xmode) - (begin - (define-derived-operand - (name (.sym src32- offset -8-SB-relative- group - xmode)) - (comment (.str "m32c dsp:8[sb] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[sb]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) - (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8))) -; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -16-SB-relative- group - xmode)) - (comment (.str "m32c dsp:16[sb] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[sb]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) - (getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16))) -; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -8-FB-relative- group - xmode)) - (comment (.str "m32c dsp:8[fb] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dsp- offset -s8))) - (syntax (.str "${Dsp-" offset "-s8}[fb]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) - (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8))) -; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -16-FB-relative- group - xmode)) - (comment (.str "m32c dsp:16[fb] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dsp- offset -s16))) - (syntax (.str "${Dsp-" offset "-s16}[fb]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) - (getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16))) -; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -8-An-relative- group - xmode)) - (comment (.str "m32c dsp:8[An] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Src32An group) (.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) - (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8))) -; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -16-An-relative- group - xmode)) - (comment (.str "m32c dsp:16[An] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Src32An group) (.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) - (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16))) -; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -24-An-relative- group - xmode)) - (comment (.str "m32c dsp:16[An] relative destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Src32An group) (.sym Dsp- offset -u24))) - (syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) - (getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) )) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24))) -; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group)))) -; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval)) - ) - ) -) - -(src32-relative-operand 16 Unprefixed 1 10 QI) -(src32-relative-operand 16 Unprefixed 1 10 HI) -(src32-relative-operand 16 Unprefixed 1 10 SI) -(src32-relative-operand 24 Prefixed 9 18 QI) -(src32-relative-operand 24 Prefixed 9 18 HI) -(src32-relative-operand 24 Prefixed 9 18 SI) - -;------------------------------------------------------------- -; Absolute address -;------------------------------------------------------------- - -(define-pmacro (src16-absolute xmode) - (begin - (define-derived-operand - (name (.sym src16-16-16-absolute- xmode)) - (comment (.str "m16c absolute address " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dsp-16-u16)) - (syntax (.str "${Dsp-16-u16}")) - (base-ifield f-8-4) - (encoding (+ (f-8-4 #xF) Dsp-16-u16)) - (ifield-assertion (eq f-8-4 #xF)) - (getter (mem16 xmode Dsp-16-u16)) - (setter (set (mem16 xmode Dsp-16-u16) newval)) - ) - ) -) - -(src16-absolute QI) -(src16-absolute HI) - -(define-pmacro (src32-absolute offset group base1 base2 xmode) - (begin - (define-derived-operand - (name (.sym src32- offset -16-absolute- group - xmode)) - (comment (.str "m32c absolute address " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) - (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16))) -; (getter (mem32 xmode (.sym Dsp- offset -u16))) -; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval)) - ) - (define-derived-operand - (name (.sym src32- offset -24-absolute- group - xmode)) - (comment (.str "m32c absolute address " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dsp- offset -u24))) - (syntax (.str "${Dsp-" offset "-u24}")) - (base-ifield (.sym f- base1 -11)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) - (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24))) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24))) -; (getter (mem32 xmode (.sym Dsp- offset -u24))) -; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval)) - ) - ) -) - -(src32-absolute 16 Unprefixed 1 10 QI) -(src32-absolute 16 Unprefixed 1 10 HI) -(src32-absolute 16 Unprefixed 1 10 SI) -(src32-absolute 24 Prefixed 9 18 QI) -(src32-absolute 24 Prefixed 9 18 HI) -(src32-absolute 24 Prefixed 9 18 SI) - -;------------------------------------------------------------- -; An indirect indirect -; -; Double indirect addressing uses the lower 3 bytes of the value stored -; at the address referenced by 'op' as the effective address. -;------------------------------------------------------------- - -(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff)) - -; (define-pmacro (src-An-indirect-indirect-operand xmode) -; (define-derived-operand -; (name (.sym src32-An-indirect-indirect- xmode)) -; (comment (.str "m32c An indirect indirect destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Src32AnPrefixed)) -; (syntax (.str "[[$Src32AnPrefixed]]")) -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed)) -; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0))) -; (getter (mem32 xmode (indirect-addr Src32AnPrefixed))) -; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval)) -; ) -; ) - -; (src-An-indirect-indirect-operand QI) -; (src-An-indirect-indirect-operand HI) -; (src-An-indirect-indirect-operand SI) - -;------------------------------------------------------------- -; Relative indirect -;------------------------------------------------------------- - -(define-pmacro (src-relative-indirect-operand xmode) - (begin -; (define-derived-operand -; (name (.sym src32-24-8-SB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:8[sb] relative source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-24-u8)) -; (syntax "[${Dsp-24-u8}[sb]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8)) -; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb))))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32-24-16-SB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:16[sb] relative source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-24-u16)) -; (syntax "[${Dsp-24-u16}[sb]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16)) -; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb))))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32-24-8-FB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:8[fb] relative source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-24-s8)) -; (syntax "[${Dsp-24-s8}[fb]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8)) -; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb))))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32-24-16-FB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:16[fb] relative source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-24-s16)) -; (syntax "[${Dsp-24-s16}[fb]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16)) -; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb))))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32-24-8-An-relative-indirect- xmode)) -; (comment (.str "m32c dsp:8[An] relative indirect source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Src32AnPrefixed Dsp-24-u8)) -; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed)) -; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed)))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32-24-16-An-relative-indirect- xmode)) -; (comment (.str "m32c dsp:16[An] relative source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Src32AnPrefixed Dsp-24-u16)) -; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed)) -; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed)))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32-24-24-An-relative-indirect- xmode)) -; (comment (.str "m32c dsp:24[An] relative source " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Src32AnPrefixed Dsp-24-u24)) -; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]") -; (base-ifield f-9-11) -; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed)) -; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0))) -; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed)))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval)) -; ) - ) -) - -; (src-relative-indirect-operand QI) -; (src-relative-indirect-operand HI) -; (src-relative-indirect-operand SI) - -;------------------------------------------------------------- -; Absolute Indirect address -;------------------------------------------------------------- - -(define-pmacro (src32-absolute-indirect offset base1 base2 xmode) - (begin -; (define-derived-operand -; (name (.sym src32- offset -16-absolute-indirect-derived- xmode)) -; (comment (.str "m32c absolute indirect address " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -u16))) -; (syntax (.str "[${Dsp-" offset "-u16}]")) -; (base-ifield (.sym f- base1 -11)) -; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) -; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) -; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) -; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) -; ) -; (define-derived-operand -; (name (.sym src32- offset -24-absolute-indirect-derived- xmode)) -; (comment (.str "m32c absolute indirect address " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -u24))) -; (syntax (.str "[${Dsp-" offset "-u24}]")) -; (base-ifield (.sym f- base1 -11)) -; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) -; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) -; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) -; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) -; ) - ) -) - -(src32-absolute-indirect 24 9 18 QI) -(src32-absolute-indirect 24 9 18 HI) -(src32-absolute-indirect 24 9 18 SI) - -;------------------------------------------------------------- -; Register relative source operands for short format insns -;------------------------------------------------------------- - -(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3) - (begin - (define-derived-operand - (name (.sym src mach -2-S-8-SB-relative- xmode)) - (comment (.str "m" mach "c SB relative address")) - (attrs (machine mach)) - (mode xmode) - (args (Dsp-8-u8)) - (syntax "${Dsp-8-u8}[sb]") - (base-ifield (.sym f- base -2)) - (encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8)) - (ifield-assertion (eq (.sym f- base -2) opc1)) - (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) -; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8)))) -; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval)) - ) - (define-derived-operand - (name (.sym src mach -2-S-8-FB-relative- xmode)) - (comment (.str "m" mach "c FB relative address")) - (attrs (machine mach)) - (mode xmode) - (args (Dsp-8-s8)) - (syntax "${Dsp-8-s8}[fb]") - (base-ifield (.sym f- base -2)) - (encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8)) - (ifield-assertion (eq (.sym f- base -2) opc2)) - (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) -; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8)))) -; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval)) - ) - (define-derived-operand - (name (.sym src mach -2-S-16-absolute- xmode)) - (comment (.str "m" mach "c absolute address")) - (attrs (machine mach)) - (mode xmode) - (args (Dsp-8-u16)) - (syntax "${Dsp-8-u16}") - (base-ifield (.sym f- base -2)) - (encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16)) - (ifield-assertion (eq (.sym f- base -2) opc3)) - (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) -; (getter (mem-mach mach xmode Dsp-8-u16)) -; (setter (set (mem-mach mach xmode Dsp-8-u16) newval)) - ) - ) -) - -(src-2-S-operands 16 QI 6 1 2 3) -(src-2-S-operands 32 QI 2 2 3 1) -(src-2-S-operands 32 HI 2 2 3 1) - -;============================================================= -; Derived Operands -;------------------------------------------------------------- -; Destination -;------------------------------------------------------------- -; Rn direct -;------------------------------------------------------------- - -(define-pmacro (dst16-Rn-direct-operand xmode) - (begin - (define-derived-operand - (name (.sym dst16-Rn-direct- xmode)) - (comment (.str "m16c Rn direct destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Dst16Rn xmode))) - (syntax (.str "$Dst16Rn" xmode)) - (base-ifield f-12-4) - (encoding (+ (f-12-2 0) (.sym Dst16Rn xmode))) - (ifield-assertion (eq f-12-2 0)) - (getter (trunc xmode (.sym Dst16Rn xmode))) - (setter (set (.sym Dst16Rn xmode) newval)) - ) - ) -) - -(dst16-Rn-direct-operand QI) -(dst16-Rn-direct-operand HI) -(dst16-Rn-direct-operand SI) - -(define-derived-operand - (name dst16-Rn-direct-Ext-QI) - (comment "m16c Rn direct destination QI") - (attrs (machine 16)) - (mode HI) - (args (Dst16RnExtQI)) - (syntax "$Dst16RnExtQI") - (base-ifield f-12-4) - (encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0))) - (ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0))) - (getter (trunc QI (.sym Dst16RnExtQI))) - (setter (set Dst16RnExtQI newval)) -) - -(define-pmacro (dst32-Rn-direct-operand group base xmode) - (begin - (define-derived-operand - (name (.sym dst32-Rn-direct- group - xmode)) - (comment (.str "m32c Rn direct destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dst32Rn group xmode))) - (syntax (.str "$Dst32Rn" group xmode)) - (base-ifield (.sym f- base -6)) - (encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode))) - (ifield-assertion (eq (.sym f- base -3) 4)) - (getter (trunc xmode (.sym Dst32Rn group xmode))) - (setter (set (.sym Dst32Rn group xmode) newval)) - ) - ) -) - -(dst32-Rn-direct-operand Unprefixed 4 QI) -(dst32-Rn-direct-operand Prefixed 12 QI) -(dst32-Rn-direct-operand Unprefixed 4 HI) -(dst32-Rn-direct-operand Prefixed 12 HI) -(dst32-Rn-direct-operand Unprefixed 4 SI) -(dst32-Rn-direct-operand Prefixed 12 SI) - -(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode) - (begin - (define-derived-operand - (name (.sym dst32-Rn-direct- group - smode)) - (comment (.str "m32c Rn direct destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dst32Rn group smode))) - (syntax (.str "$Dst32Rn" group smode)) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1))) - (getter (trunc smode (.sym Dst32Rn group smode))) - (setter (set (.sym Dst32Rn group smode) newval)) - ) - ) -) - -(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI) -(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI) - -(define-derived-operand - (name dst32-R3-direct-Unprefixed-HI) - (comment "m32c R3 direct HI") - (attrs (machine 32)) - (mode HI) - (args (R3)) - (syntax "$R3") - (base-ifield f-4-6) - (encoding (+ (f-4-3 4) (f-8-2 #x1))) - (ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1))) - (getter (trunc HI R3)) - (setter (set R3 newval)) -) -;------------------------------------------------------------- -; An direct -;------------------------------------------------------------- - -(define-pmacro (dst16-An-direct-operand xmode) - (begin - (define-derived-operand - (name (.sym dst16-An-direct- xmode)) - (comment (.str "m16c An direct destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Dst16An xmode))) - (syntax (.str "$Dst16An" xmode)) - (base-ifield f-12-4) - (encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode))) - (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) - (getter (trunc xmode (.sym Dst16An xmode))) - (setter (set (.sym Dst16An xmode) newval)) - ) - ) -) - -(dst16-An-direct-operand QI) -(dst16-An-direct-operand HI) -(dst16-An-direct-operand SI) - -(define-pmacro (dst32-An-direct-operand group base1 base2 xmode) - (begin - (define-derived-operand - (name (.sym dst32-An-direct- group - xmode)) - (comment (.str "m32c An direct destination " xmode)) - (attrs (machine 32)) - (mode xmode) - (args ((.sym Dst32An group xmode))) - (syntax (.str "$Dst32An" group xmode)) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) - (getter (trunc xmode (.sym Dst32An group xmode))) - (setter (set (.sym Dst32An group xmode) newval)) - ) - ) -) - -(dst32-An-direct-operand Unprefixed 4 8 QI) -(dst32-An-direct-operand Prefixed 12 16 QI) -(dst32-An-direct-operand Unprefixed 4 8 HI) -(dst32-An-direct-operand Prefixed 12 16 HI) -(dst32-An-direct-operand Unprefixed 4 8 SI) -(dst32-An-direct-operand Prefixed 12 16 SI) - -;------------------------------------------------------------- -; An indirect -;------------------------------------------------------------- - -(define-pmacro (dst16-An-indirect-operand xmode) - (begin - (define-derived-operand - (name (.sym dst16-An-indirect- xmode)) - (comment (.str "m16c An indirect destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dst16An)) - (syntax "[$Dst16An]") - (base-ifield f-12-4) - (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) - (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) - (getter (mem16 xmode Dst16An)) - (setter (set (mem16 xmode Dst16An) newval)) - ) - ) -) - -(dst16-An-indirect-operand QI) -(dst16-An-indirect-operand HI) -(dst16-An-indirect-operand SI) - -(define-derived-operand - (name dst16-An-indirect-Ext-QI) - (comment "m16c An indirect destination QI") - (attrs (machine 16)) - (mode HI) - (args (Dst16An)) - (syntax "[$Dst16An]") - (base-ifield f-12-4) - (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) - (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) - (getter (mem16 QI Dst16An)) - (setter (set (mem16 HI Dst16An) newval)) -) - -(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode) - (begin - (define-derived-operand - (name (.sym dst32-An-indirect- group - smode)) - (comment (.str "m32c An indirect destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dst32An group))) - (syntax (.str "[$Dst32An" group "]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) - (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) - (const 0))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval - (.sym Dst32An group) (const 0))) -; (getter (mem32 smode (.sym Dst32An group))) -; (setter (set (mem32 dmode (.sym Dst32An group)) newval)) - ) - ) -) - -(dst32-An-indirect-operand Unprefixed 4 8 QI QI) -(dst32-An-indirect-operand Prefixed 12 16 QI QI) -(dst32-An-indirect-operand Unprefixed 4 8 HI HI) -(dst32-An-indirect-operand Prefixed 12 16 HI HI) -(dst32-An-indirect-operand Unprefixed 4 8 SI SI) -(dst32-An-indirect-operand Prefixed 12 16 SI SI) -(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI) -(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI) - -;------------------------------------------------------------- -; dsp:d[r] relative -;------------------------------------------------------------- - -(define-pmacro (dst16-relative-operand offset xmode) - (begin - (define-derived-operand - (name (.sym dst16- offset -8-SB-relative- xmode)) - (comment (.str "m16c dsp:8[sb] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[sb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) - (ifield-assertion (eq f-12-4 #xA)) - (getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb)))) - (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -16-SB-relative- xmode)) - (comment (.str "m16c dsp:16[sb] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[sb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) - (ifield-assertion (eq f-12-4 #xE)) - (getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb)))) - (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -8-FB-relative- xmode)) - (comment (.str "m16c dsp:8[fb] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Dsp- offset -s8))) - (syntax (.str "${Dsp-" offset "-s8}[fb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) - (ifield-assertion (eq f-12-4 #xB)) - (getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb)))) - (setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -8-An-relative- xmode)) - (comment (.str "m16c dsp:8[An] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dst16An (.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) - (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) - (getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An))) - (setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -16-An-relative- xmode)) - (comment (.str "m16c dsp:16[An] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dst16An (.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) - (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) - (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) - (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -20-An-relative- xmode)) - (comment (.str "m16c dsp:20[An] relative destination " xmode)) - (attrs (machine 16)) - (mode xmode) - (args (Dst16An (.sym Dsp- offset -u20))) - (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) - (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) - (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) - (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) - ) - ) -) - -(dst16-relative-operand 16 QI) -(dst16-relative-operand 24 QI) -(dst16-relative-operand 32 QI) -(dst16-relative-operand 40 QI) -(dst16-relative-operand 48 QI) -(dst16-relative-operand 16 HI) -(dst16-relative-operand 24 HI) -(dst16-relative-operand 32 HI) -(dst16-relative-operand 40 HI) -(dst16-relative-operand 48 HI) -(dst16-relative-operand 16 SI) -(dst16-relative-operand 24 SI) -(dst16-relative-operand 32 SI) -(dst16-relative-operand 40 SI) -(dst16-relative-operand 48 SI) - -(define-pmacro (dst16-relative-Ext-operand offset smode dmode) - (begin - (define-derived-operand - (name (.sym dst16- offset -8-SB-relative-Ext- smode)) - (comment (.str "m16c dsp:8[sb] relative destination " smode)) - (attrs (machine 16)) - (mode dmode) - (args ((.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[sb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8))) - (ifield-assertion (eq f-12-4 #xA)) - (getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) - (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -16-SB-relative-Ext- smode)) - (comment (.str "m16c dsp:16[sb] relative destination " smode)) - (attrs (machine 16)) - (mode dmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[sb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16))) - (ifield-assertion (eq f-12-4 #xE)) - (getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) - (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -8-FB-relative-Ext- smode)) - (comment (.str "m16c dsp:8[fb] relative destination " smode)) - (attrs (machine 16)) - (mode dmode) - (args ((.sym Dsp- offset -s8))) - (syntax (.str "${Dsp-" offset "-s8}[fb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8))) - (ifield-assertion (eq f-12-4 #xB)) - (getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) - (setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -8-An-relative-Ext- smode)) - (comment (.str "m16c dsp:8[An] relative destination " smode)) - (attrs (machine 16)) - (mode dmode) - (args (Dst16An (.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[$Dst16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An)) - (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) - (getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An))) - (setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval)) - ) - (define-derived-operand - (name (.sym dst16- offset -16-An-relative-Ext- smode)) - (comment (.str "m16c dsp:16[An] relative destination " smode)) - (attrs (machine 16)) - (mode dmode) - (args (Dst16An (.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[$Dst16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An)) - (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) - (getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An))) - (setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) - ) - ) -) - -(dst16-relative-Ext-operand 16 QI HI) - -(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode) - (begin - (define-derived-operand - (name (.sym dst32- offset -8-SB-relative- group - smode)) - (comment (.str "m32c dsp:8[sb] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[sb]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) - (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8))) -; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -16-SB-relative- group - smode)) - (comment (.str "m32c dsp:16[sb] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[sb]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) - (getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16))) -; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -8-FB-relative- group - smode)) - (comment (.str "m32c dsp:8[fb] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dsp- offset -s8))) - (syntax (.str "${Dsp-" offset "-s8}[fb]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) - (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8))) -; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -16-FB-relative- group - smode)) - (comment (.str "m32c dsp:16[fb] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dsp- offset -s16))) - (syntax (.str "${Dsp-" offset "-s16}[fb]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) - (getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16))) -; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -8-An-relative- group - smode)) - (comment (.str "m32c dsp:8[An] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dst32An group) (.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) - (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8))) -; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -16-An-relative- group - smode)) - (comment (.str "m32c dsp:16[An] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dst32An group) (.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) - (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16))) -; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -24-An-relative- group - smode)) - (comment (.str "m32c dsp:16[An] relative destination " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dst32An group) (.sym Dsp- offset -u24))) - (syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) - (getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24))) -; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group)))) -; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval)) - ) - ) -) - -(dst32-relative-operand 16 Unprefixed 4 8 QI QI) -(dst32-relative-operand 24 Unprefixed 4 8 QI QI) -(dst32-relative-operand 32 Unprefixed 4 8 QI QI) -(dst32-relative-operand 40 Unprefixed 4 8 QI QI) -(dst32-relative-operand 16 Unprefixed 4 8 HI HI) -(dst32-relative-operand 24 Unprefixed 4 8 HI HI) -(dst32-relative-operand 32 Unprefixed 4 8 HI HI) -(dst32-relative-operand 40 Unprefixed 4 8 HI HI) -(dst32-relative-operand 16 Unprefixed 4 8 SI SI) -(dst32-relative-operand 24 Unprefixed 4 8 SI SI) -(dst32-relative-operand 32 Unprefixed 4 8 SI SI) -(dst32-relative-operand 40 Unprefixed 4 8 SI SI) - -(dst32-relative-operand 24 Prefixed 12 16 QI QI) -(dst32-relative-operand 32 Prefixed 12 16 QI QI) -(dst32-relative-operand 40 Prefixed 12 16 QI QI) -(dst32-relative-operand 48 Prefixed 12 16 QI QI) -(dst32-relative-operand 24 Prefixed 12 16 HI HI) -(dst32-relative-operand 32 Prefixed 12 16 HI HI) -(dst32-relative-operand 40 Prefixed 12 16 HI HI) -(dst32-relative-operand 48 Prefixed 12 16 HI HI) -(dst32-relative-operand 24 Prefixed 12 16 SI SI) -(dst32-relative-operand 32 Prefixed 12 16 SI SI) -(dst32-relative-operand 40 Prefixed 12 16 SI SI) -(dst32-relative-operand 48 Prefixed 12 16 SI SI) - -(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI) -(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI) - -;------------------------------------------------------------- -; Absolute address -;------------------------------------------------------------- - -(define-pmacro (dst16-absolute offset xmode) - (begin - (define-derived-operand - (name (.sym dst16- offset -16-absolute- xmode)) - (comment (.str "m16c absolute address " xmode)) - (attrs (machine 16)) - (mode xmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16))) - (ifield-assertion (eq f-12-4 #xF)) - (getter (mem16 xmode (.sym Dsp- offset -u16))) - (setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval)) - ) - ) -) - -(dst16-absolute 16 QI) -(dst16-absolute 24 QI) -(dst16-absolute 32 QI) -(dst16-absolute 40 QI) -(dst16-absolute 48 QI) -(dst16-absolute 16 HI) -(dst16-absolute 24 HI) -(dst16-absolute 32 HI) -(dst16-absolute 40 HI) -(dst16-absolute 48 HI) -(dst16-absolute 16 SI) -(dst16-absolute 24 SI) -(dst16-absolute 32 SI) -(dst16-absolute 40 SI) -(dst16-absolute 48 SI) - -(define-derived-operand - (name dst16-16-16-absolute-Ext-QI) - (comment "m16c absolute address QI") - (attrs (machine 16)) - (mode HI) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}") - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xF) Dsp-16-u16)) - (ifield-assertion (eq f-12-4 #xF)) - (getter (mem16 QI Dsp-16-u16)) - (setter (set (mem16 HI Dsp-16-u16) newval)) -) - -(define-pmacro (dst32-absolute offset group base1 base2 smode dmode) - (begin - (define-derived-operand - (name (.sym dst32- offset -16-absolute- group - smode)) - (comment (.str "m32c absolute address " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) - (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16))) -; (getter (mem32 smode (.sym Dsp- offset -u16))) -; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval)) - ) - (define-derived-operand - (name (.sym dst32- offset -24-absolute- group - smode)) - (comment (.str "m32c absolute address " smode)) - (attrs (machine 32)) - (mode dmode) - (args ((.sym Dsp- offset -u24))) - (syntax (.str "${Dsp-" offset "-u24}")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) - (getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24))) - (setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24))) -; (getter (mem32 smode (.sym Dsp- offset -u24))) -; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval)) - ) - ) -) - -(dst32-absolute 16 Unprefixed 4 8 QI QI) -(dst32-absolute 24 Unprefixed 4 8 QI QI) -(dst32-absolute 32 Unprefixed 4 8 QI QI) -(dst32-absolute 40 Unprefixed 4 8 QI QI) -(dst32-absolute 16 Unprefixed 4 8 HI HI) -(dst32-absolute 24 Unprefixed 4 8 HI HI) -(dst32-absolute 32 Unprefixed 4 8 HI HI) -(dst32-absolute 40 Unprefixed 4 8 HI HI) -(dst32-absolute 16 Unprefixed 4 8 SI SI) -(dst32-absolute 24 Unprefixed 4 8 SI SI) -(dst32-absolute 32 Unprefixed 4 8 SI SI) -(dst32-absolute 40 Unprefixed 4 8 SI SI) - -(dst32-absolute 24 Prefixed 12 16 QI QI) -(dst32-absolute 32 Prefixed 12 16 QI QI) -(dst32-absolute 40 Prefixed 12 16 QI QI) -(dst32-absolute 48 Prefixed 12 16 QI QI) -(dst32-absolute 24 Prefixed 12 16 HI HI) -(dst32-absolute 32 Prefixed 12 16 HI HI) -(dst32-absolute 40 Prefixed 12 16 HI HI) -(dst32-absolute 48 Prefixed 12 16 HI HI) -(dst32-absolute 24 Prefixed 12 16 SI SI) -(dst32-absolute 32 Prefixed 12 16 SI SI) -(dst32-absolute 40 Prefixed 12 16 SI SI) -(dst32-absolute 48 Prefixed 12 16 SI SI) - -(dst32-absolute 16 ExtUnprefixed 4 8 QI HI) -(dst32-absolute 16 ExtUnprefixed 4 8 HI SI) - -;------------------------------------------------------------- -; An indirect indirect -;------------------------------------------------------------- - -;(define-pmacro (dst-An-indirect-indirect-operand xmode) -; (define-derived-operand -; (name (.sym dst32-An-indirect-indirect- xmode)) -; (comment (.str "m32c An indirect indirect destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dst32AnPrefixed)) -; (syntax (.str "[[$Dst32AnPrefixed]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed)) -; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0))) -; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed))) -; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval)) -; ) -;) - -; (dst-An-indirect-indirect-operand QI) -; (dst-An-indirect-indirect-operand HI) -; (dst-An-indirect-indirect-operand SI) - -;------------------------------------------------------------- -; Relative indirect -;------------------------------------------------------------- - -(define-pmacro (dst-relative-indirect-operand offset xmode) - (begin -; (define-derived-operand -; (name (.sym dst32- offset -8-SB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:8[sb] relative destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -u8))) -; (syntax (.str "[${Dsp-" offset "-u8}[sb]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8))) -; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb))))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -16-SB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:16[sb] relative destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -u16))) -; (syntax (.str "[${Dsp-" offset "-u16}[sb]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16))) -; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb))))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -8-FB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:8[fb] relative destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -s8))) -; (syntax (.str "[${Dsp-" offset "-s8}[fb]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8))) -; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb))))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -16-FB-relative-indirect- xmode)) -; (comment (.str "m32c dsp:16[fb] relative destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -s16))) -; (syntax (.str "[${Dsp-" offset "-s16}[fb]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16))) -; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb))))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -8-An-relative-indirect- xmode)) -; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dst32AnPrefixed (.sym Dsp- offset -u8))) -; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed)) -; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed)))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -16-An-relative-indirect- xmode)) -; (comment (.str "m32c dsp:16[An] relative destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dst32AnPrefixed (.sym Dsp- offset -u16))) -; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed)) -; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed)))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -24-An-relative-indirect- xmode)) -; (comment (.str "m32c dsp:24[An] relative destination " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args (Dst32AnPrefixed (.sym Dsp- offset -u24))) -; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed)) -; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0))) -; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed)))) -; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval)) -; ) - ) -) - -; (dst-relative-indirect-operand 24 QI) -; (dst-relative-indirect-operand 32 QI) -; (dst-relative-indirect-operand 40 QI) -; (dst-relative-indirect-operand 48 QI) -; (dst-relative-indirect-operand 24 HI) -; (dst-relative-indirect-operand 32 HI) -; (dst-relative-indirect-operand 40 HI) -; (dst-relative-indirect-operand 48 HI) -; (dst-relative-indirect-operand 24 SI) -; (dst-relative-indirect-operand 32 SI) -; (dst-relative-indirect-operand 40 SI) -; (dst-relative-indirect-operand 48 SI) - -;------------------------------------------------------------- -; Absolute indirect -;------------------------------------------------------------- - -(define-pmacro (dst-absolute-indirect offset xmode) - (begin -; (define-derived-operand -; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode)) -; (comment (.str "m32c absolute indirect address " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -u16))) -; (syntax (.str "[${Dsp-" offset "-u16}]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16))) -; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3))) -; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16)))) -; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode)) -; (comment (.str "m32c absolute indirect address " xmode)) -; (attrs (machine 32)) -; (mode xmode) -; (args ((.sym Dsp- offset -u24))) -; (syntax (.str "[${Dsp-" offset "-u24}]")) -; (base-ifield f-12-6) -; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24))) -; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2))) -; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24)))) -; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval)) -; ) - ) -) - -(dst-absolute-indirect 24 QI) -(dst-absolute-indirect 32 QI) -(dst-absolute-indirect 40 QI) -(dst-absolute-indirect 48 QI) -(dst-absolute-indirect 24 HI) -(dst-absolute-indirect 32 HI) -(dst-absolute-indirect 40 HI) -(dst-absolute-indirect 48 HI) -(dst-absolute-indirect 24 SI) -(dst-absolute-indirect 32 SI) -(dst-absolute-indirect 40 SI) -(dst-absolute-indirect 48 SI) - -;------------------------------------------------------------- -; Bit operands -;------------------------------------------------------------- -(define-pmacro (get-register-bit reg bitno) - (and (srl reg bitno) 1) -) - -(define-pmacro (set-register-bit reg bitno value) - (set reg (or (and reg (inv (sll 1 bitno))) - (sll (and QI value 1) bitno))) -) - -(define-pmacro (get-memory-bit mach base bitno) - (and (srl (mem-mach mach QI (add base (div bitno 8))) - (mod bitno 8)) - 1) -) - -(define-pmacro (set-memory-bit mach base bitno value) - (sequence ((USI addr)) - (set addr (add base (div bitno 8))) - (set (mem-mach mach QI addr) - (or (and (mem-mach mach QI addr) - (inv (sll 1 (mod bitno 8)))) - (sll (and QI value 1) (mod bitno 8))))) -) - -;------------------------------------------------------------- -; Rn direct -;------------------------------------------------------------- - -(define-derived-operand - (name bit16-Rn-direct) - (comment "m16c Rn direct bit") - (attrs (machine 16)) - (mode BI) - (args (Bitno16R Bit16Rn)) - (syntax "$Bitno16R,$Bit16Rn") - (base-ifield f-12-4) - (encoding (+ (f-12-2 0) Bit16Rn Bitno16R)) - (ifield-assertion (eq f-12-2 0)) - (getter (get-register-bit Bit16Rn Bitno16R)) - (setter (set-register-bit Bit16Rn Bitno16R newval)) -) - -(define-pmacro (bit32-Rn-direct-operand group base) - (begin - (define-derived-operand - (name (.sym bit32-Rn-direct- group)) - (comment "m32c Rn direct bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym Bitno32 group) (.sym Bit32Rn group))) - (syntax (.str "$Bitno32" group ",$Bit32Rn" group)) - (base-ifield (.sym f- base -6)) - (encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group))) - (ifield-assertion (eq (.sym f- base -3) 4)) - (getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group))) - (setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval)) - ) - ) -) - -(bit32-Rn-direct-operand Unprefixed 4) -(bit32-Rn-direct-operand Prefixed 12) - -;------------------------------------------------------------- -; An direct -;------------------------------------------------------------- - -(define-derived-operand - (name bit16-An-direct) - (comment "m16c An direct bit") - (attrs (machine 16)) - (mode BI) - (args (Bitno16R Bit16An)) - (syntax "$Bitno16R,$Bit16An") - (base-ifield f-12-4) - (encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R)) - (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0))) - (getter (get-register-bit Bit16An Bitno16R)) - (setter (set-register-bit Bit16An Bitno16R newval)) -) - -(define-pmacro (bit32-An-direct-operand group base1 base2) - (begin - (define-derived-operand - (name (.sym bit32-An-direct- group)) - (comment "m32c An direct bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym Bitno32 group) (.sym Bit32An group))) - (syntax (.str "$Bitno32" group ",$Bit32An" group)) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1))) - (getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group))) - (setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval)) - ) - ) -) - -(bit32-An-direct-operand Unprefixed 4 8) -(bit32-An-direct-operand Prefixed 12 16) - -;------------------------------------------------------------- -; An indirect -;------------------------------------------------------------- - -(define-derived-operand - (name bit16-An-indirect) - (comment "m16c An indirect bit") - (attrs (machine 16)) - (mode BI) - (args (Bit16An)) - (syntax "[$Bit16An]") - (base-ifield f-12-4) - (encoding (+ (f-12-2 1) (f-14-1 1) Bit16An)) - (ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1))) - (getter (get-memory-bit 16 0 Bit16An)) - (setter (set-memory-bit 16 0 Bit16An newval)) -) - -(define-pmacro (bit32-An-indirect-operand group base1 base2) - (begin - (define-derived-operand - (name (.sym bit32-An-indirect- group)) - (comment "m32c An indirect destination ") - (attrs (machine 32)) - (mode BI) - (args ((.sym Bitno32 group) (.sym Bit32An group))) - (syntax (.str "$Bitno32" group ",[$Bit32An" group "]")) - (base-ifield (.sym f- base1 -6)) - (encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0))) - (getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group))) - (setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval)) - ) - ) -) - -(bit32-An-indirect-operand Unprefixed 4 8) -(bit32-An-indirect-operand Prefixed 12 16) - -;------------------------------------------------------------- -; dsp:d[r] relative -;------------------------------------------------------------- - -(define-pmacro (bit16-relative-operand offset) - (begin - (define-derived-operand - (name (.sym bit16- offset -8-SB-relative)) - (comment (.str "m16c dsp:8[sb] relative bit " xmode)) - (attrs (machine 16)) - (mode BI) - (args ((.sym BitBase16- offset -u8))) - (syntax (.str "${BitBase16-" offset "-u8}[sb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8))) - (ifield-assertion (eq f-12-4 #xA)) - (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8))) - (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval)) - ) - (define-derived-operand - (name (.sym bit16- offset -16-SB-relative)) - (comment (.str "m16c dsp:16[sb] relative bit " xmode)) - (attrs (machine 16)) - (mode BI) - (args ((.sym BitBase16- offset -u16))) - (syntax (.str "${BitBase16-" offset "-u16}[sb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16))) - (ifield-assertion (eq f-12-4 #xE)) - (getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16))) - (setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval)) - ) - (define-derived-operand - (name (.sym bit16- offset -8-FB-relative)) - (comment (.str "m16c dsp:8[fb] relative bit " xmode)) - (attrs (machine 16)) - (mode BI) - (args ((.sym BitBase16- offset -s8))) - (syntax (.str "${BitBase16-" offset "-s8}[fb]")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8))) - (ifield-assertion (eq f-12-4 #xB)) - (getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8))) - (setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval)) - ) - (define-derived-operand - (name (.sym bit16- offset -8-An-relative)) - (comment (.str "m16c dsp:8[An] relative bit " xmode)) - (attrs (machine 16)) - (mode BI) - (args (Bit16An (.sym Dsp- offset -u8))) - (syntax (.str "${Dsp-" offset "-u8}[$Bit16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An)) - (ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0))) - (getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An)) - (setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval)) - ) - (define-derived-operand - (name (.sym bit16- offset -16-An-relative)) - (comment (.str "m16c dsp:16[An] relative bit " xmode)) - (attrs (machine 16)) - (mode BI) - (args (Bit16An (.sym Dsp- offset -u16))) - (syntax (.str "${Dsp-" offset "-u16}[$Bit16An]")) - (base-ifield f-12-4) - (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An)) - (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) - (getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An)) - (setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval)) - ) - ) -) - -(bit16-relative-operand 16) - -(define-pmacro (bit32-relative-operand offset group base1 base2) - (begin - (define-derived-operand - (name (.sym bit32- offset -11-SB-relative- group)) - (comment "m32c bit,base:11[sb] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u11- group))) - (syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2))) - (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group))) - (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -19-SB-relative- group)) - (comment "m32c bit,base:19[sb] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u19- group))) - (syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2))) - (getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group))) - (setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -11-FB-relative- group)) - (comment "m32c bit,base:11[fb] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -s11- group))) - (syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3))) - (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group))) - (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -19-FB-relative- group)) - (comment "m32c bit,base:19[fb] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -s19- group))) - (syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3))) - (getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group))) - (setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -11-An-relative- group)) - (comment "m32c bit,base:11[An] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group))) - (syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0))) - (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group))) - (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -19-An-relative- group)) - (comment "m32c bit,base:19[An] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group))) - (syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0))) - (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group))) - (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -27-An-relative- group)) - (comment "m32c bit,base:27[An] relative bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group))) - (syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0))) - (getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group))) - (setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval)) - ) - ) -) - -(bit32-relative-operand 16 Unprefixed 4 8) -(bit32-relative-operand 24 Prefixed 12 16) - -(define-derived-operand - (name bit16-11-SB-relative-S) - (comment "m16c bit,base:11[sb] relative bit") - (attrs (machine 16)) - (mode BI) - (args (BitBase16-8-u11-S)) - (syntax "${BitBase16-8-u11-S}[sb]") - (base-ifield (.sym f-5-3)) - (encoding (+ BitBase16-8-u11-S)) -; (ifield-assertion (#t)) - (getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S)) - (setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval)) -) - -(define-derived-operand - (name Rn16-push-S-derived) - (comment "m16c r0[lh] for push,pop short version") - (attrs (machine 16)) - (mode QI) - (args (Rn16-push-S)) - (syntax "${Rn16-push-S}") - (base-ifield (.sym f-4-1)) - (encoding (+ Rn16-push-S)) -; (ifield-assertion (#t)) - (getter (trunc QI Rn16-push-S)) - (setter (set Rn16-push-S newval)) -) - -(define-derived-operand - (name An16-push-S-derived) - (comment "m16c r0[lh] for push,pop short version") - (attrs (machine 16)) - (mode HI) - (args (An16-push-S)) - (syntax "${An16-push-S}") - (base-ifield (.sym f-4-1)) - (encoding (+ An16-push-S)) -; (ifield-assertion (#t)) - (getter (trunc QI An16-push-S)) - (setter (set An16-push-S newval)) -) - -;------------------------------------------------------------- -; Absolute address -;------------------------------------------------------------- - -(define-pmacro (bit16-absolute offset) - (begin - (define-derived-operand - (name (.sym bit16- offset -16-absolute)) - (comment "m16c absolute address") - (attrs (machine 16)) - (mode BI) - (args ((.sym BitBase16- offset -u16))) - (syntax (.str "${BitBase16-" offset "-u16}")) - (base-ifield f-12-4) - (encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16))) - (ifield-assertion (eq f-12-4 #xF)) - (getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16))) - (setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval)) - ) - ) -) - -(bit16-absolute 16) - -(define-pmacro (bit32-absolute offset group base1 base2) - (begin - (define-derived-operand - (name (.sym bit32- offset -19-absolute- group)) - (comment "m32c absolute address bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u19- group))) - (syntax (.str "${BitBase32-" offset "-u19-" group "}")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3))) - (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group))) - (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval)) - ) - (define-derived-operand - (name (.sym bit32- offset -27-absolute- group)) - (comment "m32c absolute address bit") - (attrs (machine 32)) - (mode BI) - (args ((.sym BitBase32- offset -u27- group))) - (syntax (.str "${BitBase32-" offset "-u27-" group "}")) - (base-ifield (.sym f- base1 -12)) - (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group))) - (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2))) - (getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group))) - (setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval)) - ) - ) -) - -(bit32-absolute 16 Unprefixed 4 8) -(bit32-absolute 24 Prefixed 12 16) - -;------------------------------------------------------------- -; Destination operands for short fomat insns -;------------------------------------------------------------- - -(define-derived-operand - (name dst16-3-S-R0l-direct-QI) - (comment "m16c R0l direct QI") - (attrs (machine 16)) - (mode QI) - (args (R0l)) - (syntax "r0l") - (base-ifield f-5-3) - (encoding (+ (f-5-3 4))) - (ifield-assertion (eq f-5-3 4)) - (getter (trunc QI R0l)) - (setter (set R0l newval)) -) -(define-derived-operand - (name dst16-3-S-R0h-direct-QI) - (comment "m16c R0h direct QI") - (attrs (machine 16)) - (mode QI) - (args (R0h)) - (syntax "r0h") - (base-ifield f-5-3) - (encoding (+ (f-5-3 3))) - (ifield-assertion (eq f-5-3 3)) - (getter (trunc QI R0h)) - (setter (set R0h newval)) -) -(define-derived-operand - (name dst16-3-S-8-8-SB-relative-QI) - (comment "m16c SB relative QI") - (attrs (machine 16)) - (mode QI) - (args (Dsp-8-u8)) - (syntax "${Dsp-8-u8}[sb]") - (base-ifield f-5-3) - (encoding (+ (f-5-3 5) Dsp-8-u8)) - (ifield-assertion (eq f-5-3 5)) - (getter (mem16 QI (add Dsp-8-u8 (reg h-sb)))) - (setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval)) -) -(define-derived-operand - (name dst16-3-S-8-8-FB-relative-QI) - (comment "m16c FB relative QI") - (attrs (machine 16)) - (mode QI) - (args (Dsp-8-s8)) - (syntax "${Dsp-8-s8}[fb]") - (base-ifield f-5-3) - (encoding (+ (f-5-3 6) Dsp-8-s8)) - (ifield-assertion (eq f-5-3 6)) - (getter (mem16 QI (add Dsp-8-s8 (reg h-fb)))) - (setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval)) -) -(define-derived-operand - (name dst16-3-S-8-16-absolute-QI) - (comment "m16c absolute address QI") - (attrs (machine 16)) - (mode QI) - (args (Dsp-8-u16)) - (syntax "${Dsp-8-u16}") - (base-ifield f-5-3) - (encoding (+ (f-5-3 7) Dsp-8-u16)) - (ifield-assertion (eq f-5-3 7)) - (getter (mem16 QI Dsp-8-u16)) - (setter (set (mem16 QI Dsp-8-u16) newval)) -) -(define-derived-operand - (name dst16-3-S-16-8-SB-relative-QI) - (comment "m16c SB relative QI") - (attrs (machine 16)) - (mode QI) - (args (Dsp-16-u8)) - (syntax "${Dsp-16-u8}[sb]") - (base-ifield f-5-3) - (encoding (+ (f-5-3 5) Dsp-16-u8)) - (ifield-assertion (eq f-5-3 5)) - (getter (mem16 QI (add Dsp-16-u8 (reg h-sb)))) - (setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval)) -) -(define-derived-operand - (name dst16-3-S-16-8-FB-relative-QI) - (comment "m16c FB relative QI") - (attrs (machine 16)) - (mode QI) - (args (Dsp-16-s8)) - (syntax "${Dsp-16-s8}[fb]") - (base-ifield f-5-3) - (encoding (+ (f-5-3 6) Dsp-16-s8)) - (ifield-assertion (eq f-5-3 6)) - (getter (mem16 QI (add Dsp-16-s8 (reg h-fb)))) - (setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval)) -) -(define-derived-operand - (name dst16-3-S-16-16-absolute-QI) - (comment "m16c absolute address QI") - (attrs (machine 16)) - (mode QI) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}") - (base-ifield f-5-3) - (encoding (+ (f-5-3 7) Dsp-16-u16)) - (ifield-assertion (eq f-5-3 7)) - (getter (mem16 QI Dsp-16-u16)) - (setter (set (mem16 QI Dsp-16-u16) newval)) -) -(define-derived-operand - (name srcdst16-r0l-r0h-S-derived) - (comment "m16c r0l/r0h operand for short format insns") - (attrs (machine 16)) - (mode SI) - (args (SrcDst16-r0l-r0h-S-normal)) - (syntax "${SrcDst16-r0l-r0h-S-normal}") - (base-ifield f-6-3) - (encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal)) - (ifield-assertion (eq f-6-2 0)) - (getter (trunc SI SrcDst16-r0l-r0h-S-normal)) - (setter ()) ; no setter -) -(define-derived-operand - (name dst32-2-S-R0l-direct-QI) - (comment "m32c R0l direct QI") - (attrs (machine 32)) - (mode QI) - (args (R0l)) - (syntax "r0l") - (base-ifield f-2-2) - (encoding (+ (f-2-2 0))) - (ifield-assertion (eq f-2-2 0)) - (getter (trunc QI R0l)) - (setter (set R0l newval)) -) -(define-derived-operand - (name dst32-2-S-R0-direct-HI) - (comment "m32c R0 direct HI") - (attrs (machine 32)) - (mode HI) - (args (R0)) - (syntax "r0") - (base-ifield f-2-2) - (encoding (+ (f-2-2 0))) - (ifield-assertion (eq f-2-2 0)) - (getter (trunc HI R0)) - (setter (set R0 newval)) -) -(define-derived-operand - (name dst32-1-S-A0-direct-HI) - (comment "m32c A0 direct HI") - (attrs (machine 32)) - (mode HI) - (args (A0)) - (syntax "a0") - (base-ifield f-7-1) - (encoding (+ (f-7-1 0))) - (ifield-assertion (eq f-7-1 0)) - (getter (trunc HI A0)) - (setter (set A0 newval)) -) -(define-derived-operand - (name dst32-1-S-A1-direct-HI) - (comment "m32c A1 direct HI") - (attrs (machine 32)) - (mode HI) - (args (A1)) - (syntax "a1") - (base-ifield f-7-1) - (encoding (+ (f-7-1 1))) - (ifield-assertion (eq f-7-1 1)) - (getter (trunc HI A1)) - (setter (set A1 newval)) -) -(define-pmacro (dst32-2-S-operands xmode) - (begin - (define-derived-operand - (name (.sym dst32-2-S-8-SB-relative- xmode)) - (comment "m32c SB relative for short binary insns") - (attrs (machine 32)) - (mode xmode) - (args (Dsp-8-u8)) - (syntax "${Dsp-8-u8}[sb]") - (base-ifield f-2-2) - (encoding (+ (f-2-2 2) Dsp-8-u8)) - (ifield-assertion (eq f-2-2 2)) - (getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8)) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8)) -; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb)))) -; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval)) - ) - (define-derived-operand - (name (.sym dst32-2-S-8-FB-relative- xmode)) - (comment "m32c FB relative for short binary insns") - (attrs (machine 32)) - (mode xmode) - (args (Dsp-8-s8)) - (syntax "${Dsp-8-s8}[fb]") - (base-ifield f-2-2) - (encoding (+ (f-2-2 3) Dsp-8-s8)) - (ifield-assertion (eq f-2-2 3)) - (getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8)) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8)) -; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb)))) -; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval)) - ) - (define-derived-operand - (name (.sym dst32-2-S-16-absolute- xmode)) - (comment "m32c absolute address for short binary insns") - (attrs (machine 32)) - (mode xmode) - (args (Dsp-8-u16)) - (syntax "${Dsp-8-u16}") - (base-ifield f-2-2) - (encoding (+ (f-2-2 1) Dsp-8-u16)) - (ifield-assertion (eq f-2-2 1)) - (getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16)) - (setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16)) -; (getter (mem32 xmode Dsp-8-u16)) -; (setter (set (mem32 xmode Dsp-8-u16) newval)) - ) -; (define-derived-operand -; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode)) -; (comment "m32c SB relative for short binary insns") -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-16-u8)) -; (syntax "[${Dsp-16-u8}[sb]]") -; (base-ifield f-10-2) -; (encoding (+ (f-10-2 2) Dsp-16-u8)) -; (ifield-assertion (eq f-10-2 2)) -; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb))))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode)) -; (comment "m32c FB relative for short binary insns") -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-16-s8)) -; (syntax "[${Dsp-16-s8}[fb]]") -; (base-ifield f-10-2) -; (encoding (+ (f-10-2 3) Dsp-16-s8)) -; (ifield-assertion (eq f-10-2 3)) -; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb))))) -; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval)) -; ) -; (define-derived-operand -; (name (.sym dst32-2-S-16-absolute-indirect- xmode)) -; (comment "m32c absolute address for short binary insns") -; (attrs (machine 32)) -; (mode xmode) -; (args (Dsp-16-u16)) -; (syntax "[${Dsp-16-u16}]") -; (base-ifield f-10-2) -; (encoding (+ (f-10-2 1) Dsp-16-u16)) -; (ifield-assertion (eq f-10-2 1)) -; (getter (mem32 xmode (indirect-addr Dsp-16-u16))) -; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval)) -; ) - ) -) - -(dst32-2-S-operands QI) -(dst32-2-S-operands HI) -(dst32-2-S-operands SI) - -;============================================================= -; Anyof operands -;------------------------------------------------------------- -; Source operands with no additional fields -;------------------------------------------------------------- - -(define-pmacro (src16-basic-operand xmode) - (begin - (define-anyof-operand - (name (.sym src16-basic- xmode)) - (comment (.str "m16c source operand of size " xmode " with no additional fields")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym src16-Rn-direct- xmode) - (.sym src16-An-direct- xmode) - (.sym src16-An-indirect- xmode) - ) - ) - ) -) -(src16-basic-operand QI) -(src16-basic-operand HI) - -(define-pmacro (src32-basic-operand xmode) - (begin - (define-anyof-operand - (name (.sym src32-basic-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with no additional fields")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-Rn-direct-Unprefixed- xmode) - (.sym src32-An-direct-Unprefixed- xmode) - (.sym src32-An-indirect-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym src32-basic-Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with no additional fields")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-Rn-direct-Prefixed- xmode) - (.sym src32-An-direct-Prefixed- xmode) - (.sym src32-An-indirect-Prefixed- xmode) - ) - ) -; (define-anyof-operand -; (name (.sym src32-basic-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym src32-An-indirect-indirect- xmode) -; ) -; ) - ) -) - -(src32-basic-operand QI) -(src32-basic-operand HI) -(src32-basic-operand SI) - -(define-anyof-operand - (name src32-basic-ExtPrefixed-QI) - (comment "m32c source operand of size QI with no additional fields") - (attrs (machine 32)) - (mode QI) - (choices - src32-Rn-direct-Prefixed-QI - src32-An-indirect-Prefixed-QI - ) -) - -;------------------------------------------------------------- -; Source operands with additional fields at offset 16 bits -;------------------------------------------------------------- - -(define-pmacro (src16-16-operand xmode) - (begin - (define-anyof-operand - (name (.sym src16-16-8- xmode)) - (comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym src16-16-8-An-relative- xmode) - (.sym src16-16-8-SB-relative- xmode) - (.sym src16-16-8-FB-relative- xmode) - ) - ) - (define-anyof-operand - (name (.sym src16-16-16- xmode)) - (comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym src16-16-16-An-relative- xmode) - (.sym src16-16-16-SB-relative- xmode) - (.sym src16-16-16-absolute- xmode) - ) - ) - ) -) -(src16-16-operand QI) -(src16-16-operand HI) - -(define-pmacro (src32-16-operand xmode) - (begin - (define-anyof-operand - (name (.sym src32-16-8-Unprefixed- xmode)) - (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-16-8-An-relative-Unprefixed- xmode) - (.sym src32-16-8-SB-relative-Unprefixed- xmode) - (.sym src32-16-8-FB-relative-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym src32-16-16-Unprefixed- xmode)) - (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-16-16-An-relative-Unprefixed- xmode) - (.sym src32-16-16-SB-relative-Unprefixed- xmode) - (.sym src32-16-16-FB-relative-Unprefixed- xmode) - (.sym src32-16-16-absolute-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym src32-16-24-Unprefixed- xmode)) - (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-16-24-An-relative-Unprefixed- xmode) - (.sym src32-16-24-absolute-Unprefixed- xmode) - ) - ) - ) -) - -(src32-16-operand QI) -(src32-16-operand HI) -(src32-16-operand SI) - -;------------------------------------------------------------- -; Source operands with additional fields at offset 24 bits -;------------------------------------------------------------- - -(define-pmacro (src-24-operand group xmode) - (begin - (define-anyof-operand - (name (.sym src32-24-8- group - xmode)) - (comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-24-8-An-relative- group - xmode) - (.sym src32-24-8-SB-relative- group - xmode) - (.sym src32-24-8-FB-relative- group - xmode) - ) - ) - (define-anyof-operand - (name (.sym src32-24-16- group - xmode)) - (comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-24-16-An-relative- group - xmode) - (.sym src32-24-16-SB-relative- group - xmode) - (.sym src32-24-16-FB-relative- group - xmode) - (.sym src32-24-16-absolute- group - xmode) - ) - ) - (define-anyof-operand - (name (.sym src32-24-24- group - xmode)) - (comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym src32-24-24-An-relative- group - xmode) - (.sym src32-24-24-absolute- group - xmode) - ) - ) - ) -) - -(src-24-operand Prefixed QI) -(src-24-operand Prefixed HI) -(src-24-operand Prefixed SI) - -(define-pmacro (src-24-indirect-operand xmode) - (begin -; (define-anyof-operand -; (name (.sym src32-24-8-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym src32-24-8-An-relative-indirect- xmode) -; (.sym src32-24-8-SB-relative-indirect- xmode) -; (.sym src32-24-8-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym src32-24-16-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym src32-24-16-An-relative-indirect- xmode) -; (.sym src32-24-16-SB-relative-indirect- xmode) -; (.sym src32-24-16-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym src32-24-24-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym src32-24-24-An-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym src32-24-16-absolute-indirect- xmode)) -; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym src32-24-16-absolute-indirect-derived- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym src32-24-24-absolute-indirect- xmode)) -; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym src32-24-24-absolute-indirect-derived- xmode) -; ) -; ) - ) -) - -; (src-24-indirect-operand QI) -; (src-24-indirect-operand HI) -; (src-24-indirect-operand SI) - -;------------------------------------------------------------- -; Destination operands with no additional fields -;------------------------------------------------------------- - -(define-pmacro (dst16-basic-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst16-basic- xmode)) - (comment (.str "m16c destination operand of size " xmode " with no additional fields")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-Rn-direct- xmode) - (.sym dst16-An-direct- xmode) - (.sym dst16-An-indirect- xmode) - ) - ) - ) -) - -(dst16-basic-operand QI) -(dst16-basic-operand HI) -(dst16-basic-operand SI) - -(define-pmacro (dst32-basic-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst32-basic-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with no additional fields")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Unprefixed- xmode) - (.sym dst32-An-direct-Unprefixed- xmode) - (.sym dst32-An-indirect-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-basic-Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with no additional fields")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Prefixed- xmode) - (.sym dst32-An-direct-Prefixed- xmode) - (.sym dst32-An-indirect-Prefixed- xmode) - ) - ) - ) -) - -(dst32-basic-operand QI) -(dst32-basic-operand HI) -(dst32-basic-operand SI) - -;------------------------------------------------------------- -; Destination operands with possible additional fields at offset 16 bits -;------------------------------------------------------------- - -(define-pmacro (dst16-16-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst16-16- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-Rn-direct- xmode) - (.sym dst16-An-direct- xmode) - (.sym dst16-An-indirect- xmode) - (.sym dst16-16-8-An-relative- xmode) - (.sym dst16-16-16-An-relative- xmode) - (.sym dst16-16-8-SB-relative- xmode) - (.sym dst16-16-16-SB-relative- xmode) - (.sym dst16-16-8-FB-relative- xmode) - (.sym dst16-16-16-absolute- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst16-16-8- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-16-8-An-relative- xmode) - (.sym dst16-16-8-SB-relative- xmode) - (.sym dst16-16-8-FB-relative- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst16-16-16- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-16-16-An-relative- xmode) - (.sym dst16-16-16-SB-relative- xmode) - (.sym dst16-16-16-absolute- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst16-16-16sa- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-16-16-SB-relative- xmode) - (.sym dst16-16-16-absolute- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst16-16-20ar- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-16-20-An-relative- xmode) - ) - ) - ) -) - -(dst16-16-operand QI) -(dst16-16-operand HI) -(dst16-16-operand SI) - -(define-anyof-operand - (name dst16-16-Ext-QI) - (comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16") - (attrs (machine 16)) - (mode QI) - (choices - dst16-Rn-direct-Ext-QI - dst16-An-indirect-Ext-QI - dst16-16-8-An-relative-Ext-QI - dst16-16-16-An-relative-Ext-QI - dst16-16-8-SB-relative-Ext-QI - dst16-16-16-SB-relative-Ext-QI - dst16-16-8-FB-relative-Ext-QI - dst16-16-16-absolute-Ext-QI - ) -) - -(define-derived-operand - (name dst16-An-indirect-Mova-HI) - (comment "m16c addressof An indirect destination HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dst16An)) - (syntax "[$Dst16An]") - (base-ifield f-12-4) - (encoding (+ (f-12-2 1) (f-14-1 1) Dst16An)) - (ifield-assertion - (andif (eq f-12-2 1) (eq f-14-1 1))) - (getter Dst16An) - (setter (nop)) - ) - -(define-derived-operand - (name dst16-16-8-An-relative-Mova-HI) - (comment - "m16c addressof dsp:8[An] relative destination HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dst16An Dsp-16-u8)) - (syntax "${Dsp-16-u8}[$Dst16An]") - (base-ifield f-12-4) - (encoding - (+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An)) - (ifield-assertion - (andif (eq f-12-2 2) (eq f-14-1 0))) - (getter (add Dsp-16-u8 Dst16An)) - (setter (nop)) -) -(define-derived-operand - (name dst16-16-16-An-relative-Mova-HI) - (comment - "m16c addressof dsp:16[An] relative destination HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dst16An Dsp-16-u16)) - (syntax "${Dsp-16-u16}[$Dst16An]") - (base-ifield f-12-4) - (encoding - (+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An)) - (ifield-assertion - (andif (eq f-12-2 3) (eq f-14-1 0))) - (getter (add Dsp-16-u16 Dst16An)) - (setter (nop)) - ) -(define-derived-operand - (name dst16-16-8-SB-relative-Mova-HI) - (comment - "m16c addressof dsp:8[sb] relative destination HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dsp-16-u8)) - (syntax "${Dsp-16-u8}[sb]") - (base-ifield f-12-4) - (encoding (+ (f-12-4 10) Dsp-16-u8)) - (ifield-assertion (eq f-12-4 10)) - (getter (add Dsp-16-u8 (reg h-sb))) - (setter (nop)) -) -(define-derived-operand - (name dst16-16-16-SB-relative-Mova-HI) - (comment - "m16c addressof dsp:16[sb] relative destination HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}[sb]") - (base-ifield f-12-4) - (encoding (+ (f-12-4 14) Dsp-16-u16)) - (ifield-assertion (eq f-12-4 14)) - (getter (add Dsp-16-u16 (reg h-sb))) - (setter (nop)) - ) -(define-derived-operand - (name dst16-16-8-FB-relative-Mova-HI) - (comment - "m16c addressof dsp:8[fb] relative destination HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dsp-16-s8)) - (syntax "${Dsp-16-s8}[fb]") - (base-ifield f-12-4) - (encoding (+ (f-12-4 11) Dsp-16-s8)) - (ifield-assertion (eq f-12-4 11)) - (getter (add Dsp-16-s8 (reg h-fb))) - (setter (nop)) - ) -(define-derived-operand - (name dst16-16-16-absolute-Mova-HI) - (comment "m16c addressof absolute address HI") - (attrs (ISA m16c)) - (mode HI) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}") - (base-ifield f-12-4) - (encoding (+ (f-12-4 15) Dsp-16-u16)) - (ifield-assertion (eq f-12-4 15)) - (getter Dsp-16-u16) - (setter (nop)) - ) - -(define-anyof-operand - (name dst16-16-Mova-HI) - (comment "m16c addressof destination operand of size HI with additional fields at offset 16") - (attrs (machine 16)) - (mode HI) - (choices - dst16-An-indirect-Mova-HI - dst16-16-8-An-relative-Mova-HI - dst16-16-16-An-relative-Mova-HI - dst16-16-8-SB-relative-Mova-HI - dst16-16-16-SB-relative-Mova-HI - dst16-16-8-FB-relative-Mova-HI - dst16-16-16-absolute-Mova-HI - ) -) - -(define-derived-operand - (name dst32-An-indirect-Unprefixed-Mova-SI) - (comment "m32c addressof An indirect destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dst32AnUnprefixed)) - (syntax "[$Dst32AnUnprefixed]") - (base-ifield f-4-6) - (encoding - (+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed)) - (ifield-assertion - (andif (eq f-4-3 0) (eq f-8-1 0))) - (getter Dst32AnUnprefixed) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-8-An-relative-Unprefixed-Mova-SI) - (comment "m32c addressof dsp:8[An] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dst32AnUnprefixed Dsp-16-u8)) - (syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]") - (base-ifield f-4-6) - (encoding - (+ (f-4-3 1) - (f-8-1 0) - Dsp-16-u8 - Dst32AnUnprefixed)) - (ifield-assertion - (andif (eq f-4-3 1) (eq f-8-1 0))) - (getter (add Dsp-16-u8 Dst32AnUnprefixed)) - (setter (nop)) -) - -(define-derived-operand - (name dst32-16-16-An-relative-Unprefixed-Mova-SI) - (comment - "m32c addressof dsp:16[An] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dst32AnUnprefixed Dsp-16-u16)) - (syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]") - (base-ifield f-4-6) - (encoding - (+ (f-4-3 2) - (f-8-1 0) - Dsp-16-u16 - Dst32AnUnprefixed)) - (ifield-assertion - (andif (eq f-4-3 2) (eq f-8-1 0))) - (getter (add Dsp-16-u16 Dst32AnUnprefixed)) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-24-An-relative-Unprefixed-Mova-SI) - (comment "addressof m32c dsp:16[An] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dst32AnUnprefixed Dsp-16-u24)) - (syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]") - (base-ifield f-4-6) - (encoding - (+ (f-4-3 3) - (f-8-1 0) - Dsp-16-u24 - Dst32AnUnprefixed)) - (ifield-assertion - (andif (eq f-4-3 3) (eq f-8-1 0))) - (getter (add Dsp-16-u24 Dst32AnUnprefixed)) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-8-SB-relative-Unprefixed-Mova-SI) - (comment "m32c addressof dsp:8[sb] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dsp-16-u8)) - (syntax "${Dsp-16-u8}[sb]") - (base-ifield f-4-6) - (encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8)) - (ifield-assertion - (andif (eq f-4-3 1) (eq f-8-2 2))) - (getter (add Dsp-16-u8 (reg h-sb))) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-16-SB-relative-Unprefixed-Mova-SI) - (comment "m32c addressof dsp:16[sb] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}[sb]") - (base-ifield f-4-6) - (encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16)) - (ifield-assertion - (andif (eq f-4-3 2) (eq f-8-2 2))) - (getter (add Dsp-16-u16 (reg h-sb))) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-8-FB-relative-Unprefixed-Mova-SI) - (comment "m32c addressof dsp:8[fb] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dsp-16-s8)) - (syntax "${Dsp-16-s8}[fb]") - (base-ifield f-4-6) - (encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8)) - (ifield-assertion - (andif (eq f-4-3 1) (eq f-8-2 3))) - (getter (add Dsp-16-s8 (reg h-fb))) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-16-FB-relative-Unprefixed-Mova-SI) - (comment "m32c addressof dsp:16[fb] relative destination SI") - (attrs (ISA m32c)) - (mode SI) - (args (Dsp-16-s16)) - (syntax "${Dsp-16-s16}[fb]") - (base-ifield f-4-6) - (encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16)) - (ifield-assertion - (andif (eq f-4-3 2) (eq f-8-2 3))) - (getter (add Dsp-16-s16 (reg h-fb))) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-16-absolute-Unprefixed-Mova-SI) - (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) - (mode SI) - (args (Dsp-16-u16)) - (syntax "${Dsp-16-u16}") - (base-ifield f-4-6) - (encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16)) - (ifield-assertion - (andif (eq f-4-3 3) (eq f-8-2 3))) - (getter Dsp-16-u16) - (setter (nop)) - ) - -(define-derived-operand - (name dst32-16-24-absolute-Unprefixed-Mova-SI) - (comment "m32c addressof absolute address SI") (attrs (ISA m32c)) - (mode SI) - (args (Dsp-16-u24)) - (syntax "${Dsp-16-u24}") - (base-ifield f-4-6) - (encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24)) - (ifield-assertion - (andif (eq f-4-3 3) (eq f-8-2 2))) - (getter Dsp-16-u24) - (setter (nop)) - ) - -(define-anyof-operand - (name dst32-16-Unprefixed-Mova-SI) - (comment - "m32c addressof destination operand of size SI with additional fields at offset 16") - (attrs (ISA m32c)) - (mode SI) - (choices - dst32-An-indirect-Unprefixed-Mova-SI - dst32-16-8-An-relative-Unprefixed-Mova-SI - dst32-16-16-An-relative-Unprefixed-Mova-SI - dst32-16-24-An-relative-Unprefixed-Mova-SI - dst32-16-8-SB-relative-Unprefixed-Mova-SI - dst32-16-16-SB-relative-Unprefixed-Mova-SI - dst32-16-8-FB-relative-Unprefixed-Mova-SI - dst32-16-16-FB-relative-Unprefixed-Mova-SI - dst32-16-16-absolute-Unprefixed-Mova-SI - dst32-16-24-absolute-Unprefixed-Mova-SI)) - -(define-pmacro (dst32-16-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst32-16-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Unprefixed- xmode) - (.sym dst32-An-direct-Unprefixed- xmode) - (.sym dst32-An-indirect-Unprefixed- xmode) - (.sym dst32-16-8-An-relative-Unprefixed- xmode) - (.sym dst32-16-16-An-relative-Unprefixed- xmode) - (.sym dst32-16-24-An-relative-Unprefixed- xmode) - (.sym dst32-16-8-SB-relative-Unprefixed- xmode) - (.sym dst32-16-16-SB-relative-Unprefixed- xmode) - (.sym dst32-16-8-FB-relative-Unprefixed- xmode) - (.sym dst32-16-16-FB-relative-Unprefixed- xmode) - (.sym dst32-16-16-absolute-Unprefixed- xmode) - (.sym dst32-16-24-absolute-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-16-8-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-16-8-An-relative-Unprefixed- xmode) - (.sym dst32-16-8-SB-relative-Unprefixed- xmode) - (.sym dst32-16-8-FB-relative-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-16-16-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-16-16-An-relative-Unprefixed- xmode) - (.sym dst32-16-16-SB-relative-Unprefixed- xmode) - (.sym dst32-16-16-FB-relative-Unprefixed- xmode) - (.sym dst32-16-16-absolute-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-16-16sa-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-16-16-SB-relative-Unprefixed- xmode) - (.sym dst32-16-16-FB-relative-Unprefixed- xmode) - (.sym dst32-16-16-absolute-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-16-24-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-16-24-An-relative-Unprefixed- xmode) - (.sym dst32-16-24-absolute-Unprefixed- xmode) - ) - ) - ) -) - -(dst32-16-operand QI) -(dst32-16-operand HI) -(dst32-16-operand SI) - -(define-pmacro (dst32-16-Ext-operand smode dmode) - (begin - (define-anyof-operand - (name (.sym dst32-16-ExtUnprefixed- smode)) - (comment (.str "m32c destination operand of size " smode " with additional fields at offset 16")) - (attrs (machine 32)) - (mode dmode) - (choices - (.sym dst32-Rn-direct-ExtUnprefixed- smode) - (.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version - (.sym dst32-An-indirect-ExtUnprefixed- smode) - (.sym dst32-16-8-An-relative-ExtUnprefixed- smode) - (.sym dst32-16-16-An-relative-ExtUnprefixed- smode) - (.sym dst32-16-24-An-relative-ExtUnprefixed- smode) - (.sym dst32-16-8-SB-relative-ExtUnprefixed- smode) - (.sym dst32-16-16-SB-relative-ExtUnprefixed- smode) - (.sym dst32-16-8-FB-relative-ExtUnprefixed- smode) - (.sym dst32-16-16-FB-relative-ExtUnprefixed- smode) - (.sym dst32-16-16-absolute-ExtUnprefixed- smode) - (.sym dst32-16-24-absolute-ExtUnprefixed- smode) - ) - ) - ) -) - -(dst32-16-Ext-operand QI HI) -(dst32-16-Ext-operand HI SI) - -(define-anyof-operand - (name dst32-16-Unprefixed-Mulex-HI) - (comment "m32c destination operand of size HI with additional fields at offset 16") - (attrs (machine 32)) - (mode HI) - (choices - dst32-R3-direct-Unprefixed-HI - dst32-An-direct-Unprefixed-HI - dst32-An-indirect-Unprefixed-HI - dst32-16-8-An-relative-Unprefixed-HI - dst32-16-16-An-relative-Unprefixed-HI - dst32-16-24-An-relative-Unprefixed-HI - dst32-16-8-SB-relative-Unprefixed-HI - dst32-16-16-SB-relative-Unprefixed-HI - dst32-16-8-FB-relative-Unprefixed-HI - dst32-16-16-FB-relative-Unprefixed-HI - dst32-16-16-absolute-Unprefixed-HI - dst32-16-24-absolute-Unprefixed-HI - ) -) -;------------------------------------------------------------- -; Destination operands with possible additional fields at offset 24 bits -;------------------------------------------------------------- - -(define-pmacro (dst16-24-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst16-24- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-Rn-direct- xmode) - (.sym dst16-An-direct- xmode) - (.sym dst16-An-indirect- xmode) - (.sym dst16-24-8-An-relative- xmode) - (.sym dst16-24-16-An-relative- xmode) - (.sym dst16-24-8-SB-relative- xmode) - (.sym dst16-24-16-SB-relative- xmode) - (.sym dst16-24-8-FB-relative- xmode) - (.sym dst16-24-16-absolute- xmode) - ) - ) - ) -) - -(dst16-24-operand QI) -(dst16-24-operand HI) - -(define-pmacro (dst32-24-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst32-24-Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Unprefixed- xmode) - (.sym dst32-An-direct-Unprefixed- xmode) - (.sym dst32-An-indirect-Unprefixed- xmode) - (.sym dst32-24-8-An-relative-Unprefixed- xmode) - (.sym dst32-24-16-An-relative-Unprefixed- xmode) - (.sym dst32-24-24-An-relative-Unprefixed- xmode) - (.sym dst32-24-8-SB-relative-Unprefixed- xmode) - (.sym dst32-24-16-SB-relative-Unprefixed- xmode) - (.sym dst32-24-8-FB-relative-Unprefixed- xmode) - (.sym dst32-24-16-FB-relative-Unprefixed- xmode) - (.sym dst32-24-16-absolute-Unprefixed- xmode) - (.sym dst32-24-24-absolute-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-24-Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Prefixed- xmode) - (.sym dst32-An-direct-Prefixed- xmode) - (.sym dst32-An-indirect-Prefixed- xmode) - (.sym dst32-24-8-An-relative-Prefixed- xmode) - (.sym dst32-24-16-An-relative-Prefixed- xmode) - (.sym dst32-24-24-An-relative-Prefixed- xmode) - (.sym dst32-24-8-SB-relative-Prefixed- xmode) - (.sym dst32-24-16-SB-relative-Prefixed- xmode) - (.sym dst32-24-8-FB-relative-Prefixed- xmode) - (.sym dst32-24-16-FB-relative-Prefixed- xmode) - (.sym dst32-24-16-absolute-Prefixed- xmode) - (.sym dst32-24-24-absolute-Prefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-24-8-Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-24-8-An-relative-Prefixed- xmode) - (.sym dst32-24-8-SB-relative-Prefixed- xmode) - (.sym dst32-24-8-FB-relative-Prefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-24-16-Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-24-16-An-relative-Prefixed- xmode) - (.sym dst32-24-16-SB-relative-Prefixed- xmode) - (.sym dst32-24-16-FB-relative-Prefixed- xmode) - (.sym dst32-24-16-absolute-Prefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-24-24-Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-24-24-An-relative-Prefixed- xmode) - (.sym dst32-24-24-absolute-Prefixed- xmode) - ) - ) -; (define-anyof-operand -; (name (.sym dst32-24-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-An-indirect-indirect- xmode) -; (.sym dst32-24-8-An-relative-indirect- xmode) -; (.sym dst32-24-16-An-relative-indirect- xmode) -; (.sym dst32-24-24-An-relative-indirect- xmode) -; (.sym dst32-24-8-SB-relative-indirect- xmode) -; (.sym dst32-24-16-SB-relative-indirect- xmode) -; (.sym dst32-24-8-FB-relative-indirect- xmode) -; (.sym dst32-24-16-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-basic-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with no additional fields")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-An-indirect-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-24-8-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-24-8-An-relative-indirect- xmode) -; (.sym dst32-24-8-SB-relative-indirect- xmode) -; (.sym dst32-24-8-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-24-16-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-24-16-An-relative-indirect- xmode) -; (.sym dst32-24-16-SB-relative-indirect- xmode) -; (.sym dst32-24-16-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-24-24-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-24-24-An-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-24-absolute-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-24-16-absolute-indirect-derived- xmode) -; (.sym dst32-24-24-absolute-indirect-derived- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-24-16-absolute-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-24-16-absolute-indirect-derived- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-24-24-absolute-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-24-24-absolute-indirect-derived- xmode) -; ) -; ) - ) -) - -(dst32-24-operand QI) -(dst32-24-operand HI) -(dst32-24-operand SI) - -;------------------------------------------------------------- -; Destination operands with possible additional fields at offset 32 bits -;------------------------------------------------------------- - -(define-pmacro (dst16-32-operand xmode) - (begin - (define-anyof-operand - (name (.sym dst16-32- xmode)) - (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32")) - (attrs (machine 16)) - (mode xmode) - (choices - (.sym dst16-Rn-direct- xmode) - (.sym dst16-An-direct- xmode) - (.sym dst16-An-indirect- xmode) - (.sym dst16-32-8-An-relative- xmode) - (.sym dst16-32-16-An-relative- xmode) - (.sym dst16-32-8-SB-relative- xmode) - (.sym dst16-32-16-SB-relative- xmode) - (.sym dst16-32-8-FB-relative- xmode) - (.sym dst16-32-16-absolute- xmode) - ) - ) - ) -) -(dst16-32-operand QI) -(dst16-32-operand HI) - -; This macro actually handles operands at offset 32, 40 and 48 bits -(define-pmacro (dst32-32plus-operand offset xmode) - (begin - (define-anyof-operand - (name (.sym dst32- offset -Unprefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Unprefixed- xmode) - (.sym dst32-An-direct-Unprefixed- xmode) - (.sym dst32-An-indirect-Unprefixed- xmode) - (.sym dst32- offset -8-An-relative-Unprefixed- xmode) - (.sym dst32- offset -16-An-relative-Unprefixed- xmode) - (.sym dst32- offset -24-An-relative-Unprefixed- xmode) - (.sym dst32- offset -8-SB-relative-Unprefixed- xmode) - (.sym dst32- offset -16-SB-relative-Unprefixed- xmode) - (.sym dst32- offset -8-FB-relative-Unprefixed- xmode) - (.sym dst32- offset -16-FB-relative-Unprefixed- xmode) - (.sym dst32- offset -16-absolute-Unprefixed- xmode) - (.sym dst32- offset -24-absolute-Unprefixed- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32- offset -Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Prefixed- xmode) - (.sym dst32-An-direct-Prefixed- xmode) - (.sym dst32-An-indirect-Prefixed- xmode) - (.sym dst32- offset -8-An-relative-Prefixed- xmode) - (.sym dst32- offset -16-An-relative-Prefixed- xmode) - (.sym dst32- offset -24-An-relative-Prefixed- xmode) - (.sym dst32- offset -8-SB-relative-Prefixed- xmode) - (.sym dst32- offset -16-SB-relative-Prefixed- xmode) - (.sym dst32- offset -8-FB-relative-Prefixed- xmode) - (.sym dst32- offset -16-FB-relative-Prefixed- xmode) - (.sym dst32- offset -16-absolute-Prefixed- xmode) - (.sym dst32- offset -24-absolute-Prefixed- xmode) - ) - ) -; (define-anyof-operand -; (name (.sym dst32- offset -indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-An-indirect-indirect- xmode) -; (.sym dst32- offset -8-An-relative-indirect- xmode) -; (.sym dst32- offset -16-An-relative-indirect- xmode) -; (.sym dst32- offset -24-An-relative-indirect- xmode) -; (.sym dst32- offset -8-SB-relative-indirect- xmode) -; (.sym dst32- offset -16-SB-relative-indirect- xmode) -; (.sym dst32- offset -8-FB-relative-indirect- xmode) -; (.sym dst32- offset -16-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32- offset -absolute-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32- offset -16-absolute-indirect-derived- xmode) -; (.sym dst32- offset -24-absolute-indirect-derived- xmode) -; ) -; ) - ) -) - -(dst32-32plus-operand 32 QI) -(dst32-32plus-operand 32 HI) -(dst32-32plus-operand 32 SI) -(dst32-32plus-operand 40 QI) -(dst32-32plus-operand 40 HI) -(dst32-32plus-operand 40 SI) - -;------------------------------------------------------------- -; Destination operands with possible additional fields at offset 48 bits -;------------------------------------------------------------- - -(define-pmacro (dst32-48-operand offset xmode) - (begin - (define-anyof-operand - (name (.sym dst32- offset -Prefixed- xmode)) - (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-Rn-direct-Prefixed- xmode) - (.sym dst32-An-direct-Prefixed- xmode) - (.sym dst32-An-indirect-Prefixed- xmode) - (.sym dst32- offset -8-An-relative-Prefixed- xmode) - (.sym dst32- offset -16-An-relative-Prefixed- xmode) - (.sym dst32- offset -24-An-relative-Prefixed- xmode) - (.sym dst32- offset -8-SB-relative-Prefixed- xmode) - (.sym dst32- offset -16-SB-relative-Prefixed- xmode) - (.sym dst32- offset -8-FB-relative-Prefixed- xmode) - (.sym dst32- offset -16-FB-relative-Prefixed- xmode) - (.sym dst32- offset -16-absolute-Prefixed- xmode) - (.sym dst32- offset -24-absolute-Prefixed- xmode) - ) - ) -; (define-anyof-operand -; (name (.sym dst32- offset -indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-An-indirect-indirect- xmode) -; (.sym dst32- offset -8-An-relative-indirect- xmode) -; (.sym dst32- offset -16-An-relative-indirect- xmode) -; (.sym dst32- offset -24-An-relative-indirect- xmode) -; (.sym dst32- offset -8-SB-relative-indirect- xmode) -; (.sym dst32- offset -16-SB-relative-indirect- xmode) -; (.sym dst32- offset -8-FB-relative-indirect- xmode) -; (.sym dst32- offset -16-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32- offset -absolute-indirect- xmode)) -; (comment (.str "m32c destination operand of size " xmode " absolute indirect")) -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32- offset -16-absolute-indirect-derived- xmode) -; (.sym dst32- offset -24-absolute-indirect-derived- xmode) -; ) -; ) - ) -) - -(dst32-48-operand 48 QI) -(dst32-48-operand 48 HI) -(dst32-48-operand 48 SI) - -;------------------------------------------------------------- -; Bit operands for m16c -;------------------------------------------------------------- - -(define-pmacro (bit16-operand offset) - (begin - (define-anyof-operand - (name (.sym bit16- offset)) - (comment (.str "m16c bit operand with possible additional fields at offset 24")) - (attrs (machine 16)) - (mode BI) - (choices - bit16-Rn-direct - bit16-An-direct - bit16-An-indirect - (.sym bit16- offset -8-An-relative) - (.sym bit16- offset -16-An-relative) - (.sym bit16- offset -8-SB-relative) - (.sym bit16- offset -16-SB-relative) - (.sym bit16- offset -8-FB-relative) - (.sym bit16- offset -16-absolute) - ) - ) - (define-anyof-operand - (name (.sym bit16- offset -basic)) - (comment (.str "m16c bit operand with no additional fields")) - (attrs (machine 16)) - (mode BI) - (choices - bit16-An-indirect - ) - ) - (define-anyof-operand - (name (.sym bit16- offset -8)) - (comment (.str "m16c bit operand with possible additional fields at offset 24")) - (attrs (machine 16)) - (mode BI) - (choices - bit16-Rn-direct - bit16-An-direct - (.sym bit16- offset -8-An-relative) - (.sym bit16- offset -8-SB-relative) - (.sym bit16- offset -8-FB-relative) - ) - ) - (define-anyof-operand - (name (.sym bit16- offset -16)) - (comment (.str "m16c bit operand with possible additional fields at offset 24")) - (attrs (machine 16)) - (mode BI) - (choices - (.sym bit16- offset -16-An-relative) - (.sym bit16- offset -16-SB-relative) - (.sym bit16- offset -16-absolute) - ) - ) - ) -) - -(bit16-operand 16) - -;------------------------------------------------------------- -; Bit operands for m32c -;------------------------------------------------------------- - -(define-pmacro (bit32-operand offset group) - (begin - (define-anyof-operand - (name (.sym bit32- offset - group)) - (comment (.str "m32c bit operand with possible additional fields at offset 24")) - (attrs (machine 32)) - (mode BI) - (choices - (.sym bit32-Rn-direct- group) - (.sym bit32-An-direct- group) - (.sym bit32-An-indirect- group) - (.sym bit32- offset -11-An-relative- group) - (.sym bit32- offset -19-An-relative- group) - (.sym bit32- offset -27-An-relative- group) - (.sym bit32- offset -11-SB-relative- group) - (.sym bit32- offset -19-SB-relative- group) - (.sym bit32- offset -11-FB-relative- group) - (.sym bit32- offset -19-FB-relative- group) - (.sym bit32- offset -19-absolute- group) - (.sym bit32- offset -27-absolute- group) - ) - ) - ) -) - -(bit32-operand 16 Unprefixed) -(bit32-operand 24 Prefixed) - -(define-anyof-operand - (name bit32-basic-Unprefixed) - (comment "m32c bit operand with no additional fields") - (attrs (machine 32)) - (mode BI) - (choices - bit32-Rn-direct-Unprefixed - bit32-An-direct-Unprefixed - bit32-An-indirect-Unprefixed - ) -) - -(define-anyof-operand - (name bit32-16-8-Unprefixed) - (comment "m32c bit operand with 8 bit additional fields") - (attrs (machine 32)) - (mode BI) - (choices - bit32-16-11-An-relative-Unprefixed - bit32-16-11-SB-relative-Unprefixed - bit32-16-11-FB-relative-Unprefixed - ) -) - -(define-anyof-operand - (name bit32-16-16-Unprefixed) - (comment "m32c bit operand with 16 bit additional fields") - (attrs (machine 32)) - (mode BI) - (choices - bit32-16-19-An-relative-Unprefixed - bit32-16-19-SB-relative-Unprefixed - bit32-16-19-FB-relative-Unprefixed - bit32-16-19-absolute-Unprefixed - ) -) - -(define-anyof-operand - (name bit32-16-24-Unprefixed) - (comment "m32c bit operand with 24 bit additional fields") - (attrs (machine 32)) - (mode BI) - (choices - bit32-16-27-An-relative-Unprefixed - bit32-16-27-absolute-Unprefixed - ) -) - -;------------------------------------------------------------- -; Operands for short format binary insns -;------------------------------------------------------------- - -(define-anyof-operand - (name src16-2-S) - (comment "m16c source operand of size QI for short format insns") - (attrs (machine 16)) - (mode QI) - (choices - src16-2-S-8-SB-relative-QI - src16-2-S-8-FB-relative-QI - src16-2-S-16-absolute-QI - ) -) - -(define-anyof-operand - (name src32-2-S-QI) - (comment "m32c source operand of size QI for short format insns") - (attrs (machine 32)) - (mode QI) - (choices - src32-2-S-8-SB-relative-QI - src32-2-S-8-FB-relative-QI - src32-2-S-16-absolute-QI - ) -) - -(define-anyof-operand - (name src32-2-S-HI) - (comment "m32c source operand of size QI for short format insns") - (attrs (machine 32)) - (mode HI) - (choices - src32-2-S-8-SB-relative-HI - src32-2-S-8-FB-relative-HI - src32-2-S-16-absolute-HI - ) -) - -(define-anyof-operand - (name Dst16-3-S-8) - (comment "m16c destination operand of size QI for short format insns") - (attrs (machine 16)) - (mode QI) - (choices - dst16-3-S-R0l-direct-QI - dst16-3-S-R0h-direct-QI - dst16-3-S-8-8-SB-relative-QI - dst16-3-S-8-8-FB-relative-QI - dst16-3-S-8-16-absolute-QI - ) -) - -(define-anyof-operand - (name Dst16-3-S-16) - (comment "m16c destination operand of size QI for short format insns") - (attrs (machine 16)) - (mode QI) - (choices - dst16-3-S-R0l-direct-QI - dst16-3-S-R0h-direct-QI - dst16-3-S-16-8-SB-relative-QI - dst16-3-S-16-8-FB-relative-QI - dst16-3-S-16-16-absolute-QI - ) -) - -(define-anyof-operand - (name srcdst16-r0l-r0h-S) - (comment "m16c r0l/r0h operand of size QI for short format insns") - (attrs (machine 16)) - (mode SI) - (choices - srcdst16-r0l-r0h-S-derived - ) -) - -(define-anyof-operand - (name dst32-2-S-basic-QI) - (comment "m32c r0l operand of size QI for short format binary insns") - (attrs (machine 32)) - (mode QI) - (choices - dst32-2-S-R0l-direct-QI - ) -) - -(define-anyof-operand - (name dst32-2-S-basic-HI) - (comment "m32c r0 operand of size HI for short format binary insns") - (attrs (machine 32)) - (mode HI) - (choices - dst32-2-S-R0-direct-HI - ) -) - -(define-pmacro (dst32-2-S-operands xmode) - (begin - (define-anyof-operand - (name (.sym dst32-2-S-8- xmode)) - (comment "m32c operand of size " xmode " for short format binary insns") - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-2-S-8-SB-relative- xmode) - (.sym dst32-2-S-8-FB-relative- xmode) - ) - ) - (define-anyof-operand - (name (.sym dst32-2-S-16- xmode)) - (comment "m32c operand of size " xmode " for short format binary insns") - (attrs (machine 32)) - (mode xmode) - (choices - (.sym dst32-2-S-16-absolute- xmode) - ) - ) -; (define-anyof-operand -; (name (.sym dst32-2-S-8-indirect- xmode)) -; (comment "m32c operand of size " xmode " for short format binary insns") -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-2-S-8-SB-relative-indirect- xmode) -; (.sym dst32-2-S-8-FB-relative-indirect- xmode) -; ) -; ) -; (define-anyof-operand -; (name (.sym dst32-2-S-absolute-indirect- xmode)) -; (comment "m32c operand of size " xmode " for short format binary insns") -; (attrs (machine 32)) -; (mode xmode) -; (choices -; (.sym dst32-2-S-16-absolute-indirect- xmode) -; ) -; ) - ) -) - -(dst32-2-S-operands QI) -(dst32-2-S-operands HI) -(dst32-2-S-operands SI) - -(define-anyof-operand - (name dst32-an-S) - (comment "m32c An operand for short format binary insns") - (attrs (machine 32)) - (mode HI) - (choices - dst32-1-S-A0-direct-HI - dst32-1-S-A1-direct-HI - ) -) - -(define-anyof-operand - (name bit16-11-S) - (comment "m16c bit operand for short format insns") - (attrs (machine 16)) - (mode BI) - (choices - bit16-11-SB-relative-S - ) -) - -(define-anyof-operand - (name Rn16-push-S-anyof) - (comment "m16c bit operand for short format insns") - (attrs (machine 16)) - (mode QI) - (choices - Rn16-push-S-derived - ) -) - -(define-anyof-operand - (name An16-push-S-anyof) - (comment "m16c bit operand for short format insns") - (attrs (machine 16)) - (mode HI) - (choices - An16-push-S-derived - ) -) - -;============================================================= -; Common macros for instruction definitions -; -(define-pmacro (set-z x) - (sequence () - (set zbit (zflag x))) - -) - -(define-pmacro (set-s x) - (sequence () - (set sbit (nflag x))) -) - -(define-pmacro (set-z-and-s x) - (sequence () - (set-z x) - (set-s x)) -) - -;============================================================= -; Unary insn macros -;------------------------------------------------------------- - -(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg) - (dni (.sym op mach wstr - group) - (.str op wstr opg " dst" mach "-" group "-" mode) - ((machine mach) RL_1ADDR) - (.str op wstr opg " ${dst" mach "-" group "-" mode "}") - encoding - (sem mode (.sym dst mach - group - mode)) - ()) -) - -(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) - (unary-insn-defn-g mach group mode wstr op encoding sem "") -) - - -(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) - (unary-insn-defn-g 16 16 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) - sem opg) -) -(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem) - (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") -) - -(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) - (begin - ; Multi insns are tried for assembly in the reverse order in which they appear here, so - ; define the absolute-indirect insns first in order to prevent them from being selected - ; when the mode is register-indirect -; (unary-insn-defn 32 24-absolute-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) -; sem) - (unary-insn-defn-g 32 16-Unprefixed mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) - sem opg) -; (unary-insn-defn 32 24-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) -; sem) - ) -) -(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) - (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") -) - -(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg) - (begin - (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg)) - (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg)) - ) -) -(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) - (unary-insn-mach-g mach op opc1 opc2 opc3 sem "") -) - -(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "") - (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "") - ) -) - -(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G") - (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G") - ) -) - -;------------------------------------------------------------- -; Sign/zero extension macros -;------------------------------------------------------------- - -(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem) - (dni (.sym op mach wstr - group) - (.str op wstr " dst" mach "-" group "-" smode) - ((machine mach)) - (.str op wstr " ${dst" mach "-" group "-" smode "}") - encoding - (sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode)) - ()) -) - -(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) - (ext-insn-defn 16 16-Ext smode dmode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode)) - sem) -) - -(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem) - (ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode)) - sem) -) - -(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem) - (dni (.sym op 32 wstr - src-group - dst-group) - (.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI") - ((machine 32)) - (.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}") - encoding - (sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI)) - ()) -) - -(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem) - (begin - (ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2)) - sem) - (ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2)) - sem) - (ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2)) - sem) - (ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2)) - sem) - ) -) - -;============================================================= -; Binary Arithmetic macros -; -;------------------------------------------------------------- -;<arith>.size:S src2,r0[l] -- for m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem) - (dni (.sym op 32 wstr .S-src2-r0- xmode) - (.str op 32 wstr ":S src2,r0[l]") - ((machine 32)) - (.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}") - (+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit)) - (sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S)) - ()) -) - -;------------------------------------------------------------- -;<arith>.b:S src2,r0l/r0h -- for m16c -;------------------------------------------------------------- - -(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem) - (begin - (dni (.sym op 16 .b.S-src2) - (.str op ".b:S src2,r0[lh]") - ((machine 16)) - (.str op ".b$S ${src16-2-S},${Dst16RnQI-S}") - (+ opc1 opc2 Dst16RnQI-S src16-2-S) - (sem QI src16-2-S Dst16RnQI-S) - ()) - (dni (.sym op 16 .b.S-r0l-r0h) - (.str op ".b:S r0l/r0h") - ((machine 16)) - (.str op ".b$S ${srcdst16-r0l-r0h-S}") - (+ opc1 opc2 srcdst16-r0l-r0h-S) - (if (eq srcdst16-r0l-r0h-S 0) - (sem QI R0h R0l) - (sem QI R0l R0h)) - ()) - ) -) - -;------------------------------------------------------------- -;<arith>.b:S #imm8,dst3 -- for m16c -;------------------------------------------------------------- - -(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem) - (dni (.sym op 16 .b.S-imm8-dst3) - (.str op sz ":S imm8,dst3") - ((machine 16)) - (.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}") - (+ opc1 opc2 Dst16-3-S-16 Imm-8-QI) - (sem QI Imm-8-QI Dst16-3-S-16) - ()) -) - -;------------------------------------------------------------- -;<arith>.size:Q #imm4,sp -- for m16c -;------------------------------------------------------------- - -(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) - (dni (.sym op 16 -wQ-sp) - (.str op ".w:q #imm4,sp") - ((machine 16)) - (.str op ".w$Q #${Imm-12-s4},sp") - (+ opc1 opc2 opc3 Imm-12-s4) - (sem QI Imm-12-s4 sp) - ()) -) - -;------------------------------------------------------------- -;<arith>.size:G #imm,sp -- for m16c -;------------------------------------------------------------- - -(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem) - (dni (.sym op 16 wstr - G-sp) - (.str op wstr " imm-sp " mode) - ((machine 16)) - (.str op wstr "$G #${Imm-16-" mode "},sp") - (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode)) - (sem mode (.sym Imm-16- mode) sp) - ()) -) - -(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem) - (begin - (binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem) - (binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem) - ) -) - -;------------------------------------------------------------- -;<arith>.size:G #imm,dst -- for m16c and m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem) - (dni (.sym op mach wstr - imm-G - dstgroup) - (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode) - ((machine mach) RL_1ADDR) - (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}") - encoding - (sem dmode src (.sym dst mach - dstgroup - dmode)) - ()) -) - -; m16c variants -(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) - (begin - (binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode)) - sem) - (binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode)) - sem) - (binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode)) - sem) - ) -) - -; m32c Unprefixed variants -(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) - (begin - (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode)) - sem) - (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode)) - sem) - (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode)) - sem) - (binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode)) - sem) - ) -) - -; m32c Prefixed variants -(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) - (begin - (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode)) - sem) - (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode)) - sem) - (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode)) - sem) - (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode)) - sem) - ) -) - -; All m32c variants -(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) - (begin - ; Multi insns are tried for assembly in the reverse order in which they appear here, so - ; define the absolute-indirect insns first in order to prevent them from being selected - ; when the mode is register-indirect -; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode)) -; sem) -; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode)) -; sem) - ; Unprefixed modes next - (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem) - - ; Remaining indirect modes -; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode)) -; sem) -; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode)) -; sem) -; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode)) -; sem) -; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode)) -; sem) - ) -) - -(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem) - (begin - (.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem)) - (.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem)) - ) -) - -(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem) - (binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem) - ) -) - -;------------------------------------------------------------- -;<arith>.size:Q #imm4,dst -- for m16c and m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem) - (dni (.sym op mach wstr - imm4-Q - dstgroup) - (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode) - ((machine mach) RL_1ADDR) - (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}") - encoding - (sem mode src (.sym dst mach - dstgroup - mode)) - ()) -) - -; m16c variants -(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) - (binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op - (+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode)) - sem) -) - -(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) - (binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op - (+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode)) - sem) -) - -; m32c variants -(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) - (begin - ; Multi insns are tried for assembly in the reverse order in which they appear here, so - ; define the absolute-indirect insns first in order to prevent them from being selected - ; when the mode is register-indirect -; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4) -; sem) - (binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op - (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4) - sem) -; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4) -; sem) - ) -) - -(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem) - (begin - ; Multi insns are tried for assembly in the reverse order in which they appear here, so - ; define the absolute-indirect insns first in order to prevent them from being selected - ; when the mode is register-indirect -; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) -; sem) - (binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op - (+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4) - sem) -; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4) -; sem) - ) -) - -(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem) - (begin - (.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem)) - (.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem)) - ) -) - -(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) - (begin - (binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem) - (binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem) - ) -) - -;------------------------------------------------------------- -;<arith>.size:G src,dst -- for m16c and m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem) - (dni (.sym op mach wstr - srcgroup - dstgroup) - (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode) - ((machine mach) RL_2ADDR) - (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}") - encoding - (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode)) - ()) -) - -; m16c variants -(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) - (begin - (binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix - (+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode)) - sem) - (binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix - (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode)) - sem) - (binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix - (+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode)) - sem) - ) -) - -; m32c Prefixed variants -(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem) - (begin - (binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) - sem) - (binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) - sem) - (binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) - sem) - (binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix - (+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) - sem) - ) -) - -; all m32c variants -(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem) - (begin - ; Multi insns are tried for assembly in the reverse order in which they appear here, so - ; define the absolute-indirect insns first in order to prevent them from being selected - ; when the mode is register-indirect -; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2)) -; sem) - (binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix - (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2)) - sem) - (binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix - (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2)) - sem) - (binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix - (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2)) - sem) - (binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix - (+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2)) - sem) -; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix -; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2)) -; sem) -; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix -; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit) -; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2)) -; sem) - ) -) - -(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem) - (begin - (.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem)) - (.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem)) - ) -) - -(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem) - (begin - (binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem) - (binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem) - ) -) - -;------------------------------------------------------------- -;<arith>.size:S #imm,dst -- for m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem) - (dni (.sym op 32 wstr - imm-S - dstgroup) - (.str op wstr " 32-imm-S-" dstgroup "-" mode) - ((machine 32)) - (.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}") - encoding - (sem mode src (.sym dst32- dstgroup - mode)) - ()) -) - -(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem) - (dni (.sym op 32 wstr - imm-Z - dstgroup) - (.str op wstr " 32-imm-Z-" dstgroup "-" mode) - ((machine 32)) - (.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}") - encoding - (sem mode (const 0) (.sym dst32- dstgroup - mode)) - ()) -) - -(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem) - (begin -; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) -; sem) - (binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op - (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode)) - sem) - (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op - (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode)) - sem) - (binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op - (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode)) - sem) -; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) -; sem) - ) -) - -(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem) - (begin -; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode)) -; sem) - (binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op - (+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit)) - sem) - (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op - (+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit)) - sem) - (binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op - (+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit)) - sem) -; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op -; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode)) -; sem) - ) -) - -;------------------------------------------------------------- -;<arith>.L:S #imm1,An -- for m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem) - (begin - (dni (.sym op 32.l-s-imm1-S-an) - (.str op ".l 32-imm1-S-an") - ((machine 32)) - (.str op ".l$S #${Imm1-S},${dst32-an-S}") - (+ opc1 Imm1-S opc2 dst32-an-S) - (sem SI Imm1-S dst32-an-S) - ()) - ) -) - -;------------------------------------------------------------- -;<arith>.L:Q #imm3,sp -- for m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem) - (begin - (dni (.sym op 32.l-imm3-Q) - (.str op ".l 32-imm3-Q") - ((machine 32)) - (.str op ".l$Q #${Imm3-S},sp") - (+ opc1 Imm3-S opc2) - (sem SI Imm3-S sp) - ()) - ) -) - -;------------------------------------------------------------- -;<arith>.L:S #imm8,sp -- for m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem) - (begin - (dni (.sym op 32.l-imm8-S) - (.str op ".l 32-imm8-S") - ((machine 32)) - (.str op ".l$S #${Imm-16-QI},sp") - (+ opc1 opc2 opc3 opc4 Imm-16-QI) - (sem SI Imm-16-QI sp) - ()) - ) -) - -;------------------------------------------------------------- -;<arith>.L:G #imm16,sp -- for m32c -;------------------------------------------------------------- - -(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem) - (begin - (dni (.sym op 32.l-imm16-G) - (.str op ".l 32-imm16-G") - ((machine 32)) - (.str op ".l$G #${Imm-16-HI},sp") - (+ opc1 opc2 opc3 opc4 Imm-16-HI) - (sem SI Imm-16-HI sp) - ()) - ) -) - -;------------------------------------------------------------- -;<arith>jnz.size #imm4,dst,label -- for m16c and m32c -;------------------------------------------------------------- - -(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) - (dni (.sym op mach wstr - imm4 - dstgroup) - (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) - (RL_JUMP RELAXABLE (machine mach)) - (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") - encoding - (sem mode src (.sym dst mach - dstgroup - mode) label) - ()) -) - -; m16c variants -(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) - (begin - (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) - sem) - (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8) - sem) - (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8) - sem) - ) -) - -; m32c variants -(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) - (begin - (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8) - sem) - (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8) - sem) - (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8) - sem) - (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8) - sem) - ) -) - -(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem) - (begin - (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem)) - (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem)) - ) -) - -(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem) - (begin - (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem) - (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem) - ) -) - -;------------------------------------------------------------- -;mov.size dsp8[sp],dst -- for m16c and m32c -;------------------------------------------------------------- -(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dspsp-dst- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") - encoding - (sem mach mode dsp (.sym dst mach - dstgroup - mode)) - ()) -) -(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") - encoding - (sem mach mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) - -; m16c variants -(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) - (begin - (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) - sem) - (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) - sem) - (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) - sem) - ) -) - -(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) - (begin - (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) - sem) - (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) - sem) - (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) - sem) - ) -) - -; m32c variants -(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) - (begin - (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) - sem) - (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) - sem) - (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) - sem) - (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) - sem) - ) -) -(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) - (begin - (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) - sem) - (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) - sem) - (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) - sem) - (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) - sem) - ) -) - -(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem) - (begin - (.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem)) - (.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem)) - ) -) - -(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem) - (begin - (.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem)) - (.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem)) - ) -) - -(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem) - (mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem) - ) -) -(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem) - (mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem) - ) -) - -;------------------------------------------------------------- -; lde dsp24,dst -- for m16c -;------------------------------------------------------------- - -(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp) - (begin - - (dni (.sym lde wstr - dstgroup -u20) - (.str "lde" wstr "-" dstgroup "-u20") - ((machine 16)) - (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}") - (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8) - (.sym dst16- dstgroup - mode) srcdisp) - (nop) - ()) - - (dni (.sym lde wstr - dstgroup -u20a0) - (.str "lde" wstr "-" dstgroup "-u20a0") - ((machine 16)) - (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}") - (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9) - (.sym dst16- dstgroup - mode) srcdisp) - (nop) - ()) - - (dni (.sym lde wstr - dstgroup -a1a0) - (.str "lde" wstr "-" dstgroup "-a1a0") - ((machine 16)) - (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}") - (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa) - (.sym dst16- dstgroup - mode)) - (nop) - ()) - ) - ) - -(define-pmacro (lde-dst mode wstr wbit) - (begin - ; like: QI .b 0 - (lde-dst-dsp mode wstr wbit basic Dsp-16-u20) - (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) - (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) - ) -) - -;------------------------------------------------------------- -; ste dst,dsp24 -- for m16c -;------------------------------------------------------------- - -(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp) - (begin - - (dni (.sym ste wstr - dstgroup -u20) - (.str "ste" wstr "-" dstgroup "-u20") - ((machine 16)) - (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}") - (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0) - (.sym dst16- dstgroup - mode) srcdisp) - (nop) - ()) - - (dni (.sym ste wstr - dstgroup -u20a0) - (.str "ste" wstr "-" dstgroup "-u20a0") - ((machine 16)) - (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]") - (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1) - (.sym dst16- dstgroup - mode) srcdisp) - (nop) - ()) - - (dni (.sym ste wstr - dstgroup -a1a0) - (.str "ste" wstr "-" dstgroup "-a1a0") - ((machine 16)) - (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]") - (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2) - (.sym dst16- dstgroup - mode)) - (nop) - ()) - ) - ) - -(define-pmacro (ste-dst mode wstr wbit) - (begin - ; like: QI .b 0 - (ste-dst-dsp mode wstr wbit basic Dsp-16-u20) - (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) - (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) - ) -) - -;============================================================= -; Division -;------------------------------------------------------------- - -(define-pmacro (div-sem divop modop opmode reg src quot rem max min) - (sequence () - (if (eq src 0) - (set obit (const BI 1)) - (sequence ((opmode quot-result) (opmode rem-result)) - (set quot-result (divop opmode (ext opmode reg) src)) - (set rem-result (modop opmode (ext opmode reg) src)) - (set obit (orif (gt opmode quot-result max) - (lt opmode quot-result min))) - (set quot quot-result) - (set rem rem-result)))) -) - -;<divop>.size #imm -- for m16c and m32c -(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) - (dni (.sym op mach wstr - src) - (.str op mach wstr "-" src) - ((machine mach)) - (.str op wstr " #${" src "}") - encoding - (sem divop modop opmode reg src quot rem max min) - ()) -) -(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) - (div-imm-defn 16 wstr op (.sym Imm-16 - smode) - (+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode)) - divop modop opmode reg quot rem max min - sem) -) -(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem) - (div-imm-defn 32 wstr op (.sym Imm-16 - smode) - (+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode)) - divop modop opmode reg quot rem max min - sem) -) -(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem) - (begin - (.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem)) - (.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem)) - ) -) -(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem) - (begin - (div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem) - (div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem) - ) -) - -;<divop>.size src -- for m16c and m32c -(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem) - (dni (.sym op mach wstr - src) - (.str op mach wstr "-" src) - ((machine mach)) - (.str op wstr " ${" src "}") - encoding - (sem divop modop opmode reg src quot rem max min) - ()) -) -(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) - (div-src-defn 16 wstr op (.sym dst16-16 - smode) - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode)) - divop modop opmode reg quot rem max min - sem) -) -(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem) - (begin - ; Multi insns are tried for assembly in the reverse order in which they appear here, so - ; define the absolute-indirect insns first in order to prevent them from being selected - ; when the mode is register-indirect -; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode) -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode)) -; divop modop opmode reg quot rem max min -; sem) - (div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode) - (+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode)) - divop modop opmode reg quot rem max min - sem) -; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode) -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode)) -; divop modop opmode reg quot rem max min -; sem) - ) -) -(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem) - (begin - (.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem)) - (.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem)) - ) -) -(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem) - (div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem) - ) -) - -;============================================================= -; Bit manipulation -; -(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem) - (dni (.sym op mach - suffix - opnd) - (.str op mach ":" suffix " " opnd) - ((machine mach)) - (.str op "$" suffix " ${" opnd "}") - encoding - (sem opnd) - ()) -) - -(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem) - (bit-insn-defn 16 op X bit16-16 - (+ opc1 opc2 opc3 bit16-16) - sem) -) - -(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem) - (begin - (bit-insn-defn 32 op X bit32-24-Prefixed - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3)) - sem) - ) -) - -(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) - (bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem) - ) -) - -(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem) - (begin - (bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem) - (bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem) - (bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem) - (bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem) - ) -) - -(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem) - (begin - (bit-insn-defn 32 op X bit32-16-Unprefixed - (+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3)) - sem) - ) -) - -(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem) - (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) - ) -) - -(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem) - (begin - (bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem) - (bitdst32-defn op opc32-1 opc32-2 opc32-3 sem) - ) -) - -;============================================================= -; Bit condition -; -(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem) - (dni (.sym op mach - bit-opnd - cond-opnd) - (.str op mach " " bit-opnd " " cond-opnd) - ((machine mach)) - (.str op "${" cond-opnd "} ${" bit-opnd "}") - encoding - (sem mach bit-opnd cond-opnd) - ()) -) - -(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem) - (begin - (bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem) - (bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem) - (bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem) - ) -) - -(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem) - (begin - (bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40 - (+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40) - sem) - (bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32 - (+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32) - sem) - (bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24 - (+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24) - sem) - (bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16 - (+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16) - sem) - ) -) - -(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) - (begin - (bitcond16-defn op opc16-1 opc16-2 opc16-3 sem) - (bitcond32-defn op opc32-1 opc32-2 opc32-3 sem) - ) -) - -;============================================================= -;<insn>.size #imm1,#imm2,dst -- for m32c -; -(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem) - (dni (.sym op 32 wstr - src1 - src2 - dstgroup) - (.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode) - ((machine 32)) - (.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}") - encoding - (sem xmode src1 src2 (.sym dst32- dstgroup - xmode)) - ()) -) - -; m32c Prefixed variants -(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) - (begin - (insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) - (.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode)) - sem) - (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) - (.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode)) - sem) - (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) - (.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode)) - sem) - (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op - (+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) - (.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode)) - sem) - ) -) - -; m32c Unprefixed variants -(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem) - (begin - (insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) - (.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode)) - sem) - (insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) - (.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode)) - sem) - (insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) - (.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode)) - sem) - (insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op - (+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) - (.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode)) - sem) - ) -) - -(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem) - (begin - (insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) - (insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem) - ) -) -(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem) - (begin - (insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem) - (insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem) - ) -) - -;============================================================= -; Insn definitions -;------------------------------------------------------------- -; abs - absolute -;------------------------------------------------------------- - -(define-pmacro (abs-sem mode dst) - (sequence ((mode result)) - (set result (abs mode dst)) - (set obit (eq result dst)) - (set-z-and-s result) - (set dst result)) -) -(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem) - -;------------------------------------------------------------- -; adcf - addition carry flag -;------------------------------------------------------------- - -(define-pmacro (adcf-sem mode dst) - (sequence ((mode result)) - (set result (addc mode dst 0 cbit)) - (set obit (add-oflag mode dst 0 cbit)) - (set cbit (add-cflag mode dst 0 cbit)) - (set-z-and-s result) - (set dst result)) -) -(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem) - -;------------------------------------------------------------- -; add - binary addition -;------------------------------------------------------------- - -(define-pmacro (add-sem mode src1 dst) - (sequence ((mode result)) - (set result (add mode src1 dst)) - (set obit (add-oflag mode src1 dst 0)) - (set cbit (add-cflag mode src1 dst 0)) - (set-z-and-s result) - (set dst result)) -) - -; add.L:G #imm32,dst (m32 #2) -(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem) -; add.size:G #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem) -; add.size:Q #imm4,dst (m16 #2 m32 #3) -(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem) -(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem) -; add.b:S #imm8,dst3 (m16 #3) -(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) -; add.BW:Q #imm4,sp (m16 #7) -(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) -(dnmi add16-bQ-sp "add16-bQ-sp" () - "add.b:q #${Imm-12-s4},sp" - (emit add16-wQ-sp Imm-12-s4)) -; add.BW:G #imm,sp (m16 #6) -(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) -; add.BW:G src,dst (m16 #4 m32 #6) -(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem) -; add.B.S src2,r0l/r0h (m16 #5) -(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem) -; add.L:G src,dst (m32 #7) -(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem) -; add.L:S #imm{1,2},A0/A1 (m32 #5) -(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem) -; add.L:Q #imm3,sp (m32 #9) -(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem) -; add.L:S #imm8,sp (m32 #10) -(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem) -; add.L:G #imm16,sp (m32 #8) -(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem) -; add.BW:S #imm,dst2 (m32 #4) -(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem) -(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem) - -;------------------------------------------------------------- -; adc - binary add with carry -;------------------------------------------------------------- - -(define-pmacro (addc-sem mode src dst) - (sequence ((mode result)) - (set result (addc mode src dst cbit)) - (set obit (add-oflag mode src dst cbit)) - (set cbit (add-cflag mode src dst cbit)) - (set-z-and-s result) - (set dst result)) -) - -; adc.size:G #imm,dst -(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) -(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem) -(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem) - -; adc.BW:G src,dst -(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) -(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem) -(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem) - -;------------------------------------------------------------- -; dadc - decimal add with carry -; dadd - decimal addition -;------------------------------------------------------------- - -(define-pmacro (dadc-sem mode src dst) - (sequence ((mode result)) - (set result (subc mode dst src (not cbit))) - (set cbit (sub-cflag mode dst src (not cbit))) - (set-z-and-s result) - (set dst result)) -) - -(define-pmacro (decimal-subtraction16-insn op opc1 opc2) - (begin - ; op.b #imm8,r0l - (dni (.sym op 16.b-imm8) - (.str op ".b #imm8") - ((machine 16)) - (.str op ".b #${Imm-16-QI},r0l") - (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI) - ((.sym op -sem) QI Imm-16-QI R0l) - ()) - ; op.w #imm16,r0 - (dni (.sym op 16.w-imm16) - (.str op ".b #imm16") - ((machine 16)) - (.str op ".w #${Imm-16-HI},r0") - (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI) - ((.sym op -sem) HI Imm-16-HI R0) - ()) - ; op.b #r0h,r0l - (dni (.sym op 16.b-r0h-r0l) - (.str op ".b r0h,r0l") - ((machine 16)) - (.str op ".b r0h,r0l") - (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2)) - ((.sym op -sem) QI R0h R0l) - ()) - ; op.w #r1,r0 - (dni (.sym op 16.w-r1-r0) - (.str op ".b r1,r0") - ((machine 16)) - (.str op ".w r1,r0") - (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2)) - ((.sym op -sem) HI R1 R0) - ()) - ) -) - -; dadc for m16c -(decimal-subtraction16-insn dadc #xE #x6 ) - -; dadc.size #imm,dst -(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem) -; dadc.BW src,dst -(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem) - -(define-pmacro (dadd-sem mode src dst) - (sequence ((mode result)) - (set result (subc mode dst src 0)) - (set cbit (sub-cflag mode dst src 0)) - (set-z-and-s result) - (set dst result)) -) - -; dadd for m16c -(decimal-subtraction16-insn dadd #xC #x4) - -; dadd.size #imm,dst -(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem) -; dadd.BW src,dst -(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem) - -;-------------------------------------------------------------; -; addx - Add extend sign with no carry -;-------------------------------------------------------------; - -(define-pmacro (addx-sem mode src dst) - (sequence ((SI source) (SI result)) - (set source (zext SI (trunc QI src))) - (set result (add SI source dst)) - (set obit (add-oflag SI source dst 0)) - (set cbit (add-cflag SI source dst 0)) - (set-z-and-s result) - (set dst result)) -) - -; addx #imm,dst -(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem) -; addx src,dst -(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem) - -;------------------------------------------------------------- -; adjnz - Add/Sub and branch if not zero -;------------------------------------------------------------- - -(define-pmacro (arith-jnz-sem mode src dst label) - (sequence ((mode result)) - (set result (add mode src dst)) - (set dst result) - (if (ne result 0) - (set pc label))) -) - -; adjnz.size #imm4,dst,label -(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) - -;------------------------------------------------------------- -; and - binary and -;------------------------------------------------------------- - -(define-pmacro (and-sem mode src1 dst) - (sequence ((mode result)) - (set result (and mode src1 dst)) - (set-z-and-s result) - (set dst result)) -) - -; and.size:G #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem) -; and.b:S #imm8,dst3 (m16 #2) -(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem) -; and.BW:G src,dst (m16 #3 m32 #3) -(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem) -; and.B.S src2,r0l/r0h (m16 #4) -(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem) -; and.BW:S #imm,dst2 (m32 #2) -(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem) -(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem) - -;------------------------------------------------------------- -; band - bit and -;------------------------------------------------------------- - -(define-pmacro (band-sem src) - (set cbit (and src cbit)) -) -(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem) - -;------------------------------------------------------------- -; bclr - bit clear -;------------------------------------------------------------- - -(define-pmacro (bclr-sem dst) - (set dst 0) -) -(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem) - -;------------------------------------------------------------- -; bitindex - bit index -;------------------------------------------------------------- - -(define-pmacro (bitindex-sem mode dst) - (set BitIndex dst) -) -(unary-insn-defn 32 16-Unprefixed QI .b bitindex - (+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE)) - bitindex-sem) -(unary-insn-defn 32 16-Unprefixed HI .w bitindex - (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE)) - bitindex-sem) - -;------------------------------------------------------------- -; bmCnd - bit move condition -;------------------------------------------------------------- - -(define-pmacro (test-condition16 cond) - (case UQI cond - ((#x00) (trunc BI cbit)) - ((#x01) (not (or cbit zbit))) - ((#x02) (trunc BI zbit)) - ((#x03) (trunc BI sbit)) - ((#x04) (or zbit (xor sbit obit))) - ((#x05) (trunc BI obit)) - ((#x06) (xor sbit obit)) - ((#xf8) (not cbit)) - ((#xf9) (or cbit zbit)) - ((#xfa) (not zbit)) - ((#xfb) (not sbit)) - ((#xfc) (not (or zbit (xor sbit obit)))) - ((#xfd) (not obit)) - ((#xfe) (not (xor sbit obit))) - (else (const BI 0)) - ) -) - -(define-pmacro (test-condition32 cond) - (case UQI cond - ((#x00) (not cbit)) - ((#x01) (or cbit zbit)) - ((#x02) (not zbit)) - ((#x03) (not sbit)) - ((#x04) (not obit)) - ((#x05) (not (or zbit (xor sbit obit)))) - ((#x06) (not (xor sbit obit))) - ((#x08) (trunc BI cbit)) - ((#x09) (not (or cbit zbit))) - ((#x0a) (trunc BI zbit)) - ((#x0b) (trunc BI sbit)) - ((#x0c) (trunc BI obit)) - ((#x0d) (or zbit (xor sbit obit))) - ((#x0e) (xor sbit obit)) - (else (const BI 0)) - ) -) - -(define-pmacro (bitcond-sem mach op cond) - (if ((.sym test-condition mach) cond) - (set op 1) - (set op 0)) -) -(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem) - -(dni bm16-c - "bm16 C" - ((machine 16)) - "bm$cond16c c" - (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c) - (bitcond-sem 16 cbit cond16c) - ()) - -(dni bm32-c - "bm32 C" - ((machine 32)) - "bm$cond32 c" - (+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32) - (bitcond-sem 32 cbit cond32) - ()) - -;------------------------------------------------------------- -; bnand -;------------------------------------------------------------- - -(define-pmacro (bnand-sem src) - (set cbit (and (inv src) cbit)) -) -(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem) - -;------------------------------------------------------------- -; bnor -;------------------------------------------------------------- - -(define-pmacro (bnor-sem src) - (set cbit (or (inv src) cbit)) -) -(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem) - -;------------------------------------------------------------- -; bnot -;------------------------------------------------------------- - -(define-pmacro (bnot-sem dst) - (set dst (inv dst)) -) -(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem) - -;------------------------------------------------------------- -; bntst -;------------------------------------------------------------- - -(define-pmacro (bntst-sem src) - (set cbit (inv src)) - (set zbit (inv src)) -) -(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem) - -;------------------------------------------------------------- -; bnxor -;------------------------------------------------------------- - -(define-pmacro (bnxor-sem src) - (set cbit (xor (inv src) cbit)) -) -(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem) - -;------------------------------------------------------------- -; bor -;------------------------------------------------------------- - -(define-pmacro (bor-sem src) - (set cbit (or src cbit)) -) -(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem) - -;------------------------------------------------------------- -; brk -;------------------------------------------------------------- - -(dni brk16 - "brk" - ((machine 16)) - "brk" - (+ (f-0-4 #x0) (f-4-4 #x0)) - (nop) - ()) - -(dni brk32 - "brk" - ((machine 32)) - "brk" - (+ (f-0-4 #x0) (f-4-4 #x0)) - (nop) - ()) - -;------------------------------------------------------------- -; brk2 -;------------------------------------------------------------- - -(dni brk232 - "brk2" - ((machine 32)) - "brk2" - (+ (f-0-4 #x0) (f-4-4 #x8)) - (nop) - ()) - -;------------------------------------------------------------- -; bset -;------------------------------------------------------------- - -(define-pmacro (bset-sem dst) - (set dst 1) -) -(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem) - -;------------------------------------------------------------- -; btst -;------------------------------------------------------------- - -(define-pmacro (btst-sem dst) - (set zbit (inv dst)) - (set cbit dst) -) -(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem) - -(bit-insn-defn 32 btst G bit32-16-Unprefixed - (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0)) - btst-sem) - -(dni btst.s "btst:s" ((machine 32)) - "btst:s ${Bit3-S},${Dsp-8-u16}" - (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16) - () ()) - -;------------------------------------------------------------- -; btstc -;------------------------------------------------------------- - -(define-pmacro (btstc-sem dst) - (set zbit (inv dst)) - (set cbit dst) - (set dst (const 0)) -) -(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem) - -;------------------------------------------------------------- -; btsts -;------------------------------------------------------------- - -(define-pmacro (btsts-sem dst) - (set zbit (inv dst)) - (set cbit dst) - (set dst (const 0)) -) -(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem) - -;------------------------------------------------------------- -; bxor -;------------------------------------------------------------- - -(define-pmacro (bxor-sem src) - (set cbit (xor src cbit)) -) -(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem) - -;------------------------------------------------------------- -; clip -;------------------------------------------------------------- - -(define-pmacro (clip-sem mode imm1 imm2 dest) - (sequence () - (if (gt mode imm1 dest) - (set dest imm1)) - (if (lt mode imm2 dest) - (set dest imm2))) -) - -(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem) - -;------------------------------------------------------------- -; cmp - binary compare -;------------------------------------------------------------- - -(define-pmacro (cmp-sem mode src1 dst) - (sequence ((mode result)) - (set result (sub mode dst src1)) - (set obit (sub-oflag mode dst src1 0)) - (set cbit (not (sub-cflag mode dst src1 0))) - (set-z-and-s result)) -) - -; cmp.L:G #imm32,dst (m32 #2) -(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem) -; cmp.size:G #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem) -; cmp.size:Q #imm4,dst (m16 #2 m32 #3) -(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem) -; cmp.b:S #imm8,dst3 (m16 #3) -(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem) -; cmp.BW:G src,dst (m16 #4 m32 #5) -(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem) -; cmp.B.S src2,r0l/r0h (m16 #5) -(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem) -; cmp.L:G src,dst (m32 #6) -(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem) -; cmp.BW:S #imm,dst2 (m32 #4) -(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem) -(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem) -; cmp.BW:s src2,r0[l] (m32 #7) -(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem) -(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem) - -;------------------------------------------------------------- -; cmpx - binary compare extend sign -;------------------------------------------------------------- - -(define-pmacro (cmpx-sem mode src1 dst) - (sequence ((mode result)) - (set result (sub mode dst (ext mode src1))) - (set obit (sub-oflag mode dst (ext mode src1) 0)) - (set cbit (sub-cflag mode dst (ext mode src1) 0)) - (set-z-and-s result)) -) - -(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem) - -;------------------------------------------------------------- -; dec - decrement -;------------------------------------------------------------- - -(define-pmacro (dec-sem mode dest) - (sequence ((mode result)) - (set result (sub mode dest 1)) - (set-z-and-s result) - (set dest result)) -) - -(dni dec16.b - "dec.b Dst16-3-S-8" - ((machine 16)) - "dec.b ${Dst16-3-S-8}" - (+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8) - (dec-sem QI Dst16-3-S-8) - ()) - -(dni dec16.w - "dec.w Dst16An-S" - ((machine 16)) - "dec.w ${Dst16An-S}" - (+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S) - (dec-sem HI Dst16An-S) - ()) - -(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem) -(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem) - -;------------------------------------------------------------- -; div - divide -; divu - divide unsigned -; divx - divide extension -;------------------------------------------------------------- - -; div.BW #imm -(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem) -(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem) -(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem) -; div.BW src -(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem) -(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem) -(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem) - -(div-src-defn 32 .l div dst32-24-Prefixed-SI - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI) - div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) - div-sem) -(div-src-defn 32 .l divu dst32-24-Prefixed-SI - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI) - udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0 - div-sem) -(div-src-defn 32 .l divx dst32-24-Prefixed-SI - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI) - div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000) - div-sem) - -;------------------------------------------------------------- -; dsbb - decimal subtraction with borrow -; dsub - decimal subtraction -;------------------------------------------------------------- - -(define-pmacro (dsbb-sem mode src dst) - (sequence ((mode result)) - (set result (subc mode dst src (not cbit))) - (set cbit (sub-cflag mode dst src (not cbit))) - (set-z-and-s result) - (set dst result)) -) - -; dsbb for m16c -(decimal-subtraction16-insn dsbb #xF #x7) - -; dsbb.size #imm,dst -(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem) -; dsbb.BW src,dst -(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem) - -(define-pmacro (dsub-sem mode src dst) - (sequence ((mode result)) - (set result (subc mode dst src 0)) - (set cbit (sub-cflag mode dst src 0)) - (set-z-and-s result) - (set dst result)) -) - -; dsub for m16c -(decimal-subtraction16-insn dsub #xD #x5) - -; dsub.size #imm,dst -(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem) -; dsub.BW src,dst -(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem) - -;------------------------------------------------------------- -; sub - binary subtraction -;------------------------------------------------------------- - -(define-pmacro (sub-sem mode src1 dst) - (sequence ((mode result)) - (set result (sub mode dst src1)) - (set obit (sub-oflag mode dst src1 0)) - (set cbit (sub-cflag mode dst src1 0)) - (set dst result) - (set-z-and-s result))) - -; sub.size:G #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem) -; sub.b:S #imm8,dst3 (m16 #2) -(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem) -; sub.BW:G src,dst (m16 #3 m32 #4) -(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem) -; sub.B.S src2,r0l/r0h (m16 #4) -(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem) -; sub.L:G #imm32,dst (m32 #2) -(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem) -; sub.BW:S #imm,dst2 (m32 #3) -(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem) -(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem) -; sub.L:G src,dst (m32 #5) -(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem) - -;------------------------------------------------------------- -; enter - enter function -; exitd - exit and deallocate stack frame -;------------------------------------------------------------- - -(define-pmacro (enter16-sem mach amt) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem16 HI (reg h-sp)) (reg h-fb)) - (set (reg h-fb) (reg h-sp)) - (set (reg h-sp) (sub (reg h-sp) amt)))) - -(define-pmacro (exit16-sem mach) - (sequence ((SI newpc)) - (set (reg h-sp) (reg h-fb)) - (set (reg h-fb) (mem16 HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)) - (set newpc (mem16 HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)) - (set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16)))) - (set (reg h-sp) (add (reg h-sp) 1)) - (set pc newpc))) - -(define-pmacro (enter32-sem mach amt) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 4)) - (set (mem32 SI (reg h-sp)) (reg h-fb)) - (set (reg h-fb) (reg h-sp)) - (set (reg h-sp) (sub (reg h-sp) amt)))) - -(define-pmacro (exit32-sem mach) - (sequence ((SI newpc)) - (set (reg h-sp) (reg h-fb)) - (set (reg h-fb) (mem32 SI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 4)) - (set newpc (mem32 SI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 4)) - (set pc newpc))) - -(dni enter16 "enter #Imm-16-QI" ((machine 16)) - ("enter #${Dsp-16-u8}") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8) - (enter16-sem 16 Dsp-16-u8) - ()) - -(dni exitd16 "exitd" ((machine 16)) - ("exitd") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2)) - (exit16-sem 16) - ()) - -(dni enter32 "enter #Imm-8-QI" ((machine 32)) - ("enter #${Dsp-8-u8}") - (+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8) - (enter32-sem 32 Dsp-8-u8) - ()) - -(dni exitd32 "exitd" ((machine 32)) - ("exitd") - (+ (f-0-4 #xF) (f-4-4 #xC)) - (exit32-sem 32) - ()) - -;------------------------------------------------------------- -; fclr - flag register clear -; fset - flag register set -;------------------------------------------------------------- - -(define-pmacro (set-flags-sem flag) - (sequence ((SI tmp)) - (case DFLT flag - ((#x0) (set cbit 1)) - ((#x1) (set dbit 1)) - ((#x2) (set zbit 1)) - ((#x3) (set sbit 1)) - ((#x4) (set bbit 1)) - ((#x5) (set obit 1)) - ((#x6) (set ibit 1)) - ((#x7) (set ubit 1))) - ) - ) - -(define-pmacro (clear-flags-sem flag) - (sequence ((SI tmp)) - (case DFLT flag - ((#x0) (set cbit 0)) - ((#x1) (set dbit 0)) - ((#x2) (set zbit 0)) - ((#x3) (set sbit 0)) - ((#x4) (set bbit 0)) - ((#x5) (set obit 0)) - ((#x6) (set ibit 0)) - ((#x7) (set ubit 0))) - ) - ) - -(dni fclr16 "fclr flag" ((machine 16)) - ("fclr ${flags16}") - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5)) - (clear-flags-sem flags16) - ()) - -(dni fset16 "fset flag" ((machine 16)) - ("fset ${flags16}") - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4)) - (set-flags-sem flags16) - ()) - -(dni fclr "fclr" ((machine 32)) - ("fclr ${flags32}") - (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32) - (clear-flags-sem flags32) - ()) - -(dni fset "fset" ((machine 32)) - ("fset ${flags32}") - (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32) - (set-flags-sem flags32) - ()) - -;------------------------------------------------------------- -; inc - increment -;------------------------------------------------------------- - -(define-pmacro (inc-sem mode dest) - (sequence ((mode result)) - (set result (add mode dest 1)) - (set-z-and-s result) - (set dest result)) -) - -(dni inc16.b - "inc.b Dst16-3-S-8" - ((machine 16)) - "inc.b ${Dst16-3-S-8}" - (+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8) - (inc-sem QI Dst16-3-S-8) - ()) - -(dni inc16.w - "inc.w Dst16An-S" - ((machine 16)) - "inc.w ${Dst16An-S}" - (+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S) - (inc-sem HI Dst16An-S) - ()) - -(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem) -(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem) - -;------------------------------------------------------------- -; freit - fast return from interrupt (m32) -; int - interrupt -; into - interrupt on overflow -;------------------------------------------------------------- - -; ??? semantics -(dni freit32 "FREIT" ((machine 32)) - ("freit") - (+ (f-0-4 9) (f-4-4 #xF)) - (nop) - ()) - -(dni int16 "int Dsp-10-u6" ((machine 16)) - ("int #${Dsp-10-u6}") - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6) - (c-call VOID "do_int" pc Dsp-10-u6) - ()) - -(dni into16 "into" ((machine 16)) - ("into") - (+ (f-0-4 #xF) (f-4-4 6)) - (nop) - ()) - -(dni int32 "int Dsp-8-u6" ((machine 32)) - ("int #${Dsp-8-u6}") - (+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0)) - (c-call VOID "do_int" pc Dsp-8-u6) - ()) - -(dni into32 "into" ((machine 32)) - ("into") - (+ (f-0-4 #xB) (f-4-4 #xF)) - (nop) - ()) - -;------------------------------------------------------------- -; index (m32c) -;------------------------------------------------------------- - -; TODO add support to insns allowing index -(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d)) -(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d)) -(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0))) -(define-pmacro (indexw-sem mode d) - (set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2)))) -(define-pmacro (indexwd-sem mode d) - (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) -(define-pmacro (indexws-sem mode d) - (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) -(define-pmacro (indexl-sem mode d) - (set SrcIndex d) (set DstIndex (sll d (const 2)))) -(define-pmacro (indexld-sem mode d) - (set SrcIndex (const 0)) (set DstIndex (sll d (const 2)))) -(define-pmacro (indexls-sem mode d) - (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) - -; Note that "wbit" not where the size bit goes here, hence, it's -; always 0 in these calls but op2 differs instead. - -; indexb src (index byte) -(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) -(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) -; indexbd src (index byte dest) -(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) -(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) -; indexbs src (index byte src) -(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) -(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) -; indexl src (index long) -(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) -(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) -; indexld src (index long dest) -(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) -(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) -; indexls src (index long src) -(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) -(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) -; indexw src (index word) -(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) -(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) -; indexwd src (index word dest) -(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) -(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) -; indexws (index word src) -(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) -(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) - -;------------------------------------------------------------- -; jcc - jump on condition -;------------------------------------------------------------- - -(define-pmacro (jcnd32-sem cnd label) - (sequence () - (case DFLT cnd - ((#x00) (if (not cbit) (set pc label))) ;ltu nc - ((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu - ((#x02) (if (not zbit) (set pc label))) ;ne nz - ((#x03) (if (not sbit) (set pc label))) ;pz - ((#x04) (if (not obit) (set pc label))) ;no - ((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt - ((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge - ((#x08) (if (trunc BI cbit) (set pc label))) ;geu c - ((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu - ((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z - ((#x0b) (if (trunc BI sbit) (set pc label))) ;n - ((#x0c) (if (trunc BI obit) (set pc label))) ;o - ((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le - ((#x0e) (if (xor sbit obit) (set pc label))) ;lt - ) - ) - ) - -(define-pmacro (jcnd16-sem cnd label) - (sequence () - (case DFLT cnd - ((#x00) (if (trunc BI cbit) (set pc label))) ;geu c - ((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu - ((#x02) (if (trunc BI zbit) (set pc label))) ;eq z - ((#x03) (if (trunc BI sbit) (set pc label))) ;n - ((#x04) (if (not cbit) (set pc label))) ;ltu nc - ((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu - ((#x06) (if (not zbit) (set pc label))) ;ne nz - ((#x07) (if (not sbit) (set pc label))) ;pz - ((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le - ((#x09) (if (trunc BI obit) (set pc label))) ;o - ((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge - ((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt - ((#x0d) (if (not obit) (set pc label))) ;no - ((#x0e) (if (xor sbit obit) (set pc label))) ;lt - ) - ) - ) - -(dni jcnd16-5 - "jCnd label" - (RL_JUMP RELAXABLE (machine 16)) - "j$cond16j5 ${Lab-8-8}" - (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8) - (jcnd16-sem cond16j5 Lab-8-8) - () -) - -(dni jcnd16 - "jCnd label" - (RL_JUMP RELAXABLE (machine 16)) - "j$cond16j ${Lab-16-8}" - (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8) - (jcnd16-sem cond16j Lab-16-8) - () -) - -(dni jcnd32 - "jCnd label" - (RL_JUMP RELAXABLE (machine 32)) - "j$cond32j ${Lab-8-8}" - (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8) - (jcnd32-sem cond32j Lab-8-8) - () -) - -;------------------------------------------------------------- -; jmp - jump -;------------------------------------------------------------- - -; jmp.s label3 (m16 #1) -(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16)) - ("jmp.s ${Lab-5-3}") - (+ (f-0-4 6) (f-4-1 0) Lab-5-3) - (sequence () (set pc Lab-5-3)) - ()) -; jmp.b label8 (m16 #2) -(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16)) - ("jmp.b ${Lab-8-8}") - (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8) - (sequence () (set pc Lab-8-8)) - ()) -; jmp.w label16 (m16 #3) -(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) - ("jmp.w ${Lab-8-16}") - (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16) - (sequence () (set pc Lab-8-16)) - ()) -; jmp.a label24 (m16 #4) -(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) - ("jmp.a ${Lab-8-24}") - (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24) - (sequence () (set pc Lab-8-24)) - ()) - -(define-pmacro (jmp16-sem mode dst) - (set pc (and dst #xfffff)) -) -(define-pmacro (jmp32-sem mode dst) - (set pc dst) -) -; jmpi.w dst (m16 #1 m32 #2) -(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem) -(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem) -; jmpi.a dst (m16 #2 m32 #2) -(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem) -(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem) -; jmps imm8 (m16 #1) -(dni jmps16 "jmps Imm-8-QI" ((machine 16)) - ("jmps #${Imm-8-QI}") - (+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI) - (sequence () (set pc Imm-8-QI)) - ()) -; jmp.s label3 (m32 #1) -(dni jmp32.s - "jmp.s label" - (RL_JUMP RELAXABLE (machine 32)) - "jmp.s ${Lab32-jmp-s}" - (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s) - (set pc Lab32-jmp-s) - () -) -; jmp.b label8 (m32 #2) -(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32)) - ("jmp.b ${Lab-8-8}") - (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8) - (set pc Lab-8-8) - ()) -; jmp.w label16 (m32 #3) -(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32)) - ("jmp.w ${Lab-8-16}") - (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16) - (set pc Lab-8-16) - ()) -; jmp.a label24 (m32 #4) -(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32)) - ("jmp.a ${Lab-8-24}") - (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24) - (set pc Lab-8-24) - ()) -; jmp.s imm8 (m32 #1) -(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32)) - ("jmps #${Imm-8-QI}") - (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI) - (set pc Imm-8-QI) - ()) - -;------------------------------------------------------------- -; jsr jump subroutine -;------------------------------------------------------------- - -(define-pmacro (jsr16-sem length dst) - (sequence ((SI tpc)) - (set tpc (add pc length)) - (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8)) - (set (reg h-sp) (sub (reg h-sp) 1)) - (set (mem16 QI (reg h-sp)) (and tpc #xff)) - (set pc dst) - ) -) -(define-pmacro (jsr32-sem length dst) - (sequence ((SI tpc)) - (set tpc (add pc length)) - (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16)) - (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem32 HI (reg h-sp)) (and tpc #xffff)) - (set pc dst) - ) -) - -; jsr.w label16 (m16 #1) -(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) - ("jsr.w ${Lab-8-16}") - (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16) - (jsr16-sem 3 Lab-8-16) - ()) -; jsr.a label24 (m16 #2) -(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) - ("jsr.a ${Lab-8-24}") - (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24) - (jsr16-sem 4 Lab-8-24) - ()) -(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem - op32 op32-1 op32-2 op32-3 op32-4 op32-sem len) - (begin - (dni (.sym jsri16 mode - op16) - (.str "jsri." mode " " op16) - (RL_1ADDR (machine 16)) - (.str "jsri." mode " ${" op16 "}") - (+ op16-1 op16-2 op16-3 op16) - (op16-sem len op16) - ()) - (dni (.sym jsri32 mode - op32) - (.str "jsri." mode " " op32) - (RL_1ADDR (machine 32)) - (.str "jsri." mode " ${" op32 "}") - (+ op32-1 op32-2 op32-3 op32-4 op32) - (op32-sem len op32) - ()) - ) - ) -; jsri.w dst (m16 #1 m32 #1)) -(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) -(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) -(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) -(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) - -; jsri.a (m16 #2 m32 #2) -(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) -(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) -(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) -(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) - -(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) - ("jsri.a ${dst32-16-24-Unprefixed-SI}") - (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) - (jsr32-sem 6 dst32-16-24-Unprefixed-SI) - ()) -; jsr.w label16 (m32 #1) -(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32)) - ("jsr.w ${Lab-8-16}") - (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16) - (jsr32-sem 3 Lab-8-16) - ()) -; jsr.a label16 (m32 #2) -(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32)) - ("jsr.a ${Lab-8-24}") - (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24) - (jsr32-sem 4 Lab-8-24) - ()) -; jsrs imm8 (m16 #1) -(dni jsrs16 "jsrs Imm-8-QI" ((machine 16)) - ("jsrs #${Imm-8-QI}") - (+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI) - (jsr16-sem 2 Imm-8-QI) - ()) -; jsrs imm8 (m32 #1) -(dni jsrs "jsrs #Imm-8-QI" ((machine 32)) - ("jsrs #${Imm-8-QI}") - (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI) - (jsr32-sem 2 Imm-8-QI) - ()) - -;------------------------------------------------------------- -; ldc - load control register -; stc - store control register -;------------------------------------------------------------- - -(define-pmacro (ldc32-cr1-sem src dst) - (sequence () - (case DFLT dst - ((#x0) (set (reg h-dct0) src)) - ((#x1) (set (reg h-dct1) src)) - ((#x2) (sequence ((HI tflag)) - (set tflag src) - (if (and tflag #x1) (set cbit 1)) - (if (and tflag #x2) (set dbit 1)) - (if (and tflag #x4) (set zbit 1)) - (if (and tflag #x8) (set sbit 1)) - (if (and tflag #x10) (set bbit 1)) - (if (and tflag #x20) (set obit 1)) - (if (and tflag #x40) (set ibit 1)) - (if (and tflag #x80) (set ubit 1)))) - ((#x3) (set (reg h-svf) src)) - ((#x4) (set (reg h-drc0) src)) - ((#x5) (set (reg h-drc1) src)) - ((#x6) (set (reg h-dmd0) src)) - ((#x7) (set (reg h-dmd1) src)) - ) - ) -) -(define-pmacro (ldc32-cr2-sem src dst) - (sequence () - (case DFLT dst - ((#x0) (set (reg h-intb) src)) - ((#x1) (set (reg h-sp) src)) - ((#x2) (set (reg h-sb) src)) - ((#x3) (set (reg h-fb) src)) - ((#x4) (set (reg h-svp) src)) - ((#x5) (set (reg h-vct) src)) - ((#x7) (set (reg h-isp) src)) - ) - ) -) -(define-pmacro (ldc32-cr3-sem src dst) - (sequence () - (case DFLT dst - ((#x2) (set (reg h-dma0) src)) - ((#x3) (set (reg h-dma1) src)) - ((#x4) (set (reg h-dra0) src)) - ((#x5) (set (reg h-dra1) src)) - ((#x6) (set (reg h-dsa0) src)) - ((#x7) (set (reg h-dsa1) src)) - ) - ) -) -(define-pmacro (ldc16-sem src dst) - (sequence () - (case DFLT dst - ((#x1) (set (reg h-intb) src)) - ((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16))))) - ((#x3) (sequence ((HI tflag)) - (set tflag src) - (if (and tflag #x1) (set cbit 1)) - (if (and tflag #x2) (set dbit 1)) - (if (and tflag #x4) (set zbit 1)) - (if (and tflag #x8) (set sbit 1)) - (if (and tflag #x10) (set bbit 1)) - (if (and tflag #x20) (set obit 1)) - (if (and tflag #x40) (set ibit 1)) - (if (and tflag #x80) (set ubit 1)))) - ((#x4) (set (reg h-isp) src)) - ((#x5) (set (reg h-sp) src)) - ((#x6) (set (reg h-sb) src)) - ((#x7) (set (reg h-fb) src)) - ) - ) -) - -(define-pmacro (stc32-cr1-sem src dst) - (sequence () - (case DFLT src - ((#x0) (set dst (reg h-dct0))) - ((#x1) (set dst (reg h-dct1))) - ((#x2) (sequence ((HI tflag)) - (set tflag 0) - (if (eq cbit 1) (set tflag (or tflag #x1))) - (if (eq dbit 1) (set tflag (or tflag #x2))) - (if (eq zbit 1) (set tflag (or tflag #x4))) - (if (eq sbit 1) (set tflag (or tflag #x8))) - (if (eq bbit 1) (set tflag (or tflag #x10))) - (if (eq obit 1) (set tflag (or tflag #x20))) - (if (eq ibit 1) (set tflag (or tflag #x40))) - (if (eq ubit 1) (set tflag (or tflag #x80))) - (set dst tflag))) - ((#x3) (set dst (reg h-svf))) - ((#x4) (set dst (reg h-drc0))) - ((#x5) (set dst (reg h-drc1))) - ((#x6) (set dst (reg h-dmd0))) - ((#x7) (set dst (reg h-dmd1))) - ) - ) -) -(define-pmacro (stc32-cr2-sem src dst) - (sequence () - (case DFLT src - ((#x0) (set dst (reg h-intb))) - ((#x1) (set dst (reg h-sp))) - ((#x2) (set dst (reg h-sb))) - ((#x3) (set dst (reg h-fb))) - ((#x4) (set dst (reg h-svp))) - ((#x5) (set dst (reg h-vct))) - ((#x7) (set dst (reg h-isp))) - ) - ) -) -(define-pmacro (stc32-cr3-sem src dst) - (sequence () - (case DFLT src - ((#x2) (set dst (reg h-dma0))) - ((#x3) (set dst (reg h-dma1))) - ((#x4) (set dst (reg h-dra0))) - ((#x5) (set dst (reg h-dra1))) - ((#x6) (set dst (reg h-dsa0))) - ((#x7) (set dst (reg h-dsa1))) - ) - ) -) -(define-pmacro (stc16-sem src dst) - (sequence () - (case DFLT src - ((#x1) (set dst (and (reg h-intb) (const #xffff)))) - ((#x2) (set dst (srl (reg h-intb) (const 16)))) - ((#x3) (sequence ((HI tflag)) - (set tflag 0) - (if (eq cbit 1) (set tflag (or tflag #x1))) - (if (eq dbit 1) (set tflag (or tflag #x2))) - (if (eq zbit 1) (set tflag (or tflag #x4))) - (if (eq sbit 1) (set tflag (or tflag #x8))) - (if (eq bbit 1) (set tflag (or tflag #x10))) - (if (eq obit 1) (set tflag (or tflag #x20))) - (if (eq ibit 1) (set tflag (or tflag #x40))) - (if (eq ubit 1) (set tflag (or tflag #x80))) - (set dst tflag))) - ((#x4) (set dst (reg h-isp))) - ((#x5) (set dst (reg h-sp))) - ((#x6) (set dst (reg h-sb))) - ((#x7) (set dst (reg h-fb))) - ) - ) -) - -(dni ldc16.imm16 "ldc #imm,dst" ((machine 16)) - ("ldc #${Imm-16-HI},${cr16}") - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI) - (ldc16-sem Imm-16-HI cr16) - ()) - -(dni ldc16.dst "ldc src,dest" ((machine 16)) - ("ldc ${dst16-16-HI},${cr16}") - (+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI) - (ldc16-sem dst16-16-HI cr16) - ()) -; ldc src,dest (m32c #4) -(dni ldc32.src-cr1 "ldc src,dst" ((machine 32)) - ("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}") - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32) - (ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32) - ()) -; ldc src,dest (m32c #5) -(dni ldc32.src-cr2 "ldc src,dest" ((machine 32)) - ("ldc ${dst32-16-Unprefixed-SI},${cr2-32}") - (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32) - (ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32) - ()) -; ldc src,dest (m32c #6) -(dni ldc32.src-cr3 "ldc src,dst" ((machine 32)) - ("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}") - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32) - (ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32) - ()) -; ldc src,dest (m32c #1) -(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32)) - ("ldc #${Imm-16-HI},${cr1-Unprefixed-32}") - (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI) - (ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32) - ()) -; ldc src,dest (m32c #2) -(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32)) - ("ldc #${Dsp-16-u24},${cr2-32}") - (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24) - (ldc32-cr2-sem Dsp-16-u24 cr2-32) - ()) -; ldc src,dest (m32c #3) -(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32)) - ("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}") - (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24) - (ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32) - ()) - -(dni stc16.src "stc src,dest" ((machine 16)) - ("stc ${cr16},${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI) - (stc16-sem cr16 dst16-16-HI ) - ()) - -(dni stc16.pc "stc pc,dest" ((machine 16)) - ("stc pc,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI) - (sequence () (set dst16-16-HI (reg h-pc))) - ()) - -(dni stc32.src-cr1 "stc src,dst" ((machine 32)) - ("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}") - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32) - (stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI ) - ()) - -(dni stc32.src-cr2 "stc src,dest" ((machine 32)) - ("stc ${cr2-32},${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32) - (stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI ) - ()) - -(dni stc32.src-cr3 "stc src,dst" ((machine 32)) - ("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}") - (+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32) - (stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI ) - ()) - -;------------------------------------------------------------- -; ldctx - load context -; stctx - store context -;------------------------------------------------------------- - -; ??? semantics -(dni ldctx16 "ldctx abs16,abs24" ((machine 16)) - ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") - (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) - (nop) - ()) -(dni ldctx32 "ldctx abs16,abs24" ((machine 32)) - ("ldctx ${Dsp-16-u16},${Dsp-32-u24}") - (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) - (nop) - ()) -(dni stctx16 "stctx abs16,abs24" ((machine 16)) - ("stctx ${Dsp-16-u16},${Dsp-32-u24}") - (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24) - (nop) - ()) -(dni stctx32 "stctx abs16,abs24" ((machine 32)) - ("stctx ${Dsp-16-u16},${Dsp-32-u24}") - (+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24) - (nop) - ()) - -;------------------------------------------------------------- -; lde - load from extra far data area (m16) -; ste - store to extra far data area (m16) -;------------------------------------------------------------- - -(lde-dst QI .b 0) -(lde-dst HI .w 1) - -(ste-dst QI .b 0) -(ste-dst HI .w 1) - -;------------------------------------------------------------- -; ldipl - load interrupt permission level -;------------------------------------------------------------- - -; ??? semantics -; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl - -(dni ldipl16.imm "ldipl #imm" ((machine 16)) - ("ldipl #${Imm-13-u3}") - (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3) - (nop) - ()) -(dni ldipl32.imm "ldipl #imm" ((machine 32)) - ("ldipl #${Imm-13-u3}") - (+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3) - (nop) - ()) - - -;------------------------------------------------------------- -; max - maximum value -;------------------------------------------------------------- - -; TODO check semantics for min -1,0 -(define-pmacro (max-sem mode src dst) - (sequence () - (if (gt mode src dst) - (set mode dst src))) -) - -; max.size:G #imm,dst -(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem) - -; max.BW:G src,dst -(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem) - -;------------------------------------------------------------- -; min - minimum value -;------------------------------------------------------------- - -(define-pmacro (min-sem mode src dst) - (sequence () - (if (lt mode src dst) - (set mode dst src))) -) - -; min.size:G #imm,dst -(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem) - -; min.BW:G src,dst -(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem) - -;------------------------------------------------------------- -; mov - move -;------------------------------------------------------------- - -(define-pmacro (mov-sem mode src1 dst) - (sequence ((mode result)) - (set result src1) - (set-z-and-s result) - (set mode dst src1)) -) - -(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst) - (set dst (mem-mach mach mode (add sp src1))) -) - -(define-pmacro (mov-src-dspsp-sem mach mode src dst1) - (set (mem-mach mach mode (add sp dst1)) src) -) - -(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2) - (dni (.sym mov16. size .S-imm- regn) - (.str "mov." size ":S " imm "," regn) - ((machine 16)) - (.str "mov." size "$S #${" imm "}," regn) - (+ op1 op2 imm) - (mov-sem mode imm (reg (.sym h- regn))) - ()) -) -; mov.size:G #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem) -; mov.L:G #imm32,dst (m32 #2) -(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem) -; mov.BW:S #imm,dst2 (m32 #4) -(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem) -(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem) -; mov.b:S #imm8,dst3 (m16 #3) -(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem) -; mov.b:S #imm8,aN (m16 #4) -(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2)) -(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA)) -(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2)) -(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA)) -; mov.WL:S #imm,A0/A1 (m32 #5) -(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2) - (dni (.sym mov32- sz - regn) - (.str "mov." sz ":s" imm "," regn) - ((machine 32)) - (.str "mov." sz "$S #${" imm "}," regn) - (+ (f-0-4 op1) (f-4-4 op2) imm) - (mov-sem mode imm (reg (.sym h- regn))) - ()) -) -(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC) -(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD) -(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC) -(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD) - -; mov.size:Q #imm4,dst (m16 #2 m32 #3) -(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) -(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem) -(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem) -(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem) - -; mov.BW:Z #0,dst (m16 #5 m32 #6) -(dni mov16.b-Z-imm8-dst3 - "mov.b:Z #0,Dst16-3-S-8" - ((machine 16)) - "mov.b$Z #0,${Dst16-3-S-8}" - (+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8) - (mov-sem QI (const 0) Dst16-3-S-8) - ()) -; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem) -(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem) -(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem) -; mov.BW:G src,dst (m16 #6 m32 #7) -(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem) -; mov.B:S src2,a0/a1 (m16 #7) -(dni (.sym mov 16 .b.S-An) - (.str mov ".b:S src2,a[01]") - ((machine 16)) - (.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}") - (+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S) - (mov-sem QI src16-2-S Dst16AnQI-S) - ()) -(define-pmacro (mov16-b-s-an-defn op1 op2 op2c) - (dni (.sym mov16.b.S- op1 - op2) - (.str mov ".b:S " op1 "," op2) - ((machine 16)) - (.str mov ".b$S " op1 "," op2) - (+ (f-0-4 #x3) op2c) - (mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2))) - ()) - ) -(mov16-b-s-an-defn r0l a1 (f-4-4 #x4)) -(mov16-b-s-an-defn r0h a0 (f-4-4 #x0)) - -; mov.L:G src,dst (m32 #8) -(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem) -; mov.B:S r0l/r0h,dst2 (m16 #8) -(dni (.sym mov 16 .b.S-Rn-An) - (.str mov ".b:S r0[lh],src2") - ((machine 16)) - (.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}") - (+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S) - (mov-sem QI src16-2-S Dst16RnQI-S) - ()) - -; mov.B.S src2,r0l/r0h (m16 #9) -(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem) - -; mov.BW:S src2,r0l/r0 (m32 #9) -; mov.BW:S src2,r1l/r1 (m32 #10) -(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2) - (begin - (dni (.sym mov32. sz - src - dst) - (.str "mov." sz "src," dst) - ((machine 32)) - (.str "mov." sz "$S ${" (.sym src - mode) "}," dst) - (+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode)) - (mov-sem mode (.sym src - mode) (reg (.sym h- dst))) - ()) - ) - ) -(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4) -(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4) -(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4) -(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4) -(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7) -(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7) -(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7) -(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7) -(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7) -(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7) - -; mov.BW:S r0l/r0,dst2 (m32 #11) -(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2) - (begin - (dni (.sym mov32. sz - src - dst) - (.str "mov." sz "src," dst) - ((machine 32)) - (.str "mov." sz "$S " src ",${" (.sym dst - mode) "}") - (+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode)) - (mov-sem mode (reg (.sym h- src)) (.sym dst - mode)) - ()) - ) - ) -(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0) -(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0) -(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0) -(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0) - -; mov.L:S src,A0/A1 (m32 #12) -(define-pmacro (mov32-src-a src dst dstcode opc1 opc2) - (begin - (dni (.sym mov32. sz - src - dst) - (.str "mov." sz "src," dst) - ((machine 32)) - (.str "mov.l" "$S ${" (.sym src - SI) "}," dst) - (+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode)) - (mov-sem SI (.sym src - SI) (reg (.sym h- dst))) - ()) - ) - ) -(mov32-src-a dst32-2-S-16 a0 0 1 4) -(mov32-src-a dst32-2-S-16 a1 1 1 4) -(mov32-src-a dst32-2-S-8 a0 0 1 4) -(mov32-src-a dst32-2-S-8 a1 1 1 4) - -; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13) -; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14) -(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem) -(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem) - -;------------------------------------------------------------- -; mova - move effective address -;------------------------------------------------------------- - -(define-pmacro (mov16a-defn dst dstop dstcode) - (dni (.sym mova16. src - dst) - (.str "mova src," dst) - ((machine 16)) - (.str "mova ${dst16-16-Mova-HI}," dst) - (+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode)) - (sequence () (set HI (reg dstop) dst16-16-Mova-HI)) - ()) -) -(mov16a-defn r0 h-r0 0) -(mov16a-defn r1 h-r1 1) -(mov16a-defn r2 h-r2 2) -(mov16a-defn r3 h-r3 3) -(mov16a-defn a0 h-a0 4) -(mov16a-defn a1 h-a1 5) - -(define-pmacro (mov32a-defn dst dstop dstcode) - (dni (.sym mova32. src - dst) - (.str "mova src," dst) - ((machine 32)) - (.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst) - (+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode)) - (sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI)) - ()) -) -(mov32a-defn r2r0 h-r2r0 0) -(mov32a-defn r3r1 h-r3r1 1) -(mov32a-defn a0 h-a0 2) -(mov32a-defn a1 h-a1 3) - -;------------------------------------------------------------- -; movDir - move nibble -;------------------------------------------------------------- - -(define-pmacro (movdir-sem nib src dst) - (sequence ((SI tmp)) - (case DFLT nib - ((0) (set dst (or (and dst #xf0) (and src #xf)))) - ((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4)))) - ((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4)))) - ((3) (set dst (or (and dst #x0f) (and src #xf0)))) - ) - ) - ) -; movDir src,dst -(define-pmacro (mov16dir-1-defn nib dircode dir) - (dni (.sym mov nib 16 ".r0l-dst") - (.str "mov" nib " r0l,dst") - ((machine 16)) - (.str "mov" nib " r0l,${dst16-16-QI}") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) - (movdir-sem dircode (reg h-r0l) dst16-16-QI) - ()) -) -(mov16dir-1-defn ll 0 8) -(mov16dir-1-defn lh 1 #xA) -(mov16dir-1-defn hl 2 9) -(mov16dir-1-defn hh 3 #xB) -(define-pmacro (mov16dir-2-defn nib dircode dir) - (dni (.sym mov nib 16 ".src-r0l") - (.str "mov" nib " src,r0l") - ((machine 16)) - (.str "mov" nib " ${dst16-16-QI},r0l") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI) - (movdir-sem dircode dst16-16-QI (reg h-r0l)) - ()) -) -(mov16dir-2-defn ll 0 0) -(mov16dir-2-defn lh 1 2) -(mov16dir-2-defn hl 2 1) -(mov16dir-2-defn hh 3 3) - -(define-pmacro (mov32dir-1-defn nib o1o0) - (dni (.sym mov nib 32 ".r0l-dst") - (.str "mov" nib " r0l,dst") - ((machine 32)) - (.str "mov" nib " r0l,${dst32-24-Prefixed-QI}") - (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) - (movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI) - ()) -) -(mov32dir-1-defn ll 0) -(mov32dir-1-defn lh 1) -(mov32dir-1-defn hl 2) -(mov32dir-1-defn hh 3) -(define-pmacro (mov32dir-2-defn nib o1o0) - (dni (.sym mov nib 32 ".src-r0l") - (.str "mov" nib " src,r0l") - ((machine 32)) - (.str "mov" nib " ${dst32-24-Prefixed-QI},r0l") - (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE)) - (movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l)) - ()) -) -(mov32dir-2-defn ll 0) -(mov32dir-2-defn lh 1) -(mov32dir-2-defn hl 2) -(mov32dir-2-defn hh 3) - -;------------------------------------------------------------- -; movx - move extend sign (m32) -;------------------------------------------------------------- - -(define-pmacro (movx-sem mode src dst) - (sequence ((SI source) (SI result)) - (set SI result src) - (set-z-and-s result) - (set dst result)) -) - -; movx #imm,dst -(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem) - -;------------------------------------------------------------- -; mul - multiply -;------------------------------------------------------------- - -(define-pmacro (mul-sem mode src1 dst) - (sequence ((mode result)) - (set obit (add-oflag mode src1 dst 0)) - (set result (mul mode src1 dst)) - (set dst result)) -) - -; mul.BW #imm,dst -(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem) -; mul.BW src,dst -(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem) - -(dni mul_l "mul.l src,r2r0" ((machine 32)) - ("mul.l ${dst32-24-Prefixed-SI},r2r0") - (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf) - dst32-24-Prefixed-SI) - () ()) - -(dni mulu_l "mulu.l src,r2r0" ((machine 32)) - ("mulu.l ${dst32-24-Prefixed-SI},r2r0") - (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf) - dst32-24-Prefixed-SI) - () ()) -;------------------------------------------------------------- -; mulex - multiple extend sign (m32) -;------------------------------------------------------------- - -; mulex src,dst -; (dni mulex-absolute-indirect "mulex [src]" ((machine 32)) -; ("mulex ${dst32-24-absolute-indirect-HI}") -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) -; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI))) -; ()) -(dni mulex "mulex src" ((machine 32)) - ("mulex ${dst32-16-Unprefixed-Mulex-HI}") - (+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) - (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI))) - ()) -; (dni mulex-indirect "mulex [src]" ((machine 32)) -; ("mulex ${dst32-24-indirect-HI}") -; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE)) -; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI))) -; ()) - -;------------------------------------------------------------- -; mulu - multiply unsigned -;------------------------------------------------------------- - -(define-pmacro (mulu-sem mode src1 dst) - (sequence ((mode result)) - (set obit (add-oflag mode src1 dst 0)) - (set result (mul mode src1 dst)) - (set dst result)) -) - -; mulu.BW #imm,dst -(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem) -; mulu.BW src,dst -(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem) - -;------------------------------------------------------------- -; neg - twos complement -;------------------------------------------------------------- - -(define-pmacro (neg-sem mode dst) - (sequence ((mode result)) - (set result (neg mode dst)) - (set-z-and-s result) - (set dst result)) -) - -; neg.BW:G -(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem) - -;------------------------------------------------------------- -; not - twos complement -;------------------------------------------------------------- - -(define-pmacro (not-sem mode dst) - (sequence ((mode result)) - (set result (not mode dst)) - (set-z-and-s result) - (set dst result)) -) - -; not.BW:G -(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) - -(dni not16.b.s - "not.b:s Dst16-3-S-8" - ((machine 16)) - "not.b:s ${Dst16-3-S-8}" - (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8) - (not-sem QI Dst16-3-S-8) - ()) - -;------------------------------------------------------------- -; nop -;------------------------------------------------------------- - -(dni nop16 - "nop" - ((machine 16)) - "nop" - (+ (f-0-4 #x0) (f-4-4 #x4)) - (nop) - ()) - -(dni nop32 - "nop" - ((machine 32)) - "nop" - (+ (f-0-4 #xD) (f-4-4 #xE)) - (nop) - ()) - -;------------------------------------------------------------- -; or - logical or -;------------------------------------------------------------- - -(define-pmacro (or-sem mode src1 dst) - (sequence ((mode result)) - (set result (or mode src1 dst)) - (set-z-and-s result) - (set dst result)) -) - -; or.BW #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem) -; or.b:S #imm8,dst3 (m16 #2 m32 #2) -(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem) -(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem) -(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem) -; or.BW src,dst (m16 #3 m32 #3) -(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem) -; or.b:S src,r0[lh] (m16) -(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem) - -;------------------------------------------------------------- -; pop - restore register/memory -;------------------------------------------------------------- - -; TODO future: split this into .b and .w semantics -(define-pmacro (pop-sem-mach mach mode dst) - (sequence ((mode b_or_w) (SI length)) - (set b_or_w -1) - (set b_or_w (srl b_or_w #x8)) - (if (eq b_or_w #x0) - (set length 1) ; .b - (set length 2)) ; .w - - (case DFLT length - ((1) (set dst (mem-mach mach QI (reg h-sp)))) - ((2) (set dst (mem-mach mach HI (reg h-sp))))) - (set (reg h-sp) (add (reg h-sp) length)) - ) -) - -(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest)) -(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest)) - -; pop.BW:G (m16 #1) -(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G) -; pop.BW:G (m32 #1) -(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32) - -; pop.b:S r0l/r0h -(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16)) - "pop.b$S ${Rn16-push-S-anyof}" - (+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2)) - (pop-sem16 QI Rn16-push-S-anyof) - ()) -; pop.w:S a0/a1 -(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16)) - "pop.w$S ${An16-push-S-anyof}" - (+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2)) - (pop-sem16 HI An16-push-S-anyof) - ()) - -;------------------------------------------------------------- -; popc - pop control register -; pushc - push control register -;------------------------------------------------------------- - -(define-pmacro (popc32-cr1-sem mode dst) - (sequence () - (case DFLT dst - ((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp)))) - ((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp)))) - ((#x2) (sequence ((HI tflag)) - (set tflag (mem32 mode (reg h-sp))) - (if (and tflag #x1) (set cbit 1)) - (if (and tflag #x2) (set dbit 1)) - (if (and tflag #x4) (set zbit 1)) - (if (and tflag #x8) (set sbit 1)) - (if (and tflag #x10) (set bbit 1)) - (if (and tflag #x20) (set obit 1)) - (if (and tflag #x40) (set ibit 1)) - (if (and tflag #x80) (set ubit 1)))) - ((#x3) (set (reg h-svf) (mem32 mode (reg h-sp)))) - ((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp)))) - ((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp)))) - ((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp)))) - ((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp)))) - ) - (set (reg h-sp) (add (reg h-sp) 2)) - ) -) -(define-pmacro (popc32-cr2-sem mode dst) - (sequence () - (case DFLT dst - ((#x0) (set (reg h-intb) (mem32 mode (reg h-sp)))) - ((#x1) (set (reg h-sp) (mem32 mode (reg h-sp)))) - ((#x2) (set (reg h-sb) (mem32 mode (reg h-sp)))) - ((#x3) (set (reg h-fb) (mem32 mode (reg h-sp)))) - ((#x7) (set (reg h-isp) (mem32 mode (reg h-sp)))) - ) - (set (reg h-sp) (add (reg h-sp) 4)) - ) -) -(define-pmacro (popc16-sem mode dst) - (sequence () - (case DFLT dst - ((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000) - (mem16 mode (reg h-sp))))) - ((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000) - (mem16 mode (reg h-sp))))) - ((#x3) (sequence ((HI tflag)) - (set tflag (mem16 mode (reg h-sp))) - (if (and tflag #x1) (set cbit 1)) - (if (and tflag #x2) (set dbit 1)) - (if (and tflag #x4) (set zbit 1)) - (if (and tflag #x8) (set sbit 1)) - (if (and tflag #x10) (set bbit 1)) - (if (and tflag #x20) (set obit 1)) - (if (and tflag #x40) (set ibit 1)) - (if (and tflag #x80) (set ubit 1)))) - ((#x4) (set (reg h-isp) (mem16 mode (reg h-sp)))) - ((#x5) (set (reg h-sp) (mem16 mode (reg h-sp)))) - ((#x6) (set (reg h-sb) (mem16 mode (reg h-sp)))) - ((#x7) (set (reg h-fb) (mem16 mode (reg h-sp)))) - ) - (set (reg h-sp) (add (reg h-sp) 2)) - ) -) -; popc dest (m16c #1) -(dni popc16.imm16 "popc dst" ((machine 16)) - ("popc ${cr16}") - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16) - (popc16-sem HI cr16) - ()) -; popc dest (m32c #1) -(dni popc32.imm16-cr1 "popc dst" ((machine 32)) - ("popc ${cr1-Unprefixed-32}") - (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) - (popc32-cr1-sem HI cr1-Unprefixed-32) - ()) -; popc dest (m32c #2) -(dni popc32.imm16-cr2 "popc dst" ((machine 32)) - ("popc ${cr2-32}") - (+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32) - (popc32-cr2-sem SI cr2-32) - ()) - -(define-pmacro (pushc32-cr1-sem mode dst) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 2)) - (case DFLT dst - ((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0))) - ((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1))) - ((#x2) (sequence ((HI tflag)) - (set tflag 0) - (if (eq cbit 1) (set tflag (or tflag #x1))) - (if (eq dbit 1) (set tflag (or tflag #x2))) - (if (eq zbit 1) (set tflag (or tflag #x4))) - (if (eq sbit 1) (set tflag (or tflag #x8))) - (if (eq bbit 1) (set tflag (or tflag #x10))) - (if (eq obit 1) (set tflag (or tflag #x20))) - (if (eq ibit 1) (set tflag (or tflag #x40))) - (if (eq ubit 1) (set tflag (or tflag #x80))) - (set (mem32 mode (reg h-sp)) tflag))) - ((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf))) - ((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0))) - ((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1))) - ((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0))) - ((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1))) - ) - ) -) -(define-pmacro (pushc32-cr2-sem mode dst) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 4)) - (case DFLT dst - ((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb))) - ((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp))) - ((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb))) - ((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb))) - ((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp))) - ) - ) -) -(define-pmacro (pushc16-sem mode dst) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 2)) - (case DFLT dst - ((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff))) - ((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000))) - ((#x3) (sequence ((HI tflag)) - (if (eq cbit 1) (set tflag (or tflag #x1))) - (if (eq dbit 1) (set tflag (or tflag #x2))) - (if (eq zbit 1) (set tflag (or tflag #x4))) - (if (eq sbit 1) (set tflag (or tflag #x8))) - (if (eq bbit 1) (set tflag (or tflag #x10))) - (if (eq obit 1) (set tflag (or tflag #x20))) - (if (eq ibit 1) (set tflag (or tflag #x40))) - (if (eq ubit 1) (set tflag (or tflag #x80))) - (set (mem16 mode (reg h-sp)) tflag))) - - ((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp))) - ((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp))) - ((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb))) - ((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb))) - ) - ) -) -; pushc src (m16c) -(dni pushc16.imm16 "pushc dst" ((machine 16)) - ("pushc ${cr16}") - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16) - (pushc16-sem HI cr16) - ()) -; pushc src (m32c #1) -(dni pushc32.imm16-cr1 "pushc dst" ((machine 32)) - ("pushc ${cr1-Unprefixed-32}") - (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32) - (pushc32-cr1-sem HI cr1-Unprefixed-32) - ()) -; pushc src (m32c #2) -(dni pushc32.imm16-cr2 "pushc dst" ((machine 32)) - ("pushc ${cr2-32}") - (+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32) - (pushc32-cr2-sem SI cr2-32) - ()) - -;------------------------------------------------------------- -; popm - pop multiple -; pushm - push multiple -;------------------------------------------------------------- - -(define-pmacro (popm-sem machine dst) - (sequence ((SI addrlen)) - (if (eq machine 16) - (set addrlen 2) - (set addrlen 4)) - (if (and dst 1) - (sequence () (set R0 (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)))) - (if (and dst 2) - (sequence () (set R1 (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)))) - (if (and dst 4) - (sequence () (set R2 (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)))) - (if (and dst 8) - (sequence () (set R3 (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)))) - (if (and dst 16) - (sequence () (set A0 (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) addrlen)))) - (if (and dst 32) - (sequence () (set A1 (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) addrlen)))) - (if (and dst 64) - (sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) addrlen)))) - (if (eq dst 128) - (sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) addrlen)))) - ) -) - -(define-pmacro (pushm-sem machine dst) - (sequence ((SI count) (SI addrlen)) - (if (eq machine 16) - (set addrlen 2) - (set addrlen 4)) - (if (eq dst 1) - (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) - (set (mem-mach machine HI (reg h-sp)) (reg h-fb)))) - (if (and dst 2) - (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) - (set (mem-mach machine HI (reg h-sp)) (reg h-sb)))) - (if (and dst 4) - (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) - (set (mem-mach machine HI (reg h-sp)) A1))) - (if (and dst 8) - (sequence () (set (reg h-sp) (sub (reg h-sp) addrlen)) - (set (mem-mach machine HI (reg h-sp)) A0))) - (if (and dst 16) - (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem-mach machine HI (reg h-sp)) R3))) - (if (and dst 32) - (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem-mach machine HI (reg h-sp)) R2))) - (if (and dst 64) - (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem-mach machine HI (reg h-sp)) R1))) - (if (and dst 128) - (sequence () (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem-mach machine HI (reg h-sp)) R0))) - ) -) - -(dni popm16 "popm regs" ((machine 16)) - ("popm ${Regsetpop}") - (+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop) - (popm-sem 16 Regsetpop) - ()) -(dni pushm16 "pushm regs" ((machine 16)) - ("pushm ${Regsetpush}") - (+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush) - (pushm-sem 16 Regsetpush) - ()) -(dni popm "popm regs" ((machine 32)) - ("popm ${Regsetpop}") - (+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop) - (popm-sem 32 Regsetpop) - ()) -(dni pushm "pushm regs" ((machine 32)) - ("pushm ${Regsetpush}") - (+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush) - (pushm-sem 32 Regsetpush) - ()) - -;------------------------------------------------------------- -; push - Save register/memory/immediate data -;------------------------------------------------------------- - -; TODO future: split this into .b and .w semantics -(define-pmacro (push-sem-mach mach mode dst) - (sequence ((mode b_or_w) (SI length)) - (set b_or_w -1) - (set b_or_w (srl b_or_w #x8)) - (if (eq b_or_w #x0) - (set length 1) ; .b - (if (eq b_or_w #xff) - (set length 2) ; .w - (set length 4))) ; .l - (set (reg h-sp) (sub (reg h-sp) length)) - (case DFLT length - ((1) (set (mem-mach mach QI (reg h-sp)) dst)) - ((2) (set (mem-mach mach HI (reg h-sp)) dst)) - ((4) (set (mem-mach mach SI (reg h-sp)) dst))) - ) - ) - -(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst)) -(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst)) - -; push.BW:G imm (m16 #1 m32 #1) -(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16)) - ("push.b$G #${Imm-16-QI}") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI) - (push-sem16 QI Imm-16-QI) - ()) - -(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16)) - ("push.w$G #${Imm-16-HI}") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI) - (push-sem16 HI Imm-16-HI) - ()) - -(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32)) - ("push.b #${Imm-8-QI}") - (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI) - (push-sem32 QI Imm-8-QI) - ()) - -(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32)) - ("push.w #${Imm-8-HI}") - (+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI) - (push-sem32 HI Imm-8-HI) - ()) - -; push.BW:G src (m16 #2) -(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G) -; push.BW:G src (m32 #2) -(unary-insn-mach 32 push #xC #x0 #xE push-sem32) - - -; push.b:S r0l/r0h (m16 #3) -(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16)) - "push.b$S ${Rn16-push-S-anyof}" - (+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2)) - (push-sem16 QI Rn16-push-S-anyof) - ()) -; push.w:S a0/a1 (m16 #4) -(dni push16.b-s-an "push.w:S a[01]" ((machine 16)) - "push.w$S ${An16-push-S-anyof}" - (+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2)) - (push-sem16 HI An16-push-S-anyof) - ()) - -; push.l imm32 (m32 #3) -(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32)) - ("push.l #${Imm-16-SI}") - (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI) - (push-sem32 SI Imm-16-SI) - ()) -; push.l src (m32 #4) -(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32) - -;------------------------------------------------------------- -; pusha - push effective address -;------------------------------------------------------------ - -(define-pmacro (push16a-sem mode dst) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 2)) - (set (mem16 HI (reg h-sp)) dst)) -) -(define-pmacro (push32a-sem mode dst) - (sequence () - (set (reg h-sp) (sub (reg h-sp) 4)) - (set (mem32 SI (reg h-sp)) dst)) -) -(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem) -(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem) - -;------------------------------------------------------------- -; reit - return from interrupt -;------------------------------------------------------------- - -; ??? semantics -(dni reit16 "REIT" ((machine 16)) - ("reit") - (+ (f-0-4 #xF) (f-4-4 #xB)) - (nop) - ()) -(dni reit32 "REIT" ((machine 32)) - ("reit") - (+ (f-0-4 9) (f-4-4 #xE)) - (nop) - ()) - -;------------------------------------------------------------- -; rmpa - repeat multiple and addition -;------------------------------------------------------------- - -; TODO semantics -(dni rmpa16.b "rmpa.size" ((machine 16)) - ("rmpa.b") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1)) - (nop) - ()) -(dni rmpa16.w "rmpa.size" ((machine 16)) - ("rmpa.w") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1)) - (nop) - ()) -(dni rmpa32.b "rmpa.size" ((machine 32)) - ("rmpa.b") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3)) - (nop) - ()) - -(dni rmpa32.w "rmpa.size" ((machine 32)) - ("rmpa.w") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3)) - (nop) - ()) - -;------------------------------------------------------------- -; rolc - rotate left with carry -;------------------------------------------------------------- - -; TODO check semantics -; TODO future: split this into .b and .w semantics -(define-pmacro (rolc-sem mode dst) - (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask)) - (set b_or_w -1) - (set b_or_w (srl b_or_w #x8)) - (if (eq b_or_w #x0) - (set mask #x8000) ; .b - (set mask #x80000000)) ; .w - (set ocbit cbit) - (set cbit (and dst mask)) - (set result (sll mode dst 1)) - (set result (or result ocbit)) - (set-z-and-s result) - (set dst result)) -) -; rolc.BW src,dst -(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem) - -;------------------------------------------------------------- -; rorc - rotate right with carry -;------------------------------------------------------------- - -; TODO check semantics -; TODO future: split this into .b and .w semantics -(define-pmacro (rorc-sem mode dst) - (sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt)) - (set b_or_w -1) - (set b_or_w (srl b_or_w #x8)) - (if (eq b_or_w #x0) - (sequence () (set mask #x7fff) (set shamt 15)) ; .b - (sequence () (set mask #x7fffffff) (set shamt 31))) ; .w - (set ocbit cbit) - (set cbit (and dst #x1)) - (set result (srl mode dst (const 1))) - (set result (or (and result mask) (sll ocbit shamt))) - (set-z-and-s result) - (set dst result)) -) -; rorc.BW src,dst -(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem) - -;------------------------------------------------------------- -; rot - rotate -;------------------------------------------------------------- - -; TODO future: split this into .b and .w semantics -(define-pmacro (rot-1-sem mode src1 dst) - (sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift)) - (case DFLT src1 - ((#x0) (set shift 1)) - ((#x1) (set shift 2)) - ((#x2) (set shift 3)) - ((#x3) (set shift 4)) - ((#x4) (set shift 5)) - ((#x5) (set shift 6)) - ((#x6) (set shift 7)) - ((#x7) (set shift 8)) - ((-8) (set shift -1)) - ((-7) (set shift -2)) - ((-6) (set shift -3)) - ((-5) (set shift -4)) - ((-4) (set shift -5)) - ((-3) (set shift -6)) - ((-2) (set shift -7)) - ((-1) (set shift -8)) - (else (set shift 0)) - ) - (set b_or_w -1) - (set b_or_w (srl b_or_w #x8)) - (if (eq b_or_w #x0) - (set mask #x7fff) ; .b - (set mask #x7fffffff)) ; .w - (set tmp dst) - (if (gt mode shift 0) - (sequence () - (set tmp (rol mode tmp shift)) - (set cbit (and tmp #x1))) - (sequence () - (set tmp (ror mode tmp (mul shift -1))) - (set cbit (and tmp mask)))) - (set-z-and-s tmp) - (set dst tmp)) -) -(define-pmacro (rot-2-sem mode dst) - (sequence ((mode tmp) (mode b_or_w) (USI mask)) - (set b_or_w -1) - (set b_or_w (srl b_or_w #x8)) - (if (eq b_or_w #x0) - (set mask #x7fff) ; .b - (set mask #x7fffffff)) ; .w - (set tmp dst) - (if (gt mode (reg h-r1h) 0) - (sequence () - (set tmp (rol mode tmp (reg h-r1h))) - (set cbit (and tmp #x1))) - (sequence () - (set tmp (ror mode tmp (reg h-r1h))) - (set cbit (and tmp mask)))) - (set-z-and-s tmp) - (set dst tmp)) -) - -; rot.BW #imm4,dst -(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) -(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem) -(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem) -(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem) -; rot.BW src,dst - -(dni rot16.b-dst "rot r1h,dest" ((machine 16)) - ("rot.b r1h,${dst16-16-QI}") - (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI) - (rot-2-sem QI dst16-16-QI) - ()) -(dni rot16.w-dst "rot r1h,dest" ((machine 16)) - ("rot.w r1h,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI) - (rot-2-sem HI dst16-16-HI) - ()) - -(dni rot32.b-dst "rot r1h,dest" ((machine 32)) - ("rot.b r1h,${dst32-16-Unprefixed-QI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem QI dst32-16-Unprefixed-QI) - ()) -(dni rot32.w-dst "rot r1h,dest" ((machine 32)) - ("rot.w r1h,${dst32-16-Unprefixed-HI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem HI dst32-16-Unprefixed-HI) - ()) - -;------------------------------------------------------------- -; rts - return from subroutine -;------------------------------------------------------------- - -(define-pmacro (rts16-sem) - (sequence ((SI tpc)) - (set tpc (mem16 HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)) - (set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16))) - (set (reg h-sp) (add (reg h-sp) 1)) - (set pc tpc) - ) -) -(define-pmacro (rts32-sem) - (sequence ((SI tpc)) - (set tpc (mem32 HI (reg h-sp))) - (set (reg h-sp) (add (reg h-sp) 2)) - (set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16))) - (set (reg h-sp) (add (reg h-sp) 2)) - (set pc tpc) - ) -) - -(dni rts16 "rts" ((machine 16)) - ("rts") - (+ (f-0-4 #xF) (f-4-4 3)) - (rts16-sem) - ()) - -(dni rts32 "rts" ((machine 32)) - ("rts") - (+ (f-0-4 #xD) (f-4-4 #xF)) - (rts32-sem) - ()) - -;------------------------------------------------------------- -; sbb - subtract with borrow -;------------------------------------------------------------- - -(define-pmacro (sbb-sem mode src dst) - (sequence ((mode result)) - (set result (subc mode dst src cbit)) - (set obit (add-oflag mode dst src cbit)) - (set cbit (add-oflag mode dst src cbit)) - (set-z-and-s result) - (set dst result)) -) - -; sbb.size:G #imm,dst -(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) -(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem) -(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem) -(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem) - -; sbb.BW:G src,dst -(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) -(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem) -(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem) - -;------------------------------------------------------------- -; sbjnz - subtract then jump on not zero -;------------------------------------------------------------- - -(define-pmacro (sub-jnz-sem mode src dst label) - (sequence ((mode result)) - (set result (sub mode dst src)) - (set dst result) - (if (ne result 0) - (set pc label))) -) - -; sbjnz.size #imm4,dst,label -(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) - -;------------------------------------------------------------- -; sccnd - store condition on condition (m32) -;------------------------------------------------------------- - -(define-pmacro (sccnd-sem cnd dst) - (sequence () - (set dst 0) - (case DFLT cnd - ((#x00) (if (not cbit) (set dst 1))) ;ltu nc - ((#x01) (if (or cbit zbit) (set dst 1))) ;leu - ((#x02) (if (not zbit) (set dst 1))) ;ne nz - ((#x03) (if (not sbit) (set dst 1))) ;pz - ((#x04) (if (not obit) (set dst 1))) ;no - ((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt - ((#x06) (if (xor sbit obit) (set dst 1))) ;ge - ((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c - ((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu - ((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z - ((#x0b) (if (trunc BI sbit) (set dst 1))) ;n - ((#x0c) (if (trunc BI obit) (set dst 1))) ;o - ((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le - ((#x0e) (if (xor sbit obit) (set dst 1))) ;lt - ) - ) - ) - -; scCND dst -(dni sccnd - "sccnd dst" - ((machine 32)) - "sc$sccond32 ${dst32-16-Unprefixed-HI}" - (+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32) - (sccnd-sem sccond32 dst32-16-Unprefixed-HI) - ()) - -;------------------------------------------------------------- -; scmpu - string compare unequal (m32) -;------------------------------------------------------------- - -; TODO semantics -(dni scmpu.b "scmpu.b" ((machine 32)) - ("scmpu.b") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3)) - (c-call VOID "scmpu_QI_semantics") - ()) - -(dni scmpu.w "scmpu.w" ((machine 32)) - ("scmpu.w") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3)) - (c-call VOID "scmpu_HI_semantics") - ()) - -;------------------------------------------------------------- -; sha - shift arithmetic -;------------------------------------------------------------- - -; TODO future: split this into .b and .w semantics -(define-pmacro (sha-sem mode src1 dst) - (sequence ((mode result)(mode shift)(mode shmode)) - (case DFLT src1 - ((#x0) (set shift 1)) - ((#x1) (set shift 2)) - ((#x2) (set shift 3)) - ((#x3) (set shift 4)) - ((#x4) (set shift 5)) - ((#x5) (set shift 6)) - ((#x6) (set shift 7)) - ((#x7) (set shift 8)) - ((-8) (set shift -1)) - ((-7) (set shift -2)) - ((-6) (set shift -3)) - ((-5) (set shift -4)) - ((-4) (set shift -5)) - ((-3) (set shift -6)) - ((-2) (set shift -7)) - ((-1) (set shift -8)) - (else (set shift 0)) - ) - (set shmode -1) - (set shmode (srl shmode #x8)) - (if (lt mode shift #x0) (set result (sra mode dst (mul shift -1)))) - (if (gt mode shift 0) (set result (sll mode dst shift))) - (if (eq shmode #x0) ; QI - (sequence - ((mode cbitamt)) - (if (lt mode shift #x0) - (set cbitamt (sub #x8 shift)) ; sra - (set cbitamt (sub shift 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) - (set obit (ne (and dst #x80) (and result #x80))) - )) - (if (eq shmode #xff) ; HI - (sequence - ((mode cbitamt)) - (if (lt mode shift #x0) - (set cbitamt (sub 16 shift)) ; sra - (set cbitamt (sub shift 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) - (set obit (ne (and dst #x8000) (and result #x8000))) - )) - (set-z-and-s result) - (set dst result)) -) -(define-pmacro (shar1h-sem mode dst) - (sequence ((mode result)(mode shmode)) - (set shmode -1) - (set shmode (srl shmode #x8)) - (if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h)))) - (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) - (if (eq shmode #x0) ; QI - (sequence - ((mode cbitamt)) - (if (lt mode (reg h-r1h) #x0) - (set cbitamt (sub #x8 (reg h-r1h))) ; sra - (set cbitamt (sub (reg h-r1h) 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) - (set obit (ne (and dst #x80) (and result #x80))) - )) - (if (eq shmode #xff) ; HI - (sequence - ((mode cbitamt)) - (if (lt mode (reg h-r1h) #x0) - (set cbitamt (sub 16 (reg h-r1h))) ; sra - (set cbitamt (sub (reg h-r1h) 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) - (set obit (ne (and dst #x8000) (and result #x8000))) - )) - (set-z-and-s result) - (set dst result)) -) -; sha.BW #imm4,dst (m16 #1 m32 #1) -(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem) -(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem) -(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem) -(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem) -; sha.BW r1h,dst (m16 #2 m32 #3) -(dni sha16.b-dst "sha.b r1h,dest" ((machine 16)) - ("sha.b r1h,${dst16-16-QI}") - (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI) - (shar1h-sem HI dst16-16-QI) - ()) -(dni sha16.w-dst "sha.w r1h,dest" ((machine 16)) - ("sha.w r1h,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI) - (shar1h-sem HI dst16-16-HI) - ()) -(dni sha32.b-dst "sha.b r1h,dest" ((machine 32)) - ("sha.b r1h,${dst32-16-Unprefixed-QI}") - (+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) - (shar1h-sem QI dst32-16-Unprefixed-QI) - ()) -(dni sha32.w-dst "sha.w r1h,dest" ((machine 32)) - ("sha.w r1h,${dst32-16-Unprefixed-HI}") - (+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) - (shar1h-sem HI dst32-16-Unprefixed-HI) - ()) -; sha.L #imm,dst (m16 #3) -(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16)) - "sha.l #${Imm-sh-12-s4},r2r0" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4) - (sha-sem SI Imm-sh-12-s4 (reg h-r2r0)) - ()) -(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16)) - "sha.l #${Imm-sh-12-s4},r3r1" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4) - (sha-sem SI Imm-sh-12-s4 (reg h-r3r1)) - ()) -; sha.L r1h,dst (m16 #4) -(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16)) - "sha.l r1h,r2r0" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1)) - (sha-sem SI (reg h-r1h) (reg h-r2r0)) - ()) -(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16)) - "sha.l r1h,r3r1" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1)) - (sha-sem SI (reg h-r1h) (reg h-r3r1)) - ()) -; sha.L #imm8,dst (m32 #2) -(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem) -; sha.L r1h,dst (m32 #4) -(dni sha32.l-dst "sha.l r1h,dest" ((machine 32)) - ("sha.l r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1)) - (shar1h-sem QI dst32-16-Unprefixed-SI) - ()) - -;------------------------------------------------------------- -; shanc - shift arithmetic non carry (m32) -;------------------------------------------------------------- - -; TODO check semantics -; shanc.L #imm8,dst -(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem) - -;------------------------------------------------------------- -; shl - shift logical -;------------------------------------------------------------- - -; TODO future: split this into .b and .w semantics -(define-pmacro (shl-sem mode src1 dst) - (sequence ((mode result)(mode shift)(mode shmode)) - (case DFLT src1 - ((#x0) (set shift 1)) - ((#x1) (set shift 2)) - ((#x2) (set shift 3)) - ((#x3) (set shift 4)) - ((#x4) (set shift 5)) - ((#x5) (set shift 6)) - ((#x6) (set shift 7)) - ((#x7) (set shift 8)) - ((-8) (set shift -1)) - ((-7) (set shift -2)) - ((-6) (set shift -3)) - ((-5) (set shift -4)) - ((-4) (set shift -5)) - ((-3) (set shift -6)) - ((-2) (set shift -7)) - ((-1) (set shift -8)) - (else (set shift 0)) - ) - (set shmode -1) - (set shmode (srl shmode #x8)) - (if (lt mode shift #x0) (set result (srl mode dst (mul shift -1)))) - (if (gt mode shift 0) (set result (sll mode dst shift))) - (if (eq shmode #x0) ; QI - (sequence - ((mode cbitamt)) - (if (lt mode shift #x0) - (set cbitamt (sub #x8 shift)); srl - (set cbitamt (sub shift 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) - (set obit (ne (and dst #x80) (and result #x80))) - )) - (if (eq shmode #xff) ; HI - (sequence - ((mode cbitamt)) - (if (lt mode shift #x0) - (set cbitamt (sub 16 shift)) ; srl - (set cbitamt (sub shift 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) - (set obit (ne (and dst #x8000) (and result #x8000))) - )) - (set-z-and-s result) - (set dst result)) - ) -(define-pmacro (shlr1h-sem mode dst) - (sequence ((mode result)(mode shmode)) - (set shmode -1) - (set shmode (srl shmode #x8)) - (if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h)))) - (if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h)))) - (if (eq shmode #x0) ; QI - (sequence - ((mode cbitamt)) - (if (lt mode (reg h-r1h) #x0) - (set cbitamt (sub #x8 (reg h-r1h))) ; srl - (set cbitamt (sub (reg h-r1h) 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x80) #x7)) - (set obit (ne (and dst #x80) (and result #x80))) - )) - (if (eq shmode #xff) ; HI - (sequence - ((mode cbitamt)) - (if (lt mode (reg h-r1h) #x0) - (set cbitamt (sub 16 (reg h-r1h))) ; srl - (set cbitamt (sub (reg h-r1h) 1))) ; sll - (set cbit (srl (and (sll dst cbitamt) #x8000) #xf)) - (set obit (ne (and dst #x8000) (and result #x8000))) - )) - (set-z-and-s result) - (set dst result)) - ) -; shl.BW #imm4,dst (m16 #1 m32 #1) -(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem) -(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem) -(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem) -(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem) -; shl.BW r1h,dst (m16 #2 m32 #3) -(dni shl16.b-dst "shl.b r1h,dest" ((machine 16)) - ("shl.b r1h,${dst16-16-QI}") - (+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI) - (shlr1h-sem HI dst16-16-QI) - ()) -(dni shl16.w-dst "shl.w r1h,dest" ((machine 16)) - ("shl.w r1h,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI) - (shlr1h-sem HI dst16-16-HI) - ()) -(dni shl32.b-dst "shl.b r1h,dest" ((machine 32)) - ("shl.b r1h,${dst32-16-Unprefixed-QI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE)) - (shlr1h-sem QI dst32-16-Unprefixed-QI) - ()) -(dni shl32.w-dst "shl.w r1h,dest" ((machine 32)) - ("shl.w r1h,${dst32-16-Unprefixed-HI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE)) - (shlr1h-sem HI dst32-16-Unprefixed-HI) - ()) -; shl.L #imm,dst (m16 #3) -(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16)) - "shl.l #${Imm-sh-12-s4},r2r0" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4) - (shl-sem SI Imm-sh-12-s4 (reg h-r2r0)) - ()) -(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16)) - "shl.l #${Imm-sh-12-s4},r3r1" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4) - (shl-sem SI Imm-sh-12-s4 (reg h-r3r1)) - ()) -; shl.L r1h,dst (m16 #4) -(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16)) - "shl.l r1h,r2r0" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1)) - (shl-sem SI (reg h-r1h) (reg h-r2r0)) - ()) -(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16)) - "shl.l r1h,r3r1" - (+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1)) - (shl-sem SI (reg h-r1h) (reg h-r3r1)) - ()) -; shl.L #imm8,dst (m32 #2) -(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem) -; shl.L r1h,dst (m32 #4) -(dni shl32.l-dst "shl.l r1h,dest" ((machine 32)) - ("shl.l r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1)) - (shlr1h-sem QI dst32-16-Unprefixed-SI) - ()) - -;------------------------------------------------------------- -; shlnc - shift logical non carry -;------------------------------------------------------------- - -; TODO check semantics -; shlnc.L #imm8,dst -(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem) - -;------------------------------------------------------------- -; sin - string input (m32) -;------------------------------------------------------------- - -; TODO semantics -(dni sin32.b "sin" ((machine 32)) - ("sin.b") - (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3)) - (c-call VOID "sin_QI_semantics") - ()) - -(dni sin32.w "sin" ((machine 32)) - ("sin.w") - (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3)) - (c-call VOID "sin_HI_semantics") - ()) - -;------------------------------------------------------------- -; smovb - string move backward -;------------------------------------------------------------- - -; TODO semantics -(dni smovb16.b "smovb.b" ((machine 16)) - ("smovb.b") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9)) - (c-call VOID "smovb_QI_semantics") - ()) - -(dni smovb16.w "smovb.w" ((machine 16)) - ("smovb.w") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9)) - (c-call VOID "smovb_HI_semantics") - ()) - -(dni smovb32.b "smovb.b" ((machine 32)) - ("smovb.b") - (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3)) - (c-call VOID "smovb_QI_semantics") - ()) - -(dni smovb32.w "smovb.w" ((machine 32)) - ("smovb.w") - (+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3)) - (c-call VOID "smovb_HI_semantics") - ()) - -;------------------------------------------------------------- -; smovf - string move forward (m32) -;------------------------------------------------------------- - -; TODO semantics -(dni smovf16.b "smovf.b" ((machine 16)) - ("smovf.b") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8)) - (c-call VOID "smovf_QI_semantics") - ()) - -(dni smovf16.w "smovf.w" ((machine 16)) - ("smovf.w") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8)) - (c-call VOID "smovf_HI_semantics") - ()) - -(dni smovf32.b "smovf.b" ((machine 32)) - ("smovf.b") - (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3)) - (c-call VOID "smovf_QI_semantics") - ()) - -(dni smovf32.w "smovf.w" ((machine 32)) - ("smovf.w") - (+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3)) - (c-call VOID "smovf_HI_semantics") - ()) - -;------------------------------------------------------------- -; smovu - string move unequal (m32) -;------------------------------------------------------------- - -; TODO semantics -(dni smovu.b "smovu.b" ((machine 32)) - ("smovu.b") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3)) - (c-call VOID "smovu_QI_semantics") - ()) - -(dni smovu.w "smovu.w" ((machine 32)) - ("smovu.w") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3)) - (c-call VOID "smovu_HI_semantics") - ()) - -;------------------------------------------------------------- -; sout - string output (m32) -;------------------------------------------------------------- - -; TODO semantics -(dni sout.b "sout.b" ((machine 32)) - ("sout.b") - (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3)) - (c-call VOID "sout_QI_semantics") - ()) - -(dni sout.w "sout" ((machine 32)) - ("sout.w") - (+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3)) - (c-call VOID "sout_HI_semantics") - ()) - -;------------------------------------------------------------- -; sstr - string store -;------------------------------------------------------------- - -; TODO semantics -(dni sstr16.b "sstr.b" ((machine 16)) - ("sstr.b") - (+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA)) - (c-call VOID "sstr_QI_semantics") - ()) - -(dni sstr16.w "sstr.w" ((machine 16)) - ("sstr.w") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA)) - (c-call VOID "sstr_HI_semantics") - ()) - -(dni sstr.b "sstr" ((machine 32)) - ("sstr.b") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3)) - (c-call VOID "sstr_QI_semantics") - ()) - -(dni sstr.w "sstr" ((machine 32)) - ("sstr.w") - (+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3)) - (c-call VOID "sstr_HI_semantics") - ()) - -;------------------------------------------------------------- -; stnz - store on not zero -;------------------------------------------------------------- - -(define-pmacro (stnz-sem mode src dst) - (sequence () - (if (ne zbit (const 1)) - (set dst src))) -) -; stnz #imm8,dst3 (m16) -(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem) -; stnz.BW #imm,dst (m32) -(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem) -(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem) - -;------------------------------------------------------------- -; stz - store on zero -;------------------------------------------------------------- - -(define-pmacro (stz-sem mode src dst) - (sequence () - (if (eq zbit (const 1)) - (set dst src))) -) -; stz #imm8,dst3 (m16) -(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem) -; stz.BW #imm,dst (m32) -(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem) -(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem) - -;------------------------------------------------------------- -; stzx - store on zero extention -;------------------------------------------------------------- - -(define-pmacro (stzx-sem mode src1 src2 dst) - (sequence () - (if (eq zbit (const 1)) - (set dst src1) - (set dst src2))) - ) -; stzx #imm8,dst3 (m16) -(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},r0h") - (+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI) - (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h)) - ()) -(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},r0l") - (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI) - (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l)) - ()) -(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]") - (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI) - (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8))) - ()) -(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI) - (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8))) - ()) -(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") - (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) - (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) - ()) -; stzx.BW #imm,dst (m32) -(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem) - -;------------------------------------------------------------- -; subx - subtract extend (m32) -;------------------------------------------------------------- - -(define-pmacro (subx-sem mode src1 dst) - (sequence ((mode result)) - (set result (sub mode dst (ext mode src1))) - (set obit (sub-oflag mode dst (ext mode src1) 0)) - (set cbit (sub-cflag mode dst (ext mode src1) 0)) - (set dst result) - (set-z-and-s result))) -; subx #imm8,dst -(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem) -; subx src,dst -(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem) - -;------------------------------------------------------------- -; tst - test -;------------------------------------------------------------- - -(define-pmacro (tst-sem mode src1 dst) - (sequence ((mode result)) - (set result (and mode dst src1)) - (set-z-and-s result)) -) - -; tst.BW #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) -; tst.BW src,dst (m16 #2 m32 #3) -(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) -(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) -(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem) -; tst.BW:S #imm,dst2 (m32 #2) -(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem) -(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem) - -;------------------------------------------------------------- -; und - undefined -;------------------------------------------------------------- - -(dni und16 "und" ((machine 16)) - ("und") - (+ (f-0-4 #xF) (f-4-4 #xF)) - (nop) - ()) - -(dni und32 "und" ((machine 32)) - ("und") - (+ (f-0-4 #xF) (f-4-4 #xF)) - (nop) - ()) - -;------------------------------------------------------------- -; wait -;------------------------------------------------------------- - -; ??? semantics -(dni wait16 "wait" ((machine 16)) - ("wait") - (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3)) - (nop) - ()) - -(dni wait "wait" ((machine 32)) - ("wait") - (+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3)) - (nop) - ()) - -;------------------------------------------------------------- -; xchg - exchange -;------------------------------------------------------------- - -(define-pmacro (xchg-sem mode src dst) - (sequence ((mode result)) - (set result src) - (set src dst) - (set dst result)) - ) -(define-pmacro (xchg16-defn mode sz szc src srcreg) - (dni (.sym xchg16 sz - srcreg) - (.str "xchg" sz "-" srcreg ",dst16-16-" mode) - ((machine 16)) - (.str "xchg." sz " " srcreg ",${dst16-16-" mode "}") - (+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode)) - (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode)) - ()) -) -(xchg16-defn QI b 0 0 r0l) -(xchg16-defn QI b 0 1 r0h) -(xchg16-defn QI b 0 2 r1l) -(xchg16-defn QI b 0 3 r1h) -(xchg16-defn HI w 1 0 r0) -(xchg16-defn HI w 1 1 r1) -(xchg16-defn HI w 1 2 r2) -(xchg16-defn HI w 1 3 r3) -(define-pmacro (xchg32-defn mode sz szc src srcreg) - (dni (.sym xchg32 sz - srcreg) - (.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode) - ((machine 32)) - (.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}") - (+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src)) - (xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode)) - ()) -) -(xchg32-defn QI b 0 0 r0l) -(xchg32-defn QI b 0 1 r1l) -(xchg32-defn QI b 0 2 a0) -(xchg32-defn QI b 0 3 a1) -(xchg32-defn QI b 0 4 r0h) -(xchg32-defn QI b 0 5 r1h) -(xchg32-defn HI w 1 0 r0) -(xchg32-defn HI w 1 1 r1) -(xchg32-defn HI w 1 2 a0) -(xchg32-defn HI w 1 3 a1) -(xchg32-defn HI w 1 4 r2) -(xchg32-defn HI w 1 5 r3) - -;------------------------------------------------------------- -; xor - exclusive or -;------------------------------------------------------------- - -(define-pmacro (xor-sem mode src1 dst) - (sequence ((mode result)) - (set result (xor mode src1 dst)) - (set-z-and-s result) - (set dst result)) -) - -; xor.BW #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem) -; xor.BW src,dst (m16 #3 m32 #3) -(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem) - -;------------------------------------------------------------- -; Widening -;------------------------------------------------------------- - -(define-pmacro (exts-sem smode dmode src dst) - (set dst (ext dmode (trunc smode src))) -) -(define-pmacro (extz-sem smode dmode src dst) - (set dst (zext dmode (trunc smode src))) -) - -; exts.b dst for m16c -(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem) - -; exts.w r0 for m16c -(dni exts16.w-r0 - "exts.w r0" - ((machine 16)) - "exts.w r0" - (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3)) - (exts-sem HI SI R0 R2R0) - ()) - -; exts.size dst for m32c -(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) -(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem) -; exts.b src,dst for m32c -(ext32-binary-defn exts .b #x1 #x7 exts-sem) - -; extz.b src,dst for m32c -(ext32-binary-defn extz "" #x1 #xB extz-sem) - -;------------------------------------------------------------- -; Indirect -;------------------------------------------------------------- - -; TODO semantics -(dni srcind "SRC-INDIRECT" ((machine 32)) - ("src-indirect") - (+ (f-0-4 4) (f-4-4 1)) - (set (reg h-src-indirect) 1) - ()) - -(dni destind "DEST-INDIRECT" ((machine 32)) - ("dest-indirect") - (+ (f-0-4 0) (f-4-4 9)) - (set (reg h-dst-indirect) 1) - ()) - -(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32)) - ("src-dest-indirect") - (+ (f-0-4 4) (f-4-4 9)) - (sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1)) - ()) diff --git a/binutils-2.24/cpu/m32c.opc b/binutils-2.24/cpu/m32c.opc deleted file mode 100644 index 2796e1c1..00000000 --- a/binutils-2.24/cpu/m32c.opc +++ /dev/null @@ -1,1182 +0,0 @@ -/* m32c opcode support. -*- C -*- - - Copyright 2005, 2007, 2009, 2010 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; developed under contract from Renesas - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* This file is an addendum to m32c.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* Needed for RTL's 'ext' and 'trunc' operators. */ -#include "cgen/basic-modes.h" -#include "cgen/basic-ops.h" - -/* We can't use the default hash size because many bits are used by - operands. */ -#define CGEN_DIS_HASH_SIZE 1 -#define CGEN_DIS_HASH(buf, value) 0 -#define CGEN_VERBOSE_ASSEMBLER_ERRORS -#define CGEN_VALIDATE_INSN_SUPPORTED - -extern int m32c_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); - -#define CGEN_ASM_HASH_SIZE 0xffff -#define CGEN_ASM_HASH(mnem) m32c_asm_hash ((mnem)) - -/* -- */ - -/* -- opc.c */ -static unsigned int -m32c_asm_hash (const char *mnem) -{ - unsigned int h; - - /* The length of the mnemonic for the Jcnd insns is 1. Hash jsri. */ - if (mnem[0] == 'j' && mnem[1] != 's') - return 'j'; - - /* Don't hash scCND */ - if (mnem[0] == 's' && mnem[1] == 'c') - return 's'; - - /* Don't hash bmCND */ - if (mnem[0] == 'b' && mnem[1] == 'm') - return 'b'; - - for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem) - h += *mnem; - return h % CGEN_ASM_HASH_SIZE; -} - -/* -- asm.c */ -#include "safe-ctype.h" - -#define MACH_M32C 5 /* Must match md_begin. */ - -static int -m32c_cgen_isa_register (const char **strp) - { - int u; - const char *s = *strp; - static char * m32c_register_names [] = - { - "r0", "r1", "r2", "r3", "r0l", "r0h", "r1l", "r1h", - "a0", "a1", "r2r0", "r3r1", "sp", "fb", "dct0", "dct1", "flg", "svf", - "drc0", "drc1", "dmd0", "dmd1", "intb", "svp", "vct", "isp", "dma0", - "dma1", "dra0", "dra1", "dsa0", "dsa1", 0 - }; - - for (u = 0; m32c_register_names[u]; u++) - { - int len = strlen (m32c_register_names[u]); - - if (memcmp (m32c_register_names[u], s, len) == 0 - && (s[len] == 0 || ! ISALNUM (s[len]))) - return 1; - } - return 0; -} - -#define PARSE_UNSIGNED \ - do \ - { \ - /* Don't successfully parse literals beginning with '['. */ \ - if (**strp == '[') \ - return "Invalid literal"; /* Anything -- will not be seen. */ \ - \ - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value);\ - if (errmsg) \ - return errmsg; \ - } \ - while (0) - -#define PARSE_SIGNED \ - do \ - { \ - /* Don't successfully parse literals beginning with '['. */ \ - if (**strp == '[') \ - return "Invalid literal"; /* Anything -- will not be seen. */ \ - \ - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); \ - if (errmsg) \ - return errmsg; \ - } \ - while (0) - -static const char * -parse_unsigned6 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value; - - PARSE_UNSIGNED; - - if (value > 0x3f) - return _("imm:6 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned8 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value = 0; - long have_zero = 0; - - if (strncasecmp (*strp, "%dsp8(", 6) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma val; - - *strp += 6; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_8, - & result_type, & val); - if (**strp != ')') - return _("missing `)'"); - (*strp) ++; - - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - return _("%dsp8() takes a symbolic address, not a number"); - - value = val; - *valuep = value; - return errmsg; - } - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - - PARSE_UNSIGNED; - - if (value > 0xff) - return _("dsp:8 immediate is out of range"); - - /* If this field may require a relocation then use larger dsp16. */ - if (! have_zero && value == 0) - return _("dsp:8 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_signed4 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - long have_zero = 0; - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - - PARSE_SIGNED; - - if (value < -8 || value > 7) - return _("Immediate is out of range -8 to 7"); - - /* If this field may require a relocation then use larger dsp16. */ - if (! have_zero && value == 0) - return _("Immediate is out of range -8 to 7"); - - *valuep = value; - return 0; -} - -static const char * -parse_signed4n (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - long have_zero = 0; - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - - PARSE_SIGNED; - - if (value < -7 || value > 8) - return _("Immediate is out of range -7 to 8"); - - /* If this field may require a relocation then use larger dsp16. */ - if (! have_zero && value == 0) - return _("Immediate is out of range -7 to 8"); - - *valuep = -value; - return 0; -} - -static const char * -parse_signed8 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value = 0; - - if (strncasecmp (*strp, "%hi8(", 5) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma val; - - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32C_HI8, - & result_type, & val); - if (**strp != ')') - return _("missing `)'"); - (*strp) ++; - - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - val >>= 16; - - value = val; - *valuep = value; - return errmsg; - } - - PARSE_SIGNED; - - if (value <= 255 && value > 127) - value -= 0x100; - - if (value < -128 || value > 127) - return _("dsp:8 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value = 0; - long have_zero = 0; - - if (strncasecmp (*strp, "%dsp16(", 7) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma val; - - *strp += 7; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, - & result_type, & val); - if (**strp != ')') - return _("missing `)'"); - (*strp) ++; - - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - return _("%dsp16() takes a symbolic address, not a number"); - - value = val; - *valuep = value; - return errmsg; - } - - /* Don't successfully parse literals beginning with '['. */ - if (**strp == '[') - return "Invalid literal"; /* Anything -- will not be seen. */ - - /* Don't successfully parse register names. */ - if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* Anything -- will not be seen. */ - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value > 0xffff) - return _("dsp:16 immediate is out of range"); - - /* If this field may require a relocation then use larger dsp24. */ - if (cd->machs == MACH_M32C && ! have_zero && value == 0 - && (strncmp (*strp, "[a", 2) == 0 - || **strp == ',' - || **strp == 0)) - return _("dsp:16 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_signed16 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value = 0; - - if (strncasecmp (*strp, "%lo16(", 6) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma val; - - *strp += 6; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - & result_type, & val); - if (**strp != ')') - return _("missing `)'"); - (*strp) ++; - - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - val &= 0xffff; - - value = val; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%hi16(", 6) == 0) - { - enum cgen_parse_operand_result result_type; - bfd_vma val; - - *strp += 6; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - & result_type, & val); - if (**strp != ')') - return _("missing `)'"); - (*strp) ++; - - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - val >>= 16; - - value = val; - *valuep = value; - return errmsg; - } - - PARSE_SIGNED; - - if (value <= 65535 && value > 32767) - value -= 0x10000; - - if (value < -32768 || value > 32767) - return _("dsp:16 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned20 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value; - - /* Don't successfully parse literals beginning with '['. */ - if (**strp == '[') - return "Invalid literal"; /* Anything -- will not be seen. */ - - /* Don't successfully parse register names. */ - if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* Anything -- will not be seen. */ - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value > 0xfffff) - return _("dsp:20 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value; - - /* Don't successfully parse literals beginning with '['. */ - if (**strp == '[') - return "Invalid literal"; /* Anything -- will not be seen. */ - - /* Don't successfully parse register names. */ - if (m32c_cgen_isa_register (strp)) - return "Invalid literal"; /* Anything -- will not be seen. */ - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value > 0xffffff) - return _("dsp:24 immediate is out of range"); - - *valuep = value; - return 0; -} - -/* This should only be used for #imm->reg. */ -static const char * -parse_signed24 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - PARSE_SIGNED; - - if (value <= 0xffffff && value > 0x7fffff) - value -= 0x1000000; - - if (value > 0xffffff) - return _("dsp:24 immediate is out of range"); - - *valuep = value; - return 0; -} - -static const char * -parse_signed32 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - *valuep = value; - return 0; -} - -static const char * -parse_imm1_S (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value < 1 || value > 2) - return _("immediate is out of range 1-2"); - - *valuep = value; - return 0; -} - -static const char * -parse_imm3_S (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value < 1 || value > 8) - return _("immediate is out of range 1-8"); - - *valuep = value; - return 0; -} - -static const char * -parse_bit3_S (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value < 0 || value > 7) - return _("immediate is out of range 0-7"); - - *valuep = value; - return 0; -} - -static const char * -parse_lab_5_3 (CGEN_CPU_DESC cd, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - int opinfo, - enum cgen_parse_operand_result *type_addr, - bfd_vma *valuep) -{ - const char *errmsg = 0; - bfd_vma value; - enum cgen_parse_operand_result op_res; - - errmsg = cgen_parse_address (cd, strp, M32C_OPERAND_LAB_5_3, - opinfo, & op_res, & value); - - if (type_addr) - *type_addr = op_res; - - if (op_res == CGEN_PARSE_OPERAND_RESULT_QUEUED) - { - /* This is a hack; the field cannot handle near-zero signed - offsets that CGEN wants to put in to indicate an "empty" - operand at first. */ - *valuep = 2; - return 0; - } - if (errmsg) - return errmsg; - - if (value < 2 || value > 9) - return _("immediate is out of range 2-9"); - - *valuep = value; - return 0; -} - -static const char * -parse_Bitno16R (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value > 15) - return _("Bit number for indexing general register is out of range 0-15"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned_bitbase (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep, - unsigned bits, int allow_syms) -{ - const char *errmsg = 0; - unsigned long bit; - unsigned long base; - const char *newp = *strp; - unsigned long long bitbase; - long have_zero = 0; - - errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); - if (errmsg) - return errmsg; - - if (*newp != ',') - return "Missing base for bit,base:8"; - - ++newp; - - if (strncmp (newp, "0x0", 3) == 0 - || (newp[0] == '0' && newp[1] != 'x')) - have_zero = 1; - - errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & base); - if (errmsg) - return errmsg; - - bitbase = (unsigned long long) bit + ((unsigned long long) base * 8); - - if (bitbase >= (1ull << bits)) - return _("bit,base is out of range"); - - /* If this field may require a relocation then use larger displacement. */ - if (! have_zero && base == 0) - { - switch (allow_syms) { - case 0: - return _("bit,base out of range for symbol"); - case 1: - break; - case 2: - if (strncmp (newp, "[sb]", 4) != 0) - return _("bit,base out of range for symbol"); - break; - } - } - - *valuep = bitbase; - *strp = newp; - return 0; -} - -static const char * -parse_signed_bitbase (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep, - unsigned bits, int allow_syms) -{ - const char *errmsg = 0; - unsigned long bit; - signed long base; - const char *newp = *strp; - long long bitbase; - long long limit; - long have_zero = 0; - - errmsg = cgen_parse_unsigned_integer (cd, & newp, opindex, & bit); - if (errmsg) - return errmsg; - - if (*newp != ',') - return "Missing base for bit,base:8"; - - ++newp; - - if (strncmp (newp, "0x0", 3) == 0 - || (newp[0] == '0' && newp[1] != 'x')) - have_zero = 1; - - errmsg = cgen_parse_signed_integer (cd, & newp, opindex, & base); - if (errmsg) - return errmsg; - - bitbase = (long long)bit + ((long long)base * 8); - - limit = 1ll << (bits - 1); - if (bitbase < -limit || bitbase >= limit) - return _("bit,base is out of range"); - - /* If this field may require a relocation then use larger displacement. */ - if (! have_zero && base == 0 && ! allow_syms) - return _("bit,base out of range for symbol"); - - *valuep = bitbase; - *strp = newp; - return 0; -} - -static const char * -parse_unsigned_bitbase8 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - return parse_unsigned_bitbase (cd, strp, opindex, valuep, 8, 0); -} - -static const char * -parse_unsigned_bitbase11 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - return parse_unsigned_bitbase (cd, strp, opindex, valuep, 11, 0); -} - -static const char * -parse_unsigned_bitbase16 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - return parse_unsigned_bitbase (cd, strp, opindex, valuep, 16, 1); -} - -static const char * -parse_unsigned_bitbase19 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - return parse_unsigned_bitbase (cd, strp, opindex, valuep, 19, 2); -} - -static const char * -parse_unsigned_bitbase27 (CGEN_CPU_DESC cd, const char **strp, - int opindex, unsigned long *valuep) -{ - return parse_unsigned_bitbase (cd, strp, opindex, valuep, 27, 1); -} - -static const char * -parse_signed_bitbase8 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - return parse_signed_bitbase (cd, strp, opindex, valuep, 8, 1); -} - -static const char * -parse_signed_bitbase11 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - return parse_signed_bitbase (cd, strp, opindex, valuep, 11, 0); -} - -static const char * -parse_signed_bitbase19 (CGEN_CPU_DESC cd, const char **strp, - int opindex, signed long *valuep) -{ - return parse_signed_bitbase (cd, strp, opindex, valuep, 19, 1); -} - -/* Parse the suffix as :<char> or as nothing followed by a whitespace. */ - -static const char * -parse_suffix (const char **strp, char suffix) -{ - const char *newp = *strp; - - if (**strp == ':' && TOLOWER (*(*strp + 1)) == suffix) - newp = *strp + 2; - - if (ISSPACE (*newp)) - { - *strp = newp; - return 0; - } - - return "Invalid suffix"; /* Anything -- will not be seen. */ -} - -static const char * -parse_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) -{ - return parse_suffix (strp, 's'); -} - -static const char * -parse_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) -{ - return parse_suffix (strp, 'g'); -} - -static const char * -parse_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) -{ - return parse_suffix (strp, 'q'); -} - -static const char * -parse_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) -{ - return parse_suffix (strp, 'z'); -} - -/* Parse an empty suffix. Fail if the next char is ':'. */ - -static const char * -parse_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) -{ - if (**strp == ':') - return "Unexpected suffix"; - return 0; -} - -static const char * -parse_r0l_r0h (CGEN_CPU_DESC cd, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep) -{ - const char *errmsg; - signed long value; - signed long junk; - const char *newp = *strp; - - /* Parse r0[hl]. */ - errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l_r0h, & value); - if (errmsg) - return errmsg; - - if (*newp != ',') - return _("not a valid r0l/r0h pair"); - ++newp; - - /* Parse the second register in the pair. */ - if (value == 0) /* r0l */ - errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0h, & junk); - else - errmsg = cgen_parse_keyword (cd, & newp, & m32c_cgen_opval_h_r0l, & junk); - if (errmsg) - return errmsg; - - *strp = newp; - *valuep = ! value; - return 0; -} - -/* Accept .b or .w in any case. */ - -static const char * -parse_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char **strp, - int opindex ATTRIBUTE_UNUSED, signed long *valuep ATTRIBUTE_UNUSED) -{ - if (**strp == '.' - && (*(*strp + 1) == 'b' || *(*strp + 1) == 'B' - || *(*strp + 1) == 'w' || *(*strp + 1) == 'W')) - { - *strp += 2; - return NULL; - } - - return _("Invalid size specifier"); -} - -/* Special check to ensure that instruction exists for given machine. */ - -int -m32c_cgen_insn_supported (CGEN_CPU_DESC cd, - const CGEN_INSN *insn) -{ - int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); - - /* If attributes are absent, assume no restriction. */ - if (machs == 0) - machs = ~0; - - return ((machs & cd->machs) - && cgen_bitset_intersect_p (& isas, cd->isas)); -} - -/* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ - -static const char * -parse_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep, - int push) -{ - const char *errmsg = 0; - int regno = 0; - - *valuep = 0; - while (**strp && **strp != ')') - { - if (**strp == 'r' || **strp == 'R') - { - ++*strp; - regno = **strp - '0'; - if (regno > 4) - errmsg = _("Register number is not valid"); - } - else if (**strp == 'a' || **strp == 'A') - { - ++*strp; - regno = **strp - '0'; - if (regno > 2) - errmsg = _("Register number is not valid"); - regno = **strp - '0' + 4; - } - - else if (strncasecmp (*strp, "sb", 2) == 0 || strncasecmp (*strp, "SB", 2) == 0) - { - regno = 6; - ++*strp; - } - - else if (strncasecmp (*strp, "fb", 2) == 0 || strncasecmp (*strp, "FB", 2) == 0) - { - regno = 7; - ++*strp; - } - - if (push) /* Mask is reversed for push. */ - *valuep |= 0x80 >> regno; - else - *valuep |= 1 << regno; - - ++*strp; - if (**strp == ',') - { - if (*(*strp + 1) == ')') - break; - ++*strp; - } - } - - if (!*strp) - errmsg = _("Register list is not valid"); - - return errmsg; -} - -#define POP 0 -#define PUSH 1 - -static const char * -parse_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep) -{ - return parse_regset (cd, strp, opindex, valuep, POP); -} - -static const char * -parse_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - unsigned long *valuep) -{ - return parse_regset (cd, strp, opindex, valuep, PUSH); -} - -/* -- dis.c */ - -#include "elf/m32c.h" -#include "elf-bfd.h" - -/* Always print the short insn format suffix as ':<char>'. */ - -static void -print_suffix (void * dis_info, char suffix) -{ - disassemble_info *info = dis_info; - - (*info->fprintf_func) (info->stream, ":%c", suffix); -} - -static void -print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_suffix (dis_info, 's'); -} - - -static void -print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_suffix (dis_info, 'g'); -} - -static void -print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_suffix (dis_info, 'q'); -} - -static void -print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_suffix (dis_info, 'z'); -} - -/* Print the empty suffix. */ - -static void -print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - return; -} - -static void -print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = dis_info; - - if (value == 0) - (*info->fprintf_func) (info->stream, "r0h,r0l"); - else - (*info->fprintf_func) (info->stream, "r0l,r0h"); -} - -static void -print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - unsigned long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = dis_info; - - (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); -} - -static void -print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - signed long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = dis_info; - - (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); -} - -static void -print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - /* Always print the size as '.w'. */ - disassemble_info *info = dis_info; - - (*info->fprintf_func) (info->stream, ".w"); -} - -#define POP 0 -#define PUSH 1 - -static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); -static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); - -/* Print a set of registers, R0,R1,A0,A1,SB,FB. */ - -static void -print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED, - int push) -{ - static char * m16c_register_names [] = - { - "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" - }; - disassemble_info *info = dis_info; - int mask; - int reg_index = 0; - char* comma = ""; - - if (push) - mask = 0x80; - else - mask = 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); - comma = ","; - } - - for (reg_index = 1; reg_index <= 7; ++reg_index) - { - if (push) - mask >>= 1; - else - mask <<= 1; - - if (value & mask) - { - (*info->fprintf_func) (info->stream, "%s%s", comma, - m16c_register_names [reg_index]); - comma = ","; - } - } -} - -static void -print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_regset (cd, dis_info, value, attrs, pc, length, POP); -} - -static void -print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_regset (cd, dis_info, value, attrs, pc, length, PUSH); -} - -static void -print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - signed long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = dis_info; - - (*info->fprintf_func) (info->stream, "%ld", -value); -} diff --git a/binutils-2.24/cpu/m32r.cpu b/binutils-2.24/cpu/m32r.cpu deleted file mode 100644 index 003c8486..00000000 --- a/binutils-2.24/cpu/m32r.cpu +++ /dev/null @@ -1,2437 +0,0 @@ -; Renesas M32R CPU description. -*- Scheme -*- -; -; Copyright 1998, 1999, 2000, 2001, 2003, 2007, 2009 -; Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Mitsubishi -; Electric Corporation. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -; FIXME: Delete sign extension of accumulator results. -; Sign extension is done when accumulator is read. - -; define-arch must appear first - -(define-arch - (name m32r) ; name of cpu family - (comment "Renesas M32R") - (default-alignment aligned) - (insn-lsb0? #f) - (machs m32r m32rx m32r2) - (isas m32r) -) - -; Attributes. - -; An attribute to describe which pipeline an insn runs in. -; O_OS is a special attribute for sll, sra, sla, slli, srai, slai. -; These instructions have O attribute for m32rx and OS attribute for m32r2. - -(define-attr - (for insn) - (type enum) - (name PIPE) - (comment "parallel execution pipeline selection") - (values NONE O S OS O_OS) -) - -; A derived attribute that says which insns can be executed in parallel -; with others. This is a required attribute for architectures with -; parallel execution. - -(define-attr - (for insn) - (type enum) - (name PARALLEL) - (attrs META) ; do not define in any generated file for now - (values NO YES) - (default (if (eq-attr (current-insn) PIPE NONE) (symbol NO) (symbol YES))) -) - -; Instruction set parameters. - -(define-isa - (name m32r) - - ; This is 32 because 16 bit insns always appear as pairs. - ; ??? See if this can go away. It's only used by the disassembler (right?) - ; to decide how long an unknown insn is. One value isn't sufficient (e.g. if - ; on a 16 bit (and not 32 bit) boundary, will only want to advance pc by 16.) - (default-insn-bitsize 32) - - ; Number of bytes of insn we can initially fetch. - ; The M32R is tricky in that insns are either two 16-bit insns - ; (executed sequentially or in parallel) or one 32-bit insn. - ; So on one hand the base insn size is 16 bits, but on another it's 32. - ; 32 is chosen because: - ; - if the chip were ever bi-endian it is believed that the byte order would - ; be based on 32 bit quantities - ; - 32 bit insns are always aligned on 32 bit boundaries - ; - the pc will never stop on a 16 bit (and not 32 bit) boundary - ; [well actually it can, but there are no branches to such places] - (base-insn-bitsize 32) - - ; Used in computing bit numbers. - (default-insn-word-bitsize 32) - - ; The m32r fetches 2 insns at a time. - (liw-insns 2) - - ; While the m32r can execute insns in parallel, the base mach can't - ; (other than nop). The base mach is greatly handicapped by this, but - ; we still need to cleanly handle it. - (parallel-insns 2) - - ; Initial bitnumbers to decode insns by. - (decode-assist (0 1 2 3 8 9 10 11)) - - ; Classification of instructions that fit in the various frames. - ; wip, not currently used - (insn-types (long ; name - 31 ; length - (eq-attr (current-insn) LENGTH 31) ; matching insns - (0 1 2 7 8 9 10) ; decode-assist - ) - (short - 15 - (eq-attr (current-insn) LENGTH 15) ; matching insns - (0 1 2 7 8 9 10) - ) - ) - - ; Instruction framing. - ; Each m32r insn is either one 32 bit insn, two 16 bit insns executed - ; serially (left->right), or two 16 bit insns executed parallelly. - ; wip, not currently used - (frame long32 ; name - ((long)) ; list of insns in frame, plus constraint - "$0" ; assembler - (+ (1 1) (31 $0)) ; value - (sequence () (execute $0)) ; action - ) - (frame serial2x16 - ((short) - (short)) - "$0 -> $1" - (+ (1 0) (15 $0) (1 0) (15 $1)) - (sequence () - (execute $0) - (execute $1)) - ) - (frame parallel2x16 - ((short (eq-attr (current-insn) PIPE "O,BOTH")) - (short (eq-attr (current-insn) PIPE "S,BOTH"))) - "$0 || $1" - (+ (1 0) (15 $0) (1 1) (15 $1)) - (parallel () - (execute $0) - (execute $1)) - ) -) - -; Cpu family definitions. - -; ??? define-cpu-family [and in general "cpu-family"] might be clearer than -; define-cpu. -; ??? Have define-arch provide defaults for architecture that define-cpu can -; then override [reduces duplication in define-cpu]. -; ??? Another way to go is to delete cpu-families entirely and have one mach -; able to inherit things from another mach (would also need the ability to -; not only override specific inherited things but also disable some, -; e.g. if an insn wasn't supported). - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name m32rbf) - (comment "Renesas M32R base family") - (endian either) - (word-bitsize 32) - ; Override isa spec (??? keeps things simpler, though it was more true - ; in the early days and not so much now). - (parallel-insns 1) -) - -(define-cpu - (name m32rxf) - (comment "Renesas M32Rx family") - (endian either) - (word-bitsize 32) - ; Generated files have an "x" suffix. - (file-transform "x") -) - -(define-cpu - (name m32r2f) - (comment "Renesas M32R2 family") - (endian either) - (word-bitsize 32) - ; Generated files have an "2" suffix. - (file-transform "2") -) - -(define-mach - (name m32r) - (comment "Generic M32R cpu") - (cpu m32rbf) -) - -(define-mach - (name m32rx) - (comment "M32RX cpu") - (cpu m32rxf) -) - -(define-mach - (name m32r2) - (comment "M32R2 cpu") - (cpu m32r2f) -) - -; Model descriptions. - -; The meaning of this value is wip but at the moment it's intended to describe -; the implementation (i.e. what -mtune=foo does in sparc gcc). -; -; Notes while wip: -; - format of pipeline entry: -; (pipeline name (stage1-name ...) (stage2-name ...) ...) -; The contents of a stage description is wip. -; - each mach must have at least one model -; - the default model must be the first one -;- maybe have `retire' support update total cycle count to handle current -; parallel insn cycle counting problems - -(define-model - (name m32r/d) (comment "m32r/d") (attrs) - (mach m32r) - - ;(prefetch) - ;(retire) - - (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback))) - (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) - - ; `state' is a list of variables for recording model state - (state - ; bit mask of h-gr registers, =1 means value being loaded from memory - (h-gr UINT) - ) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - ((sr INT -1) (dr INT -1)) ; inputs - ((dr INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-cmp "Compare Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-mac "Multiply/Accumulate Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-cti "Branch Unit" () - 1 1 ; issue done - () ; state - ((sr INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - (unit u-load "Memory Load Unit" () - 1 1 ; issue done - () ; state - ((sr INT) - ;(ld-mem AI) - ) ; inputs - ((dr INT)) ; outputs - () ; profile action (default) - ) - (unit u-store "Memory Store Unit" () - 1 1 ; issue done - () ; state - ((src1 INT) (src2 INT)) ; inputs - () ; ((st-mem AI)) ; outputs - () ; profile action (default) - ) -) - -(define-model - (name test) (comment "test") (attrs) - (mach m32r) - (pipeline all "" () ((fetch) (decode) (execute) (writeback))) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () () () ()) -) - -; Each mach must have at least one model. - -(define-model - (name m32rx) (comment "m32rx") (attrs) - (mach m32rx) - - ; ??? It's 6 stages but I forget the details right now. - (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) - (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) - (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - ((sr INT -1) (dr INT -1)) ; inputs - ((dr INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-cmp "Compare Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-mac "Multiply/Accumulate Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-cti "Branch Unit" () - 1 1 ; issue done - () ; state - ((sr INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - (unit u-load "Memory Load Unit" () - 1 1 ; issue done - () ; state - ((sr INT)) ; inputs - ((dr INT)) ; outputs - () ; profile action (default) - ) - (unit u-store "Memory Store Unit" () - 1 1 ; issue done - () ; state - ((src1 INT) (src2 INT)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -(define-model - (name m32r2) (comment "m32r2") (attrs) - (mach m32r2) - - ; ??? It's 6 stages but I forget the details right now. - (pipeline p-o "" () ((fetch) (decode) (execute) (writeback))) - (pipeline p-s "" () ((fetch) (decode) (execute) (writeback))) - (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback))) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - ((sr INT -1) (dr INT -1)) ; inputs - ((dr INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-cmp "Compare Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-mac "Multiply/Accumulate Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-cti "Branch Unit" () - 1 1 ; issue done - () ; state - ((sr INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - (unit u-load "Memory Load Unit" () - 1 1 ; issue done - () ; state - ((sr INT)) ; inputs - ((dr INT)) ; outputs - () ; profile action (default) - ) - (unit u-store "Memory Store Unit" () - 1 1 ; issue done - () ; state - ((src1 INT) (src2 INT)) ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; The instruction fetch/execute cycle. -; This is split into two parts as sometimes more than one instruction is -; decoded at once. -; The `const SI' argument to decode/execute is used to distinguish -; multiple instructions processed at the same time (e.g. m32r). -; -; ??? This is wip, and not currently used. -; ??? Needs to be moved to define-isa. - -; This is how to fetch and decode an instruction. - -;(define-extract -; (sequence VOID -; (if VOID (ne AI (and AI pc (const AI 3)) (const AI 0)) -; (sequence VOID -; (set-quiet USI (scratch UHI insn1) (ifetch UHI pc)) -; (decode VOID pc (and UHI insn1 (const UHI #x7fff)) -; (const SI 0))) -; (sequence VOID -; (set-quiet USI (scratch USI insn) (ifetch USI pc)) -; (if VOID (ne USI (and USI insn (const USI #x80000000)) -; (const USI 0)) -; (decode VOID pc (srl USI insn (const WI 16)) (const SI 0)) -; (sequence VOID -; ; ??? parallel support -; (decode VOID pc (srl USI insn (const WI 16)) -; (const SI 0)) -; (decode VOID (add AI pc (const AI 2)) -; (and USI insn (const WI #x7fff)) -; (const SI 1)))))) -; ) -;) - -; This is how to execute a decoded instruction. - -;(define-execute -; (sequence VOID () ; () is empty option list -; ((AI new_pc)) -; (set AI new_pc (execute: AI (const 0)) #:quiet) -; (set AI pc new_pc #:direct) -; ) -;) - -; FIXME: It might simplify things to separate the execute process from the -; one that updates the PC. - -; Instruction fields. -; -; Attributes: -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 -; RELOC: there is a relocation associated with this field (experiment) - -(define-attr - (for ifield operand) - (type boolean) - (name RELOC) - (comment "there is a reloc associated with this field (experiment)") -) - -(dnf f-op1 "op1" () 0 4) -(dnf f-op2 "op2" () 8 4) -(dnf f-cond "cond" () 4 4) -(dnf f-r1 "r1" () 4 4) -(dnf f-r2 "r2" () 12 4) -(df f-simm8 "simm8" () 8 8 INT #f #f) -(df f-simm16 "simm16" () 16 16 INT #f #f) -(dnf f-shift-op2 "shift op2" () 8 3) -(dnf f-uimm3 "uimm3" () 5 3) -(dnf f-uimm4 "uimm4" () 12 4) -(dnf f-uimm5 "uimm5" () 11 5) -(dnf f-uimm8 "uimm8" () 8 8) -(dnf f-uimm16 "uimm16" () 16 16) -(dnf f-uimm24 "uimm24" (ABS-ADDR RELOC) 8 24) -(dnf f-hi16 "high 16 bits" (SIGN-OPT) 16 16) -(df f-disp8 "disp8, slot unknown" (PCREL-ADDR RELOC) 8 8 INT - ((value pc) (sra WI (sub WI value (and WI pc (const -4))) (const 2))) - ((value pc) (add WI (sll WI value (const 2)) (and WI pc (const -4))))) -(df f-disp16 "disp16" (PCREL-ADDR RELOC) 16 16 INT - ((value pc) (sra WI (sub WI value pc) (const 2))) - ((value pc) (add WI (sll WI value (const 2)) pc))) -(df f-disp24 "disp24" (PCREL-ADDR RELOC) 8 24 INT - ((value pc) (sra WI (sub WI value pc) (const 2))) - ((value pc) (add WI (sll WI value (const 2)) pc))) - -(dnf f-op23 "op2.3" () 9 3) -(dnf f-op3 "op3" () 14 2) -(dnf f-acc "acc" () 8 1) -(dnf f-accs "accs" () 12 2) -(dnf f-accd "accd" () 4 2) -(dnf f-bits67 "bits67" () 6 2) -(dnf f-bit4 "bit4" () 4 1) -(dnf f-bit14 "bit14" () 14 1) - -(define-ifield (name f-imm1) (comment "1 bit immediate, 0->1 1->2") - (attrs) - (start 15) (length 1) - (encode (value pc) (sub WI value (const WI 1))) - (decode (value pc) (add WI value (const WI 1))) -) - -; Enums. - -; insn-op1: bits 0-3 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "10" "11" "12" "13" "14" "15") -) - -; insn-op2: bits 8-11 -; FIXME: should use die macro or some such -(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "10" "11" "12" "13" "14" "15") -) - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. - -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -(dnh h-hi16 "high 16 bits" () - (immediate (UINT 16)) - () () () -) - -; These two aren't technically needed. -; They're here for illustration sake mostly. -; Plus they cause the value to be stored in the extraction buffers to only -; be 16 bits wide (vs 32 or 64). Whoopie ding. But it's fun. -(dnh h-slo16 "signed low 16 bits" () - (immediate (INT 16)) - () () () -) -(dnh h-ulo16 "unsigned low 16 bits" () - (immediate (UINT 16)) - () () () -) - -(define-keyword - (name gr-names) - (print-name h-gr) - (prefix "") - (values (fp 13) (lr 14) (sp 15) - (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)) -) - -(define-hardware - (name h-gr) - (comment "general registers") - (attrs PROFILE CACHE-ADDR) - (type register WI (16)) - (indices extern-keyword gr-names) -) - -(define-keyword - (name cr-names) - (print-name h-cr) - (prefix "") - (values (psw 0) (cbr 1) (spi 2) (spu 3) - (bpc 6) (bbpsw 8) (bbpc 14) (evb 5) - (cr0 0) (cr1 1) (cr2 2) (cr3 3) - (cr4 4) (cr5 5) (cr6 6) (cr7 7) - (cr8 8) (cr9 9) (cr10 10) (cr11 11) - (cr12 12) (cr13 13) (cr14 14) (cr15 15)) -) - -(define-hardware - (name h-cr) - (comment "control registers") - (type register UWI (16)) - (indices extern-keyword cr-names) - (get (index) (c-call UWI "@cpu@_h_cr_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_cr_set_handler" index newval)) -) - -; The actual accumulator is only 56 bits. -; The top 8 bits are sign extended from bit 8 (when counting msb = bit 0). -; To simplify the accumulator instructions, no attempt is made to keep the -; top 8 bits properly sign extended (currently there's no point since they -; all ignore them). When the value is read it is properly sign extended -; [in the `get' handler]. -(define-hardware - (name h-accum) - (comment "accumulator") - (type register DI) - (get () (c-call DI "@cpu@_h_accum_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_accum_set_handler" newval)) -) - -; FIXME: Revisit after sanitization can be removed. Remove h-accum. -(define-hardware - (name h-accums) - (comment "accumulators") - (attrs (MACH m32rx,m32r2)) - (type register DI (2)) - (indices keyword "" ((a0 0) (a1 1))) - ; get/set so a0 accesses are redirected to h-accum. - ; They're also so reads can properly sign extend the value. - ; FIXME: Needn't be a function call. - (get (index) (c-call DI "@cpu@_h_accums_get_handler" index)) - (set (index newval) (c-call VOID "@cpu@_h_accums_set_handler" index newval)) -) - -; For condbit operand. FIXME: Need to allow spec of get/set of operands. -; Having this separate from h-psw keeps the parts that use it simpler -; [since they greatly outnumber those that use h-psw]. -(dsh h-cond "condition bit" () (register BI)) - -; The actual values of psw,bpsw,bbpsw are recorded here to allow access -; to them as a unit. -(define-hardware - (name h-psw) - (comment "psw part of psw") - (type register UQI) - ; get/set to handle cond bit. - ; FIXME: missing: use's and clobber's - ; FIXME: remove c-call? - (get () (c-call UQI "@cpu@_h_psw_get_handler")) - (set (newval) (c-call VOID "@cpu@_h_psw_set_handler" newval)) -) -(dsh h-bpsw "backup psw" () (register UQI)) -(dsh h-bbpsw "backup bpsw" () (register UQI)) - -; FIXME: Later make add get/set specs and support SMP. -(dsh h-lock "lock" () (register BI)) - -; Instruction Operands. -; These entries provide a layer between the assembler and the raw hardware -; description, and are used to refer to hardware elements in the semantic -; code. Usually there's a bit of over-specification, but in more complicated -; instruction sets there isn't. - -;; Print some operands take a hash prefix. -;; ??? Why don't we also handle one when parsing? - -(define-pmacro (duhpo x-name x-comment x-attrs x-type x-index) - (define-operand (name x-name) (comment x-comment) - (.splice attrs (.unsplice x-attrs)) - (type x-type) (index x-index) - (handlers (print "unsigned_with_hash_prefix"))) -) - -(define-pmacro (dshpo x-name x-comment x-attrs x-type x-index) - (define-operand (name x-name) (comment x-comment) - (.splice attrs (.unsplice x-attrs)) - (type x-type) (index x-index) - (handlers (print "signed_with_hash_prefix"))) -) - -; ??? Convention says this should be o-sr, but then the insn definitions -; should refer to o-sr which is clumsy. The "o-" could be implicit, but -; then it should be implicit for all the symbols here, but then there would -; be confusion between (f-)simm8 and (h-)simm8. -; So for now the rule is exactly as it appears here. - -(dnop sr "source register" () h-gr f-r2) -(dnop dr "destination register" () h-gr f-r1) -;; The assembler relies upon the fact that dr and src1 are the same field. -;; FIXME: Revisit. -(dnop src1 "source register 1" () h-gr f-r1) -(dnop src2 "source register 2" () h-gr f-r2) -(dnop scr "source control register" () h-cr f-r2) -(dnop dcr "destination control register" () h-cr f-r1) - -(dshpo simm8 "8 bit signed immediate" () h-sint f-simm8) -(dshpo simm16 "16 bit signed immediate" () h-sint f-simm16) -(duhpo uimm3 "3 bit unsigned number" () h-uint f-uimm3) -(duhpo uimm4 "4 bit trap number" () h-uint f-uimm4) -(duhpo uimm5 "5 bit shift count" () h-uint f-uimm5) -(duhpo uimm8 "8 bit unsigned immediate" () h-uint f-uimm8) -(duhpo uimm16 "16 bit unsigned immediate" () h-uint f-uimm16) - -(duhpo imm1 "1 bit immediate" ((MACH m32rx,m32r2)) h-uint f-imm1) - -(dnop accd "accumulator destination register" ((MACH m32rx,m32r2)) h-accums f-accd) -(dnop accs "accumulator source register" ((MACH m32rx,m32r2)) h-accums f-accs) -(dnop acc "accumulator reg (d)" ((MACH m32rx,m32r2)) h-accums f-acc) - -; slo16,ulo16 are used in both with-hash-prefix/no-hash-prefix cases. -; e.g. add3 r3,r3,#1 and ld r3,@(4,r4). We could use special handlers on -; the operands themselves. -; Instead we create a fake operand `hash'. The m32r is an illustration port, -; so we often try out various ways of doing things. - -(define-operand (name hash) (comment "# prefix") (attrs) - (type h-sint) ; doesn't really matter - (index f-nil) - (handlers (parse "hash") (print "hash")) -) - -; For high(foo),shigh(foo). -(define-operand - (name hi16) - (comment "high 16 bit immediate, sign optional") - (attrs) - (type h-hi16) - (index f-hi16) - (handlers (parse "hi16")) -) - -; For low(foo),sda(foo). -(define-operand - (name slo16) - (comment "16 bit signed immediate, for low()") - (attrs) - (type h-slo16) - (index f-simm16) - (handlers (parse "slo16")) -) - -; For low(foo). -(define-operand - (name ulo16) - (comment "16 bit unsigned immediate, for low()") - (attrs) - (type h-ulo16) - (index f-uimm16) - (handlers (parse "ulo16")) -) - -(dnop uimm24 "24 bit address" () h-addr f-uimm24) - -(define-operand - (name disp8) - (comment "8 bit displacement") - (attrs RELAX) - (type h-iaddr) - (index f-disp8) - ; ??? Early experiments had insert/extract fields here. - ; Moving these to f-disp8 made things cleaner, but may wish to re-introduce - ; fields here to handle more complicated cases. -) - -(dnop disp16 "16 bit displacement" () h-iaddr f-disp16) -(dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24) - -; These hardware elements are refered to frequently. - -(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) -(dnop accum "accumulator" (SEM-ONLY) h-accum f-nil) - -; Instruction definitions. -; -; Notes while wip: -; - dni is a cover macro to the real "this is an instruction" keyword. -; The syntax of the real one is yet to be determined. -; At the lowest level (i.e. the "real" one) it will probably take a variable -; list of arguments where each argument [perhaps after the standard three of -; name, comment, attrs] is "(keyword arg-to-keyword)". This syntax is simple -; and yet completely upward extensible. And given the macro facility, one -; needn't code at that low a level so even though it'll be more verbose than -; necessary it won't matter. This same reasoning can be applied to most -; types of entries in this file. - -; M32R specific instruction attributes: - -; FILL-SLOT: Need next insn to begin on 32 bit boundary. -; (A "slot" as used here is a 32 bit quantity that can either be filled with -; one 32 bit insn or two 16 bit insns which go in the "left bin" and "right -; bin" where the left bin is the one with a lower address). - -(define-attr - (for insn) - (type boolean) - (name FILL-SLOT) - (comment "fill right bin with `nop' if insn is in left bin") -) - -(define-attr - (for insn) - (type boolean) - (name SPECIAL) - (comment "non-public m32rx insn") -) - -(define-attr - (for insn) - (type boolean) - (name SPECIAL_M32R) - (comment "non-public m32r insn") -) - -(define-attr - (for insn) - (type boolean) - (name SPECIAL_FLOAT) - (comment "floating point insn") -) - -; IDOC attribute for instruction documentation. - -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MEM - () "Memory") - (ALU - () "ALU") - (BR - () "Branch") - (ACCUM - () "Accumulator") - (MAC - () "Multiply/Accumulate") - (MISC - () "Miscellaneous") - ) -) - -(define-pmacro (bin-op mnemonic op2-op sem-op imm-prefix imm) - (begin - (dni mnemonic - (.str mnemonic " reg/reg") - ((PIPE OS) (IDOC ALU)) - (.str mnemonic " $dr,$sr") - (+ OP1_0 op2-op dr sr) - (set dr (sem-op dr sr)) - () - ) - (dni (.sym mnemonic "3") - (.str mnemonic " reg/" imm) - ((IDOC ALU)) - (.str mnemonic "3 $dr,$sr," imm-prefix "$" imm) - (+ OP1_8 op2-op dr sr imm) - (set dr (sem-op sr imm)) - () - ) - ) -) -(bin-op add OP2_10 add "$hash" slo16) -; sub isn't present because sub3 doesn't exist. -(bin-op and OP2_12 and "" uimm16) -(bin-op or OP2_14 or "$hash" ulo16) -(bin-op xor OP2_13 xor "" uimm16) - -(dni addi "addi" - ((PIPE OS) (IDOC ALU)) - ;#.(string-append "addi " "$dr,$simm8") ; #. experiment - "addi $dr,$simm8" - (+ OP1_4 dr simm8) - (set dr (add dr simm8)) - ((m32r/d (unit u-exec)) - (m32rx (unit u-exec)) - (m32r2 (unit u-exec))) -) - -(dni addv "addv" - ((PIPE OS) (IDOC ALU)) - "addv $dr,$sr" - (+ OP1_0 OP2_8 dr sr) - (parallel () - (set dr (add dr sr)) - (set condbit (add-oflag dr sr (const 0)))) - () -) - -(dni addv3 "addv3" - ((IDOC ALU)) - "addv3 $dr,$sr,$simm16" - (+ OP1_8 OP2_8 dr sr simm16) - (parallel () - (set dr (add sr simm16)) - (set condbit (add-oflag sr simm16 (const 0)))) - () -) - -(dni addx "addx" - ((PIPE OS) (IDOC ALU)) - "addx $dr,$sr" - (+ OP1_0 OP2_9 dr sr) - (parallel () - (set dr (addc dr sr condbit)) - (set condbit (add-cflag dr sr condbit))) - () -) - -(dni bc8 "bc with 8 bit displacement" - (COND-CTI (PIPE O) (IDOC BR)) - "bc.s $disp8" - (+ OP1_7 (f-r1 12) disp8) - (if condbit (set pc disp8)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bc8r "relaxable bc8" - (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) - "bc $disp8" - (emit bc8 disp8) -) - -(dni bc24 "bc with 24 bit displacement" - (COND-CTI (IDOC BR)) - "bc.l $disp24" - (+ OP1_15 (f-r1 12) disp24) - (if condbit (set pc disp24)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bc24r "relaxable bc24" - (COND-CTI RELAXED (IDOC BR)) - "bc $disp24" - (emit bc24 disp24) -) - -(dni beq "beq" - (COND-CTI (IDOC BR)) - "beq $src1,$src2,$disp16" - (+ OP1_11 OP2_0 src1 src2 disp16) - (if (eq src1 src2) (set pc disp16)) - ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) - (m32rx (unit u-cti) (unit u-cmp (cycles 0))) - (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) -) - -(define-pmacro (cbranch sym comment op2-op comp-op) - (dni sym comment (COND-CTI (IDOC BR)) - (.str sym " $src2,$disp16") - (+ OP1_11 op2-op (f-r1 0) src2 disp16) - (if (comp-op src2 (const WI 0)) (set pc disp16)) - ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) - (m32rx (unit u-cti) (unit u-cmp (cycles 0))) - (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) - ) -) -(cbranch beqz "beqz" OP2_8 eq) -(cbranch bgez "bgez" OP2_11 ge) -(cbranch bgtz "bgtz" OP2_13 gt) -(cbranch blez "blez" OP2_12 le) -(cbranch bltz "bltz" OP2_10 lt) -(cbranch bnez "bnez" OP2_9 ne) - -(dni bl8 "bl with 8 bit displacement" - (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) - "bl.s $disp8" - (+ OP1_7 (f-r1 14) disp8) - (sequence () - (set (reg h-gr 14) - (add (and pc (const -4)) (const 4))) - (set pc disp8)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bl8r "relaxable bl8" - (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) - "bl $disp8" - (emit bl8 disp8) -) - -(dni bl24 "bl with 24 bit displacement" - (UNCOND-CTI (IDOC BR)) - "bl.l $disp24" - (+ OP1_15 (f-r1 14) disp24) - (sequence () - (set (reg h-gr 14) (add pc (const 4))) - (set pc disp24)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bl24r "relaxable bl24" - (UNCOND-CTI RELAXED (IDOC BR)) - "bl $disp24" - (emit bl24 disp24) -) - -(dni bcl8 "bcl with 8 bit displacement" - (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) - "bcl.s $disp8" - (+ OP1_7 (f-r1 8) disp8) - (if condbit - (sequence () - (set (reg h-gr 14) - (add (and pc (const -4)) - (const 4))) - (set pc disp8))) - ((m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bcl8r "relaxable bcl8" - (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) - "bcl $disp8" - (emit bcl8 disp8) -) - -(dni bcl24 "bcl with 24 bit displacement" - (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) - "bcl.l $disp24" - (+ OP1_15 (f-r1 8) disp24) - (if condbit - (sequence () - (set (reg h-gr 14) (add pc (const 4))) - (set pc disp24))) - ((m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bcl24r "relaxable bcl24" - (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) - "bcl $disp24" - (emit bcl24 disp24) -) - -(dni bnc8 "bnc with 8 bit displacement" - (COND-CTI (PIPE O) (IDOC BR)) - "bnc.s $disp8" - (+ OP1_7 (f-r1 13) disp8) - (if (not condbit) (set pc disp8)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bnc8r "relaxable bnc8" - (COND-CTI RELAXABLE (PIPE O) (IDOC BR)) - "bnc $disp8" - (emit bnc8 disp8) -) - -(dni bnc24 "bnc with 24 bit displacement" - (COND-CTI (IDOC BR)) - "bnc.l $disp24" - (+ OP1_15 (f-r1 13) disp24) - (if (not condbit) (set pc disp24)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bnc24r "relaxable bnc24" - (COND-CTI RELAXED (IDOC BR)) - "bnc $disp24" - (emit bnc24 disp24) -) - -(dni bne "bne" - (COND-CTI (IDOC BR)) - "bne $src1,$src2,$disp16" - (+ OP1_11 OP2_1 src1 src2 disp16) - (if (ne src1 src2) (set pc disp16)) - ((m32r/d (unit u-cti) (unit u-cmp (cycles 0))) - (m32rx (unit u-cti) (unit u-cmp (cycles 0))) - (m32r2 (unit u-cti) (unit u-cmp (cycles 0)))) -) - -(dni bra8 "bra with 8 bit displacement" - (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) - "bra.s $disp8" - (+ OP1_7 (f-r1 15) disp8) - (set pc disp8) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bra8r "relaxable bra8" - (UNCOND-CTI FILL-SLOT RELAXABLE (PIPE O) (IDOC BR)) - "bra $disp8" - (emit bra8 disp8) -) - -(dni bra24 "bra with 24 displacement" - (UNCOND-CTI (IDOC BR)) - "bra.l $disp24" - (+ OP1_15 (f-r1 15) disp24) - (set pc disp24) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bra24r "relaxable bra24" - (UNCOND-CTI RELAXED (IDOC BR)) - "bra $disp24" - (emit bra24 disp24) -) - -(dni bncl8 "bncl with 8 bit displacement" - (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) (IDOC BR)) - "bncl.s $disp8" - (+ OP1_7 (f-r1 9) disp8) - (if (not condbit) - (sequence () - (set (reg h-gr 14) - (add (and pc (const -4)) - (const 4))) - (set pc disp8))) - ((m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bncl8r "relaxable bncl8" - (COND-CTI FILL-SLOT (MACH m32rx,m32r2) (PIPE O) RELAXABLE (IDOC BR)) - "bncl $disp8" - (emit bncl8 disp8) -) - -(dni bncl24 "bncl with 24 bit displacement" - (COND-CTI (MACH m32rx,m32r2) (IDOC BR)) - "bncl.l $disp24" - (+ OP1_15 (f-r1 9) disp24) - (if (not condbit) - (sequence () - (set (reg h-gr 14) (add pc (const 4))) - (set pc disp24))) - ((m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dnmi bncl24r "relaxable bncl24" - (COND-CTI (MACH m32rx,m32r2) RELAXED (IDOC BR)) - "bncl $disp24" - (emit bncl24 disp24) -) - -(dni cmp "cmp" - ((PIPE OS) (IDOC ALU)) - "cmp $src1,$src2" - (+ OP1_0 OP2_4 src1 src2) - (set condbit (lt src1 src2)) - ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -(dni cmpi "cmpi" - ((IDOC ALU)) - "cmpi $src2,$simm16" - (+ OP1_8 (f-r1 0) OP2_4 src2 simm16) - (set condbit (lt src2 simm16)) - ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -(dni cmpu "cmpu" - ((PIPE OS) (IDOC ALU)) - "cmpu $src1,$src2" - (+ OP1_0 OP2_5 src1 src2) - (set condbit (ltu src1 src2)) - ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -(dni cmpui "cmpui" - ((IDOC ALU)) - "cmpui $src2,$simm16" - (+ OP1_8 (f-r1 0) OP2_5 src2 simm16) - (set condbit (ltu src2 simm16)) - ((m32r/d (unit u-cmp)) - (m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -(dni cmpeq "cmpeq" - ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) - "cmpeq $src1,$src2" - (+ OP1_0 OP2_6 src1 src2) - (set condbit (eq src1 src2)) - ((m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -(dni cmpz "cmpz" - ((MACH m32rx,m32r2) (PIPE OS) (IDOC ALU)) - "cmpz $src2" - (+ OP1_0 OP2_7 (f-r1 0) src2) - (set condbit (eq src2 (const 0))) - ((m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -(dni div "div" - ((IDOC ALU)) - "div $dr,$sr" - (+ OP1_9 OP2_0 dr sr (f-simm16 0)) - (if (ne sr (const 0)) (set dr (div dr sr))) - ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37))) - (m32r2 (unit u-exec (cycles 37)))) -) - -(dni divu "divu" - ((IDOC ALU)) - "divu $dr,$sr" - (+ OP1_9 OP2_1 dr sr (f-simm16 0)) - (if (ne sr (const 0)) (set dr (udiv dr sr))) - ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37))) - (m32r2 (unit u-exec (cycles 37)))) -) - -(dni rem "rem" - ((IDOC ALU)) - "rem $dr,$sr" - (+ OP1_9 OP2_2 dr sr (f-simm16 0)) - ; FIXME: Check rounding direction. - (if (ne sr (const 0)) (set dr (mod dr sr))) - ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37))) - (m32r2 (unit u-exec (cycles 37)))) -) - -(dni remu "remu" - ((IDOC ALU)) - "remu $dr,$sr" - (+ OP1_9 OP2_3 dr sr (f-simm16 0)) - ; FIXME: Check rounding direction. - (if (ne sr (const 0)) (set dr (umod dr sr))) - ((m32r/d (unit u-exec (cycles 37))) - (m32rx (unit u-exec (cycles 37))) - (m32r2 (unit u-exec (cycles 37)))) -) - -(dni remh "remh" - ((MACH m32r2)) - "remh $dr,$sr" - (+ OP1_9 OP2_2 dr sr (f-simm16 #x10)) - ; FIXME: Check rounding direction. - (if (ne sr (const 0)) (set dr (mod (ext WI (trunc HI dr)) sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni remuh "remuh" - ((MACH m32r2)) - "remuh $dr,$sr" - (+ OP1_9 OP2_3 dr sr (f-simm16 #x10)) - ; FIXME: Check rounding direction. - (if (ne sr (const 0)) (set dr (umod dr sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni remb "remb" - ((MACH m32r2)) - "remb $dr,$sr" - (+ OP1_9 OP2_2 dr sr (f-simm16 #x18)) - ; FIXME: Check rounding direction. - (if (ne sr (const 0)) (set dr (mod (ext WI (trunc BI dr)) sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni remub "remub" - ((MACH m32r2)) - "remub $dr,$sr" - (+ OP1_9 OP2_3 dr sr (f-simm16 #x18)) - ; FIXME: Check rounding direction. - (if (ne sr (const 0)) (set dr (umod dr sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni divuh "divuh" - ((MACH m32r2)) - "divuh $dr,$sr" - (+ OP1_9 OP2_1 dr sr (f-simm16 #x10)) - (if (ne sr (const 0)) (set dr (udiv dr sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni divb "divb" - ((MACH m32r2)) - "divb $dr,$sr" - (+ OP1_9 OP2_0 dr sr (f-simm16 #x18)) - (if (ne sr (const 0)) (set dr (div (ext WI (trunc BI dr)) sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni divub "divub" - ((MACH m32r2)) - "divub $dr,$sr" - (+ OP1_9 OP2_1 dr sr (f-simm16 #x18)) - (if (ne sr (const 0)) (set dr (udiv dr sr))) - ((m32r2 (unit u-exec (cycles 21)))) -) - -(dni divh "divh" - ((MACH m32rx,m32r2) (IDOC ALU)) - "divh $dr,$sr" - (+ OP1_9 OP2_0 dr sr (f-simm16 #x10)) - (if (ne sr (const 0)) (set dr (div (ext WI (trunc HI dr)) sr))) - ((m32rx (unit u-exec (cycles 21))) - (m32r2 (unit u-exec (cycles 21)))) -) - -(dni jc "jc" - (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) - "jc $sr" - (+ OP1_1 (f-r1 12) OP2_12 sr) - (if condbit (set pc (and sr (const -4)))) - ((m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dni jnc "jnc" - (COND-CTI (MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) - "jnc $sr" - (+ OP1_1 (f-r1 13) OP2_12 sr) - (if (not condbit) (set pc (and sr (const -4)))) - ((m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dni jl "jl" - (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC BR)) - "jl $sr" - (+ OP1_1 (f-r1 14) OP2_12 sr) - (parallel () - (set (reg h-gr 14) - (add (and pc (const -4)) (const 4))) - (set pc (and sr (const -4)))) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(dni jmp "jmp" - (UNCOND-CTI (PIPE O) (IDOC BR)) - "jmp $sr" - (+ OP1_1 (f-r1 15) OP2_12 sr) - (set pc (and sr (const -4))) - ; The above works now so this kludge has been commented out. - ; It's kept around because the f-r1 reference in the semantic part - ; should work. - ; FIXME: kludge, instruction decoding not finished. - ; But this should work, so that's another FIXME. - ;(sequence VOID (if VOID (eq SI f-r1 (const SI 14)) - ; FIXME: abuf->insn should be a macro of some sort. - ;(sequence VOID - ; (if VOID (eq SI (c-code SI "((abuf->insn >> 8) & 15)") - ; (const SI 14)) - ; (set WI (reg WI h-gr 14) - ; (add WI (and WI pc (const WI -4)) (const WI 4)))) - ; (set WI pc sr)) - ((m32r/d (unit u-cti)) - (m32rx (unit u-cti)) - (m32r2 (unit u-cti))) -) - -(define-pmacro (no-ext-expr mode expr) expr) -(define-pmacro (ext-expr mode expr) (ext mode expr)) -(define-pmacro (zext-expr mode expr) (zext mode expr)) - -(define-pmacro (load-op suffix op2-op mode ext-op) - (begin - (dni (.sym ld suffix) (.str "ld" suffix) - ((PIPE O) (IDOC MEM)) - (.str "ld" suffix " $dr,@$sr") - (+ OP1_2 op2-op dr sr) - (set dr (ext-op WI (mem mode sr))) - ((m32r/d (unit u-load)) - (m32rx (unit u-load)) - (m32r2 (unit u-load))) - ) - (dnmi (.sym ld suffix "-2") (.str "ld" suffix "-2") - (NO-DIS (PIPE O) (IDOC MEM)) - (.str "ld" suffix " $dr,@($sr)") - (emit (.sym ld suffix) dr sr)) - (dni (.sym ld suffix -d) (.str "ld" suffix "-d") - ((IDOC MEM)) - (.str "ld" suffix " $dr,@($slo16,$sr)") - (+ OP1_10 op2-op dr sr slo16) - (set dr (ext-op WI (mem mode (add sr slo16)))) - ((m32r/d (unit u-load (cycles 2))) - (m32rx (unit u-load (cycles 2))) - (m32r2 (unit u-load (cycles 2)))) - ) - (dnmi (.sym ld suffix -d2) (.str "ld" suffix "-d2") - (NO-DIS (IDOC MEM)) - (.str "ld" suffix " $dr,@($sr,$slo16)") - (emit (.sym ld suffix -d) dr sr slo16)) - ) -) -(load-op "" OP2_12 WI no-ext-expr) -(load-op b OP2_8 QI ext-expr) -(load-op h OP2_10 HI ext-expr) -(load-op ub OP2_9 QI zext-expr) -(load-op uh OP2_11 HI zext-expr) - -(dni ld-plus "ld+" - ((PIPE O) (IDOC MEM)) - "ld $dr,@$sr+" - (+ OP1_2 dr OP2_14 sr) - (parallel () - ; wip: memory addresses in profiling support - ;(set dr (name ld-mem (mem WI sr))) - (set dr (mem WI sr)) - (set sr (add sr (const 4)))) - ; Note: `pred' is the constraint. Also useful here is (ref name) - ; and returns true if operand <name> was referenced - ; (where "referenced" means _read_ if input operand and _written_ if - ; output operand). - ; args to unit are "unit-name (name1 value1) ..." - ; - cycles(done),issue,pred are also specified this way - ; - if unspecified, default is used - ; - for ins/outs, extra arg is passed that says what was specified - ; - this is AND'd with `written' for outs - ((m32r/d (unit u-load (pred (const 1))) - (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) - (m32rx (unit u-load) - (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) - (m32r2 (unit u-load) - (unit u-exec (in sr #f) (in dr sr) (out dr sr) (cycles 0) (pred (const 1)))) - ) -) - -(dnmi pop "pop" - ((PIPE O) (IDOC MEM)) - "pop $dr" - (emit ld-plus dr (sr 15)) ; "ld %0,@sp+" -) - -(dni ld24 "ld24" - ((IDOC MEM)) - "ld24 $dr,$uimm24" - (+ OP1_14 dr uimm24) - (set dr uimm24) - () -) - -; ldi8 appears before ldi16 so we try the shorter version first - -(dni ldi8 "ldi8" - ((PIPE OS) (IDOC ALU)) - "ldi8 $dr,$simm8" - (+ OP1_6 dr simm8) - (set dr simm8) - () -) - -(dnmi ldi8a "ldi8 alias" - ((PIPE OS) (IDOC ALU)) - "ldi $dr,$simm8" - (emit ldi8 dr simm8) -) - -(dni ldi16 "ldi16" - ((IDOC ALU)) - "ldi16 $dr,$hash$slo16" - (+ OP1_9 OP2_15 (f-r2 0) dr slo16) - (set dr slo16) - () -) - -(dnmi ldi16a "ldi16 alias" - ((IDOC ALU)) - "ldi $dr,$hash$slo16" - (emit ldi16 dr slo16) -) - -(dni lock "lock" - ((PIPE O) (IDOC MISC)) - "lock $dr,@$sr" - (+ OP1_2 OP2_13 dr sr) - (sequence () - (set (reg h-lock) (const BI 1)) - (set dr (mem WI sr))) - ((m32r/d (unit u-load)) - (m32rx (unit u-load)) - (m32r2 (unit u-load))) -) - -(dni machi "machi" - ( - ; (MACH m32r) is a temporary hack. This insn collides with machi-a - ; in the simulator so disable it for m32rx. - (MACH m32r) (PIPE S) (IDOC MAC) - ) - "machi $src1,$src2" - (+ OP1_3 OP2_4 src1 src2) - ; FIXME: TRACE_RESULT will print the wrong thing since we - ; alter one of the arguments. - (set accum - (sra DI - (sll DI - (add DI - accum - (mul DI - (ext DI (and WI src1 (const #xffff0000))) - (ext DI (trunc HI (sra WI src2 (const 16)))))) - (const 8)) - (const 8))) - ((m32r/d (unit u-mac))) -) - -(dni machi-a "machi-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "machi $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 4) src2) - (set acc - (sra DI - (sll DI - (add DI - acc - (mul DI - (ext DI (and WI src1 (const #xffff0000))) - (ext DI (trunc HI (sra WI src2 (const 16)))))) - (const 8)) - (const 8))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni maclo "maclo" - ((MACH m32r) (PIPE S) (IDOC MAC)) - "maclo $src1,$src2" - (+ OP1_3 OP2_5 src1 src2) - (set accum - (sra DI - (sll DI - (add DI - accum - (mul DI - (ext DI (sll WI src1 (const 16))) - (ext DI (trunc HI src2)))) - (const 8)) - (const 8))) - ((m32r/d (unit u-mac))) -) - -(dni maclo-a "maclo-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "maclo $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 5) src2) - (set acc - (sra DI - (sll DI - (add DI - acc - (mul DI - (ext DI (sll WI src1 (const 16))) - (ext DI (trunc HI src2)))) - (const 8)) - (const 8))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni macwhi "macwhi" - ((MACH m32r) (PIPE S) (IDOC MAC)) - "macwhi $src1,$src2" - (+ OP1_3 OP2_6 src1 src2) - (set accum - (sra DI - (sll DI - (add DI - accum - (mul DI - (ext DI src1) - (ext DI (trunc HI (sra WI src2 (const 16)))))) - (const 8)) - (const 8))) - ((m32r/d (unit u-mac))) -) - -(dni macwhi-a "macwhi-a" - ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) - "macwhi $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 6) src2) - ; Note that this doesn't do the sign extension, which is correct. - (set acc - (add acc - (mul (ext DI src1) - (ext DI (trunc HI (sra src2 (const 16))))))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni macwlo "macwlo" - ((MACH m32r) (PIPE S) (IDOC MAC)) - "macwlo $src1,$src2" - (+ OP1_3 OP2_7 src1 src2) - (set accum - (sra DI - (sll DI - (add DI - accum - (mul DI - (ext DI src1) - (ext DI (trunc HI src2)))) - (const 8)) - (const 8))) - ((m32r/d (unit u-mac))) -) - -(dni macwlo-a "macwlo-a" - ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC MAC)) - "macwlo $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 7) src2) - ; Note that this doesn't do the sign extension, which is correct. - (set acc - (add acc - (mul (ext DI src1) - (ext DI (trunc HI src2))))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni mul "mul" - ((PIPE S) (IDOC ALU)) - "mul $dr,$sr" - (+ OP1_1 OP2_6 dr sr) - (set dr (mul dr sr)) - ((m32r/d (unit u-exec (cycles 4))) - (m32rx (unit u-exec (cycles 4))) - (m32r2 (unit u-exec (cycles 4)))) -) - -(dni mulhi "mulhi" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mulhi $src1,$src2" - (+ OP1_3 OP2_0 src1 src2) - (set accum - (sra DI - (sll DI - (mul DI - (ext DI (and WI src1 (const #xffff0000))) - (ext DI (trunc HI (sra WI src2 (const 16))))) - (const 16)) - (const 16))) - ((m32r/d (unit u-mac))) -) - -(dni mulhi-a "mulhi-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mulhi $src1,$src2,$acc" - (+ OP1_3 (f-op23 0) src1 acc src2) - (set acc - (sra DI - (sll DI - (mul DI - (ext DI (and WI src1 (const #xffff0000))) - (ext DI (trunc HI (sra WI src2 (const 16))))) - (const 16)) - (const 16))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni mullo "mullo" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mullo $src1,$src2" - (+ OP1_3 OP2_1 src1 src2) - (set accum - (sra DI - (sll DI - (mul DI - (ext DI (sll WI src1 (const 16))) - (ext DI (trunc HI src2))) - (const 16)) - (const 16))) - ((m32r/d (unit u-mac))) -) - -(dni mullo-a "mullo-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mullo $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 1) src2) - (set acc - (sra DI - (sll DI - (mul DI - (ext DI (sll WI src1 (const 16))) - (ext DI (trunc HI src2))) - (const 16)) - (const 16))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni mulwhi "mulwhi" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mulwhi $src1,$src2" - (+ OP1_3 OP2_2 src1 src2) - (set accum - (sra DI - (sll DI - (mul DI - (ext DI src1) - (ext DI (trunc HI (sra WI src2 (const 16))))) - (const 8)) - (const 8))) - ((m32r/d (unit u-mac))) -) - -(dni mulwhi-a "mulwhi-a" - ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) - "mulwhi $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 2) src2) - ; Note that this doesn't do the sign extension, which is correct. - (set acc - (mul (ext DI src1) - (ext DI (trunc HI (sra src2 (const 16)))))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni mulwlo "mulwlo" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mulwlo $src1,$src2" - (+ OP1_3 OP2_3 src1 src2) - (set accum - (sra DI - (sll DI - (mul DI - (ext DI src1) - (ext DI (trunc HI src2))) - (const 8)) - (const 8))) - ((m32r/d (unit u-mac))) -) - -(dni mulwlo-a "mulwlo-a" - ((MACH m32rx,m32r2) (PIPE S) SPECIAL (IDOC ACCUM)) - "mulwlo $src1,$src2,$acc" - (+ OP1_3 src1 acc (f-op23 3) src2) - ; Note that this doesn't do the sign extension, which is correct. - (set acc - (mul (ext DI src1) - (ext DI (trunc HI src2)))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dni mv "mv" - ((PIPE OS) (IDOC ALU)) - "mv $dr,$sr" - (+ OP1_1 OP2_8 dr sr) - (set dr sr) - () -) - -(dni mvfachi "mvfachi" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mvfachi $dr" - (+ OP1_5 OP2_15 (f-r2 0) dr) - (set dr (trunc WI (sra DI accum (const 32)))) - ((m32r/d (unit u-exec (cycles 2)))) -) - -(dni mvfachi-a "mvfachi-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mvfachi $dr,$accs" - (+ OP1_5 dr OP2_15 accs (f-op3 0)) - (set dr (trunc WI (sra DI accs (const 32)))) - ((m32rx (unit u-exec (cycles 2))) - (m32r2 (unit u-exec (cycles 2)))) -) - -(dni mvfaclo "mvfaclo" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mvfaclo $dr" - (+ OP1_5 OP2_15 (f-r2 1) dr) - (set dr (trunc WI accum)) - ((m32r/d (unit u-exec (cycles 2)))) -) - -(dni mvfaclo-a "mvfaclo-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mvfaclo $dr,$accs" - (+ OP1_5 dr OP2_15 accs (f-op3 1)) - (set dr (trunc WI accs)) - ((m32rx (unit u-exec (cycles 2))) - (m32r2 (unit u-exec (cycles 2)))) -) - -(dni mvfacmi "mvfacmi" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mvfacmi $dr" - (+ OP1_5 OP2_15 (f-r2 2) dr) - (set dr (trunc WI (sra DI accum (const 16)))) - ((m32r/d (unit u-exec (cycles 2)))) -) - -(dni mvfacmi-a "mvfacmi-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mvfacmi $dr,$accs" - (+ OP1_5 dr OP2_15 accs (f-op3 2)) - (set dr (trunc WI (sra DI accs (const 16)))) - ((m32rx (unit u-exec (cycles 2))) - (m32r2 (unit u-exec (cycles 2)))) -) - -(dni mvfc "mvfc" - ((PIPE O) (IDOC MISC)) - "mvfc $dr,$scr" - (+ OP1_1 OP2_9 dr scr) - (set dr scr) - () -) - -(dni mvtachi "mvtachi" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mvtachi $src1" - (+ OP1_5 OP2_7 (f-r2 0) src1) - (set accum - (or DI - (and DI accum (const DI #xffffffff)) - (sll DI (ext DI src1) (const 32)))) - ((m32r/d (unit u-exec (in sr src1)))) -) - -(dni mvtachi-a "mvtachi-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mvtachi $src1,$accs" - (+ OP1_5 src1 OP2_7 accs (f-op3 0)) - (set accs - (or DI - (and DI accs (const DI #xffffffff)) - (sll DI (ext DI src1) (const 32)))) - ((m32rx (unit u-exec (in sr src1))) - (m32r2 (unit u-exec (in sr src1)))) -) - -(dni mvtaclo "mvtaclo" - ((MACH m32r) (PIPE S) (IDOC ACCUM)) - "mvtaclo $src1" - (+ OP1_5 OP2_7 (f-r2 1) src1) - (set accum - (or DI - (and DI accum (const DI #xffffffff00000000)) - (zext DI src1))) - ((m32r/d (unit u-exec (in sr src1)))) -) - -(dni mvtaclo-a "mvtaclo-a" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "mvtaclo $src1,$accs" - (+ OP1_5 src1 OP2_7 accs (f-op3 1)) - (set accs - (or DI - (and DI accs (const DI #xffffffff00000000)) - (zext DI src1))) - ((m32rx (unit u-exec (in sr src1))) - (m32r2 (unit u-exec (in sr src1)))) -) - -(dni mvtc "mvtc" - ((PIPE O) (IDOC MISC)) - "mvtc $sr,$dcr" - (+ OP1_1 OP2_10 dcr sr) - (set dcr sr) - () -) - -(dni neg "neg" - ((PIPE OS) (IDOC ALU)) - "neg $dr,$sr" - (+ OP1_0 OP2_3 dr sr) - (set dr (neg sr)) - () -) - -(dni nop "nop" - ((PIPE OS) (IDOC MISC)) - "nop" - (+ OP1_7 OP2_0 (f-r1 0) (f-r2 0)) - (c-code VOID "PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);\n") - ; FIXME: quick hack: parallel nops don't contribute to cycle count. - ; Other kinds of nops do however (which we currently ignore). - ((m32r/d (unit u-exec (cycles 0))) - (m32rx (unit u-exec (cycles 0))) - (m32r2 (unit u-exec (cycles 0)))) -) - -(dni not "not" - ((PIPE OS) (IDOC ALU)) - "not $dr,$sr" - (+ OP1_0 OP2_11 dr sr) - (set dr (inv sr)) - () -) - -(dni rac "rac" - ((MACH m32r) (PIPE S) (IDOC MAC)) - "rac" - (+ OP1_5 OP2_9 (f-r1 0) (f-r2 0)) - (sequence ((DI tmp1)) - (set tmp1 (sll DI accum (const 1))) - (set tmp1 (add DI tmp1 (const DI #x8000))) - (set accum - (cond DI - ((gt tmp1 (const DI #x00007fffffff0000)) - (const DI #x00007fffffff0000)) - ((lt tmp1 (const DI #xffff800000000000)) - (const DI #xffff800000000000)) - (else (and tmp1 (const DI #xffffffffffff0000))))) - ) - ((m32r/d (unit u-mac))) -) - -(dni rac-dsi "rac-dsi" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "rac $accd,$accs,$imm1" - (+ OP1_5 accd (f-bits67 0) OP2_9 accs (f-bit14 0) imm1) - (sequence ((DI tmp1)) - (set tmp1 (sll accs imm1)) - (set tmp1 (add tmp1 (const DI #x8000))) - (set accd - (cond DI - ((gt tmp1 (const DI #x00007fffffff0000)) - (const DI #x00007fffffff0000)) - ((lt tmp1 (const DI #xffff800000000000)) - (const DI #xffff800000000000)) - (else (and tmp1 (const DI #xffffffffffff0000))))) - ) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dnmi rac-d "rac-d" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "rac $accd" - (emit rac-dsi accd (f-accs 0) (f-imm1 0)) -) - -(dnmi rac-ds "rac-ds" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "rac $accd,$accs" - (emit rac-dsi accd accs (f-imm1 0)) -) - - -(dni rach "rach" - ((MACH m32r) (PIPE S) (IDOC MAC)) - "rach" - (+ OP1_5 OP2_8 (f-r1 0) (f-r2 0)) - (sequence ((DI tmp1)) - ; Lop off top 8 bits. - ; The sign bit we want to use is bit 55 so the 64 bit value - ; isn't properly signed which we deal with in the if's below. - (set tmp1 (and accum (const DI #xffffffffffffff))) - (if (andif (ge tmp1 (const DI #x003fff80000000)) - (le tmp1 (const DI #x7fffffffffffff))) - (set tmp1 (const DI #x003fff80000000)) - ; else part - (if (andif (ge tmp1 (const DI #x80000000000000)) - (le tmp1 (const DI #xffc00000000000))) - (set tmp1 (const DI #xffc00000000000)) - (set tmp1 (and (add accum (const DI #x40000000)) - (const DI #xffffffff80000000))))) - (set tmp1 (sll tmp1 (const 1))) - ; Sign extend top 8 bits. - (set accum - ; FIXME: 7? - (sra DI (sll DI tmp1 (const 7)) (const 7))) - ) - ((m32r/d (unit u-mac))) -) - -(dni rach-dsi "rach-dsi" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "rach $accd,$accs,$imm1" - (+ OP1_5 accd (f-bits67 0) OP2_8 accs (f-bit14 0) imm1) - (sequence ((DI tmp1)) - (set tmp1 (sll accs imm1)) - (set tmp1 (add tmp1 (const DI #x80000000))) - (set accd - (cond DI - ((gt tmp1 (const DI #x00007fff00000000)) - (const DI #x00007fff00000000)) - ((lt tmp1 (const DI #xffff800000000000)) - (const DI #xffff800000000000)) - (else (and tmp1 (const DI #xffffffff00000000))))) - ) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -(dnmi rach-d "rach-d" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "rach $accd" - (emit rach-dsi accd (f-accs 0) (f-imm1 0)) -) - -(dnmi rach-ds "rach-ds" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "rach $accd,$accs" - (emit rach-dsi accd accs (f-imm1 0)) -) - -(dni rte "rte" - (UNCOND-CTI (PIPE O) (IDOC BR)) - "rte" - (+ OP1_1 OP2_13 (f-r1 0) (f-r2 6)) - (sequence () - ; pc = bpc & -4 - (set pc (and (reg h-cr 6) (const -4))) - ; bpc = bbpc - (set (reg h-cr 6) (reg h-cr 14)) - ; psw = bpsw - (set (reg h-psw) (reg h-bpsw)) - ; bpsw = bbpsw - (set (reg h-bpsw) (reg h-bbpsw)) - ) - () -) - -(dni seth "seth" - ((IDOC ALU)) - "seth $dr,$hash$hi16" - (+ OP1_13 OP2_12 dr (f-r2 0) hi16) - (set dr (sll WI hi16 (const 16))) - () -) - -(define-pmacro (shift-op sym op2-r-op op2-3-op op2-i-op sem-op) - (begin - (dni sym sym ((PIPE O_OS) (IDOC ALU)) - (.str sym " $dr,$sr") - (+ OP1_1 op2-r-op dr sr) - (set dr (sem-op dr (and sr (const 31)))) - () - ) - (dni (.sym sym "3") sym ((IDOC ALU)) - (.str sym "3 $dr,$sr,$simm16") - (+ OP1_9 op2-3-op dr sr simm16) - (set dr (sem-op sr (and WI simm16 (const 31)))) - () - ) - (dni (.sym sym "i") sym ((PIPE O_OS) (IDOC ALU)) - (.str sym "i $dr,$uimm5") - (+ OP1_5 (f-shift-op2 op2-i-op) dr uimm5) - (set dr (sem-op dr uimm5)) - () - ) - ) -) -(shift-op sll OP2_4 OP2_12 2 sll) -(shift-op sra OP2_2 OP2_10 1 sra) -(shift-op srl OP2_0 OP2_8 0 srl) - -(define-pmacro (store-op suffix op2-op mode) - (begin - (dni (.sym st suffix) (.str "st" suffix) - ((PIPE O) (IDOC MEM)) - (.str "st" suffix " $src1,@$src2") - (+ OP1_2 op2-op src1 src2) - (set mode (mem mode src2) src1) - ((m32r/d (unit u-store (cycles 1))) - (m32rx (unit u-store (cycles 1))) - (m32r2 (unit u-store (cycles 1)))) - ) - (dnmi (.sym st suffix "-2") (.str "st" suffix "-2") - (NO-DIS (PIPE O) (IDOC MEM)) - (.str "st" suffix " $src1,@($src2)") - (emit (.sym st suffix) src1 src2)) - (dni (.sym st suffix -d) (.str "st" suffix "-d") - ((IDOC MEM)) - (.str "st" suffix " $src1,@($slo16,$src2)") - (+ OP1_10 op2-op src1 src2 slo16) - (set mode (mem mode (add src2 slo16)) src1) - ((m32r/d (unit u-store (cycles 2))) - (m32rx (unit u-store (cycles 2))) - (m32r2 (unit u-store (cycles 2)))) - ) - (dnmi (.sym st suffix -d2) (.str "st" suffix "-d2") - (NO-DIS (IDOC MEM)) - (.str "st" suffix " $src1,@($src2,$slo16)") - (emit (.sym st suffix -d) src1 src2 slo16)) - ) -) -(store-op "" OP2_4 WI) -(store-op b OP2_0 QI) -(store-op h OP2_2 HI) - -(dni st-plus "st+" - ((PIPE O) (IDOC MEM)) - "st $src1,@+$src2" - (+ OP1_2 OP2_6 src1 src2) - ; This has to be coded carefully to avoid an "earlyclobber" of src2. - (sequence ((WI new-src2)) - (set new-src2 (add WI src2 (const WI 4))) - (set (mem WI new-src2) src1) - (set src2 new-src2)) - ((m32r/d (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - (m32rx (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - (m32r2 (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - ) -) - -(dni sth-plus "sth+" - ((MACH m32rx,m32r2) (PIPE O) SPECIAL) - "sth $src1,@$src2+" - (+ OP1_2 OP2_3 src1 src2) - ; This has to be coded carefully to avoid an "earlyclobber" of src2. - (sequence ((WI new-src2)) - (set new-src2 src2) - (set (mem HI new-src2) src1) - (set src2 (add new-src2 (const 2)))) - ((m32rx (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - (m32r2 (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - ) -) - -(dni stb-plus "stb+" - ((MACH m32rx,m32r2) (PIPE O) SPECIAL) - "stb $src1,@$src2+" - (+ OP1_2 OP2_1 src1 src2) - ; This has to be coded carefully to avoid an "earlyclobber" of src2. - (sequence ((WI new-src2)) - (set new-src2 src2) - (set (mem QI new-src2) src1) - (set src2 (add new-src2 (const 1)))) - ((m32rx (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - (m32r2 (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - ) -) - -(dni st-minus "st-" - ((PIPE O) (IDOC MEM)) - "st $src1,@-$src2" - (+ OP1_2 OP2_7 src1 src2) - ; This is the original way. It doesn't work for parallel execution - ; because of the earlyclobber of src2. - ;(sequence () - ; (set src2 (sub src2 (const 4))) - ; (set (mem WI src2) src1)) - (sequence ((WI new-src2)) - (set new-src2 (sub src2 (const 4))) - (set (mem WI new-src2) src1) - (set src2 new-src2)) - ((m32r/d (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - (m32rx (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - (m32r2 (unit u-store) - (unit u-exec (in dr src2) (out dr src2) (cycles 0))) - ) -) - -(dnmi push "push" ((PIPE O) (IDOC MEM)) - "push $src1" - (emit st-minus src1 (src2 15)) ; "st %0,@-sp" -) - -(dni sub "sub" - ((PIPE OS) (IDOC ALU)) - "sub $dr,$sr" - (+ OP1_0 OP2_2 dr sr) - (set dr (sub dr sr)) - () -) - -(dni subv "sub:rv" - ((PIPE OS) (IDOC ALU)) - "subv $dr,$sr" - (+ OP1_0 OP2_0 dr sr) - (parallel () - (set dr (sub dr sr)) - (set condbit (sub-oflag dr sr (const 0)))) - () -) - -(dni subx "sub:rx" - ((PIPE OS) (IDOC ALU)) - "subx $dr,$sr" - (+ OP1_0 OP2_1 dr sr) - (parallel () - (set dr (subc dr sr condbit)) - (set condbit (sub-cflag dr sr condbit))) - () -) - -(dni trap "trap" - (UNCOND-CTI FILL-SLOT (PIPE O) (IDOC MISC)) - "trap $uimm4" - (+ OP1_1 OP2_15 (f-r1 0) uimm4) - (sequence () - ; bbpc = bpc - (set (reg h-cr 14) (reg h-cr 6)) - ; Set bpc to the return address. Actually it's not quite the - ; return address as RTE rounds the address down to a word - ; boundary. - (set (reg h-cr 6) (add pc (const 4))) - ; bbpsw = bpsw - (set (reg h-bbpsw) (reg h-bpsw)) - ; bpsw = psw - (set (reg h-bpsw) (reg h-psw)) - ; sm is unchanged, ie,c are set to zero. - (set (reg h-psw) (and (reg h-psw) (const #x80))) - ; m32r_trap handles operating vs user mode - (set WI pc (c-call WI "m32r_trap" pc uimm4)) - ) - () -) - -(dni unlock "unlock" - ((PIPE O) (IDOC MISC)) - "unlock $src1,@$src2" - (+ OP1_2 OP2_5 src1 src2) - (sequence () - (if (reg h-lock) - (set (mem WI src2) src1)) - (set (reg h-lock) (const BI 0))) - ((m32r/d (unit u-load)) - (m32rx (unit u-load)) - (m32r2 (unit u-load))) -) - -; Saturate into byte. -(dni satb "satb" - ((MACH m32rx,m32r2) (IDOC ALU)) - "satb $dr,$sr" - (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0300)) - (set dr - ; FIXME: min/max would simplify this nicely of course. - (cond WI - ((ge sr (const 127)) (const 127)) - ((le sr (const -128)) (const -128)) - (else sr))) - () -) - -; Saturate into half word. -(dni sath "sath" - ((MACH m32rx,m32r2) (IDOC ALU)) - "sath $dr,$sr" - (+ OP1_8 dr OP2_6 sr (f-uimm16 #x0200)) - (set dr - (cond WI - ((ge sr (const 32767)) (const 32767)) - ((le sr (const -32768)) (const -32768)) - (else sr))) - () -) - -; Saturate word. -(dni sat "sat" - ((MACH m32rx,m32r2) SPECIAL (IDOC ALU)) - "sat $dr,$sr" - (+ OP1_8 dr OP2_6 sr (f-uimm16 0)) - (set dr - (if WI condbit - (if WI (lt sr (const 0)) - (const #x7fffffff) - (const #x80000000)) - sr)) - () -) - -; Parallel compare byte zeros. -; Set C bit in condition register if any byte in source register is zero. -(dni pcmpbz "pcmpbz" - ((MACH m32rx,m32r2) (PIPE OS) SPECIAL (IDOC ALU)) - "pcmpbz $src2" - (+ OP1_0 (f-r1 3) OP2_7 src2) - (set condbit - (cond BI - ((eq (and src2 (const #xff)) (const 0)) (const BI 1)) - ((eq (and src2 (const #xff00)) (const 0)) (const BI 1)) - ((eq (and src2 (const #xff0000)) (const 0)) (const BI 1)) - ((eq (and src2 (const #xff000000)) (const 0)) (const BI 1)) - (else (const BI 0)))) - ((m32rx (unit u-cmp)) - (m32r2 (unit u-cmp))) -) - -; Add accumulators -(dni sadd "sadd" - ((MACH m32rx,m32r2) (PIPE S) (IDOC ACCUM)) - "sadd" - (+ OP1_5 (f-r1 0) OP2_14 (f-r2 4)) - (set (reg h-accums 0) - (add (sra (reg h-accums 1) (const 16)) - (reg h-accums 0))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -; Multiply and add into accumulator 1 -(dni macwu1 "macwu1" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "macwu1 $src1,$src2" - (+ OP1_5 src1 OP2_11 src2) - (set (reg h-accums 1) - (sra DI - (sll DI - (add DI - (reg h-accums 1) - (mul DI - (ext DI src1) - (ext DI (and src2 (const #xffff))))) - (const 8)) - (const 8))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -; Multiply and subtract from accumulator 0 -(dni msblo "msblo" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "msblo $src1,$src2" - (+ OP1_5 src1 OP2_13 src2) - (set accum - (sra DI - (sll DI - (sub accum - (sra DI - (sll DI - (mul DI - (ext DI (trunc HI src1)) - (ext DI (trunc HI src2))) - (const 32)) - (const 16))) - (const 8)) - (const 8))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -; Multiply into accumulator 1 -(dni mulwu1 "mulwu1" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "mulwu1 $src1,$src2" - (+ OP1_5 src1 OP2_10 src2) - (set (reg h-accums 1) - (sra DI - (sll DI - (mul DI - (ext DI src1) - (ext DI (and src2 (const #xffff)))) - (const 16)) - (const 16))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -; Multiply and add into accumulator 1 -(dni maclh1 "maclh1" - ((MACH m32rx,m32r2) (PIPE S) (IDOC MAC)) - "maclh1 $src1,$src2" - (+ OP1_5 src1 OP2_12 src2) - (set (reg h-accums 1) - (sra DI - (sll DI - (add DI - (reg h-accums 1) - (sll DI - (ext DI - (mul SI - (ext SI (trunc HI src1)) - (sra SI src2 (const SI 16)))) - (const 16))) - (const 8)) - (const 8))) - ((m32rx (unit u-mac)) - (m32r2 (unit u-mac))) -) - -; skip instruction if C -(dni sc "sc" - ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) - "sc" - (+ OP1_7 (f-r1 4) OP2_0 (f-r2 1)) - (skip (zext INT condbit)) - () -) - -; skip instruction if not C -(dni snc "snc" - ((MACH m32rx,m32r2) (PIPE O) SPECIAL (IDOC BR)) - "snc" - (+ OP1_7 (f-r1 5) OP2_0 (f-r2 1)) - (skip (zext INT (not condbit))) - () -) - -; PSW &= ((~ uimm8) | 0xff00) -(dni clrpsw "clrpsw" - ((PIPE O) SPECIAL_M32R) - "clrpsw $uimm8" - (+ OP1_7 (f-r1 2) uimm8) - (set USI (reg h-cr 0) - (and USI (reg h-cr 0) - (or USI (zext SI (inv QI uimm8)) (const #xff00)))) - () -) - -; PSW |= (unsigned char) uimm8 -(dni setpsw "setpsw" - ((PIPE O) SPECIAL_M32R) - "setpsw $uimm8" - (+ OP1_7 (f-r1 1) uimm8) - (set USI (reg h-cr 0) uimm8) - () -) - -; bset -(dni bset "bset" - (SPECIAL_M32R) - "bset $uimm3,@($slo16,$sr)" - (+ OP1_10 (f-bit4 0) uimm3 OP2_6 sr slo16) - (set QI (mem QI (add sr slo16)) - (or QI (mem QI (add sr slo16)) - (sll QI (const 1) (sub (const 7) uimm3)))) - () -) - -; bclr -(dni bclr "bclr" - (SPECIAL_M32R) - "bclr $uimm3,@($slo16,$sr)" - (+ OP1_10 (f-bit4 0) uimm3 OP2_7 sr slo16) - (set QI (mem QI (add sr slo16)) - (and QI (mem QI (add sr slo16)) - (inv QI (sll QI (const 1) (sub (const 7) uimm3))))) - () -) - -; btst -(dni btst "btst" - (SPECIAL_M32R (PIPE O)) - "btst $uimm3,$sr" - (+ OP1_0 (f-bit4 0) uimm3 OP2_15 sr) - (set condbit (and QI (srl QI sr (sub (const 7) uimm3)) (const 1))) - () -) diff --git a/binutils-2.24/cpu/m32r.opc b/binutils-2.24/cpu/m32r.opc deleted file mode 100644 index 30e0956e..00000000 --- a/binutils-2.24/cpu/m32r.opc +++ /dev/null @@ -1,347 +0,0 @@ -/* M32R opcode support. -*- C -*- - - Copyright 1998, 1999, 2000, 2001, 2004, 2005, 2007, 2009 - Free Software Foundation, Inc. - - Contributed by Red Hat Inc; developed under contract from - Mitsubishi Electric Corporation. - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* This file is an addendum to m32r.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h" */ - -/* -- opc.h */ - -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 256 -#undef CGEN_DIS_HASH -#if 0 -#define X(b) (((unsigned char *) (b))[0] & 0xf0) -#define CGEN_DIS_HASH(buffer, value) \ -(X (buffer) | \ - (X (buffer) == 0x40 || X (buffer) == 0xe0 || X (buffer) == 0x60 || X (buffer) == 0x50 ? 0 \ - : X (buffer) == 0x70 || X (buffer) == 0xf0 ? (((unsigned char *) (buffer))[0] & 0xf) \ - : X (buffer) == 0x30 ? ((((unsigned char *) (buffer))[1] & 0x70) >> 4) \ - : ((((unsigned char *) (buffer))[1] & 0xf0) >> 4))) -#else -#define CGEN_DIS_HASH(buffer, value) m32r_cgen_dis_hash (buffer, value) -extern unsigned int m32r_cgen_dis_hash (const char *, CGEN_INSN_INT); -#endif - -/* -- */ - -/* -- opc.c */ -unsigned int -m32r_cgen_dis_hash (const char * buf ATTRIBUTE_UNUSED, CGEN_INSN_INT value) -{ - unsigned int x; - - if (value & 0xffff0000) /* 32bit instructions. */ - value = (value >> 16) & 0xffff; - - x = (value >> 8) & 0xf0; - if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50) - return x; - - if (x == 0x70 || x == 0xf0) - return x | ((value >> 8) & 0x0f); - - if (x == 0x30) - return x | ((value & 0x70) >> 4); - else - return x | ((value & 0xf0) >> 4); -} - -/* -- */ - -/* -- asm.c */ -static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); - -/* Handle '#' prefixes (i.e. skip over them). */ - -static const char * -parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (**strp == '#') - ++*strp; - return NULL; -} - -/* Handle shigh(), high(). */ - -static const char * -parse_hi16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "high(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - value >>= 16; - value &= 0xffff; - } - *valuep = value; - return errmsg; - } - else if (strncasecmp (*strp, "shigh(", 6) == 0) - { - *strp += 6; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - { - value += 0x8000; - value >>= 16; - value &= 0xffff; - } - *valuep = value; - return errmsg; - } - - return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -} - -/* Handle low() in a signed context. Also handle sda(). - The signedness of the value doesn't matter to low(), but this also - handles the case where low() isn't present. */ - -static const char * -parse_slo16 (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - long * valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "low(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = ((value & 0xffff) ^ 0x8000) - 0x8000; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "sda(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16, - NULL, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - *valuep = value; - return errmsg; - } - - return cgen_parse_signed_integer (cd, strp, opindex, valuep); -} - -/* Handle low() in an unsigned context. - The signedness of the value doesn't matter to low(), but this also - handles the case where low() isn't present. */ - -static const char * -parse_ulo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "low(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - *valuep = value; - return errmsg; - } - - return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -} - -/* -- */ - -/* -- dis.c */ - -/* Print signed operands with '#' prefixes. */ - -static void -print_signed_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "#"); - (*info->fprintf_func) (info->stream, "%ld", value); -} - -/* Print unsigned operands with '#' prefixes. */ - -static void -print_unsigned_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "#"); - (*info->fprintf_func) (info->stream, "0x%lx", value); -} - -/* Handle '#' prefixes as operands. */ - -static void -print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "#"); -} - -#undef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN my_print_insn - -static int -my_print_insn (CGEN_CPU_DESC cd, - bfd_vma pc, - disassemble_info *info) -{ - bfd_byte buffer[CGEN_MAX_INSN_SIZE]; - bfd_byte *buf = buffer; - int status; - int buflen = (pc & 3) == 0 ? 4 : 2; - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - bfd_byte *x; - - /* Read the base part of the insn. */ - - status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0), - buf, buflen, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - /* 32 bit insn? */ - x = (big_p ? &buf[0] : &buf[3]); - if ((pc & 3) == 0 && (*x & 0x80) != 0) - return print_insn (cd, pc, info, buf, buflen); - - /* Print the first insn. */ - if ((pc & 3) == 0) - { - buf += (big_p ? 0 : 2); - if (print_insn (cd, pc, info, buf, 2) == 0) - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - buf += (big_p ? 2 : -2); - } - - x = (big_p ? &buf[0] : &buf[1]); - if (*x & 0x80) - { - /* Parallel. */ - (*info->fprintf_func) (info->stream, " || "); - *x &= 0x7f; - } - else - (*info->fprintf_func) (info->stream, " -> "); - - /* The "& 3" is to pass a consistent address. - Parallel insns arguably both begin on the word boundary. - Also, branch insns are calculated relative to the word boundary. */ - if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0) - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - - return (pc & 3) ? 2 : 4; -} - -/* -- */ diff --git a/binutils-2.24/cpu/mep-avc.cpu b/binutils-2.24/cpu/mep-avc.cpu deleted file mode 100644 index e4d13f8d..00000000 --- a/binutils-2.24/cpu/mep-avc.cpu +++ /dev/null @@ -1,1423 +0,0 @@ -; Toshiba MeP AVC Coprocessor description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; This file was customized based upon the output of a2cgen 0.42 - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; This coprocessor requires 16 and 32 bit insns. -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro avc-core-isa () (ISA ext_core1)) -(define-pmacro avc-16-isa () (ISA ext_cop1_16)) -(define-pmacro avc-32-isa () (ISA ext_cop1_32)) -(define-pmacro all-avc-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32)) -; end-isas - -(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc-core-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc-16-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc-32-isa) xsyntax xformat xsemantics xtiming)) - -; register definitions -; --------------------- -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-avc) - (comment "32-bit coprocessor registers for avc coprocessor") - (attrs VIRTUAL all-avc-isas) - (type register SI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) - (indices keyword "$c" (.map -reg-pair (.iota 8))) -) -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-avc) - (comment "Coprocessor control registers for avc coprocessor") - (attrs VIRTUAL all-avc-isas) - (type register SI (64)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) - (indices keyword "" - (.splice - ($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0) - ($cbcr 1) - (.unsplice (.map -ccr-reg-pair (.iota 6))) - ) - ) -) -(dnop avccopCCR5 "Audio Copro Accumulator" (all-avc-isas) h-ccr 5) -(dnop avccopCCR4 "Audio Copro Accumulator" (all-avc-isas) h-ccr 4) -(dnop avccopCCR3 "Audio Copro Accumulator" (all-avc-isas) h-ccr 3) -(dnop avccopCCR2 "Audio Copro Accumulator" (all-avc-isas) h-ccr 2) -(dnop avccopCCR1 "Audio Copro Branch Condition Register" (all-avc-isas) h-ccr 1) -(dnop avccopCCR0 "Audio Copro Shift-Amount Register" (all-avc-isas) h-ccr 0) - -; instruction field and operand definitions -(dnf f-avc-v3sub4u0 "sub opecode field" (avc-32-isa) 0 4) -(dnf f-avc-v1sub4u0 "sub opecode field" (avc-16-isa) 0 4) -(dnf f-avc-v3Rn "register field" (avc-32-isa) 4 4) -(dnop avcv3Rn "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rn) -(dnf f-avc-v3CCRn "register field" (avc-32-isa) 4 4) -(define-full-operand avcv3CCRn "the operand definition" (avc-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc-v3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ()) -(df f-avc-v3Imm16s4x24e32-hi "split immediate field hi" (avc-32-isa) 4 8 INT #f #f) -(df f-avc-v3Imm16s4x24e32-lo "split immediate field lo" (avc-32-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc-v3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc-32-isa) - (mode INT) - (subfields f-avc-v3Imm16s4x24e32-hi f-avc-v3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc-v3Imm16s4x24e32) 8)) - (set (ifield f-avc-v3Imm16s4x24e32-lo) (and (ifield f-avc-v3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc-v3Imm16s4x24e32) - (or (sll (ifield f-avc-v3Imm16s4x24e32-hi) 8) (ifield f-avc-v3Imm16s4x24e32-lo)))) - ) -(dnop avcv3Imm16s4x24e32 "the operand definition" (avc-32-isa) h-sint f-avc-v3Imm16s4x24e32) -(dnf f-avc-v3CRn "register field" (avc-32-isa) 4 4) -(define-full-operand avcv3CRn "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRn ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1CRq "register field" (avc-16-isa) 4 4) -(define-full-operand avcv1CRq "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRq ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1sub4u4 "sub opecode field" (avc-16-isa) 4 4) -(dnf f-avc-c3Rn "register field" (avc-core-isa) 4 4) -(dnop avcc3Rn "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rn) -(dnf f-avc-c3CCRn "register field" (avc-core-isa) 4 4) -(define-full-operand avcc3CCRn "the operand definition" (avc-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc-c3CCRn ( (parse "avc_ccr") (print "avc_ccr")) () ()) -(df f-avc-c3Imm16s4x24e32-hi "split immediate field hi" (avc-core-isa) 4 8 INT #f #f) -(df f-avc-c3Imm16s4x24e32-lo "split immediate field lo" (avc-core-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc-c3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc-core-isa) - (mode INT) - (subfields f-avc-c3Imm16s4x24e32-hi f-avc-c3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc-c3Imm16s4x24e32) 8)) - (set (ifield f-avc-c3Imm16s4x24e32-lo) (and (ifield f-avc-c3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc-c3Imm16s4x24e32) - (or (sll (ifield f-avc-c3Imm16s4x24e32-hi) 8) (ifield f-avc-c3Imm16s4x24e32-lo)))) - ) -(dnop avcc3Imm16s4x24e32 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm16s4x24e32) -(dnf f-avc-c3CRn "register field" (avc-core-isa) 4 4) -(define-full-operand avcc3CRn "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRn ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u4 "sub opecode field" (avc-core-isa) 4 4) -(dnf f-avc-v3Rm "register field" (avc-32-isa) 8 4) -(dnop avcv3Rm "the operand definition" (avc-32-isa) h-gpr f-avc-v3Rm) -(df f-avc-v1Imm5u8 "immediate field" (avc-16-isa) 8 5 UINT #f #f) -(dnop avcv1Imm5u8 "the operand definition" (avc-16-isa) h-uint f-avc-v1Imm5u8) -(df f-avc-v1Imm6s8 "immediate field" (avc-16-isa) 8 6 INT #f #f) -(dnop avcv1Imm6s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm6s8) -(df f-avc-v1Imm8s8 "immediate field" (avc-16-isa) 8 8 INT #f #f) -(dnop avcv1Imm8s8 "the operand definition" (avc-16-isa) h-sint f-avc-v1Imm8s8) -(dnf f-avc-v1CRp "register field" (avc-16-isa) 8 4) -(define-full-operand avcv1CRp "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRp ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1sub4u8 "sub opecode field" (avc-16-isa) 8 4) -(dnf f-avc-c3Rm "register field" (avc-core-isa) 8 4) -(dnop avcc3Rm "the operand definition" (avc-core-isa) h-gpr f-avc-c3Rm) -(dnf f-avc-c3sub4u8 "sub opecode field" (avc-core-isa) 8 4) -(dnf f-avc-v3sub4u12 "sub opecode field" (avc-32-isa) 12 4) -(dnf f-avc-v1CRo "register field" (avc-16-isa) 12 4) -(define-full-operand avcv1CRo "the operand definition" (avc-16-isa) h-cr DFLT f-avc-v1CRo ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v1sub4u12 "sub opecode field" (avc-16-isa) 12 4) -(dnf f-avc-v1sub3u13 "sub opecode field" (avc-16-isa) 13 3) -(dnf f-avc-v1sub2u14 "sub opecode field" (avc-16-isa) 14 2) -(dnf f-avc-v3sub4u16 "sub opecode field" (avc-32-isa) 16 4) -(dnf f-avc-c3sub4u16 "sub opecode field" (avc-core-isa) 16 4) -(dnf f-avc-v3CRq "register field" (avc-32-isa) 20 4) -(define-full-operand avcv3CRq "the operand definition" (avc-32-isa) h-cr DFLT f-avc-v3CRq ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-v3sub4u20 "sub opecode field" (avc-32-isa) 20 4) -(dnf f-avc-c3CRq "register field" (avc-core-isa) 20 4) -(define-full-operand avcc3CRq "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRq ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u20 "sub opecode field" (avc-core-isa) 20 4) -(dnf f-avc-v3sub4u24 "sub opecode field" (avc-32-isa) 24 4) -(df f-avc-c3Imm5u24 "immediate field" (avc-core-isa) 24 5 UINT #f #f) -(dnop avcc3Imm5u24 "the operand definition" (avc-core-isa) h-uint f-avc-c3Imm5u24) -(df f-avc-c3Imm6s24 "immediate field" (avc-core-isa) 24 6 INT #f #f) -(dnop avcc3Imm6s24 "the operand definition" (avc-core-isa) h-sint f-avc-c3Imm6s24) -(dnf f-avc-c3CRp "register field" (avc-core-isa) 24 4) -(define-full-operand avcc3CRp "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRp ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u24 "sub opecode field" (avc-core-isa) 24 4) -(dnf f-avc-v3sub4u28 "sub opecode field" (avc-32-isa) 28 4) -(dnf f-avc-c3CRo "register field" (avc-core-isa) 28 4) -(define-full-operand avcc3CRo "the operand definition" (avc-core-isa) h-cr DFLT f-avc-c3CRo ((parse "avc_cr") (print "avc_cr")) () ()) -(dnf f-avc-c3sub4u28 "sub opecode field" (avc-core-isa) 28 4) -(dnf f-avc-c3sub3u29 "sub opecode field" (avc-core-isa) 29 3) -(dnf f-avc-c3sub2u30 "sub opecode field" (avc-core-isa) 30 2) - -; instruction definitions -(dncpi cnop_avc_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop")) - "cnop" -(+ MAJ_15 (f-sub4 7) (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(c-call "check_option_cp" pc) - ()) -(dncpi cmov1_avc_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1")) - "cmov $avcc3CRn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3CRn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRn avcc3Rm) -) - ()) -(dncpi cmov2_avc_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2")) - "cmov $avcc3Rm,$avcc3CRn" -(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CRn (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3Rm avcc3CRn) -) - ()) -(dncpi cmovi_avc_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi")) - "cmovi $avcc3CRq,$avcc3Imm16s4x24e32" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm16s4x24e32 (f-avc-c3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (ext SI avcc3Imm16s4x24e32)) -) - ()) -(dncpi cmovc1_avc_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1")) - "cmovc $avcc3CCRn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3CCRn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CCRn avcc3Rm) -) - ()) -(dncpi cmovc2_avc_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2")) - "cmovc $avcc3Rm,$avcc3CCRn" -(+ MAJ_15 (f-sub4 7) avcc3Rm avcc3CCRn (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3Rm avcc3CCRn) -) - ()) -(dncpi cmov_avc_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov")) - "cmov $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq avcc3CRp) -) - ()) -(dncpi cadd3_avc_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3")) - "cadd3 $avcc3CRo,$avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRo avcc3CRq avcc3CRp (f-avc-c3sub4u16 #x3) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRo (add avcc3CRq avcc3CRp)) -) - ()) -(dncpi caddi_avc_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi")) - "caddi $avcc3CRq,$avcc3Imm6s24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm6s24 (f-avc-c3sub2u30 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (add avcc3CRq (ext SI avcc3Imm6s24))) -) - ()) -(dncpi csub_avc_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub")) - "csub $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sub avcc3CRq avcc3CRp)) -) - ()) -(dncpi cneg_avc_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg")) - "cneg $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (neg avcc3CRp)) -) - ()) -(dncpi cextb_avc_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb")) - "cextb $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (ext SI (and QI (srl avcc3CRq 0) #xff))) -) - ()) -(dncpi cexth_avc_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth")) - "cexth $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x2) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (ext SI (and HI (srl avcc3CRq 0) #xffff))) -) - ()) -(dncpi cextub_avc_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub")) - "cextub $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x8) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (zext SI (and QI (srl avcc3CRq 0) #xff))) -) - ()) -(dncpi cextuh_avc_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh")) - "cextuh $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (zext SI (and HI (srl avcc3CRq 0) #xffff))) -) - ()) -(dncpi cscltz_avc_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz")) - "cscltz $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #xa) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dncpi cldz_avc_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz")) - "cldz $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (and avcc3CRp #x80000000) (set avcc3CRq 0) -(if (and avcc3CRp #x40000000) (set avcc3CRq 1) -(if (and avcc3CRp #x20000000) (set avcc3CRq 2) -(if (and avcc3CRp #x10000000) (set avcc3CRq 3) -(if (and avcc3CRp #x8000000) (set avcc3CRq 4) -(if (and avcc3CRp #x4000000) (set avcc3CRq 5) -(if (and avcc3CRp #x2000000) (set avcc3CRq 6) -(if (and avcc3CRp #x1000000) (set avcc3CRq 7) -(if (and avcc3CRp #x800000) (set avcc3CRq 8) -(if (and avcc3CRp #x400000) (set avcc3CRq 9) -(if (and avcc3CRp #x200000) (set avcc3CRq 10) -(if (and avcc3CRp #x100000) (set avcc3CRq 11) -(if (and avcc3CRp #x80000) (set avcc3CRq 12) -(if (and avcc3CRp #x40000) (set avcc3CRq 13) -(if (and avcc3CRp #x20000) (set avcc3CRq 14) -(if (and avcc3CRp #x10000) (set avcc3CRq 15) -(if (and avcc3CRp #x8000) (set avcc3CRq 16) -(if (and avcc3CRp #x4000) (set avcc3CRq 17) -(if (and avcc3CRp #x2000) (set avcc3CRq 18) -(if (and avcc3CRp #x1000) (set avcc3CRq 19) -(if (and avcc3CRp #x800) (set avcc3CRq 20) -(if (and avcc3CRp #x400) (set avcc3CRq 21) -(if (and avcc3CRp #x200) (set avcc3CRq 22) -(if (and avcc3CRp #x100) (set avcc3CRq 23) -(if (and avcc3CRp #x80) (set avcc3CRq 24) -(if (and avcc3CRp #x40) (set avcc3CRq 25) -(if (and avcc3CRp #x20) (set avcc3CRq 26) -(if (and avcc3CRp #x10) (set avcc3CRq 27) -(if (and avcc3CRp #x8) (set avcc3CRq 28) -(if (and avcc3CRp #x4) (set avcc3CRq 29) -(if (and avcc3CRp #x2) (set avcc3CRq 30) -(if (and avcc3CRp #x1) (set avcc3CRq 31) -(set avcc3CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dncpi cabs_avc_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs")) - "cabs $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x3) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (abs (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1)))) -) - ()) -(dncpi cad1s_avc_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s")) - "cad1s $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (add avcc3CRq avcc3CRp) 1))) -(set avcc3CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dncpi csb1s_avc_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s")) - "csb1s $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (sub avcc3CRq avcc3CRp) 1))) -(set avcc3CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dncpi cmin_avc_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin")) - "cmin $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cmax_avc_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax")) - "cmax $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avcc3CRq) (ext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cminu_avc_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu")) - "cminu $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cmaxu_avc_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu")) - "cmaxu $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xb) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avcc3CRq) (zext SI avcc3CRp)) (set avcc3CRq avcc3CRq) -(set avcc3CRq avcc3CRp) -) -) - ()) -(dncpi cclipi_avc_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi")) - "cclipi $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x4) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0) -(sequence() (set tmp0 (sll 1 (sub avcc3Imm5u24 1))) -(set tmp1 (sub (subword SI tmp0 1) 1)) -(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp1 1))) (set avcc3CRq (subword SI tmp1 1)) -(if (lt (ext SI avcc3CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcc3CRq (neg (subword SI tmp0 1))) -(set avcc3CRq avcc3CRq) -) -) -) -) -) - ()) -(dncpi cclipiu_avc_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu")) - "cclipiu $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x5) (f-avc-c3sub4u16 #x5) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcc3Imm5u24) (ext SI 0)) (set avcc3CRq 0) -(sequence() (set tmp0 (sub (sll 1 avcc3Imm5u24) 1)) -(if (gt (ext SI avcc3CRq) (ext SI (subword SI tmp0 1))) (set avcc3CRq (subword SI tmp0 1)) -(if (lt (ext SI avcc3CRq) (ext SI 0)) (set avcc3CRq 0) -(set avcc3CRq avcc3CRq) -) -) -) -) -) - ()) -(dncpi cor_avc_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor")) - "cor $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (or avcc3CRq avcc3CRp)) -) - ()) -(dncpi cand_avc_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand")) - "cand $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (and avcc3CRq avcc3CRp)) -) - ()) -(dncpi cxor_avc_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor")) - "cxor $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (xor avcc3CRq avcc3CRp)) -) - ()) -(dncpi cnor_avc_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor")) - "cnor $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (inv (or avcc3CRq avcc3CRp))) -) - ()) -(dncpi csra_avc_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra")) - "csra $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sra avcc3CRq (and QI (srl avcc3CRp 0) #x1f))) -) - ()) -(dncpi csrl_avc_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl")) - "csrl $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (srl avcc3CRq (and QI (srl avcc3CRp 0) #x1f))) -) - ()) -(dncpi csll_avc_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll")) - "csll $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sll avcc3CRq (and QI (srl avcc3CRp 0) #x1f))) -) - ()) -(dncpi csrai_avc_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai")) - "csrai $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x2) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sra avcc3CRq avcc3Imm5u24)) -) - ()) -(dncpi csrli_avc_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli")) - "csrli $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x3) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (srl avcc3CRq avcc3Imm5u24)) -) - ()) -(dncpi cslli_avc_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli")) - "cslli $avcc3CRq,$avcc3Imm5u24" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3Imm5u24 (f-avc-c3sub3u29 #x6) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (sll avcc3CRq avcc3Imm5u24)) -) - ()) -(dncpi cfsft_avc_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft")) - "cfsft $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x0) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avcc3CRq)) 32) (zext DI avcc3CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta0_avc_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0")) - "cfsfta0 $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta1_avc_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1")) - "cfsfta1 $avcc3CRq" -(+ MAJ_15 (f-sub4 7) avcc3CRq (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u16 #x1) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcc3CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cmula0_avc_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0")) - "cmula0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat0)) (c-call "check_option_cp" pc) -(set concat0 (mul (ext DI avcc3CRq) (ext DI avcc3CRp))) -(set avccopCCR2 (subword SI concat0 0)) -(set avccopCCR3 (subword SI concat0 1)) -) - ()) -(dncpi cmulua0_avc_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0")) - "cmulua0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat1)) (c-call "check_option_cp" pc) -(set concat1 (mul (zext DI avcc3CRq) (zext DI avcc3CRp))) -(set avccopCCR2 (subword SI concat1 0)) -(set avccopCCR3 (subword SI concat1 1)) -) - ()) -(dncpi cnmula0_avc_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0")) - "cnmula0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat2)) (c-call "check_option_cp" pc) -(set concat2 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat2 0)) -(set avccopCCR3 (subword SI concat2 1)) -) - ()) -(dncpi cmada0_avc_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0")) - "cmada0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat3)) (c-call "check_option_cp" pc) -(set concat3 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat3 0)) -(set avccopCCR3 (subword SI concat3 1)) -) - ()) -(dncpi cmadua0_avc_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0")) - "cmadua0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat4)) (c-call "check_option_cp" pc) -(set concat4 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat4 0)) -(set avccopCCR3 (subword SI concat4 1)) -) - ()) -(dncpi cmsba0_avc_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0")) - "cmsba0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat5)) (c-call "check_option_cp" pc) -(set concat5 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat5 0)) -(set avccopCCR3 (subword SI concat5 1)) -) - ()) -(dncpi cmsbua0_avc_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0")) - "cmsbua0 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat6)) (c-call "check_option_cp" pc) -(set concat6 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR2 (subword SI concat6 0)) -(set avccopCCR3 (subword SI concat6 1)) -) - ()) -(dncpi cmula1_avc_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1")) - "cmula1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat7)) (c-call "check_option_cp" pc) -(set concat7 (mul (ext DI avcc3CRq) (ext DI avcc3CRp))) -(set avccopCCR4 (subword SI concat7 0)) -(set avccopCCR5 (subword SI concat7 1)) -) - ()) -(dncpi cmulua1_avc_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1")) - "cmulua1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat8)) (c-call "check_option_cp" pc) -(set concat8 (mul (zext DI avcc3CRq) (zext DI avcc3CRp))) -(set avccopCCR4 (subword SI concat8 0)) -(set avccopCCR5 (subword SI concat8 1)) -) - ()) -(dncpi cnmula1_avc_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1")) - "cnmula1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat9)) (c-call "check_option_cp" pc) -(set concat9 (neg (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat9 0)) -(set avccopCCR5 (subword SI concat9 1)) -) - ()) -(dncpi cmada1_avc_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1")) - "cmada1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat10)) (c-call "check_option_cp" pc) -(set concat10 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat10 0)) -(set avccopCCR5 (subword SI concat10 1)) -) - ()) -(dncpi cmadua1_avc_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1")) - "cmadua1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat11)) (c-call "check_option_cp" pc) -(set concat11 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat11 0)) -(set avccopCCR5 (subword SI concat11 1)) -) - ()) -(dncpi cmsba1_avc_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1")) - "cmsba1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat12)) (c-call "check_option_cp" pc) -(set concat12 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3CRq) (ext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat12 0)) -(set avccopCCR5 (subword SI concat12 1)) -) - ()) -(dncpi cmsbua1_avc_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1")) - "cmsbua1 $avcc3CRq,$avcc3CRp" -(+ MAJ_15 (f-sub4 7) avcc3CRq avcc3CRp (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u16 #x4) (f-avc-c3sub4u8 #x0) (f-avc-c3sub4u4 #x0)) -(sequence((DI concat13)) (c-call "check_option_cp" pc) -(set concat13 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3CRq) (zext DI avcc3CRp)))) -(set avccopCCR4 (subword SI concat13 0)) -(set avccopCCR5 (subword SI concat13 1)) -) - ()) -(dncpi xmula0_avc_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0")) - "xmula0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x0) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat14)) (c-call "check_option_cp" pc) -(set concat14 (mul (ext DI avcc3Rn) (ext DI avcc3Rm))) -(set avccopCCR2 (subword SI concat14 0)) -(set avccopCCR3 (subword SI concat14 1)) -) - ()) -(dncpi xmulua0_avc_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0")) - "xmulua0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x1) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat15)) (c-call "check_option_cp" pc) -(set concat15 (mul (zext DI avcc3Rn) (zext DI avcc3Rm))) -(set avccopCCR2 (subword SI concat15 0)) -(set avccopCCR3 (subword SI concat15 1)) -) - ()) -(dncpi xnmula0_avc_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0")) - "xnmula0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x2) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat16)) (c-call "check_option_cp" pc) -(set concat16 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat16 0)) -(set avccopCCR3 (subword SI concat16 1)) -) - ()) -(dncpi xmada0_avc_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0")) - "xmada0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x4) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat17)) (c-call "check_option_cp" pc) -(set concat17 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat17 0)) -(set avccopCCR3 (subword SI concat17 1)) -) - ()) -(dncpi xmadua0_avc_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0")) - "xmadua0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x5) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat18)) (c-call "check_option_cp" pc) -(set concat18 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat18 0)) -(set avccopCCR3 (subword SI concat18 1)) -) - ()) -(dncpi xmsba0_avc_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0")) - "xmsba0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x6) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat19)) (c-call "check_option_cp" pc) -(set concat19 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat19 0)) -(set avccopCCR3 (subword SI concat19 1)) -) - ()) -(dncpi xmsbua0_avc_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x7) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat20)) (c-call "check_option_cp" pc) -(set concat20 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR2 (subword SI concat20 0)) -(set avccopCCR3 (subword SI concat20 1)) -) - ()) -(dncpi xmula1_avc_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1")) - "xmula1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x8) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat21)) (c-call "check_option_cp" pc) -(set concat21 (mul (ext DI avcc3Rn) (ext DI avcc3Rm))) -(set avccopCCR4 (subword SI concat21 0)) -(set avccopCCR5 (subword SI concat21 1)) -) - ()) -(dncpi xmulua1_avc_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1")) - "xmulua1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #x9) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat22)) (c-call "check_option_cp" pc) -(set concat22 (mul (zext DI avcc3Rn) (zext DI avcc3Rm))) -(set avccopCCR4 (subword SI concat22 0)) -(set avccopCCR5 (subword SI concat22 1)) -) - ()) -(dncpi xnmula1_avc_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1")) - "xnmula1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xa) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat23)) (c-call "check_option_cp" pc) -(set concat23 (neg (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat23 0)) -(set avccopCCR5 (subword SI concat23 1)) -) - ()) -(dncpi xmada1_avc_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1")) - "xmada1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xc) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat24)) (c-call "check_option_cp" pc) -(set concat24 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat24 0)) -(set avccopCCR5 (subword SI concat24 1)) -) - ()) -(dncpi xmadua1_avc_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1")) - "xmadua1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xd) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat25)) (c-call "check_option_cp" pc) -(set concat25 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat25 0)) -(set avccopCCR5 (subword SI concat25 1)) -) - ()) -(dncpi xmsba1_avc_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1")) - "xmsba1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xe) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat26)) (c-call "check_option_cp" pc) -(set concat26 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcc3Rn) (ext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat26 0)) -(set avccopCCR5 (subword SI concat26 1)) -) - ()) -(dncpi xmsbua1_avc_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avcc3Rn,$avcc3Rm" -(+ MAJ_15 (f-sub4 7) avcc3Rn avcc3Rm (f-avc-c3sub4u28 #xf) (f-avc-c3sub4u24 #x0) (f-avc-c3sub4u20 #x0) (f-avc-c3sub4u16 #xc)) -(sequence((DI concat27)) (c-call "check_option_cp" pc) -(set concat27 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcc3Rn) (zext DI avcc3Rm)))) -(set avccopCCR4 (subword SI concat27 0)) -(set avccopCCR5 (subword SI concat27 1)) -) - ()) -(dn16i cnop_avc_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop")) - "cnop" -(+ (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u4 #x0) (f-avc-v1sub4u0 #x0)) -(c-call "check_option_cp" pc) - ()) -(dnmi cpnop16_avc_v1 "cpnop16" -(avc-16-isa NO-DIS) -"cpnop16" -(emit cnop_avc_v1) -) -(dn16i cmov_avc_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov")) - "cmov $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq avcv1CRp) -) - ()) -(dn16i cmovi_avc_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi")) - "cmovi $avcv1CRq,$avcv1Imm8s8" -(+ avcv1CRq avcv1Imm8s8 (f-avc-v1sub4u0 #x2)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (ext SI avcv1Imm8s8)) -) - ()) -(dn16i cadd3_avc_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3")) - "cadd3 $avcv1CRo,$avcv1CRq,$avcv1CRp" -(+ avcv1CRo avcv1CRq avcv1CRp (f-avc-v1sub4u0 #x3)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRo (add avcv1CRq avcv1CRp)) -) - ()) -(dn16i caddi_avc_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi")) - "caddi $avcv1CRq,$avcv1Imm6s8" -(+ avcv1CRq avcv1Imm6s8 (f-avc-v1sub2u14 #x0) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (add avcv1CRq (ext SI avcv1Imm6s8))) -) - ()) -(dn16i csub_avc_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub")) - "csub $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sub avcv1CRq avcv1CRp)) -) - ()) -(dn16i cneg_avc_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg")) - "cneg $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (neg avcv1CRp)) -) - ()) -(dn16i cextb_avc_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb")) - "cextb $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (ext SI (and QI (srl avcv1CRq 0) #xff))) -) - ()) -(dn16i cexth_avc_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth")) - "cexth $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x2) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (ext SI (and HI (srl avcv1CRq 0) #xffff))) -) - ()) -(dn16i cextub_avc_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub")) - "cextub $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #x8) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (zext SI (and QI (srl avcv1CRq 0) #xff))) -) - ()) -(dn16i cextuh_avc_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh")) - "cextuh $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (zext SI (and HI (srl avcv1CRq 0) #xffff))) -) - ()) -(dn16i cscltz_avc_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz")) - "cscltz $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u8 #xa) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avccopCCR1 (or (sll (srl avccopCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dn16i cldz_avc_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz")) - "cldz $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (and avcv1CRp #x80000000) (set avcv1CRq 0) -(if (and avcv1CRp #x40000000) (set avcv1CRq 1) -(if (and avcv1CRp #x20000000) (set avcv1CRq 2) -(if (and avcv1CRp #x10000000) (set avcv1CRq 3) -(if (and avcv1CRp #x8000000) (set avcv1CRq 4) -(if (and avcv1CRp #x4000000) (set avcv1CRq 5) -(if (and avcv1CRp #x2000000) (set avcv1CRq 6) -(if (and avcv1CRp #x1000000) (set avcv1CRq 7) -(if (and avcv1CRp #x800000) (set avcv1CRq 8) -(if (and avcv1CRp #x400000) (set avcv1CRq 9) -(if (and avcv1CRp #x200000) (set avcv1CRq 10) -(if (and avcv1CRp #x100000) (set avcv1CRq 11) -(if (and avcv1CRp #x80000) (set avcv1CRq 12) -(if (and avcv1CRp #x40000) (set avcv1CRq 13) -(if (and avcv1CRp #x20000) (set avcv1CRq 14) -(if (and avcv1CRp #x10000) (set avcv1CRq 15) -(if (and avcv1CRp #x8000) (set avcv1CRq 16) -(if (and avcv1CRp #x4000) (set avcv1CRq 17) -(if (and avcv1CRp #x2000) (set avcv1CRq 18) -(if (and avcv1CRp #x1000) (set avcv1CRq 19) -(if (and avcv1CRp #x800) (set avcv1CRq 20) -(if (and avcv1CRp #x400) (set avcv1CRq 21) -(if (and avcv1CRp #x200) (set avcv1CRq 22) -(if (and avcv1CRp #x100) (set avcv1CRq 23) -(if (and avcv1CRp #x80) (set avcv1CRq 24) -(if (and avcv1CRp #x40) (set avcv1CRq 25) -(if (and avcv1CRp #x20) (set avcv1CRq 26) -(if (and avcv1CRp #x10) (set avcv1CRq 27) -(if (and avcv1CRp #x8) (set avcv1CRq 28) -(if (and avcv1CRp #x4) (set avcv1CRq 29) -(if (and avcv1CRp #x2) (set avcv1CRq 30) -(if (and avcv1CRp #x1) (set avcv1CRq 31) -(set avcv1CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dn16i cabs_avc_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs")) - "cabs $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x3) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (abs (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1)))) -) - ()) -(dn16i cad1s_avc_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s")) - "cad1s $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (add avcv1CRq avcv1CRp) 1))) -(set avcv1CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dn16i csb1s_avc_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s")) - "csb1s $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (ext SI (subword SI (sub avcv1CRq avcv1CRp) 1))) -(set avcv1CRq (subword SI (sra tmp0 1) 1)) -) - ()) -(dn16i cmin_avc_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin")) - "cmin $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cmax_avc_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax")) - "cmax $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avcv1CRq) (ext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cminu_avc_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu")) - "cminu $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cmaxu_avc_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu")) - "cmaxu $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xb) (f-avc-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avcv1CRq) (zext SI avcv1CRp)) (set avcv1CRq avcv1CRq) -(set avcv1CRq avcv1CRp) -) -) - ()) -(dn16i cclipi_avc_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi")) - "cclipi $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x4) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp1)(DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0) -(sequence() (set tmp0 (sll 1 (sub avcv1Imm5u8 1))) -(set tmp1 (sub (subword SI tmp0 1) 1)) -(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp1 1))) (set avcv1CRq (subword SI tmp1 1)) -(if (lt (ext SI avcv1CRq) (ext SI (neg (subword SI tmp0 1)))) (set avcv1CRq (neg (subword SI tmp0 1))) -(set avcv1CRq avcv1CRq) -) -) -) -) -) - ()) -(dn16i cclipiu_avc_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu")) - "cclipiu $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x5) (f-avc-v1sub4u0 #x5)) -(sequence((DI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avcv1Imm5u8) (ext SI 0)) (set avcv1CRq 0) -(sequence() (set tmp0 (sub (sll 1 avcv1Imm5u8) 1)) -(if (gt (ext SI avcv1CRq) (ext SI (subword SI tmp0 1))) (set avcv1CRq (subword SI tmp0 1)) -(if (lt (ext SI avcv1CRq) (ext SI 0)) (set avcv1CRq 0) -(set avcv1CRq avcv1CRq) -) -) -) -) -) - ()) -(dn16i cor_avc_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor")) - "cor $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (or avcv1CRq avcv1CRp)) -) - ()) -(dn16i cand_avc_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand")) - "cand $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (and avcv1CRq avcv1CRp)) -) - ()) -(dn16i cxor_avc_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor")) - "cxor $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (xor avcv1CRq avcv1CRp)) -) - ()) -(dn16i cnor_avc_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor")) - "cnor $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (inv (or avcv1CRq avcv1CRp))) -) - ()) -(dn16i csra_avc_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra")) - "csra $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sra avcv1CRq (and QI (srl avcv1CRp 0) #x1f))) -) - ()) -(dn16i csrl_avc_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl")) - "csrl $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (srl avcv1CRq (and QI (srl avcv1CRp 0) #x1f))) -) - ()) -(dn16i csll_avc_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll")) - "csll $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sll avcv1CRq (and QI (srl avcv1CRp 0) #x1f))) -) - ()) -(dn16i csrai_avc_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai")) - "csrai $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x2) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sra avcv1CRq avcv1Imm5u8)) -) - ()) -(dn16i csrli_avc_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli")) - "csrli $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x3) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (srl avcv1CRq avcv1Imm5u8)) -) - ()) -(dn16i cslli_avc_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli")) - "cslli $avcv1CRq,$avcv1Imm5u8" -(+ avcv1CRq avcv1Imm5u8 (f-avc-v1sub3u13 #x6) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (sll avcv1CRq avcv1Imm5u8)) -) - ()) -(dn16i cfsft_avc_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft")) - "cfsft $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avcv1CRq)) 32) (zext DI avcv1CRp)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta0_avc_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0")) - "cfsfta0 $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta1_avc_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1")) - "cfsfta1 $avcv1CRq" -(+ avcv1CRq (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u8 #x0) (f-avc-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avcv1CRq (subword SI (sll (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (and QI (srl avccopCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cmula0_avc_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0")) - "cmula0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x0) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat28)) (c-call "check_option_cp" pc) -(set concat28 (mul (ext DI avcv1CRq) (ext DI avcv1CRp))) -(set avccopCCR2 (subword SI concat28 0)) -(set avccopCCR3 (subword SI concat28 1)) -) - ()) -(dn16i cmulua0_avc_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0")) - "cmulua0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x1) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat29)) (c-call "check_option_cp" pc) -(set concat29 (mul (zext DI avcv1CRq) (zext DI avcv1CRp))) -(set avccopCCR2 (subword SI concat29 0)) -(set avccopCCR3 (subword SI concat29 1)) -) - ()) -(dn16i cnmula0_avc_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0")) - "cnmula0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x2) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat30)) (c-call "check_option_cp" pc) -(set concat30 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat30 0)) -(set avccopCCR3 (subword SI concat30 1)) -) - ()) -(dn16i cmada0_avc_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0")) - "cmada0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x4) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat31)) (c-call "check_option_cp" pc) -(set concat31 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat31 0)) -(set avccopCCR3 (subword SI concat31 1)) -) - ()) -(dn16i cmadua0_avc_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0")) - "cmadua0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x5) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat32)) (c-call "check_option_cp" pc) -(set concat32 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat32 0)) -(set avccopCCR3 (subword SI concat32 1)) -) - ()) -(dn16i cmsba0_avc_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0")) - "cmsba0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x6) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat33)) (c-call "check_option_cp" pc) -(set concat33 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat33 0)) -(set avccopCCR3 (subword SI concat33 1)) -) - ()) -(dn16i cmsbua0_avc_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0")) - "cmsbua0 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x7) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat34)) (c-call "check_option_cp" pc) -(set concat34 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR2 (subword SI concat34 0)) -(set avccopCCR3 (subword SI concat34 1)) -) - ()) -(dn16i cmula1_avc_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1")) - "cmula1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x8) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat35)) (c-call "check_option_cp" pc) -(set concat35 (mul (ext DI avcv1CRq) (ext DI avcv1CRp))) -(set avccopCCR4 (subword SI concat35 0)) -(set avccopCCR5 (subword SI concat35 1)) -) - ()) -(dn16i cmulua1_avc_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1")) - "cmulua1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #x9) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat36)) (c-call "check_option_cp" pc) -(set concat36 (mul (zext DI avcv1CRq) (zext DI avcv1CRp))) -(set avccopCCR4 (subword SI concat36 0)) -(set avccopCCR5 (subword SI concat36 1)) -) - ()) -(dn16i cnmula1_avc_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1")) - "cnmula1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xa) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat37)) (c-call "check_option_cp" pc) -(set concat37 (neg (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat37 0)) -(set avccopCCR5 (subword SI concat37 1)) -) - ()) -(dn16i cmada1_avc_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1")) - "cmada1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xc) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat38)) (c-call "check_option_cp" pc) -(set concat38 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat38 0)) -(set avccopCCR5 (subword SI concat38 1)) -) - ()) -(dn16i cmadua1_avc_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1")) - "cmadua1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xd) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat39)) (c-call "check_option_cp" pc) -(set concat39 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat39 0)) -(set avccopCCR5 (subword SI concat39 1)) -) - ()) -(dn16i cmsba1_avc_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1")) - "cmsba1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xe) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat40)) (c-call "check_option_cp" pc) -(set concat40 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv1CRq) (ext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat40 0)) -(set avccopCCR5 (subword SI concat40 1)) -) - ()) -(dn16i cmsbua1_avc_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1")) - "cmsbua1 $avcv1CRq,$avcv1CRp" -(+ avcv1CRq avcv1CRp (f-avc-v1sub4u12 #xf) (f-avc-v1sub4u0 #x4)) -(sequence((DI concat41)) (c-call "check_option_cp" pc) -(set concat41 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv1CRq) (zext DI avcv1CRp)))) -(set avccopCCR4 (subword SI concat41 0)) -(set avccopCCR5 (subword SI concat41 1)) -) - ()) -(dn32i cmov1_avc_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1")) - "cmov $avcv3CRn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3CRn avcv3Rm) -) - ()) -(dn32i cmov2_avc_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2")) - "cmov $avcv3Rm,$avcv3CRn" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CRn (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3Rm avcv3CRn) -) - ()) -(dn32i cmovi_avc_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi")) - "cmovi $avcv3CRq,$avcv3Imm16s4x24e32" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CRq avcv3Imm16s4x24e32 (f-avc-v3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3CRq (ext SI avcv3Imm16s4x24e32)) -) - ()) -(dn32i cmovc1_avc_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1")) - "cmovc $avcv3CCRn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3CCRn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3CCRn avcv3Rm) -) - ()) -(dn32i cmovc2_avc_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2")) - "cmovc $avcv3Rm,$avcv3CCRn" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rm avcv3CCRn (f-avc-v3sub4u28 #x3) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avcv3Rm avcv3CCRn) -) - ()) -(dn32i xmula0_avc_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0")) - "xmula0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x0) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat42)) (c-call "check_option_cp" pc) -(set concat42 (mul (ext DI avcv3Rn) (ext DI avcv3Rm))) -(set avccopCCR2 (subword SI concat42 0)) -(set avccopCCR3 (subword SI concat42 1)) -) - ()) -(dn32i xmulua0_avc_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0")) - "xmulua0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x1) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat43)) (c-call "check_option_cp" pc) -(set concat43 (mul (zext DI avcv3Rn) (zext DI avcv3Rm))) -(set avccopCCR2 (subword SI concat43 0)) -(set avccopCCR3 (subword SI concat43 1)) -) - ()) -(dn32i xnmula0_avc_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0")) - "xnmula0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x2) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat44)) (c-call "check_option_cp" pc) -(set concat44 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat44 0)) -(set avccopCCR3 (subword SI concat44 1)) -) - ()) -(dn32i xmada0_avc_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0")) - "xmada0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x4) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat45)) (c-call "check_option_cp" pc) -(set concat45 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat45 0)) -(set avccopCCR3 (subword SI concat45 1)) -) - ()) -(dn32i xmadua0_avc_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0")) - "xmadua0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x5) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat46)) (c-call "check_option_cp" pc) -(set concat46 (add (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat46 0)) -(set avccopCCR3 (subword SI concat46 1)) -) - ()) -(dn32i xmsba0_avc_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0")) - "xmsba0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x6) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat47)) (c-call "check_option_cp" pc) -(set concat47 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat47 0)) -(set avccopCCR3 (subword SI concat47 1)) -) - ()) -(dn32i xmsbua0_avc_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x7) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat48)) (c-call "check_option_cp" pc) -(set concat48 (sub (or (sll (zext DI (zext SI avccopCCR2)) 32) (zext DI avccopCCR3)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR2 (subword SI concat48 0)) -(set avccopCCR3 (subword SI concat48 1)) -) - ()) -(dn32i xmula1_avc_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1")) - "xmula1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x8) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat49)) (c-call "check_option_cp" pc) -(set concat49 (mul (ext DI avcv3Rn) (ext DI avcv3Rm))) -(set avccopCCR4 (subword SI concat49 0)) -(set avccopCCR5 (subword SI concat49 1)) -) - ()) -(dn32i xmulua1_avc_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1")) - "xmulua1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #x9) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat50)) (c-call "check_option_cp" pc) -(set concat50 (mul (zext DI avcv3Rn) (zext DI avcv3Rm))) -(set avccopCCR4 (subword SI concat50 0)) -(set avccopCCR5 (subword SI concat50 1)) -) - ()) -(dn32i xnmula1_avc_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1")) - "xnmula1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xa) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat51)) (c-call "check_option_cp" pc) -(set concat51 (neg (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat51 0)) -(set avccopCCR5 (subword SI concat51 1)) -) - ()) -(dn32i xmada1_avc_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1")) - "xmada1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xc) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat52)) (c-call "check_option_cp" pc) -(set concat52 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat52 0)) -(set avccopCCR5 (subword SI concat52 1)) -) - ()) -(dn32i xmadua1_avc_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1")) - "xmadua1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xd) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat53)) (c-call "check_option_cp" pc) -(set concat53 (add (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat53 0)) -(set avccopCCR5 (subword SI concat53 1)) -) - ()) -(dn32i xmsba1_avc_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1")) - "xmsba1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xe) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat54)) (c-call "check_option_cp" pc) -(set concat54 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (ext DI avcv3Rn) (ext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat54 0)) -(set avccopCCR5 (subword SI concat54 1)) -) - ()) -(dn32i xmsbua1_avc_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avcv3Rn,$avcv3Rm" -(+ (f-avc-v3sub4u0 #xf) (f-avc-v3sub4u12 #x7) avcv3Rn avcv3Rm (f-avc-v3sub4u28 #xf) (f-avc-v3sub4u24 #x0) (f-avc-v3sub4u20 #x0) (f-avc-v3sub4u16 #xc)) -(sequence((DI concat55)) (c-call "check_option_cp" pc) -(set concat55 (sub (or (sll (zext DI (zext SI avccopCCR4)) 32) (zext DI avccopCCR5)) (mul (zext DI avcv3Rn) (zext DI avcv3Rm)))) -(set avccopCCR4 (subword SI concat55 0)) -(set avccopCCR5 (subword SI concat55 1)) -) - ()) diff --git a/binutils-2.24/cpu/mep-avc2.cpu b/binutils-2.24/cpu/mep-avc2.cpu deleted file mode 100644 index 8de05d16..00000000 --- a/binutils-2.24/cpu/mep-avc2.cpu +++ /dev/null @@ -1,1987 +0,0 @@ -; Toshiba MeP AVC2 Coprocessor description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; This file was customized based upon the output of a2cgen 0.42 - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; This coprocessor requires 16 and 32 bit insns. -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro avc2-core-isa () (ISA ext_core1)) -(define-pmacro avc2-16-isa () (ISA ext_cop1_16)) -(define-pmacro avc2-32-isa () (ISA ext_cop1_32)) -(define-pmacro all-avc2-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32)) -; end-isas - -(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc2-core-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn16i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc2-16-isa) xsyntax xformat xsemantics xtiming)) -(define-pmacro (dn32i xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni xname xcomment (.splice (.unsplice xattrs) avc2-32-isa) xsyntax xformat xsemantics xtiming)) - -; register definitions -; --------------------- -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-avc2) - (comment "32-bit coprocessor registers for avc2 coprocessor") - (attrs VIRTUAL all-avc2-isas) - (type register SI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) - (indices keyword "$c" (.map -reg-pair (.iota 8))) -) -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-avc2) - (comment "Coprocessor control registers for avc2 coprocessor") - (attrs VIRTUAL all-avc2-isas) - (type register SI (64)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) - (indices keyword "" - (.splice - ($accl1 5) ($acch1 4) ($accl0 3) ($acch0 2) ($CBCR 1) ($csar 0) - ($cbcr 1) - (.unsplice (.map -ccr-reg-pair (.iota 6))) - ) - ) -) -(dnop avc2copCCR5 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 5) -(dnop avc2copCCR4 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 4) -(dnop avc2copCCR3 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 3) -(dnop avc2copCCR2 "Audio Copro Accumulator" (all-avc2-isas) h-ccr 2) -(dnop avc2copCCR1 "Audio Copro Branch Condition Register" (all-avc2-isas) h-ccr 1) -(dnop avc2copCCR0 "Audio Copro Shift-Amount Register" (all-avc2-isas) h-ccr 0) - -; instruction field and operand definitions -(dnf f-avc2-v3sub4u0 "sub opecode field" (avc2-32-isa) 0 4) -(dnf f-avc2-v1sub4u0 "sub opecode field" (avc2-16-isa) 0 4) -(dnf f-avc2-v3Rn "register field" (avc2-32-isa) 4 4) -(dnop avc2v3Rn "the operand definition" (avc2-32-isa) h-gpr f-avc2-v3Rn) -(dnf f-avc2-v3CCRn "register field" (avc2-32-isa) 4 4) -(define-full-operand avc2v3CCRn "the operand definition" (avc2-32-isa (CDATA REGNUM)) h-ccr DFLT f-avc2-v3CCRn ((parse "avc2_ccr") (print "avc2_ccr")) () ()) -(df f-avc2-v3Imm16s4x24e32-hi "split immediate field hi" (avc2-32-isa) 4 8 INT #f #f) -(df f-avc2-v3Imm16s4x24e32-lo "split immediate field lo" (avc2-32-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc2-v3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc2-32-isa) - (mode INT) - (subfields f-avc2-v3Imm16s4x24e32-hi f-avc2-v3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc2-v3Imm16s4x24e32-hi) (sra INT (ifield f-avc2-v3Imm16s4x24e32) 8)) - (set (ifield f-avc2-v3Imm16s4x24e32-lo) (and (ifield f-avc2-v3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc2-v3Imm16s4x24e32) - (or (sll (ifield f-avc2-v3Imm16s4x24e32-hi) 8) (ifield f-avc2-v3Imm16s4x24e32-lo)))) - ) -(dnop avc2v3Imm16s4x24e32 "the operand definition" (avc2-32-isa) h-sint f-avc2-v3Imm16s4x24e32) -(dnf f-avc2-v3CRn "register field" (avc2-32-isa) 4 4) -(define-full-operand avc2v3CRn "the operand definition" (avc2-32-isa) h-cr DFLT f-avc2-v3CRn ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1CRq "register field" (avc2-16-isa) 4 4) -(define-full-operand avc2v1CRq "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRq ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1sub4u4 "sub opecode field" (avc2-16-isa) 4 4) -(dnf f-avc2-c3Rn "register field" (avc2-core-isa) 4 4) -(dnop avc2c3Rn "the operand definition" (avc2-core-isa) h-gpr f-avc2-c3Rn) -(dnf f-avc2-c3CCRn "register field" (avc2-core-isa) 4 4) -(define-full-operand avc2c3CCRn "the operand definition" (avc2-core-isa (CDATA REGNUM)) h-ccr DFLT f-avc2-c3CCRn ((parse "avc2_ccr") (print "avc2_ccr")) () ()) -(df f-avc2-c3Imm16s4x24e32-hi "split immediate field hi" (avc2-core-isa) 4 8 INT #f #f) -(df f-avc2-c3Imm16s4x24e32-lo "split immediate field lo" (avc2-core-isa) 24 8 UINT #f #f) -(define-multi-ifield - (name f-avc2-c3Imm16s4x24e32) - (comment "split immediate field") - (attrs avc2-core-isa) - (mode INT) - (subfields f-avc2-c3Imm16s4x24e32-hi f-avc2-c3Imm16s4x24e32-lo) - (insert (sequence () - (set (ifield f-avc2-c3Imm16s4x24e32-hi) (sra INT (ifield f-avc2-c3Imm16s4x24e32) 8)) - (set (ifield f-avc2-c3Imm16s4x24e32-lo) (and (ifield f-avc2-c3Imm16s4x24e32) #xff)))) - (extract (set (ifield f-avc2-c3Imm16s4x24e32) - (or (sll (ifield f-avc2-c3Imm16s4x24e32-hi) 8) (ifield f-avc2-c3Imm16s4x24e32-lo)))) - ) -(dnop avc2c3Imm16s4x24e32 "the operand definition" (avc2-core-isa) h-sint f-avc2-c3Imm16s4x24e32) -(dnf f-avc2-c3CRn "register field" (avc2-core-isa) 4 4) -(define-full-operand avc2c3CRn "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRn ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u4 "sub opecode field" (avc2-core-isa) 4 4) -(dnf f-avc2-v3Rm "register field" (avc2-32-isa) 8 4) -(dnop avc2v3Rm "the operand definition" (avc2-32-isa) h-gpr f-avc2-v3Rm) -(df f-avc2-v1Imm6u8 "immediate field" (avc2-16-isa) 8 6 UINT #f #f) -(dnop avc2v1Imm6u8 "the operand definition" (avc2-16-isa) h-uint f-avc2-v1Imm6u8) -(df f-avc2-v1Imm5u8 "immediate field" (avc2-16-isa) 8 5 UINT #f #f) -(dnop avc2v1Imm5u8 "the operand definition" (avc2-16-isa) h-uint f-avc2-v1Imm5u8) -(df f-avc2-v1Imm6s8 "immediate field" (avc2-16-isa) 8 6 INT #f #f) -(dnop avc2v1Imm6s8 "the operand definition" (avc2-16-isa) h-sint f-avc2-v1Imm6s8) -(df f-avc2-v1Imm8s8 "immediate field" (avc2-16-isa) 8 8 INT #f #f) -(dnop avc2v1Imm8s8 "the operand definition" (avc2-16-isa) h-sint f-avc2-v1Imm8s8) -(dnf f-avc2-v1CRp "register field" (avc2-16-isa) 8 4) -(define-full-operand avc2v1CRp "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRp ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1sub4u8 "sub opecode field" (avc2-16-isa) 8 4) -(dnf f-avc2-c3Rm "register field" (avc2-core-isa) 8 4) -(dnop avc2c3Rm "the operand definition" (avc2-core-isa) h-gpr f-avc2-c3Rm) -(dnf f-avc2-c3sub4u8 "sub opecode field" (avc2-core-isa) 8 4) -(dnf f-avc2-v3sub4u12 "sub opecode field" (avc2-32-isa) 12 4) -(dnf f-avc2-v1CRo "register field" (avc2-16-isa) 12 4) -(define-full-operand avc2v1CRo "the operand definition" (avc2-16-isa) h-cr DFLT f-avc2-v1CRo ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v1sub4u12 "sub opecode field" (avc2-16-isa) 12 4) -(dnf f-avc2-v1sub3u13 "sub opecode field" (avc2-16-isa) 13 3) -(dnf f-avc2-v1sub2u14 "sub opecode field" (avc2-16-isa) 14 2) -(dnf f-avc2-v3sub4u16 "sub opecode field" (avc2-32-isa) 16 4) -(dnf f-avc2-c3sub4u16 "sub opecode field" (avc2-core-isa) 16 4) -(dnf f-avc2-v3CRq "register field" (avc2-32-isa) 20 4) -(define-full-operand avc2v3CRq "the operand definition" (avc2-32-isa) h-cr DFLT f-avc2-v3CRq ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-v3sub4u20 "sub opecode field" (avc2-32-isa) 20 4) -(dnf f-avc2-c3CRq "register field" (avc2-core-isa) 20 4) -(define-full-operand avc2c3CRq "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRq ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u20 "sub opecode field" (avc2-core-isa) 20 4) -(dnf f-avc2-v3sub4u24 "sub opecode field" (avc2-32-isa) 24 4) -(df f-avc2-c3Imm6u24 "immediate field" (avc2-core-isa) 24 6 UINT #f #f) -(dnop avc2c3Imm6u24 "the operand definition" (avc2-core-isa) h-uint f-avc2-c3Imm6u24) -(df f-avc2-c3Imm5u24 "immediate field" (avc2-core-isa) 24 5 UINT #f #f) -(dnop avc2c3Imm5u24 "the operand definition" (avc2-core-isa) h-uint f-avc2-c3Imm5u24) -(df f-avc2-c3Imm6s24 "immediate field" (avc2-core-isa) 24 6 INT #f #f) -(dnop avc2c3Imm6s24 "the operand definition" (avc2-core-isa) h-sint f-avc2-c3Imm6s24) -(dnf f-avc2-c3CRp "register field" (avc2-core-isa) 24 4) -(define-full-operand avc2c3CRp "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRp ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u24 "sub opecode field" (avc2-core-isa) 24 4) -(dnf f-avc2-v3sub4u28 "sub opecode field" (avc2-32-isa) 28 4) -(dnf f-avc2-c3CRo "register field" (avc2-core-isa) 28 4) -(define-full-operand avc2c3CRo "the operand definition" (avc2-core-isa) h-cr DFLT f-avc2-c3CRo ((parse "avc2_cr") (print "avc2_cr")) () ()) -(dnf f-avc2-c3sub4u28 "sub opecode field" (avc2-core-isa) 28 4) -(dnf f-avc2-c3sub3u29 "sub opecode field" (avc2-core-isa) 29 3) -(dnf f-avc2-c3sub2u30 "sub opecode field" (avc2-core-isa) 30 2) - -; instruction definitions -(dncpi cnop_avc2_c3 "cnop" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnop")) - "cnop" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(c-call "check_option_cp" pc) - ()) -(dncpi cmov1_avc2_c3 "cmov1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov1")) - "cmov $avc2c3CRn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3CRn avc2c3Rm (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRn avc2c3Rm) -) - ()) -(dncpi cmov2_avc2_c3 "cmov2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov2")) - "cmov $avc2c3Rm,$avc2c3CRn" -(+ MAJ_15 (f-sub4 7) avc2c3Rm avc2c3CRn (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3Rm avc2c3CRn) -) - ()) -(dncpi cmovi_avc2_c3 "cmovi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovi")) - "cmovi $avc2c3CRq,$avc2c3Imm16s4x24e32" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm16s4x24e32 (f-avc2-c3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (ext SI avc2c3Imm16s4x24e32)) -) - ()) -(dncpi cmovc1_avc2_c3 "cmovc1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc1")) - "cmovc $avc2c3CCRn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3CCRn avc2c3Rm (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CCRn avc2c3Rm) -) - ()) -(dncpi cmovc2_avc2_c3 "cmovc2" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmovc2")) - "cmovc $avc2c3Rm,$avc2c3CCRn" -(+ MAJ_15 (f-sub4 7) avc2c3Rm avc2c3CCRn (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3Rm avc2c3CCRn) -) - ()) -(dncpi cmov_avc2_c3 "cmov" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmov")) - "cmov $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq avc2c3CRp) -) - ()) -(dncpi cadd3_avc2_c3 "cadd3" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd3")) - "cadd3 $avc2c3CRo,$avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRo avc2c3CRq avc2c3CRp (f-avc2-c3sub4u16 #x3) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRo (add avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi caddi_avc2_c3 "caddi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddi")) - "caddi $avc2c3CRq,$avc2c3Imm6s24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6s24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (add avc2c3CRq (ext SI avc2c3Imm6s24))) -) - ()) -(dncpi csub_avc2_c3 "csub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub")) - "csub $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sub avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cneg_avc2_c3 "cneg" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cneg")) - "cneg $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (neg avc2c3CRp)) -) - ()) -(dncpi cextb_avc2_c3 "cextb" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextb")) - "cextb $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (ext SI (and QI (srl avc2c3CRq 0) #xff))) -) - ()) -(dncpi cexth_avc2_c3 "cexth" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cexth")) - "cexth $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x2) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (ext SI (and HI (srl avc2c3CRq 0) #xffff))) -) - ()) -(dncpi cextub_avc2_c3 "cextub" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextub")) - "cextub $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x8) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (zext SI (and QI (srl avc2c3CRq 0) #xff))) -) - ()) -(dncpi cextuh_avc2_c3 "cextuh" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cextuh")) - "cextuh $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #xa) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (zext SI (and HI (srl avc2c3CRq 0) #xffff))) -) - ()) -(dncpi cscltz_avc2_c3 "cscltz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cscltz")) - "cscltz $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u24 #xa) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dncpi cldz_avc2_c3 "cldz" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cldz")) - "cldz $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (and avc2c3CRp #x80000000) (set avc2c3CRq 0) -(if (and avc2c3CRp #x40000000) (set avc2c3CRq 1) -(if (and avc2c3CRp #x20000000) (set avc2c3CRq 2) -(if (and avc2c3CRp #x10000000) (set avc2c3CRq 3) -(if (and avc2c3CRp #x8000000) (set avc2c3CRq 4) -(if (and avc2c3CRp #x4000000) (set avc2c3CRq 5) -(if (and avc2c3CRp #x2000000) (set avc2c3CRq 6) -(if (and avc2c3CRp #x1000000) (set avc2c3CRq 7) -(if (and avc2c3CRp #x800000) (set avc2c3CRq 8) -(if (and avc2c3CRp #x400000) (set avc2c3CRq 9) -(if (and avc2c3CRp #x200000) (set avc2c3CRq 10) -(if (and avc2c3CRp #x100000) (set avc2c3CRq 11) -(if (and avc2c3CRp #x80000) (set avc2c3CRq 12) -(if (and avc2c3CRp #x40000) (set avc2c3CRq 13) -(if (and avc2c3CRp #x20000) (set avc2c3CRq 14) -(if (and avc2c3CRp #x10000) (set avc2c3CRq 15) -(if (and avc2c3CRp #x8000) (set avc2c3CRq 16) -(if (and avc2c3CRp #x4000) (set avc2c3CRq 17) -(if (and avc2c3CRp #x2000) (set avc2c3CRq 18) -(if (and avc2c3CRp #x1000) (set avc2c3CRq 19) -(if (and avc2c3CRp #x800) (set avc2c3CRq 20) -(if (and avc2c3CRp #x400) (set avc2c3CRq 21) -(if (and avc2c3CRp #x200) (set avc2c3CRq 22) -(if (and avc2c3CRp #x100) (set avc2c3CRq 23) -(if (and avc2c3CRp #x80) (set avc2c3CRq 24) -(if (and avc2c3CRp #x40) (set avc2c3CRq 25) -(if (and avc2c3CRp #x20) (set avc2c3CRq 26) -(if (and avc2c3CRp #x10) (set avc2c3CRq 27) -(if (and avc2c3CRp #x8) (set avc2c3CRq 28) -(if (and avc2c3CRp #x4) (set avc2c3CRq 29) -(if (and avc2c3CRp #x2) (set avc2c3CRq 30) -(if (and avc2c3CRp #x1) (set avc2c3CRq 31) -(set avc2c3CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dncpi cabs_avc2_c3 "cabs" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cabs")) - "cabs $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (abs (ext SI (subword SI (sub avc2c3CRq avc2c3CRp) 1)))) -) - ()) -(dncpi cad1s_avc2_c3 "cad1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cad1s")) - "cad1s $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (add avc2c3CRq avc2c3CRp) 1)) -(set avc2c3CRq (sra tmp0 1)) -) - ()) -(dncpi csb1s_avc2_c3 "csb1s" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csb1s")) - "csb1s $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (sub avc2c3CRq avc2c3CRp) 1)) -(set avc2c3CRq (sra tmp0 1)) -) - ()) -(dncpi cmin_avc2_c3 "cmin" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmin")) - "cmin $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2c3CRq) (ext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cmax_avc2_c3 "cmax" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmax")) - "cmax $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avc2c3CRq) (ext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cminu_avc2_c3 "cminu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cminu")) - "cminu $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avc2c3CRq) (zext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cmaxu_avc2_c3 "cmaxu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmaxu")) - "cmaxu $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xb) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avc2c3CRq) (zext SI avc2c3CRp)) (set avc2c3CRq avc2c3CRq) -(set avc2c3CRq avc2c3CRp) -) -) - ()) -(dncpi cclipi_avc2_c3 "cclipi" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipi")) - "cclipi $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x4) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2c3Imm5u24) (ext SI 0)) (set avc2c3CRq 0) -(sequence() (set tmp0 (sll 1 (sub avc2c3Imm5u24 1))) -(set tmp1 (sub tmp0 1)) -(if (gt (ext SI avc2c3CRq) (ext SI tmp1)) (set avc2c3CRq tmp1) -(if (lt (ext SI avc2c3CRq) (ext SI (neg tmp0))) (set avc2c3CRq (neg tmp0)) -(set avc2c3CRq avc2c3CRq) -) -) -) -) -) - ()) -(dncpi cclipiu_avc2_c3 "cclipiu" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipiu")) - "cclipiu $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x5) (f-avc2-c3sub4u16 #x5) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((SI tmp0)(SI tmp1)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2c3Imm5u24) (ext SI 0)) (set avc2c3CRq 0) -(sequence() (set tmp0 (sub (sll 1 avc2c3Imm5u24) 1)) -(if (gtu (ext SI avc2c3CRq) (zext SI tmp0)) (set avc2c3CRq tmp0) -(if (lt (ext SI avc2c3CRq) (ext SI 0)) (set avc2c3CRq 0) -(set avc2c3CRq avc2c3CRq) -) -) -) -) -) - ()) -(dncpi cor_avc2_c3 "cor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cor")) - "cor $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (or avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cand_avc2_c3 "cand" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cand")) - "cand $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (and avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cxor_avc2_c3 "cxor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cxor")) - "cxor $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (xor avc2c3CRq avc2c3CRp)) -) - ()) -(dncpi cnor_avc2_c3 "cnor" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnor")) - "cnor $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (inv (or avc2c3CRq avc2c3CRp))) -) - ()) -(dncpi csra_avc2_c3 "csra" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csra")) - "csra $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sra avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f))) -) - ()) -(dncpi csrl_avc2_c3 "csrl" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrl")) - "csrl $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (srl avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f))) -) - ()) -(dncpi csll_avc2_c3 "csll" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csll")) - "csll $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sll avc2c3CRq (and QI (srl avc2c3CRp 0) #x1f))) -) - ()) -(dncpi csrai_avc2_c3 "csrai" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrai")) - "csrai $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x2) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sra avc2c3CRq avc2c3Imm5u24)) -) - ()) -(dncpi csrli_avc2_c3 "csrli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrli")) - "csrli $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x3) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (srl avc2c3CRq avc2c3Imm5u24)) -) - ()) -(dncpi cslli_avc2_c3 "cslli" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslli")) - "cslli $avc2c3CRq,$avc2c3Imm5u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm5u24 (f-avc2-c3sub3u29 #x6) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (sll avc2c3CRq avc2c3Imm5u24)) -) - ()) -(dncpi cfsft_avc2_c3 "cfsft" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsft")) - "cfsft $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u16 #x0) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (subword SI (sll (or (sll (zext DI avc2c3CRq) 32) (zext DI avc2c3CRp)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta0_avc2_c3 "cfsfta0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta0")) - "cfsfta0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cfsfta1_avc2_c3 "cfsfta1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cfsfta1")) - "cfsfta1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x1) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2c3CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dncpi cmula0_avc2_c3 "cmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula0")) - "cmula0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat0)) (c-call "check_option_cp" pc) -(set concat0 (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat0 0)) -(set avc2copCCR3 (subword SI concat0 1)) -) - ()) -(dncpi cmulua0_avc2_c3 "cmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua0")) - "cmulua0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat1)) (c-call "check_option_cp" pc) -(set concat1 (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat1 0)) -(set avc2copCCR3 (subword SI concat1 1)) -) - ()) -(dncpi cnmula0_avc2_c3 "cnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula0")) - "cnmula0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat2)) (c-call "check_option_cp" pc) -(set concat2 (neg (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat2 0)) -(set avc2copCCR3 (subword SI concat2 1)) -) - ()) -(dncpi cmada0_avc2_c3 "cmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada0")) - "cmada0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat3)) (c-call "check_option_cp" pc) -(set concat3 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat3 0)) -(set avc2copCCR3 (subword SI concat3 1)) -) - ()) -(dncpi cmadua0_avc2_c3 "cmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua0")) - "cmadua0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat4)) (c-call "check_option_cp" pc) -(set concat4 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat4 0)) -(set avc2copCCR3 (subword SI concat4 1)) -) - ()) -(dncpi cmsba0_avc2_c3 "cmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba0")) - "cmsba0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat5)) (c-call "check_option_cp" pc) -(set concat5 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat5 0)) -(set avc2copCCR3 (subword SI concat5 1)) -) - ()) -(dncpi cmsbua0_avc2_c3 "cmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua0")) - "cmsbua0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat6)) (c-call "check_option_cp" pc) -(set concat6 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR2 (subword SI concat6 0)) -(set avc2copCCR3 (subword SI concat6 1)) -) - ()) -(dncpi cmula1_avc2_c3 "cmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmula1")) - "cmula1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat7)) (c-call "check_option_cp" pc) -(set concat7 (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat7 0)) -(set avc2copCCR5 (subword SI concat7 1)) -) - ()) -(dncpi cmulua1_avc2_c3 "cmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmulua1")) - "cmulua1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat8)) (c-call "check_option_cp" pc) -(set concat8 (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat8 0)) -(set avc2copCCR5 (subword SI concat8 1)) -) - ()) -(dncpi cnmula1_avc2_c3 "cnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cnmula1")) - "cnmula1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat9)) (c-call "check_option_cp" pc) -(set concat9 (neg (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat9 0)) -(set avc2copCCR5 (subword SI concat9 1)) -) - ()) -(dncpi cmada1_avc2_c3 "cmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmada1")) - "cmada1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat10)) (c-call "check_option_cp" pc) -(set concat10 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat10 0)) -(set avc2copCCR5 (subword SI concat10 1)) -) - ()) -(dncpi cmadua1_avc2_c3 "cmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmadua1")) - "cmadua1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat11)) (c-call "check_option_cp" pc) -(set concat11 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat11 0)) -(set avc2copCCR5 (subword SI concat11 1)) -) - ()) -(dncpi cmsba1_avc2_c3 "cmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsba1")) - "cmsba1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat12)) (c-call "check_option_cp" pc) -(set concat12 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3CRq) (ext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat12 0)) -(set avc2copCCR5 (subword SI concat12 1)) -) - ()) -(dncpi cmsbua1_avc2_c3 "cmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmsbua1")) - "cmsbua1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u16 #x4) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat13)) (c-call "check_option_cp" pc) -(set concat13 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3CRq) (zext DI avc2c3CRp)))) -(set avc2copCCR4 (subword SI concat13 0)) -(set avc2copCCR5 (subword SI concat13 1)) -) - ()) -(dncpi xmula0_avc2_c3 "xmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula0")) - "xmula0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat14)) (c-call "check_option_cp" pc) -(set concat14 (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))) -(set avc2copCCR2 (subword SI concat14 0)) -(set avc2copCCR3 (subword SI concat14 1)) -) - ()) -(dncpi xmulua0_avc2_c3 "xmulua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua0")) - "xmulua0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat15)) (c-call "check_option_cp" pc) -(set concat15 (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))) -(set avc2copCCR2 (subword SI concat15 0)) -(set avc2copCCR3 (subword SI concat15 1)) -) - ()) -(dncpi xnmula0_avc2_c3 "xnmula0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula0")) - "xnmula0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat16)) (c-call "check_option_cp" pc) -(set concat16 (neg (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat16 0)) -(set avc2copCCR3 (subword SI concat16 1)) -) - ()) -(dncpi xmada0_avc2_c3 "xmada0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada0")) - "xmada0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x4) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat17)) (c-call "check_option_cp" pc) -(set concat17 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat17 0)) -(set avc2copCCR3 (subword SI concat17 1)) -) - ()) -(dncpi xmadua0_avc2_c3 "xmadua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua0")) - "xmadua0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x5) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat18)) (c-call "check_option_cp" pc) -(set concat18 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat18 0)) -(set avc2copCCR3 (subword SI concat18 1)) -) - ()) -(dncpi xmsba0_avc2_c3 "xmsba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba0")) - "xmsba0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x6) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat19)) (c-call "check_option_cp" pc) -(set concat19 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat19 0)) -(set avc2copCCR3 (subword SI concat19 1)) -) - ()) -(dncpi xmsbua0_avc2_c3 "xmsbua0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x7) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat20)) (c-call "check_option_cp" pc) -(set concat20 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR2 (subword SI concat20 0)) -(set avc2copCCR3 (subword SI concat20 1)) -) - ()) -(dncpi xmula1_avc2_c3 "xmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmula1")) - "xmula1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat21)) (c-call "check_option_cp" pc) -(set concat21 (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm))) -(set avc2copCCR4 (subword SI concat21 0)) -(set avc2copCCR5 (subword SI concat21 1)) -) - ()) -(dncpi xmulua1_avc2_c3 "xmulua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmulua1")) - "xmulua1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat22)) (c-call "check_option_cp" pc) -(set concat22 (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm))) -(set avc2copCCR4 (subword SI concat22 0)) -(set avc2copCCR5 (subword SI concat22 1)) -) - ()) -(dncpi xnmula1_avc2_c3 "xnmula1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xnmula1")) - "xnmula1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat23)) (c-call "check_option_cp" pc) -(set concat23 (neg (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat23 0)) -(set avc2copCCR5 (subword SI concat23 1)) -) - ()) -(dncpi xmada1_avc2_c3 "xmada1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmada1")) - "xmada1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xc) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat24)) (c-call "check_option_cp" pc) -(set concat24 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat24 0)) -(set avc2copCCR5 (subword SI concat24 1)) -) - ()) -(dncpi xmadua1_avc2_c3 "xmadua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmadua1")) - "xmadua1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xd) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat25)) (c-call "check_option_cp" pc) -(set concat25 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat25 0)) -(set avc2copCCR5 (subword SI concat25 1)) -) - ()) -(dncpi xmsba1_avc2_c3 "xmsba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsba1")) - "xmsba1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xe) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat26)) (c-call "check_option_cp" pc) -(set concat26 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2c3Rn) (ext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat26 0)) -(set avc2copCCR5 (subword SI concat26 1)) -) - ()) -(dncpi xmsbua1_avc2_c3 "xmsbua1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avc2c3Rn,$avc2c3Rm" -(+ MAJ_15 (f-sub4 7) avc2c3Rn avc2c3Rm (f-avc2-c3sub4u28 #xf) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xc)) -(sequence((DI concat27)) (c-call "check_option_cp" pc) -(set concat27 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2c3Rn) (zext DI avc2c3Rm)))) -(set avc2copCCR4 (subword SI concat27 0)) -(set avc2copCCR5 (subword SI concat27 1)) -) - ()) -(dncpi cclipa0_avc2_c3 "cclipa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipa0")) - "cclipa0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x6) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) -) -) -(set avc2c3CRq (subword SI tmp_rslt 1)) -) - ()) -(dncpi cclipa1_avc2_c3 "cclipa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cclipa1")) - "cclipa1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x6) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) -) -) -(set avc2c3CRq (subword SI tmp_rslt 1)) -) - ()) -(dncpi cmvsla0i_avc2_c3 "cmvsla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsla0i")) - "cmvsla0i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x2) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat28)) (c-call "check_option_cp" pc) -(set concat28 (sll (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat28 0)) -(set avc2copCCR3 (subword SI concat28 1)) -) - ()) -(dncpi cmvsra0i_avc2_c3 "cmvsra0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsra0i")) - "cmvsra0i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat29)) (c-call "check_option_cp" pc) -(set concat29 (sra (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat29 0)) -(set avc2copCCR3 (subword SI concat29 1)) -) - ()) -(dncpi cmvsla1i_avc2_c3 "cmvsla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsla1i")) - "cmvsla1i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x3) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat30)) (c-call "check_option_cp" pc) -(set concat30 (sll (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat30 0)) -(set avc2copCCR5 (subword SI concat30 1)) -) - ()) -(dncpi cmvsra1i_avc2_c3 "cmvsra1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cmvsra1i")) - "cmvsra1i $avc2c3CRq,$avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u16 #xb) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat31)) (c-call "check_option_cp" pc) -(set concat31 (sra (ext DI avc2c3CRq) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat31 0)) -(set avc2copCCR5 (subword SI concat31 1)) -) - ()) -(dncpi csraa0i_avc2_c3 "csraa0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa0i")) - "csraa0i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat32)) (c-call "check_option_cp" pc) -(set concat32 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat32 0)) -(set avc2copCCR3 (subword SI concat32 1)) -) - ()) -(dncpi csraa1i_avc2_c3 "csraa1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa1i")) - "csraa1i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat33)) (c-call "check_option_cp" pc) -(set concat33 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat33 0)) -(set avc2copCCR5 (subword SI concat33 1)) -) - ()) -(dncpi csrla0i_avc2_c3 "csrla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla0i")) - "csrla0i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x1) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat34)) (c-call "check_option_cp" pc) -(set concat34 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat34 0)) -(set avc2copCCR3 (subword SI concat34 1)) -) - ()) -(dncpi csrla1i_avc2_c3 "csrla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla1i")) - "csrla1i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x1) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat35)) (c-call "check_option_cp" pc) -(set concat35 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat35 0)) -(set avc2copCCR5 (subword SI concat35 1)) -) - ()) -(dncpi cslla0i_avc2_c3 "cslla0i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla0i")) - "cslla0i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x0) (f-avc2-c3sub4u20 #x3) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat36)) (c-call "check_option_cp" pc) -(set concat36 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2c3Imm6u24)) -(set avc2copCCR2 (subword SI concat36 0)) -(set avc2copCCR3 (subword SI concat36 1)) -) - ()) -(dncpi cslla1i_avc2_c3 "cslla1i" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla1i")) - "cslla1i $avc2c3Imm6u24" -(+ MAJ_15 (f-sub4 7) avc2c3Imm6u24 (f-avc2-c3sub2u30 #x1) (f-avc2-c3sub4u20 #x3) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat37)) (c-call "check_option_cp" pc) -(set concat37 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2c3Imm6u24)) -(set avc2copCCR4 (subword SI concat37 0)) -(set avc2copCCR5 (subword SI concat37 1)) -) - ()) -(dncpi csraa0_avc2_c3 "csraa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa0")) - "csraa0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xc) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat38)) (c-call "check_option_cp" pc) -(set concat38 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat38 0)) -(set avc2copCCR3 (subword SI concat38 1)) -) - ()) -(dncpi csraa1_avc2_c3 "csraa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csraa1")) - "csraa1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xc) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat39)) (c-call "check_option_cp" pc) -(set concat39 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat39 0)) -(set avc2copCCR5 (subword SI concat39 1)) -) - ()) -(dncpi csrla0_avc2_c3 "csrla0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla0")) - "csrla0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xd) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat40)) (c-call "check_option_cp" pc) -(set concat40 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat40 0)) -(set avc2copCCR3 (subword SI concat40 1)) -) - ()) -(dncpi csrla1_avc2_c3 "csrla1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csrla1")) - "csrla1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xd) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat41)) (c-call "check_option_cp" pc) -(set concat41 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat41 0)) -(set avc2copCCR5 (subword SI concat41 1)) -) - ()) -(dncpi cslla0_avc2_c3 "cslla0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla0")) - "cslla0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xf) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat42)) (c-call "check_option_cp" pc) -(set concat42 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat42 0)) -(set avc2copCCR3 (subword SI concat42 1)) -) - ()) -(dncpi cslla1_avc2_c3 "cslla1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cslla1")) - "cslla1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #xf) (f-avc2-c3sub4u16 #x9) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat43)) (c-call "check_option_cp" pc) -(set concat43 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat43 0)) -(set avc2copCCR5 (subword SI concat43 1)) -) - ()) -(dncpi cadda0_avc2_c3 "cadda0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadda0")) - "cadda0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat44)) (c-call "check_option_cp" pc) -(set concat44 (add (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2c3CRq))) -(set avc2copCCR2 (subword SI concat44 0)) -(set avc2copCCR3 (subword SI concat44 1)) -) - ()) -(dncpi cadda1_avc2_c3 "cadda1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadda1")) - "cadda1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat45)) (c-call "check_option_cp" pc) -(set concat45 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2c3CRq))) -(set avc2copCCR4 (subword SI concat45 0)) -(set avc2copCCR5 (subword SI concat45 1)) -) - ()) -(dncpi csuba0_avc2_c3 "csuba0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csuba0")) - "csuba0 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat46)) (c-call "check_option_cp" pc) -(set concat46 (sub (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2c3CRq))) -(set avc2copCCR2 (subword SI concat46 0)) -(set avc2copCCR3 (subword SI concat46 1)) -) - ()) -(dncpi csuba1_avc2_c3 "csuba1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csuba1")) - "csuba1 $avc2c3CRq" -(+ MAJ_15 (f-sub4 7) avc2c3CRq (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat47)) (c-call "check_option_cp" pc) -(set concat47 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2c3CRq))) -(set avc2copCCR4 (subword SI concat47 0)) -(set avc2copCCR5 (subword SI concat47 1)) -) - ()) -(dncpi cadd2a0_avc2_c3 "cadd2a0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd2a0")) - "cadd2a0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x8) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat48)) (c-call "check_option_cp" pc) -(set concat48 (add (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat48 0)) -(set avc2copCCR3 (subword SI concat48 1)) -) - ()) -(dncpi cadd2a1_avc2_c3 "cadd2a1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "cadd2a1")) - "cadd2a1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #x9) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat49)) (c-call "check_option_cp" pc) -(set concat49 (add (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat49 0)) -(set avc2copCCR5 (subword SI concat49 1)) -) - ()) -(dncpi csub2a0_avc2_c3 "csub2a0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub2a0")) - "csub2a0 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xa) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat50)) (c-call "check_option_cp" pc) -(set concat50 (sub (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR2 (subword SI concat50 0)) -(set avc2copCCR3 (subword SI concat50 1)) -) - ()) -(dncpi csub2a1_avc2_c3 "csub2a1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csub2a1")) - "csub2a1 $avc2c3CRq,$avc2c3CRp" -(+ MAJ_15 (f-sub4 7) avc2c3CRq avc2c3CRp (f-avc2-c3sub4u28 #xb) (f-avc2-c3sub4u16 #x8) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat51)) (c-call "check_option_cp" pc) -(set concat51 (sub (ext DI avc2c3CRq) (ext DI avc2c3CRp))) -(set avc2copCCR4 (subword SI concat51 0)) -(set avc2copCCR5 (subword SI concat51 1)) -) - ()) -(dncpi caddaa0_avc2_c3 "caddaa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddaa0")) - "caddaa0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x0) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat52)) (c-call "check_option_cp" pc) -(set concat52 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat52 0)) -(set avc2copCCR3 (subword SI concat52 1)) -) - ()) -(dncpi caddaa1_avc2_c3 "caddaa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "caddaa1")) - "caddaa1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x1) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat53)) (c-call "check_option_cp" pc) -(set concat53 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat53 0)) -(set avc2copCCR5 (subword SI concat53 1)) -) - ()) -(dncpi csubaa0_avc2_c3 "csubaa0" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csubaa0")) - "csubaa0" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x2) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat54)) (c-call "check_option_cp" pc) -(set concat54 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat54 0)) -(set avc2copCCR3 (subword SI concat54 1)) -) - ()) -(dncpi csubaa1_avc2_c3 "csubaa1" (OPTIONAL_CP_INSN (SLOT C3) (INTRINSIC "csubaa1")) - "csubaa1" -(+ MAJ_15 (f-sub4 7) (f-avc2-c3sub4u28 #x3) (f-avc2-c3sub4u24 #x0) (f-avc2-c3sub4u20 #x0) (f-avc2-c3sub4u16 #xa) (f-avc2-c3sub4u8 #x0) (f-avc2-c3sub4u4 #x0)) -(sequence((DI concat55)) (c-call "check_option_cp" pc) -(set concat55 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat55 0)) -(set avc2copCCR5 (subword SI concat55 1)) -) - ()) -(dn16i cnop_avc2_v1 "cnop" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnop")) - "cnop" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x0)) -(c-call "check_option_cp" pc) - ()) -(dnmi cpnop16_avc2_v1 "cpnop16" -(avc2-16-isa NO-DIS) -"cpnop16" -(emit cnop_avc2_v1) -) -(dn16i cmov_avc2_v1 "cmov" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmov")) - "cmov $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq avc2v1CRp) -) - ()) -(dn16i cmovi_avc2_v1 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmovi")) - "cmovi $avc2v1CRq,$avc2v1Imm8s8" -(+ avc2v1CRq avc2v1Imm8s8 (f-avc2-v1sub4u0 #x2)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (ext SI avc2v1Imm8s8)) -) - ()) -(dn16i cadd3_avc2_v1 "cadd3" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd3")) - "cadd3 $avc2v1CRo,$avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRo avc2v1CRq avc2v1CRp (f-avc2-v1sub4u0 #x3)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRo (add avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i caddi_avc2_v1 "caddi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddi")) - "caddi $avc2v1CRq,$avc2v1Imm6s8" -(+ avc2v1CRq avc2v1Imm6s8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (add avc2v1CRq (ext SI avc2v1Imm6s8))) -) - ()) -(dn16i csub_avc2_v1 "csub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub")) - "csub $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sub avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cneg_avc2_v1 "cneg" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cneg")) - "cneg $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (neg avc2v1CRp)) -) - ()) -(dn16i cextb_avc2_v1 "cextb" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextb")) - "cextb $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (ext SI (and QI (srl avc2v1CRq 0) #xff))) -) - ()) -(dn16i cexth_avc2_v1 "cexth" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cexth")) - "cexth $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x2) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (ext SI (and HI (srl avc2v1CRq 0) #xffff))) -) - ()) -(dn16i cextub_avc2_v1 "cextub" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextub")) - "cextub $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #x8) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (zext SI (and QI (srl avc2v1CRq 0) #xff))) -) - ()) -(dn16i cextuh_avc2_v1 "cextuh" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cextuh")) - "cextuh $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u8 #xa) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (zext SI (and HI (srl avc2v1CRq 0) #xffff))) -) - ()) -(dn16i cscltz_avc2_v1 "cscltz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cscltz")) - "cscltz $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u8 #xa) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2v1CRq) (ext SI 0)) (set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 1) 31) 31))) -(set avc2copCCR1 (or (sll (srl avc2copCCR1 1) 1) (srl (sll (zext SI 0) 31) 31))) -) -) - ()) -(dn16i cldz_avc2_v1 "cldz" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cldz")) - "cldz $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (and avc2v1CRp #x80000000) (set avc2v1CRq 0) -(if (and avc2v1CRp #x40000000) (set avc2v1CRq 1) -(if (and avc2v1CRp #x20000000) (set avc2v1CRq 2) -(if (and avc2v1CRp #x10000000) (set avc2v1CRq 3) -(if (and avc2v1CRp #x8000000) (set avc2v1CRq 4) -(if (and avc2v1CRp #x4000000) (set avc2v1CRq 5) -(if (and avc2v1CRp #x2000000) (set avc2v1CRq 6) -(if (and avc2v1CRp #x1000000) (set avc2v1CRq 7) -(if (and avc2v1CRp #x800000) (set avc2v1CRq 8) -(if (and avc2v1CRp #x400000) (set avc2v1CRq 9) -(if (and avc2v1CRp #x200000) (set avc2v1CRq 10) -(if (and avc2v1CRp #x100000) (set avc2v1CRq 11) -(if (and avc2v1CRp #x80000) (set avc2v1CRq 12) -(if (and avc2v1CRp #x40000) (set avc2v1CRq 13) -(if (and avc2v1CRp #x20000) (set avc2v1CRq 14) -(if (and avc2v1CRp #x10000) (set avc2v1CRq 15) -(if (and avc2v1CRp #x8000) (set avc2v1CRq 16) -(if (and avc2v1CRp #x4000) (set avc2v1CRq 17) -(if (and avc2v1CRp #x2000) (set avc2v1CRq 18) -(if (and avc2v1CRp #x1000) (set avc2v1CRq 19) -(if (and avc2v1CRp #x800) (set avc2v1CRq 20) -(if (and avc2v1CRp #x400) (set avc2v1CRq 21) -(if (and avc2v1CRp #x200) (set avc2v1CRq 22) -(if (and avc2v1CRp #x100) (set avc2v1CRq 23) -(if (and avc2v1CRp #x80) (set avc2v1CRq 24) -(if (and avc2v1CRp #x40) (set avc2v1CRq 25) -(if (and avc2v1CRp #x20) (set avc2v1CRq 26) -(if (and avc2v1CRp #x10) (set avc2v1CRq 27) -(if (and avc2v1CRp #x8) (set avc2v1CRq 28) -(if (and avc2v1CRp #x4) (set avc2v1CRq 29) -(if (and avc2v1CRp #x2) (set avc2v1CRq 30) -(if (and avc2v1CRp #x1) (set avc2v1CRq 31) -(set avc2v1CRq 32) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) -) - ()) -(dn16i cabs_avc2_v1 "cabs" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cabs")) - "cabs $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (abs (ext SI (subword SI (sub avc2v1CRq avc2v1CRp) 1)))) -) - ()) -(dn16i cad1s_avc2_v1 "cad1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cad1s")) - "cad1s $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (add avc2v1CRq avc2v1CRp) 1)) -(set avc2v1CRq (sra tmp0 1)) -) - ()) -(dn16i csb1s_avc2_v1 "csb1s" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csb1s")) - "csb1s $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp0)) (c-call "check_option_cp" pc) -(set tmp0 (subword SI (sub avc2v1CRq avc2v1CRp) 1)) -(set avc2v1CRq (sra tmp0 1)) -) - ()) -(dn16i cmin_avc2_v1 "cmin" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmin")) - "cmin $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (lt (ext SI avc2v1CRq) (ext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cmax_avc2_v1 "cmax" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmax")) - "cmax $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gt (ext SI avc2v1CRq) (ext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cminu_avc2_v1 "cminu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cminu")) - "cminu $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (ltu (zext SI avc2v1CRq) (zext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cmaxu_avc2_v1 "cmaxu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmaxu")) - "cmaxu $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xb) (f-avc2-v1sub4u0 #x5)) -(sequence() (c-call "check_option_cp" pc) -(if (gtu (zext SI avc2v1CRq) (zext SI avc2v1CRp)) (set avc2v1CRq avc2v1CRq) -(set avc2v1CRq avc2v1CRp) -) -) - ()) -(dn16i cclipi_avc2_v1 "cclipi" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipi")) - "cclipi $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x4) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2v1Imm5u8) (ext SI 0)) (set avc2v1CRq 0) -(sequence() (set tmp0 (sll 1 (sub avc2v1Imm5u8 1))) -(set tmp1 (sub tmp0 1)) -(if (gt (ext SI avc2v1CRq) (ext SI tmp1)) (set avc2v1CRq tmp1) -(if (lt (ext SI avc2v1CRq) (ext SI (neg tmp0))) (set avc2v1CRq (neg tmp0)) -(set avc2v1CRq avc2v1CRq) -) -) -) -) -) - ()) -(dn16i cclipiu_avc2_v1 "cclipiu" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipiu")) - "cclipiu $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x5) (f-avc2-v1sub4u0 #x5)) -(sequence((SI tmp1)(SI tmp0)) (c-call "check_option_cp" pc) -(if (eq (zext SI avc2v1Imm5u8) (ext SI 0)) (set avc2v1CRq 0) -(sequence() (set tmp0 (sub (sll 1 avc2v1Imm5u8) 1)) -(if (gtu (ext SI avc2v1CRq) (zext SI tmp0)) (set avc2v1CRq tmp0) -(if (lt (ext SI avc2v1CRq) (ext SI 0)) (set avc2v1CRq 0) -(set avc2v1CRq avc2v1CRq) -) -) -) -) -) - ()) -(dn16i cor_avc2_v1 "cor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cor")) - "cor $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x4) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (or avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cand_avc2_v1 "cand" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cand")) - "cand $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x5) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (and avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cxor_avc2_v1 "cxor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cxor")) - "cxor $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x6) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (xor avc2v1CRq avc2v1CRp)) -) - ()) -(dn16i cnor_avc2_v1 "cnor" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnor")) - "cnor $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (inv (or avc2v1CRq avc2v1CRp))) -) - ()) -(dn16i csra_avc2_v1 "csra" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csra")) - "csra $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xc) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sra avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f))) -) - ()) -(dn16i csrl_avc2_v1 "csrl" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrl")) - "csrl $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xd) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (srl avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f))) -) - ()) -(dn16i csll_avc2_v1 "csll" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csll")) - "csll $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xe) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sll avc2v1CRq (and QI (srl avc2v1CRp 0) #x1f))) -) - ()) -(dn16i csrai_avc2_v1 "csrai" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrai")) - "csrai $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x2) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sra avc2v1CRq avc2v1Imm5u8)) -) - ()) -(dn16i csrli_avc2_v1 "csrli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrli")) - "csrli $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x3) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (srl avc2v1CRq avc2v1Imm5u8)) -) - ()) -(dn16i cslli_avc2_v1 "cslli" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslli")) - "cslli $avc2v1CRq,$avc2v1Imm5u8" -(+ avc2v1CRq avc2v1Imm5u8 (f-avc2-v1sub3u13 #x6) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (sll avc2v1CRq avc2v1Imm5u8)) -) - ()) -(dn16i cfsft_avc2_v1 "cfsft" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsft")) - "cfsft $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u0 #x0)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2v1CRq)) 32) (zext DI avc2v1CRp)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta0_avc2_v1 "cfsfta0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta0")) - "cfsfta0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cfsfta1_avc2_v1 "cfsfta1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cfsfta1")) - "cfsfta1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x1)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v1CRq (subword SI (sll (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f)) 0)) -) - ()) -(dn16i cmula0_avc2_v1 "cmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula0")) - "cmula0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat56)) (c-call "check_option_cp" pc) -(set concat56 (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat56 0)) -(set avc2copCCR3 (subword SI concat56 1)) -) - ()) -(dn16i cmulua0_avc2_v1 "cmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua0")) - "cmulua0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat57)) (c-call "check_option_cp" pc) -(set concat57 (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat57 0)) -(set avc2copCCR3 (subword SI concat57 1)) -) - ()) -(dn16i cnmula0_avc2_v1 "cnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula0")) - "cnmula0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat58)) (c-call "check_option_cp" pc) -(set concat58 (neg (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat58 0)) -(set avc2copCCR3 (subword SI concat58 1)) -) - ()) -(dn16i cmada0_avc2_v1 "cmada0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada0")) - "cmada0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x4) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat59)) (c-call "check_option_cp" pc) -(set concat59 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat59 0)) -(set avc2copCCR3 (subword SI concat59 1)) -) - ()) -(dn16i cmadua0_avc2_v1 "cmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua0")) - "cmadua0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x5) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat60)) (c-call "check_option_cp" pc) -(set concat60 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat60 0)) -(set avc2copCCR3 (subword SI concat60 1)) -) - ()) -(dn16i cmsba0_avc2_v1 "cmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba0")) - "cmsba0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x6) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat61)) (c-call "check_option_cp" pc) -(set concat61 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat61 0)) -(set avc2copCCR3 (subword SI concat61 1)) -) - ()) -(dn16i cmsbua0_avc2_v1 "cmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua0")) - "cmsbua0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x7) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat62)) (c-call "check_option_cp" pc) -(set concat62 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR2 (subword SI concat62 0)) -(set avc2copCCR3 (subword SI concat62 1)) -) - ()) -(dn16i cmula1_avc2_v1 "cmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmula1")) - "cmula1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat63)) (c-call "check_option_cp" pc) -(set concat63 (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat63 0)) -(set avc2copCCR5 (subword SI concat63 1)) -) - ()) -(dn16i cmulua1_avc2_v1 "cmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmulua1")) - "cmulua1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat64)) (c-call "check_option_cp" pc) -(set concat64 (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat64 0)) -(set avc2copCCR5 (subword SI concat64 1)) -) - ()) -(dn16i cnmula1_avc2_v1 "cnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cnmula1")) - "cnmula1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat65)) (c-call "check_option_cp" pc) -(set concat65 (neg (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat65 0)) -(set avc2copCCR5 (subword SI concat65 1)) -) - ()) -(dn16i cmada1_avc2_v1 "cmada1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmada1")) - "cmada1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xc) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat66)) (c-call "check_option_cp" pc) -(set concat66 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat66 0)) -(set avc2copCCR5 (subword SI concat66 1)) -) - ()) -(dn16i cmadua1_avc2_v1 "cmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmadua1")) - "cmadua1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xd) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat67)) (c-call "check_option_cp" pc) -(set concat67 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat67 0)) -(set avc2copCCR5 (subword SI concat67 1)) -) - ()) -(dn16i cmsba1_avc2_v1 "cmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsba1")) - "cmsba1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xe) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat68)) (c-call "check_option_cp" pc) -(set concat68 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v1CRq) (ext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat68 0)) -(set avc2copCCR5 (subword SI concat68 1)) -) - ()) -(dn16i cmsbua1_avc2_v1 "cmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmsbua1")) - "cmsbua1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xf) (f-avc2-v1sub4u0 #x4)) -(sequence((DI concat69)) (c-call "check_option_cp" pc) -(set concat69 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v1CRq) (zext DI avc2v1CRp)))) -(set avc2copCCR4 (subword SI concat69 0)) -(set avc2copCCR5 (subword SI concat69 1)) -) - ()) -(dn16i cclipa0_avc2_v1 "cclipa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipa0")) - "cclipa0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x6)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3))) -) -) -(set avc2v1CRq (subword SI tmp_rslt 1)) -) - ()) -(dn16i cclipa1_avc2_v1 "cclipa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cclipa1")) - "cclipa1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x6)) -(sequence((DI tmp_rslt)(DI min)(DI max)) (c-call "check_option_cp" pc) -(set max #x000000007FFFFFFF) -(set min #xFFFFFFFF80000000) -(if (gt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI max)) (set tmp_rslt max) -(if (lt (ext DI (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) (ext DI min)) (set tmp_rslt min) -(set tmp_rslt (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5))) -) -) -(set avc2v1CRq (subword SI tmp_rslt 1)) -) - ()) -(dn16i cmvsla0i_avc2_v1 "cmvsla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsla0i")) - "cmvsla0i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x2) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat70)) (c-call "check_option_cp" pc) -(set concat70 (sll (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat70 0)) -(set avc2copCCR3 (subword SI concat70 1)) -) - ()) -(dn16i cmvsra0i_avc2_v1 "cmvsra0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsra0i")) - "cmvsra0i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat71)) (c-call "check_option_cp" pc) -(set concat71 (sra (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat71 0)) -(set avc2copCCR3 (subword SI concat71 1)) -) - ()) -(dn16i cmvsla1i_avc2_v1 "cmvsla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsla1i")) - "cmvsla1i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x3) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat72)) (c-call "check_option_cp" pc) -(set concat72 (sll (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat72 0)) -(set avc2copCCR5 (subword SI concat72 1)) -) - ()) -(dn16i cmvsra1i_avc2_v1 "cmvsra1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cmvsra1i")) - "cmvsra1i $avc2v1CRq,$avc2v1Imm6u8" -(+ avc2v1CRq avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u0 #xb)) -(sequence((DI concat73)) (c-call "check_option_cp" pc) -(set concat73 (sra (ext DI avc2v1CRq) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat73 0)) -(set avc2copCCR5 (subword SI concat73 1)) -) - ()) -(dn16i csraa0i_avc2_v1 "csraa0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa0i")) - "csraa0i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat74)) (c-call "check_option_cp" pc) -(set concat74 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat74 0)) -(set avc2copCCR3 (subword SI concat74 1)) -) - ()) -(dn16i csraa1i_avc2_v1 "csraa1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa1i")) - "csraa1i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat75)) (c-call "check_option_cp" pc) -(set concat75 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat75 0)) -(set avc2copCCR5 (subword SI concat75 1)) -) - ()) -(dn16i csrla0i_avc2_v1 "csrla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla0i")) - "csrla0i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x1) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat76)) (c-call "check_option_cp" pc) -(set concat76 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat76 0)) -(set avc2copCCR3 (subword SI concat76 1)) -) - ()) -(dn16i csrla1i_avc2_v1 "csrla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla1i")) - "csrla1i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x1) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat77)) (c-call "check_option_cp" pc) -(set concat77 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat77 0)) -(set avc2copCCR5 (subword SI concat77 1)) -) - ()) -(dn16i cslla0i_avc2_v1 "cslla0i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla0i")) - "cslla0i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x0) (f-avc2-v1sub4u4 #x3) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat78)) (c-call "check_option_cp" pc) -(set concat78 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) avc2v1Imm6u8)) -(set avc2copCCR2 (subword SI concat78 0)) -(set avc2copCCR3 (subword SI concat78 1)) -) - ()) -(dn16i cslla1i_avc2_v1 "cslla1i" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla1i")) - "cslla1i $avc2v1Imm6u8" -(+ avc2v1Imm6u8 (f-avc2-v1sub2u14 #x1) (f-avc2-v1sub4u4 #x3) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat79)) (c-call "check_option_cp" pc) -(set concat79 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) avc2v1Imm6u8)) -(set avc2copCCR4 (subword SI concat79 0)) -(set avc2copCCR5 (subword SI concat79 1)) -) - ()) -(dn16i csraa0_avc2_v1 "csraa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa0")) - "csraa0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xc) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat80)) (c-call "check_option_cp" pc) -(set concat80 (sra (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat80 0)) -(set avc2copCCR3 (subword SI concat80 1)) -) - ()) -(dn16i csraa1_avc2_v1 "csraa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csraa1")) - "csraa1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xc) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat81)) (c-call "check_option_cp" pc) -(set concat81 (sra (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat81 0)) -(set avc2copCCR5 (subword SI concat81 1)) -) - ()) -(dn16i csrla0_avc2_v1 "csrla0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla0")) - "csrla0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xd) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat82)) (c-call "check_option_cp" pc) -(set concat82 (srl (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat82 0)) -(set avc2copCCR3 (subword SI concat82 1)) -) - ()) -(dn16i csrla1_avc2_v1 "csrla1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csrla1")) - "csrla1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xd) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat83)) (c-call "check_option_cp" pc) -(set concat83 (srl (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat83 0)) -(set avc2copCCR5 (subword SI concat83 1)) -) - ()) -(dn16i cslla0_avc2_v1 "cslla0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla0")) - "cslla0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xf) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat84)) (c-call "check_option_cp" pc) -(set concat84 (sll (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR2 (subword SI concat84 0)) -(set avc2copCCR3 (subword SI concat84 1)) -) - ()) -(dn16i cslla1_avc2_v1 "cslla1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cslla1")) - "cslla1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #xf) (f-avc2-v1sub4u0 #x9)) -(sequence((DI concat85)) (c-call "check_option_cp" pc) -(set concat85 (sll (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (and QI (srl avc2copCCR0 0) #x3f))) -(set avc2copCCR4 (subword SI concat85 0)) -(set avc2copCCR5 (subword SI concat85 1)) -) - ()) -(dn16i cadda0_avc2_v1 "cadda0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadda0")) - "cadda0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat86)) (c-call "check_option_cp" pc) -(set concat86 (add (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2v1CRq))) -(set avc2copCCR2 (subword SI concat86 0)) -(set avc2copCCR3 (subword SI concat86 1)) -) - ()) -(dn16i cadda1_avc2_v1 "cadda1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadda1")) - "cadda1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat87)) (c-call "check_option_cp" pc) -(set concat87 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2v1CRq))) -(set avc2copCCR4 (subword SI concat87 0)) -(set avc2copCCR5 (subword SI concat87 1)) -) - ()) -(dn16i csuba0_avc2_v1 "csuba0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csuba0")) - "csuba0 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat88)) (c-call "check_option_cp" pc) -(set concat88 (sub (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)) (ext DI avc2v1CRq))) -(set avc2copCCR2 (subword SI concat88 0)) -(set avc2copCCR3 (subword SI concat88 1)) -) - ()) -(dn16i csuba1_avc2_v1 "csuba1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csuba1")) - "csuba1 $avc2v1CRq" -(+ avc2v1CRq (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat89)) (c-call "check_option_cp" pc) -(set concat89 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (ext DI avc2v1CRq))) -(set avc2copCCR4 (subword SI concat89 0)) -(set avc2copCCR5 (subword SI concat89 1)) -) - ()) -(dn16i cadd2a0_avc2_v1 "cadd2a0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd2a0")) - "cadd2a0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x8) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat90)) (c-call "check_option_cp" pc) -(set concat90 (add (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat90 0)) -(set avc2copCCR3 (subword SI concat90 1)) -) - ()) -(dn16i cadd2a1_avc2_v1 "cadd2a1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "cadd2a1")) - "cadd2a1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #x9) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat91)) (c-call "check_option_cp" pc) -(set concat91 (add (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat91 0)) -(set avc2copCCR5 (subword SI concat91 1)) -) - ()) -(dn16i csub2a0_avc2_v1 "csub2a0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub2a0")) - "csub2a0 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xa) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat92)) (c-call "check_option_cp" pc) -(set concat92 (sub (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR2 (subword SI concat92 0)) -(set avc2copCCR3 (subword SI concat92 1)) -) - ()) -(dn16i csub2a1_avc2_v1 "csub2a1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csub2a1")) - "csub2a1 $avc2v1CRq,$avc2v1CRp" -(+ avc2v1CRq avc2v1CRp (f-avc2-v1sub4u12 #xb) (f-avc2-v1sub4u0 #x8)) -(sequence((DI concat93)) (c-call "check_option_cp" pc) -(set concat93 (sub (ext DI avc2v1CRq) (ext DI avc2v1CRp))) -(set avc2copCCR4 (subword SI concat93 0)) -(set avc2copCCR5 (subword SI concat93 1)) -) - ()) -(dn16i caddaa0_avc2_v1 "caddaa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddaa0")) - "caddaa0" -(+ (f-avc2-v1sub4u12 #x0) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat94)) (c-call "check_option_cp" pc) -(set concat94 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat94 0)) -(set avc2copCCR3 (subword SI concat94 1)) -) - ()) -(dn16i caddaa1_avc2_v1 "caddaa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "caddaa1")) - "caddaa1" -(+ (f-avc2-v1sub4u12 #x1) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat95)) (c-call "check_option_cp" pc) -(set concat95 (add (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat95 0)) -(set avc2copCCR5 (subword SI concat95 1)) -) - ()) -(dn16i csubaa0_avc2_v1 "csubaa0" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csubaa0")) - "csubaa0" -(+ (f-avc2-v1sub4u12 #x2) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat96)) (c-call "check_option_cp" pc) -(set concat96 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR2 (subword SI concat96 0)) -(set avc2copCCR3 (subword SI concat96 1)) -) - ()) -(dn16i csubaa1_avc2_v1 "csubaa1" (VLIW64_NO_MATCHING_NOP (SLOT V1) (INTRINSIC "csubaa1")) - "csubaa1" -(+ (f-avc2-v1sub4u12 #x3) (f-avc2-v1sub4u8 #x0) (f-avc2-v1sub4u4 #x0) (f-avc2-v1sub4u0 #xa)) -(sequence((DI concat97)) (c-call "check_option_cp" pc) -(set concat97 (sub (or (sll (zext DI avc2copCCR4) 32) (zext DI avc2copCCR5)) (or (sll (zext DI avc2copCCR2) 32) (zext DI avc2copCCR3)))) -(set avc2copCCR4 (subword SI concat97 0)) -(set avc2copCCR5 (subword SI concat97 1)) -) - ()) -(dn32i cmov1_avc2_v3 "cmov1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov1")) - "cmov $avc2v3CRn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CRn avc2v3Rm (f-avc2-v3sub4u28 #x0) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3CRn avc2v3Rm) -) - ()) -(dn32i cmov2_avc2_v3 "cmov2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmov2")) - "cmov $avc2v3Rm,$avc2v3CRn" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rm avc2v3CRn (f-avc2-v3sub4u28 #x1) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3Rm avc2v3CRn) -) - ()) -(dn32i cmovi_avc2_v3 "cmovi" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovi")) - "cmovi $avc2v3CRq,$avc2v3Imm16s4x24e32" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CRq avc2v3Imm16s4x24e32 (f-avc2-v3sub4u16 #xe)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3CRq (ext SI avc2v3Imm16s4x24e32)) -) - ()) -(dn32i cmovc1_avc2_v3 "cmovc1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc1")) - "cmovc $avc2v3CCRn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3CCRn avc2v3Rm (f-avc2-v3sub4u28 #x2) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3CCRn avc2v3Rm) -) - ()) -(dn32i cmovc2_avc2_v3 "cmovc2" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "cmovc2")) - "cmovc $avc2v3Rm,$avc2v3CCRn" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rm avc2v3CCRn (f-avc2-v3sub4u28 #x3) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xf)) -(sequence() (c-call "check_option_cp" pc) -(set avc2v3Rm avc2v3CCRn) -) - ()) -(dn32i xmula0_avc2_v3 "xmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula0")) - "xmula0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x0) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat98)) (c-call "check_option_cp" pc) -(set concat98 (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))) -(set avc2copCCR2 (subword SI concat98 0)) -(set avc2copCCR3 (subword SI concat98 1)) -) - ()) -(dn32i xmulua0_avc2_v3 "xmulua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua0")) - "xmulua0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x1) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat99)) (c-call "check_option_cp" pc) -(set concat99 (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))) -(set avc2copCCR2 (subword SI concat99 0)) -(set avc2copCCR3 (subword SI concat99 1)) -) - ()) -(dn32i xnmula0_avc2_v3 "xnmula0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula0")) - "xnmula0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x2) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat100)) (c-call "check_option_cp" pc) -(set concat100 (neg (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat100 0)) -(set avc2copCCR3 (subword SI concat100 1)) -) - ()) -(dn32i xmada0_avc2_v3 "xmada0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada0")) - "xmada0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x4) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat101)) (c-call "check_option_cp" pc) -(set concat101 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat101 0)) -(set avc2copCCR3 (subword SI concat101 1)) -) - ()) -(dn32i xmadua0_avc2_v3 "xmadua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua0")) - "xmadua0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x5) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat102)) (c-call "check_option_cp" pc) -(set concat102 (add (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat102 0)) -(set avc2copCCR3 (subword SI concat102 1)) -) - ()) -(dn32i xmsba0_avc2_v3 "xmsba0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba0")) - "xmsba0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x6) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat103)) (c-call "check_option_cp" pc) -(set concat103 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat103 0)) -(set avc2copCCR3 (subword SI concat103 1)) -) - ()) -(dn32i xmsbua0_avc2_v3 "xmsbua0" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua0")) - "xmsbua0 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x7) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat104)) (c-call "check_option_cp" pc) -(set concat104 (sub (or (sll (zext DI (zext SI avc2copCCR2)) 32) (zext DI avc2copCCR3)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR2 (subword SI concat104 0)) -(set avc2copCCR3 (subword SI concat104 1)) -) - ()) -(dn32i xmula1_avc2_v3 "xmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmula1")) - "xmula1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x8) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat105)) (c-call "check_option_cp" pc) -(set concat105 (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm))) -(set avc2copCCR4 (subword SI concat105 0)) -(set avc2copCCR5 (subword SI concat105 1)) -) - ()) -(dn32i xmulua1_avc2_v3 "xmulua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmulua1")) - "xmulua1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #x9) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat106)) (c-call "check_option_cp" pc) -(set concat106 (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm))) -(set avc2copCCR4 (subword SI concat106 0)) -(set avc2copCCR5 (subword SI concat106 1)) -) - ()) -(dn32i xnmula1_avc2_v3 "xnmula1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xnmula1")) - "xnmula1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xa) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat107)) (c-call "check_option_cp" pc) -(set concat107 (neg (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat107 0)) -(set avc2copCCR5 (subword SI concat107 1)) -) - ()) -(dn32i xmada1_avc2_v3 "xmada1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmada1")) - "xmada1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xc) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat108)) (c-call "check_option_cp" pc) -(set concat108 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat108 0)) -(set avc2copCCR5 (subword SI concat108 1)) -) - ()) -(dn32i xmadua1_avc2_v3 "xmadua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmadua1")) - "xmadua1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xd) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat109)) (c-call "check_option_cp" pc) -(set concat109 (add (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat109 0)) -(set avc2copCCR5 (subword SI concat109 1)) -) - ()) -(dn32i xmsba1_avc2_v3 "xmsba1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsba1")) - "xmsba1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xe) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat110)) (c-call "check_option_cp" pc) -(set concat110 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (ext DI avc2v3Rn) (ext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat110 0)) -(set avc2copCCR5 (subword SI concat110 1)) -) - ()) -(dn32i xmsbua1_avc2_v3 "xmsbua1" (VLIW64_NO_MATCHING_NOP (SLOT V3) (INTRINSIC "xmsbua1")) - "xmsbua1 $avc2v3Rn,$avc2v3Rm" -(+ (f-avc2-v3sub4u0 #xf) (f-avc2-v3sub4u12 #x7) avc2v3Rn avc2v3Rm (f-avc2-v3sub4u28 #xf) (f-avc2-v3sub4u24 #x0) (f-avc2-v3sub4u20 #x0) (f-avc2-v3sub4u16 #xc)) -(sequence((DI concat111)) (c-call "check_option_cp" pc) -(set concat111 (sub (or (sll (zext DI (zext SI avc2copCCR4)) 32) (zext DI avc2copCCR5)) (mul (zext DI avc2v3Rn) (zext DI avc2v3Rm)))) -(set avc2copCCR4 (subword SI concat111 0)) -(set avc2copCCR5 (subword SI concat111 1)) -) - ()) diff --git a/binutils-2.24/cpu/mep-c5.cpu b/binutils-2.24/cpu/mep-c5.cpu deleted file mode 100644 index d3d46218..00000000 --- a/binutils-2.24/cpu/mep-c5.cpu +++ /dev/null @@ -1,281 +0,0 @@ -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; Insns introduced for the MeP-c5 core -; - -(dnf f-c5n4 "extended field" (all-mep-core-isas) 16 4) -(dnf f-c5n5 "extended field" (all-mep-core-isas) 20 4) -(dnf f-c5n6 "extended field" (all-mep-core-isas) 24 4) -(dnf f-c5n7 "extended field" (all-mep-core-isas) 28 4) -(dnf f-rl5 "register l c5" (all-mep-core-isas) 20 4) -(df f-12s20 "extended field" (all-mep-core-isas) 20 12 INT #f #f) - -(dnop rl5 "register Rl c5" (all-mep-core-isas) h-gpr f-rl5) -(dnop cdisp12 "copro addend (12 bits)" (all-mep-core-isas) h-sint f-12s20) - -(dnci stcb_r "store in control bus space" (VOLATILE (MACH c5)) - "stcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 12)) - (c-call VOID "do_stcb" rn (and rma #xffff)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-stcb)))) - -(dnci ldcb_r "load from control bus space" (VOLATILE (MACH c5) (LATENCY 3)) - "ldcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 13)) - (set rn (c-call SI "do_ldcb" (and rma #xffff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-ldcb) - (unit u-exec) - (unit u-ldcb-gpr (out loadreg rn))))) - -(dnci pref "cache prefetch" ((MACH c5) VOLATILE) - "pref $cimm4,($rma)" - (+ MAJ_7 cimm4 rma (f-sub4 5)) - (sequence () - (c-call VOID "check_option_dcache" pc) - (c-call VOID "do_cache_prefetch" cimm4 rma pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci prefd "cache prefetch" ((MACH c5) VOLATILE) - "pref $cimm4,$sdisp16($rma)" - (+ MAJ_15 cimm4 rma (f-sub4 3) sdisp16) - (sequence () - (c-call VOID "check_option_dcache" pc) - (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci casb3 "compare and swap byte 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN) - "casb3 $rl5,$rn,($rm)" - (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x0)) - (sequence () - (c-call VOID "do_casb3" (index-of rl5) rn rm pc) - (set rl5 rl5) - ) - ((mep (unit u-use-gpr (in usereg rl5)) - (unit u-load-gpr (out loadreg rl5)) - (unit u-exec)))) - -(dnci cash3 "compare and swap halfword 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN) - "cash3 $rl5,$rn,($rm)" - (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x1)) - (sequence () - (c-call VOID "do_cash3" (index-of rl5) rn rm pc) - (set rl5 rl5) - ) - ((mep (unit u-use-gpr (in usereg rl5)) - (unit u-load-gpr (out loadreg rl5)) - (unit u-exec)))) - -(dnci casw3 "compare and swap word 3" ((MACH c5) VOLATILE OPTIONAL_BIT_INSN) - "casw3 $rl5,$rn,($rm)" - (+ MAJ_15 rn rm (f-sub4 #x1) (f-c5n4 #x2) rl5 (f-c5n6 #x0) (f-c5n7 #x2)) - (sequence () - (c-call VOID "do_casw3" (index-of rl5) rn rm pc) - (set rl5 rl5) - ) - ((mep (unit u-use-gpr (in usereg rl5)) - (unit u-load-gpr (out loadreg rl5)) - (unit u-exec)))) - - - -(dnci sbcp "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "sbcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 0) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12))) - (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lbcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 4) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbucp "load byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lbucp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 12) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -(dnci shcp "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "shcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 1) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12))) - (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lhcp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 5) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucp "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE) (MACH c5)) - "lhucp $crn,$cdisp12($rma)" - (+ MAJ_15 crn rma (f-sub4 6) (f-ext4 13) cdisp12) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (add rma (ext SI cdisp12)))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -(dnci lbucpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5)) - "lbucpa $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xC) (f-ext62 #x0) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI rma))) - (set rma (add rma cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD) (MACH c5)) - "lhucpa $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xD) (f-ext62 #x0) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (and rma (inv SI 1))))) - (set rma (add rma (ext SI cdisp10a2)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbucpm0 "lbucpm0" (OPTIONAL_CP_INSN (MACH c5)) - "lbucpm0 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x2) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI rma))) - (set rma (mod0 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucpm0 "lhucpm0" (OPTIONAL_CP_INSN (MACH c5)) - "lhucpm0 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x2) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod0 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbucpm1 "lbucpm1" (OPTIONAL_CP_INSN (MACH c5)) - "lbucpm1 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xc) (f-ext62 #x3) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem QI rma))) - (set rma (mod1 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhucpm1 "lhucpm1" (OPTIONAL_CP_INSN (MACH c5)) - "lhucpm1 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #xd) (f-ext62 #x3) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (zext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod1 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci uci "uci" ((MACH c5) VOLATILE) - "uci $rn,$rm,$uimm16" - (+ MAJ_15 rn rm (f-sub4 2) simm16) - (set rn (c-call SI "do_UCI" rn rm (zext SI uimm16) pc)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnf f-c5-rnm "register n/m" (all-mep-isas) 4 8) -(dnf f-c5-rm "register m" (all-mep-isas) 8 4) -(df f-c5-16u16 "general 16-bit u-val" (all-mep-isas) 16 16 UINT #f #f) - -(dnmf f-c5-rmuimm20 "20-bit immediate in Rm/Imm16" (all-mep-isas) UINT - (f-c5-rm f-c5-16u16) - (sequence () ; insert - (set (ifield f-c5-rm) (srl (ifield f-c5-rmuimm20) 16)) - (set (ifield f-c5-16u16) (and (ifield f-c5-rmuimm20) #xffff)) - ) - (sequence () ; extract - (set (ifield f-c5-rmuimm20) (or (ifield f-c5-16u16) - (sll (ifield f-c5-rm) 16))) - ) - ) -(dnop c5rmuimm20 "20-bit immediate in rm and imm16" (all-mep-core-isas) h-uint f-c5-rmuimm20) - -(dnmf f-c5-rnmuimm24 "24-bit immediate in Rm/Imm16" (all-mep-isas) UINT - (f-c5-rnm f-c5-16u16) - (sequence () ; insert - (set (ifield f-c5-rnm) (srl (ifield f-c5-rnmuimm24) 16)) - (set (ifield f-c5-16u16) (and (ifield f-c5-rnmuimm24) #xffff)) - ) - (sequence () ; extract - (set (ifield f-c5-rnmuimm24) (or (ifield f-c5-16u16) - (sll (ifield f-c5-rnm) 16))) - ) - ) -(dnop c5rnmuimm24 "24-bit immediate in rn, rm, and imm16" (all-mep-core-isas) h-uint f-c5-rnmuimm24) - -(dnci dsp "dsp" ((MACH c5) VOLATILE) - "dsp $rn,$rm,$uimm16" - (+ MAJ_15 rn rm (f-sub4 0) uimm16) - (set rn (c-call SI "do_DSP" rn rm (zext SI uimm16) pc)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci dsp0 "dsp0" ((MACH c5) VOLATILE NO-DIS ALIAS) - "dsp0 $c5rnmuimm24" - (+ MAJ_15 c5rnmuimm24 (f-sub4 0)) - (c-call VOID "do_DSP" (zext SI c5rnmuimm24) pc) - ((mep (unit u-exec)))) - -(dnci dsp1 "dsp1" ((MACH c5) VOLATILE NO-DIS ALIAS) - "dsp1 $rn,$c5rmuimm20" - (+ MAJ_15 rn (f-sub4 0) c5rmuimm20) - (set rn (c-call SI "do_DSP" rn (zext SI c5rmuimm20) pc)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) diff --git a/binutils-2.24/cpu/mep-core.cpu b/binutils-2.24/cpu/mep-core.cpu deleted file mode 100644 index accf00ef..00000000 --- a/binutils-2.24/cpu/mep-core.cpu +++ /dev/null @@ -1,3082 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -(define-pmacro isa-enum () - (isas mep -; begin-isa-enum - ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64 -; end-isa-enum - ) -) - -(define-arch - (name mep) - (comment "Toshiba MeP Media Engine") - (insn-lsb0? #f) ;; work around cgen limitation - (machs mep h1 c5) - isa-enum -) - -(define-isa - (name mep) - (comment "MeP core instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -; begin-isas -(define-isa - (name ext_core1) - (comment "MeP core extension instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_16) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_32) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_48) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-isa - (name ext_cop1_64) - (comment "MeP coprocessor instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) -) - -(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) - -(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32)) - -(define-pmacro all-core-isa-list () mep,ext_core1) -; end-isas - -(define-cpu - (name mepf) - (comment "MeP family") - (endian either) - (insn-chunk-bitsize 16) - (word-bitsize 32) -) - -(define-mach - (name mep) - (comment "MeP media engine") - (cpu mepf) - isa-enum -) - -(define-mach - (name h1) - (comment "H1 media engine") - (cpu mepf) - isa-enum -) - -(define-mach - (name c5) - (comment "C5 media engine") - (cpu mepf) - isa-enum -) - -(define-model - (name mep) - (comment "MeP media engine processor") - (mach c5) ; mach gets changed by MeP-Integrator - - (unit u-exec "execution unit" () - 1 1 ; issue done - () () () ()) - - ; Branch unit - (unit u-branch "Branch Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - - ; Multiply unit - (unit u-multiply "Multiply Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Divide unit - (unit u-divide "Divide Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Stcb unit - (unit u-stcb "stcb Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Ldcb unit - (unit u-ldcb "ldcb Unit" () - 0 0 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Load gpr unit - (unit u-load-gpr "Load into GPR Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((loadreg INT -1)) ; outputs - () ; profile action (default) - ) - - (unit u-ldcb-gpr "Ldcb into GPR Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((loadreg INT -1)) ; outputs - () ; profile action (default) - ) - - ; Multiply into GPR unit - (unit u-mul-gpr "Multiply into GPR Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((resultreg INT -1)) ; outputs - () ; profile action (default) - ) - - ; Use gpr unit -- stalls if GPR not ready - (unit u-use-gpr "Use GPR Unit" () - 0 0 ; issue done - () ; state - ((usereg INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Use ctrl-reg unit -- stalls if CTRL-REG not ready - (unit u-use-ctrl-reg "Use CTRL-REG Unit" () - 0 0 ; issue done - () ; state - ((usereg INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - - ; Store ctrl-reg unit -- stalls if CTRL-REG not ready - (unit u-store-ctrl-reg "Store CTRL-REG Unit" () - 0 0 ; issue done - () ; state - () ; inputs - ((storereg INT -1)) ; outputs - () ; profile action (default) - ) -) - -; Hardware elements. - -(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ()) - -(define-hardware - (name h-gpr) - (comment "General purpose registers") - (attrs all-mep-isas CACHE-ADDR PROFILE) - (type register SI (16)) - (indices keyword "$" - (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) - ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) - ; "$8" is the preferred name for register 8, but "$tp", "$gp" - ; and "$sp" are preferred for their respective registers. - (fp 8) (tp 13) (gp 14) (sp 15) - ("12" 12) ("13" 13) ("14" 14) ("15" 15))) -) - -(define-hardware - (name h-csr) - (comment "Control/special registers") - (attrs all-mep-isas PROFILE) - (type register SI (32)) - (indices keyword "$" - ((pc 0) (lp 1) (sar 2) (rpb 4) (rpe 5) (rpc 6) - (hi 7) (lo 8) (mb0 12) (me0 13) (mb1 14) (me1 15) - (psw 16) (id 17) (tmp 18) (epc 19) (exc 20) (cfg 21) - (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28) -; begin-extra-csr-registers - (vid 22) -; end-extra-csr-registers - )) - (get (index) (c-call SI "cgen_get_csr_value" index)) - (set (index newval) (c-call VOID "cgen_set_csr_value" index newval)) -) - -(define-pmacro (-reg-pair n) ((.sym n) n)) -(define-hardware - (name h-cr64) - (comment "64-bit coprocessor registers") - (attrs all-mep-isas) - ; This assumes that the data path of the co-pro is 64 bits. - (type register DI (32)) - (indices keyword "$c" (.map -reg-pair (.iota 32))) - (set (index newval) (c-call VOID "h_cr64_queue_set" index newval)) -) -(define-hardware - (name h-cr64-w) - (comment "64-bit coprocessor registers, pending writes") - (attrs all-mep-isas) - ; This assumes that the data path of the co-pro is 64 bits. - (type register DI (32)) -) - -(define-hardware - (name h-cr) - (comment "32-bit coprocessor registers") - (attrs all-mep-isas VIRTUAL) - (type register SI (32)) - (indices keyword "$c" (.map -reg-pair (.iota 32))) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) -) - -;; Given a coprocessor control register number N, expand to a -;; name/index pair: ($ccrN N) -(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n)) - -(define-hardware - (name h-ccr) - (comment "Coprocessor control registers") - (attrs all-mep-isas) - (type register SI (64)) - (indices keyword "" (.map -ccr-reg-pair (.iota 64))) - (set (index newval) (c-call VOID "h_ccr_queue_set" index newval)) -) -(define-hardware - (name h-ccr-w) - (comment "Coprocessor control registers, pending writes") - (attrs all-mep-isas) - (type register SI (64)) -) - - -; Instruction fields. Bit numbering reversed. - -; Conventions: -; -; N = number of bits in value -; A = alignment (2 or 4, omit for 1) -; B = leftmost (i.e. closest to zero) bit position -; -; -- Generic Fields (f-*) -- -; N number of bits in *value* (1-24) -; [us] signed vs unsigned -; B position of left-most bit (4-16) -; aA opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc) -; n opt. for noncontiguous fields -; f-foo-{hi,lo} msb/lsb parts of field f-foo -; -; -- Operands -- -; pcrelNaA PC-relative branch target (signed) -; pcabsNaA Absolute branch target (unsigned) -; -; [us]dispNaA [un]signed displacement -; [us]immN [un]signed immediate value -; addrNaA absolute address (unsigned) -; -; Additional prefixes may be used for special cases. - -(dnf f-major "major opcode" (all-mep-core-isas) 0 4) - -(dnf f-rn "register n" (all-mep-core-isas) 4 4) -(dnf f-rn3 "register 0-7" (all-mep-core-isas) 5 3) -(dnf f-rm "register m" (all-mep-core-isas) 8 4) -(dnf f-rl "register l" (all-mep-core-isas) 12 4) -(dnf f-sub2 "sub opcode (2 bits)" (all-mep-core-isas) 14 2) -(dnf f-sub3 "sub opcode (3 bits)" (all-mep-core-isas) 13 3) -(dnf f-sub4 "sub opcode (4 bits)" (all-mep-core-isas) 12 4) -(dnf f-ext "extended field" (all-mep-core-isas) 16 8) -(dnf f-ext4 "extended field 16:4" (all-mep-core-isas) 16 4) -(dnf f-ext62 "extended field 20:2" (all-mep-core-isas) 20 2) -(dnf f-crn "copro register n" (all-mep-core-isas) 4 4) - -(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f) -(df f-csrn-lo "cr lo 4u8" (all-mep-core-isas) 8 4 UINT #f #f) -(define-multi-ifield - (name f-csrn) - (comment "control reg") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-csrn-hi f-csrn-lo) - (insert (sequence () - (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf)) - (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4)))) - (extract (set (ifield f-csrn) - (or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo)))) - ) - -(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f) -(df f-crnx-lo "crx lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) -(define-multi-ifield - (name f-crnx) - (comment "copro register n (0-31)") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-crnx-hi f-crnx-lo) - (insert (sequence () - (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf)) - (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4)))) - (extract (set (ifield f-crnx) - (or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo)))) - ) - -; Miscellaneous fields. - -(define-pmacro (dnfb n) - (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1)) - -; Define small fields used throughout the instruction set description. -; Each field (eg. `f-N') is at single bit field at position N. - -(dnfb 0) -(dnfb 1) -(dnfb 2) -(dnfb 3) -(dnfb 4) -(dnfb 5) -(dnfb 6) -(dnfb 7) -(dnfb 8) -(dnfb 9) -(dnfb 10) -(dnfb 11) -(dnfb 12) -(dnfb 13) -(dnfb 14) -(dnfb 15) -(dnfb 16) -(dnfb 17) -(dnfb 18) -(dnfb 19) -(dnfb 20) -(dnfb 21) -(dnfb 22) -(dnfb 23) -(dnfb 24) -(dnfb 25) -(dnfb 26) -(dnfb 27) -(dnfb 28) -(dnfb 29) -(dnfb 30) -(dnfb 31) - -; Branch/Jump target addresses - -(df f-8s8a2 "pc-rel addr (8 bits)" (all-mep-core-isas PCREL-ADDR) 8 7 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-12s4a2 "pc-rel addr (12 bits)" (all-mep-core-isas PCREL-ADDR) 4 11 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT - ((value pc) (sra SI (sub SI value pc) 1)) - ((value pc) (add SI (sll SI value 1) pc))) - -(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16 INT #f #f) -(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR) 5 7 UINT #f #f) -(define-multi-ifield - (name f-24s5a2n) - (comment "pc-rel addr (24 bits align 2)") - (attrs all-mep-core-isas PCREL-ADDR) - (mode INT) - (subfields f-24s5a2n-hi f-24s5a2n-lo) - (insert (sequence () - (set (ifield f-24s5a2n) - (sub (ifield f-24s5a2n) pc)) - (set (ifield f-24s5a2n-lo) - (srl (and (ifield f-24s5a2n) #xfe) 1)) - (set (ifield f-24s5a2n-hi) - (sra INT (ifield f-24s5a2n) 8)))) - (extract (set (ifield f-24s5a2n) - (add SI (or (sll (ifield f-24s5a2n-hi) 8) - (sll (ifield f-24s5a2n-lo) 1)) - pc))) - ) - -(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas) 5 7 UINT #f #f) -(define-multi-ifield - (name f-24u5a2n) - (comment "abs jump target (24 bits, alignment 2)") - (attrs all-mep-core-isas ABS-ADDR) - (mode UINT) - (subfields f-24u5a2n-hi f-24u5a2n-lo) - (insert (sequence () - (set (ifield f-24u5a2n-lo) - (srl (and (ifield f-24u5a2n) #xff) 1)) - (set (ifield f-24u5a2n-hi) - (srl (ifield f-24u5a2n) 8)) - )) - (extract (set (ifield f-24u5a2n) - (or (sll (ifield f-24u5a2n-hi) 8) - (sll (ifield f-24u5a2n-lo) 1)))) - ) - -; Displacement fields. - -(df f-2u6 "SAR offset (2 bits)" (all-mep-core-isas) 6 2 UINT #f #f) -(df f-7u9 "tp-rel b (7 bits)" (all-mep-core-isas) 9 7 UINT #f #f) -(df f-7u9a2 "tp-rel h (7 bits)" (all-mep-core-isas) 9 6 UINT - ((value pc) (srl SI value 1)) - ((value pc) (sll SI value 1))) -(df f-7u9a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas) 9 5 UINT - ((value pc) (srl SI value 2)) - ((value pc) (sll SI value 2))) -(df f-16s16 "general 16-bit s-val" (all-mep-core-isas) 16 16 INT #f #f) - -; Immediate fields. - -(df f-2u10 "swi level (2 bits)" (all-mep-core-isas) 10 2 UINT #f #f) -(df f-3u5 "bit offset (3 bits)" (all-mep-core-isas) 5 3 UINT #f #f) -(df f-4u8 "bCC const (4 bits)" (all-mep-core-isas) 8 4 UINT #f #f) -(df f-5u8 "slt & shifts (5 bits)" (all-mep-core-isas) 8 5 UINT #f #f) -(df f-5u24 "clip immediate (5 bits)" (all-mep-core-isas) 24 5 UINT #f #f) -(df f-6s8 "add immediate (6 bits)" (all-mep-core-isas) 8 6 INT #f #f) -(df f-8s8 "add imm (8 bits)" (all-mep-core-isas) 8 8 INT #f #f) -(df f-16u16 "general 16-bit u-val" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-12u16 "cmov fixed 1" (all-mep-core-isas) 16 12 UINT #f #f) -(df f-3u29 "cmov fixed 2" (all-mep-core-isas) 29 3 UINT #f #f) - - -; These are all for the coprocessor opcodes - -; The field is like IJKiiiiiii where I and J are toggled if K is set, -; for compatibility with older cores. -(define-pmacro (compute-cdisp10 val) - (cond SI - ((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200) - (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400)) - (else - (cond SI ((and SI val #x80) (xor SI val #x300)) (else val))) - ) - ) -(define-pmacro (extend-cdisp10 val) - (cond SI - ((and SI (compute-cdisp10 val) #x200) - (sub (and SI (compute-cdisp10 val) #x3ff) #x400)) - (else - (and SI (compute-cdisp10 val) #x3ff)) - ) - ) - -(df f-cdisp10 "cop imm10" (all-mep-core-isas) 22 10 INT - ((value pc) (extend-cdisp10 value)) - ((value pc) (extend-cdisp10 value)) - ) - -; Non-contiguous fields. - -(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas) 8 6 UINT #f #f) -(define-multi-ifield - (name f-24u8a4n) - (comment "absolute 24-bit address") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-24u8a4n-hi f-24u8a4n-lo) - (insert (sequence () - (set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8)) - (set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2)))) - (extract (set (ifield f-24u8a4n) - (or (sll (ifield f-24u8a4n-hi) 8) - (sll (ifield f-24u8a4n-lo) 2)))) - ) - -(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(df f-24u8n-lo "24u8n lo 8u8" (all-mep-core-isas) 8 8 UINT #f #f) -(define-multi-ifield - (name f-24u8n) - (comment "24-bit constant") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-24u8n-hi f-24u8n-lo) - (insert (sequence () - (set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8)) - (set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff)))) - (extract (set (ifield f-24u8n) - (or (sll (ifield f-24u8n-hi) 8) - (ifield f-24u8n-lo)))) - ) - -(df f-24u4n-hi "24u4n hi 8u4" (all-mep-core-isas) 4 8 UINT #f #f) -(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f) -(define-multi-ifield - (name f-24u4n) - (comment "coprocessor code") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-24u4n-hi f-24u4n-lo) - (insert (sequence () - (set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16)) - (set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff)))) - (extract (set (ifield f-24u4n) - (or (sll (ifield f-24u4n-hi) 16) - (ifield f-24u4n-lo)))) - ) - -(define-multi-ifield - (name f-callnum) - (comment "system call number field") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-5 f-6 f-7 f-11) - (insert (sequence () - (set (ifield f-5) (and (srl (ifield f-callnum) 3) 1)) - (set (ifield f-6) (and (srl (ifield f-callnum) 2) 1)) - (set (ifield f-7) (and (srl (ifield f-callnum) 1) 1)) - (set (ifield f-11) (and (ifield f-callnum) 1)))) - (extract (set (ifield f-callnum) - (or (sll (ifield f-5) 3) - (or (sll (ifield f-6) 2) - (or (sll (ifield f-7) 1) - (ifield f-11)))))) - ) - -(df f-ccrn-hi "ccrn hi 2u28" (all-mep-core-isas) 28 2 UINT #f #f) -(df f-ccrn-lo "ccrn lo 4u4" (all-mep-core-isas) 4 4 UINT #f #f) -(define-multi-ifield - (name f-ccrn) - (comment "Coprocessor register number field") - (attrs all-mep-core-isas) - (mode UINT) - (subfields f-ccrn-hi f-ccrn-lo) - (insert (sequence () - (set (ifield f-ccrn-hi) (and (srl (ifield f-ccrn) 4) #x3)) - (set (ifield f-ccrn-lo) (and (ifield f-ccrn) #xf)))) - (extract (set (ifield f-ccrn) - (or (sll (ifield f-ccrn-hi) 4) - (ifield f-ccrn-lo)))) - ) - -; Operands. - -;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct -;; operation. The others are mostly kept for backwards compatibility, -;; although they do affect the dummy prototypes in -;; gcc/config/mep/intrinsics.h. -(define-attr - (type enum) - (for operand) - (name CDATA) - (comment "datatype to use for C intrinsics mapping") - (values LABEL REGNUM FMAX_FLOAT FMAX_INT - POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT) - (default LONG)) - -(define-attr - (type enum) - (for insn) - (name CPTYPE) - (comment "datatype to use for coprocessor values") - (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI) - (default CP_DATA_BUS_INT)) - -(define-attr - (type enum) - (for insn) - (name CRET) - ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed. - ;; FIRST - the first argument is the return value. - ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter. - (values VOID FIRST FIRSTCOPY) - (default VOID) - (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.")) - -(define-attr - (type integer) - (for operand) - (name ALIGN) - (comment "alignment of immediate operands") - (default 1)) - -(define-attr - (for operand) - (type boolean) - (name RELOC_IMPLIES_OVERFLOW) - (comment "Operand should not be considered as a candidate for relocs")) - -(define-attr - (for hardware) - (type boolean) - (name IS_FLOAT) - (comment "Register contains a floating point value")) - -(define-pmacro (dpop name commment attrib hwr field func) - (define-full-operand name comment attrib - hwr DFLT field ((parse func)) () ())) -(define-pmacro (dprp name commment attrib hwr field pafunc prfunc) - (define-full-operand name comment attrib - hwr DFLT field ((parse pafunc) (print prfunc)) () ())) - -(dnop r0 "register 0" (all-mep-core-isas) h-gpr 0) -(dnop rn "register Rn" (all-mep-core-isas) h-gpr f-rn) -(dnop rm "register Rm" (all-mep-core-isas) h-gpr f-rm) -(dnop rl "register Rl" (all-mep-core-isas) h-gpr f-rl) -(dnop rn3 "register 0-7" (all-mep-core-isas) h-gpr f-rn3) - -;; Variants of RM/RN with different CDATA attributes. See comment above -;; CDATA for more details. - -(dnop rma "register Rm holding pointer" (all-mep-core-isas (CDATA POINTER)) h-gpr f-rm) - -(dnop rnc "register Rn holding char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnuc "register Rn holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rns "register Rn holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnus "register Rn holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnl "register Rn holding long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn) -(dnop rnul "register Rn holding unsigned long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn) - -(dnop rn3c "register 0-7 holding unsigned char" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3uc "register 0-7 holding byte" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3s "register 0-7 holding unsigned short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3us "register 0-7 holding short" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3l "register 0-7 holding unsigned long" (all-mep-core-isas (CDATA LONG)) h-gpr f-rn3) -(dnop rn3ul "register 0-7 holding long" (all-mep-core-isas (CDATA ULONG)) h-gpr f-rn3) - - -(dnop lp "link pointer" (all-mep-core-isas) h-csr 1) -(dnop sar "shift amount register" (all-mep-core-isas) h-csr 2) -(dnop hi "high result" (all-mep-core-isas) h-csr 7) -(dnop lo "low result" (all-mep-core-isas) h-csr 8) -(dnop mb0 "modulo begin register 0" (all-mep-core-isas) h-csr 12) -(dnop me0 "modulo end register 0" (all-mep-core-isas) h-csr 13) -(dnop mb1 "modulo begin register 1" (all-mep-core-isas) h-csr 14) -(dnop me1 "modulo end register 1" (all-mep-core-isas) h-csr 15) -(dnop psw "program status word" (all-mep-core-isas) h-csr 16) -(dnop epc "exception prog counter" (all-mep-core-isas) h-csr 19) -(dnop exc "exception cause" (all-mep-core-isas) h-csr 20) -(dnop npc "nmi program counter" (all-mep-core-isas) h-csr 23) -(dnop dbg "debug register" (all-mep-core-isas) h-csr 24) -(dnop depc "debug exception pc" (all-mep-core-isas) h-csr 25) -(dnop opt "option register" (all-mep-core-isas) h-csr 26) -(dnop r1 "register 1" (all-mep-core-isas) h-gpr 1) -(dnop tp "tiny data area pointer" (all-mep-core-isas) h-gpr 13) -(dnop sp "stack pointer" (all-mep-core-isas) h-gpr 15) -(dprp tpr "TP register" (all-mep-core-isas) h-gpr 13 "tpreg" "tpreg") -(dprp spr "SP register" (all-mep-core-isas) h-gpr 15 "spreg" "spreg") - -(define-full-operand - csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr - DFLT f-csrn ((parse "csrn")) () () -) - -(dnop csrn-idx "control/special reg idx" (all-mep-core-isas) h-uint f-csrn) -(dnop crn64 "copro Rn (64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crn) -(dnop crn "copro Rn (32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crn) -(dnop crnx64 "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-crnx) -(dnop crnx "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr f-crnx) -(dnop ccrn "copro control reg CCRn" (all-mep-core-isas (CDATA REGNUM)) h-ccr f-ccrn) -(dnop cccc "copro flags" (all-mep-core-isas) h-uint f-rm) - -(dprp pcrel8a2 "pc-rel addr (8 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-8s8a2 "mep_align" "address") -(dprp pcrel12a2 "pc-rel addr (12 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-12s4a2 "mep_align" "address") -(dprp pcrel17a2 "pc-rel addr (17 bits)" (all-mep-core-isas (CDATA LABEL) RELAX) h-sint f-17s16a2 "mep_align" "address") -(dprp pcrel24a2 "pc-rel addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-sint f-24s5a2n "mep_align" "address") -(dprp pcabs24a2 "pc-abs addr (24 bits)" (all-mep-core-isas (CDATA LABEL)) h-uint f-24u5a2n "mep_alignu" "address") - -(dpop sdisp16 "displacement (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16") -(dpop simm16 "signed imm (16 bits)" (all-mep-core-isas) h-sint f-16s16 "signed16") -(dpop uimm16 "unsigned imm (16 bits)" (all-mep-core-isas) h-uint f-16u16 "unsigned16") -(dnop code16 "uci/dsp code (16 bits)" (all-mep-core-isas) h-uint f-16u16) - -(dnop udisp2 "SSARB addend (2 bits)" (all-mep-core-isas) h-sint f-2u6) -(dnop uimm2 "interrupt (2 bits)" (all-mep-core-isas) h-uint f-2u10) - -(dnop simm6 "add const (6 bits)" (all-mep-core-isas) h-sint f-6s8) -(dnop simm8 "mov const (8 bits)" (all-mep-core-isas RELOC_IMPLIES_OVERFLOW) - h-sint f-8s8) - -(dpop addr24a4 "sw/lw addr (24 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-24u8a4n "mep_alignu") -(dnop code24 "coprocessor code" (all-mep-core-isas) h-uint f-24u4n) - -(dnop callnum "system call number" (all-mep-core-isas) h-uint f-callnum) -(dnop uimm3 "bit immediate (3 bits)" (all-mep-core-isas) h-uint f-3u5) -(dnop uimm4 "bCC const (4 bits)" (all-mep-core-isas) h-uint f-4u8) -(dnop uimm5 "bit/shift val (5 bits)" (all-mep-core-isas) h-uint f-5u8) - -(dpop udisp7 "tp-rel b (7 bits)" (all-mep-core-isas) h-uint f-7u9 "unsigned7") -(dpop udisp7a2 "tp-rel h (7 bits)" (all-mep-core-isas (ALIGN 2)) h-uint f-7u9a2 "unsigned7") -(dpop udisp7a4 "tp/sp-rel w (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "unsigned7") -(dpop uimm7a4 "sp w-addend (7 bits)" (all-mep-core-isas (ALIGN 4)) h-uint f-7u9a4 "mep_alignu") - -(dnop uimm24 "immediate (24 bits)" (all-mep-core-isas) h-uint f-24u8n) - -(dnop cimm4 "cache immed'te (4 bits)" (all-mep-core-isas) h-uint f-rn) -(dnop cimm5 "clip immediate (5 bits)" (all-mep-core-isas) h-uint f-5u24) - -(dpop cdisp10 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") -(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") -(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") -(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint f-cdisp10 "cdisp10") - -; Special operand representing the various ways that the literal zero can be -; specified. -(define-full-operand - zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil - ((parse "zero")) () () -) - -; Attributes. - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_BIT_INSN) - (comment "optional bit manipulation instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_MUL_INSN) - (comment "optional 32-bit multiply instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_DIV_INSN) - (comment "optional 32-bit divide instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_DEBUG_INSN) - (comment "optional debug instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_LDZ_INSN) - (comment "optional leading zeroes instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_ABS_INSN) - (comment "optional absolute difference instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_AVE_INSN) - (comment "optional average instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_MINMAX_INSN) - (comment "optional min/max instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_CLIP_INSN) - (comment "optional clipping instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_SAT_INSN) - (comment "optional saturation instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_UCI_INSN) - (comment "optional UCI instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_DSP_INSN) - (comment "optional DSP instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_CP_INSN) - (comment "optional coprocessor-related instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_CP64_INSN) - (comment "optional coprocessor-related 64 data bit instruction")) - -(define-attr - (for insn) - (type boolean) - (name OPTIONAL_VLIW64) - (comment "optional vliw64 mode (vliw32 is default)")) - -(define-attr - (for insn) - (type enum) - (name STALL) - (attrs META) - (values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET - ADVCK MUL MULR DIV) - (default NONE) - (comment "gcc stall attribute")) - -(define-attr - (for insn) - (type string) - (name INTRINSIC) - (attrs META) - (comment "gcc intrinsic name")) - -(define-attr - (for insn) - (type enum) - (name SLOT) - (attrs META) - (values NONE C3 V1 V3 P0S P0 P1) - (default NONE) - (comment "coprocessor slot type")) - -(define-attr - (for insn) - (type boolean) - (name MAY_TRAP) - (comment "instruction may generate an exception")) - -; Attributes for scheduling restrictions in vliw mode - -(define-attr - (for insn) - (type boolean) - (name VLIW_ALONE) - (comment "instruction can be scheduled alone in vliw mode")) - -(define-attr - (for insn) - (type boolean) - (name VLIW_NO_CORE_NOP) - (comment "there is no corresponding nop core instruction")) - -(define-attr - (for insn) - (type boolean) - (name VLIW_NO_COP_NOP) - (comment "there is no corresponding nop coprocessor instruction")) - -(define-attr - (for insn) - (type boolean) - (name VLIW64_NO_MATCHING_NOP) - (comment "there is no corresponding nop coprocessor instruction")) -(define-attr - (for insn) - (type boolean) - (name VLIW32_NO_MATCHING_NOP) - (comment "there is no corresponding nop coprocessor instruction")) - -(define-attr - (for insn) - (type boolean) - (name VOLATILE) - (comment "Insn is volatile.")) - -(define-attr - (for insn) - (type integer) - (name LATENCY) - (comment "The latency of this insn, used for scheduling as an intrinsic in gcc") - (default 0)) - -; The MeP config tool will edit this. -(define-attr - (type enum) - (for insn) - (name CONFIG) - (values NONE ; config-attr-start - default - ) ; config-attr-end -) - - -; Enumerations. - -(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_ - f-major - (.map .str (.iota 16)) -) - - -(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa) - (define-insn - (name xname) - (comment xcomment) - (.splice attrs (.unsplice xattrs) (ISA isa)) - (syntax xsyntax) - (format xformat) - (semantics xsemantics) - (.splice timing (.unsplice xtiming)) - ) -) - -(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa) - (dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit) -) - -; For making profiling calls and dynamic configuration -(define-pmacro (cg-profile caller callee) - (c-call "cg_profile" caller callee) -) -; For dynamic configuration only -(define-pmacro (cg-profile-jump caller callee) - (c-call "cg_profile_jump" caller callee) -) - -; For defining Core Instructions -(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming) - (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list) -) -(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit) - (dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list) -) - -; For defining Coprocessor Instructions -;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop) -;) - -;; flag setting macro -(define-pmacro (set-bit xop xbitnum xval) - (set xop (or - (and xop (inv (sll 1 xbitnum))) - (and (sll 1 xbitnum) (sll xval xbitnum))))) - -;; some flags we commonly use in vliw reasoning / mode-switching etc. -(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1)) -(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1)) -(define-pmacro (get-rm.lsb) (and rm 1)) -(define-pmacro (get-psw.om) (and (srl psw 12) 1)) -(define-pmacro (get-psw.nmi) (and (srl psw 9) 1)) -(define-pmacro (get-psw.iep) (and (srl psw 1) 1)) -(define-pmacro (get-psw.ump) (and (srl psw 3) 1)) -(define-pmacro (get-epc.etom) (and epc 1)) -(define-pmacro (get-npc.ntom) (and npc 1)) -(define-pmacro (get-lp.ltom) (and lp 1)) - -(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval)) -(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval)) -(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval)) -(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval)) -(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval)) - - -;; the "3 way switch" depending on our current operating mode and vliw status flags -(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl) - (cond - ((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl) - ((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl) - (else core-rtl))) - -;; the varying-pcrel idiom -(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc) - (core-vliw-switch (set xtarg (add pc xa)) - (set xtarg (add pc xb)) - (set xtarg (add pc xc)))) - -;; the increasing-alignment idiom in branch displacements -(define-pmacro (set-vliw-alignment-modified xtarg zaddr) - (core-vliw-switch (set xtarg (and zaddr (inv 1))) - (set xtarg (and zaddr (inv 3))) - (set xtarg (and zaddr (inv 7))))) - -;; the increasing-alignment idiom in option-only form -(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr) - (if (get-opt.vliw32) - (set xtarg (and zaddr (inv 3))) - (set xtarg (and zaddr (inv 7))))) - - - -; pmacros needed for coprocessor modulo addressing. - -; Taken from supplement ``The operation of the modulo addressing'' in -; Toshiba documentation rev 2.2, p. 34. - -(define-pmacro (compute-mask0) - (sequence SI ((SI temp)) - (set temp (or mb0 me0)) - (srl (const SI -1) (c-call SI "do_ldz" temp)))) - -(define-pmacro (mod0 immed) - (sequence SI ((SI modulo-mask)) - (set modulo-mask (compute-mask0)) - (if SI (eq (and rma modulo-mask) me0) - (or (and rma (inv modulo-mask)) mb0) - (add rma (ext SI immed))))) - -(define-pmacro (compute-mask1) - (sequence SI ((SI temp)) - (set temp (or mb1 me1)) - (srl (const SI -1) (c-call SI "do_ldz" temp)))) - -(define-pmacro (mod1 immed) - (sequence SI ((SI modulo-mask)) - (set modulo-mask (compute-mask1)) - (if SI (eq (and rma modulo-mask) me1) - (or (and rma (inv modulo-mask)) mb1) - (add rma (ext SI immed))))) - - -; Instructions. - -; A pmacro for use in semantic bodies of unimplemented insns. -(define-pmacro (unimp mnemonic) (nop)) - -; Core specific instructions -; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator -(include "mep-c5.cpu") ; -- exposed by MeP-Integrator - -; Load/store instructions. - -(dnci sb "store byte (register indirect)" ((STALL STORE)) - "sb $rnc,($rma)" - (+ MAJ_0 rnc rma (f-sub4 8)) - (sequence () - (c-call VOID "check_write_to_text" rma) - (set (mem UQI rma) (and rnc #xff))) - ((mep (unit u-use-gpr (in usereg rnc)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sh "store half-word (register indirect)" ((STALL STORE)) - "sh $rns,($rma)" - (+ MAJ_0 rns rma (f-sub4 9)) - (sequence () - (c-call VOID "check_write_to_text" (and rma (inv 1))) - (set (mem UHI (and rma (inv 1))) (and rns #xffff))) - ((mep (unit u-use-gpr (in usereg rns)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sw "store word (register indirect)" ((STALL STORE)) - "sw $rnl,($rma)" - (+ MAJ_0 rnl rma (f-sub4 10)) - (sequence () - (c-call VOID "check_write_to_text" (and rma (inv 3))) - (set (mem USI (and rma (inv 3))) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lb $rnc,($rma)" - (+ MAJ_0 rnc rma (f-sub4 12)) - (set rnc (ext SI (mem QI rma))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnc))))) - -(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lh $rns,($rma)" - (+ MAJ_0 rns rma (f-sub4 13)) - (set rns (ext SI (mem HI (and rma (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rns))))) - -(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,($rma)" - (+ MAJ_0 rnl rma (f-sub4 14)) - (set rnl (mem SI (and rma (inv 3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - -(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lbu $rnuc,($rma)" - (+ MAJ_0 rnuc rma (f-sub4 11)) - (set rnuc (zext SI (mem UQI rma))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnuc))))) - -(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2)) - "lhu $rnus,($rma)" - (+ MAJ_0 rnus rma (f-sub4 15)) - (set rnus (zext SI (mem UHI (and rma (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnus))))) - -(dnci sw-sp "store word (sp relative)" ((STALL STORE)) - "sw $rnl,$udisp7a4($spr)" - (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2)) - (sequence () - (c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3))) - (set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-use-gpr (in usereg sp)) - (unit u-exec)))) - - -(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,$udisp7a4($spr)" - (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3)) - (set rnl (mem SI (and (add udisp7a4 sp) (inv 3)))) - ((mep (unit u-use-gpr (in usereg sp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - -(dnci sb-tp "store byte (tp relative)" ((STALL STORE)) - "sb $rn3c,$udisp7($tpr)" - (+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7) - (sequence () - (c-call VOID "check_write_to_text" (add (zext SI udisp7) tp)) - (set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff))) - ((mep (unit u-use-gpr (in usereg rn3c)) - (unit u-use-gpr (in usereg tp)) - (unit u-exec)))) - -(dnci sh-tp "store half-word (tp relative)" ((STALL STORE)) - "sh $rn3s,$udisp7a2($tpr)" - (+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0)) - (sequence () - (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1))) - (set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff))) - ((mep (unit u-use-gpr (in usereg rn3s)) - (unit u-use-gpr (in usereg tp)) - (unit u-exec)))) - -(dnci sw-tp "store word (tp relative)" ((STALL STORE)) - "sw $rn3l,$udisp7a4($tpr)" - (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2)) - (sequence () - (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3))) - (set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l)) - ((mep (unit u-use-gpr (in usereg rn3l)) - (unit u-use-gpr (in usereg tp)) - (unit u-exec)))) - -(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lb $rn3c,$udisp7($tpr)" - (+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7) - (set rn3c (ext SI (mem QI (add (zext SI udisp7) tp)))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3c))))) - -(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lh $rn3s,$udisp7a2($tpr)" - (+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0)) - (set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3s))))) - -(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lw $rn3l,$udisp7a4($tpr)" - (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3)) - (set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3)))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3l))))) - -(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lbu $rn3uc,$udisp7($tpr)" - (+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7) - (set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp)))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3uc))))) - -(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2)) - "lhu $rn3us,$udisp7a2($tpr)" - (+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1)) - (set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))))) - ((mep (unit u-use-gpr (in usereg tp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn3us))))) - -(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE)) - "sb $rnc,$sdisp16($rma)" - (+ MAJ_12 rnc rma (f-sub4 8) sdisp16) - (sequence () - (c-call VOID "check_write_to_text" (add rma (ext SI sdisp16))) - (set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff))) - ((mep (unit u-use-gpr (in usereg rnc)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE)) - "sh $rns,$sdisp16($rma)" - (+ MAJ_12 rns rma (f-sub4 9) sdisp16) - (sequence () - (c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1))) - (set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff))) - ((mep (unit u-use-gpr (in usereg rns)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sw16 "store word (16 bit displacement)" ((STALL STORE)) - "sw $rnl,$sdisp16($rma)" - (+ MAJ_12 rnl rma (f-sub4 10) sdisp16) - (sequence () - (c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3))) - (set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lb $rnc,$sdisp16($rma)" - (+ MAJ_12 rnc rma (f-sub4 12) sdisp16) - (set rnc (ext SI (mem QI (add rma (ext SI sdisp16))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnc))))) - -(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lh $rns,$sdisp16($rma)" - (+ MAJ_12 rns rma (f-sub4 13) sdisp16) - (set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rns))))) - -(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,$sdisp16($rma)" - (+ MAJ_12 rnl rma (f-sub4 14) sdisp16) - (set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - -(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lbu $rnuc,$sdisp16($rma)" - (+ MAJ_12 rnuc rma (f-sub4 11) sdisp16) - (set rnuc (zext SI (mem QI (add rma (ext SI sdisp16))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnuc))))) - -(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2)) - "lhu $rnus,$sdisp16($rma)" - (+ MAJ_12 rnus rma (f-sub4 15) sdisp16) - (set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-load-gpr (out loadreg rnus))))) - -(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE)) - "sw $rnl,($addr24a4)" - (+ MAJ_14 rnl addr24a4 (f-sub2 2)) - (sequence () - (c-call VOID "check_write_to_text" (zext SI addr24a4)) - (set (mem SI (zext SI addr24a4)) rnl)) - ((mep (unit u-use-gpr (in usereg rnl)) - (unit u-exec)))) - -(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2)) - "lw $rnl,($addr24a4)" - (+ MAJ_14 rnl addr24a4 (f-sub2 3)) - (set rnl (mem SI (zext SI addr24a4))) - ((mep (unit u-exec) - (unit u-load-gpr (out loadreg rnl))))) - - -; Extension instructions. - -(dnci extb "sign extend byte" () - "extb $rn" - (+ MAJ_1 rn (f-rm 0) (f-sub4 13)) - (set rn (ext SI (and QI rn #xff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci exth "sign extend half-word" () - "exth $rn" - (+ MAJ_1 rn (f-rm 2) (f-sub4 13)) - (set rn (ext SI (and HI rn #xffff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci extub "zero extend byte" () - "extub $rn" - (+ MAJ_1 rn (f-rm 8) (f-sub4 13)) - (set rn (zext SI (and rn #xff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci extuh "zero extend half-word" () - "extuh $rn" - (+ MAJ_1 rn (f-rm 10) (f-sub4 13)) - (set rn (zext SI (and rn #xffff))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Shift amount manipulation instructions. - -(dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE) - "ssarb $udisp2($rm)" - (+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12)) - (if (c-call BI "big_endian_p") - (set sar (zext SI (mul (and (add udisp2 rm) 3) 8))) - (set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8))))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Move instructions. - -(dnci mov "move" () - "mov $rn,$rm" - (+ MAJ_0 rn rm (f-sub4 0)) - (set rn rm) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci movi8 "move 8-bit immediate" () - "mov $rn,$simm8" - (+ MAJ_5 rn simm8) - (set rn (ext SI simm8)) - ()) - -(dnci movi16 "move 16-bit immediate" () - "mov $rn,$simm16" - (+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16) - (set rn (ext SI simm16)) - ()) - -(dnci movu24 "move 24-bit unsigned immediate" () - "movu $rn3,$uimm24" - (+ MAJ_13 (f-4 0) rn3 uimm24) - (set rn3 (zext SI uimm24)) - ()) - -(dnci movu16 "move 16-bit unsigned immediate" () - "movu $rn,$uimm16" - (+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16) - (set rn (zext SI uimm16)) - ()) - -(dnci movh "move high 16-bit immediate" () - "movh $rn,$uimm16" - (+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16) - (set rn (sll uimm16 16)) - ()) - - -; Arithmetic instructions. - -(dnci add3 "add three registers" () - "add3 $rl,$rn,$rm" - (+ MAJ_9 rn rm rl) - (set rl (add rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci add "add" () - "add $rn,$simm6" - (+ MAJ_6 rn simm6 (f-sub2 0)) - (set rn (add rn (ext SI simm6))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci add3i "add two registers and immediate" () - "add3 $rn,$spr,$uimm7a4" - (+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0)) - (set rn (add sp (zext SI uimm7a4))) - ((mep (unit u-use-gpr (in usereg sp)) - (unit u-exec)))) - -(dnci advck3 "add overflow check" ((STALL ADVCK)) - "advck3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 7)) - (if (add-oflag rn rm 0) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sub "subtract" () - "sub $rn,$rm" - (+ MAJ_0 rn rm (f-sub4 4)) - (set rn (sub rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm))))) - -(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK)) - "sbvck3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 5)) - (if (sub-oflag rn rm 0) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci neg "negate" () - "neg $rn,$rm" - (+ MAJ_0 rn rm (f-sub4 1)) - (set rn (neg rm)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci slt3 "set if less than" () - "slt3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 2)) - (if (lt rn rm) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sltu3 "set less than unsigned" () - "sltu3 \\$0,$rn,$rm" - (+ MAJ_0 rn rm (f-sub4 3)) - (if (ltu rn rm) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci slt3i "set if less than immediate" () - "slt3 \\$0,$rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 1)) - (if (lt rn (zext SI uimm5)) - (set r0 1) - (set r0 0)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci sltu3i "set if less than unsigned immediate" () - "sltu3 \\$0,$rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 5)) - (if (ltu rn (zext SI uimm5)) - (set r0 1) - (set r0 0)) - ()) - -(dnci sl1ad3 "shift left one and add" ((STALL INT2)) - "sl1ad3 \\$0,$rn,$rm" - (+ MAJ_2 rn rm (f-sub4 6)) - (set r0 (add (sll rn 1) rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sl2ad3 "shift left two and add" ((STALL INT2)) - "sl2ad3 \\$0,$rn,$rm" - (+ MAJ_2 rn rm (f-sub4 7)) - (set r0 (add (sll rn 2) rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci add3x "three operand add (extended)" () - "add3 $rn,$rm,$simm16" - (+ MAJ_12 rn rm (f-sub4 0) simm16) - (set rn (add rm (ext SI simm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci slt3x "set if less than (extended)" () - "slt3 $rn,$rm,$simm16" - (+ MAJ_12 rn rm (f-sub4 2) simm16) - (if (lt rm (ext SI simm16)) - (set rn 1) - (set rn 0)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sltu3x "set if less than unsigned (extended)" () - "sltu3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 3) uimm16) - (if (ltu rm (zext SI uimm16)) - (set rn 1) - (set rn 0)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Logical instructions. - -(dnci or "bitwise or" () - "or $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 0)) - (set rn (or rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci and "bitwise and" () - "and $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 1)) - (set rn (and rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci xor "bitwise exclusive or" () - "xor $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 2)) - (set rn (xor rn rm)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci nor "bitwise negated or" () - "nor $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 3)) - (set rn (inv (or rn rm))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci or3 "or three operand" () - "or3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 4) uimm16) - (set rn (or rm (zext SI uimm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci and3 "and three operand" () - "and3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 5) uimm16) - (set rn (and rm (zext SI uimm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci xor3 "exclusive or three operand" () - "xor3 $rn,$rm,$uimm16" - (+ MAJ_12 rn rm (f-sub4 6) uimm16) - (set rn (xor rm (zext SI uimm16))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Shift instructions. - -(dnci sra "shift right arithmetic" ((STALL INT2)) - "sra $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 13)) - (set rn (sra rn (and rm #x1f))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci srl "shift right logical" ((STALL INT2)) - "srl $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 12)) - (set rn (srl rn (and rm #x1f))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci sll "shift left logical" ((STALL INT2)) - "sll $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 14)) - (set rn (sll rn (and rm #x1f))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - -(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI)) - "sra $rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 3)) - (set rn (sra rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci srli "shift right logical (immediate)" ((STALL SHIFTI)) - "srl $rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 2)) - (set rn (srl rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci slli "shift left logical (immediate)" ((STALL SHIFTI)) - "sll $rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 6)) - (set rn (sll rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci sll3 "three-register shift left logical" ((STALL INT2)) - "sll3 \\$0,$rn,$uimm5" - (+ MAJ_6 rn uimm5 (f-sub3 7)) - (set r0 (sll rn uimm5)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci fsft "field shift" ((STALL FSFT) VOLATILE) - "fsft $rn,$rm" - (+ MAJ_2 rn rm (f-sub4 15)) - (sequence ((DI temp) (QI shamt)) - (set shamt (and sar #x3f)) - (set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt)) - (set rn (subword SI (srl temp 32) 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Branch/jump instructions. - -(dnci bra "branch" (RELAXABLE) - "bra $pcrel12a2" - (+ MAJ_11 pcrel12a2 (f-15 0)) - (set-vliw-alignment-modified pc pcrel12a2) - ((mep (unit u-branch) - (unit u-exec)))) - -(dnci beqz "branch if equal zero" (RELAXABLE) - "beqz $rn,$pcrel8a2" - (+ MAJ_10 rn pcrel8a2 (f-15 0)) - (if (eq rn 0) - (set-vliw-alignment-modified pc pcrel8a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci bnez "branch if not equal zero" (RELAXABLE) - "bnez $rn,$pcrel8a2" - (+ MAJ_10 rn pcrel8a2 (f-15 1)) - (if (ne rn 0) - (set-vliw-alignment-modified pc pcrel8a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci beqi "branch equal immediate" (RELAXABLE) - "beqi $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2) - (if (eq rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci bnei "branch not equal immediate" (RELAXABLE) - "bnei $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2) - (if (ne rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci blti "branch less than immediate" (RELAXABLE) - "blti $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2) - (if (lt rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci bgei "branch greater than immediate" (RELAXABLE) - "bgei $rn,$uimm4,$pcrel17a2" - (+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2) - (if (ge rn (zext SI uimm4)) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-branch)))) - -(dnci beq "branch equal" () - "beq $rn,$rm,$pcrel17a2" - (+ MAJ_14 rn rm (f-sub4 1) pcrel17a2) - (if (eq rn rm) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci bne "branch not equal" () - "bne $rn,$rm,$pcrel17a2" - (+ MAJ_14 rn rm (f-sub4 5) pcrel17a2) - (if (ne rn rm) - (set-vliw-alignment-modified pc pcrel17a2)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE) - "bsr $pcrel12a2" - (+ MAJ_11 pcrel12a2 (f-15 1)) - (sequence () - (cg-profile pc pcrel12a2) - (set-vliw-modified-pcrel-offset lp 2 4 8) - (set-vliw-alignment-modified pc pcrel12a2)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci bsr24 "branch to subroutine (24 bit displacement)" () - "bsr $pcrel24a2" - (+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2) - (sequence () - (cg-profile pc pcrel24a2) - (set-vliw-modified-pcrel-offset lp 4 4 8) - (set-vliw-alignment-modified pc pcrel24a2)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci jmp "jump" () - "jmp $rm" - (+ MAJ_1 (f-rn 0) rm (f-sub4 14)) - (sequence () - (if (eq (get-psw.om) 0) - ;; core mode - (if (get-rm.lsb) - (sequence () - (set-psw.om 1) ;; enter VLIW mode - (set-vliw-aliignment-modified-by-option pc rm)) - (set pc (and rm (inv 1)))) - ;; VLIW mode - (if (get-rm.lsb) - (sequence () - (set-psw.om 0) ;; enter core mode - (set pc (and rm (inv 1)))) - (set-vliw-aliignment-modified-by-option pc rm))) - (cg-profile-jump pc rm)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci jmp24 "jump (24 bit target)" () - "jmp $pcabs24a2" - (+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2) - (sequence () - (set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2)) - (cg-profile-jump pc pcabs24a2)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci jsr "jump to subroutine" () - "jsr $rm" - (+ MAJ_1 (f-rn 0) rm (f-sub4 15)) - (sequence () - (cg-profile pc rm) - (set-vliw-modified-pcrel-offset lp 2 4 8) - (set-vliw-alignment-modified pc rm)) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci ret "return from subroutine" ((STALL RET)) - "ret" - (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2)) - (sequence () - (if (eq (get-psw.om) 0) - ;; core mode - (if (get-lp.ltom) ;; link-pointer "toggle mode" bit - (sequence () - (set-psw.om 1) ;; enter VLIW mode - (set-vliw-aliignment-modified-by-option pc lp)) - (set pc (and lp (inv 1)))) - ;; VLIW mode - (if (get-lp.ltom) ;; link-pointer "toggle mode" bit - (sequence () - (set-psw.om 0) ;; enter VLIW mode - (set pc (and lp (inv 1)))) - (set-vliw-aliignment-modified-by-option pc lp))) - (c-call VOID "notify_ret" pc)) - ((mep (unit u-exec) - (unit u-branch)))) - - -; Repeat instructions. - -(dnci repeat "repeat specified repeat block" () - "repeat $rn,$pcrel17a2" - (+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2) - (sequence () - (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8) - (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2) - (set (reg h-csr 6) rn)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci erepeat "endless repeat" () - "erepeat $pcrel17a2" - (+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2) - (sequence () - (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8) - (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2) - (set-rpe.elr 1) - ; rpc may be undefined for erepeat - ; use 1 to trigger repeat logic in the sim's main loop - (set (reg h-csr 6) 1)) - ()) - - -; Control instructions. - -;; special store variants - -(dnci stc_lp "store to control register lp" ((STALL STC)) - "stc $rn,\\$lp" - (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) - (set lp rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg lp)) - (unit u-exec)))) - -(dnci stc_hi "store to control register hi" ((STALL STC)) - "stc $rn,\\$hi" - (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) - (set hi rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg hi)) - (unit u-exec)))) - -(dnci stc_lo "store to control register lo" ((STALL STC)) - "stc $rn,\\$lo" - (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0)) - (set lo rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg lo)) - (unit u-exec)))) - -;; general store - -(dnci stc "store to control register" (VOLATILE (STALL STC)) - "stc $rn,$csrn" - (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0)) - (set csrn rn) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-store-ctrl-reg (out storereg csrn)) - (unit u-exec)))) - -;; special load variants - -(dnci ldc_lp "load from control register lp" ((STALL LDC)) - "ldc $rn,\\$lp" - (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) - (set rn lp) - ((mep (unit u-use-ctrl-reg (in usereg lp)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - - -(dnci ldc_hi "load from control register hi" ((STALL LDC)) - "ldc $rn,\\$hi" - (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) - (set rn hi) - ((mep (unit u-use-ctrl-reg (in usereg hi)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - -(dnci ldc_lo "load from control register lo" ((STALL LDC)) - "ldc $rn,\\$lo" - (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1)) - (set rn lo) - ((mep (unit u-use-ctrl-reg (in usereg lo)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - -;; general load - -(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2)) - "ldc $rn,$csrn" - (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1)) - (if (eq (ifield f-csrn) 0) - ;; loading from the pc - (set-vliw-modified-pcrel-offset rn 2 4 8) - ;; loading from something else - (set rn csrn)) - ((mep (unit u-use-ctrl-reg (in usereg csrn)) - (unit u-exec) - (unit u-load-gpr (out loadreg rn))))) - -(dnci di "disable interrupt" (VOLATILE) - "di" - (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0)) - ; clear psw.iec - (set psw (sll (srl psw 1) 1)) - ()) - -(dnci ei "enable interrupt" (VOLATILE) - "ei" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0)) - ; set psw.iec - (set psw (or psw 1)) - ()) - -(dnci reti "return from interrupt" ((STALL RET)) - "reti" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2)) - (if (eq (get-psw.om) 0) - ;; core operation mode - (if (get-psw.nmi) - ;; return from NMI - (if (get-npc.ntom) - ;; return in VLIW operation mode - (sequence () - (set-psw.om 1) - (set-vliw-aliignment-modified-by-option pc npc) - (set-psw.nmi 0)) - ;; return in core mode - (sequence () - (set pc (and npc (inv 1))) - (set-psw.nmi 0))) - ;; return from non-NMI - (if (get-epc.etom) - ;; return in VLIW mode - (sequence () - (set-psw.om 1) - (set-vliw-aliignment-modified-by-option pc epc) - (set-psw.umc (get-psw.ump)) - (set-psw.iec (get-psw.iep))) - ;; return in core mode - (sequence () - (set pc (and epc (inv 1))) - (set-psw.umc (get-psw.ump)) - (set-psw.iec (get-psw.iep))))) - ;; VLIW operation mode - ;; xxx undefined - (nop)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci halt "halt pipeline" (VOLATILE) - "halt" - (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2)) - ; set psw.halt - (set (raw-reg h-csr 16) (or psw (sll 1 11))) - ()) - -(dnci sleep "sleep pipeline" (VOLATILE) - "sleep" - (+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2)) - (c-call VOID "do_sleep") - ()) - -(dnci swi "software interrupt" (MAY_TRAP VOLATILE) - "swi $uimm2" - (+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6)) - (cond - ((eq uimm2 0) (set exc (or exc (sll 1 4)))) - ((eq uimm2 1) (set exc (or exc (sll 1 5)))) - ((eq uimm2 2) (set exc (or exc (sll 1 6)))) - ((eq uimm2 3) (set exc (or exc (sll 1 7))))) - ()) - -(dnci break "break exception" (MAY_TRAP VOLATILE) - "break" - (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2)) - (set pc (c-call USI "break_exception" pc)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci syncm "synchronise with memory" (VOLATILE) - "syncm" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1)) - (unimp "syncm") - ()) - -(dnci stcb "store in control bus space" (VOLATILE (STALL STCB)) - "stcb $rn,$uimm16" - (+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16) - (c-call VOID "do_stcb" rn uimm16) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec) - (unit u-stcb)))) - -(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3)) - "ldcb $rn,$uimm16" - (+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16) - (set rn (c-call SI "do_ldcb" uimm16)) - ((mep (unit u-ldcb) - (unit u-exec) - (unit u-ldcb-gpr (out loadreg rn))))) - - -; Bit manipulation instructions. -; The following instructions become the reserved instruction when the -; bit manipulation option is off. - -(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN) - "bsetm ($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0)) - (sequence () - (c-call "check_option_bit" pc) - (set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN) - "bclrm ($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1)) - (sequence () - (c-call "check_option_bit" pc) - (set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN) - "bnotm ($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2)) - (sequence () - (c-call "check_option_bit" pc) - (set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN) - "btstm \\$0,($rma),$uimm3" - (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3)) - (sequence () - (c-call "check_option_bit" pc) - (set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci tas "test and set" (OPTIONAL_BIT_INSN) - "tas $rn,($rma)" - (+ MAJ_2 rn rma (f-sub4 4)) - (sequence ((SI result)) - (c-call "check_option_bit" pc) - (set result (zext SI (mem UQI rma))) - (set (mem UQI rma) 1) - (set rn result)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -; Data cache instruction. - -(dnci cache "cache operations" (VOLATILE) - "cache $cimm4,($rma)" - (+ MAJ_7 cimm4 rma (f-sub4 4)) - (c-call VOID "do_cache" cimm4 rma pc) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -; Multiply instructions. -; These instructions become the RI when the 32-bit multiply -; instruction option is off. - -(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL)) - "mul $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 4)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (ext DI rn) (ext DI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - -(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL)) - "mulu $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 5)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (zext UDI rn) (zext UDI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - -(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "mulr $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 6)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (ext DI rn) (ext DI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - -(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "mulru $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 7)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (mul (zext UDI rn) (zext UDI rm))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - -(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL)) - "madd $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (ext DI rn) (ext DI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - -(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL)) - "maddu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (zext UDI rn) (zext UDI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply)))) - - -(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "maddr $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (ext DI rn) (ext DI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - -(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3)) - "maddru $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007)) - (sequence ((DI result)) - (c-call "check_option_mul" pc) - (set result (or (sll (zext DI hi) 32) (zext DI lo))) - (set result (add result (mul (zext UDI rn) (zext UDI rm)))) - (set hi (subword SI result 0)) - (set lo (subword SI result 1)) - (set rn (subword SI result 1))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-multiply) - (unit u-mul-gpr (out resultreg rn))))) - - -; Divide instructions. -; These instructions become the RI when the 32-bit divide instruction -; option is off. - -(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP) - "div $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 8)) - (sequence () - (c-call "check_option_div" pc) - (if (eq rm 0) - (set pc (c-call USI "zdiv_exception" pc)) - ; Special case described on p. 76. - (if (and (eq rn #x80000000) - (eq rm #xffffffff)) - (sequence () - (set lo #x80000000) - (set hi 0)) - (sequence () - (set lo (div rn rm)) - (set hi (mod rn rm)))))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-divide) - (unit u-branch)))) - -(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP) - "divu $rn,$rm" - (+ MAJ_1 rn rm (f-sub4 9)) - (sequence () - (c-call "check_option_div" pc) - (if (eq rm 0) - (set pc (c-call USI "zdiv_exception" pc)) - (sequence () - (set lo (udiv rn rm)) - (set hi (umod rn rm))))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-divide) - (unit u-branch)))) - - -; Debug functions. -; These instructions become the RI when the debug function option is -; off. - -(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN) - "dret" - (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3)) - (sequence () - (c-call "check_option_debug" pc) - ; set DBG.DM. - (set dbg (and dbg (inv (sll SI 1 15)))) - (set pc depc)) - ((mep (unit u-exec) - (unit u-branch)))) - -(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE) - "dbreak" - (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3)) - (sequence () - (c-call "check_option_debug" pc) - ; set DBG.DPB. - (set dbg (or dbg 1))) - ()) - - -; Leading zero instruction. - -(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2)) - "ldz $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0)) - (sequence () - (c-call "check_option_ldz" pc) - (set rn (c-call SI "do_ldz" rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec)))) - - -; Absolute difference instruction. - -(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2)) - "abs $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3)) - (sequence () - (c-call "check_option_abs" pc) - (set rn (abs (sub rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Average instruction. - -(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2)) - "ave $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2)) - (sequence () - (c-call "check_option_ave" pc) - (set rn (sra (add (add rn rm) 1) 1))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; MIN/MAX instructions. - -(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "min $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4)) - (sequence () - (c-call "check_option_minmax" pc) - (if (gt rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "max $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5)) - (sequence () - (c-call "check_option_minmax" pc) - (if (lt rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "minu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6)) - (sequence () - (c-call "check_option_minmax" pc) - (if (gtu rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2)) - "maxu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7)) - (sequence () - (c-call "check_option_minmax" pc) - (if (ltu rn rm) - (set rn rm))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Clipping instruction. - -(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2)) - "clip $rn,$cimm5" - (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0)) - (sequence ((SI min) (SI max)) - (c-call "check_option_clip" pc) - (set max (sub (sll 1 (sub cimm5 1)) 1)) - (set min (neg (sll 1 (sub cimm5 1)))) - (cond - ((eq cimm5 0) (set rn 0)) - ((gt rn max) (set rn max)) - ((lt rn min) (set rn min)))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2)) - "clipu $rn,$cimm5" - (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1)) - (sequence ((SI max)) - (c-call "check_option_clip" pc) - (set max (sub (sll 1 cimm5) 1)) - (cond - ((eq cimm5 0) (set rn 0)) - ((gt rn max) (set rn max)) - ((lt rn 0) (set rn 0)))) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; Saturation instructions. - -(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2)) - "sadd $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8)) - (sequence () - (c-call "check_option_sat" pc) - (if (add-oflag rn rm 0) - (if (nflag rn) - ; underflow - (set rn (neg (sll 1 31))) - ; overflow - (set rn (sub (sll 1 31) 1))) - (set rn (add rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2)) - "ssub $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10)) - (sequence () - (c-call "check_option_sat" pc) - (if (sub-oflag rn rm 0) - (if (nflag rn) - ; underflow - (set rn (neg (sll 1 31))) - ; overflow - (set rn (sub (sll 1 31) 1))) - (set rn (sub rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2)) - "saddu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9)) - (sequence () - (c-call "check_option_sat" pc) - (if (add-cflag rn rm 0) - (set rn (inv 0)) - (set rn (add rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - -(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2)) - "ssubu $rn,$rm" - (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11)) - (sequence () - (c-call "check_option_sat" pc) - (if (sub-cflag rn rm 0) - (set rn 0) - (set rn (sub rn rm)))) - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-use-gpr (in usereg rn)) - (unit u-exec)))) - - -; UCI and DSP options are defined in an external file. -; See `mep-sample-ucidsp.cpu' for a sample. - - -; Coprocessor instructions. - -(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "swcp $crn,($rma)" - (+ MAJ_3 crn rma (f-sub4 8)) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcp $crn,($rma)" - (+ MAJ_3 crn rma (f-sub4 9)) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcp $crn64,($rma)" - (+ MAJ_3 crn64 rma (f-sub4 10)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcp" rma crn64 pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcp $crn64,($rma)" - (+ MAJ_3 crn64 rma (f-sub4 11)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp" rma pc))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE)) - "swcpi $crn,($rma+)" - (+ MAJ_3 crn rma (f-sub4 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (add rma 4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcpi $crn,($rma+)" - (+ MAJ_3 crn rma (f-sub4 1)) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3)))) - (set rma (add rma 4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcpi $crn64,($rma+)" - (+ MAJ_3 crn64 rma (f-sub4 2)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcpi" (index-of rma) crn64 pc) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcpi $crn64,($rma+)" - (+ MAJ_3 crn64 rma (f-sub4 3)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcpi" (index-of rma) pc)) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE)) - "swcp $crn,$sdisp16($rma)" - (+ MAJ_15 crn rma (f-sub4 12) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (set (mem SI (and (add rma sdisp16) (inv SI 3))) crn)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcp $crn,$sdisp16($rma)" - (+ MAJ_15 crn rma (f-sub4 13) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and (add rma sdisp16) (inv SI 3))))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcp $crn64,$sdisp16($rma)" - (+ MAJ_15 crn64 rma (f-sub4 14) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call "do_smcp16" rma sdisp16 crn64 pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcp $crn64,$sdisp16($rma)" - (+ MAJ_15 crn64 rma (f-sub4 15) sdisp16) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "sbcpa $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" rma) - (set (mem QI rma) (and crn #xff)) - (set rma (add rma (ext SI cdisp10)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lbcpa $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI rma))) - (set rma (add rma (ext SI cdisp10)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "shcpa $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 1))) - (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) - (set rma (add rma (ext SI cdisp10a2)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lhcpa $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (and rma (inv SI 1))))) - (set rma (add rma (ext SI cdisp10a2)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE)) - "swcpa $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (add rma (ext SI cdisp10a4)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD)) - "lwcpa $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3)))) - (set rma (add rma (ext SI cdisp10a4)))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE)) - "smcpa $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD)) - "lmcpa $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc)) - (set rma rma)) ; reference as output for intrinsic generation - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - - -(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN) - "sbcpm0 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" rma) - (set (mem QI rma) (and crn #xff)) - (set rma (mod0 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN) - "lbcpm0 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI rma))) - (set rma (mod0 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN) - "shcpm0 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 1))) - (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) - (set rma (mod0 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN) - "lhcpm0 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod0 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN) - "swcpm0 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (mod0 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN) - "lwcpm0 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (set crn (mem SI (and rma (inv SI 3)))) - (set rma (mod0 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "smcpm0 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call VOID "check_write_to_text" rma) - (c-call "do_smcp" rma crn64 pc) - (set rma (mod0 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "lmcpm0 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp" rma pc)) - (set rma (mod0 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN) - "sbcpm1 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" rma) - (set (mem QI rma) (and crn #xff)) - (set rma (mod1 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN) - "lbcpm1 $crn,($rma+),$cdisp10" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem QI rma))) - (set rma (mod1 cdisp10))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN) - "shcpm1 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 1))) - (set (mem HI (and rma (inv SI 1))) (and crn #xffff)) - (set rma (mod1 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN) - "lhcpm1 $crn,($rma+),$cdisp10a2" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem HI (and rma (inv SI 1))))) - (set rma (mod1 cdisp10a2))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN) - "swcpm1 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (c-call VOID "check_write_to_text" (and rma (inv SI 3))) - (set (mem SI (and rma (inv SI 3))) crn) - (set rma (mod1 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN) - "lwcpm1 $crn,($rma+),$cdisp10a4" - (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4) - (sequence () - (c-call "check_option_cp" pc) - (set crn (ext SI (mem SI (and rma (inv SI 3))))) - (set rma (mod1 cdisp10a4))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "smcpm1 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (c-call "do_smcp" rma crn64 pc) - (c-call VOID "check_write_to_text" rma) - (set rma (mod1 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN) - "lmcpm1 $crn64,($rma+),$cdisp10a8" - (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8) - (sequence () - (c-call "check_option_cp" pc) - (c-call "check_option_cp64" pc) - (set crn64 (c-call DI "do_lmcp" rma pc)) - (set rma (mod1 cdisp10a8))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) - -(dnop cp_flag "branch condition register" (all-mep-isas) h-ccr 1) - -(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE) - "bcpeq $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (eq (xor cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE) - "bcpne $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (ne (xor cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE) - "bcpat $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (ne (and cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE) - "bcpaf $cccc,$pcrel17a2" - (+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2) - (sequence () - (c-call "check_option_cp" pc) - (if (eq (and cccc cp_flag) 0) - (set-vliw-alignment-modified pc pcrel17a2))) - ()) - -(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN) - "synccp" - (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1)) - (sequence () - (c-call "check_option_cp" pc) - (unimp "synccp")) - ()) - -(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN) - "jsrv $rm" - (+ MAJ_1 (f-rn 8) rm (f-sub4 15)) - (sequence () - (cg-profile pc rm) - (c-call "check_option_cp" pc) - (core-vliw-switch - - ;; in core operating mode - (sequence () - (set lp (or (add pc 2) 1)) - (set-vliw-aliignment-modified-by-option pc rm) - (set-psw.om 1)) ;; to VLIW operation mode - - ;; in VLIW32 operating mode - (sequence () - (set lp (or (add pc 4) 1)) - (set pc (and rm (inv 1))) - (set-psw.om 0)) ;; to core operation mode - - ;; in VLIW64 operating mode - (sequence () - (set lp (or (add pc 8) 1)) - (set pc (and rm (inv 1))) - (set-psw.om 0)))) ;; to core operation mode - ((mep (unit u-use-gpr (in usereg rm)) - (unit u-exec) - (unit u-branch)))) - -(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN) - "bsrv $pcrel24a2" - (+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2) - (sequence () - (cg-profile pc pcrel24a2) - (c-call "check_option_cp" pc) - (core-vliw-switch - - ;; in core operating mode - (sequence () - (set lp (or (add pc 4) 1)) - (set-vliw-aliignment-modified-by-option pc pcrel24a2) - (set-psw.om 1)) ;; to VLIW operation mode - - ;; in VLIW32 operating mode - (sequence () - (set lp (or (add pc 4) 1)) - (set pc (and pcrel24a2 (inv 1))) - (set-psw.om 0)) ;; to core operation mode - - ;; in VLIW64 operating mode - (sequence () - (set lp (or (add pc 8) 1)) - (set pc (and pcrel24a2 (inv 1))) - (set-psw.om 0)))) ;; to core operation mode - ((mep (unit u-exec) - (unit u-branch)))) - - -; An instruction for test instrumentation. -; Using a reserved opcode. - -(dnci sim-syscall "simulator system call" () - "--syscall--" - (+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0)) - (c-call "do_syscall" pc callnum) - ()) - -(define-pmacro (dnri n major minor) - (dnci (.sym ri- n) "reserved instruction" () - "--reserved--" - (+ major rn rm (f-sub4 minor)) - (set pc (c-call USI "ri_exception" pc)) - ((mep (unit u-exec) - (unit u-branch))))) - -(dnri 0 MAJ_0 6) -(dnri 1 MAJ_1 10) -(dnri 2 MAJ_1 11) -(dnri 3 MAJ_2 5) -(dnri 4 MAJ_2 8) -(dnri 5 MAJ_2 9) -(dnri 6 MAJ_2 10) -(dnri 7 MAJ_2 11) -(dnri 8 MAJ_3 4) -(dnri 9 MAJ_3 5) -(dnri 10 MAJ_3 6) -(dnri 11 MAJ_3 7) -(dnri 12 MAJ_3 12) -(dnri 13 MAJ_3 13) -(dnri 14 MAJ_3 14) -(dnri 15 MAJ_3 15) -(dnri 17 MAJ_7 7) -(dnri 20 MAJ_7 14) -(dnri 21 MAJ_7 15) -(dnri 22 MAJ_12 7) -(dnri 23 MAJ_14 13) -;(dnri 24 MAJ_15 3) -(dnri 26 MAJ_15 8) -; begin core-specific reserved insns -; end core-specific reserved insns - - -; Macro instructions. - -(dnmi nop "nop" - () - "nop" - (emit mov (rn 0) (rm 0))) - -; Emit the 16 bit form of these 32 bit insns when the displacement is zero. -; -(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS) - "sb $rnc,$zero($rma)" - (emit sb rnc rma)) - -(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS) - "sh $rns,$zero($rma)" - (emit sh rns rma)) - -(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS) - "sw $rnl,$zero($rma)" - (emit sw rnl rma)) - -(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS) - "lb $rnc,$zero($rma)" - (emit lb rnc rma)) - -(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS) - "lh $rns,$zero($rma)" - (emit lh rns rma)) - -(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS) - "lw $rnl,$zero($rma)" - (emit lw rnl rma)) - -(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS) - "lbu $rnuc,$zero($rma)" - (emit lbu rnuc rma)) - -(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS) - "lhu $rnus,$zero($rma)" - (emit lhu rnus rma)) - -(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS) - "swcp $crn,$zero($rma)" - (emit swcp crn rma)) - -(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS) - "lwcp $crn,$zero($rma)" - (emit lwcp crn rma)) - -(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS) - "smcp $crn64,$zero($rma)" - (emit smcp crn64 rma)) - -(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS) - "lmcp $crn64,$zero($rma)" - (emit lmcp crn64 rma)) diff --git a/binutils-2.24/cpu/mep-default.cpu b/binutils-2.24/cpu/mep-default.cpu deleted file mode 100644 index eac0f08d..00000000 --- a/binutils-2.24/cpu/mep-default.cpu +++ /dev/null @@ -1,27 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; This file serves as a wrapper to bring in the core description plus -; sample implementations of the UCI and DSP instructions. - -(include "mep-core.cpu") -(include "mep-ext-cop.cpu") diff --git a/binutils-2.24/cpu/mep-ext-cop.cpu b/binutils-2.24/cpu/mep-ext-cop.cpu deleted file mode 100644 index 1fd386a0..00000000 --- a/binutils-2.24/cpu/mep-ext-cop.cpu +++ /dev/null @@ -1,25 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -;; begin-user-isa-includes -(include "mep-ivc2.cpu") -;; end-user-isa-includes diff --git a/binutils-2.24/cpu/mep-fmax.cpu b/binutils-2.24/cpu/mep-fmax.cpu deleted file mode 100644 index e47d24f9..00000000 --- a/binutils-2.24/cpu/mep-fmax.cpu +++ /dev/null @@ -1,340 +0,0 @@ -; Toshiba MeP FMAX Coprocessor description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; This coprocessor requires only the 32 bit insns in the core. -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro fmax-core-isa () (ISA ext_core2)) -(define-pmacro all-fmax-isas () (ISA ext_core2)) -; end-isas - -;****************************************************************************** -; ifields -;------------------------------------------------------------------------------ -; opcodes -(dnf f-fmax-0-4 "opcode" (all-fmax-isas) 0 4) -(dnf f-fmax-4-4 "opcode" (all-fmax-isas) 4 4) -(dnf f-fmax-8-4 "opcode" (all-fmax-isas) 8 4) -(dnf f-fmax-12-4 "opcode" (all-fmax-isas) 12 4) -(dnf f-fmax-16-4 "opcode" (all-fmax-isas) 16 4) -(dnf f-fmax-20-4 "opcode" (all-fmax-isas) 20 4) -(dnf f-fmax-24-4 "opcode" (all-fmax-isas) 24 4) -(dnf f-fmax-28-1 "opcode" (all-fmax-isas) 28 1) -(dnf f-fmax-29-1 "opcode" (all-fmax-isas) 29 1) -(dnf f-fmax-30-1 "opcode" (all-fmax-isas) 30 1) -(dnf f-fmax-31-1 "opcode" (all-fmax-isas) 31 1) - -;------------------------------------------------------------------------------ -; FR registers -(define-multi-ifield - (name f-fmax-frd) - (comment "FRd register") - (attrs all-fmax-isas) - (mode UINT) - (subfields f-fmax-28-1 f-fmax-4-4) - (insert (sequence () - (set (ifield f-fmax-4-4) (and (ifield f-fmax-frd) #xf)) - (set (ifield f-fmax-28-1) (srl (ifield f-fmax-frd) 4)))) - (extract (set (ifield f-fmax-frd) - (or (sll (ifield f-fmax-28-1) 4) (ifield f-fmax-4-4)))) -) -(define-multi-ifield - (name f-fmax-frn) - (comment "FRn register") - (attrs all-fmax-isas) - (mode UINT) - (subfields f-fmax-29-1 f-fmax-20-4) - (insert (sequence () - (set (ifield f-fmax-20-4) (and (ifield f-fmax-frn) #xf)) - (set (ifield f-fmax-29-1) (srl (ifield f-fmax-frn) 4)))) - (extract (set (ifield f-fmax-frn) - (or (sll (ifield f-fmax-29-1) 4) (ifield f-fmax-20-4)))) -) -(define-multi-ifield - (name f-fmax-frm) - (comment "FRm register") - (attrs all-fmax-isas) - (mode UINT) - (subfields f-fmax-30-1 f-fmax-24-4) - (insert (sequence () - (set (ifield f-fmax-24-4) (and (ifield f-fmax-frm) #xf)) - (set (ifield f-fmax-30-1) (srl (ifield f-fmax-frm) 4)))) - (extract (set (ifield f-fmax-frm) - (or (sll (ifield f-fmax-30-1) 4) (ifield f-fmax-24-4)))) -) - -;------------------------------------------------------------------------------ -; Core General registers -(dnf f-fmax-rm "opcode" (all-fmax-isas) 8 4) - -;------------------------------------------------------------------------------ -; Condition opcodes enum -(define-normal-insn-enum fmax-cond "condition opcode enum" (all-fmax-isas) FMAX_ f-fmax-8-4 - ("f" "u" "e" "ue" "l" "ul" "le" "ule" - "fi" "ui" "ei" "uei" "li" "uli" "lei" "ulei") -) - -;****************************************************************************** -; Hardware -;------------------------------------------------------------------------------ -; FR registers - -; Given a coprocessor register number N, expand to a -; name/index pair: ($frN N) -(define-pmacro (-fmax-fr-reg-pair n) ((.sym "fr" n) n)) -(define-pmacro (-fmax-cr-reg-pair n) ((.sym "c" n) n)) - -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-fmax) - (comment "Floating point registers") - (attrs all-fmax-isas VIRTUAL IS_FLOAT) - (type register SF (32)) - (indices keyword "$" - (.splice (.unsplice (.map -fmax-fr-reg-pair (.iota 32))) - (.unsplice (.map -fmax-cr-reg-pair (.iota 32)))) - ) - (get (index) (c-call SF "fmax_fr_get_handler" index)) - (set (index newval) (c-call VOID "fmax_fr_set_handler" index newval)) -) - -;------------------------------------------------------------------------------ -; Control registers -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-fmax) - (comment "Coprocessor Identifier and Revision Register") - (attrs all-fmax-isas VIRTUAL) - (type register USI (16)) - (indices keyword "$" ( - ("cirr" 0) ("fcr0" 0) ("ccr0" 0) - ("cbcr" 1) ("fcr1" 1) ("ccr1" 1) - ("cerr" 15) ("fcr15" 15) ("ccr15" 15) - ) - ) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) -) - -;------------------------------------------------------------------------------ -; Misc -(define-hardware - (name h-fmax-compare-i-p) - (comment "flag") - (attrs all-fmax-isas) - (type register USI) -) - -;****************************************************************************** -; Operands -;------------------------------------------------------------------------------ -; FR Registers -(define-full-operand fmax-FRd "FRd" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ()) -(define-full-operand fmax-FRn "FRn" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ()) -(define-full-operand fmax-FRm "FRm" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frm ((parse "fmax_cr") (print "fmax_cr")) () ()) - -(define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ()) -(define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ()) - -;------------------------------------------------------------------------------ -; Control registers -(define-full-operand fmax-CCRn "CCRn" (all-fmax-isas (CDATA REGNUM)) h-ccr DFLT f-fmax-4-4 ((parse "fmax_ccr") (print "fmax_ccr")) () ()) - -(dnop fmax-CIRR "CIRR" (all-fmax-isas SEM-ONLY) h-ccr 0) -(dnop fmax-CBCR "CBCR" (all-fmax-isas SEM-ONLY) h-ccr 1) -(dnop fmax-CERR "CERR" (all-fmax-isas SEM-ONLY) h-ccr 15) - -;------------------------------------------------------------------------------ -; Core General Registers -(dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm) - -;------------------------------------------------------------------------------ -; misc -(dnop fmax-Compare-i-p "flag" (all-fmax-isas SEM-ONLY) h-fmax-compare-i-p f-nil) - -;****************************************************************************** -; Instructions -;------------------------------------------------------------------------------ -; Binary Arithmetic -(define-pmacro (fmax-binary-arith op opc sem) - (dni op - (.str op " FRd,FRn,FRm") - (all-fmax-isas MAY_TRAP) - (.str op " ${fmax-FRd},${fmax-FRn},${fmax-FRm}") - (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) (f-fmax-16-4 0) - fmax-FRn fmax-FRm (f-fmax-31-1 0)) - sem - () - ) -) - -(fmax-binary-arith fadds #x0 (set fmax-FRd (add fmax-FRn fmax-FRm))) -(fmax-binary-arith fsubs #x1 (set fmax-FRd (sub fmax-FRn fmax-FRm))) -(fmax-binary-arith fmuls #x2 (set fmax-FRd (mul fmax-FRn fmax-FRm))) -(fmax-binary-arith fdivs #x3 (set fmax-FRd (div fmax-FRn fmax-FRm))) - -;------------------------------------------------------------------------------ -; Unary Arithmetic -(define-pmacro (fmax-unary-arith op opc sem) - (dni op - (.str op " FRd,FRn") - (all-fmax-isas MAY_TRAP) - (.str op " ${fmax-FRd},${fmax-FRn}") - (+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) - (f-fmax-16-4 0) fmax-FRn (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0)) - sem - () - ) -) - -(fmax-unary-arith fsqrts #x4 (set fmax-FRd (sqrt fmax-FRn))) -(fmax-unary-arith fabss #x5 (set fmax-FRd (abs fmax-FRn))) -(fmax-unary-arith fnegs #x7 (set fmax-FRd (neg fmax-FRn))) -(fmax-unary-arith fmovs #x6 (set fmax-FRd fmax-FRn)) - -;------------------------------------------------------------------------------ -; Conversions -(define-pmacro (fmax-conv op opc1 opc2 opnd1 opnd2 sem) - (dni op - (.str op " FRd,FRn") - (all-fmax-isas MAY_TRAP) - (.str op " ${" opnd1 "},${" opnd2 "}") - (+ (f-fmax-0-4 #xF) opnd1 (f-fmax-8-4 opc1) (f-fmax-12-4 #x7) - (f-fmax-16-4 opc2) opnd2 (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0)) - sem - () - ) -) - -(fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_froundws" fmax-FRn))) -(fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ftruncws" fmax-FRn))) -(fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn))) -(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn))) -(fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn))) -(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF FPCONV-DEFAULT fmax-FRn-int))) - -;------------------------------------------------------------------------------ -; Comparisons -; -; Comparison with no exceptions -(define-pmacro (fmax-f-sem x y) (andif (gt x y) (lt x y))) ; do this to get exception detection -(define-pmacro (fmax-u-sem x y) (not (orif (lt x y) (orif (eq x y) (gt x y))))) -(define-pmacro (fmax-e-sem x y) (eq x y)) -(define-pmacro (fmax-ue-sem x y) (not (orif (lt x y) (gt x y)))) -(define-pmacro (fmax-l-sem x y) (lt x y)) -(define-pmacro (fmax-ul-sem x y) (not (orif (gt x y) (eq x y)))) -(define-pmacro (fmax-le-sem x y) (orif (lt x y) (eq x y))) -(define-pmacro (fmax-ule-sem x y) (not (gt x y))) - -(define-pmacro (fmax-comp cond suffix exceptions) - (dni (.sym fcmp cond suffix s) - (.str "fcmp" cond suffix "s FRn,FRm") - ;; Even though the instruction doesn't really trap if EXCEPTIONS - ;; is zero, we don't want gcc to put it in a repeat or erepeat - ;; block because of the hazards between fcmp instructions and - ;; anything that reads CBCR. - (all-fmax-isas MAY_TRAP) - (.str "fcmp" cond suffix "s ${fmax-FRn},${fmax-FRm}") - (+ (f-fmax-0-4 #xF) (f-fmax-4-4 0) (.sym FMAX_ cond suffix) (f-fmax-12-4 #x7) - (f-fmax-16-4 #x2) (f-fmax-28-1 0) fmax-FRn fmax-FRm (f-fmax-31-1 0)) - (sequence () - (set fmax-Compare-i-p exceptions) - (set fmax-CBCR ((.sym fmax- cond -sem) fmax-FRn fmax-FRm)) - (set fmax-Compare-i-p 0) - ) - () - ) -) - -; Comparison with no exceptions -(fmax-comp f "" 0) -(fmax-comp u "" 0) -(fmax-comp e "" 0) -(fmax-comp ue "" 0) -(fmax-comp l "" 0) -(fmax-comp ul "" 0) -(fmax-comp le "" 0) -(fmax-comp ule "" 0) - -; Comparison with exceptions -(fmax-comp f i 1) -(fmax-comp u i 1) -(fmax-comp e i 1) -(fmax-comp ue i 1) -(fmax-comp l i 1) -(fmax-comp ul i 1) -(fmax-comp le i 1) -(fmax-comp ule i 1) - -;------------------------------------------------------------------------------ -; Move to/from core registers -(dni cmov-frn-rm - "cmov FRn,Rm" - (all-fmax-isas (INTRINSIC "cmov1")) - "cmov ${fmax-FRd-int},${fmax-Rm}" - (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 0)) - (set fmax-FRd-int fmax-Rm) - () -) -(dni cmov-rm-frn - "cmov Rm,FRn" - (all-fmax-isas (INTRINSIC "cmov2")) - "cmov ${fmax-Rm},${fmax-FRd-int}" - (+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 1)) - (set fmax-Rm fmax-FRd-int) - () -) -(dni cmovc-ccrn-rm - "cmovc CCRn,Rm" - (all-fmax-isas (INTRINSIC "cmovc1")) - "cmovc ${fmax-CCRn},${fmax-Rm}" - (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 0)) - (set fmax-CCRn fmax-Rm) - () -) -(dni cmovc-rm-ccrn - "cmovc Rm,CCRn" - (all-fmax-isas (INTRINSIC "cmovc2")) - "cmovc ${fmax-Rm},${fmax-CCRn}" - (+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7) - (f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0) - (f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 1)) - (set fmax-Rm fmax-CCRn) - () -) diff --git a/binutils-2.24/cpu/mep-h1.cpu b/binutils-2.24/cpu/mep-h1.cpu deleted file mode 100644 index 31d4d056..00000000 --- a/binutils-2.24/cpu/mep-h1.cpu +++ /dev/null @@ -1,49 +0,0 @@ -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; Insns introduced for the MeP-h1 core -; -(dnci stcb_r "store in control bus space" (VOLATILE (MACH h1)) - "stcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 12)) - (c-call VOID "do_stcb" rn (and rma #xffff)) - ((mep (unit u-use-gpr (in usereg rn)) - (unit u-use-gpr (in usereg rma)) - (unit u-exec) - (unit u-stcb)))) - -(dnci ldcb_r "load from control bus space" (VOLATILE (MACH h1) (LATENCY 3)) - "ldcb $rn,($rma)" - (+ MAJ_7 rn rma (f-sub4 13)) - (set rn (c-call SI "do_ldcb" (and rma #xffff))) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-ldcb) - (unit u-exec) - (unit u-ldcb-gpr (out loadreg rn))))) - -(dnci pref "cache prefetch" ((MACH h1) VOLATILE) - "pref $cimm4,($rma)" - (+ MAJ_7 cimm4 rma (f-sub4 5)) - (sequence () - (c-call VOID "check_option_dcache" pc) - (c-call VOID "do_cache_prefetch" cimm4 rma pc)) - ((mep (unit u-use-gpr (in usereg rma)) - (unit u-exec)))) diff --git a/binutils-2.24/cpu/mep-ivc2.cpu b/binutils-2.24/cpu/mep-ivc2.cpu deleted file mode 100644 index f1d78660..00000000 --- a/binutils-2.24/cpu/mep-ivc2.cpu +++ /dev/null @@ -1,9777 +0,0 @@ -; Toshiba MeP IVC2 Coprocessor description. -*- scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -;------------------------------------------------------------------------------ -; MeP-Integrator will redefine the isa pmacros below to allow the bit widths -; specified below for each ME_MODULE using this coprocessor. -; IVC2 uses the isas as follows: -; C3 32 -; P0S 16 -; P0 48 -; P1 64 -;------------------------------------------------------------------------------ -; begin-isas -(define-pmacro ivc2-core-isa () (ISA ext_core1)) -(define-pmacro ivc2-16-isa () (ISA ext_cop1_16)) -(define-pmacro ivc2-32-isa () (ISA ext_cop1_32)) -(define-pmacro ivc2-48-isa () (ISA ext_cop1_48)) -(define-pmacro ivc2-64-isa () (ISA ext_cop1_64)) -(define-pmacro all-ivc2-isas () (ISA ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) -(define-pmacro ivc2-p0s-isa () (ISA ext_cop1_16)) -(define-pmacro ivc2-p0-isa () (ISA ext_cop1_48)) -(define-pmacro ivc2-p0s-p0-isa () (ISA ext_cop1_16,ext_cop1_48)) -(define-pmacro ivc2-p1-isa () (ISA ext_cop1_64)) -(define-pmacro ivc2-p0s-p1-isa () (ISA ext_cop1_16,ext_cop1_64)) -(define-pmacro ivc2-p0-p1-isa () (ISA ext_cop1_48,ext_cop1_64)) -(define-pmacro ivc2-p0s-p0-p1-isa () (ISA ext_cop1_16,ext_cop1_48,ext_cop1_64)) -(define-pmacro ivc2-c3-isa () (ISA ext_cop1_32)) -; end-isas - -; register definitions -; --------------------- -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-cr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-cr-ivc2) - (comment "64-bit coprocessor registers for ivc2 coprocessor") - (attrs VIRTUAL all-mep-core-isas (CDATA CP_DATA_BUS_INT)) - (type register DI (64)) - (set (index newval) (c-call VOID "h_cr64_set" index newval)) - (get (index) (c-call DI "h_cr64_get" index)) - (indices keyword "$c" (.map -reg-pair (.iota 8))) -) - -; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor. -; GDB will use the hardware table generated from this declaration. The operands use h-ccr -; from mep-core.cpu so that SID's semantic trace will be consistent between -; the core and the coprocessor but use parse/print handlers which reference the hardware table -; generated from this declarations -(define-hardware - (name h-ccr-ivc2) - (comment "Coprocessor control registers for ivc2 coprocessor") - (attrs VIRTUAL all-mep-isas) - (type register SI (32)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call SI "h_ccr_get" index)) - (indices keyword "" - (.splice - - ($csar0 0) - ($cc 1) - ($cofr0 4) - ($cofr1 5) - ($cofa0 6) - ($cofa1 7) - - ($csar1 15) - - ($acc0_0 16) - ($acc0_1 17) - ($acc0_2 18) - ($acc0_3 19) - ($acc0_4 20) - ($acc0_5 21) - ($acc0_6 22) - ($acc0_7 23) - - ($acc1_0 24) - ($acc1_1 25) - ($acc1_2 26) - ($acc1_3 27) - ($acc1_4 28) - ($acc1_5 29) - ($acc1_6 30) - ($acc1_7 31) - (.unsplice (.map -ccr-reg-pair (.iota 32))) - ) - ) -) - -(define-attr - (type bitset) - (for insn) - (name SLOTS) - (comment "slots for which this opcode is valid - c3, p0s, p0, p1") - (values CORE C3 P0S P0 P1) - (default CORE) - ) - -;----------------------------------------------------------------------------- -; macros for standard opcodes for each slot type - -; C3 -(dnf f-ivc2-2u4 "sub opcode field" (all-mep-isas) 4 2) -(dnf f-ivc2-3u4 "sub opcode field" (all-mep-isas) 4 3) -(dnf f-ivc2-8u4 "sub opcode field" (all-mep-isas) 4 8) -(df f-ivc2-8s4 "sub opcode field" (all-mep-isas) 4 8 INT #f #f) -(dnf f-ivc2-1u6 "sub opcode field" (all-mep-isas) 6 1) -(dnf f-ivc2-2u6 "sub opcode field" (all-mep-isas) 6 2) -(dnf f-ivc2-3u6 "sub opcode field" (all-mep-isas) 6 3) -(dnf f-ivc2-6u6 "sub opcode field" (all-mep-isas) 6 6) -(dnf f-ivc2-5u7 "sub opcode field" (all-mep-isas) 7 5) -(dnf f-ivc2-4u8 "sub opcode field" (all-mep-isas) 8 4) -(dnf f-ivc2-3u9 "sub opcode field" (all-mep-isas) 9 3) -(dnf f-ivc2-5u16 "sub opcode field" (all-mep-isas) 16 5) -(dnf f-ivc2-5u21 "sub opcode field" (all-mep-isas) 21 5) -(dnf f-ivc2-5u26 "sub opcode field" (all-mep-isas) 26 5) -(dnf f-ivc2-1u31 "sub opcode field" (all-mep-isas) 31 1) - -(dnf f-ivc2-4u16 "sub opcode field" (all-mep-isas) 16 4) -(dnf f-ivc2-4u20 "sub opcode field" (all-mep-isas) 20 4) -(dnf f-ivc2-4u24 "sub opcode field" (all-mep-isas) 24 4) -(dnf f-ivc2-4u28 "sub opcode field" (all-mep-isas) 28 4) - -; P0S/P0/P1 -(dnf f-ivc2-2u0 "sub opcode field" (all-mep-isas) 0 2) -(dnf f-ivc2-3u0 "sub opcode field" (all-mep-isas) 0 3) -(dnf f-ivc2-4u0 "sub opcode field" (all-mep-isas) 0 4) -(dnf f-ivc2-5u0 "sub opcode field" (all-mep-isas) 0 5) -(dnf f-ivc2-8u0 "sub opcode field" (all-mep-isas) 0 8) -(df f-ivc2-8s0 "sub opcode field" (all-mep-isas) 0 8 INT #f #f) -(dnf f-ivc2-6u2 "sub opcode field" (all-mep-isas) 2 6) -(dnf f-ivc2-5u3 "sub opcode field" (all-mep-isas) 3 5) -(dnf f-ivc2-4u4 "sub opcode field" (all-mep-isas) 4 4) -(dnf f-ivc2-3u5 "sub opcode field" (all-mep-isas) 5 3) -(dnf f-ivc2-5u8 "sub opcode field" (all-mep-isas) 8 5) -(dnf f-ivc2-4u10 "sub opcode field" (all-mep-isas) 10 4) -(dnf f-ivc2-3u12 "sub opcode field" (all-mep-isas) 12 3) -(dnf f-ivc2-5u13 "sub opcode field" (all-mep-isas) 13 5) -(dnf f-ivc2-2u18 "sub opcode field" (all-mep-isas) 18 2) -(dnf f-ivc2-5u18 "sub opcode field" (all-mep-isas) 18 5) -(dnf f-ivc2-8u20 "sub opcode field" (all-mep-isas) 20 8) -(df f-ivc2-8s20 "sub opcode field" (all-mep-isas) 20 8 INT #f #f) -(dnf f-ivc2-5u23 "sub opcode field" (all-mep-isas) 23 5) -(dnf f-ivc2-2u23 "sub opcode field" (all-mep-isas) 23 2) -(dnf f-ivc2-3u25 "sub opcode field" (all-mep-isas) 25 3) - -(dnmf f-ivc2-imm16p0 "16-bit immediate in P0/P1" (all-mep-isas) UINT - (f-ivc2-8u0 f-ivc2-8u20) - (sequence () ; insert - (set (ifield f-ivc2-8u0) (and (srl (ifield f-ivc2-imm16p0) 8) #xff)) - (set (ifield f-ivc2-8u20) (and (ifield f-ivc2-imm16p0) #xff)) - ) - (sequence () ; extract - (set (ifield f-ivc2-imm16p0) (or (ifield f-ivc2-8u20) - (sll (ifield f-ivc2-8u0) 8))) - ) - ) - -(dnmf f-ivc2-simm16p0 "16-bit immediate in P0/P1" (all-mep-isas) INT - (f-ivc2-8u0 f-ivc2-8u20) - (sequence () ; insert - (set (ifield f-ivc2-8u0) (and (srl (ifield f-ivc2-simm16p0) 8) #xff)) - (set (ifield f-ivc2-8u20) (and (ifield f-ivc2-simm16p0) #xff)) - ) - (sequence () ; extract - (set (ifield f-ivc2-simm16p0) (or (ifield f-ivc2-8u20) - (sll (ifield f-ivc2-8u0) 8))) - ) - ) - -(dnop ivc2_csar0 "ivc2_csar0" (all-ivc2-isas) h-ccr-ivc2 0) -(dnop ivc2_cc "ivc2_cc" (all-ivc2-isas) h-ccr-ivc2 1) -(dnop ivc2_cofr0 "ivc2_cofr0" (all-ivc2-isas) h-ccr-ivc2 4) -(dnop ivc2_cofr1 "ivc2_cofr1" (all-ivc2-isas) h-ccr-ivc2 5) -(dnop ivc2_cofa0 "ivc2_cofa0" (all-ivc2-isas) h-ccr-ivc2 6) -(dnop ivc2_cofa1 "ivc2_cofa1" (all-ivc2-isas) h-ccr-ivc2 7) - -(dnop ivc2_csar1 "ivc2_csar1" (all-ivc2-isas) h-ccr-ivc2 15) - -(dnop ivc2_acc0_0 "acc0_0" (all-ivc2-isas) h-ccr-ivc2 16) -(dnop ivc2_acc0_1 "acc0_1" (all-ivc2-isas) h-ccr-ivc2 17) -(dnop ivc2_acc0_2 "acc0_2" (all-ivc2-isas) h-ccr-ivc2 18) -(dnop ivc2_acc0_3 "acc0_3" (all-ivc2-isas) h-ccr-ivc2 19) -(dnop ivc2_acc0_4 "acc0_4" (all-ivc2-isas) h-ccr-ivc2 20) -(dnop ivc2_acc0_5 "acc0_5" (all-ivc2-isas) h-ccr-ivc2 21) -(dnop ivc2_acc0_6 "acc0_6" (all-ivc2-isas) h-ccr-ivc2 22) -(dnop ivc2_acc0_7 "acc0_7" (all-ivc2-isas) h-ccr-ivc2 23) - -(dnop ivc2_acc1_0 "acc1_0" (all-ivc2-isas) h-ccr-ivc2 24) -(dnop ivc2_acc1_1 "acc1_1" (all-ivc2-isas) h-ccr-ivc2 25) -(dnop ivc2_acc1_2 "acc1_2" (all-ivc2-isas) h-ccr-ivc2 26) -(dnop ivc2_acc1_3 "acc1_3" (all-ivc2-isas) h-ccr-ivc2 27) -(dnop ivc2_acc1_4 "acc1_4" (all-ivc2-isas) h-ccr-ivc2 28) -(dnop ivc2_acc1_5 "acc1_5" (all-ivc2-isas) h-ccr-ivc2 29) -(dnop ivc2_acc1_6 "acc1_6" (all-ivc2-isas) h-ccr-ivc2 30) -(dnop ivc2_acc1_7 "acc1_7" (all-ivc2-isas) h-ccr-ivc2 31) - -(dnop croc "$CRo C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u7) -(dnop crqc "$CRq C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u21) -(dnop crpc "$CRp C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u26) - -(dnop ivc-x-6-1 "filler" (all-mep-isas) h-uint f-ivc2-1u6) -(dnop ivc-x-6-2 "filler" (all-mep-isas) h-uint f-ivc2-2u6) -(dnop ivc-x-6-3 "filler" (all-mep-isas) h-uint f-ivc2-3u6) - - -(dnop imm3p4 "Imm3p4" (all-mep-isas) h-uint f-ivc2-3u4) -(dnop imm3p9 "Imm3p9" (all-mep-isas) h-uint f-ivc2-3u9) -(dnop imm4p8 "Imm4p8" (all-mep-isas) h-uint f-ivc2-4u8) -(dnop imm5p7 "Imm5p7" (all-mep-isas) h-uint f-ivc2-5u7) -(dnop imm6p6 "Imm6p6" (all-mep-isas) h-uint f-ivc2-6u6) -(dnop imm8p4 "Imm8p4" (all-mep-isas) h-uint f-ivc2-8u4) -(dnop simm8p4 "sImm8p4" (all-mep-isas) h-sint f-ivc2-8s4) - -(dnop imm3p5 "Imm3p5" (all-mep-isas) h-uint f-ivc2-3u5) -(dnop imm3p12 "Imm3p12" (all-mep-isas) h-uint f-ivc2-3u12) -(dnop imm4p4 "Imm4p4" (all-mep-isas) h-uint f-ivc2-4u4) -(dnop imm4p10 "Imm4p10" (all-mep-isas) h-uint f-ivc2-4u10) -(dnop imm5p8 "Imm5p8" (all-mep-isas) h-uint f-ivc2-5u8) -(dnop imm5p3 "Imm5p3" (all-mep-isas) h-uint f-ivc2-5u3) -(dnop imm6p2 "Imm6p2" (all-mep-isas) h-uint f-ivc2-6u2) -(dnop imm5p23 "Imm5p23" (all-mep-isas) h-uint f-ivc2-5u23) -(dnop imm3p25 "Imm3p25" (all-mep-isas) h-uint f-ivc2-3u25) -(dnop imm8p0 "Imm8p0" (all-mep-isas) h-uint f-ivc2-8u0) -(dnop simm8p0 "sImm8p0" (all-mep-isas) h-sint f-ivc2-8s0) -(dnop simm8p20 "sImm8p20" (all-mep-isas) h-sint f-ivc2-8s20) -(dnop imm8p20 "Imm8p20" (all-mep-isas) h-uint f-ivc2-8u20) - -(dnop crop "$CRo Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u23) -(dnop crqp "$CRq Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u13) -(dnop crpp "$CRp Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u18) - -(dnop ivc-x-0-2 "filler" (all-mep-isas) h-uint f-ivc2-2u0) -(dnop ivc-x-0-3 "filler" (all-mep-isas) h-uint f-ivc2-3u0) -(dnop ivc-x-0-4 "filler" (all-mep-isas) h-uint f-ivc2-4u0) -(dnop ivc-x-0-5 "filler" (all-mep-isas) h-uint f-ivc2-5u0) - -(dpop imm16p0 "Imm16p0" (all-mep-isas) h-uint f-ivc2-imm16p0 "unsigned16_range") -(dpop simm16p0 "sImm16p0" (all-mep-isas) h-sint f-ivc2-simm16p0 "signed16_range") - - -(df f-ivc2-ccrn-c3hi "ccrn hi 2u28" (all-mep-isas) 28 2 UINT #f #f) -(df f-ivc2-ccrn-c3lo "ccrn lo 4u4" (all-mep-isas) 4 4 UINT #f #f) - -(df f-ivc2-crn "ivc2 crn" (all-mep-isas) 0 4 UINT #f #f) -(df f-ivc2-crm "ivc2 crm" (all-mep-isas) 4 4 UINT #f #f) -(df f-ivc2-ccrn-h1 "ccrx hi 1u20" (all-mep-isas) 20 1 UINT #f #f) -(df f-ivc2-ccrn-h2 "ccrx hi 2u20" (all-mep-isas) 20 2 UINT #f #f) -(df f-ivc2-ccrn-lo "ccrx lo 4u0" (all-mep-isas) 0 4 UINT #f #f) -(df f-ivc2-cmov1 "ivc2 cmov op1" (all-mep-isas) 8 12 UINT #f #f) -(df f-ivc2-cmov2 "ivc2 cmov op2" (all-mep-isas) 22 6 UINT #f #f) -(df f-ivc2-cmov3 "ivc2 cmov op2" (all-mep-isas) 28 4 UINT #f #f) - -(define-multi-ifield - (name f-ivc2-ccrn-c3) - (comment "Coprocessor register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-c3hi f-ivc2-ccrn-c3lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-c3hi) (and (srl (ifield f-ivc2-ccrn-c3) 4) #x3)) - (set (ifield f-ivc2-ccrn-c3lo) (and (ifield f-ivc2-ccrn-c3) #xf)))) - (extract (set (ifield f-ivc2-ccrn-c3) - (or (sll (ifield f-ivc2-ccrn-c3hi) 4) - (ifield f-ivc2-ccrn-c3lo)))) - ) - -(define-multi-ifield - (name f-ivc2-ccrn) - (comment "Coprocessor control register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-h2 f-ivc2-ccrn-lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-h2) (and (srl (ifield f-ivc2-ccrn) 4) #x3)) - (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-ccrn) #xf)))) - (extract (set (ifield f-ivc2-ccrn) - (or (sll (ifield f-ivc2-ccrn-h2) 4) - (ifield f-ivc2-ccrn-lo)))) - ) - -(define-multi-ifield - (name f-ivc2-crnx) - (comment "Coprocessor register number field") - (attrs all-mep-isas) - (mode UINT) - (subfields f-ivc2-ccrn-h1 f-ivc2-ccrn-lo) - (insert (sequence () - (set (ifield f-ivc2-ccrn-h1) (and (srl (ifield f-ivc2-crnx) 4) #x1)) - (set (ifield f-ivc2-ccrn-lo) (and (ifield f-ivc2-crnx) #xf)))) - (extract (set (ifield f-ivc2-crnx) - (or (sll (ifield f-ivc2-ccrn-h1) 4) - (ifield f-ivc2-ccrn-lo)))) - ) - -(dnop ivc2rm "reg Rm" (all-mep-isas) h-gpr f-ivc2-crm) -(dnop ivc2crn "copro Rn (0-31, 64-bit" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-crnx) -(dnop ivc2ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn) -(dnop ivc2c3ccrn "copro control reg CCRn" (all-mep-isas (CDATA REGNUM)) h-ccr-ivc2 f-ivc2-ccrn-c3) - -; [--][--] [--][--] [--][--] [--] -; 0----+-- --1----+ ----2--- -+-- -; 01234567 89012345 67890123 4567 - - -; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm -(dni cmov-crn-rm - "cmov CRn,Rm" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov1")) - "cmov $crnx64,$rm" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0)) - (set crnx64 (or (zext DI rm) (and DI crnx64 #xffffffff00000000))) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn -(dni cmov-rn-crm - "cmov Rm,CRn" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmov2")) - "cmov $rm,$crnx64" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1)) - (set rm crnx64) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm -(dni cmovc-ccrn-rm - "cmovc CCRn,Rm" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc1")) - "cmovc $ivc2c3ccrn,$rm" - (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 0)) - (set ivc2c3ccrn rm) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn -(dni cmovc-rn-ccrm - "cmovc Rm,CCRn" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovc2")) - "cmovc $rm,$ivc2c3ccrn" - (+ MAJ_15 ivc2c3ccrn rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 0) (f-ivc2-4u24 0) (f-30 1) (f-31 1)) - (set rm ivc2c3ccrn) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N000 cmov =crn,rm -(dni cmovh-crn-rm - "cmovh CRn,Rm" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovh1")) - "cmovh $crnx64,$rm" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 0)) - (set crnx64 (or (sll (zext DI rm) 32) (and DI crnx64 #xffffffff))) - () -) - -; 1111 nnnn mmmm 0111 1111 0000 0000 N001 cmov =rm,crn -(dni cmovh-rn-crm - "cmovh Rm,CRn" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cmovh2")) - "cmovh $rm,$crnx64" - (+ MAJ_15 crnx64 rm (f-sub4 #x7) - (f-ivc2-4u16 #xF) (f-ivc2-4u20 1) (f-ivc2-4u24 0) (f-29 0) (f-30 0) (f-31 1)) - (set rm (srl crnx64 32)) - () -) - -; nnnnmmmm 11110000 0000N000 0000 cmov =crn,rm -(dni cmov-crn-rm-p0 - "cmov CRn,Rm" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmov1")) - "cmov $ivc2crn,$ivc2rm" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0)) - (set ivc2crn ivc2rm) - () -) - -; nnnnmmmm 11110000 0000N001 0000 cmov =rm,crn -(dni cmov-rn-crm-p0 - "cmov Rm,CRn" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmov2")) - "cmov $ivc2rm,$ivc2crn" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf00) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0)) - (set ivc2rm ivc2crn) - () -) - -; nnnnmmmm 11110000 0000NN10 0000 cmovc =ccrn,rm -(dni cmovc-ccrn-rm-p0 - "cmovc CCRn,Rm" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovc1")) - "cmovc $ivc2ccrn,$ivc2rm" - (+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x20) (f-ivc2-cmov3 0)) - (set ivc2ccrn ivc2rm) - () -) - -; nnnnmmmm 11110000 0000NN11 0000 cmovc =rm,ccrn -(dni cmovc-rn-ccrm-p0 - "cmovc Rm,CCRn" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovc2")) - "cmovc $ivc2rm,$ivc2ccrn" - (+ ivc2ccrn ivc2rm (f-ivc2-cmov1 #xf00) (f-ivc2-cmov2 #x30) (f-ivc2-cmov3 0)) - (set ivc2rm ivc2ccrn) - () -) - -; nnnnmmmm 11110001 0000N000 0000 cmovh =crn,rm -(dni cmovh-crn-rm-p0 - "cmovh CRn,Rm" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovh1")) - "cmovh $ivc2crn,$ivc2rm" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x00) (f-ivc2-cmov3 0)) - (set ivc2crn (or (sll (zext DI ivc2rm) 32) (and DI ivc2crn #xffffffff))) - () -) - -; nnnnmmmm 11110001 0000N001 0000 cmovh =rm,crn -(dni cmovh-rn-crm-p0 - "cmovh Rm,CRn" - (OPTIONAL_CP_INSN ivc2-p0-isa (SLOTS P0) (INTRINSIC "cmovh2")) - "cmovh $ivc2rm,$ivc2crn" - (+ ivc2crn ivc2rm (f-ivc2-cmov1 #xf10) (f-21 0) (f-ivc2-cmov2 #x10) (f-ivc2-cmov3 0)) - (set ivc2rm (srl ivc2crn 32)) - () -) - - -; 1111 000 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.b =croc,crqc,crpc (c3_1) -(dni cpadd3_b_C3 "cpadd3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpadd3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpadd3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.h =croc,crqc,crpc (c3_1) -(dni cpadd3_h_C3 "cpadd3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpadd3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpadd3_h" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.w =croc,crqc,crpc (c3_1) -(dni cpadd3_w_C3 "cpadd3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpadd3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpadd3_w" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00000 qqqqq ppppp 0 cdadd3 =croc,crqc,crpc (c3_1) -(dni cdadd3_C3 "cdadd3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdadd3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdadd3" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.b =croc,crqc,crpc (c3_1) -(dni cpsub3_b_C3 "cpsub3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsub3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsub3_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.h =croc,crqc,crpc (c3_1) -(dni cpsub3_h_C3 "cpsub3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsub3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsub3_h" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.w =croc,crqc,crpc (c3_1) -(dni cpsub3_w_C3 "cpsub3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsub3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsub3_w" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 00000 qqqqq ppppp 0 cdsub3 =croc,crqc,crpc (c3_1) -(dni cdsub3_C3 "cdsub3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsub3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsub3" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00001 qqqqq ppppp 0 cpand3 =croc,crqc,crpc (c3_1) -(dni cpand3_C3 "cpand3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST)) - "cpand3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpand3" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00001 qqqqq ppppp 0 cpor3 =croc,crqc,crpc (c3_1) -(dni cpor3_C3 "cpor3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST)) - "cpor3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpor3" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00001 qqqqq ppppp 0 cpnor3 =croc,crqc,crpc (c3_1) -(dni cpnor3_C3 "cpnor3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST)) - "cpnor3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpnor3" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00001 qqqqq ppppp 0 cpxor3 =croc,crqc,crpc (c3_1) -(dni cpxor3_C3 "cpxor3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST)) - "cpxor3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpxor3" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00001 qqqqq ppppp 0 cpsel =croc,crqc,crpc (c3_1) -(dni cpsel_C3 "cpsel $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpsel $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsel" pc crqc crpc)) ) - () - ) - -; 1111 iii ooooo 0111 11101 qqqqq ppppp 0 cpfsftbi =croc,crqc,crpc,imm3p4 (c3_1) -(dni cpfsftbi_C3 "cpfsftbi $croc,$crqc,$crpc,imm3p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpfsftbi $croc,$crqc,$crpc,$imm3p4" - (+ MAJ_15 imm3p4 croc (f-sub4 7) - (f-ivc2-5u16 #x1d) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpfsftbi" pc crqc crpc imm3p4)) ) - () - ) - -; 1111 110 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs0 =croc,crqc,crpc (c3_1) -(dni cpfsftbs0_C3 "cpfsftbs0 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs0 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpfsftbs0" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs1 =croc,crqc,crpc (c3_1) -(dni cpfsftbs1_C3 "cpfsftbs1 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs1 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpfsftbs1" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.b =croc,crqc,crpc (c3_1) -(dni cpunpacku_b_C3 "cpunpacku.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpunpacku.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpacku_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.h =croc,crqc,crpc (c3_1) -(dni cpunpacku_h_C3 "cpunpacku.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpunpacku.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpacku_h" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.w =croc,crqc,crpc (c3_1) -(dni cpunpacku_w_C3 "cpunpacku.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST)) - "cpunpacku.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpacku_w" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.b =croc,crqc,crpc (c3_1) -(dni cpunpackl_b_C3 "cpunpackl.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpunpackl.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpackl_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.h =croc,crqc,crpc (c3_1) -(dni cpunpackl_h_C3 "cpunpackl.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpunpackl.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpackl_h" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.w =croc,crqc,crpc (c3_1) -(dni cpunpackl_w_C3 "cpunpackl.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST)) - "cpunpackl.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpunpackl_w" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00011 qqqqq ppppp 0 cppacku.b =croc,crqc,crpc (c3_1) -(dni cppacku_b_C3 "cppacku.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cppacku.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppacku_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00011 qqqqq ppppp 0 cppack.b =croc,crqc,crpc (c3_1) -(dni cppack_b_C3 "cppack.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST)) - "cppack.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppack_b" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 00011 qqqqq ppppp 0 cppack.h =croc,crqc,crpc (c3_1) -(dni cppack_h_C3 "cppack.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST)) - "cppack.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppack_h" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.b =croc,crqc,crpc (c3_1) -(dni cpsrl3_b_C3 "cpsrl3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrl3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsrl3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.b =croc,crqc,crpc (c3_1) -(dni cpssrl3_b_C3 "cpssrl3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssrl3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssrl3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.h =croc,crqc,crpc (c3_1) -(dni cpsrl3_h_C3 "cpsrl3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrl3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsrl3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.h =croc,crqc,crpc (c3_1) -(dni cpssrl3_h_C3 "cpssrl3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssrl3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssrl3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.w =croc,crqc,crpc (c3_1) -(dni cpsrl3_w_C3 "cpsrl3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrl3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsrl3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.w =croc,crqc,crpc (c3_1) -(dni cpssrl3_w_C3 "cpssrl3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssrl3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssrl3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00100 qqqqq ppppp 0 cdsrl3 =croc,crqc,crpc (c3_1) -(dni cdsrl3_C3 "cdsrl3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrl3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsrl3" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.b =croc,crqc,crpc (c3_1) -(dni cpsra3_b_C3 "cpsra3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsra3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsra3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.b =croc,crqc,crpc (c3_1) -(dni cpssra3_b_C3 "cpssra3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssra3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssra3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.h =croc,crqc,crpc (c3_1) -(dni cpsra3_h_C3 "cpsra3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsra3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsra3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.h =croc,crqc,crpc (c3_1) -(dni cpssra3_h_C3 "cpssra3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssra3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssra3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.w =croc,crqc,crpc (c3_1) -(dni cpsra3_w_C3 "cpsra3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsra3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsra3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.w =croc,crqc,crpc (c3_1) -(dni cpssra3_w_C3 "cpssra3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssra3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssra3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00101 qqqqq ppppp 0 cdsra3 =croc,crqc,crpc (c3_1) -(dni cdsra3_C3 "cdsra3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsra3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsra3" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.b =croc,crqc,crpc (c3_1) -(dni cpsll3_b_C3 "cpsll3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsll3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsll3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.b =croc,crqc,crpc (c3_1) -(dni cpssll3_b_C3 "cpssll3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssll3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssll3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.h =croc,crqc,crpc (c3_1) -(dni cpsll3_h_C3 "cpsll3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsll3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsll3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.h =croc,crqc,crpc (c3_1) -(dni cpssll3_h_C3 "cpssll3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssll3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssll3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.w =croc,crqc,crpc (c3_1) -(dni cpsll3_w_C3 "cpsll3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsll3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsll3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.w =croc,crqc,crpc (c3_1) -(dni cpssll3_w_C3 "cpssll3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssll3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpssll3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 00110 qqqqq ppppp 0 cdsll3 =croc,crqc,crpc (c3_1) -(dni cdsll3_C3 "cdsll3 $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsll3 $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdsll3" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.h =croc,crqc,crpc (c3_1) -(dni cpsla3_h_C3 "cpsla3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsla3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsla3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.w =croc,crqc,crpc (c3_1) -(dni cpsla3_w_C3 "cpsla3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsla3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsla3_w" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.h =croc,crqc,crpc (c3_1) -(dni cpsadd3_h_C3 "cpsadd3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsadd3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsadd3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.w =croc,crqc,crpc (c3_1) -(dni cpsadd3_w_C3 "cpsadd3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsadd3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpsadd3_w" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.h =croc,crqc,crpc (c3_1) -(dni cpssub3_h_C3 "cpssub3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpssub3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set croc (c-call DI "ivc2_cpssub3_h" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.w =croc,crqc,crpc (c3_1) -(dni cpssub3_w_C3 "cpssub3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpssub3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set croc (c-call DI "ivc2_cpssub3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01001 qqqqq ppppp 0 cpextuaddu3.b =croc,crqc,crpc (c3_1) -(dni cpextuaddu3_b_C3 "cpextuaddu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuaddu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuaddu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01001 qqqqq ppppp 0 cpextuadd3.b =croc,crqc,crpc (c3_1) -(dni cpextuadd3_b_C3 "cpextuadd3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuadd3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuadd3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01001 qqqqq ppppp 0 cpextladdu3.b =croc,crqc,crpc (c3_1) -(dni cpextladdu3_b_C3 "cpextladdu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladdu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextladdu3_b" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01001 qqqqq ppppp 0 cpextladd3.b =croc,crqc,crpc (c3_1) -(dni cpextladd3_b_C3 "cpextladd3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladd3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextladd3_b" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01001 qqqqq ppppp 0 cpextusubu3.b =croc,crqc,crpc (c3_1) -(dni cpextusubu3_b_C3 "cpextusubu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusubu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextusubu3_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01001 qqqqq ppppp 0 cpextusub3.b =croc,crqc,crpc (c3_1) -(dni cpextusub3_b_C3 "cpextusub3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusub3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextusub3_b" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 01001 qqqqq ppppp 0 cpextlsubu3.b =croc,crqc,crpc (c3_1) -(dni cpextlsubu3_b_C3 "cpextlsubu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsubu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlsubu3_b" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 01001 qqqqq ppppp 0 cpextlsub3.b =croc,crqc,crpc (c3_1) -(dni cpextlsub3_b_C3 "cpextlsub3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsub3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlsub3_b" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01010 qqqqq ppppp 0 cpaveu3.b =croc,crqc,crpc (c3_1) -(dni cpaveu3_b_C3 "cpaveu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaveu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaveu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01010 qqqqq ppppp 0 cpave3.b =croc,crqc,crpc (c3_1) -(dni cpave3_b_C3 "cpave3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpave3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpave3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01010 qqqqq ppppp 0 cpave3.h =croc,crqc,crpc (c3_1) -(dni cpave3_h_C3 "cpave3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpave3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpave3_h" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01010 qqqqq ppppp 0 cpave3.w =croc,crqc,crpc (c3_1) -(dni cpave3_w_C3 "cpave3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpave3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpave3_w" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01010 qqqqq ppppp 0 cpaddsru3.b =croc,crqc,crpc (c3_1) -(dni cpaddsru3_b_C3 "cpaddsru3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsru3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsru3_b" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.b =croc,crqc,crpc (c3_1) -(dni cpaddsr3_b_C3 "cpaddsr3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsr3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsr3_b" pc crqc crpc)) ) - () - ) - -; 1111 110 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.h =croc,crqc,crpc (c3_1) -(dni cpaddsr3_h_C3 "cpaddsr3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpaddsr3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsr3_h" pc crqc crpc)) ) - () - ) - -; 1111 111 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.w =croc,crqc,crpc (c3_1) -(dni cpaddsr3_w_C3 "cpaddsr3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpaddsr3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7) - (f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpaddsr3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01011 qqqqq ppppp 0 cpabsu3.b =croc,crqc,crpc (c3_1) -(dni cpabsu3_b_C3 "cpabsu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.b =croc,crqc,crpc (c3_1) -(dni cpabs3_b_C3 "cpabs3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabs3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabs3_b" pc crqc crpc)) ) - () - ) - -; 1111 010 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.h =croc,crqc,crpc (c3_1) -(dni cpabs3_h_C3 "cpabs3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabs3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7) - (f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabs3_h" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.b =croc,crqc,crpc (c3_1) -(dni cpmaxu3_b_C3 "cpmaxu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmaxu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmaxu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.b =croc,crqc,crpc (c3_1) -(dni cpmax3_b_C3 "cpmax3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmax3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmax3_b" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.h =croc,crqc,crpc (c3_1) -(dni cpmax3_h_C3 "cpmax3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmax3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmax3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.w =croc,crqc,crpc (c3_1) -(dni cpmaxu3_w_C3 "cpmaxu3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmaxu3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmaxu3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.w =croc,crqc,crpc (c3_1) -(dni cpmax3_w_C3 "cpmax3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmax3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmax3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.b =croc,crqc,crpc (c3_1) -(dni cpminu3_b_C3 "cpminu3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpminu3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpminu3_b" pc crqc crpc)) ) - () - ) - -; 1111 001 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.b =croc,crqc,crpc (c3_1) -(dni cpmin3_b_C3 "cpmin3.b $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmin3.b $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmin3_b" pc crqc crpc)) ) - () - ) - -; 1111 011 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.h =croc,crqc,crpc (c3_1) -(dni cpmin3_h_C3 "cpmin3.h $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmin3.h $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmin3_h" pc crqc crpc)) ) - () - ) - -; 1111 100 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.w =croc,crqc,crpc (c3_1) -(dni cpminu3_w_C3 "cpminu3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpminu3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpminu3_w" pc crqc crpc)) ) - () - ) - -; 1111 101 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.w =croc,crqc,crpc (c3_1) -(dni cpmin3_w_C3 "cpmin3.w $croc,$crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmin3.w $croc,$crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7) - (f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmin3_w" pc crqc crpc)) ) - () - ) - -; 1111 000 ooooo 0111 10000 00000 00000 0 cpmovfrcsar0 =croc (c3_1) -(dni cpmovfrcsar0_C3 "cpmovfrcsar0 $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar0 $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovfrcsar0" pc)) ) - () - ) - -; 1111 000 ooooo 0111 10000 00000 01111 0 cpmovfrcsar1 =croc (c3_1) -(dni cpmovfrcsar1_C3 "cpmovfrcsar1 $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar1 $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovfrcsar1" pc)) ) - () - ) - -; 1111 000 ooooo 0111 10000 00000 00001 0 cpmovfrcc =croc (c3_1) -(dni cpmovfrcc_C3 "cpmovfrcc $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcc $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovfrcc" pc)) ) - () - ) - -; 1111 0000 0000 0111 10000 qqqqq 10000 0 cpmovtocsar0 crqc (c3_1) -(dni cpmovtocsar0_C3 "cpmovtocsar0 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0") VOLATILE) - "cpmovtocsar0 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar0 0) - (c-call "ivc2_cpmovtocsar0" pc crqc) ) - () - ) - -; 1111 0000 0000 0111 10000 qqqqq 11111 0 cpmovtocsar1 crqc (c3_1) -(dni cpmovtocsar1_C3 "cpmovtocsar1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1") VOLATILE) - "cpmovtocsar1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar1 0) - (c-call "ivc2_cpmovtocsar1" pc crqc) ) - () - ) - -; 1111 0000 0000 0111 10000 qqqqq 10001 0 cpmovtocc crqc (c3_1) -(dni cpmovtocc_C3 "cpmovtocc $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc") VOLATILE) - "cpmovtocc $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpmovtocc" pc crqc) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00000 0 cpmov =croc,crqc (c3_1) -(dni cpmov_C3 "cpmov $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpmov $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmov" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00001 0 cpabsz.b =croc,crqc (c3_1) -(dni cpabsz_b_C3 "cpabsz.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsz.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsz_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00010 0 cpabsz.h =croc,crqc (c3_1) -(dni cpabsz_h_C3 "cpabsz.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabsz.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsz_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00011 0 cpabsz.w =croc,crqc (c3_1) -(dni cpabsz_w_C3 "cpabsz.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpabsz.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpabsz_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00100 0 cpldz.h =croc,crqc (c3_1) -(dni cpldz_h_C3 "cpldz.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpldz.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpldz_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00101 0 cpldz.w =croc,crqc (c3_1) -(dni cpldz_w_C3 "cpldz.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpldz.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpldz_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00110 0 cpnorm.h =croc,crqc (c3_1) -(dni cpnorm_h_C3 "cpnorm.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST)) - "cpnorm.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpnorm_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 00111 0 cpnorm.w =croc,crqc (c3_1) -(dni cpnorm_w_C3 "cpnorm.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST)) - "cpnorm.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpnorm_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01000 0 cphaddu.b =croc,crqc (c3_1) -(dni cphaddu_b_C3 "cphaddu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cphaddu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x8) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphaddu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01001 0 cphadd.b =croc,crqc (c3_1) -(dni cphadd_b_C3 "cphadd.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST)) - "cphadd.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x9) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphadd_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01010 0 cphadd.h =croc,crqc (c3_1) -(dni cphadd_h_C3 "cphadd.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST)) - "cphadd.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xa) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphadd_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01011 0 cphadd.w =croc,crqc (c3_1) -(dni cphadd_w_C3 "cphadd.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST)) - "cphadd.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xb) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cphadd_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01100 0 cpccadd.b +crqc (c3_1) -(dni cpccadd_b_C3 "cpccadd.b $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY) VOLATILE) - "cpccadd.b $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xc) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpccadd_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01101 0 cpbcast.b =croc,crqc (c3_1) -(dni cpbcast_b_C3 "cpbcast.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST)) - "cpbcast.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xd) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpbcast_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01110 0 cpbcast.h =croc,crqc (c3_1) -(dni cpbcast_h_C3 "cpbcast.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST)) - "cpbcast.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xe) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpbcast_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 01111 0 cpbcast.w =croc,crqc (c3_1) -(dni cpbcast_w_C3 "cpbcast.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST)) - "cpbcast.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpbcast_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10000 0 cpextuu.b =croc,crqc (c3_1) -(dni cpextuu_b_C3 "cpextuu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextuu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10001 0 cpextu.b =croc,crqc (c3_1) -(dni cpextu_b_C3 "cpextu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10010 0 cpextuu.h =croc,crqc (c3_1) -(dni cpextuu_h_C3 "cpextuu.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextuu.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextuu_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10011 0 cpextu.h =croc,crqc (c3_1) -(dni cpextu_h_C3 "cpextu.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextu.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextu_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10100 0 cpextlu.b =croc,crqc (c3_1) -(dni cpextlu_b_C3 "cpextlu.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextlu.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlu_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10101 0 cpextl.b =croc,crqc (c3_1) -(dni cpextl_b_C3 "cpextl.b $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextl.b $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextl_b" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10110 0 cpextlu.h =croc,crqc (c3_1) -(dni cpextlu_h_C3 "cpextlu.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextlu.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextlu_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 10111 0 cpextl.h =croc,crqc (c3_1) -(dni cpextl_h_C3 "cpextl.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpextl.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpextl_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11000 0 cpcastub.h =croc,crqc (c3_1) -(dni cpcastub_h_C3 "cpcastub.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastub.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x18) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastub_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11001 0 cpcastb.h =croc,crqc (c3_1) -(dni cpcastb_h_C3 "cpcastb.h $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastb.h $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x19) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastb_h" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11100 0 cpcastub.w =croc,crqc (c3_1) -(dni cpcastub_w_C3 "cpcastub.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastub.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1c) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastub_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11101 0 cpcastb.w =croc,crqc (c3_1) -(dni cpcastb_w_C3 "cpcastb.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastb.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1d) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastb_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11110 0 cpcastuh.w =croc,crqc (c3_1) -(dni cpcastuh_w_C3 "cpcastuh.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastuh.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1e) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcastuh_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11111 0 cpcasth.w =croc,crqc (c3_1) -(dni cpcasth_w_C3 "cpcasth.w $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcasth.w $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpcasth_w" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11010 0 cdcastuw =croc,crqc (c3_1) -(dni cdcastuw_C3 "cdcastuw $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastuw $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1a) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdcastuw" pc crqc)) ) - () - ) - -; 1111 000 ooooo 0111 10001 qqqqq 11011 0 cdcastw =croc,crqc (c3_1) -(dni cdcastw_C3 "cdcastw $croc,$crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastw $croc,$crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1b) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cdcastw" pc crqc)) ) - () - ) - -; 1111 0000 0000 0111 10010 qqqqq ppppp 0 cpcmpeqz.b crqc,crpc (c3_1) -(dni cpcmpeqz_b_C3 "cpcmpeqz.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeqz.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeqz_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0001 0111 10010 qqqqq ppppp 0 cpcmpeq.b crqc,crpc (c3_1) -(dni cpcmpeq_b_C3 "cpcmpeq.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeq.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0011 0111 10010 qqqqq ppppp 0 cpcmpeq.h crqc,crpc (c3_1) -(dni cpcmpeq_h_C3 "cpcmpeq.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI) VOLATILE) - "cpcmpeq.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0101 0111 10010 qqqqq ppppp 0 cpcmpeq.w crqc,crpc (c3_1) -(dni cpcmpeq_w_C3 "cpcmpeq.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI) VOLATILE) - "cpcmpeq.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1001 0111 10010 qqqqq ppppp 0 cpcmpne.b crqc,crpc (c3_1) -(dni cpcmpne_b_C3 "cpcmpne.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI) VOLATILE) - "cpcmpne.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1011 0111 10010 qqqqq ppppp 0 cpcmpne.h crqc,crpc (c3_1) -(dni cpcmpne_h_C3 "cpcmpne.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI) VOLATILE) - "cpcmpne.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1101 0111 10010 qqqqq ppppp 0 cpcmpne.w crqc,crpc (c3_1) -(dni cpcmpne_w_C3 "cpcmpne.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI) VOLATILE) - "cpcmpne.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0000 0111 10010 qqqqq ppppp 0 cpcmpgtu.b crqc,crpc (c3_1) -(dni cpcmpgtu_b_C3 "cpcmpgtu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgtu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0001 0111 10010 qqqqq ppppp 0 cpcmpgt.b crqc,crpc (c3_1) -(dni cpcmpgt_b_C3 "cpcmpgt.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI) VOLATILE) - "cpcmpgt.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0011 0111 10010 qqqqq ppppp 0 cpcmpgt.h crqc,crpc (c3_1) -(dni cpcmpgt_h_C3 "cpcmpgt.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI) VOLATILE) - "cpcmpgt.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0100 0111 10010 qqqqq ppppp 0 cpcmpgtu.w crqc,crpc (c3_1) -(dni cpcmpgtu_w_C3 "cpcmpgtu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgtu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0101 0111 10010 qqqqq ppppp 0 cpcmpgt.w crqc,crpc (c3_1) -(dni cpcmpgt_w_C3 "cpcmpgt.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI) VOLATILE) - "cpcmpgt.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1000 0111 10010 qqqqq ppppp 0 cpcmpgeu.b crqc,crpc (c3_1) -(dni cpcmpgeu_b_C3 "cpcmpgeu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgeu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x18) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_b" pc crqc crpc) ) - () - ) - -; 1111 0001 1001 0111 10010 qqqqq ppppp 0 cpcmpge.b crqc,crpc (c3_1) -(dni cpcmpge_b_C3 "cpcmpge.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI) VOLATILE) - "cpcmpge.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x19) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_b" pc crqc crpc) ) - () - ) - -; 1111 0001 1011 0111 10010 qqqqq ppppp 0 cpcmpge.h crqc,crpc (c3_1) -(dni cpcmpge_h_C3 "cpcmpge.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI) VOLATILE) - "cpcmpge.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_h" pc crqc crpc) ) - () - ) - -; 1111 0001 1100 0111 10010 qqqqq ppppp 0 cpcmpgeu.w crqc,crpc (c3_1) -(dni cpcmpgeu_w_C3 "cpcmpgeu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgeu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1101 0111 10010 qqqqq ppppp 0 cpcmpge.w crqc,crpc (c3_1) -(dni cpcmpge_w_C3 "cpcmpge.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI) VOLATILE) - "cpcmpge.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_w" pc crqc crpc) ) - () - ) - -; 1111 0010 0001 0111 10010 qqqqq ppppp 0 cpacmpeq.b crqc,crpc (c3_1) -(dni cpacmpeq_b_C3 "cpacmpeq.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI)) - "cpacmpeq.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpeq_b" pc crqc crpc) ) - () - ) - -; 1111 0010 0011 0111 10010 qqqqq ppppp 0 cpacmpeq.h crqc,crpc (c3_1) -(dni cpacmpeq_h_C3 "cpacmpeq.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI)) - "cpacmpeq.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpeq_h" pc crqc crpc) ) - () - ) - -; 1111 0010 0101 0111 10010 qqqqq ppppp 0 cpacmpeq.w crqc,crpc (c3_1) -(dni cpacmpeq_w_C3 "cpacmpeq.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI)) - "cpacmpeq.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpeq_w" pc crqc crpc) ) - () - ) - -; 1111 0010 1001 0111 10010 qqqqq ppppp 0 cpacmpne.b crqc,crpc (c3_1) -(dni cpacmpne_b_C3 "cpacmpne.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI)) - "cpacmpne.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpne_b" pc crqc crpc) ) - () - ) - -; 1111 0010 1011 0111 10010 qqqqq ppppp 0 cpacmpne.h crqc,crpc (c3_1) -(dni cpacmpne_h_C3 "cpacmpne.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI)) - "cpacmpne.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpne_h" pc crqc crpc) ) - () - ) - -; 1111 0010 1101 0111 10010 qqqqq ppppp 0 cpacmpne.w crqc,crpc (c3_1) -(dni cpacmpne_w_C3 "cpacmpne.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI)) - "cpacmpne.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpne_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0000 0111 10010 qqqqq ppppp 0 cpacmpgtu.b crqc,crpc (c3_1) -(dni cpacmpgtu_b_C3 "cpacmpgtu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI)) - "cpacmpgtu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgtu_b" pc crqc crpc) ) - () - ) - -; 1111 0011 0001 0111 10010 qqqqq ppppp 0 cpacmpgt.b crqc,crpc (c3_1) -(dni cpacmpgt_b_C3 "cpacmpgt.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI)) - "cpacmpgt.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgt_b" pc crqc crpc) ) - () - ) - -; 1111 0011 0011 0111 10010 qqqqq ppppp 0 cpacmpgt.h crqc,crpc (c3_1) -(dni cpacmpgt_h_C3 "cpacmpgt.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI)) - "cpacmpgt.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgt_h" pc crqc crpc) ) - () - ) - -; 1111 0011 0100 0111 10010 qqqqq ppppp 0 cpacmpgtu.w crqc,crpc (c3_1) -(dni cpacmpgtu_w_C3 "cpacmpgtu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI)) - "cpacmpgtu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgtu_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0101 0111 10010 qqqqq ppppp 0 cpacmpgt.w crqc,crpc (c3_1) -(dni cpacmpgt_w_C3 "cpacmpgt.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI)) - "cpacmpgt.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgt_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1000 0111 10010 qqqqq ppppp 0 cpacmpgeu.b crqc,crpc (c3_1) -(dni cpacmpgeu_b_C3 "cpacmpgeu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI)) - "cpacmpgeu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x18) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgeu_b" pc crqc crpc) ) - () - ) - -; 1111 0011 1001 0111 10010 qqqqq ppppp 0 cpacmpge.b crqc,crpc (c3_1) -(dni cpacmpge_b_C3 "cpacmpge.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI)) - "cpacmpge.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x19) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpge_b" pc crqc crpc) ) - () - ) - -; 1111 0011 1011 0111 10010 qqqqq ppppp 0 cpacmpge.h crqc,crpc (c3_1) -(dni cpacmpge_h_C3 "cpacmpge.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI)) - "cpacmpge.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpge_h" pc crqc crpc) ) - () - ) - -; 1111 0011 1100 0111 10010 qqqqq ppppp 0 cpacmpgeu.w crqc,crpc (c3_1) -(dni cpacmpgeu_w_C3 "cpacmpgeu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI)) - "cpacmpgeu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpgeu_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1101 0111 10010 qqqqq ppppp 0 cpacmpge.w crqc,crpc (c3_1) -(dni cpacmpge_w_C3 "cpacmpge.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI)) - "cpacmpge.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpacmpge_w" pc crqc crpc) ) - () - ) - -; 1111 0100 0001 0111 10010 qqqqq ppppp 0 cpocmpeq.b crqc,crpc (c3_1) -(dni cpocmpeq_b_C3 "cpocmpeq.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI)) - "cpocmpeq.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpeq_b" pc crqc crpc) ) - () - ) - -; 1111 0100 0011 0111 10010 qqqqq ppppp 0 cpocmpeq.h crqc,crpc (c3_1) -(dni cpocmpeq_h_C3 "cpocmpeq.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI)) - "cpocmpeq.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpeq_h" pc crqc crpc) ) - () - ) - -; 1111 0100 0101 0111 10010 qqqqq ppppp 0 cpocmpeq.w crqc,crpc (c3_1) -(dni cpocmpeq_w_C3 "cpocmpeq.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI)) - "cpocmpeq.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpeq_w" pc crqc crpc) ) - () - ) - -; 1111 0100 1001 0111 10010 qqqqq ppppp 0 cpocmpne.b crqc,crpc (c3_1) -(dni cpocmpne_b_C3 "cpocmpne.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI)) - "cpocmpne.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpne_b" pc crqc crpc) ) - () - ) - -; 1111 0100 1011 0111 10010 qqqqq ppppp 0 cpocmpne.h crqc,crpc (c3_1) -(dni cpocmpne_h_C3 "cpocmpne.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI)) - "cpocmpne.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpne_h" pc crqc crpc) ) - () - ) - -; 1111 0100 1101 0111 10010 qqqqq ppppp 0 cpocmpne.w crqc,crpc (c3_1) -(dni cpocmpne_w_C3 "cpocmpne.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI)) - "cpocmpne.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpne_w" pc crqc crpc) ) - () - ) - -; 1111 0101 0000 0111 10010 qqqqq ppppp 0 cpocmpgtu.b crqc,crpc (c3_1) -(dni cpocmpgtu_b_C3 "cpocmpgtu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI)) - "cpocmpgtu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgtu_b" pc crqc crpc) ) - () - ) - -; 1111 0101 0001 0111 10010 qqqqq ppppp 0 cpocmpgt.b crqc,crpc (c3_1) -(dni cpocmpgt_b_C3 "cpocmpgt.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI)) - "cpocmpgt.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgt_b" pc crqc crpc) ) - () - ) - -; 1111 0101 0011 0111 10010 qqqqq ppppp 0 cpocmpgt.h crqc,crpc (c3_1) -(dni cpocmpgt_h_C3 "cpocmpgt.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI)) - "cpocmpgt.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgt_h" pc crqc crpc) ) - () - ) - -; 1111 0101 0100 0111 10010 qqqqq ppppp 0 cpocmpgtu.w crqc,crpc (c3_1) -(dni cpocmpgtu_w_C3 "cpocmpgtu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI)) - "cpocmpgtu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgtu_w" pc crqc crpc) ) - () - ) - -; 1111 0101 0101 0111 10010 qqqqq ppppp 0 cpocmpgt.w crqc,crpc (c3_1) -(dni cpocmpgt_w_C3 "cpocmpgt.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI)) - "cpocmpgt.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgt_w" pc crqc crpc) ) - () - ) - -; 1111 0101 1000 0111 10010 qqqqq ppppp 0 cpocmpgeu.b crqc,crpc (c3_1) -(dni cpocmpgeu_b_C3 "cpocmpgeu.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI)) - "cpocmpgeu.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x18) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgeu_b" pc crqc crpc) ) - () - ) - -; 1111 0101 1001 0111 10010 qqqqq ppppp 0 cpocmpge.b crqc,crpc (c3_1) -(dni cpocmpge_b_C3 "cpocmpge.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI)) - "cpocmpge.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x19) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpge_b" pc crqc crpc) ) - () - ) - -; 1111 0101 1011 0111 10010 qqqqq ppppp 0 cpocmpge.h crqc,crpc (c3_1) -(dni cpocmpge_h_C3 "cpocmpge.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI)) - "cpocmpge.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpge_h" pc crqc crpc) ) - () - ) - -; 1111 0101 1100 0111 10010 qqqqq ppppp 0 cpocmpgeu.w crqc,crpc (c3_1) -(dni cpocmpgeu_w_C3 "cpocmpgeu.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI)) - "cpocmpgeu.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpgeu_w" pc crqc crpc) ) - () - ) - -; 1111 0101 1101 0111 10010 qqqqq ppppp 0 cpocmpge.w crqc,crpc (c3_1) -(dni cpocmpge_w_C3 "cpocmpge.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI)) - "cpocmpge.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpocmpge_w" pc crqc crpc) ) - () - ) - -; 1111 00xx xiii 0111 10100 qqqqq ppppp 0 cpsrli3.b =crqc,crpc,imm3p9 (c3_imm) -(dni cpsrli3_b_C3 "cpsrli3.b $crqc,$crpc,imm3p9 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrli3.b $crqc,$crpc,$imm3p9" - (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrli3_b" pc crpc imm3p9)) ) - () - ) - -; 1111 01xx iiii 0111 10100 qqqqq ppppp 0 cpsrli3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpsrli3_h_C3 "cpsrli3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrli3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrli3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10100 qqqqq ppppp 0 cpsrli3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpsrli3_w_C3 "cpsrli3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrli3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrli3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 11ii iiii 0111 10100 qqqqq ppppp 0 cdsrli3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdsrli3_C3 "cdsrli3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrli3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdsrli3" pc crpc imm6p6)) ) - () - ) - -; 1111 00xx xiii 0111 10101 qqqqq ppppp 0 cpsrai3.b =crqc,crpc,imm3p9 (c3_imm) -(dni cpsrai3_b_C3 "cpsrai3.b $crqc,$crpc,imm3p9 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrai3.b $crqc,$crpc,$imm3p9" - (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrai3_b" pc crpc imm3p9)) ) - () - ) - -; 1111 01xx iiii 0111 10101 qqqqq ppppp 0 cpsrai3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpsrai3_h_C3 "cpsrai3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrai3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrai3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10101 qqqqq ppppp 0 cpsrai3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpsrai3_w_C3 "cpsrai3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrai3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpsrai3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 11ii iiii 0111 10101 qqqqq ppppp 0 cdsrai3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdsrai3_C3 "cdsrai3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrai3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdsrai3" pc crpc imm6p6)) ) - () - ) - -; 1111 00xx xiii 0111 10110 qqqqq ppppp 0 cpslli3.b =crqc,crpc,imm3p9 (c3_imm) -(dni cpslli3_b_C3 "cpslli3.b $crqc,$crpc,imm3p9 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpslli3.b $crqc,$crpc,$imm3p9" - (+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslli3_b" pc crpc imm3p9)) ) - () - ) - -; 1111 01xx iiii 0111 10110 qqqqq ppppp 0 cpslli3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpslli3_h_C3 "cpslli3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpslli3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslli3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10110 qqqqq ppppp 0 cpslli3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpslli3_w_C3 "cpslli3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpslli3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslli3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 11ii iiii 0111 10110 qqqqq ppppp 0 cdslli3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdslli3_C3 "cdslli3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdslli3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdslli3" pc crpc imm6p6)) ) - () - ) - -; 1111 01xx iiii 0111 10111 qqqqq ppppp 0 cpslai3.h =crqc,crpc,imm4p8 (c3_imm) -(dni cpslai3_h_C3 "cpslai3.h $crqc,$crpc,imm4p8 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpslai3.h $crqc,$crpc,$imm4p8" - (+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7) - (f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslai3_h" pc crpc imm4p8)) ) - () - ) - -; 1111 10xi iiii 0111 10111 qqqqq ppppp 0 cpslai3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpslai3_w_C3 "cpslai3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpslai3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpslai3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 00xi iiii 0111 11000 qqqqq ppppp 0 cpclipiu3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpclipiu3_w_C3 "cpclipiu3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipiu3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpclipiu3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 01xi iiii 0111 11000 qqqqq ppppp 0 cpclipi3.w =crqc,crpc,imm5p7 (c3_imm) -(dni cpclipi3_w_C3 "cpclipi3.w $crqc,$crpc,imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipi3.w $crqc,$crpc,$imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpclipi3_w" pc crpc imm5p7)) ) - () - ) - -; 1111 10ii iiii 0111 11000 qqqqq ppppp 0 cdclipiu3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdclipiu3_C3 "cdclipiu3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipiu3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x2) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdclipiu3" pc crpc imm6p6)) ) - () - ) - -; 1111 11ii iiii 0111 11000 qqqqq ppppp 0 cdclipi3 =crqc,crpc,imm6p6 (c3_imm) -(dni cdclipi3_C3 "cdclipi3 $crqc,$crpc,imm6p6 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipi3 $crqc,$crpc,$imm6p6" - (+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7) - (f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdclipi3" pc crpc imm6p6)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00000 0 cpmovi.b =crqc,simm8p4 (c3_imm) -(dni cpmovi_b_C3 "cpmovi.b $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmovi.b $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmovi_b" pc simm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00010 0 cpmoviu.h =crqc,imm8p4 (c3_imm) -(dni cpmoviu_h_C3 "cpmoviu.h $crqc,imm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpmoviu.h $crqc,$imm8p4" - (+ MAJ_15 imm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmoviu_h" pc imm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00011 0 cpmovi.h =crqc,simm8p4 (c3_imm) -(dni cpmovi_h_C3 "cpmovi.h $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmovi.h $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmovi_h" pc simm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00100 0 cpmoviu.w =crqc,imm8p4 (c3_imm) -(dni cpmoviu_w_C3 "cpmoviu.w $crqc,imm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST)) - "cpmoviu.w $crqc,$imm8p4" - (+ MAJ_15 imm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmoviu_w" pc imm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00101 0 cpmovi.w =crqc,simm8p4 (c3_imm) -(dni cpmovi_w_C3 "cpmovi.w $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmovi.w $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cpmovi_w" pc simm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00110 0 cdmoviu =crqc,imm8p4 (c3_imm) -(dni cdmoviu_C3 "cdmoviu $crqc,imm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmoviu $crqc,$imm8p4" - (+ MAJ_15 imm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdmoviu" pc imm8p4)) ) - () - ) - -; 1111 iiii iiii 0111 11001 qqqqq 00111 0 cdmovi =crqc,simm8p4 (c3_imm) -(dni cdmovi_C3 "cdmovi $crqc,simm8p4 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmovi $crqc,$simm8p4" - (+ MAJ_15 simm8p4 (f-sub4 7) - (f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) ) - (sequence () - (c-call "check_option_cp" pc) - (set crqc (c-call DI "ivc2_cdmovi" pc simm8p4)) ) - () - ) - -; 1111 0000 0000 0111 00000 qqqqq ppppp 1 cpadda1u.b crqc,crpc (c3_1) -(dni cpadda1u_b_C3 "cpadda1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpadda1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0001 0111 00000 qqqqq ppppp 1 cpadda1.b crqc,crpc (c3_1) -(dni cpadda1_b_C3 "cpadda1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b") (CPTYPE V8QI) VOLATILE) - "cpadda1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0010 0111 00000 qqqqq ppppp 1 cpaddua1.h crqc,crpc (c3_1) -(dni cpaddua1_h_C3 "cpaddua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpaddua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0011 0111 00000 qqqqq ppppp 1 cpaddla1.h crqc,crpc (c3_1) -(dni cpaddla1_h_C3 "cpaddla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpaddla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0100 0111 00000 qqqqq ppppp 1 cpaddaca1u.b crqc,crpc (c3_1) -(dni cpaddaca1u_b_C3 "cpaddaca1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpaddaca1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0101 0111 00000 qqqqq ppppp 1 cpaddaca1.b crqc,crpc (c3_1) -(dni cpaddaca1_b_C3 "cpaddaca1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI) VOLATILE) - "cpaddaca1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0110 0111 00000 qqqqq ppppp 1 cpaddacua1.h crqc,crpc (c3_1) -(dni cpaddacua1_h_C3 "cpaddacua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x6) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 0111 0111 00000 qqqqq ppppp 1 cpaddacla1.h crqc,crpc (c3_1) -(dni cpaddacla1_h_C3 "cpaddacla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x7) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1000 0111 00000 qqqqq ppppp 1 cpsuba1u.b crqc,crpc (c3_1) -(dni cpsuba1u_b_C3 "cpsuba1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsuba1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1001 0111 00000 qqqqq ppppp 1 cpsuba1.b crqc,crpc (c3_1) -(dni cpsuba1_b_C3 "cpsuba1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI) VOLATILE) - "cpsuba1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1010 0111 00000 qqqqq ppppp 1 cpsubua1.h crqc,crpc (c3_1) -(dni cpsubua1_h_C3 "cpsubua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsubua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1011 0111 00000 qqqqq ppppp 1 cpsubla1.h crqc,crpc (c3_1) -(dni cpsubla1_h_C3 "cpsubla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsubla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1100 0111 00000 qqqqq ppppp 1 cpsubaca1u.b crqc,crpc (c3_1) -(dni cpsubaca1u_b_C3 "cpsubaca1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsubaca1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1101 0111 00000 qqqqq ppppp 1 cpsubaca1.b crqc,crpc (c3_1) -(dni cpsubaca1_b_C3 "cpsubaca1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI) VOLATILE) - "cpsubaca1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1110 0111 00000 qqqqq ppppp 1 cpsubacua1.h crqc,crpc (c3_1) -(dni cpsubacua1_h_C3 "cpsubacua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1111 0111 00000 qqqqq ppppp 1 cpsubacla1.h crqc,crpc (c3_1) -(dni cpsubacla1_h_C3 "cpsubacla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0000 0111 00000 qqqqq ppppp 1 cpabsa1u.b crqc,crpc (c3_1) -(dni cpabsa1u_b_C3 "cpabsa1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpabsa1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1u_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0001 0111 00000 qqqqq ppppp 1 cpabsa1.b crqc,crpc (c3_1) -(dni cpabsa1_b_C3 "cpabsa1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI) VOLATILE) - "cpabsa1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0010 0111 00000 qqqqq ppppp 1 cpabsua1.h crqc,crpc (c3_1) -(dni cpabsua1_h_C3 "cpabsua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI) VOLATILE) - "cpabsua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0011 0111 00000 qqqqq ppppp 1 cpabsla1.h crqc,crpc (c3_1) -(dni cpabsla1_h_C3 "cpabsla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI) VOLATILE) - "cpabsla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpabsla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0100 0111 00000 qqqqq ppppp 1 cpsada1u.b crqc,crpc (c3_1) -(dni cpsada1u_b_C3 "cpsada1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsada1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1u_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0101 0111 00000 qqqqq ppppp 1 cpsada1.b crqc,crpc (c3_1) -(dni cpsada1_b_C3 "cpsada1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b") (CPTYPE V8QI) VOLATILE) - "cpsada1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0110 0111 00000 qqqqq ppppp 1 cpsadua1.h crqc,crpc (c3_1) -(dni cpsadua1_h_C3 "cpsadua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsadua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0111 0111 00000 qqqqq ppppp 1 cpsadla1.h crqc,crpc (c3_1) -(dni cpsadla1_h_C3 "cpsadla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsadla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadla1_h" pc crqc crpc) ) - () - ) - -; 1111 0010 0000 0111 00000 qqqqq ppppp 1 cpseta1.h crqc,crpc (c3_1) -(dni cpseta1_h_C3 "cpseta1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h") (CPTYPE V4HI) VOLATILE) - "cpseta1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpseta1_h" pc crqc crpc) ) - () - ) - -; 1111 0010 0010 0111 00000 qqqqq ppppp 1 cpsetua1.w crqc,crpc (c3_1) -(dni cpsetua1_w_C3 "cpsetua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI) VOLATILE) - "cpsetua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x2) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsetua1_w" pc crqc crpc) ) - () - ) - -; 1111 0010 0011 0111 00000 qqqqq ppppp 1 cpsetla1.w crqc,crpc (c3_1) -(dni cpsetla1_w_C3 "cpsetla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI) VOLATILE) - "cpsetla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7) - (f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsetla1_w" pc crqc crpc) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00000 1 cpmova1.b =croc (c3_1) -(dni cpmova1_b_C3 "cpmova1.b $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cpmova1.b $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmova1_b" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00010 1 cpmovua1.h =croc (c3_1) -(dni cpmovua1_h_C3 "cpmovua1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovua1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovua1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00011 1 cpmovla1.h =croc (c3_1) -(dni cpmovla1_h_C3 "cpmovla1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovla1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovla1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00100 1 cpmovuua1.w =croc (c3_1) -(dni cpmovuua1_w_C3 "cpmovuua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovuua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovuua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00101 1 cpmovula1.w =croc (c3_1) -(dni cpmovula1_w_C3 "cpmovula1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovula1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovula1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00110 1 cpmovlua1.w =croc (c3_1) -(dni cpmovlua1_w_C3 "cpmovlua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovlua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 00111 1 cpmovlla1.w =croc (c3_1) -(dni cpmovlla1_w_C3 "cpmovlla1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlla1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovlla1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10000 1 cppacka1u.b =croc (c3_1) -(dni cppacka1u_b_C3 "cppacka1u.b $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST) VOLATILE) - "cppacka1u.b $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppacka1u_b" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10001 1 cppacka1.b =croc (c3_1) -(dni cppacka1_b_C3 "cppacka1.b $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cppacka1.b $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppacka1_b" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10010 1 cppackua1.h =croc (c3_1) -(dni cppackua1_h_C3 "cppackua1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackua1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackua1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10011 1 cppackla1.h =croc (c3_1) -(dni cppackla1_h_C3 "cppackla1.h $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackla1.h $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackla1_h" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10100 1 cppackua1.w =croc (c3_1) -(dni cppackua1_w_C3 "cppackua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10101 1 cppackla1.w =croc (c3_1) -(dni cppackla1_w_C3 "cppackla1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackla1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cppackla1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10110 1 cpmovhua1.w =croc (c3_1) -(dni cpmovhua1_w_C3 "cpmovhua1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhua1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovhua1_w" pc)) ) - () - ) - -; 1111 000 ooooo 0111 00100 00000 10111 1 cpmovhla1.w =croc (c3_1) -(dni cpmovhla1_w_C3 "cpmovhla1.w $croc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhla1.w $croc" - (+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7) - (f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set croc (c-call DI "ivc2_cpmovhla1_w" pc)) ) - () - ) - -; 1111 0000 0000 0111 00010 qqqqq 00000 1 cpsrla1 crqc (c3_1) -(dni cpsrla1_C3 "cpsrla1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrla1") VOLATILE) - "cpsrla1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrla1" pc crqc) ) - () - ) - -; 1111 0000 0001 0111 00010 qqqqq 00000 1 cpsraa1 crqc (c3_1) -(dni cpsraa1_C3 "cpsraa1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraa1") VOLATILE) - "cpsraa1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraa1" pc crqc) ) - () - ) - -; 1111 0000 0010 0111 00010 qqqqq 00000 1 cpslla1 crqc (c3_1) -(dni cpslla1_C3 "cpslla1 $crqc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslla1") VOLATILE) - "cpslla1 $crqc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7) - (f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpslla1" pc crqc) ) - () - ) - -; 1111 00xi iiii 0111 00011 00000 00000 1 cpsrlia1 imm5p7 (c3_imm) -(dni cpsrlia1_P1 "cpsrlia1 imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrlia1") VOLATILE) - "cpsrlia1 $imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrlia1" pc imm5p7) ) - () - ) - -; 1111 01xi iiii 0111 00011 00000 00000 1 cpsraia1 imm5p7 (c3_imm) -(dni cpsraia1_P1 "cpsraia1 imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsraia1") VOLATILE) - "cpsraia1 $imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraia1" pc imm5p7) ) - () - ) - -; 1111 10xi iiii 0111 00011 00000 00000 1 cpsllia1 imm5p7 (c3_imm) -(dni cpsllia1_P1 "cpsllia1 imm5p7 C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsllia1") VOLATILE) - "cpsllia1 $imm5p7" - (+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7) - (f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsllia1" pc imm5p7) ) - () - ) - -; 1111 0000 0000 0111 00001 qqqqq ppppp 1 cpssqa1u.b crqc,crpc (c3_1) -(dni cpssqa1u_b_C3 "cpssqa1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssqa1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0001 0111 00001 qqqqq ppppp 1 cpssqa1.b crqc,crpc (c3_1) -(dni cpssqa1_b_C3 "cpssqa1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI) VOLATILE) - "cpssqa1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0100 0111 00001 qqqqq ppppp 1 cpssda1u.b crqc,crpc (c3_1) -(dni cpssda1u_b_C3 "cpssda1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssda1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpssda1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 0101 0111 00001 qqqqq ppppp 1 cpssda1.b crqc,crpc (c3_1) -(dni cpssda1_b_C3 "cpssda1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b") (CPTYPE V8QI) VOLATILE) - "cpssda1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpssda1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1000 0111 00001 qqqqq ppppp 1 cpmula1u.b crqc,crpc (c3_1) -(dni cpmula1u_b_C3 "cpmula1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmula1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1u_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1001 0111 00001 qqqqq ppppp 1 cpmula1.b crqc,crpc (c3_1) -(dni cpmula1_b_C3 "cpmula1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b") (CPTYPE V8QI) VOLATILE) - "cpmula1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1_b" pc crqc crpc) ) - () - ) - -; 1111 0000 1010 0111 00001 qqqqq ppppp 1 cpmulua1.h crqc,crpc (c3_1) -(dni cpmulua1_h_C3 "cpmulua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1011 0111 00001 qqqqq ppppp 1 cpmulla1.h crqc,crpc (c3_1) -(dni cpmulla1_h_C3 "cpmulla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_h" pc crqc crpc) ) - () - ) - -; 1111 0000 1100 0111 00001 qqqqq ppppp 1 cpmulua1u.w crqc,crpc (c3_1) -(dni cpmulua1u_w_C3 "cpmulua1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulua1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1u_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1101 0111 00001 qqqqq ppppp 1 cpmulla1u.w crqc,crpc (c3_1) -(dni cpmulla1u_w_C3 "cpmulla1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulla1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1u_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1110 0111 00001 qqqqq ppppp 1 cpmulua1.w crqc,crpc (c3_1) -(dni cpmulua1_w_C3 "cpmulua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_w" pc crqc crpc) ) - () - ) - -; 1111 0000 1111 0111 00001 qqqqq ppppp 1 cpmulla1.w crqc,crpc (c3_1) -(dni cpmulla1_w_C3 "cpmulla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0000 0111 00001 qqqqq ppppp 1 cpmada1u.b crqc,crpc (c3_1) -(dni cpmada1u_b_C3 "cpmada1u.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmada1u.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1u_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0001 0111 00001 qqqqq ppppp 1 cpmada1.b crqc,crpc (c3_1) -(dni cpmada1_b_C3 "cpmada1.b $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b") (CPTYPE V8QI) VOLATILE) - "cpmada1.b $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1_b" pc crqc crpc) ) - () - ) - -; 1111 0001 0010 0111 00001 qqqqq ppppp 1 cpmadua1.h crqc,crpc (c3_1) -(dni cpmadua1_h_C3 "cpmadua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpmadua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0011 0111 00001 qqqqq ppppp 1 cpmadla1.h crqc,crpc (c3_1) -(dni cpmadla1_h_C3 "cpmadla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpmadla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 0100 0111 00001 qqqqq ppppp 1 cpmadua1u.w crqc,crpc (c3_1) -(dni cpmadua1u_w_C3 "cpmadua1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadua1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0101 0111 00001 qqqqq ppppp 1 cpmadla1u.w crqc,crpc (c3_1) -(dni cpmadla1u_w_C3 "cpmadla1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadla1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0110 0111 00001 qqqqq ppppp 1 cpmadua1.w crqc,crpc (c3_1) -(dni cpmadua1_w_C3 "cpmadua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpmadua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 0111 0111 00001 qqqqq ppppp 1 cpmadla1.w crqc,crpc (c3_1) -(dni cpmadla1_w_C3 "cpmadla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpmadla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1010 0111 00001 qqqqq ppppp 1 cpmsbua1.h crqc,crpc (c3_1) -(dni cpmsbua1_h_C3 "cpmsbua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1a) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 1011 0111 00001 qqqqq ppppp 1 cpmsbla1.h crqc,crpc (c3_1) -(dni cpmsbla1_h_C3 "cpmsbla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_h" pc crqc crpc) ) - () - ) - -; 1111 0001 1100 0111 00001 qqqqq ppppp 1 cpmsbua1u.w crqc,crpc (c3_1) -(dni cpmsbua1u_w_C3 "cpmsbua1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbua1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1101 0111 00001 qqqqq ppppp 1 cpmsbla1u.w crqc,crpc (c3_1) -(dni cpmsbla1u_w_C3 "cpmsbla1u.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbla1u.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1u_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1110 0111 00001 qqqqq ppppp 1 cpmsbua1.w crqc,crpc (c3_1) -(dni cpmsbua1_w_C3 "cpmsbua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1e) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_w" pc crqc crpc) ) - () - ) - -; 1111 0001 1111 0111 00001 qqqqq ppppp 1 cpmsbla1.w crqc,crpc (c3_1) -(dni cpmsbla1_w_C3 "cpmsbla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1f) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0010 0111 00001 qqqqq ppppp 1 cpsmadua1.h crqc,crpc (c3_1) -(dni cpsmadua1_h_C3 "cpsmadua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 0011 0111 00001 qqqqq ppppp 1 cpsmadla1.h crqc,crpc (c3_1) -(dni cpsmadla1_h_C3 "cpsmadla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 0110 0111 00001 qqqqq ppppp 1 cpsmadua1.w crqc,crpc (c3_1) -(dni cpsmadua1_w_C3 "cpsmadua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 0111 0111 00001 qqqqq ppppp 1 cpsmadla1.w crqc,crpc (c3_1) -(dni cpsmadla1_w_C3 "cpsmadla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1010 0111 00001 qqqqq ppppp 1 cpsmsbua1.h crqc,crpc (c3_1) -(dni cpsmsbua1_h_C3 "cpsmsbua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1a) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 1011 0111 00001 qqqqq ppppp 1 cpsmsbla1.h crqc,crpc (c3_1) -(dni cpsmsbla1_h_C3 "cpsmsbla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_h" pc crqc crpc) ) - () - ) - -; 1111 0011 1110 0111 00001 qqqqq ppppp 1 cpsmsbua1.w crqc,crpc (c3_1) -(dni cpsmsbua1_w_C3 "cpsmsbua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1e) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_w" pc crqc crpc) ) - () - ) - -; 1111 0011 1111 0111 00001 qqqqq ppppp 1 cpsmsbla1.w crqc,crpc (c3_1) -(dni cpsmsbla1_w_C3 "cpsmsbla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1f) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_w" pc crqc crpc) ) - () - ) - -; 1111 0100 1010 0111 00001 qqqqq ppppp 1 cpmulslua1.h crqc,crpc (c3_1) -(dni cpmulslua1_h_C3 "cpmulslua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xa) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_h" pc crqc crpc) ) - () - ) - -; 1111 0100 1011 0111 00001 qqqqq ppppp 1 cpmulslla1.h crqc,crpc (c3_1) -(dni cpmulslla1_h_C3 "cpmulslla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_h" pc crqc crpc) ) - () - ) - -; 1111 0100 1110 0111 00001 qqqqq ppppp 1 cpmulslua1.w crqc,crpc (c3_1) -(dni cpmulslua1_w_C3 "cpmulslua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xe) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_w" pc crqc crpc) ) - () - ) - -; 1111 0100 1111 0111 00001 qqqqq ppppp 1 cpmulslla1.w crqc,crpc (c3_1) -(dni cpmulslla1_w_C3 "cpmulslla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xf) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 0010 0111 00001 qqqqq ppppp 1 cpsmadslua1.h crqc,crpc (c3_1) -(dni cpsmadslua1_h_C3 "cpsmadslua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x12) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 0011 0111 00001 qqqqq ppppp 1 cpsmadslla1.h crqc,crpc (c3_1) -(dni cpsmadslla1_h_C3 "cpsmadslla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x13) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 0110 0111 00001 qqqqq ppppp 1 cpsmadslua1.w crqc,crpc (c3_1) -(dni cpsmadslua1_w_C3 "cpsmadslua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x16) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 0111 0111 00001 qqqqq ppppp 1 cpsmadslla1.w crqc,crpc (c3_1) -(dni cpsmadslla1_w_C3 "cpsmadslla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x17) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 1010 0111 00001 qqqqq ppppp 1 cpsmsbslua1.h crqc,crpc (c3_1) -(dni cpsmsbslua1_h_C3 "cpsmsbslua1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslua1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1a) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 1011 0111 00001 qqqqq ppppp 1 cpsmsbslla1.h crqc,crpc (c3_1) -(dni cpsmsbslla1_h_C3 "cpsmsbslla1.h $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslla1.h $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1b) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_h" pc crqc crpc) ) - () - ) - -; 1111 0111 1110 0111 00001 qqqqq ppppp 1 cpsmsbslua1.w crqc,crpc (c3_1) -(dni cpsmsbslua1_w_C3 "cpsmsbslua1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslua1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1e) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_w" pc crqc crpc) ) - () - ) - -; 1111 0111 1111 0111 00001 qqqqq ppppp 1 cpsmsbslla1.w crqc,crpc (c3_1) -(dni cpsmsbslla1_w_C3 "cpsmsbslla1.w $crqc,$crpc C3" - (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslla1.w $crqc,$crpc" - (+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1f) (f-sub4 7) - (f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) ) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_w" pc crqc crpc) ) - () - ) - -; 00000 00000 00000 00000 c0nop (p0_1) -(dni c0nop_P0_P0S "c0nop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p0-isa (SLOTS P0,P0S) (INTRINSIC "c0nop")) - "c0nop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x0) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_c0nop" pc) ) - () - ) - -; 00001 qqqqq ppppp ooooo cpadd3.b =crop,crqp,crpp (p0_1) -(dni cpadd3_b_P0S_P1 "cpadd3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpadd3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpadd3_b" pc crqp crpp)) ) - () - ) - -; 00010 qqqqq ppppp ooooo cpadd3.h =crop,crqp,crpp (p0_1) -(dni cpadd3_h_P0S_P1 "cpadd3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpadd3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x2) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpadd3_h" pc crqp crpp)) ) - () - ) - -; 00011 qqqqq ppppp ooooo cpadd3.w =crop,crqp,crpp (p0_1) -(dni cpadd3_w_P0S_P1 "cpadd3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpadd3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x3) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpadd3_w" pc crqp crpp)) ) - () - ) - -; 00101 qqqqq ppppp ooooo cpunpacku.b =crop,crqp,crpp (p0_1) -(dni cpunpacku_b_P0S_P1 "cpunpacku.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpunpacku.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x5) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpacku_b" pc crqp crpp)) ) - () - ) - -; 00110 qqqqq ppppp ooooo cpunpacku.h =crop,crqp,crpp (p0_1) -(dni cpunpacku_h_P0S_P1 "cpunpacku.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpunpacku.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x6) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpacku_h" pc crqp crpp)) ) - () - ) - -; 00111 qqqqq ppppp ooooo cpunpacku.w =crop,crqp,crpp (p0_1) -(dni cpunpacku_w_P0S_P1 "cpunpacku.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST)) - "cpunpacku.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x7) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpacku_w" pc crqp crpp)) ) - () - ) - -; 01001 qqqqq ppppp ooooo cpunpackl.b =crop,crqp,crpp (p0_1) -(dni cpunpackl_b_P0S_P1 "cpunpackl.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpunpackl.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x9) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpackl_b" pc crqp crpp)) ) - () - ) - -; 01010 qqqqq ppppp ooooo cpunpackl.h =crop,crqp,crpp (p0_1) -(dni cpunpackl_h_P0S_P1 "cpunpackl.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpunpackl.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xa) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpackl_h" pc crqp crpp)) ) - () - ) - -; 01011 qqqqq ppppp ooooo cpunpackl.w =crop,crqp,crpp (p0_1) -(dni cpunpackl_w_P0S_P1 "cpunpackl.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST)) - "cpunpackl.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xb) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpunpackl_w" pc crqp crpp)) ) - () - ) - -; 00100 qqqqq ppppp ooooo cpsel =crop,crqp,crpp (p0_1) -(dni cpsel_P0S_P1 "cpsel $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpsel $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x4) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsel" pc crqp crpp)) ) - () - ) - -; 01100 qqqqq ppppp ooooo cpfsftbs0 =crop,crqp,crpp (p0_1) -(dni cpfsftbs0_P0S_P1 "cpfsftbs0 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs0 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xc) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpfsftbs0" pc crqp crpp)) ) - () - ) - -; 01101 qqqqq ppppp ooooo cpfsftbs1 =crop,crqp,crpp (p0_1) -(dni cpfsftbs1_P0S_P1 "cpfsftbs1 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpfsftbs1 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xd) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpfsftbs1" pc crqp crpp)) ) - () - ) - -; 10000 qqqqq 00000 ooooo cpmov =crop,crqp (p0_1) -(dni cpmov_P0S_P1 "cpmov $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpmov $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmov" pc crqp)) ) - () - ) - -; 10000 qqqqq 00001 ooooo cpabsz.b =crop,crqp (p0_1) -(dni cpabsz_b_P0S_P1 "cpabsz.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsz.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsz_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 00010 ooooo cpabsz.h =crop,crqp (p0_1) -(dni cpabsz_h_P0S_P1 "cpabsz.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabsz.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsz_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 00011 ooooo cpabsz.w =crop,crqp (p0_1) -(dni cpabsz_w_P0S_P1 "cpabsz.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpabsz.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsz_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 00100 ooooo cpldz.h =crop,crqp (p0_1) -(dni cpldz_h_P0S_P1 "cpldz.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST)) - "cpldz.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpldz_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 00101 ooooo cpldz.w =crop,crqp (p0_1) -(dni cpldz_w_P0S_P1 "cpldz.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST)) - "cpldz.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpldz_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 00110 ooooo cpnorm.h =crop,crqp (p0_1) -(dni cpnorm_h_P0S_P1 "cpnorm.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST)) - "cpnorm.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpnorm_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 00111 ooooo cpnorm.w =crop,crqp (p0_1) -(dni cpnorm_w_P0S_P1 "cpnorm.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST)) - "cpnorm.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpnorm_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 01000 ooooo cphaddu.b =crop,crqp (p0_1) -(dni cphaddu_b_P0S_P1 "cphaddu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cphaddu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphaddu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01001 ooooo cphadd.b =crop,crqp (p0_1) -(dni cphadd_b_P0S_P1 "cphadd.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST)) - "cphadd.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphadd_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01010 ooooo cphadd.h =crop,crqp (p0_1) -(dni cphadd_h_P0S_P1 "cphadd.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST)) - "cphadd.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphadd_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 01011 ooooo cphadd.w =crop,crqp (p0_1) -(dni cphadd_w_P0S_P1 "cphadd.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST)) - "cphadd.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cphadd_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 01100 00000 cpccadd.b +crqp (p0_1) -(dni cpccadd_b_P0S_P1 "cpccadd.b $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY) VOLATILE) - "cpccadd.b $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xc) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpccadd_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01101 ooooo cpbcast.b =crop,crqp (p0_1) -(dni cpbcast_b_P0S_P1 "cpbcast.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST)) - "cpbcast.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpbcast_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 01110 ooooo cpbcast.h =crop,crqp (p0_1) -(dni cpbcast_h_P0S_P1 "cpbcast.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST)) - "cpbcast.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpbcast_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 01111 ooooo cpbcast.w =crop,crqp (p0_1) -(dni cpbcast_w_P0S_P1 "cpbcast.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST)) - "cpbcast.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpbcast_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 10000 ooooo cpextuu.b =crop,crqp (p0_1) -(dni cpextuu_b_P0S_P1 "cpextuu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextuu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10001 ooooo cpextu.b =crop,crqp (p0_1) -(dni cpextu_b_P0S_P1 "cpextu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10010 ooooo cpextuu.h =crop,crqp (p0_1) -(dni cpextuu_h_P0S_P1 "cpextuu.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextuu.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuu_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 10011 ooooo cpextu.h =crop,crqp (p0_1) -(dni cpextu_h_P0S_P1 "cpextu.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextu.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextu_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 10100 ooooo cpextlu.b =crop,crqp (p0_1) -(dni cpextlu_b_P0S_P1 "cpextlu.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST)) - "cpextlu.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x14) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlu_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10101 ooooo cpextl.b =crop,crqp (p0_1) -(dni cpextl_b_P0S_P1 "cpextl.b $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextl.b $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x15) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextl_b" pc crqp)) ) - () - ) - -; 10000 qqqqq 10110 ooooo cpextlu.h =crop,crqp (p0_1) -(dni cpextlu_h_P0S_P1 "cpextlu.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST)) - "cpextlu.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x16) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlu_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 10111 ooooo cpextl.h =crop,crqp (p0_1) -(dni cpextl_h_P0S_P1 "cpextl.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST)) - "cpextl.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x17) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextl_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 11000 ooooo cpcastub.h =crop,crqp (p0_1) -(dni cpcastub_h_P0S_P1 "cpcastub.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastub.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x18) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastub_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 11001 ooooo cpcastb.h =crop,crqp (p0_1) -(dni cpcastb_h_P0S_P1 "cpcastb.h $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST)) - "cpcastb.h $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x19) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastb_h" pc crqp)) ) - () - ) - -; 10000 qqqqq 11100 ooooo cpcastub.w =crop,crqp (p0_1) -(dni cpcastub_w_P0S_P1 "cpcastub.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastub.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1c) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastub_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11101 ooooo cpcastb.w =crop,crqp (p0_1) -(dni cpcastb_w_P0S_P1 "cpcastb.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastb.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1d) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastb_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11110 ooooo cpcastuh.w =crop,crqp (p0_1) -(dni cpcastuh_w_P0S_P1 "cpcastuh.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcastuh.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1e) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcastuh_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11111 ooooo cpcasth.w =crop,crqp (p0_1) -(dni cpcasth_w_P0S_P1 "cpcasth.w $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST)) - "cpcasth.w $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1f) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpcasth_w" pc crqp)) ) - () - ) - -; 10000 qqqqq 11010 ooooo cdcastuw =crop,crqp (p0_1) -(dni cdcastuw_P0S_P1 "cdcastuw $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastuw $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1a) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdcastuw" pc crqp)) ) - () - ) - -; 10000 qqqqq 11011 ooooo cdcastw =crop,crqp (p0_1) -(dni cdcastw_P0S_P1 "cdcastw $crop,$crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdcastw $crop,$crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1b) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdcastw" pc crqp)) ) - () - ) - -; 10001 00000 00000 ooooo cpmovfrcsar0 =crop (p0_1) -(dni cpmovfrcsar0_P0S_P1 "cpmovfrcsar0 $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar0 $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovfrcsar0" pc)) ) - () - ) - -; 10001 00000 01111 ooooo cpmovfrcsar1 =crop (p0_1) -(dni cpmovfrcsar1_P0S_P1 "cpmovfrcsar1 $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcsar1 $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovfrcsar1" pc)) ) - () - ) - -; 10001 00000 00001 ooooo cpmovfrcc =crop (p0_1) -(dni cpmovfrcc_P0S_P1 "cpmovfrcc $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST) VOLATILE) - "cpmovfrcc $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovfrcc" pc)) ) - () - ) - -; 10001 qqqqq 10000 00000 cpmovtocsar0 crqp (p0_1) -(dni cpmovtocsar0_P0S_P1 "cpmovtocsar0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0") VOLATILE) - "cpmovtocsar0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar0 0) - (c-call "ivc2_cpmovtocsar0" pc crqp) ) - () - ) - -; 10001 qqqqq 11111 00000 cpmovtocsar1 crqp (p0_1) -(dni cpmovtocsar1_P0S_P1 "cpmovtocsar1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1") VOLATILE) - "cpmovtocsar1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x1f) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_csar1 0) - (c-call "ivc2_cpmovtocsar1" pc crqp) ) - () - ) - -; 10001 qqqqq 10001 00000 cpmovtocc crqp (p0_1) -(dni cpmovtocc_P0S_P1 "cpmovtocc $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc") VOLATILE) - "cpmovtocc $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpmovtocc" pc crqp) ) - () - ) - -; 10010 qqqqq ppppp 00000 cpcmpeqz.b crqp,crpp (p0_1) -(dni cpcmpeqz_b_P0S_P1 "cpcmpeqz.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeqz.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeqz_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 00001 cpcmpeq.b crqp,crpp (p0_1) -(dni cpcmpeq_b_P0S_P1 "cpcmpeq.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI) VOLATILE) - "cpcmpeq.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 00011 cpcmpeq.h crqp,crpp (p0_1) -(dni cpcmpeq_h_P0S_P1 "cpcmpeq.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI) VOLATILE) - "cpcmpeq.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 00101 cpcmpeq.w crqp,crpp (p0_1) -(dni cpcmpeq_w_P0S_P1 "cpcmpeq.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI) VOLATILE) - "cpcmpeq.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpeq_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 01001 cpcmpne.b crqp,crpp (p0_1) -(dni cpcmpne_b_P0S_P1 "cpcmpne.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI) VOLATILE) - "cpcmpne.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 01011 cpcmpne.h crqp,crpp (p0_1) -(dni cpcmpne_h_P0S_P1 "cpcmpne.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI) VOLATILE) - "cpcmpne.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 01101 cpcmpne.w crqp,crpp (p0_1) -(dni cpcmpne_w_P0S_P1 "cpcmpne.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI) VOLATILE) - "cpcmpne.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpne_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10000 cpcmpgtu.b crqp,crpp (p0_1) -(dni cpcmpgtu_b_P0S_P1 "cpcmpgtu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgtu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10001 cpcmpgt.b crqp,crpp (p0_1) -(dni cpcmpgt_b_P0S_P1 "cpcmpgt.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI) VOLATILE) - "cpcmpgt.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10011 cpcmpgt.h crqp,crpp (p0_1) -(dni cpcmpgt_h_P0S_P1 "cpcmpgt.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI) VOLATILE) - "cpcmpgt.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10100 cpcmpgtu.w crqp,crpp (p0_1) -(dni cpcmpgtu_w_P0S_P1 "cpcmpgtu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgtu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgtu_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 10101 cpcmpgt.w crqp,crpp (p0_1) -(dni cpcmpgt_w_P0S_P1 "cpcmpgt.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI) VOLATILE) - "cpcmpgt.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgt_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11000 cpcmpgeu.b crqp,crpp (p0_1) -(dni cpcmpgeu_b_P0S_P1 "cpcmpgeu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI) VOLATILE) - "cpcmpgeu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11001 cpcmpge.b crqp,crpp (p0_1) -(dni cpcmpge_b_P0S_P1 "cpcmpge.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI) VOLATILE) - "cpcmpge.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_b" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11011 cpcmpge.h crqp,crpp (p0_1) -(dni cpcmpge_h_P0S_P1 "cpcmpge.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI) VOLATILE) - "cpcmpge.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_h" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11100 cpcmpgeu.w crqp,crpp (p0_1) -(dni cpcmpgeu_w_P0S_P1 "cpcmpgeu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI) VOLATILE) - "cpcmpgeu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpgeu_w" pc crqp crpp) ) - () - ) - -; 10010 qqqqq ppppp 11101 cpcmpge.w crqp,crpp (p0_1) -(dni cpcmpge_w_P0S_P1 "cpcmpge.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI) VOLATILE) - "cpcmpge.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cc 0) - (c-call "ivc2_cpcmpge_w" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00000 cpadda0u.b crqp,crpp (p0_1) -(dni cpadda0u_b_P0S "cpadda0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b") (CPTYPE V8UQI) VOLATILE) - "cpadda0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpadda0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00001 cpadda0.b crqp,crpp (p0_1) -(dni cpadda0_b_P0S "cpadda0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b") (CPTYPE V8QI) VOLATILE) - "cpadda0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpadda0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00010 cpaddua0.h crqp,crpp (p0_1) -(dni cpaddua0_h_P0S "cpaddua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h") (CPTYPE V4HI) VOLATILE) - "cpaddua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpaddua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00011 cpaddla0.h crqp,crpp (p0_1) -(dni cpaddla0_h_P0S "cpaddla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h") (CPTYPE V4HI) VOLATILE) - "cpaddla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpaddla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00100 cpaddaca0u.b crqp,crpp (p0_1) -(dni cpaddaca0u_b_P0S "cpaddaca0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b") (CPTYPE V8UQI) VOLATILE) - "cpaddaca0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddaca0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00101 cpaddaca0.b crqp,crpp (p0_1) -(dni cpaddaca0_b_P0S "cpaddaca0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b") (CPTYPE V8QI) VOLATILE) - "cpaddaca0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddaca0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00110 cpaddacua0.h crqp,crpp (p0_1) -(dni cpaddacua0_h_P0S "cpaddacua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h") (CPTYPE V4HI) VOLATILE) - "cpaddacua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddacua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 00111 cpaddacla0.h crqp,crpp (p0_1) -(dni cpaddacla0_h_P0S "cpaddacla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h") (CPTYPE V4HI) VOLATILE) - "cpaddacla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpaddacla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01000 cpsuba0u.b crqp,crpp (p0_1) -(dni cpsuba0u_b_P0S "cpsuba0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b") (CPTYPE V8UQI) VOLATILE) - "cpsuba0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsuba0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01001 cpsuba0.b crqp,crpp (p0_1) -(dni cpsuba0_b_P0S "cpsuba0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b") (CPTYPE V8QI) VOLATILE) - "cpsuba0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsuba0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01010 cpsubua0.h crqp,crpp (p0_1) -(dni cpsubua0_h_P0S "cpsubua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h") (CPTYPE V4HI) VOLATILE) - "cpsubua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsubua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01011 cpsubla0.h crqp,crpp (p0_1) -(dni cpsubla0_h_P0S "cpsubla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h") (CPTYPE V4HI) VOLATILE) - "cpsubla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpsubla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01100 cpsubaca0u.b crqp,crpp (p0_1) -(dni cpsubaca0u_b_P0S "cpsubaca0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b") (CPTYPE V8UQI) VOLATILE) - "cpsubaca0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubaca0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01101 cpsubaca0.b crqp,crpp (p0_1) -(dni cpsubaca0_b_P0S "cpsubaca0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b") (CPTYPE V8QI) VOLATILE) - "cpsubaca0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubaca0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01110 cpsubacua0.h crqp,crpp (p0_1) -(dni cpsubacua0_h_P0S "cpsubacua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h") (CPTYPE V4HI) VOLATILE) - "cpsubacua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubacua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 01111 cpsubacla0.h crqp,crpp (p0_1) -(dni cpsubacla0_h_P0S "cpsubacla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h") (CPTYPE V4HI) VOLATILE) - "cpsubacla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsubacla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10000 cpabsa0u.b crqp,crpp (p0_1) -(dni cpabsa0u_b_P0S "cpabsa0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b") (CPTYPE V8UQI) VOLATILE) - "cpabsa0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpabsa0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10001 cpabsa0.b crqp,crpp (p0_1) -(dni cpabsa0_b_P0S "cpabsa0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b") (CPTYPE V8QI) VOLATILE) - "cpabsa0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpabsa0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10010 cpabsua0.h crqp,crpp (p0_1) -(dni cpabsua0_h_P0S "cpabsua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h") (CPTYPE V4HI) VOLATILE) - "cpabsua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpabsua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10011 cpabsla0.h crqp,crpp (p0_1) -(dni cpabsla0_h_P0S "cpabsla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h") (CPTYPE V4HI) VOLATILE) - "cpabsla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpabsla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10100 cpsada0u.b crqp,crpp (p0_1) -(dni cpsada0u_b_P0S "cpsada0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b") (CPTYPE V8UQI) VOLATILE) - "cpsada0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsada0u_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10101 cpsada0.b crqp,crpp (p0_1) -(dni cpsada0_b_P0S "cpsada0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b") (CPTYPE V8QI) VOLATILE) - "cpsada0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsada0_b" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10110 cpsadua0.h crqp,crpp (p0_1) -(dni cpsadua0_h_P0S "cpsadua0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h") (CPTYPE V4HI) VOLATILE) - "cpsadua0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsadua0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 10111 cpsadla0.h crqp,crpp (p0_1) -(dni cpsadla0_h_P0S "cpsadla0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h") (CPTYPE V4HI) VOLATILE) - "cpsadla0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpsadla0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 11011 cpseta0.h crqp,crpp (p0_1) -(dni cpseta0_h_P0S "cpseta0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h") (CPTYPE V4HI) VOLATILE) - "cpseta0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpseta0_h" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 11100 cpsetua0.w crqp,crpp (p0_1) -(dni cpsetua0_w_P0S "cpsetua0.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w") (CPTYPE V2SI) VOLATILE) - "cpsetua0.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsetua0_w" pc crqp crpp) ) - () - ) - -; 11000 qqqqq ppppp 11101 cpsetla0.w crqp,crpp (p0_1) -(dni cpsetla0_w_P0S "cpsetla0.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w") (CPTYPE V2SI) VOLATILE) - "cpsetla0.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpsetla0_w" pc crqp crpp) ) - () - ) - -; 11001 00000 00001 ooooo cpmova0.b =crop (p0_1) -(dni cpmova0_b_P0S "cpmova0.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmova0_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cpmova0.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmova0_b" pc)) ) - () - ) - -; 11001 00000 00010 ooooo cpmovua0.h =crop (p0_1) -(dni cpmovua0_h_P0S "cpmovua0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovua0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovua0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovua0_h" pc)) ) - () - ) - -; 11001 00000 00011 ooooo cpmovla0.h =crop (p0_1) -(dni cpmovla0_h_P0S "cpmovla0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovla0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovla0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovla0_h" pc)) ) - () - ) - -; 11001 00000 00100 ooooo cpmovuua0.w =crop (p0_1) -(dni cpmovuua0_w_P0S "cpmovuua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovuua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovuua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovuua0_w" pc)) ) - () - ) - -; 11001 00000 00101 ooooo cpmovula0.w =crop (p0_1) -(dni cpmovula0_w_P0S "cpmovula0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovula0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovula0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovula0_w" pc)) ) - () - ) - -; 11001 00000 00110 ooooo cpmovlua0.w =crop (p0_1) -(dni cpmovlua0_w_P0S "cpmovlua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlua0_w" pc)) ) - () - ) - -; 11001 00000 00111 ooooo cpmovlla0.w =crop (p0_1) -(dni cpmovlla0_w_P0S "cpmovlla0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlla0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlla0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlla0_w" pc)) ) - () - ) - -; 11001 00000 01000 ooooo cppacka0u.b =crop (p0_1) -(dni cppacka0u_b_P0S "cppacka0u.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0u_b") (CPTYPE V8UQI) (CRET FIRST) VOLATILE) - "cppacka0u.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka0u_b" pc)) ) - () - ) - -; 11001 00000 01001 ooooo cppacka0.b =crop (p0_1) -(dni cppacka0_b_P0S "cppacka0.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cppacka0.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka0_b" pc)) ) - () - ) - -; 11001 00000 01010 ooooo cppackua0.h =crop (p0_1) -(dni cppackua0_h_P0S "cppackua0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackua0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua0_h" pc)) ) - () - ) - -; 11001 00000 01011 ooooo cppackla0.h =crop (p0_1) -(dni cppackla0_h_P0S "cppackla0.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackla0.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla0_h" pc)) ) - () - ) - -; 11001 00000 01100 ooooo cppackua0.w =crop (p0_1) -(dni cppackua0_w_P0S "cppackua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua0_w" pc)) ) - () - ) - -; 11001 00000 01101 ooooo cppackla0.w =crop (p0_1) -(dni cppackla0_w_P0S "cppackla0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackla0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla0_w" pc)) ) - () - ) - -; 11001 00000 01110 ooooo cpmovhua0.w =crop (p0_1) -(dni cpmovhua0_w_P0S "cpmovhua0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhua0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhua0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhua0_w" pc)) ) - () - ) - -; 11001 00000 01111 ooooo cpmovhla0.w =crop (p0_1) -(dni cpmovhla0_w_P0S "cpmovhla0.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhla0_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhla0.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhla0_w" pc)) ) - () - ) - -; 11001 00000 10000 00000 cpacsuma0 (p0_1) -(dni cpacsuma0_P0S "cpacsuma0 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpacsuma0") VOLATILE) - "cpacsuma0" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpacsuma0" pc) ) - () - ) - -; 11001 00000 10001 00000 cpaccpa0 (p0_1) -(dni cpaccpa0_P0S "cpaccpa0 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaccpa0") VOLATILE) - "cpaccpa0" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpaccpa0" pc) ) - () - ) - -; 11001 qqqqq 11000 00000 cpsrla0 crqp (p0_1) -(dni cpsrla0_P0S "cpsrla0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrla0") VOLATILE) - "cpsrla0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsrla0" pc crqp) ) - () - ) - -; 11001 qqqqq 11001 00000 cpsraa0 crqp (p0_1) -(dni cpsraa0_P0S "cpsraa0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraa0") VOLATILE) - "cpsraa0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsraa0" pc crqp) ) - () - ) - -; 11001 qqqqq 11010 00000 cpslla0 crqp (p0_1) -(dni cpslla0_P0S "cpslla0 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpslla0") VOLATILE) - "cpslla0 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpslla0" pc crqp) ) - () - ) - -; 11001 00000 11100 iiiii cpsrlia0 imm5p23 (p0_1) -(dni cpsrlia0_P0S "cpsrlia0 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsrlia0") VOLATILE) - "cpsrlia0 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsrlia0" pc imm5p23) ) - () - ) - -; 11001 00000 11101 iiiii cpsraia0 imm5p23 (p0_1) -(dni cpsraia0_P0S "cpsraia0 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsraia0") VOLATILE) - "cpsraia0 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsraia0" pc imm5p23) ) - () - ) - -; 11001 00000 11110 iiiii cpsllia0 imm5p23 (p0_1) -(dni cpsllia0_P0S "cpsllia0 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsllia0") VOLATILE) - "cpsllia0 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpsllia0" pc imm5p23) ) - () - ) - -; 11111 qqqqq ppppp 00000 cpfsftba0s0u.b crqp,crpp (p0_1) -(dni cpfsftba0s0u_b_P0S "cpfsftba0s0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfsftba0s0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s0u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00001 cpfsftba0s0.b crqp,crpp (p0_1) -(dni cpfsftba0s0_b_P0S "cpfsftba0s0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b") (CPTYPE V8QI) VOLATILE) - "cpfsftba0s0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s0_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00010 cpfsftbua0s0.h crqp,crpp (p0_1) -(dni cpfsftbua0s0_h_P0S "cpfsftbua0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbua0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftbua0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00011 cpfsftbla0s0.h crqp,crpp (p0_1) -(dni cpfsftbla0s0_h_P0S "cpfsftbla0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbla0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpfsftbla0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00100 cpfaca0s0u.b crqp,crpp (p0_1) -(dni cpfaca0s0u_b_P0S "cpfaca0s0u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfaca0s0u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s0u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00101 cpfaca0s0.b crqp,crpp (p0_1) -(dni cpfaca0s0_b_P0S "cpfaca0s0.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b") (CPTYPE V8QI) VOLATILE) - "cpfaca0s0.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s0_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00110 cpfacua0s0.h crqp,crpp (p0_1) -(dni cpfacua0s0_h_P0S "cpfacua0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfacua0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacua0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 00111 cpfacla0s0.h crqp,crpp (p0_1) -(dni cpfacla0s0_h_P0S "cpfacla0s0.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h") (CPTYPE V4HI) VOLATILE) - "cpfacla0s0.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacla0s0_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01000 cpfsftba0s1u.b crqp,crpp (p0_1) -(dni cpfsftba0s1u_b_P0S "cpfsftba0s1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfsftba0s1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s1u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01001 cpfsftba0s1.b crqp,crpp (p0_1) -(dni cpfsftba0s1_b_P0S "cpfsftba0s1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b") (CPTYPE V8QI) VOLATILE) - "cpfsftba0s1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftba0s1_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01010 cpfsftbua0s1.h crqp,crpp (p0_1) -(dni cpfsftbua0s1_h_P0S "cpfsftbua0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbua0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (c-call "ivc2_cpfsftbua0s1_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01011 cpfsftbla0s1.h crqp,crpp (p0_1) -(dni cpfsftbla0s1_h_P0S "cpfsftbla0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfsftbla0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (c-call "ivc2_cpfsftbla0s1_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01100 cpfaca0s1u.b crqp,crpp (p0_1) -(dni cpfaca0s1u_b_P0S "cpfaca0s1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfaca0s1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s1u_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01101 cpfaca0s1.b crqp,crpp (p0_1) -(dni cpfaca0s1_b_P0S "cpfaca0s1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b") (CPTYPE V8QI) VOLATILE) - "cpfaca0s1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfaca0s1_b" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01110 cpfacua0s1.h crqp,crpp (p0_1) -(dni cpfacua0s1_h_P0S "cpfacua0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfacua0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacua0s1_h" pc crqp crpp) ) - () - ) - -; 11111 qqqqq ppppp 01111 cpfacla0s1.h crqp,crpp (p0_1) -(dni cpfacla0s1_h_P0S "cpfacla0s1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h") (CPTYPE V4HI) VOLATILE) - "cpfacla0s1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_cofa0 0) - (c-call "ivc2_cpfacla0s1_h" pc crqp crpp) ) - () - ) - -; xxxxxiii 01000 qqqqq ppppp ooooo cpfsftbi =crop,crqp,crpp,imm3p5 (p0_1) -(dni cpfsftbi_P0_P1 "cpfsftbi $crop,$crqp,$crpp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cpfsftbi $crop,$crqp,$crpp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x8) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpfsftbi" pc crqp crpp imm3p5)) ) - () - ) - -; 00000000 10011 qqqqq ppppp 00001 cpacmpeq.b crqp,crpp (p0_1) -(dni cpacmpeq_b_P0_P1 "cpacmpeq.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI)) - "cpacmpeq.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpeq_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 00011 cpacmpeq.h crqp,crpp (p0_1) -(dni cpacmpeq_h_P0_P1 "cpacmpeq.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI)) - "cpacmpeq.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpeq_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 00101 cpacmpeq.w crqp,crpp (p0_1) -(dni cpacmpeq_w_P0_P1 "cpacmpeq.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI)) - "cpacmpeq.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpeq_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 01001 cpacmpne.b crqp,crpp (p0_1) -(dni cpacmpne_b_P0_P1 "cpacmpne.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI)) - "cpacmpne.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpne_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 01011 cpacmpne.h crqp,crpp (p0_1) -(dni cpacmpne_h_P0_P1 "cpacmpne.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI)) - "cpacmpne.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpne_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 01101 cpacmpne.w crqp,crpp (p0_1) -(dni cpacmpne_w_P0_P1 "cpacmpne.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI)) - "cpacmpne.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpne_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10000 cpacmpgtu.b crqp,crpp (p0_1) -(dni cpacmpgtu_b_P0_P1 "cpacmpgtu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI)) - "cpacmpgtu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgtu_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10001 cpacmpgt.b crqp,crpp (p0_1) -(dni cpacmpgt_b_P0_P1 "cpacmpgt.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI)) - "cpacmpgt.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgt_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10011 cpacmpgt.h crqp,crpp (p0_1) -(dni cpacmpgt_h_P0_P1 "cpacmpgt.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI)) - "cpacmpgt.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgt_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10100 cpacmpgtu.w crqp,crpp (p0_1) -(dni cpacmpgtu_w_P0_P1 "cpacmpgtu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI)) - "cpacmpgtu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgtu_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 10101 cpacmpgt.w crqp,crpp (p0_1) -(dni cpacmpgt_w_P0_P1 "cpacmpgt.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI)) - "cpacmpgt.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgt_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11000 cpacmpgeu.b crqp,crpp (p0_1) -(dni cpacmpgeu_b_P0_P1 "cpacmpgeu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI)) - "cpacmpgeu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgeu_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11001 cpacmpge.b crqp,crpp (p0_1) -(dni cpacmpge_b_P0_P1 "cpacmpge.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI)) - "cpacmpge.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpge_b" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11011 cpacmpge.h crqp,crpp (p0_1) -(dni cpacmpge_h_P0_P1 "cpacmpge.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI)) - "cpacmpge.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpge_h" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11100 cpacmpgeu.w crqp,crpp (p0_1) -(dni cpacmpgeu_w_P0_P1 "cpacmpgeu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI)) - "cpacmpgeu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpgeu_w" pc crqp crpp) ) - () - ) - -; 00000000 10011 qqqqq ppppp 11101 cpacmpge.w crqp,crpp (p0_1) -(dni cpacmpge_w_P0_P1 "cpacmpge.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI)) - "cpacmpge.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpacmpge_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 00001 cpocmpeq.b crqp,crpp (p0_1) -(dni cpocmpeq_b_P0_P1 "cpocmpeq.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI)) - "cpocmpeq.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpeq_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 00011 cpocmpeq.h crqp,crpp (p0_1) -(dni cpocmpeq_h_P0_P1 "cpocmpeq.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI)) - "cpocmpeq.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpeq_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 00101 cpocmpeq.w crqp,crpp (p0_1) -(dni cpocmpeq_w_P0_P1 "cpocmpeq.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI)) - "cpocmpeq.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpeq_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 01001 cpocmpne.b crqp,crpp (p0_1) -(dni cpocmpne_b_P0_P1 "cpocmpne.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI)) - "cpocmpne.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpne_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 01011 cpocmpne.h crqp,crpp (p0_1) -(dni cpocmpne_h_P0_P1 "cpocmpne.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI)) - "cpocmpne.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpne_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 01101 cpocmpne.w crqp,crpp (p0_1) -(dni cpocmpne_w_P0_P1 "cpocmpne.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI)) - "cpocmpne.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpne_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10000 cpocmpgtu.b crqp,crpp (p0_1) -(dni cpocmpgtu_b_P0_P1 "cpocmpgtu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI)) - "cpocmpgtu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgtu_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10001 cpocmpgt.b crqp,crpp (p0_1) -(dni cpocmpgt_b_P0_P1 "cpocmpgt.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI)) - "cpocmpgt.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgt_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10011 cpocmpgt.h crqp,crpp (p0_1) -(dni cpocmpgt_h_P0_P1 "cpocmpgt.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI)) - "cpocmpgt.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgt_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10100 cpocmpgtu.w crqp,crpp (p0_1) -(dni cpocmpgtu_w_P0_P1 "cpocmpgtu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI)) - "cpocmpgtu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgtu_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 10101 cpocmpgt.w crqp,crpp (p0_1) -(dni cpocmpgt_w_P0_P1 "cpocmpgt.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI)) - "cpocmpgt.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgt_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11000 cpocmpgeu.b crqp,crpp (p0_1) -(dni cpocmpgeu_b_P0_P1 "cpocmpgeu.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI)) - "cpocmpgeu.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgeu_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11001 cpocmpge.b crqp,crpp (p0_1) -(dni cpocmpge_b_P0_P1 "cpocmpge.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI)) - "cpocmpge.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpge_b" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11011 cpocmpge.h crqp,crpp (p0_1) -(dni cpocmpge_h_P0_P1 "cpocmpge.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI)) - "cpocmpge.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpge_h" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11100 cpocmpgeu.w crqp,crpp (p0_1) -(dni cpocmpgeu_w_P0_P1 "cpocmpgeu.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI)) - "cpocmpgeu.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpgeu_w" pc crqp crpp) ) - () - ) - -; 00000001 10011 qqqqq ppppp 11101 cpocmpge.w crqp,crpp (p0_1) -(dni cpocmpge_w_P0_P1 "cpocmpge.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI)) - "cpocmpge.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_cpocmpge_w" pc crqp crpp) ) - () - ) - -; 00000011 10100 qqqqq ppppp ooooo cdadd3 =crop,crqp,crpp (p0_1) -(dni cdadd3_P0_P1 "cdadd3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdadd3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdadd3" pc crqp crpp)) ) - () - ) - -; 00000100 10100 qqqqq ppppp ooooo cpsub3.b =crop,crqp,crpp (p0_1) -(dni cpsub3_b_P0_P1 "cpsub3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsub3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsub3_b" pc crqp crpp)) ) - () - ) - -; 00000101 10100 qqqqq ppppp ooooo cpsub3.h =crop,crqp,crpp (p0_1) -(dni cpsub3_h_P0_P1 "cpsub3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsub3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x5) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsub3_h" pc crqp crpp)) ) - () - ) - -; 00000110 10100 qqqqq ppppp ooooo cpsub3.w =crop,crqp,crpp (p0_1) -(dni cpsub3_w_P0_P1 "cpsub3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsub3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x6) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsub3_w" pc crqp crpp)) ) - () - ) - -; 00000111 10100 qqqqq ppppp ooooo cdsub3 =crop,crqp,crpp (p0_1) -(dni cdsub3_P0_P1 "cdsub3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsub3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x7) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsub3" pc crqp crpp)) ) - () - ) - -; 00001010 10100 qqqqq ppppp ooooo cpsadd3.h =crop,crqp,crpp (p0_1) -(dni cpsadd3_h_P0_P1 "cpsadd3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsadd3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xa) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsadd3_h" pc crqp crpp)) ) - () - ) - -; 00001011 10100 qqqqq ppppp ooooo cpsadd3.w =crop,crqp,crpp (p0_1) -(dni cpsadd3_w_P0_P1 "cpsadd3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsadd3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xb) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsadd3_w" pc crqp crpp)) ) - () - ) - -; 00001110 10100 qqqqq ppppp ooooo cpssub3.h =crop,crqp,crpp (p0_1) -(dni cpssub3_h_P0_P1 "cpssub3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpssub3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xe) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set crop (c-call DI "ivc2_cpssub3_h" pc crqp crpp)) ) - () - ) - -; 00001111 10100 qqqqq ppppp ooooo cpssub3.w =crop,crqp,crpp (p0_1) -(dni cpssub3_w_P0_P1 "cpssub3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpssub3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #xf) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_cofr0 0) - (set crop (c-call DI "ivc2_cpssub3_w" pc crqp crpp)) ) - () - ) - -; 00010000 10100 qqqqq ppppp ooooo cpextuaddu3.b =crop,crqp,crpp (p0_1) -(dni cpextuaddu3_b_P0_P1 "cpextuaddu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuaddu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x10) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuaddu3_b" pc crqp crpp)) ) - () - ) - -; 00010001 10100 qqqqq ppppp ooooo cpextuadd3.b =crop,crqp,crpp (p0_1) -(dni cpextuadd3_b_P0_P1 "cpextuadd3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextuadd3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x11) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextuadd3_b" pc crqp crpp)) ) - () - ) - -; 00010010 10100 qqqqq ppppp ooooo cpextladdu3.b =crop,crqp,crpp (p0_1) -(dni cpextladdu3_b_P0_P1 "cpextladdu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladdu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x12) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextladdu3_b" pc crqp crpp)) ) - () - ) - -; 00010011 10100 qqqqq ppppp ooooo cpextladd3.b =crop,crqp,crpp (p0_1) -(dni cpextladd3_b_P0_P1 "cpextladd3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextladd3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x13) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextladd3_b" pc crqp crpp)) ) - () - ) - -; 00010100 10100 qqqqq ppppp ooooo cpextusubu3.b =crop,crqp,crpp (p0_1) -(dni cpextusubu3_b_P0_P1 "cpextusubu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusubu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x14) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextusubu3_b" pc crqp crpp)) ) - () - ) - -; 00010101 10100 qqqqq ppppp ooooo cpextusub3.b =crop,crqp,crpp (p0_1) -(dni cpextusub3_b_P0_P1 "cpextusub3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextusub3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x15) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextusub3_b" pc crqp crpp)) ) - () - ) - -; 00010110 10100 qqqqq ppppp ooooo cpextlsubu3.b =crop,crqp,crpp (p0_1) -(dni cpextlsubu3_b_P0_P1 "cpextlsubu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsubu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x16) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlsubu3_b" pc crqp crpp)) ) - () - ) - -; 00010111 10100 qqqqq ppppp ooooo cpextlsub3.b =crop,crqp,crpp (p0_1) -(dni cpextlsub3_b_P0_P1 "cpextlsub3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpextlsub3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x17) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpextlsub3_b" pc crqp crpp)) ) - () - ) - -; 00011000 10100 qqqqq ppppp ooooo cpaveu3.b =crop,crqp,crpp (p0_1) -(dni cpaveu3_b_P0_P1 "cpaveu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaveu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x18) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaveu3_b" pc crqp crpp)) ) - () - ) - -; 00011001 10100 qqqqq ppppp ooooo cpave3.b =crop,crqp,crpp (p0_1) -(dni cpave3_b_P0_P1 "cpave3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpave3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x19) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpave3_b" pc crqp crpp)) ) - () - ) - -; 00011010 10100 qqqqq ppppp ooooo cpave3.h =crop,crqp,crpp (p0_1) -(dni cpave3_h_P0_P1 "cpave3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpave3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpave3_h" pc crqp crpp)) ) - () - ) - -; 00011011 10100 qqqqq ppppp ooooo cpave3.w =crop,crqp,crpp (p0_1) -(dni cpave3_w_P0_P1 "cpave3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpave3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpave3_w" pc crqp crpp)) ) - () - ) - -; 00011100 10100 qqqqq ppppp ooooo cpaddsru3.b =crop,crqp,crpp (p0_1) -(dni cpaddsru3_b_P0_P1 "cpaddsru3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsru3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsru3_b" pc crqp crpp)) ) - () - ) - -; 00011101 10100 qqqqq ppppp ooooo cpaddsr3.b =crop,crqp,crpp (p0_1) -(dni cpaddsr3_b_P0_P1 "cpaddsr3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpaddsr3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsr3_b" pc crqp crpp)) ) - () - ) - -; 00011110 10100 qqqqq ppppp ooooo cpaddsr3.h =crop,crqp,crpp (p0_1) -(dni cpaddsr3_h_P0_P1 "cpaddsr3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpaddsr3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsr3_h" pc crqp crpp)) ) - () - ) - -; 00011111 10100 qqqqq ppppp ooooo cpaddsr3.w =crop,crqp,crpp (p0_1) -(dni cpaddsr3_w_P0_P1 "cpaddsr3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpaddsr3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x1f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpaddsr3_w" pc crqp crpp)) ) - () - ) - -; 00100000 10100 qqqqq ppppp ooooo cpabsu3.b =crop,crqp,crpp (p0_1) -(dni cpabsu3_b_P0_P1 "cpabsu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabsu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x20) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabsu3_b" pc crqp crpp)) ) - () - ) - -; 00100001 10100 qqqqq ppppp ooooo cpabs3.b =crop,crqp,crpp (p0_1) -(dni cpabs3_b_P0_P1 "cpabs3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpabs3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x21) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabs3_b" pc crqp crpp)) ) - () - ) - -; 00100010 10100 qqqqq ppppp ooooo cpabs3.h =crop,crqp,crpp (p0_1) -(dni cpabs3_h_P0_P1 "cpabs3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpabs3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x22) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpabs3_h" pc crqp crpp)) ) - () - ) - -; 00100100 10100 qqqqq ppppp ooooo cpand3 =crop,crqp,crpp (p0_1) -(dni cpand3_P0_P1 "cpand3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST)) - "cpand3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x24) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpand3" pc crqp crpp)) ) - () - ) - -; 00100101 10100 qqqqq ppppp ooooo cpor3 =crop,crqp,crpp (p0_1) -(dni cpor3_P0_P1 "cpor3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST)) - "cpor3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x25) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpor3" pc crqp crpp)) ) - () - ) - -; 00100110 10100 qqqqq ppppp ooooo cpnor3 =crop,crqp,crpp (p0_1) -(dni cpnor3_P0_P1 "cpnor3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST)) - "cpnor3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x26) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpnor3" pc crqp crpp)) ) - () - ) - -; 00100111 10100 qqqqq ppppp ooooo cpxor3 =crop,crqp,crpp (p0_1) -(dni cpxor3_P0_P1 "cpxor3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST)) - "cpxor3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x27) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpxor3" pc crqp crpp)) ) - () - ) - -; 00101100 10100 qqqqq ppppp ooooo cppacku.b =crop,crqp,crpp (p0_1) -(dni cppacku_b_P0_P1 "cppacku.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST)) - "cppacku.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x2c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacku_b" pc crqp crpp)) ) - () - ) - -; 00101101 10100 qqqqq ppppp ooooo cppack.b =crop,crqp,crpp (p0_1) -(dni cppack_b_P0_P1 "cppack.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST)) - "cppack.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x2d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppack_b" pc crqp crpp)) ) - () - ) - -; 00101111 10100 qqqqq ppppp ooooo cppack.h =crop,crqp,crpp (p0_1) -(dni cppack_h_P0_P1 "cppack.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST)) - "cppack.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x2f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppack_h" pc crqp crpp)) ) - () - ) - -; 00110000 10100 qqqqq ppppp ooooo cpmaxu3.b =crop,crqp,crpp (p0_1) -(dni cpmaxu3_b_P0_P1 "cpmaxu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmaxu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x30) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmaxu3_b" pc crqp crpp)) ) - () - ) - -; 00110001 10100 qqqqq ppppp ooooo cpmax3.b =crop,crqp,crpp (p0_1) -(dni cpmax3_b_P0_P1 "cpmax3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmax3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x31) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmax3_b" pc crqp crpp)) ) - () - ) - -; 00110011 10100 qqqqq ppppp ooooo cpmax3.h =crop,crqp,crpp (p0_1) -(dni cpmax3_h_P0_P1 "cpmax3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmax3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x33) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmax3_h" pc crqp crpp)) ) - () - ) - -; 00110100 10100 qqqqq ppppp ooooo cpmaxu3.w =crop,crqp,crpp (p0_1) -(dni cpmaxu3_w_P0_P1 "cpmaxu3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmaxu3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x34) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmaxu3_w" pc crqp crpp)) ) - () - ) - -; 00110101 10100 qqqqq ppppp ooooo cpmax3.w =crop,crqp,crpp (p0_1) -(dni cpmax3_w_P0_P1 "cpmax3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmax3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x35) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmax3_w" pc crqp crpp)) ) - () - ) - -; 00111000 10100 qqqqq ppppp ooooo cpminu3.b =crop,crqp,crpp (p0_1) -(dni cpminu3_b_P0_P1 "cpminu3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpminu3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x38) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpminu3_b" pc crqp crpp)) ) - () - ) - -; 00111001 10100 qqqqq ppppp ooooo cpmin3.b =crop,crqp,crpp (p0_1) -(dni cpmin3_b_P0_P1 "cpmin3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmin3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x39) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmin3_b" pc crqp crpp)) ) - () - ) - -; 00111011 10100 qqqqq ppppp ooooo cpmin3.h =crop,crqp,crpp (p0_1) -(dni cpmin3_h_P0_P1 "cpmin3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmin3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmin3_h" pc crqp crpp)) ) - () - ) - -; 00111100 10100 qqqqq ppppp ooooo cpminu3.w =crop,crqp,crpp (p0_1) -(dni cpminu3_w_P0_P1 "cpminu3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpminu3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpminu3_w" pc crqp crpp)) ) - () - ) - -; 00111101 10100 qqqqq ppppp ooooo cpmin3.w =crop,crqp,crpp (p0_1) -(dni cpmin3_w_P0_P1 "cpmin3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmin3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x3d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmin3_w" pc crqp crpp)) ) - () - ) - -; 01000000 10100 qqqqq ppppp ooooo cpsrl3.b =crop,crqp,crpp (p0_1) -(dni cpsrl3_b_P0_P1 "cpsrl3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrl3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x40) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrl3_b" pc crqp crpp)) ) - () - ) - -; 01000001 10100 qqqqq ppppp ooooo cpssrl3.b =crop,crqp,crpp (p0_1) -(dni cpssrl3_b_P0_P1 "cpssrl3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssrl3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x41) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssrl3_b" pc crqp crpp)) ) - () - ) - -; 01000010 10100 qqqqq ppppp ooooo cpsrl3.h =crop,crqp,crpp (p0_1) -(dni cpsrl3_h_P0_P1 "cpsrl3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrl3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x42) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrl3_h" pc crqp crpp)) ) - () - ) - -; 01000011 10100 qqqqq ppppp ooooo cpssrl3.h =crop,crqp,crpp (p0_1) -(dni cpssrl3_h_P0_P1 "cpssrl3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssrl3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x43) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssrl3_h" pc crqp crpp)) ) - () - ) - -; 01000100 10100 qqqqq ppppp ooooo cpsrl3.w =crop,crqp,crpp (p0_1) -(dni cpsrl3_w_P0_P1 "cpsrl3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrl3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x44) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrl3_w" pc crqp crpp)) ) - () - ) - -; 01000101 10100 qqqqq ppppp ooooo cpssrl3.w =crop,crqp,crpp (p0_1) -(dni cpssrl3_w_P0_P1 "cpssrl3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssrl3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x45) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssrl3_w" pc crqp crpp)) ) - () - ) - -; 01000110 10100 qqqqq ppppp ooooo cdsrl3 =crop,crqp,crpp (p0_1) -(dni cdsrl3_P0_P1 "cdsrl3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrl3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x46) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsrl3" pc crqp crpp)) ) - () - ) - -; 01001000 10100 qqqqq ppppp ooooo cpsra3.b =crop,crqp,crpp (p0_1) -(dni cpsra3_b_P0_P1 "cpsra3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsra3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x48) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsra3_b" pc crqp crpp)) ) - () - ) - -; 01001001 10100 qqqqq ppppp ooooo cpssra3.b =crop,crqp,crpp (p0_1) -(dni cpssra3_b_P0_P1 "cpssra3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssra3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x49) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssra3_b" pc crqp crpp)) ) - () - ) - -; 01001010 10100 qqqqq ppppp ooooo cpsra3.h =crop,crqp,crpp (p0_1) -(dni cpsra3_h_P0_P1 "cpsra3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsra3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsra3_h" pc crqp crpp)) ) - () - ) - -; 01001011 10100 qqqqq ppppp ooooo cpssra3.h =crop,crqp,crpp (p0_1) -(dni cpssra3_h_P0_P1 "cpssra3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssra3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssra3_h" pc crqp crpp)) ) - () - ) - -; 01001100 10100 qqqqq ppppp ooooo cpsra3.w =crop,crqp,crpp (p0_1) -(dni cpsra3_w_P0_P1 "cpsra3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsra3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsra3_w" pc crqp crpp)) ) - () - ) - -; 01001101 10100 qqqqq ppppp ooooo cpssra3.w =crop,crqp,crpp (p0_1) -(dni cpssra3_w_P0_P1 "cpssra3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssra3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssra3_w" pc crqp crpp)) ) - () - ) - -; 01001110 10100 qqqqq ppppp ooooo cdsra3 =crop,crqp,crpp (p0_1) -(dni cdsra3_P0_P1 "cdsra3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsra3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x4e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsra3" pc crqp crpp)) ) - () - ) - -; 01010000 10100 qqqqq ppppp ooooo cpsll3.b =crop,crqp,crpp (p0_1) -(dni cpsll3_b_P0_P1 "cpsll3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsll3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x50) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsll3_b" pc crqp crpp)) ) - () - ) - -; 01010001 10100 qqqqq ppppp ooooo cpssll3.b =crop,crqp,crpp (p0_1) -(dni cpssll3_b_P0_P1 "cpssll3.b $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpssll3.b $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x51) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssll3_b" pc crqp crpp)) ) - () - ) - -; 01010010 10100 qqqqq ppppp ooooo cpsll3.h =crop,crqp,crpp (p0_1) -(dni cpsll3_h_P0_P1 "cpsll3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsll3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x52) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsll3_h" pc crqp crpp)) ) - () - ) - -; 01010011 10100 qqqqq ppppp ooooo cpssll3.h =crop,crqp,crpp (p0_1) -(dni cpssll3_h_P0_P1 "cpssll3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpssll3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x53) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssll3_h" pc crqp crpp)) ) - () - ) - -; 01010100 10100 qqqqq ppppp ooooo cpsll3.w =crop,crqp,crpp (p0_1) -(dni cpsll3_w_P0_P1 "cpsll3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsll3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x54) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsll3_w" pc crqp crpp)) ) - () - ) - -; 01010101 10100 qqqqq ppppp ooooo cpssll3.w =crop,crqp,crpp (p0_1) -(dni cpssll3_w_P0_P1 "cpssll3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpssll3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x55) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpssll3_w" pc crqp crpp)) ) - () - ) - -; 01010110 10100 qqqqq ppppp ooooo cdsll3 =crop,crqp,crpp (p0_1) -(dni cdsll3_P0_P1 "cdsll3 $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsll3 $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x56) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsll3" pc crqp crpp)) ) - () - ) - -; 01011010 10100 qqqqq ppppp ooooo cpsla3.h =crop,crqp,crpp (p0_1) -(dni cpsla3_h_P0_P1 "cpsla3.h $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpsla3.h $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x5a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsla3_h" pc crqp crpp)) ) - () - ) - -; 01011100 10100 qqqqq ppppp ooooo cpsla3.w =crop,crqp,crpp (p0_1) -(dni cpsla3_w_P0_P1 "cpsla3.w $crop,$crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpsla3.w $crop,$crqp,$crpp" - (+ (f-ivc2-8u0 #x5c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsla3_w" pc crqp crpp)) ) - () - ) - -; xxxxxiii 10101 qqqqq 00000 ooooo cpsrli3.b =crop,crqp,imm3p5 (p0_1) -(dni cpsrli3_b_P0_P1 "cpsrli3.b $crop,$crqp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrli3.b $crop,$crqp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrli3_b" pc crqp imm3p5)) ) - () - ) - -; xxxxiiii 10101 qqqqq 00001 ooooo cpsrli3.h =crop,crqp,imm4p4 (p0_1) -(dni cpsrli3_h_P0_P1 "cpsrli3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrli3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrli3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 00010 ooooo cpsrli3.w =crop,crqp,imm5p3 (p0_1) -(dni cpsrli3_w_P0_P1 "cpsrli3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrli3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrli3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 00011 ooooo cdsrli3 =crop,crqp,imm6p2 (p0_1) -(dni cdsrli3_P0_P1 "cdsrli3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrli3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsrli3" pc crqp imm6p2)) ) - () - ) - -; xxxxxiii 10101 qqqqq 00100 ooooo cpsrai3.b =crop,crqp,imm3p5 (p0_1) -(dni cpsrai3_b_P0_P1 "cpsrai3.b $crop,$crqp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpsrai3.b $crop,$crqp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrai3_b" pc crqp imm3p5)) ) - () - ) - -; xxxxiiii 10101 qqqqq 00101 ooooo cpsrai3.h =crop,crqp,imm4p4 (p0_1) -(dni cpsrai3_h_P0_P1 "cpsrai3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpsrai3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrai3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 00110 ooooo cpsrai3.w =crop,crqp,imm5p3 (p0_1) -(dni cpsrai3_w_P0_P1 "cpsrai3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpsrai3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpsrai3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 00111 ooooo cdsrai3 =crop,crqp,imm6p2 (p0_1) -(dni cdsrai3_P0_P1 "cdsrai3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdsrai3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdsrai3" pc crqp imm6p2)) ) - () - ) - -; xxxxxiii 10101 qqqqq 01000 ooooo cpslli3.b =crop,crqp,imm3p5 (p0_1) -(dni cpslli3_b_P0_P1 "cpslli3.b $crop,$crqp,imm3p5 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST)) - "cpslli3.b $crop,$crqp,$imm3p5" - (+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslli3_b" pc crqp imm3p5)) ) - () - ) - -; xxxxiiii 10101 qqqqq 01001 ooooo cpslli3.h =crop,crqp,imm4p4 (p0_1) -(dni cpslli3_h_P0_P1 "cpslli3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST)) - "cpslli3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslli3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 01010 ooooo cpslli3.w =crop,crqp,imm5p3 (p0_1) -(dni cpslli3_w_P0_P1 "cpslli3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpslli3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslli3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 01011 ooooo cdslli3 =crop,crqp,imm6p2 (p0_1) -(dni cdslli3_P0_P1 "cdslli3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdslli3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdslli3" pc crqp imm6p2)) ) - () - ) - -; xxxxiiii 10101 qqqqq 01101 ooooo cpslai3.h =crop,crqp,imm4p4 (p0_1) -(dni cpslai3_h_P0_P1 "cpslai3.h $crop,$crqp,imm4p4 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpslai3.h $crop,$crqp,$imm4p4" - (+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslai3_h" pc crqp imm4p4)) ) - () - ) - -; xxxiiiii 10101 qqqqq 01110 ooooo cpslai3.w =crop,crqp,imm5p3 (p0_1) -(dni cpslai3_w_P0_P1 "cpslai3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpslai3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpslai3_w" pc crqp imm5p3)) ) - () - ) - -; xxxiiiii 10101 qqqqq 10000 ooooo cpclipiu3.w =crop,crqp,imm5p3 (p0_1) -(dni cpclipiu3_w_P0_P1 "cpclipiu3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipiu3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpclipiu3_w" pc crqp imm5p3)) ) - () - ) - -; xxxiiiii 10101 qqqqq 10001 ooooo cpclipi3.w =crop,crqp,imm5p3 (p0_1) -(dni cpclipi3_w_P0_P1 "cpclipi3.w $crop,$crqp,imm5p3 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST)) - "cpclipi3.w $crop,$crqp,$imm5p3" - (+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpclipi3_w" pc crqp imm5p3)) ) - () - ) - -; xxiiiiii 10101 qqqqq 10010 ooooo cdclipiu3 =crop,crqp,imm6p2 (p0_1) -(dni cdclipiu3_P0_P1 "cdclipiu3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipiu3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdclipiu3" pc crqp imm6p2)) ) - () - ) - -; xxiiiiii 10101 qqqqq 10011 ooooo cdclipi3 =crop,crqp,imm6p2 (p0_1) -(dni cdclipi3_P0_P1 "cdclipi3 $crop,$crqp,imm6p2 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdclipi3 $crop,$crqp,$imm6p2" - (+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cdclipi3" pc crqp imm6p2)) ) - () - ) - -; iiiiiiii 10110 qqqqq 01iii iiiii cpmovi.h =crqp,simm16p0 (p0_i) -(dni cpmovi_h_P0_P1 "cpmovi.h $crqp,simm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST)) - "cpmovi.h $crqp,$simm16p0" - (+ (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmovi_h16" pc simm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 00iii iiiii cpmoviu.w =crqp,imm16p0 (p0_i) -(dni cpmoviu_w_P0_P1 "cpmoviu.w $crqp,imm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST)) - "cpmoviu.w $crqp,$imm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x0) imm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmoviu_w16" pc imm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 01iii iiiii cpmovi.w =crqp,simm16p0 (p0_i) -(dni cpmovi_w_P0_P1 "cpmovi.w $crqp,simm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST)) - "cpmovi.w $crqp,$simm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmovi_w16" pc simm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 10iii iiiii cdmoviu =crqp,imm16p0 (p0_i) -(dni cdmoviu_P0_P1 "cdmoviu $crqp,imm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmoviu $crqp,$imm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x2) imm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cdmoviu16" pc imm16p0)) ) - () - ) - -; iiiiiiii 10111 qqqqq 11iii iiiii cdmovi =crqp,simm16p0 (p0_i) -(dni cdmovi_P0_P1 "cdmovi $crqp,simm16p0 Pn" - (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST)) - "cdmovi $crqp,$simm16p0" - (+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x3) simm16p0(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cdmovi16" pc simm16p0)) ) - () - ) - -; 00000000 00000 00000 00000 00000 c1nop (p0_1) -(dni c1nop_P1 "c1nop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "c1nop")) - "c1nop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x0) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (c-call "ivc2_c1nop" pc) ) - () - ) - -; 00000000 10110 qqqqq 00iii iiiii cpmovi.b =crqp,simm8p20 (p0_i) -(dni cpmovi_b_P0S_P1 "cpmovi.b $crqp,simm8p20 Pn" - (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST)) - "cpmovi.b $crqp,$simm8p20" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x0) imm8p20(f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crqp (c-call DI "ivc2_cpmovi_b" pc simm8p20)) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00000 cpadda1u.b crqp,crpp (p0_1) -(dni cpadda1u_b_P1 "cpadda1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpadda1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00001 cpadda1.b crqp,crpp (p0_1) -(dni cpadda1_b_P1 "cpadda1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b") (CPTYPE V8QI) VOLATILE) - "cpadda1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpadda1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00010 cpaddua1.h crqp,crpp (p0_1) -(dni cpaddua1_h_P1 "cpaddua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpaddua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00011 cpaddla1.h crqp,crpp (p0_1) -(dni cpaddla1_h_P1 "cpaddla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpaddla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00100 cpaddaca1u.b crqp,crpp (p0_1) -(dni cpaddaca1u_b_P1 "cpaddaca1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpaddaca1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00101 cpaddaca1.b crqp,crpp (p0_1) -(dni cpaddaca1_b_P1 "cpaddaca1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI) VOLATILE) - "cpaddaca1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddaca1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00110 cpaddacua1.h crqp,crpp (p0_1) -(dni cpaddacua1_h_P1 "cpaddacua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 00111 cpaddacla1.h crqp,crpp (p0_1) -(dni cpaddacla1_h_P1 "cpaddacla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI) VOLATILE) - "cpaddacla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpaddacla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01000 cpsuba1u.b crqp,crpp (p0_1) -(dni cpsuba1u_b_P1 "cpsuba1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsuba1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01001 cpsuba1.b crqp,crpp (p0_1) -(dni cpsuba1_b_P1 "cpsuba1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI) VOLATILE) - "cpsuba1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsuba1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01010 cpsubua1.h crqp,crpp (p0_1) -(dni cpsubua1_h_P1 "cpsubua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsubua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01011 cpsubla1.h crqp,crpp (p0_1) -(dni cpsubla1_h_P1 "cpsubla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsubla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01100 cpsubaca1u.b crqp,crpp (p0_1) -(dni cpsubaca1u_b_P1 "cpsubaca1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsubaca1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01101 cpsubaca1.b crqp,crpp (p0_1) -(dni cpsubaca1_b_P1 "cpsubaca1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI) VOLATILE) - "cpsubaca1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubaca1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01110 cpsubacua1.h crqp,crpp (p0_1) -(dni cpsubacua1_h_P1 "cpsubacua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 01111 cpsubacla1.h crqp,crpp (p0_1) -(dni cpsubacla1_h_P1 "cpsubacla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI) VOLATILE) - "cpsubacla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsubacla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10000 cpabsa1u.b crqp,crpp (p0_1) -(dni cpabsa1u_b_P1 "cpabsa1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpabsa1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10001 cpabsa1.b crqp,crpp (p0_1) -(dni cpabsa1_b_P1 "cpabsa1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI) VOLATILE) - "cpabsa1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsa1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10010 cpabsua1.h crqp,crpp (p0_1) -(dni cpabsua1_h_P1 "cpabsua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI) VOLATILE) - "cpabsua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpabsua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10011 cpabsla1.h crqp,crpp (p0_1) -(dni cpabsla1_h_P1 "cpabsla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI) VOLATILE) - "cpabsla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpabsla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10100 cpsada1u.b crqp,crpp (p0_1) -(dni cpsada1u_b_P1 "cpsada1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpsada1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10101 cpsada1.b crqp,crpp (p0_1) -(dni cpsada1_b_P1 "cpsada1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b") (CPTYPE V8QI) VOLATILE) - "cpsada1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsada1_b" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10110 cpsadua1.h crqp,crpp (p0_1) -(dni cpsadua1_h_P1 "cpsadua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsadua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 10111 cpsadla1.h crqp,crpp (p0_1) -(dni cpsadla1_h_P1 "cpsadla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsadla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsadla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 11011 cpseta1.h crqp,crpp (p0_1) -(dni cpseta1_h_P1 "cpseta1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h") (CPTYPE V4HI) VOLATILE) - "cpseta1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpseta1_h" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 11100 cpsetua1.w crqp,crpp (p0_1) -(dni cpsetua1_w_P1 "cpsetua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI) VOLATILE) - "cpsetua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsetua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11000 qqqqq ppppp 11101 cpsetla1.w crqp,crpp (p0_1) -(dni cpsetla1_w_P1 "cpsetla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI) VOLATILE) - "cpsetla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpsetla1_w" pc crqp crpp) ) - () - ) - -; 00000000 11001 00000 00001 ooooo cpmova1.b =crop (p0_1) -(dni cpmova1_b_P1 "cpmova1.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cpmova1.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmova1_b" pc)) ) - () - ) - -; 00000000 11001 00000 00010 ooooo cpmovua1.h =crop (p0_1) -(dni cpmovua1_h_P1 "cpmovua1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovua1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovua1_h" pc)) ) - () - ) - -; 00000000 11001 00000 00011 ooooo cpmovla1.h =crop (p0_1) -(dni cpmovla1_h_P1 "cpmovla1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cpmovla1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovla1_h" pc)) ) - () - ) - -; 00000000 11001 00000 00100 ooooo cpmovuua1.w =crop (p0_1) -(dni cpmovuua1_w_P1 "cpmovuua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovuua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovuua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 00101 ooooo cpmovula1.w =crop (p0_1) -(dni cpmovula1_w_P1 "cpmovula1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovula1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovula1_w" pc)) ) - () - ) - -; 00000000 11001 00000 00110 ooooo cpmovlua1.w =crop (p0_1) -(dni cpmovlua1_w_P1 "cpmovlua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 00111 ooooo cpmovlla1.w =crop (p0_1) -(dni cpmovlla1_w_P1 "cpmovlla1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovlla1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovlla1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01000 ooooo cppacka1u.b =crop (p0_1) -(dni cppacka1u_b_P1 "cppacka1u.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST) VOLATILE) - "cppacka1u.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka1u_b" pc)) ) - () - ) - -; 00000000 11001 00000 01001 ooooo cppacka1.b =crop (p0_1) -(dni cppacka1_b_P1 "cppacka1.b $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST) VOLATILE) - "cppacka1.b $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppacka1_b" pc)) ) - () - ) - -; 00000000 11001 00000 01010 ooooo cppackua1.h =crop (p0_1) -(dni cppackua1_h_P1 "cppackua1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackua1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua1_h" pc)) ) - () - ) - -; 00000000 11001 00000 01011 ooooo cppackla1.h =crop (p0_1) -(dni cppackla1_h_P1 "cppackla1.h $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST) VOLATILE) - "cppackla1.h $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla1_h" pc)) ) - () - ) - -; 00000000 11001 00000 01100 ooooo cppackua1.w =crop (p0_1) -(dni cppackua1_w_P1 "cppackua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01101 ooooo cppackla1.w =crop (p0_1) -(dni cppackla1_w_P1 "cppackla1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cppackla1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cppackla1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01110 ooooo cpmovhua1.w =crop (p0_1) -(dni cpmovhua1_w_P1 "cpmovhua1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhua1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhua1_w" pc)) ) - () - ) - -; 00000000 11001 00000 01111 ooooo cpmovhla1.w =crop (p0_1) -(dni cpmovhla1_w_P1 "cpmovhla1.w $crop Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST) VOLATILE) - "cpmovhla1.w $crop" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set crop (c-call DI "ivc2_cpmovhla1_w" pc)) ) - () - ) - -; 00000000 11001 00000 10000 00000 cpacsuma1 (p0_1) -(dni cpacsuma1_P1 "cpacsuma1 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacsuma1") VOLATILE) - "cpacsuma1" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpacsuma1" pc) ) - () - ) - -; 00000000 11001 00000 10001 00000 cpaccpa1 (p0_1) -(dni cpaccpa1_P1 "cpaccpa1 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaccpa1") VOLATILE) - "cpaccpa1" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpaccpa1" pc) ) - () - ) - -; 00000000 11001 00000 10010 00000 cpacswp (p0_1) -(dni cpacswp_P1 "cpacswp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacswp") VOLATILE) - "cpacswp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x12) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc0_0 0) - (set ivc2_acc0_1 0) - (set ivc2_acc0_2 0) - (set ivc2_acc0_3 0) - (set ivc2_acc0_4 0) - (set ivc2_acc0_5 0) - (set ivc2_acc0_6 0) - (set ivc2_acc0_7 0) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpacswp" pc) ) - () - ) - -; 00000000 11001 qqqqq 11000 00000 cpsrla1 crqp (p0_1) -(dni cpsrla1_P1 "cpsrla1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrla1") VOLATILE) - "cpsrla1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrla1" pc crqp) ) - () - ) - -; 00000000 11001 qqqqq 11001 00000 cpsraa1 crqp (p0_1) -(dni cpsraa1_P1 "cpsraa1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraa1") VOLATILE) - "cpsraa1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraa1" pc crqp) ) - () - ) - -; 00000000 11001 qqqqq 11010 00000 cpslla1 crqp (p0_1) -(dni cpslla1_P1 "cpslla1 $crqp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpslla1") VOLATILE) - "cpslla1 $crqp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpslla1" pc crqp) ) - () - ) - -; 00000000 11001 00000 11100 iiiii cpsrlia1 imm5p23 (p0_1) -(dni cpsrlia1_1_p1 "cpsrlia1 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsrlia1") VOLATILE) - "cpsrlia1 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsrlia1" pc imm5p23) ) - () - ) - -; 00000000 11001 00000 11101 iiiii cpsraia1 imm5p23 (p0_1) -(dni cpsraia1_1_p1 "cpsraia1 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsraia1") VOLATILE) - "cpsraia1 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsraia1" pc imm5p23) ) - () - ) - -; 00000000 11001 00000 11110 iiiii cpsllia1 imm5p23 (p0_1) -(dni cpsllia1_1_p1 "cpsllia1 imm5p23 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsllia1") VOLATILE) - "cpsllia1 $imm5p23" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpsllia1" pc imm5p23) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00000 cpfmulia1s0u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s0u_b_P1 "cpfmulia1s0u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmulia1s0u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s0u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00001 cpfmulia1s0.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s0_b_P1 "cpfmulia1s0.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b") (CPTYPE V8QI) VOLATILE) - "cpfmulia1s0.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s0_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00010 cpfmuliua1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmuliua1s0_h_P1 "cpfmuliua1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmuliua1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmuliua1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00011 cpfmulila1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmulila1s0_h_P1 "cpfmulila1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmulila1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpfmulila1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00100 cpfmadia1s0u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s0u_b_P1 "cpfmadia1s0u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmadia1s0u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s0u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00101 cpfmadia1s0.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s0_b_P1 "cpfmadia1s0.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b") (CPTYPE V8QI) VOLATILE) - "cpfmadia1s0.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s0_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00110 cpfmadiua1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadiua1s0_h_P1 "cpfmadiua1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmadiua1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadiua1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 00111 cpfmadila1s0.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadila1s0_h_P1 "cpfmadila1s0.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h") (CPTYPE V4HI) VOLATILE) - "cpfmadila1s0.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadila1s0_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01000 cpfmulia1s1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s1u_b_P1 "cpfmulia1s1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmulia1s1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01001 cpfmulia1s1.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmulia1s1_b_P1 "cpfmulia1s1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b") (CPTYPE V8QI) VOLATILE) - "cpfmulia1s1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1s1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01010 cpfmuliua1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmuliua1s1_h_P1 "cpfmuliua1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmuliua1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmuliua1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01011 cpfmulila1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmulila1s1_h_P1 "cpfmulila1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmulila1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpfmulila1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01100 cpfmadia1s1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s1u_b_P1 "cpfmadia1s1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmadia1s1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01101 cpfmadia1s1.b crqp,crpp,simm8p0 (p0_1) -(dni cpfmadia1s1_b_P1 "cpfmadia1s1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b") (CPTYPE V8QI) VOLATILE) - "cpfmadia1s1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1s1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01110 cpfmadiua1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadiua1s1_h_P1 "cpfmadiua1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadiua1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadiua1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 01111 cpfmadila1s1.h crqp,crpp,simm8p0 (p0_1) -(dni cpfmadila1s1_h_P1 "cpfmadila1s1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadila1s1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadila1s1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10000 cpamulia1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpamulia1u_b_P1 "cpamulia1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpamulia1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpamulia1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10001 cpamulia1.b crqp,crpp,simm8p0 (p0_1) -(dni cpamulia1_b_P1 "cpamulia1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b") (CPTYPE V8QI) VOLATILE) - "cpamulia1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpamulia1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10010 cpamuliua1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamuliua1_h_P1 "cpamuliua1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h") (CPTYPE V4HI) VOLATILE) - "cpamuliua1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpamuliua1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10011 cpamulila1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamulila1_h_P1 "cpamulila1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h") (CPTYPE V4HI) VOLATILE) - "cpamulila1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpamulila1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10100 cpamadia1u.b crqp,crpp,simm8p0 (p0_1) -(dni cpamadia1u_b_P1 "cpamadia1u.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpamadia1u.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadia1u_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10101 cpamadia1.b crqp,crpp,simm8p0 (p0_1) -(dni cpamadia1_b_P1 "cpamadia1.b $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b") (CPTYPE V8QI) VOLATILE) - "cpamadia1.b $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadia1_b" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10110 cpamadiua1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamadiua1_h_P1 "cpamadiua1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h") (CPTYPE V4HI) VOLATILE) - "cpamadiua1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadiua1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11111 qqqqq ppppp 10111 cpamadila1.h crqp,crpp,simm8p0 (p0_1) -(dni cpamadila1_h_P1 "cpamadila1.h $crqp,$crpp,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h") (CPTYPE V4HI) VOLATILE) - "cpamadila1.h $crqp,$crpp,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpamadila1_h" pc crqp crpp simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 00 III cpfmulia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmulia1u_b_P1 "cpfmulia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1u_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 01 III cpfmulia1.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmulia1_b_P1 "cpfmulia1.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b") (CPTYPE V8QI) VOLATILE) - "cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmulia1_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 10 III cpfmuliua1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmuliua1_h_P1 "cpfmuliua1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h") (CPTYPE V4HI) VOLATILE) - "cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpfmuliua1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11100 qqqqq ppppp 11 III cpfmulila1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmulila1_h_P1 "cpfmulila1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h") (CPTYPE V4HI) VOLATILE) - "cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpfmulila1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 00 III cpfmadia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadia1u_b_P1 "cpfmadia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b") (CPTYPE V8UQI) VOLATILE) - "cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1u_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 01 III cpfmadia1.b crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadia1_b_P1 "cpfmadia1.b $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b") (CPTYPE V8QI) VOLATILE) - "cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadia1_b" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 10 III cpfmadiua1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadiua1_h_P1 "cpfmadiua1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadiua1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; iiiiiiii 11101 qqqqq ppppp 11 III cpfmadila1.h crqp,crpp,imm3p25,simm8p0 (cpfm) -(dni cpfmadila1_h_P1 "cpfmadila1.h $crqp,$crpp,imm3p25,simm8p0 Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h") (CPTYPE V4HI) VOLATILE) - "cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0" - (+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpfmadila1_h" pc crqp crpp imm3p25 simm8p0) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00000 cpssqa1u.b crqp,crpp (p0_1) -(dni cpssqa1u_b_P1 "cpssqa1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssqa1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00001 cpssqa1.b crqp,crpp (p0_1) -(dni cpssqa1_b_P1 "cpssqa1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI) VOLATILE) - "cpssqa1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssqa1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00100 cpssda1u.b crqp,crpp (p0_1) -(dni cpssda1u_b_P1 "cpssda1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI) VOLATILE) - "cpssda1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssda1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 00101 cpssda1.b crqp,crpp (p0_1) -(dni cpssda1_b_P1 "cpssda1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b") (CPTYPE V8QI) VOLATILE) - "cpssda1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpssda1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01000 cpmula1u.b crqp,crpp (p0_1) -(dni cpmula1u_b_P1 "cpmula1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmula1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01001 cpmula1.b crqp,crpp (p0_1) -(dni cpmula1_b_P1 "cpmula1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b") (CPTYPE V8QI) VOLATILE) - "cpmula1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmula1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01010 cpmulua1.h crqp,crpp (p0_1) -(dni cpmulua1_h_P1 "cpmulua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01011 cpmulla1.h crqp,crpp (p0_1) -(dni cpmulla1_h_P1 "cpmulla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01100 cpmulua1u.w crqp,crpp (p0_1) -(dni cpmulua1u_w_P1 "cpmulua1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulua1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01101 cpmulla1u.w crqp,crpp (p0_1) -(dni cpmulla1u_w_P1 "cpmulla1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmulla1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01110 cpmulua1.w crqp,crpp (p0_1) -(dni cpmulua1_w_P1 "cpmulua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (c-call "ivc2_cpmulua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 01111 cpmulla1.w crqp,crpp (p0_1) -(dni cpmulla1_w_P1 "cpmulla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (c-call "ivc2_cpmulla1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10000 cpmada1u.b crqp,crpp (p0_1) -(dni cpmada1u_b_P1 "cpmada1u.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI) VOLATILE) - "cpmada1u.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1u_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10001 cpmada1.b crqp,crpp (p0_1) -(dni cpmada1_b_P1 "cpmada1.b $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b") (CPTYPE V8QI) VOLATILE) - "cpmada1.b $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmada1_b" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10010 cpmadua1.h crqp,crpp (p0_1) -(dni cpmadua1_h_P1 "cpmadua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpmadua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10011 cpmadla1.h crqp,crpp (p0_1) -(dni cpmadla1_h_P1 "cpmadla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpmadla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10100 cpmadua1u.w crqp,crpp (p0_1) -(dni cpmadua1u_w_P1 "cpmadua1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadua1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10101 cpmadla1u.w crqp,crpp (p0_1) -(dni cpmadla1u_w_P1 "cpmadla1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmadla1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10110 cpmadua1.w crqp,crpp (p0_1) -(dni cpmadua1_w_P1 "cpmadua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpmadua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 10111 cpmadla1.w crqp,crpp (p0_1) -(dni cpmadla1_w_P1 "cpmadla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpmadla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmadla1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11010 cpmsbua1.h crqp,crpp (p0_1) -(dni cpmsbua1_h_P1 "cpmsbua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11011 cpmsbla1.h crqp,crpp (p0_1) -(dni cpmsbla1_h_P1 "cpmsbla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpmsbla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_h" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11100 cpmsbua1u.w crqp,crpp (p0_1) -(dni cpmsbua1u_w_P1 "cpmsbua1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbua1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11101 cpmsbla1u.w crqp,crpp (p0_1) -(dni cpmsbla1u_w_P1 "cpmsbla1u.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI) VOLATILE) - "cpmsbla1u.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1u_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11110 cpmsbua1.w crqp,crpp (p0_1) -(dni cpmsbua1_w_P1 "cpmsbua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbua1_w" pc crqp crpp) ) - () - ) - -; 00000000 11110 qqqqq ppppp 11111 cpmsbla1.w crqp,crpp (p0_1) -(dni cpmsbla1_w_P1 "cpmsbla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpmsbla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmsbla1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10010 cpsmadua1.h crqp,crpp (p0_1) -(dni cpsmadua1_h_P1 "cpsmadua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10011 cpsmadla1.h crqp,crpp (p0_1) -(dni cpsmadla1_h_P1 "cpsmadla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10110 cpsmadua1.w crqp,crpp (p0_1) -(dni cpsmadua1_w_P1 "cpsmadua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadua1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 10111 cpsmadla1.w crqp,crpp (p0_1) -(dni cpsmadla1_w_P1 "cpsmadla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadla1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11010 cpsmsbua1.h crqp,crpp (p0_1) -(dni cpsmsbua1_h_P1 "cpsmsbua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11011 cpsmsbla1.h crqp,crpp (p0_1) -(dni cpsmsbla1_h_P1 "cpsmsbla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_h" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11110 cpsmsbua1.w crqp,crpp (p0_1) -(dni cpsmsbua1_w_P1 "cpsmsbua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbua1_w" pc crqp crpp) ) - () - ) - -; 00000001 11110 qqqqq ppppp 11111 cpsmsbla1.w crqp,crpp (p0_1) -(dni cpsmsbla1_w_P1 "cpsmsbla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbla1_w" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01010 cpmulslua1.h crqp,crpp (p0_1) -(dni cpmulslua1_h_P1 "cpmulslua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_h" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01011 cpmulslla1.h crqp,crpp (p0_1) -(dni cpmulslla1_h_P1 "cpmulslla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI) VOLATILE) - "cpmulslla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_h" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01110 cpmulslua1.w crqp,crpp (p0_1) -(dni cpmulslua1_w_P1 "cpmulslua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslua1_w" pc crqp crpp) ) - () - ) - -; 00000010 11110 qqqqq ppppp 01111 cpmulslla1.w crqp,crpp (p0_1) -(dni cpmulslla1_w_P1 "cpmulslla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI) VOLATILE) - "cpmulslla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpmulslla1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10010 cpsmadslua1.h crqp,crpp (p0_1) -(dni cpsmadslua1_h_P1 "cpsmadslua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10011 cpsmadslla1.h crqp,crpp (p0_1) -(dni cpsmadslla1_h_P1 "cpsmadslla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmadslla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10110 cpsmadslua1.w crqp,crpp (p0_1) -(dni cpsmadslua1_w_P1 "cpsmadslua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslua1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 10111 cpsmadslla1.w crqp,crpp (p0_1) -(dni cpsmadslla1_w_P1 "cpsmadslla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmadslla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmadslla1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11010 cpsmsbslua1.h crqp,crpp (p0_1) -(dni cpsmsbslua1_h_P1 "cpsmsbslua1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslua1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11011 cpsmsbslla1.h crqp,crpp (p0_1) -(dni cpsmsbslla1_h_P1 "cpsmsbslla1.h $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI) VOLATILE) - "cpsmsbslla1.h $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_h" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11110 cpsmsbslua1.w crqp,crpp (p0_1) -(dni cpsmsbslua1_w_P1 "cpsmsbslua1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslua1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_4 0) - (set ivc2_acc1_5 0) - (set ivc2_acc1_6 0) - (set ivc2_acc1_7 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslua1_w" pc crqp crpp) ) - () - ) - -; 00000011 11110 qqqqq ppppp 11111 cpsmsbslla1.w crqp,crpp (p0_1) -(dni cpsmsbslla1_w_P1 "cpsmsbslla1.w $crqp,$crpp Pn" - (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI) VOLATILE) - "cpsmsbslla1.w $crqp,$crpp" - (+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0)) - (sequence () - (c-call "check_option_cp" pc) - (set ivc2_acc1_0 0) - (set ivc2_acc1_1 0) - (set ivc2_acc1_2 0) - (set ivc2_acc1_3 0) - (set ivc2_cofa1 0) - (c-call "ivc2_cpsmsbslla1_w" pc crqp crpp) ) - () - ) - diff --git a/binutils-2.24/cpu/mep-rhcop.cpu b/binutils-2.24/cpu/mep-rhcop.cpu deleted file mode 100644 index 60edb854..00000000 --- a/binutils-2.24/cpu/mep-rhcop.cpu +++ /dev/null @@ -1,342 +0,0 @@ -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -;; This coprocessor definition is being used to verify vliw mode behaviour. -;; This is a mock-up done by Red Hat and is in no way supposed to represent -;; a real coprocessor. The hardware is defined in mep-core.cpu. - -; Coprocessor registers -(define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) - -(define-hardware - (name h-cr64-rh-1) - (comment "64-bit coprocessor registers for rh coprocessor for core 1") - (attrs VIRTUAL rh-isa-1) - (type register DI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index newval)) - (get (index) (c-call DI "h_cr64_get" index)) - (indices keyword "$c" (.map -reg-pair (.iota 32))) -) - -(define-hardware - (name h-cr-rh-1) - (comment "32-bit coprocessor registers for rh coprocessor for core 1") - (attrs VIRTUAL rh-isa-1) - (type register SI (32)) - (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) - (get (index) (trunc SI (c-call DI "h_cr64_get" index))) - (indices keyword "$c" (.map -reg-pair (.iota 32))) -) - -(define-hardware - (name h-ccr-rh-1) - (comment "Coprocessor control registers for rh coprocessor for core 1") - (attrs VIRTUAL rh-isa-1) - (type register SI (64)) - (set (index newval) (c-call VOID "h_ccr_set" index newval)) - (get (index) (c-call DI "h_ccr_get" index)) - (indices keyword "" (.map -ccr-reg-pair (.iota 64))) -) - -; ifields For 16-bit insns -(dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4) -(dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5) -(dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5) -(dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2) -(dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3) -(dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4) - -; ifields For 32-bit insns (some of the above are used too) -; Notes: -; -; f-alone: A value of 0111 means that the insn can run alone in -; one of the vliw modes. -; -; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit -; f-seg32-a: insns to be defined. -(dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3) -(dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4) -(dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3) -(dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8) -(dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5) - -; ifields for 48-bit insns -; Note: Part of f-uu12 can be broken off later to enumerate -; any 48-bit insns that may be added. -(dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12) -(dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16) -(dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16) - -; ifields for 64-bit insns -(dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8) -(dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8) -(dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8) -(dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16) -(dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5) -(dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4) -(dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23) -(dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4) -(dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4) -(dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24) - - -; Operands for 16-bit insns -(dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn) -(dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm) -(dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm) - -; Additional operands for 32-bit insns -(dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8) - -; Operands for 48-bit insns -(dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a) -(dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b) - -; Additional operands for 64-bit insns -(dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c) -(dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64) -(dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64) -(dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64) -(dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64) -(dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23) -(dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24) - - - -; 16- and 32-bit nops can be defined as normal instructions without -; any problems. nops take no operands, so nops longer than 32 -; bits cannot be defined as normal insns since that would result in -; decodable bits beyond cgen's 32-bit boundary. As a result, we -; have to use macros and other real insns to create 48- and 64-bit nops. -; -; In addition, since the names of the nops that will be created as part -; of future insn sets are not known at this time, the assembler needs a -; fixed set of nop names that it can use for automatic nop insertion. -; The idea is that no matter what those insns are called, we don't want -; to have to change the C code in the assemblers vliw grouping validation -; and nop insertion routines. We therefore have to create macros for -; all nops to map the macro names which are known to the assembler to the -; names of the real nop insns. -; -; These emitted insns in these macros will need to be modified when -; new nops are defined in new coprocessor insn sets. - -; A real 16-bit nop insn exists -(dnmi cpnop16 "cpnop16" - ((ISA ext_cop1_16)) - "cpnop16" - (emit cp16nop) -) - -; A real 32-bit nop insn exists -(dnmi cpnop32 "cpnop32" - ((ISA ext_cop1_32)) - "cpnop32" - (emit cp32nop) -) - -; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop. -(dnmi cpnop48 "cpnop48" - ((ISA ext_cop1_48)) - "cpnop48" - (emit cpf1nop (code16a 0) (code16b 0)) -) - -; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop. -(dnmi cpnop64 "cpnop64" - ((ISA ext_cop1_64)) - "cpnop64" - (emit cpf3nop (code16b 0) (code16c 0)) -) - - -(define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16)) -(define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32)) -(define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48)) -(define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64)) - -; 16-Bit Insns -(dncp116i movcp16 "16-bit coprocessor move insn" - (VLIW64_NO_MATCHING_NOP) - "movcp16 $cpcrn,$cpcrm" - (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm) - (set cpcrn cpcrm) - () -) - -(dncp116i movcp16a "16-bit coprocessor move insn" - (VLIW64_NO_MATCHING_NOP) - "movcp16a $cpcrn,$cprm" - (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm) - (set cpcrn (zext DI cprm)) - () -) - -(dncp116i movcp16b "16-bit coprocessor move insn" - (VLIW64_NO_MATCHING_NOP) - "movcp16b $cprm,$cpcrn" - (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm) - (set cprm (subword SI cpcrn 1)) - () -) - -(dncp116i cp16nop "16-bit coprocessor nop" - (VLIW64_NO_MATCHING_NOP) - "cp16nop" - (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0)) - (unimp "cp16nop") - () -) - -; 32-Bit Insns -(dncp132i cp32nop "32-bit coprocessor nop" - (VLIW64_NO_MATCHING_NOP) - "cp32nop" - (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) - (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0)) - (unimp "cpnop32") - () -) - -(dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests " - (VLIW64_NO_MATCHING_NOP) - "cpf2 $code8" - (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) - (f-cpcrm-32 0) (f-seg32-a 1) code8) - (unimp "cpf2") - () -) - -; 48-Bit Insns -(dncp148i cpf1 "48-bit coprocessor helper insn" - () - "cpf1 $code16a,$code16b" - (+ (f-cphigh4 4) (f-uu12 0) code16a code16b) - (sequence ((HI result)) - (if (eq code16a 0) - (set pc (c-call USI "cop_exception" pc)) - ; Set branch condition flags to value of code16a[0:3] - ; Branch condition flags do not exist yet. - (nop) - ) - ) - () -) - -(dncp148i cpf1nop "48-bit coprocessor nop insn" - () - "cpf1nop $code16a,$code16b" - (+ (f-cphigh4 5) (f-uu12 0) code16a code16b) - (sequence ((HI result)) - (set result (add code16a code16b)) - ) - () -) - -; 64-Bit Insns -(dncp164i cpf3 "64-bit coprocessor helper insn" - () - "cpf3 $code16b,$code16c" - (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 0) code16b code16c) - (sequence ((HI result)) - (set result (add code16b code16c)) - ) - () -) - -(dncp164i cpf3nop "64-bit coprocessor helper insn" - () - "cpf3nop $code16b,$code16c" - (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 7) code16b code16c) - (sequence ((HI result)) - (set result (add code16b code16c)) - ) - () -) - -(dncp164i cmov64a "64-bit cmov" - () - "cmov64a $cpcrn64,$cpcrm64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 1) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrn64 (zext DI cpcrm64))) - () -) - -(dncp164i cmov64b "64-bit cmov" - () - "cmov64b $cpcrm64,$cpcrn64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 2) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrm64 (subword SI cpcrn64 1))) - () -) - -(dncp164i cmovh64a "64-bit cmovh" - () - "cmovh64a $cpcrn64,$cpcrm64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 3) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1))))) - () -) - -(dncp164i cmovh64b "64-bit cmovh" - () - "cmovh64b $cpcrm64,$cpcrn64,$cpcode23" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 4) cpcrn64 cpcrm64 cpcode23) - (sequence ((SI dummy)) - (set dummy cpcode23) - (set cpcrm64 (subword SI cpcrn64 0))) - () -) - -(dncp164i cmovc64a "64-bit cmovc" - () - "cmovc64a $cpccrn64,$cpccrm64,$cpcode24" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 5) cpccrn64 cpccrm64 cpcode24) - (sequence ((SI dummy)) - (set dummy cpcode24) - (set cpccrn64 cpccrm64)) - () -) - -(dncp164i cmovc64b "64-bit cmovc" - () - "cmovc64b $cpccrm64,$cpccrn64,$cpcode24" - (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) - (f-seg64 6) cpccrn64 cpccrm64 cpcode24) - (sequence ((SI dummy)) - (set dummy cpcode24) - (set cpccrm64 cpccrn64)) - () -) - diff --git a/binutils-2.24/cpu/mep-sample-ucidsp.cpu b/binutils-2.24/cpu/mep-sample-ucidsp.cpu deleted file mode 100644 index 52946ac1..00000000 --- a/binutils-2.24/cpu/mep-sample-ucidsp.cpu +++ /dev/null @@ -1,120 +0,0 @@ -; Toshiba MeP Media Engine architecture description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; This file provides sample definitions for the UCI and DSP -; instructions. It is incorporated into the overall description by -; including it from a top-level file that includes all of the required -; option files. - -; UCI option. - -(define-pmacro mep-ext1-isa () (ISA ext_core1)) - - -; uci instructions for ELFextension test - -; uci.elfext.1 $simm16 -; 1111_IIII_0000_0010 0001_iiii_iiii_iiii -; simm16 = I[4:7]||i[20:31] - -; uci.elfext.2 $uimm16 -; 1111_IIII_0000_0010 0010_iiii_iiii_iiii -; uimm16 = I[4:7]||i[20:31] - -; define simm16 -(df f-uci_elfext_1-hi "uci_elfext_1 simm16 hi 4s7" (mep-ext1-isa) 4 4 INT #f #f) -(df f-uci_elfext_1-lo "uci_elfext_1 simm16 lo 20s31" (mep-ext1-isa) 20 12 UINT #f #f) -(define-multi-ifield - (name f-uci_elfext_1) - (comment "16-bits uci_elfext_ signed constant") - (attrs mep-ext1-isa) - (mode INT) - (subfields f-uci_elfext_1-hi f-uci_elfext_1-lo) - (insert (sequence () - (set (ifield f-uci_elfext_1-hi) (srl (ifield f-uci_elfext_1) 12)) - (set (ifield f-uci_elfext_1-lo) (and (ifield f-uci_elfext_1) #xfff)))) - (extract (set (ifield f-uci_elfext_1) - (or (sll (ifield f-uci_elfext_1-hi) 12) - (ifield f-uci_elfext_1-lo)))) - ) -(dpop uci_elfext_1simm16 "signed imm (16 bits)" (mep-ext1-isa) h-sint f-uci_elfext_1 "signed16") - -; define uimm16 -(df f-uci_elfext_2-hi "uci_elfext_2 uimm16 hi 4u7" (mep-ext1-isa) 4 4 UINT #f #f) -(df f-uci_elfext_2-lo "uci_elfext_2 uimm16 lo 20u31" (mep-ext1-isa) 20 12 UINT #f #f) -(define-multi-ifield - (name f-uci_elfext_2) - (comment "16-bits uci_elfext_ unsigned constant") - (attrs mep-ext1-isa) - (mode UINT) - (subfields f-uci_elfext_2-hi f-uci_elfext_2-lo) - (insert (sequence () - (set (ifield f-uci_elfext_2-hi) (srl (ifield f-uci_elfext_2) 12)) - (set (ifield f-uci_elfext_2-lo) (and (ifield f-uci_elfext_2) #xfff)))) - (extract (set (ifield f-uci_elfext_2) - (or (sll (ifield f-uci_elfext_2-hi) 12) - (ifield f-uci_elfext_2-lo)))) - ) -(dpop uci_elfext_2uimm16 "unsigned imm (16 bits)" (mep-ext1-isa) h-uint f-uci_elfext_2 "unsigned16") - -; define sub-opcode -(df f-uci_elfext-sub "sub-opcode for uci_elfext instructions" (mep-ext1-isa) 16 4 UINT #f #f) - - -; define instruction -(dni uci.elfext.1 "uci_elfext instruction 1" (OPTIONAL_UCI_INSN VOLATILE mep-ext1-isa) - "uci.elfext.1 $uci_elfext_1simm16" - (+ MAJ_15 (f-rm 0) (f-sub4 2) (f-uci_elfext-sub 1) uci_elfext_1simm16) - (c-call "check_option_uci" pc) - () - ) - -; define instruction -(dni uci.elfext.2 "uci_elfext instruction 1" (OPTIONAL_UCI_INSN VOLATILE mep-ext1-isa) - "uci.elfext.2 $uci_elfext_2uimm16" - (+ MAJ_15 (f-rm 0) (f-sub4 2) (f-uci_elfext-sub 2) uci_elfext_2uimm16) - (c-call "check_option_uci" pc) - () - ) - - - -;; some general samples -; UCI option. - -(dni uci "user defined instruction" (OPTIONAL_UCI_INSN mep-ext1-isa) - "uci $rn,$rm,$code16" - (+ MAJ_15 rn rm (f-sub4 2) code16) - (sequence () - (c-call "check_option_uci" pc) - (unimp "uci")) - ()) - -; DSP option. - -(dni dsp "dsp instruction" (OPTIONAL_DSP_INSN mep-ext1-isa) - "dsp $rn,$rm,$code16" - (+ MAJ_15 rn rm (f-sub4 0) code16) - (sequence () - (c-call "check_option_dsp" pc) - (set pc (c-call USI "dsp_exception" pc))) - ()) diff --git a/binutils-2.24/cpu/mep.cpu b/binutils-2.24/cpu/mep.cpu deleted file mode 100644 index 0fb66da2..00000000 --- a/binutils-2.24/cpu/mep.cpu +++ /dev/null @@ -1,21 +0,0 @@ -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. -(include "mep-default.cpu") diff --git a/binutils-2.24/cpu/mep.opc b/binutils-2.24/cpu/mep.opc deleted file mode 100644 index 6b4e9ff8..00000000 --- a/binutils-2.24/cpu/mep.opc +++ /dev/null @@ -1,1669 +0,0 @@ -/* MeP opcode support. -*- C -*- - Copyright 2011 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* -- opc.h */ - -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 1 - -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, insn) 0 - -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -typedef struct -{ - char * name; - int config_enum; - unsigned cpu_flag; - int big_endian; - int vliw_bits; - CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; - CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; - CGEN_ATTR_VALUE_BITSET_TYPE core_isa; - unsigned int option_mask; -} mep_config_map_struct; - -extern mep_config_map_struct mep_config_map[]; -extern int mep_config_index; - -extern void init_mep_all_core_isas_mask (void); -extern void init_mep_all_cop_isas_mask (void); -extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); - -#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) -#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) -#define MEP_OMASK (mep_config_map[mep_config_index].option_mask) -#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) -#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) -#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) -#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) -#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) -#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) -#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) -#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) -#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) - -/* begin-cop-ip-supported-defines */ -#define MEP_IVC2_SUPPORTED 1 -/* end-cop-ip-supported-defines */ - -extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); - -/* A mask for all ISAs executed by the core. */ -#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask -extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; - -#define MEP_INSN_CORE_P(insn) ( \ - init_mep_all_core_isas_mask (), \ - mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ -) - -/* A mask for all ISAs executed by a VLIW coprocessor. */ -#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask -extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; - -#define MEP_INSN_COP_P(insn) ( \ - init_mep_all_cop_isas_mask (), \ - mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ -) - -extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); -extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *); - -/* -- asm.c */ - -#include "elf/mep.h" - -#define CGEN_VALIDATE_INSN_SUPPORTED -#define mep_cgen_insn_supported mep_cgen_insn_supported_asm - - const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); - const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); - const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); - const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); - const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); -static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); -static const char * parse_signed16_range (CGEN_CPU_DESC, const char **, int, long *) ATTRIBUTE_UNUSED; -static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); -static const char * parse_unsigned16_range (CGEN_CPU_DESC, const char **, int, unsigned long *) ATTRIBUTE_UNUSED; -static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); -static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); -static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); - -const char * -parse_csrn (CGEN_CPU_DESC cd, const char **strp, - CGEN_KEYWORD *keyword_table, long *field) -{ - const char *err; - unsigned long value; - - err = cgen_parse_keyword (cd, strp, keyword_table, field); - if (!err) - return NULL; - - err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); - if (err) - return err; - *field = value; - return NULL; -} - -/* begin-cop-ip-parse-handlers */ -static const char * -parse_ivc2_cr (CGEN_CPU_DESC, - const char **, - CGEN_KEYWORD *, - long *) ATTRIBUTE_UNUSED; -static const char * -parse_ivc2_cr (CGEN_CPU_DESC cd, - const char **strp, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long *field) -{ - return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); -} -static const char * -parse_ivc2_ccr (CGEN_CPU_DESC, - const char **, - CGEN_KEYWORD *, - long *) ATTRIBUTE_UNUSED; -static const char * -parse_ivc2_ccr (CGEN_CPU_DESC cd, - const char **strp, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long *field) -{ - return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); -} -/* end-cop-ip-parse-handlers */ - -const char * -parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, - CGEN_KEYWORD *keyword_table, long *field) -{ - const char *err; - - err = cgen_parse_keyword (cd, strp, keyword_table, field); - if (err) - return err; - if (*field != 13) - return _("Only $tp or $13 allowed for this opcode"); - return NULL; -} - -const char * -parse_spreg (CGEN_CPU_DESC cd, const char ** strp, - CGEN_KEYWORD *keyword_table, long *field) -{ - const char *err; - - err = cgen_parse_keyword (cd, strp, keyword_table, field); - if (err) - return err; - if (*field != 15) - return _("Only $sp or $15 allowed for this opcode"); - return NULL; -} - -const char * -parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, - enum cgen_operand_type type, long *field) -{ - long lsbs = 0; - const char *err; - - switch (type) - { - case MEP_OPERAND_PCREL8A2: - case MEP_OPERAND_PCREL12A2: - case MEP_OPERAND_PCREL17A2: - case MEP_OPERAND_PCREL24A2: - err = cgen_parse_signed_integer (cd, strp, type, field); - break; - case MEP_OPERAND_PCABS24A2: - case MEP_OPERAND_UDISP7: - case MEP_OPERAND_UDISP7A2: - case MEP_OPERAND_UDISP7A4: - case MEP_OPERAND_UIMM7A4: - case MEP_OPERAND_ADDR24A4: - err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); - break; - default: - abort(); - } - if (err) - return err; - switch (type) - { - case MEP_OPERAND_UDISP7: - lsbs = 0; - break; - case MEP_OPERAND_PCREL8A2: - case MEP_OPERAND_PCREL12A2: - case MEP_OPERAND_PCREL17A2: - case MEP_OPERAND_PCREL24A2: - case MEP_OPERAND_PCABS24A2: - case MEP_OPERAND_UDISP7A2: - lsbs = *field & 1; - break; - case MEP_OPERAND_UDISP7A4: - case MEP_OPERAND_UIMM7A4: - case MEP_OPERAND_ADDR24A4: - lsbs = *field & 3; - break; - lsbs = *field & 7; - break; - default: - /* Safe assumption? */ - abort (); - } - if (lsbs) - return "Value is not aligned enough"; - return NULL; -} - -const char * -parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, - enum cgen_operand_type type, unsigned long *field) -{ - return parse_mep_align (cd, strp, type, (long *) field); -} - - -/* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed - constants in a signed context. */ - -static const char * -parse_signed16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - return parse_lo16 (cd, strp, opindex, valuep, 1); -} - -static const char * -parse_lo16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep, - long signedp) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - if (strncasecmp (*strp, "%lo(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value &= 0xffff; - if (signedp) - *valuep = (long)(short) value; - else - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%hi(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = (value + 0x8000) >> 16; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%uhi(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, - & result_type, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value = value >> 16; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%sdaoff(", 8) == 0) - { - *strp += 8; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, - NULL, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%tpoff(", 7) == 0) - { - *strp += 7; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, - NULL, & value); - if (**strp != ')') - return _("missing `)'"); - ++*strp; - *valuep = value; - return errmsg; - } - - if (**strp == '%') - return _("invalid %function() here"); - - return cgen_parse_signed_integer (cd, strp, opindex, valuep); -} - -static const char * -parse_unsigned16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); -} - -static const char * -parse_signed16_range (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - signed long *valuep) -{ - const char *errmsg = 0; - signed long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value < -32768 || value > 32767) - return _("Immediate is out of range -32768 to 32767"); - - *valuep = value; - return 0; -} - -static const char * -parse_unsigned16_range (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = 0; - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (value > 65535) - return _("Immediate is out of range 0 to 65535"); - - *valuep = value; - return 0; -} - -/* A special case of parse_signed16 which accepts only the value zero. */ - -static const char * -parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ - - /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. - It will fail and cause ry to be listed as an undefined symbol in the - listing. */ - if (strncmp (*strp, "($", 2) == 0) - return "not zero"; /* any string will do -- will never be seen. */ - - if (strncasecmp (*strp, "%lo(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%hi(", 4) == 0) - { - *strp += 4; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%uhi(", 5) == 0) - { - *strp += 5; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%sdaoff(", 8) == 0) - { - *strp += 8; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (strncasecmp (*strp, "%tpoff(", 7) == 0) - { - *strp += 7; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, - &result_type, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - *valuep = value; - return errmsg; - } - - if (**strp == '%') - return "invalid %function() here"; - - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, - &result_type, &value); - if (errmsg == NULL - && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) - return "not zero"; /* any string will do -- will never be seen. */ - - return errmsg; -} - -static const char * -parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, - enum cgen_operand_type opindex, unsigned long *valuep) -{ - const char *errmsg; - bfd_vma value; - - /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ - - if (strncasecmp (*strp, "%tpoff(", 7) == 0) - { - int reloc; - *strp += 7; - switch (opindex) - { - case MEP_OPERAND_UDISP7: - reloc = BFD_RELOC_MEP_TPREL7; - break; - case MEP_OPERAND_UDISP7A2: - reloc = BFD_RELOC_MEP_TPREL7A2; - break; - case MEP_OPERAND_UDISP7A4: - reloc = BFD_RELOC_MEP_TPREL7A4; - break; - default: - /* Safe assumption? */ - abort (); - } - errmsg = cgen_parse_address (cd, strp, opindex, reloc, - NULL, &value); - if (**strp != ')') - return "missing `)'"; - ++*strp; - *valuep = value; - return errmsg; - } - - if (**strp == '%') - return _("invalid %function() here"); - - return parse_mep_alignu (cd, strp, opindex, valuep); -} - -static ATTRIBUTE_UNUSED const char * -parse_cdisp10 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - long *valuep) -{ - const char *errmsg = 0; - signed long value; - long have_zero = 0; - int wide = 0; - int alignment; - - switch (opindex) - { - case MEP_OPERAND_CDISP10A4: - alignment = 2; - break; - case MEP_OPERAND_CDISP10A2: - alignment = 1; - break; - case MEP_OPERAND_CDISP10: - default: - alignment = 0; - break; - } - - if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5) - wide = 1; - - if (strncmp (*strp, "0x0", 3) == 0 - || (**strp == '0' && *(*strp + 1) != 'x')) - have_zero = 1; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); - if (errmsg) - return errmsg; - - if (wide) - { - if (value < -512 || value > 511) - return _("Immediate is out of range -512 to 511"); - } - else - { - if (value < -128 || value > 127) - return _("Immediate is out of range -128 to 127"); - } - - if (value & ((1<<alignment)-1)) - return _("Value is not aligned enough"); - - /* If this field may require a relocation then use larger dsp16. */ - if (! have_zero && value == 0) - return (wide ? _("Immediate is out of range -512 to 511") - : _("Immediate is out of range -128 to 127")); - - *valuep = value; - return 0; -} - -/* BEGIN LIGHTWEIGHT MACRO PROCESSOR. */ - -#define MAXARGS 9 - -typedef struct -{ - char *name; - char *expansion; -} macro; - -typedef struct -{ - const char *start; - int len; -} arg; - -macro macros[] = -{ - { "sizeof", "(`1.end + (- `1))"}, - { "startof", "(`1 | 0)" }, - { "align4", "(`1&(~3))"}, -/*{ "hi", "(((`1+0x8000)>>16) & 0xffff)" }, */ -/*{ "lo", "(`1 & 0xffff)" }, */ -/*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ -/*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ - { 0,0 } -}; - -static char * expand_string (const char *, int); - -static const char * -mep_cgen_expand_macros_and_parse_operand - (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); - -static char * -str_append (char *dest, const char *input, int len) -{ - char *new_dest; - int oldlen; - - if (len == 0) - return dest; - /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ - oldlen = (dest ? strlen(dest) : 0); - new_dest = realloc (dest, oldlen + len + 1); - memset (new_dest + oldlen, 0, len + 1); - return strncat (new_dest, input, len); -} - -static macro * -lookup_macro (const char *name) -{ - macro *m; - - for (m = macros; m->name; ++m) - if (strncmp (m->name, name, strlen(m->name)) == 0) - return m; - - return 0; -} - -static char * -expand_macro (arg *args, int narg, macro *mac) -{ - char *result = 0, *rescanned_result = 0; - char *e = mac->expansion; - char *mark = e; - int mac_arg = 0; - - /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ - while (*e) - { - if (*e == '`' && - (*e+1) && - ((*(e + 1) - '1') <= MAXARGS) && - ((*(e + 1) - '1') <= narg)) - { - result = str_append (result, mark, e - mark); - mac_arg = (*(e + 1) - '1'); - /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */ - result = str_append (result, args[mac_arg].start, args[mac_arg].len); - ++e; - mark = e+1; - } - ++e; - } - - if (mark != e) - result = str_append (result, mark, e - mark); - - if (result) - { - rescanned_result = expand_string (result, 0); - free (result); - return rescanned_result; - } - else - return result; -} - -#define IN_TEXT 0 -#define IN_ARGS 1 - -static char * -expand_string (const char *in, int first_only) -{ - int num_expansions = 0; - int depth = 0; - int narg = -1; - arg args[MAXARGS]; - int state = IN_TEXT; - const char *mark = in; - macro *pmacro = NULL; - char *expansion = 0; - char *result = 0; - - while (*in) - { - switch (state) - { - case IN_TEXT: - if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) - { - pmacro = lookup_macro (in + 1); - if (pmacro) - { - /* printf("entering state %d at '%s'...\n", state, in); */ - result = str_append (result, mark, in - mark); - mark = in; - in += 1 + strlen (pmacro->name); - while (*in == ' ') ++in; - if (*in != '(') - { - state = IN_TEXT; - pmacro = NULL; - } - else - { - state = IN_ARGS; - narg = 0; - args[narg].start = in + 1; - args[narg].len = 0; - mark = in + 1; - } - } - } - break; - case IN_ARGS: - if (depth == 0) - { - switch (*in) - { - case ',': - narg++; - args[narg].start = (in + 1); - args[narg].len = 0; - break; - case ')': - state = IN_TEXT; - /* printf("entering state %d at '%s'...\n", state, in); */ - if (pmacro) - { - expansion = 0; - expansion = expand_macro (args, narg, pmacro); - num_expansions++; - if (expansion) - { - result = str_append (result, expansion, strlen (expansion)); - free (expansion); - } - } - else - { - result = str_append (result, mark, in - mark); - } - pmacro = NULL; - mark = in + 1; - break; - case '(': - depth++; - default: - args[narg].len++; - break; - } - } - else - { - if (*in == ')') - depth--; - if (narg > -1) - args[narg].len++; - } - - } - ++in; - } - - if (mark != in) - result = str_append (result, mark, in - mark); - - return result; -} - -#undef IN_ARGS -#undef IN_TEXT -#undef MAXARGS - - -/* END LIGHTWEIGHT MACRO PROCESSOR. */ - -const char * mep_cgen_parse_operand - (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); - -const char * -mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, - const char ** strp_in, CGEN_FIELDS * fields) -{ - const char * errmsg = NULL; - char *str = 0, *hold = 0; - const char **strp = 0; - - /* Set up a new pointer to macro-expanded string. */ - str = expand_string (*strp_in, 1); - /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ - - hold = str; - strp = (const char **)(&str); - - errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); - - /* Now work out the advance. */ - if (strlen (str) == 0) - *strp_in += strlen (*strp_in); - - else - { - if (strstr (*strp_in, str)) - /* A macro-expansion was pulled off the front. */ - *strp_in = strstr (*strp_in, str); - else - /* A non-macro-expansion was pulled off the front. */ - *strp_in += (str - hold); - } - - if (hold) - free (hold); - - return errmsg; -} - -#define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); - -/* -- dis.c */ - -#include "elf/mep.h" -#include "elf-bfd.h" - -#define CGEN_VALIDATE_INSN_SUPPORTED - -static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); -static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); - -static void -print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, - CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, - unsigned int flags ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$tp"); -} - -static void -print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, - CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, - unsigned int flags ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, "$sp"); -} - -/* begin-cop-ip-print-handlers */ -static void -print_ivc2_cr (CGEN_CPU_DESC, - void *, - CGEN_KEYWORD *, - long, - unsigned int) ATTRIBUTE_UNUSED; -static void -print_ivc2_cr (CGEN_CPU_DESC cd, - void *dis_info, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long value, - unsigned int attrs) -{ - print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); -} -static void -print_ivc2_ccr (CGEN_CPU_DESC, - void *, - CGEN_KEYWORD *, - long, - unsigned int) ATTRIBUTE_UNUSED; -static void -print_ivc2_ccr (CGEN_CPU_DESC cd, - void *dis_info, - CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, - long value, - unsigned int attrs) -{ - print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); -} -/* end-cop-ip-print-handlers */ - -/************************************************************\ -*********************** Experimental ************************* -\************************************************************/ - -#undef CGEN_PRINT_INSN -#define CGEN_PRINT_INSN mep_print_insn - -static int -mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, - bfd_byte *buf, int corelength, int copro1length, - int copro2length ATTRIBUTE_UNUSED) -{ - int i; - int status = 0; - /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ - bfd_byte insnbuf[64]; - - /* If corelength > 0 then there is a core insn present. It - will be at the beginning of the buffer. After printing - the core insn, we need to print the + on the next line. */ - if (corelength > 0) - { - int my_status = 0; - - for (i = 0; i < corelength; i++ ) - insnbuf[i] = buf[i]; - cd->isas = & MEP_CORE_ISA; - - my_status = print_insn (cd, pc, info, insnbuf, corelength); - if (my_status != corelength) - { - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - my_status = corelength; - } - status += my_status; - - /* Print the + to indicate that the following copro insn is */ - /* part of a vliw group. */ - if (copro1length > 0) - (*info->fprintf_func) (info->stream, " + "); - } - - /* Now all that is left to be processed is the coprocessor insns - In vliw mode, there will always be one. Its positioning will - be from byte corelength to byte corelength+copro1length -1. - No need to check for existence. Also, the first vliw insn, - will, as spec'd, always be at least as long as the core insn - so we don't need to flush the buffer. */ - if (copro1length > 0) - { - int my_status = 0; - - for (i = corelength; i < corelength + copro1length; i++ ) - insnbuf[i - corelength] = buf[i]; - - switch (copro1length) - { - case 0: - break; - case 2: - cd->isas = & MEP_COP16_ISA; - break; - case 4: - cd->isas = & MEP_COP32_ISA; - break; - case 6: - cd->isas = & MEP_COP48_ISA; - break; - case 8: - cd->isas = & MEP_COP64_ISA; - break; - default: - /* Shouldn't be anything but 16,32,48,64. */ - break; - } - - my_status = print_insn (cd, pc, info, insnbuf, copro1length); - - if (my_status != copro1length) - { - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - my_status = copro1length; - } - status += my_status; - } - -#if 0 - /* Now we need to process the second copro insn if it exists. We - have no guarantee that the second copro insn will be longer - than the first, so we have to flush the buffer if we are have - a second copro insn to process. If present, this insn will - be in the position from byte corelength+copro1length to byte - corelength+copro1length+copro2length-1 (which better equal 8 - or else we're in big trouble. */ - if (copro2length > 0) - { - int my_status = 0; - - for (i = 0; i < 64 ; i++) - insnbuf[i] = 0; - - for (i = corelength + copro1length; i < 64; i++) - insnbuf[i - (corelength + copro1length)] = buf[i]; - - switch (copro2length) - { - case 2: - cd->isas = 1 << ISA_EXT_COP1_16; - break; - case 4: - cd->isas = 1 << ISA_EXT_COP1_32; - break; - case 6: - cd->isas = 1 << ISA_EXT_COP1_48; - break; - case 8: - cd->isas = 1 << ISA_EXT_COP1_64; - break; - default: - /* Shouldn't be anything but 16,32,48,64. */ - break; - } - - my_status = print_insn (cd, pc, info, insnbuf, copro2length); - - if (my_status != copro2length) - { - (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); - my_status = copro2length; - } - - status += my_status; - } -#endif - - /* Status should now be the number of bytes that were printed - which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ - - if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) - return -1; - else - return status; -} - -/* The two functions mep_examine_vliw[32,64]_insns are used find out - which vliw combinaion (16 bit core with 48 bit copro, 32 bit core - with 32 bit copro, etc.) is present. Later on, when internally - parallel coprocessors are handled, only these functions should - need to be changed. - - At this time only the following combinations are supported: - - VLIW32 Mode: - 16 bit core insn (core) and 16 bit coprocessor insn (cop1) - 32 bit core insn (core) - 32 bit coprocessor insn (cop1) - Note: As of this time, I do not believe we have enough information - to distinguish a 32 bit core insn from a 32 bit cop insn. Also, - no 16 bit coprocessor insns have been specified. - - VLIW64 Mode: - 16 bit core insn (core) and 48 bit coprocessor insn (cop1) - 32 bit core insn (core) and 32 bit coprocessor insn (cop1) - 64 bit coprocessor insn (cop1) - - The framework for an internally parallel coprocessor is also - present (2nd coprocessor insn is cop2), but at this time it - is not used. This only appears to be valid in VLIW64 mode. */ - -static int -mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - int status; - int buflength; - int corebuflength; - int cop1buflength; - int cop2buflength; - bfd_byte buf[CGEN_MAX_INSN_SIZE]; - char indicator16[1]; - char indicatorcop32[2]; - - /* At this time we're not supporting internally parallel coprocessors, - so cop2buflength will always be 0. */ - cop2buflength = 0; - - /* Read in 32 bits. */ - buflength = 4; /* VLIW insn spans 4 bytes. */ - status = (*info->read_memory_func) (pc, buf, buflength, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - /* Put the big endian representation of the bytes to be examined - in the temporary buffers for examination. */ - - if (info->endian == BFD_ENDIAN_BIG) - { - indicator16[0] = buf[0]; - indicatorcop32[0] = buf[0]; - indicatorcop32[1] = buf[1]; - } - else - { - indicator16[0] = buf[1]; - indicatorcop32[0] = buf[1]; - indicatorcop32[1] = buf[0]; - } - - /* If the two high order bits are 00, 01 or 10, we have a 16 bit - core insn and a 48 bit copro insn. */ - - if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) - { - if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) - { - /* We have a 32 bit copro insn. */ - corebuflength = 0; - /* All 4 4ytes are one copro insn. */ - cop1buflength = 4; - } - else - { - /* We have a 32 bit core. */ - corebuflength = 4; - cop1buflength = 0; - } - } - else - { - /* We have a 16 bit core insn and a 16 bit copro insn. */ - corebuflength = 2; - cop1buflength = 2; - } - - /* Now we have the distrubution set. Print them out. */ - status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, - cop1buflength, cop2buflength); - - return status; -} - -static int -mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - int status; - int buflength; - int corebuflength; - int cop1buflength; - int cop2buflength; - bfd_byte buf[CGEN_MAX_INSN_SIZE]; - char indicator16[1]; - char indicator64[4]; - - /* At this time we're not supporting internally parallel - coprocessors, so cop2buflength will always be 0. */ - cop2buflength = 0; - - /* Read in 64 bits. */ - buflength = 8; /* VLIW insn spans 8 bytes. */ - status = (*info->read_memory_func) (pc, buf, buflength, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - /* We have all 64 bits in the buffer now. We have to figure out - what combination of instruction sizes are present. The two - high order bits will indicate whether or not we have a 16 bit - core insn or not. If not, then we have to look at the 7,8th - bytes to tell whether we have 64 bit copro insn or a 32 bit - core insn with a 32 bit copro insn. Endianness will make a - difference here. */ - - /* Put the big endian representation of the bytes to be examined - in the temporary buffers for examination. */ - - /* indicator16[0] = buf[0]; */ - if (info->endian == BFD_ENDIAN_BIG) - { - indicator16[0] = buf[0]; - indicator64[0] = buf[0]; - indicator64[1] = buf[1]; - indicator64[2] = buf[2]; - indicator64[3] = buf[3]; - } - else - { - indicator16[0] = buf[1]; - indicator64[0] = buf[1]; - indicator64[1] = buf[0]; - indicator64[2] = buf[3]; - indicator64[3] = buf[2]; - } - - /* If the two high order bits are 00, 01 or 10, we have a 16 bit - core insn and a 48 bit copro insn. */ - - if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) - { - if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 - && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) - { - /* We have a 64 bit copro insn. */ - corebuflength = 0; - /* All 8 bytes are one copro insn. */ - cop1buflength = 8; - } - else - { - /* We have a 32 bit core insn and a 32 bit copro insn. */ - corebuflength = 4; - cop1buflength = 4; - } - } - else - { - /* We have a 16 bit core insn and a 48 bit copro insn. */ - corebuflength = 2; - cop1buflength = 6; - } - - /* Now we have the distrubution set. Print them out. */ - status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, - cop1buflength, cop2buflength); - - return status; -} - -#ifdef MEP_IVC2_SUPPORTED - -static int -print_slot_insn (CGEN_CPU_DESC cd, - bfd_vma pc, - disassemble_info *info, - SLOTS_ATTR slot, - bfd_byte *buf) -{ - const CGEN_INSN_LIST *insn_list; - CGEN_INSN_INT insn_value; - CGEN_EXTRACT_INFO ex_info; - - insn_value = cgen_get_insn_value (cd, buf, 32); - - /* Fill in ex_info fields like read_insn would. Don't actually call - read_insn, since the incoming buffer is already read (and possibly - modified a la m32r). */ - ex_info.valid = (1 << 8) - 1; - ex_info.dis_info = info; - ex_info.insn_bytes = buf; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); - while (insn_list != NULL) - { - const CGEN_INSN *insn = insn_list->insn; - CGEN_FIELDS fields; - int length; - - if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) - && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) - || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) - { - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - continue; - } - - if ((insn_value & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* Printing is handled in two passes. The first pass parses the - machine insn and extracts the fields. The second pass prints - them. */ - - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, insn_value, &fields, pc); - - /* Length < 0 -> error. */ - if (length < 0) - return length; - if (length > 0) - { - CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); - /* Length is in bits, result is in bytes. */ - return length / 8; - } - } - - insn_list = CGEN_DIS_NEXT_INSN (insn_list); - } - - if (slot == SLOTS_P0S) - (*info->fprintf_func) (info->stream, "*unknown-p0s*"); - else if (slot == SLOTS_P0) - (*info->fprintf_func) (info->stream, "*unknown-p0*"); - else if (slot == SLOTS_P1) - (*info->fprintf_func) (info->stream, "*unknown-p1*"); - else if (slot == SLOTS_C3) - (*info->fprintf_func) (info->stream, "*unknown-c3*"); - return 0; -} - -static int -mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) -{ - int status; - int buflength; - bfd_byte buf[8]; - bfd_byte insn[8]; - int e; - - /* Read in 64 bits. */ - buflength = 8; /* VLIW insn spans 8 bytes. */ - status = (*info->read_memory_func) (pc, buf, buflength, info); - - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - - if (info->endian == BFD_ENDIAN_LITTLE) - e = 1; - else - e = 0; - - if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) - { - /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ - /* V1 [-----core-----][--------p0s-------][------------p1------------] */ - - print_insn (cd, pc, info, buf, 2); - - insn[0^e] = 0; - insn[1^e] = buf[2^e]; - insn[2^e] = buf[3^e]; - insn[3^e] = buf[4^e] & 0xf0; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P0S, insn); - - insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; - insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; - insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; - insn[3^e] = buf[7^e] << 4; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P1, insn); - } - else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) - { - /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ - /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ - /* 00000000111111112222222233333333 */ - - insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; - insn[1^e] = buf[2^e]; - insn[2^e] = buf[3^e]; - insn[3^e] = buf[4^e] & 0xf0; - print_slot_insn (cd, pc, info, SLOTS_P0, insn); - - insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; - insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; - insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; - insn[3^e] = buf[7^e] << 4; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P1, insn); - } - else - { - /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ - /* V2 [-------------core-------------]xxxx[------------p1------------] */ - print_insn (cd, pc, info, buf, 4); - - insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; - insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; - insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; - insn[3^e] = buf[7^e] << 4; - (*info->fprintf_func) (info->stream, " + "); - print_slot_insn (cd, pc, info, SLOTS_P1, insn); - } - - return 8; -} - -#endif /* MEP_IVC2_SUPPORTED */ - -/* This is a hack. SID calls this to update the disassembler as the - CPU changes modes. */ -static int mep_ivc2_disassemble_p = 0; -static int mep_ivc2_vliw_disassemble_p = 0; - -void -mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); -void -mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) -{ - mep_ivc2_disassemble_p = ivc2_p; - mep_ivc2_vliw_disassemble_p = vliw_p; - mep_config_index = cfg_idx; -} - -static int -mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) -{ - int status; - int cop_type; - int ivc2 = 0; - static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; - - if (ivc2_core_isa == NULL) - { - /* IVC2 has some core-only coprocessor instructions. We - use COP32 to flag those, and COP64 for the VLIW ones, - since they have the same names. */ - ivc2_core_isa = cgen_bitset_create (MAX_ISAS); - } - - /* Extract and adapt to configuration number, if available. */ - if (info->section && info->section->owner) - { - bfd *abfd = info->section->owner; - mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; - /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ - - cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; - if (cop_type == EF_MEP_COP_IVC2) - ivc2 = 1; - } - - /* Picking the right ISA bitmask for the current context is tricky. */ - if (info->section) - { - if (info->section->flags & SEC_MEP_VLIW) - { -#ifdef MEP_IVC2_SUPPORTED - if (ivc2) - { - /* ivc2 has its own way of selecting its functions. */ - cd->isas = & MEP_CORE_ISA; - status = mep_examine_ivc2_insns (cd, pc, info); - } - else -#endif - /* Are we in 32 or 64 bit vliw mode? */ - if (MEP_VLIW64) - status = mep_examine_vliw64_insns (cd, pc, info); - else - status = mep_examine_vliw32_insns (cd, pc, info); - /* Both the above branches set their own isa bitmasks. */ - } - else - { - if (ivc2) - { - cgen_bitset_clear (ivc2_core_isa); - cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); - cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); - cd->isas = ivc2_core_isa; - } - else - cd->isas = & MEP_CORE_ISA; - status = default_print_insn (cd, pc, info); - } - } - else /* sid or gdb */ - { -#ifdef MEP_IVC2_SUPPORTED - if (mep_ivc2_disassemble_p) - { - if (mep_ivc2_vliw_disassemble_p) - { - cd->isas = & MEP_CORE_ISA; - status = mep_examine_ivc2_insns (cd, pc, info); - return status; - } - else - { - if (ivc2) - cd->isas = ivc2_core_isa; - } - } -#endif - - status = default_print_insn (cd, pc, info); - } - - return status; -} - - -/* -- opc.c */ -#include "elf/mep.h" - -/* A mask for all ISAs executed by the core. */ -CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; - -void -init_mep_all_core_isas_mask (void) -{ - if (mep_all_core_isas_mask.length != 0) - return; - cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); - cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); - /* begin-all-core-isas */ - cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); - /* end-all-core-isas */ -} - -CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; - -void -init_mep_all_cop_isas_mask (void) -{ - if (mep_all_cop_isas_mask.length != 0) - return; - cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); - /* begin-all-cop-isas */ - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); - cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); - /* end-all-cop-isas */ -} - -int -mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) -{ - CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); - return cgen_bitset_intersect_p (& insn_isas, isa_mask); -} - -#define OPTION_MASK \ - ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ - | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) - - -mep_config_map_struct mep_config_map[] = -{ - /* config-map-start */ - /* Default entry: first module, with all options enabled. */ - { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, - { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, - 0 - | (1 << CGEN_INSN_OPTIONAL_CP_INSN) - | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) - | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) - | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) - | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) - | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) - | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) - | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) - | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) - | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) - | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, - /* config-map-end */ - { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } -}; - -int mep_config_index = 0; - -static int -check_configured_mach (int machs) -{ - /* All base insns are supported. */ - int mach = 1 << MACH_BASE; - switch (MEP_CPU & EF_MEP_CPU_MASK) - { - case EF_MEP_CPU_C2: - case EF_MEP_CPU_C3: - mach |= (1 << MACH_MEP); - break; - case EF_MEP_CPU_H1: - mach |= (1 << MACH_H1); - break; - case EF_MEP_CPU_C5: - mach |= (1 << MACH_MEP); - mach |= (1 << MACH_C5); - break; - default: - break; - } - return machs & mach; -} - -int -mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ - int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); - int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); - int ok1; - int ok2; - int ok3; - - /* If the insn has an option bit set that we don't want, - reject it. */ - if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) - return 0; - - /* If attributes are absent, assume no restriction. */ - if (machs == 0) - machs = ~0; - - ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); - /* If the insn is config-specific, make sure it matches. */ - ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); - /* Make sure the insn is supported by the configured mach */ - ok3 = check_configured_mach (machs); - - return (ok1 && ok2 && ok3); -} - -int -mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ -#ifdef MEP_IVC2_SUPPORTED - /* If we're assembling VLIW packets, ignore the 12-bit BSR as we - can't relax that. The 24-bit BSR is matched instead. */ - if (insn->base->num == MEP_INSN_BSR12 - && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) - return 0; -#endif - - return mep_cgen_insn_supported (cd, insn); -} diff --git a/binutils-2.24/cpu/mt.cpu b/binutils-2.24/cpu/mt.cpu deleted file mode 100644 index bb987f31..00000000 --- a/binutils-2.24/cpu/mt.cpu +++ /dev/null @@ -1,1352 +0,0 @@ -; Morpho Technologies MT Arch description. -*- Scheme -*- -; Copyright 2001, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from -; Morpho Technologies. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(include "simplify.inc") - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Define The Architecture, Attributes, ISA, CPU, Machine, And Model. ;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -; define-arch must appear first -(define-arch - (name mt) ; name of cpu family - (comment "Morpho Technologies mRISC family") - (default-alignment aligned) - (insn-lsb0? #t) - (machs ms1 ms1-003 ms2) - (isas mt) -) - -; Instruction set parameters. - -(define-isa - (name mt) - (comment "Morpho Technologies MT ISA") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - (base-insn-bitsize 32) - (parallel-insns 2) -) - -; Cpu family definitions. - - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - (name ms1bf) - (comment "Morpho Technologies mRISC family") - (endian big) - (word-bitsize 32) -) - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - (name ms1-003bf) - (comment "Morpho Technologies mRISC family") - (endian big) - (word-bitsize 32) -) - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - (name ms2bf) - (comment "Morpho Technologies mRISC family") - (endian big) - (word-bitsize 32) -) - -(define-mach - (name ms1) - (comment "Morpho Technologies mrisc") - (cpu ms1bf) - (isas mt) -) - -(define-mach - (name ms1-003) - (comment "Morpho Technologies mrisc") - (cpu ms1-003bf) - (isas mt) -) - -(define-mach - (name ms2) - (comment "Morpho Technologies ms2") - (cpu ms2bf) - (isas mt) -) - - -; Model descriptions. -; Can probably take the u-exec out. We'll see. -(define-model - (name ms1) - (comment "Morpho Technologies mrisc") - (mach ms1) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -(define-model - (name ms1-003) - (comment "Morpho Technologies mrisc") - (mach ms1-003) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -(define-model - (name ms2) - (comment "Morpho Technologies ms2") - (mach ms2) - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - () ; inputs - () ; outputs - () ; profile action (default) - ) -) - -; FIXME: It might simplify things to separate the execute process from the -; one that updates the PC. - - -;;;;;;;;;;;;;;;;;;;;;;;; -;; Instruction Fields ;; -;;;;;;;;;;;;;;;;;;;;;;;; - -; Attributes: -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes?) -; RESERVED: bits are not used to decode insn, must be all 0 -; RELOC: there is a relocation associated with this field (experiment) -; -; f-msys: Identify a a morphosys insns. 1 if msys, 0 if not. -; f-opc: 6 bit opcode for non-morphosys instructions. -; f-msopc: 6 bit opcode for morphosys instructions. -; f-imm: flag to indicate use of an immediate operand. 1 if yes, 0 if no. -; f-sr1: source resgister 1. (also used for MSYS insns) -; f-sr2: source register 2. (also used for MSYS insns) -; f-dr: destination register when located in bits 19:16. -; f-drrr: destination register when located in bits 15:12. (also for MSYS insns) -; f-imm16: 16 bit immediate value when not an offset. -; f-imm16a: 16 bit immediate value when it's a pc-rel offset. -; f-uu4a: unused 4 bit field. -; f-uu4b: second unsed 4 bit field. -; f-uu1: unused 1 bit field -; f-uu12: unused 12 bit field. -; f-uu16: unused 16 bit field. -; f-uu24: unused 24 bit field. - -(dnf f-msys "morphosys insn flag" () 31 1) -(dnf f-opc "opcode field" () 30 6) -(dnf f-imm "immedate flag" () 24 1) -(dnf f-uu24 "unused 24 bits" () 23 24) -(dnf f-sr1 "sr1 register field" (ABS-ADDR) 23 4) -(dnf f-sr2 "sr2 register field" (ABS-ADDR) 19 4) -(dnf f-dr "dr register field" (ABS-ADDR) 19 4) -(dnf f-drrr "drrr register field" (ABS-ADDR) 15 4) -(dnf f-imm16u "unsigned 16 bit immediate" () 15 16) -(df f-imm16s "signed 16 bit immediate" () 15 16 INT ((value pc) (add HI value 0)) ((value pc) (add HI value 0))) -(dnf f-imm16a "pc-rel offset" (PCREL-ADDR) 15 16) -(dnf f-uu4a "unused 4 bit field" () 19 4) -(dnf f-uu4b "unused 4 bit field" () 23 4) -(dnf f-uu12 "unused 12 bit field" () 11 12) -(dnf f-uu8 "unused 8 bit field" () 15 8) -(dnf f-uu16 "unused 16 bit field" () 15 16) -(dnf f-uu1 "unused 1 bit field" () 7 1) - -; The following ifields are used exclusively for the MorphoSys instructions. -; In a few cases, a bit field is used for something in addition to what its -; name suggests. For the most part, the names are meaningful though. - -(dnf f-msopc "opcode field" () 30 5) -(dnf f-uu-26-25 "unused 26 bits" () 25 26) -(dnf f-mask "mask" () 25 16) -(dnf f-bankaddr "bank address" () 25 13) -(dnf f-rda "rda" () 25 1) -(dnf f-uu-2-25 "unused bits 25 & 24" () 25 2) -(dnf f-rbbc "Omega network configuration" () 25 2) -(dnf f-perm "perm" () 25 2) -(dnf f-mode "mode" () 25 2) -(dnf f-uu-1-24 "testing" () 24 1) -(dnf f-wr "wr" () 24 1) -(dnf f-fbincr "fb incr" () 23 4) -(dnf f-uu-2-23 "unused bits 23 and 22" () 23 2) -(dnf f-xmode "xmode" () 23 1) -(dnf f-a23 "a23" () 23 1) -(dnf f-mask1 "mask1" () 22 3) -(dnf f-cr "cr" () 22 3) -(dnf f-type "type" () 21 2) -(dnf f-incamt "increment amount" () 19 8) -(dnf f-cbs "cbs" () 19 2) -(dnf f-uu-1-19 "unused bit 19" () 19 1) -(dnf f-ball "b_all" () 19 1) -(dnf f-colnum "column number" () 18 3) -(dnf f-brc "b_r_c" () 18 3) -(dnf f-incr "incr" () 17 6) -(dnf f-fbdisp "frame buffer displacement" () 15 6) -(dnf f-uu-4-15 "unused bits 15,14,13,12" () 15 4) -(dnf f-length "length" () 15 3) -(dnf f-uu-1-15 "unused bit 15" () 15 1) -(dnf f-rc "row/column context" () 15 1) -(dnf f-rcnum "starting cell of cntxt mem." () 14 3) -(dnf f-rownum "row number" () 14 3) -(dnf f-cbx "cbx" () 14 3) -(dnf f-id "id" () 14 1) -(dnf f-size "size" () 13 14) -(dnf f-rownum1 "row number" () 12 3) -(dnf f-uu-3-11 "unused 3 bits (11-9)" () 11 3) -(dnf f-rc1 "row/column context" () 11 1) -(dnf f-ccb "ccb" () 11 1) -(dnf f-cbrb "data-bus orientation" () 10 1) -(dnf f-cdb "cdb" () 10 1) -(dnf f-rownum2 "row number" () 9 3) -(dnf f-cell "cell" () 9 3) -(dnf f-uu-3-9 "unused 3 bits (9-7)" () 9 3) -(dnf f-contnum "context number" () 8 9) -(dnf f-uu-1-6 "unused bit 6" () 6 1) -(dnf f-dup "dup" () 6 1) -(dnf f-rc2 "rc2" () 6 1) -(dnf f-ctxdisp "context displacement" () 5 6) - -; additional fields in ms2 -(dnf f-imm16l "loop count" () 23 16) -(df f-loopo "loop offset" () 7 8 UINT - ((value pc) (srl SI value 2)) - ((value pc) (add SI (sll value 2) 8)) - ) -(dnf f-cb1sel "cb1 select" () 25 3) -(dnf f-cb2sel "cb2 select" () 22 3) -(dnf f-cb1incr "cb1 increment" (SIGNED) 19 6) -(dnf f-cb2incr "cb2 increment" (SIGNED) 13 6) -(dnf f-rc3 "row/colum context" () 7 1) - -; The following is just for a test -(dnf f-msysfrsr2 "sr2 for msys" () 19 4) -(dnf f-brc2 "b_r_c2" () 14 3) -(dnf f-ball2 "b_all2" () 15 1) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Enumerations Of Instruction Fields ;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -; insn-msys: bit 31. 1 for Morphosys Insns, 0 if not. -(define-normal-insn-enum insn-msys "msys enums" () MSYS_ f-msys - (NO YES) -) - -; insn-opc: bits 30 through 25 . Non-MorphoSys Instructions -; Note - the documentation is wrong for the encoding of the DBNZ -; instruction. It is actually 011110. See Issue 67699. -(define-normal-insn-enum insn-opc "opc enums" () OPC_ f-opc - (ADD ADDU SUB SUBU MUL - - - - AND OR XOR NAND NOR XNOR LDUI - - LSL LSR ASR - - - - - - BRLT BRLE BREQ JMP JAL BRNEQ DBNZ LOOP - LDW STW - - - - - - - - - - - - - - - - EI DI SI RETI BREAK IFLUSH - - - ) -) - -; insn-msopc: bits 30 through 26 . MorphoSys Instructions -(define-normal-insn-enum insn-msopc "msopc enums" () MSOPC_ f-msopc - (LDCTXT LDFB STFB FBCB MFBCB FBCCI FBRCI FBCRI - FBRRI MFBCCI MFBRCI MFBCRI MFBRRI FBCBDR RCFBCB MRCFBCB - CBCAST DUPCBCAST WFBI WFB RCRISC FBCBINC RCXMODE INTLVR - WFBINC MWFBINC WFBINCR MWFBINCR FBCBINCS MFBCBINCS FBCBINCRS MFBCBINCRS - - - - - - - - - - ) -) - -; insn-imm: bit 24. Immediate operand indicator. -(define-normal-insn-enum insn-imm "imm enums" () IMM_ f-imm - ; This bit specifies whether and immediate operand will be present. - ; It's 1 if there is, 0 if there is not. - (NO YES) -) -;;;;;;;;;;;;;;;; -;; Attributes ;; -;;;;;;;;;;;;;;;; - -; Might not need this. Keep if for the sim just in case. -;(define-attr -; (for insn) -; (type boolean) -; (name EXT-SKIP-INSN) -; (comment "instruction is a PAGE, LOADL or LOADH instruction") -;) - -(define-attr - (for insn) - (type boolean) - (name LOAD-DELAY) - (comment "insn has a load delay") -) - -(define-attr - (for insn) - (type boolean) - (name MEMORY-ACCESS) - (comment "insn performs a memory access") -) - -(define-attr - (for insn) - (type boolean) - (name AL-INSN) - (comment "insn is an arithmetic or logic insn.") -) - -(define-attr - (for insn) - (type boolean) - (name IO-INSN) - (comment "insn performs an I/O operation") -) - -(define-attr - (for insn) - (type boolean) - (name BR-INSN) - (comment "insn performs an I/O operation") -) - -(define-attr - (for insn) - (type boolean) - (name JAL-HAZARD) - (comment "insn has jal-like hazard") -) - -(define-pmacro (define-reg-use-attr regfield) - (define-attr - (for insn) - (type boolean) - (name (.sym "USES-" (.upcase regfield))) - (comment ("insn accesses register operand " regfield)))) - -(define-reg-use-attr "frdr") -(define-reg-use-attr "frdrrr") -(define-reg-use-attr "frsr1") -(define-reg-use-attr "frsr2") - - -; Might not need this. Keep it for the sim just in case. -(define-attr - (for insn) - (type boolean) - (name SKIPA) - (comment "instruction is a SKIP instruction") -) - - -;;;;;;;;;;;;;;;;;;;;; -;; Hardware Pieces ;; -;;;;;;;;;;;;;;;;;;;;; - -;(define-pmacro (build-reg-name n) (.splice (.str "$" n) n)) - -; These are the 16 registers that the chip has. In later versions -; where there will be more registers, this will need to be expanded. -; Note that there are two entries for the registers with two names. -(define-hardware - (name h-spr) - (comment "special-purpose registers") - (type register SI (16)) - (indices keyword "" (("R0" 0) ("R1" 1) ("R2" 2) ("R3" 3) ("R4" 4) ("R5" 5) - ("R6" 6) ("R7" 7) ("R8" 8) ("R9" 9) ("R10" 10) ("R11" 11) ("R12" 12) ("fp" 12) - ("R13" 13) ("sp" 13) ("R14" 14) ("ra" 14) ("R15" 15) ("ira" 15))) -; (get (index) (and (raw-reg h-spr) #xffffffff)) -; (set (index value) (set (raw-reg h-spr) (and value #xffffffff))) -) - -; This is the program counter. -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -(define-keyword - (name msys-syms) - (print-name h-nil) - (prefix "") - (values (DUP 1) (XX 0)) -) - -;;;;;;;;;;;;;; -;; Operands ;; -;;;;;;;;;;;;;; - -(define-operand (name frsr1) (comment "register") (attrs) - (type h-spr) (index f-sr1) ) -(define-operand (name frsr2) (comment "register") (attrs) - (type h-spr) (index f-sr2) ) -(define-operand (name frdr) (comment "register") (attrs) - (type h-spr) (index f-dr) ) -(define-operand (name frdrrr) (comment "register") (attrs) - (type h-spr) (index f-drrr) ) -(define-operand (name imm16) (comment "immediate value - sign extd") (attrs) - (type h-sint) (index f-imm16s) (handlers (parse "imm16") (print "dollarhex"))) -(define-operand (name imm16z) (comment "immediate value - zero extd") (attrs) - (type h-uint) (index f-imm16u) (handlers (parse "imm16") (print "dollarhex"))) -(define-operand (name imm16o) (comment "immediate value") (attrs PCREL-ADDR) - (type h-uint) (index f-imm16s) (handlers (parse "imm16") (print "pcrel"))) - -; Operands for MorphoSys Instructions - -(define-operand (name rc) (comment "rc") (attrs) - (type h-uint) (index f-rc) (handlers (parse "rc") (print "dollarhex"))) - -(define-operand (name rcnum) (comment "rcnum") (attrs) - (type h-uint) (index f-rcnum) (handlers (print "dollarhex"))) - -(define-operand (name contnum) (comment "context number") (attrs) - (type h-uint) (index f-contnum) (handlers (print "dollarhex"))) - -(define-operand (name rbbc) (comment "omega network configuration") (attrs) - (type h-uint) (index f-rbbc) (handlers (parse "rbbc") (print "dollarhex"))) - -(define-operand (name colnum) (comment "column number") (attrs) - (type h-uint) (index f-colnum) (handlers (print "dollarhex"))) - -(define-operand (name rownum) (comment "row number") (attrs) - (type h-uint) (index f-rownum) (handlers (print "dollarhex"))) - -(define-operand (name rownum1) (comment "row number") (attrs) - (type h-uint) (index f-rownum1) (handlers (print "dollarhex"))) - -(define-operand (name rownum2) (comment "row number") (attrs) - (type h-uint) (index f-rownum2) (handlers (print "dollarhex"))) - -(define-operand (name rc1) (comment "rc1") (attrs) - (type h-uint) (index f-rc1) (handlers (parse "rc") (print "dollarhex"))) - -(define-operand (name rc2) (comment "rc2") (attrs) - (type h-uint) (index f-rc2) (handlers (parse "rc") (print "dollarhex"))) - -(define-operand (name cbrb) (comment "data-bus orientation") (attrs) - (type h-uint) (index f-cbrb) (handlers (parse "cbrb") (print "dollarhex"))) - -(define-operand (name cell) (comment "cell") (attrs) - (type h-uint) (index f-cell) (handlers (print "dollarhex"))) - -(define-operand (name dup) (comment "dup") (attrs) - (type h-uint) (index f-dup) (handlers (parse "dup") (print "dollarhex"))) - -(define-operand (name ctxdisp) (comment "context displacement") (attrs) - (type h-uint) (index f-ctxdisp) (handlers (print "dollarhex"))) - -(define-operand (name fbdisp) (comment "frame buffer displacement") (attrs) - (type h-uint) (index f-fbdisp) (handlers (print "dollarhex"))) - -(define-operand (name type) (comment "type") (attrs) - (type h-uint) (index f-type) (handlers (parse "type") (print "dollarhex"))) - -(define-operand (name mask) (comment "mask") (attrs) - (type h-uint) (index f-mask) (handlers (print "dollarhex"))) - -(define-operand (name bankaddr) (comment "bank address") (attrs) - (type h-uint) (index f-bankaddr) (handlers (print "dollarhex"))) - -(define-operand (name incamt) (comment "increment amount") (attrs) - (type h-uint) (index f-incamt) (handlers (print "dollarhex"))) - -(define-operand (name xmode) (comment "xmode") (attrs) - (type h-uint) (index f-xmode) (handlers (parse "xmode") (print "dollarhex"))) - -(define-operand (name mask1) (comment "mask1") (attrs) - (type h-uint) (index f-mask1) (handlers (print "dollarhex"))) - -(define-operand (name ball) (comment "b_all") (attrs) - (type h-uint) (index f-ball) (handlers (parse "ball") (print "dollarhex"))) - -(define-operand (name brc) (comment "b_r_c") (attrs) - (type h-uint) (index f-brc) (handlers (print "dollarhex"))) - -(define-operand (name rda) (comment "rd") (attrs) - (type h-uint) (index f-rda) (handlers (print "dollarhex"))) - -(define-operand (name wr) (comment "wr") (attrs) - (type h-uint) (index f-wr) (handlers (print "dollarhex"))) - -(define-operand (name ball2) (comment "b_all2") (attrs) - (type h-uint) (index f-ball2) (handlers (parse "ball") (print "dollarhex"))) - -(define-operand (name brc2) (comment "b_r_c2") (attrs) - (type h-uint) (index f-brc2) (handlers (print "dollarhex"))) -(define-operand (name perm) (comment "perm") (attrs) - (type h-uint) (index f-perm) (handlers (print "dollarhex"))) -(define-operand (name a23) (comment "a23") (attrs) - (type h-uint) (index f-a23) (handlers (print "dollarhex"))) -(define-operand (name cr) (comment "c-r") (attrs) - (type h-uint) (index f-cr) (handlers (print "dollarhex"))) -(define-operand (name cbs) (comment "cbs") (attrs) - (type h-uint) (index f-cbs) (handlers (print "dollarhex"))) -(define-operand (name incr) (comment "incr") (attrs) - (type h-uint) (index f-incr) (handlers (print "dollarhex"))) -(define-operand (name length) (comment "length") (attrs) - (type h-uint) (index f-length) (handlers (print "dollarhex"))) -(define-operand (name cbx) (comment "cbx") (attrs) - (type h-uint) (index f-cbx) (handlers (print "dollarhex"))) -(define-operand (name ccb) (comment "ccb") (attrs) - (type h-uint) (index f-ccb) (handlers (print "dollarhex"))) -(define-operand (name cdb) (comment "cdb") (attrs) - (type h-uint) (index f-cdb) (handlers (print "dollarhex"))) - -; For the INTLVR insn -(define-operand (name mode) (comment "mode") (attrs) - (type h-uint) (index f-mode) (handlers (print "dollarhex"))) -(define-operand (name id) (comment "i/d") (attrs) - (type h-uint) (index f-id) (handlers (print "dollarhex"))) -(define-operand (name size) (comment "size") (attrs) - (type h-uint) (index f-size) (handlers (print "dollarhex"))) - -(define-operand (name fbincr) (comment "fb incr") (attrs) - (type h-uint) (index f-fbincr) (handlers (print "dollarhex"))) - -; For the ms2 insns -(define-operand (name loopsize) (comment "immediate value") - (attrs (MACH ms2) PCREL-ADDR) - (type h-uint) (index f-loopo) (handlers (parse "loopsize") (print "pcrel"))) -(define-operand (name imm16l) (comment "immediate value") - (attrs (MACH ms2)) - (type h-uint) (index f-imm16l) (handlers (print "dollarhex"))) -(define-operand (name rc3) (comment "rc3") (attrs (MACH ms2)) - (type h-uint) (index f-rc3) (handlers (parse "rc") (print "dollarhex"))) -(define-operand (name cb1sel) (comment "cb1sel") (attrs (MACH ms2)) - (type h-uint) (index f-cb1sel) (handlers (print "dollarhex"))) -(define-operand (name cb2sel) (comment "cb2sel") (attrs (MACH ms2)) - (type h-uint) (index f-cb2sel) (handlers (print "dollarhex"))) -(define-operand (name cb1incr) (comment "cb1incr") (attrs (MACH ms2)) - (type h-sint) (index f-cb1incr) (handlers (print "dollarhex"))) -(define-operand (name cb2incr) (comment "cb2incr") (attrs (MACH ms2)) - (type h-sint) (index f-cb2incr) (handlers (print "dollarhex"))) - -; Probaby won't need most of these. -(define-pmacro r0 (reg h-spr #x0)) -(define-pmacro r1 (reg h-spr #x01)) -(define-pmacro r2 (reg h-spr #x02)) -(define-pmacro r3 (reg h-spr #x03)) -(define-pmacro r4 (reg h-spr #x04)) -(define-pmacro r5 (reg h-spr #x05)) -(define-pmacro r6 (reg h-spr #x06)) -(define-pmacro r7 (reg h-spr #x07)) -(define-pmacro r8 (reg h-spr #x08)) -(define-pmacro r9 (reg h-spr #x09)) -(define-pmacro r10 (reg h-spr #xA)) -(define-pmacro r11 (reg h-spr #xB)) -(define-pmacro r12 (reg h-spr #xC)) -(define-pmacro fp (reg h-spr #xC)) -(define-pmacro r13 (reg h-spr #xD)) -(define-pmacro sp (reg h-spr #xD)) -(define-pmacro r14 (reg h-spr #xE)) -(define-pmacro ra (reg h-spr #xE)) -(define-pmacro r15 (reg h-spr #xF)) -(define-pmacro ira (reg h-spr #xF)) - -; delayed set -(define-pmacro (dset dest src) (set (delay 1 dest) src)) - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; Instructions As Defined In the MorphoRisc ISA Document ;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - -; Arithmetic Instructions - -(dni add "ADD DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "add $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_ADD IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (add SI frsr1 frsr2)) - () -) - -(dni addu "ADDU DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "addu $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_ADDU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (add USI frsr1 frsr2)) - () -) - -(dni addi "ADDI DstReg, SrcReg1 UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "addi $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_ADD IMM_YES frsr1 frdr imm16) - (sequence((HI tmp)) - (set HI tmp (and imm16 #xffff)) - (set frdr (add SI frsr1 (ext SI tmp))) - ) - () -) - -(dni addui "ADDUI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "addui $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_ADDU IMM_YES frsr1 frdr imm16z) - (set frdr (add USI frsr1 (ext USI imm16z))) - () -) - -(dni sub "SUB DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "sub $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_SUB IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (sub SI frsr1 frsr2)) - () -) - -(dni subu "SUBU DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "subu $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_SUBU IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (sub USI frsr1 frsr2)) - () -) - -(dni subi "SUBI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "subi $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_SUB IMM_YES frsr1 frdr imm16) - (sequence((HI tmp)) - (set HI tmp (and imm16 #xffff)) - (set frdr (sub SI frsr1 (ext SI tmp))) - ) - ;(set frdr (sub SI frsr1 (ext SI imm16))) - () -) - -(dni subui "SUBUI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "subui $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_SUBU IMM_YES frsr1 frdr imm16z) - (set frdr (sub USI frsr1 (ext USI imm16z))) - () -) - -(dni mul "MUL DstReg, SrcReg1, SrcReg2" - ((MACH ms1-003,ms2) AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "mul $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_MUL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (sequence((HI op1) (HI op2)) - (set op1 (and frsr1 #xffff)) - (if (or (lt op1 (const -32768)) (gt op1 (const 32767))) - (error "operand out of range") - ) - (set op2 (and frsr2 #xffff)) - (if (or (lt op2 (const -32768)) (gt op2 (const 32767))) - (error "operand out of range") - ) - (set frdrrr (mul SI (ext SI op1) (ext SI op2))) - ) - () -) - -(dni muli "MULI DstReg, SrcReg1, UnsImm" - ((MACH ms1-003,ms2) AL-INSN USES-FRDR USES-FRSR1) - "muli $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_MUL IMM_YES frsr1 frdr imm16) - (sequence((HI op1) (HI op2)) - (set op1 (and frsr1 #xffff)) - (if (or (lt op1 (const -32768)) (gt op1 (const 32767))) - (error "operand out of range") - ) - (set op2 (and imm16 #xffff)) - (if (eq op1 (const 0)) - (error "op1 is 0") - ) - (if (eq op2 (const 0)) - (error "op2 is 0") - ) - (set frdr (mul SI (ext SI op1) (ext SI op2))) - ) - () -) - -; Logical Instructions - -(dni and "AND DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "and $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_AND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (and frsr1 frsr2)) - () -) - -(dni andi "ANDI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "andi $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_AND IMM_YES frsr1 frdr imm16z) - (set frdr (and frsr1 (ext USI imm16z))) - () -) - -(dni or "OR DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "or $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_OR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (or frsr1 frsr2)) - () -) - -(dni nop "nop" - () - "nop" - (+ MSYS_NO OPC_OR IMM_NO (f-uu24 0)) - (nop) - () -) - -(dni ori "ORI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "ori $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_OR IMM_YES frsr1 frdr imm16z) - (set frdr (or frsr1 (ext USI imm16z))) - () -) - -(dni xor "XOR DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "xor $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_XOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (xor frsr1 frsr2)) - () -) - -(dni xori "XORI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "xori $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_XOR IMM_YES frsr1 frdr imm16z) - (set frdr (xor frsr1 (ext USI imm16z))) - () -) - -(dni nand "NAND DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "nand $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_NAND IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (inv (and frsr1 frsr2))) - () -) - -(dni nandi "NANDI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "nandi $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_NAND IMM_YES frsr1 frdr imm16z) - (set frdr (inv (and frsr1 (ext USI imm16z)))) - () -) - -(dni nor "NOR DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "nor $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_NOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (inv (or frsr1 frsr2))) - () -) - -(dni nori "NORI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "nori $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_NOR IMM_YES frsr1 frdr imm16z) - (set frdr (inv (or frsr1 (ext USI imm16z)))) - () -) - -(dni xnor "XNOR DstReg, SrcReg1, SrcReg2" - (AL-INSN USES-FRDRRR USES-FRSR1 USES-FRSR2) - "xnor $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_XNOR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (inv (xor frsr1 frsr2))) - () -) - -(dni xnori "XNORI DstReg, SrcReg1, UnsImm" - (AL-INSN USES-FRDR USES-FRSR1) - "xnori $frdr,$frsr1,#$imm16z" - (+ MSYS_NO OPC_XNOR IMM_YES frsr1 frdr imm16z) - (set frdr (inv (xor frsr1 (ext USI imm16z)))) - () -) - -(dni ldui "LDUI DstReg, UnsImm" - (AL-INSN USES-FRDR) - "ldui $frdr,#$imm16z" - (+ MSYS_NO OPC_LDUI IMM_YES (f-uu4b 0) frdr imm16z) - (set frdr (and (sll imm16z 16) #xffff0000)) - () -) - -; Shift Instructions - -(dni lsl "LSL DstReg, SrcReg1, SrcReg2" - (USES-FRDRRR USES-FRSR1 USES-FRSR2) - "lsl $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_LSL IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (sll frsr1 frsr2)) - () -) - -(dni lsli "LSLI DstReg, SrcReg1, UnsImm" - (USES-FRDR USES-FRSR1) - "lsli $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_LSL IMM_YES frsr1 frdr imm16) - (set frdr (sll frsr1 imm16)) - () -) - -(dni lsr "LSR DstReg, SrcReg1, SrcReg2" - (USES-FRDRRR USES-FRSR1 USES-FRSR2) - "lsr $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_LSR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (srl frsr1 frsr2)) - () -) - -(dni lsri "LSRI DstReg, SrcReg1, UnsImm" - (USES-FRDR USES-FRSR1) - "lsri $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_LSR IMM_YES frsr1 frdr imm16) - (set frdr (srl frsr1 imm16)) - () -) - -(dni asr "ASR DstReg, SrcReg1, SrcReg2" - (USES-FRDRRR USES-FRSR1 USES-FRSR2) - "asr $frdrrr,$frsr1,$frsr2" - (+ MSYS_NO OPC_ASR IMM_NO frsr1 frsr2 frdrrr (f-uu12 0)) - (set frdrrr (sra frsr1 frsr2)) - () -) - -(dni asri "ASRI DstReg, SrcReg1, UnsImm" - (USES-FRDR USES-FRSR1) - "asri $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_ASR IMM_YES frsr1 frdr imm16) - (set frdr (sra frsr1 imm16)) - () -) - -; Control Transfer Instructions - -(dni brlt "BRLT SrcReg1, SrcReg2, label" - (BR-INSN DELAY-SLOT USES-FRDRRR USES-FRSR1 USES-FRSR2) - "brlt $frsr1,$frsr2,$imm16o" - (+ MSYS_NO OPC_BRLT IMM_YES frsr1 frsr2 imm16o) - (sequence() - (if (lt USI frsr1 frsr2) - (dset pc (add pc (ext SI imm16o)))) - ) - () -) - -(dni brle "BRLE SrcReg1, SrcReg2, label" - (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2) - "brle $frsr1,$frsr2,$imm16o" - (+ MSYS_NO OPC_BRLE IMM_YES frsr1 frsr2 imm16o) - (sequence() - (if (le USI frsr1 frsr2) - (dset pc (add pc (ext SI imm16o)))) - ) - () -) - -(dni breq "BREQ SrcReg1, SrcReg2, label" - (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2) - "breq $frsr1,$frsr2,$imm16o" - (+ MSYS_NO OPC_BREQ IMM_YES frsr1 frsr2 imm16o) - (sequence() - (if (eq USI frsr1 frsr2) - (dset pc (add pc (ext SI imm16o)))) - ) - () -) - -(dni brne "BRNE SrcReg1, SrcReg2, label" - (BR-INSN DELAY-SLOT USES-FRSR1 USES-FRSR2) - "brne $frsr1,$frsr2,$imm16o" - (+ MSYS_NO OPC_BRNEQ IMM_YES frsr1 frsr2 imm16o) - (sequence() - (if (not (eq USI frsr1 frsr2)) - (dset pc (add pc (ext SI imm16o)))) - ) - () -) - -(dni jmp "JMP, label" - (DELAY-SLOT BR-INSN) - "jmp $imm16o" - (+ MSYS_NO OPC_JMP IMM_YES (f-uu4b 0) (f-uu4a 0) imm16o) - (dset pc (add pc (ext SI imm16o))) - () -) - -(dni jal "JAL DstReg, SrcReg1" - (BR-INSN DELAY-SLOT BR-INSN USES-FRDR USES-FRSR1 JAL-HAZARD) - "jal $frdrrr,$frsr1" - (+ MSYS_NO OPC_JAL IMM_NO frsr1 (f-uu4a 0) frdrrr (f-uu12 0)) - (sequence() - (if (eq frsr1 #x0) - (c-call VOID "do_syscall" pc) - (sequence() ; else part. Do non-syscall stuff here. - (dset frdrrr (add pc #x8)) - (dset pc frsr1) - ) - ) - ) - () -) - -(dni dbnz "DBNZ SrcReg1, label" - ((MACH ms1-003,ms2) BR-INSN DELAY-SLOT USES-FRSR1) - "dbnz $frsr1,$imm16o" - (+ MSYS_NO OPC_DBNZ IMM_YES frsr1 (f-uu4a 0) imm16o) - (sequence() - (if (not (eq USI frsr1 0)) - (dset pc (add pc (ext SI imm16o)))) - ) - () -) - -; Interrupt Control Instructions - -(dni ei "EI - Enable Interrupt Processing" - () - "ei" - (+ MSYS_NO OPC_EI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0)) - (c-call VOID "enable_interrupts") - () -) - -(dni di "DI - Disable Interrupt Processing" - () - "di" - (+ MSYS_NO OPC_DI IMM_NO (f-uu4b 0) (f-uu4a 0) (f-uu16 0)) - (c-call VOID "disable_interrupts") - () -) - -(dni si "SI - Send software Interrupt" - (DELAY-SLOT BR-INSN USES-FRDR) - "si $frdrrr" - (+ MSYS_NO OPC_SI IMM_NO (f-uu4b 0) (f-uu4a 0) frdrrr (f-uu12 0)) - ;(sequence() - ; (dset frdr (add pc #x4)) - ; (c-call VOID "do_syscall1" pc) - ; ; (dset pc frsr1) Do this later when we have the address. - ;) - (sequence() - (set frdrrr (add pc #x4)) - (c-call VOID "do_syscall" pc) - ; (set pc frsr1) Do this later when we have the address. - ) - () -) - -(dni reti "RETI SrcReg1" - (DELAY-SLOT BR-INSN USES-FRSR1 JAL-HAZARD) - "reti $frsr1" - (+ MSYS_NO OPC_RETI IMM_NO frsr1 (f-uu4a 0) (f-uu16 0)) - (sequence() - (c-call VOID "enable_interrupts") - (dset pc frsr1) - ) - () -) - -; Memory Access Instructions - -(dni ldw "LDW DstReg, SrcReg1, Imm" - (LOAD-DELAY MEMORY-ACCESS USES-FRDR USES-FRSR1) - "ldw $frdr,$frsr1,#$imm16" - (+ MSYS_NO OPC_LDW IMM_YES frsr1 frdr imm16) - (sequence((USI ea) (HI tmp)) - (set HI tmp (and imm16 #xffff)) - (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc)) - (set frdr (mem SI ea)) - ) - () -) - -(dni stw "STW SrcReg2, SrcReg1, Imm" - (MEMORY-ACCESS USES-FRSR1 USES-FRSR2) - "stw $frsr2,$frsr1,#$imm16" - (+ MSYS_NO OPC_STW IMM_YES frsr1 frsr2 imm16) - (sequence((USI ea) (HI tmp)) - (set HI tmp (and imm16 #xffff)) - (set ea (and (add SI frsr1 (ext SI tmp)) #xfffffffc)) - (set (mem SI ea) frsr2) - ) - () -) - -; Break Instruction - -(dni break "BREAK" - () - "break" - (+ MSYS_NO OPC_BREAK (f-imm 0) (f-uu24 0)) - (c-call VOID "do_break" pc) - () -) - -; Cache Flush Instruction - -(dni iflush "IFLUSH" - ((MACH ms1-003,ms2)) - "iflush" - (+ MSYS_NO OPC_IFLUSH (f-imm 0) (f-uu24 0)) - (nop) - () -) - -; MorphoSys Instructions - -(dni ldctxt "LDCTXT SRC1, SRC2, r/c, r/c#, context#" - ((MACH ms1)) - "ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum" - (+ MSYS_YES MSOPC_LDCTXT (f-uu-2-25 0) frsr1 frsr2 rc rcnum (f-uu-3-11 0) - contnum ) - (nop) - () -) - -(dni ldfb "LDFB SRC1, byte#" - ((MACH ms1)) - "ldfb $frsr1,$frsr2,#$imm16z" - (+ MSYS_YES MSOPC_LDFB (f-uu-2-25 0) frsr1 frsr2 imm16z) - (nop) - () -) - -(dni stfb "STFB SRC1, SRC2, byte " - ((MACH ms1)) - "stfb $frsr1,$frsr2,#$imm16z" - (+ MSYS_YES MSOPC_STFB (f-uu-2-25 0) frsr1 frsr2 imm16z) - (nop) - () -) - -(dni fbcb "FBCB SRC1, RT/BR1/BR2/CS, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp" - ((MACH ms1,ms1-003)) - "fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCB rbbc frsr1 ball brc (f-uu-4-15 0) rc cbrb cell dup ctxdisp) - (nop) - () -) - -(dni mfbcb "MFBCB SRC1, RT/BR1/BR2/CS, SRC2, r/c, CB/RB, cell, dup, ctx_disp" - () - "mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBCB rbbc frsr1 frsr2 (f-uu-4-15 0) rc1 cbrb cell dup ctxdisp) - (nop) - () -) - -(dni fbcci "FBCCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" - () - "fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni fbrci "FBRCI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" - () - "fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBRCI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni fbcri "FBCRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" - () - "fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni fbrri "FBRRI SRC1, RT/BR1/BR2/CS, B_all, B_r_c, FB_disp, cell, dup, ctx_disp" - () - "fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBRRI rbbc frsr1 ball brc fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni mfbcci "MFBCCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" - () - "mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBCCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni mfbrci "MFBRCI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" - () - "mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBRCI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni mfbcri "MFBCRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" - () - "mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBCRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni mfbrri "MFBRRI SRC1, RT/BR1/BR2/CS, SRC2, FB_disp, cell, dup, ctx_disp" - () - "mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBRRI rbbc frsr1 frsr2 fbdisp cell dup ctxdisp) - (nop) - () -) - -(dni fbcbdr "FBCBDR SRC1, RT/BR1/BR2/CS, SRC2, B_all, B_r_c, r/c, CB/RB, cell, dup, ctx_disp" - () - "fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCBDR rbbc frsr1 frsr2 ball2 brc2 rc1 cbrb cell dup ctxdisp) - (nop) - () -) - -(dni rcfbcb "RCFBCB RT/BR1/BR2/CS, type, B_all, B_r_c, row#, r/c, CB/RB, cell, dup, ctx_disp" - () - "rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_RCFBCB rbbc (f-uu-2-23 0) type ball brc (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp) - (nop) - () -) - -(dni mrcfbcb "MRCFBCB SRC2, RT/BR1/BR2/CS, type, row#, r/c, CB/RB, cell, dup, ctx_disp" - () - "mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MRCFBCB rbbc (f-uu-2-23 0) type frsr2 (f-uu-1-15 0) rownum rc1 cbrb cell dup ctxdisp) - (nop) - () -) - -(dni cbcast "CBCAST mask, r/c, ctx_disp " - () - "cbcast #$mask,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_CBCAST mask (f-uu-3-9 0) rc2 ctxdisp) - (nop) - () -) - -(dni dupcbcast "DUPCBCAST mask, cell, r/c, ctx_disp " - () - "dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_DUPCBCAST mask cell rc2 ctxdisp) - (nop) - () -) - -(dni wfbi "WFBI Bank_address, row#, cell, dup, ctx_disp " - () - "wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_WFBI bankaddr rownum1 cell dup ctxdisp) - (nop) - () -) - -;(dni wfb "WFB SRC1, SRC2, FB_disp, row#, ctx_disp" -; () -; "wfb $frsr1,$frsr2,#$fbdisp,#$rownum,#$ctxdisp" -; (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum (f-uu-1-6 0) ctxdisp) -; (nop) -; () -;) - -(dni wfb "WFB, DRC1,SRC2,FB_disp,row#,ctx_disp" - () - "wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp" - (+ MSYS_YES MSOPC_WFB (f-uu-2-25 0) frsr1 frsr2 fbdisp rownum2 (f-uu-1-6 0) ctxdisp) - (nop) - () -) - - -(dni rcrisc "RCRISC DEST, RT/BR1/BR2/CS, SRC1, column#, r/c, CB/RB, cell, dup, ctx_disp" - () - "rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_RCRISC rbbc frsr1 (f-uu-1-19 0) colnum frdrrr rc1 cbrb cell dup ctxdisp) - (nop) - () -) - -(dni fbcbinc "FBCBINC SRC1, RT/BR1/BR2/CS, Incr_amount, r/c, CB/RB, cell, dup, ctx_disp " - () - "fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCBINC rbbc frsr1 incamt rc1 cbrb cell dup ctxdisp) - (nop) - () -) - -(dni rcxmode "RCXMODE SRC2, rd, wr, xmode, mask, FB_disp, row#, r/c, ctx_disp" - () - "rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_RCXMODE rda wr xmode mask1 frsr2 fbdisp rownum2 rc2 ctxdisp) - (nop) - () -) - -(dni interleaver "INTLVR ireg, mode, ireg, i/d, size" - () - "intlvr $frsr1,#$mode,$frsr2,#$id,#$size" - (+ MSYS_YES MSOPC_INTLVR mode frsr1 frsr2 (f-uu-1-15 0) id size) - (nop) - () -) - -;; Issue 66262: The documenatation gives the wrong order for -;; the arguments to the WFBINC instruction. -(dni wfbinc "WFBINC type, ccb/rcb, incr, all, c/r, length, rca_row, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_WFBINC rda wr fbincr ball colnum length rownum1 rownum2 dup ctxdisp) - (nop) - () -) - -(dni mwfbinc "MWFBINC mreg, type, ccb/rcb, incr, length, rca_row, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MWFBINC rda wr fbincr frsr2 length rownum1 rownum2 dup ctxdisp) - (nop) - () -) - -(dni wfbincr "WFBINCR ireg, type, ccb/rcb, all, c/r, length, rca_row, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_WFBINCR rda wr frsr1 ball colnum length rownum1 rownum2 dup ctxdisp) - (nop) - () -) - -(dni mwfbincr "MWFBINCR ireg, mreg, type, ccb/rcb, length, rca_row, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MWFBINCR rda wr frsr1 frsr2 length rownum1 rownum2 dup ctxdisp) - (nop) - () -) - -(dni fbcbincs "FBCBINCS perm, all, c/r, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCBINCS perm a23 cr cbs incr ccb cdb rownum2 dup ctxdisp) - (nop) - () -) - -(dni mfbcbincs "MFBCBINCS ireg, perm, cbs, incr, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBCBINCS perm frsr1 cbs incr ccb cdb rownum2 dup ctxdisp) - (nop) - () -) - -(dni fbcbincrs "FBCBINCRS ireg, perm, all, c/r, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCBINCRS perm frsr1 ball colnum (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp) - (nop) - () -) - -(dni mfbcbincrs "MFBCBINCRS ireg, mreg, perm, cbs, ccb/rcb, cdb/rdb, word, dup, ctxt_disp" - ((MACH ms1-003,ms2)) - "mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp" - (+ MSYS_YES MSOPC_MFBCBINCRS perm frsr1 frsr2 (f-uu-1-15 0) cbx ccb cdb rownum2 dup ctxdisp) - (nop) - () -) - -; MS2 instructions -(dni loop "LOOP SrcReg1, label" - ((MACH ms2) DELAY-SLOT USES-FRSR1) - "loop $frsr1,$loopsize" - (+ MSYS_NO OPC_LOOP IMM_NO frsr1 (f-uu4a 0) (f-uu8 0) loopsize) - (nop) ;; to be filled in - () -) - -(dni loopi "LOOPI niter, label" - ((MACH ms2) DELAY-SLOT) - "loopi #$imm16l,$loopsize" - (+ MSYS_NO OPC_LOOP IMM_YES imm16l loopsize) - (nop) ;; to be filled in - () -) - -(dni dfbc "dfbc cb1sel,cb2sel,cb1inc,cb2inc,dr/c,cr/c,ctxdisp" - ((MACH ms2)) - "dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_LDCTXT cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp) - (nop) - () -) - -(dni dwfb "dwfb cb1sel,cb2sel,cb1inc,cb2inc,cr/c,ctxdisp" - ((MACH ms2)) - "dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_LDFB cb1sel cb2sel cb1incr cb2incr (f-uu1 0) rc2 ctxdisp) - (nop) - () -) - -(dni fbwfb "fbwfb cb1sel,cb2sel,cb1inc,cb2inc,r0/1,cr/c,ctxdisp" - ((MACH ms2)) - "fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_STFB cb1sel cb2sel cb1incr cb2incr rc3 rc2 ctxdisp) - (nop) - () -) - -(dni dfbr "dfbr cb1sel,cb2sel,reg,W/O1,W/O2,mode,cr/c,ctxdisp" - ((MACH ms2) USES-FRSR2) - "dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp" - (+ MSYS_YES MSOPC_FBCB cb1sel cb2sel frsr2 length rownum1 rownum2 rc2 ctxdisp) - (nop) - () -) diff --git a/binutils-2.24/cpu/mt.opc b/binutils-2.24/cpu/mt.opc deleted file mode 100644 index d988cc25..00000000 --- a/binutils-2.24/cpu/mt.opc +++ /dev/null @@ -1,472 +0,0 @@ -/* Morpho Technologies mRISC opcode support, for GNU Binutils. -*- C -*- - Copyright 2001, 2007, 2008, 2009, 2012 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; developed under contract from - Morpho Technologies. - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h" */ - -/* -- opc.h */ - -/* Check applicability of instructions against machines. */ -#define CGEN_VALIDATE_INSN_SUPPORTED - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Override disassembly hashing - there are variable bits in the top - byte of these instructions. */ -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf, value) (((* (unsigned char *) (buf)) >> 5) % CGEN_DIS_HASH_SIZE) - -#define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(insn) mt_asm_hash (insn) - -extern unsigned int mt_asm_hash (const char *); - -extern int mt_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); - - -/* -- opc.c */ -#include "safe-ctype.h" - -/* Special check to ensure that instruction exists for given machine. */ - -int -mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) -{ - int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - - /* No mach attribute? Assume it's supported for all machs. */ - if (machs == 0) - return 1; - - return ((machs & cd->machs) != 0); -} - -/* A better hash function for instruction mnemonics. */ - -unsigned int -mt_asm_hash (const char* insn) -{ - unsigned int hash; - const char* m = insn; - - for (hash = 0; *m && ! ISSPACE (*m); m++) - hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); - - /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ - - return hash % CGEN_ASM_HASH_SIZE; -} - - -/* -- asm.c */ -/* Range checking for signed numbers. Returns 0 if acceptable - and 1 if the value is out of bounds for a signed quantity. */ - -static int -signed_out_of_bounds (long val) -{ - if ((val < -32768) || (val > 32767)) - return 1; - return 0; -} - -static const char * -parse_loopsize (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - void *arg) -{ - signed long * valuep = (signed long *) arg; - const char *errmsg; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - enum cgen_parse_operand_result result_type; - bfd_vma value; - - /* Is it a control transfer instructions? */ - if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_LOOPSIZE) - { - code = BFD_RELOC_MT_PCINSN8; - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - *valuep = value; - return errmsg; - } - - abort (); -} - -static const char * -parse_imm16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - void *arg) -{ - signed long * valuep = (signed long *) arg; - const char *errmsg; - enum cgen_parse_operand_result result_type; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - /* Is it a control transfer instructions? */ - if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16O) - { - code = BFD_RELOC_16_PCREL; - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if (errmsg == NULL) - { - if (signed_out_of_bounds (value)) - errmsg = _("Operand out of range. Must be between -32768 and 32767."); - } - *valuep = value; - return errmsg; - } - - /* If it's not a control transfer instruction, then - we have to check for %OP relocating operators. */ - if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16L) - ; - else if (strncmp (*strp, "%hi16", 5) == 0) - { - *strp += 5; - code = BFD_RELOC_HI16; - } - else if (strncmp (*strp, "%lo16", 5) == 0) - { - *strp += 5; - code = BFD_RELOC_LO16; - } - - /* If we found a %OP relocating operator, then parse it as an address. - If not, we need to parse it as an integer, either signed or unsigned - depending on which operand type we have. */ - if (code != BFD_RELOC_NONE) - { - /* %OP relocating operator found. */ - errmsg = cgen_parse_address (cd, strp, opindex, code, - & result_type, & value); - if (errmsg == NULL) - { - switch (result_type) - { - case (CGEN_PARSE_OPERAND_RESULT_NUMBER): - if (code == BFD_RELOC_HI16) - value = (value >> 16) & 0xFFFF; - else if (code == BFD_RELOC_LO16) - value = value & 0xFFFF; - else - errmsg = _("Biiiig Trouble in parse_imm16!"); - break; - - case (CGEN_PARSE_OPERAND_RESULT_QUEUED): - /* No special processing for this case. */ - break; - - default: - errmsg = _("The percent-operator's operand is not a symbol"); - break; - } - } - *valuep = value; - } - else - { - /* Parse hex values like 0xffff as unsigned, and sign extend - them manually. */ - int parse_signed = (opindex == (CGEN_OPERAND_TYPE)MT_OPERAND_IMM16); - - if ((*strp)[0] == '0' - && ((*strp)[1] == 'x' || (*strp)[1] == 'X')) - parse_signed = 0; - - /* No relocating operator. Parse as an number. */ - if (parse_signed) - { - /* Parse as as signed integer. */ - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, valuep); - - if (errmsg == NULL) - { -#if 0 - /* Manual range checking is needed for the signed case. */ - if (*valuep & 0x8000) - value = 0xffff0000 | *valuep; - else - value = *valuep; - - if (signed_out_of_bounds (value)) - errmsg = _("Operand out of range. Must be between -32768 and 32767."); - /* Truncate to 16 bits. This is necessary - because cgen will have sign extended *valuep. */ - *valuep &= 0xFFFF; -#endif - } - } - else - { - /* MT_OPERAND_IMM16Z. Parse as an unsigned integer. */ - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep); - - if (opindex == (CGEN_OPERAND_TYPE) MT_OPERAND_IMM16 - && *valuep >= 0x8000 - && *valuep <= 0xffff) - *valuep -= 0x10000; - } - } - - return errmsg; -} - - -static const char * -parse_dup (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0) - { - *strp += 3; - *valuep = 1; - } - else if (strncmp (*strp, "xx", 2) == 0 || strncmp (*strp, "XX", 2) == 0) - { - *strp += 2; - *valuep = 0; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - return errmsg; -} - - -static const char * -parse_ball (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "all", 3) == 0 || strncmp (*strp, "ALL", 3) == 0) - { - *strp += 3; - *valuep = 1; - } - else if (strncmp (*strp, "one", 3) == 0 || strncmp (*strp, "ONE", 3) == 0) - { - *strp += 3; - *valuep = 0; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - return errmsg; -} - -static const char * -parse_xmode (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "pm", 2) == 0 || strncmp (*strp, "PM", 2) == 0) - { - *strp += 2; - *valuep = 1; - } - else if (strncmp (*strp, "xm", 2) == 0 || strncmp (*strp, "XM", 2) == 0) - { - *strp += 2; - *valuep = 0; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - return errmsg; -} - -static const char * -parse_rc (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "r", 1) == 0 || strncmp (*strp, "R", 1) == 0) - { - *strp += 1; - *valuep = 1; - } - else if (strncmp (*strp, "c", 1) == 0 || strncmp (*strp, "C", 1) == 0) - { - *strp += 1; - *valuep = 0; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - return errmsg; -} - -static const char * -parse_cbrb (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "rb", 2) == 0 || strncmp (*strp, "RB", 2) == 0) - { - *strp += 2; - *valuep = 1; - } - else if (strncmp (*strp, "cb", 2) == 0 || strncmp (*strp, "CB", 2) == 0) - { - *strp += 2; - *valuep = 0; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - return errmsg; -} - -static const char * -parse_rbbc (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "rt", 2) == 0 || strncmp (*strp, "RT", 2) == 0) - { - *strp += 2; - *valuep = 0; - } - else if (strncmp (*strp, "br1", 3) == 0 || strncmp (*strp, "BR1", 3) == 0) - { - *strp += 3; - *valuep = 1; - } - else if (strncmp (*strp, "br2", 3) == 0 || strncmp (*strp, "BR2", 3) == 0) - { - *strp += 3; - *valuep = 2; - } - else if (strncmp (*strp, "cs", 2) == 0 || strncmp (*strp, "CS", 2) == 0) - { - *strp += 2; - *valuep = 3; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - return errmsg; -} - -static const char * -parse_type (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg = NULL; - - if (strncmp (*strp, "odd", 3) == 0 || strncmp (*strp, "ODD", 3) == 0) - { - *strp += 3; - *valuep = 0; - } - else if (strncmp (*strp, "even", 4) == 0 || strncmp (*strp, "EVEN", 4) == 0) - { - *strp += 4; - *valuep = 1; - } - else if (strncmp (*strp, "oe", 2) == 0 || strncmp (*strp, "OE", 2) == 0) - { - *strp += 2; - *valuep = 2; - } - else - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - - if ((errmsg == NULL) && (*valuep == 3)) - errmsg = _("invalid operand. type may have values 0,1,2 only."); - - return errmsg; -} - -/* -- dis.c */ -static void print_dollarhex (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); -static void print_pcrel (CGEN_CPU_DESC, PTR, long, unsigned, bfd_vma, int); - -static void -print_dollarhex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "$%lx", value & 0xffffffff); - - if (0) - print_normal (cd, dis_info, value, attrs, pc, length); -} - -static void -print_pcrel (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - print_address (cd, dis_info, value + pc, attrs, pc, length); -} - -/* -- */ - - - - - diff --git a/binutils-2.24/cpu/openrisc.cpu b/binutils-2.24/cpu/openrisc.cpu deleted file mode 100644 index 17cc313d..00000000 --- a/binutils-2.24/cpu/openrisc.cpu +++ /dev/null @@ -1,774 +0,0 @@ -; OpenRISC family. -*- Scheme -*- -; Copyright 2000, 2001, 2011 Free Software Foundation, Inc. -; Contributed by Johan Rydberg, jrydberg@opencores.org -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. - -(include "simplify.inc") - -; OpenRISC 1000 is an architecture of a family of open source, -; synthesizeable RISC microprocessor cores. It is a 32-bit load -; and store RISC architecture designed with emphasis on speed, -; compact instruction set and scalability. OpenRISC 1000 targets -; wide range of embedded environments. - -(define-arch - (name openrisc) - (comment "OpenRISC 1000") - (insn-lsb0? #t) - (machs openrisc or1300) - (isas or32) -) - - -; Attributes - -; An attribute to describe if a model has insn and/or data caches. -(define-attr - (for model) - (type enum) - (name HAS-CACHE) - (comment "if this model has caches") - (values DATA-CACHE INSN-CACHE) -) - -; An attribute to describe if an insn can be in the delay slot or not. -(define-attr - (for insn) - (type boolean) - (name NOT-IN-DELAY-SLOT) - (comment "insn can't go in delay slot") -) - -; IDOC attribute for instruction documentation. - -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MEM - () "Memory") - (ALU - () "ALU") - (FPU - () "FPU") - (BR - () "Branch") - (PRIV - () "Priviledged") - (MISC - () "Miscellaneous") - ) -) - -; Enum for exception vectors. -(define-enum - (name e-exception) - (comment "exception vectors") - (attrs) - (prefix E_) - (values (("RESET") ("BUSERR" -) ("DPF" -) ("IPF" -) ("EXTINT" -) ("ALIGN" -) - ("ILLEGAL" -) ("PEINT" -) ("DTLBMISS" -) ("ITLBMISS" -) ("RRANGE" -) - ("SYSCALL" -) ("BREAK" -) ("RESERVED" -))) -) - - -; Instruction set parameters. - -(define-isa - ; Name of the ISA. - (name or32) - - ; Base insturction length. The insns is always 32 bits wide. - (base-insn-bitsize 32) - - ; Address of insn in delay slot - (setup-semantics (set-quiet (reg h-delay-insn) (add pc 4))) -) - - -; CPU family definitions. - -(define-cpu - ; CPU names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name openriscbf) - (comment "OpenRISC base family") - (endian big) - (word-bitsize 32) -) - -; Generic machine -(define-mach - (name openrisc) - (comment "Generic OpenRISC cpu") - (cpu openriscbf) - (bfd-name "openrisc") -) - -; OpenRISC 1300 machine -(define-mach - (name or1300) - (comment "OpenRISC 1300") - (cpu openriscbf) - (bfd-name "openrisc:1300") -) - - -; Model descriptions - -; Generic OpenRISC model -(define-model - (name openrisc-1) (comment "OpenRISC generic model") (attrs) - (mach openrisc) - - ; Nothing special about this. - (unit u-exec "Execution Unit" () 1 1 () () () ()) -) - -; OpenRISC 1320 -(define-model - (name or1320-1) (comment "OpenRISC 1320 model") - - ; This model has both instruction and data cache - (attrs (HAS-CACHE INSN-CACHE,DATA-CACHE)) - (mach or1300) - - ; Nothing special about this. - (unit u-exec "Execution Unit" () 1 1 () () () ()) -) - - -; Instruction fields. - -; Attributes: -; . PCREL-ADDR pc relative value (for reloc and disassembly purposes) -; . ABS-ADDR absolute address (for reloc and disassembly purposes?) -; . RESERVED bits are not used to decode insn, must be all 0 - -; Instruction classes. -(dnf f-class "insn class" () 31 2) -(dnf f-sub "sub class" () 29 4) - -; Register fields. -(dnf f-r1 "r1" () 25 5) -(dnf f-r2 "r2" () 20 5) -(dnf f-r3 "r3" () 15 5) - -; Immediates. -(df f-simm16 "signed imm (16)" () 15 16 INT #f #f) -(dnf f-uimm16 "unsigned imm (16)" () 15 16) -(dnf f-uimm5 "unsigned imm (5)" () 4 5) -(df f-hi16 "high 16" () 15 16 INT #f #f) -(df f-lo16 "low 16" () 15 16 INT #f #f) - -; Sub fields -(dnf f-op1 "op1" () 31 2) -(dnf f-op2 "op2" () 29 4) -(dnf f-op3 "op3" () 25 2) -(dnf f-op4 "op4" () 23 3) -(dnf f-op5 "op3" () 25 5) -(dnf f-op6 "op4" () 7 3) -(dnf f-op7 "op5" () 3 4) - -(dnf f-i16-1 "uimm16-1" () 10 11) -(dnf f-i16-2 "uimm16-2" () 25 5) - -; PC relative, 26-bit (2 shifted to right) -(df f-disp26 "disp26" (PCREL-ADDR) 25 26 INT - ((value pc) (sra WI (sub WI value pc) (const 2))) - ((value pc) (add WI (sll WI value (const 2)) pc))) - -; absolute, 26-bit (2 shifted to right) -(df f-abs26 "abs26" (ABS-ADDR) 25 26 INT - ((value pc) (sra WI pc (const 2))) - ((value pc) (sll WI value (const 2)))) - -(define-multi-ifield - (name f-i16nc) - (comment "16 bit signed") - (attrs SIGN-OPT) - (mode HI) - (subfields f-i16-1 f-i16-2) - (insert (sequence () - (set (ifield f-i16-2) (and (sra (ifield f-i16nc) - (const 11)) - (const #x1f))) - (set (ifield f-i16-1) (and (ifield f-i16nc) - (const #x7ff))))) - (extract (sequence () - (set (ifield f-i16nc) (c-raw-call SI "@arch@_sign_extend_16bit" - (or (sll (ifield f-i16-2) - (const 11)) - (ifield f-i16-1)))))) -) - - -; Enums. - -; insn-class: bits 31-30 -(define-normal-insn-enum insn-class "FIXME" () OP1_ f-class - (.map .str (.iota 4)) -) - -(define-normal-insn-enum insn-sub "FIXME" () OP2_ f-sub - (.map .str (.iota 16)) -) - -(define-normal-insn-enum insn-op3 "FIXME" () OP3_ f-op3 - (.map .str (.iota 4)) -) - -(define-normal-insn-enum insn-op4 "FIXME" () OP4_ f-op4 - (.map .str (.iota 8)) -) - -(define-normal-insn-enum insn-op5 "FIXME" () OP5_ f-op5 - (.map .str (.iota 32)) -) - -(define-normal-insn-enum insn-op6 "FIXME" () OP6_ f-op6 - (.map .str (.iota 8)) -) - -(define-normal-insn-enum insn-op7 "FIXME" () OP7_ f-op7 - (.map .str (.iota 16)) -) - - - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. - -(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) - -(define-hardware - (name h-gr) (comment "general registers") (attrs PROFILE) - (type register WI (32)) - (indices keyword "" - ((r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) - (r15 15) (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) - (r21 21) (r22 22) (r23 23) (r24 24) (r25 25) (r26 26) - (r27 27) (r28 28) (r29 29) (r30 30) (r31 31) (lr 11) - (sp 1) (fp 2))) -) - -(define-hardware - (name h-sr) (comment "special registers") - (type register WI (#x20000)) - (get (index) (c-call SI "@arch@_h_sr_get_handler" index)) - (set (index newval) (c-call VOID "@arch@_h_sr_set_handler" index newval)) -) - -(dnh h-hi16 "high 16 bits" () (immediate (INT 16)) () () ()) -(dnh h-lo16 "low 16 bits" () (immediate (INT 16)) () () ()) - -(dsh h-cbit "condition bit" () (register BI)) -(dsh h-delay-insn "delay insn addr" () (register SI)) - - -; Instruction operands. - -(dnop sr "special register" (SEM-ONLY) h-sr f-nil) -(dnop cbit "condition bit" (SEM-ONLY) h-cbit f-nil) -(dnop simm-16 "16 bit signed immediate" () h-sint f-simm16) -(dnop uimm-16 "16 bit unsigned immediate" () h-uint f-uimm16) -(dnop disp-26 "pc-rel 26 bit" () h-iaddr f-disp26) -(dnop abs-26 "abs 26 bit" () h-iaddr f-abs26) -(dnop uimm-5 "imm5" () h-uint f-uimm5) - -(dnop rD "destination register" () h-gr f-r1) -(dnop rA "source register A" () h-gr f-r2) -(dnop rB "source register B" () h-gr f-r3) - -(dnop op-f-23 "f-op23" () h-uint f-op4) -(dnop op-f-3 "f-op3" () h-uint f-op5) - -; For hi(foo). -(define-operand - (name hi16) (comment "high 16 bit immediate, sign optional") - (attrs SIGN-OPT) - (type h-hi16) - (index f-simm16) - (handlers (parse "hi16")) -) - -; For lo(foo) -(define-operand - (name lo16) (comment "low 16 bit immediate, sign optional") - (attrs SIGN-OPT) - (type h-lo16) - (index f-lo16) - (handlers (parse "lo16")) -) - -(define-operand - (name ui16nc) - (comment "16 bit immediate, sign optional") - (attrs) - (type h-lo16) - (index f-i16nc) - (handlers (parse "lo16")) -) - - -; Instructions. - -; Branch releated instructions - -(dni l-j "jump (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.j ${abs-26}" - (+ OP1_0 OP2_0 abs-26) - - ; We execute the delay slot before doin' the real branch - (delay 1 (set pc abs-26)) - () -) - -(dni l-jal "jump and link (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.jal ${abs-26}" - (+ OP1_0 OP2_1 abs-26) - - ; We execute the delay slot before doin' the real branch - ; Set LR to (delay insn addr + 4) - (sequence () - (set (reg h-gr 11) (add (reg h-delay-insn) 4)) - (delay 1 (set pc abs-26))) - () -) - -(dni l-jr "jump register (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.jr $rA" - (+ OP1_0 OP2_5 OP3_0 OP4_0 rA uimm-16) - - ; We execute the delay slot before doin' the real branch - (delay 1 (set pc rA)) - () -) - -(dni l-jalr "jump register and link (absolute iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.jalr $rA" - (+ OP1_0 OP2_5 OP3_0 OP4_1 rA uimm-16) - - ; We save the value of rA in a temporary slot before setting - ; the link register. This because "l.jalr r11" would cause - ; a forever-and-ever loop otherwise. - ; - ; We execute the delay slot before doin' the real branch - (sequence ((WI tmp-slot)) - (set tmp-slot rA) - (set (reg h-gr 11) (add (reg h-delay-insn) 4)) - (delay 1 (set pc tmp-slot))) - () -) - -(dni l-bal "branch and link (pc relative iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.bal ${disp-26}" - (+ OP1_0 OP2_2 disp-26) - - ; We execute the delay slot before doin' the real branch - ; Set LR to (delay insn addr + 4) - (sequence () - (set (reg h-gr 11) (add (reg h-delay-insn) 4)) - (delay 1 (set pc disp-26))) - () -) - -(dni l-bnf "branch if condition bit not set (pc relative iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.bnf ${disp-26}" - (+ OP1_0 OP2_3 disp-26) - - ; We execute the delay slot before doin' the real branch - (if (eq cbit 0) - (sequence () - (delay 1 (set pc disp-26)))) - () -) - -(dni l-bf "branch if condition bit is set (pc relative iaddr)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.bf ${disp-26}" - (+ OP1_0 OP2_4 disp-26) - - ; We execute the delay slot before doin' the real branch - (if (eq cbit 1) - (sequence () - (delay 1 (set pc disp-26)))) - () -) - -(dni l-brk "break (exception)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.brk ${uimm-16}" - (+ OP1_0 OP2_5 OP3_3 OP4_0 rA uimm-16) - - ; FIXME should we do it like this ?? - (c-call VOID "@cpu@_cpu_brk" uimm-16) - () -) - -(dni l-rfe "return from exception" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.rfe $rA" - (+ OP1_0 OP2_5 OP3_0 OP4_2 rA uimm-16) - (sequence () - (delay 1 (set pc (c-call SI "@cpu@_cpu_rfe" rA)))) - () -) - -(dni l-sys "syscall (exception)" - ; This function may not be in delay slot - (NOT-IN-DELAY-SLOT) - - "l.sys ${uimm-16}" - (+ OP1_0 OP2_5 OP3_2 OP4_0 rA uimm-16) - (sequence() - (delay 1 (set pc (c-call SI "@cpu@_except" pc - #xc00 uimm-16)))) - () -) - - -; Misc instructions - -(dni l-nop "nop" - () - "l.nop" - (+ OP1_0 OP2_5 OP3_1 OP4_0 rA uimm-16) - (nop) - () -) - -(dnmi l-ret "ret" () - "l.ret" - (emit l-jr (rA 11) (uimm-16 0)) -) - -(dni l-movhi "movhi" - (DELAY-SLOT) - "l.movhi $rD,$hi16" - (+ OP1_0 OP2_6 hi16 rD rA) - (set rD (sll WI hi16 (const 16))) - () -) - - -; System releated instructions - -(dni l-mfsr "mfsr" - (DELAY-SLOT) - "l.mfsr $rD,$rA" - (+ OP1_0 OP2_7 rD rA uimm-16) - (set rD (c-call SI "@cpu@_cpu_mfsr" rA)) - () -) - -(dni l-mtsr "mtsr" - (DELAY-SLOT) - "l.mtsr $rA,$rB" - (+ OP1_1 OP2_0 rA rB rD (f-i16-1 0)) - (c-call VOID "@cpu@_cpu_mtsr" rA rB) - () -) - - - -; Load instructions - -(dni l-lw "load word" - (DELAY-SLOT) - "l.lw $rD,${simm-16}($rA)" - (+ OP1_2 OP2_0 rD rA simm-16) - (set rD (mem SI (add rA simm-16))) - () -) - -(dni l-lbz "load byte (zero extend)" - (DELAY-SLOT) - "l.lbz $rD,${simm-16}($rA)" - (+ OP1_2 OP2_1 rD rA simm-16) - (set rD (zext SI (mem QI (add rA simm-16)))) - () -) - -(dni l-lbs "load byte (sign extend)" - (DELAY-SLOT) - "l.lbs $rD,${simm-16}($rA)" - (+ OP1_2 OP2_2 rD rA simm-16) - (set rD (ext SI (mem QI (add rA simm-16)))) - () -) - -(dni l-lhz "load halfword (zero extend)" - (DELAY-SLOT) - "l.lhz $rD,${simm-16}($rA)" - (+ OP1_2 OP2_3 rD simm-16 rA) - (set rD (zext SI (mem HI (add rA simm-16)))) - () -) - -(dni l-lhs "load halfword (sign extend)" - (DELAY-SLOT) - "l.lhs $rD,${simm-16}($rA)" - (+ OP1_2 OP2_4 rD rA simm-16) - (set rD (ext SI (mem HI (add rA simm-16)))) - () -) - - -; Store instructions -; -; We have to use a multi field since the integer is splited over 2 fields - -(define-pmacro (store-insn mnemonic op2-op mode-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " imm(reg)/reg") - (DELAY-SLOT) - (.str "l." mnemonic " ${ui16nc}($rA),$rB") - (+ OP1_3 op2-op rB rD ui16nc) - (set (mem mode-op (add rA ui16nc)) rB) - () - ) - ) -) - -(store-insn sw OP2_5 SI) -(store-insn sb OP2_6 QI) -(store-insn sh OP2_7 HI) - - - -; Shift and rotate instructions - -; Reserved fields. -(dnf f-f-15-8 "nop" (RESERVED) 15 8) -(dnf f-f-10-3 "nop" (RESERVED) 10 3) -(dnf f-f-4-1 "nop" (RESERVED) 4 1) -(dnf f-f-7-3 "nop" (RESERVED) 7 3) - -(define-pmacro (shift-insn mnemonic op4-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " reg/reg/reg") - () - (.str "l." mnemonic " $rD,$rA,$rB") - (+ OP1_3 OP2_8 rD rA rB (f-f-10-3 0) op4-op (f-f-4-1 0) OP7_8) - (set rD (mnemonic rA rB)) - () - ) - (dni (.sym l- mnemonic "i") - (.str "l." mnemonic " reg/reg/imm") - () - (.str "l." mnemonic "i $rD,$rA,${uimm-5}") - (+ OP1_2 OP2_13 rD rA (f-f-15-8 0) op4-op uimm-5) - (set rD (mnemonic rA uimm-5)) - () - ) - ) -) - -(shift-insn sll OP6_0) -(shift-insn srl OP6_1) -(shift-insn sra OP6_2) -(shift-insn ror OP6_4) - - -; Arethmetic insns - -; Reserved fields. -(dnf f-f-10-7 "nop" (RESERVED) 10 7) - -(define-pmacro (ar-insn-u mnemonic op2-op op5-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " reg/reg/reg") - () - (.str "l." mnemonic " $rD,$rA,$rB") - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) - (set rD (mnemonic rA rB)) - () - ) - (dni (.sym l- mnemonic "i") - (.str "l." mnemonic " reg/reg/lo16") - () - (.str "l." mnemonic "i $rD,$rA,$lo16") - (+ OP1_2 op2-op rD rA lo16) - (set rD (mnemonic rA (and lo16 #xffff))) - () - ) - ) -) - -(define-pmacro (ar-insn-s mnemonic op2-op op5-op) - (begin - (dni (.sym l- mnemonic) - (.str "l." mnemonic " reg/reg/reg") - () - (.str "l." mnemonic " $rD,$rA,$rB") - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) op5-op) - (set rD (mnemonic rA rB)) - () - ) - (dni (.sym l- mnemonic "i") - (.str "l." mnemonic " reg/reg/lo16") - () - (.str "l." mnemonic "i $rD,$rA,$lo16") - (+ OP1_2 op2-op rD rA lo16) - (set rD (mnemonic rA lo16)) - () - ) - ) -) - -(ar-insn-s add OP2_5 OP7_0) -;;(ar-op-s addc OP2_5 OP7_0) -(ar-insn-s sub OP2_7 OP7_2) -(ar-insn-u and OP2_8 OP7_3) -(ar-insn-u or OP2_9 OP7_4) -(ar-insn-u xor OP2_10 OP7_5) -(ar-insn-u mul OP2_11 OP7_6) -;;(ar-op-u mac OP2_12 OP7_7) - - -(dni l-div "divide (signed)" - (DELAY-SLOT) - "l.div $rD,$rA,$rB" - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_9) - (if VOID (eq rB (const 0)) - (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) - (set rD (div rA rB))) - () -) - -(dni l-divu "divide (unsigned)" - (DELAY-SLOT) - "l.divu $rD,$rA,$rB" - (+ OP1_3 OP2_8 rD rA rB (f-f-10-7 0) OP7_10) - (if VOID (eq rB (const 0)) - (c-call VOID "@arch@_cpu_trap" pc (enum SI E_ILLEGAL)) - (set rD (udiv rA rB))) - () -) - - -; Compare instructions - -; Reserved fields. -(dnf f-f-10-11 "nop" (RESERVED) 10 11) - -; Register compare (both signed and unsigned) -(define-pmacro (sf-insn-r op1-op op2-op op3-op op3-op-2 sem-op) - (begin - (dni (.sym l- "sf" (.sym sem-op "s")) - (.str "l." mnemonic " reg/reg") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "s $rA,$rB") - (+ op1-op op2-op op3-op-2 rA rB (f-f-10-11 0)) - (set cbit (sem-op rA rB)) - () - ) - (dni (.sym l- "sf" (.sym sem-op "u")) - (.str "l." mnemonic " reg/reg") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "u $rA,$rB") - (+ op1-op op2-op op3-op rA rB (f-f-10-11 0)) - (set cbit (sem-op rA rB)) - () - ) - ) -) - -; Immediate compare (both signed and unsigned) -(define-pmacro (sf-insn-i op1-op op2-op op3-op op3-op-2 sem-op) - (begin - (dni (.sym l- "sf" (.sym sem-op "si")) - (.str "l." mnemonic "si reg/imm") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "si $rA,${simm-16}") - (+ op1-op op2-op op3-op-2 rA simm-16) - (set cbit (sem-op rA simm-16)) - () - ) - (dni (.sym l- "sf" (.sym sem-op "ui")) - (.str "l." mnemonic "ui reg/imm") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "ui $rA,${uimm-16}") - (+ op1-op op2-op op3-op rA uimm-16) - (set cbit (sem-op rA uimm-16)) - () - ) - ) -) - -(define-pmacro (sf-insn op5-op sem-op) - (begin - (dni (.sym l- "sf" sem-op) - (.str "l." mnemonic " reg/reg") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) " $rA,$rB") - (+ OP1_3 OP2_9 op5-op rA rB (f-f-10-11 0)) - (set cbit (sem-op rA rB)) - () - ) - (dni (.sym l- "sf" (.sym sem-op "i")) - (.str "l." mnemonic "i reg/imm") - (DELAY-SLOT) - (.str "l.sf" (.str sem-op) "i $rA,${simm-16}") - (+ OP1_2 OP2_14 op5-op rA simm-16) - (set cbit (sem-op rA simm-16)) - () - ) - ) -) - - -(sf-insn-r OP1_3 OP2_9 OP5_2 OP5_6 gt) -(sf-insn-r OP1_3 OP2_9 OP5_3 OP5_7 ge) -(sf-insn-r OP1_3 OP2_9 OP5_4 OP5_8 lt) -(sf-insn-r OP1_3 OP2_9 OP5_5 OP5_9 le) - -(sf-insn-i OP1_2 OP2_14 OP5_2 OP5_6 gt) -(sf-insn-i OP1_2 OP2_14 OP5_3 OP5_7 ge) -(sf-insn-i OP1_2 OP2_14 OP5_4 OP5_8 lt) -(sf-insn-i OP1_2 OP2_14 OP5_5 OP5_9 le) - -(sf-insn OP5_0 eq) -(sf-insn OP5_1 ne) diff --git a/binutils-2.24/cpu/openrisc.opc b/binutils-2.24/cpu/openrisc.opc deleted file mode 100644 index 291be510..00000000 --- a/binutils-2.24/cpu/openrisc.opc +++ /dev/null @@ -1,164 +0,0 @@ -/* OpenRISC opcode support. -*- C -*- - Copyright 2000, 2001, 2003, 2005, 2011 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* This file is an addendum to or32.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h" */ - -/* -- opc.h */ -#undef CGEN_DIS_HASH_SIZE -#define CGEN_DIS_HASH_SIZE 64 -#undef CGEN_DIS_HASH -#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2) - -extern long openrisc_sign_extend_16bit (long); -/* -- */ - -/* -- opc.c */ -/* -- */ - -/* -- asm.c */ - -static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'"); - -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -long -openrisc_sign_extend_16bit (long value) -{ - return ((value & 0xffff) ^ 0x8000) - 0x8000; -} - -/* Handle hi(). */ - -static const char * -parse_hi16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - unsigned long ret; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "hi(", 3) == 0) - { - bfd_vma value; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_HI16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - - ++*strp; - if (errmsg == NULL - && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value >>= 16; - ret = value; - } - else - { - if (**strp == '-') - { - long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); - ret = value; - } - else - { - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); - ret = value; - } - } - - *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; - return errmsg; -} - -/* Handle lo(). */ - -static const char * -parse_lo16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result_type; - unsigned long ret; - - if (**strp == '#') - ++*strp; - - if (strncasecmp (*strp, "lo(", 3) == 0) - { - bfd_vma value; - - *strp += 3; - errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_LO16, - & result_type, & value); - if (**strp != ')') - return MISSING_CLOSING_PARENTHESIS; - - ++*strp; - ret = value; - } - else - { - if (**strp == '-') - { - long value; - - errmsg = cgen_parse_signed_integer (cd, strp, opindex, &value); - ret = value; - } - else - { - unsigned long value; - - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, &value); - ret = value; - } - } - - *valuep = ((ret & 0xffff) ^ 0x8000) - 0x8000; - return errmsg; -} - -/* -- */ - -/* -- ibd.h */ -extern long openrisc_sign_extend_16bit (long); - -/* -- */ diff --git a/binutils-2.24/cpu/sh.cpu b/binutils-2.24/cpu/sh.cpu deleted file mode 100644 index d9ece1a0..00000000 --- a/binutils-2.24/cpu/sh.cpu +++ /dev/null @@ -1,369 +0,0 @@ -; Hitachi SH architecture description. -*- Scheme -*- -; -; Copyright 2000, 2001, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Hitachi -; Semiconductor (America) Inc. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - - -(include "simplify.inc") - -(define-arch - (name sh) - (comment "Hitachi SuperH (SH)") - (insn-lsb0? #t) - (machs sh2 sh3 sh3e sh4 sh5) - (isas compact media) -) - - -; Instruction sets. - -(define-isa - (name media) - (comment "SHmedia 32-bit instruction set") - (base-insn-bitsize 32) -) - -(define-isa - (name compact) - (comment "SHcompact 16-bit instruction set") - (base-insn-bitsize 16) -) - - -; CPU family. - -(define-cpu - (name sh64) - (comment "SH 64-bit family") - (endian either) - (word-bitsize 32) -) - - -(define-mach - (name sh2) - (comment "SH-2 CPU core") - (cpu sh64) - (isas compact) -) - -(define-mach - (name sh3) - (comment "SH-3 CPU core") - (cpu sh64) - (isas compact) -) - -(define-mach - (name sh3e) - (comment "SH-3e CPU core") - (cpu sh64) - (isas compact) -) - -(define-mach - (name sh4) - (comment "SH-4 CPU core") - (cpu sh64) - (isas compact) -) - -(define-mach - (name sh5) - (comment "SH-5 CPU core") - (cpu sh64) - (isas compact media) -) - -(define-model - (name sh5) - (comment "SH-5 reference implementation") - (mach sh5) - (unit u-exec "Execution unit" () - 1 1 ; issue done - () () () ()) -) - -; Hardware elements. - -(define-hardware - (name h-pc) - (comment "Program counter") - (attrs PC (ISA compact,media)) - (type pc UDI) - (get () (raw-reg h-pc)) - (set (newval) (sequence () - (set (raw-reg h-ism) (and newval 1)) - (set (raw-reg h-pc) (and newval (inv UDI 1))))) -) - -(define-pmacro (-build-greg-name n) ((.sym r n) n)) - -(define-hardware - (name h-gr) - (comment "General purpose integer registers") - (attrs (ISA media,compact)) - (type register DI (64)) - (indices keyword "" (.map -build-greg-name (.iota 64))) - (get (index) - (if DI (eq index 63) - (const 0) - (raw-reg h-gr index))) - (set (index newval) - (if (ne index 63) - (set (raw-reg h-gr index) newval) - (nop))) -) - -(define-hardware - (name h-grc) - (comment "General purpose integer registers (SHcompact view)") - (attrs VIRTUAL (ISA compact)) - (type register SI (16)) - (indices keyword "" (.map -build-greg-name (.iota 16))) - (get (index) - (and (raw-reg h-gr index) (zext DI #xFFFFFFFF))) - (set (index newval) - (set (raw-reg h-gr index) (ext DI newval))) -) - -(define-pmacro (-build-creg-name n) ((.sym cr n) n)) - -(define-hardware - (name h-cr) - (comment "Control registers") - (attrs (ISA media)) - (type register DI (64)) - (indices keyword "" (.map -build-creg-name (.iota 64))) - (get (index) - (if DI (eq index 0) - (zext DI (reg h-sr)) - (raw-reg h-cr index))) - (set (index newval) - (if (eq index 0) - (set (reg h-sr) newval) - (set (raw-reg h-cr index) newval))) -) - -(define-hardware - (name h-sr) - (comment "Status register") - (attrs (ISA compact,media)) - (type register SI) -) - -(define-hardware - (name h-fpscr) - (comment "Floating point status and control register") - (attrs (ISA compact,media)) - (type register SI) -) - -(define-hardware - (name h-frbit) - (comment "Floating point register file bit") - (attrs (ISA media,compact) VIRTUAL) - (type register BI) - (get () (and (srl (reg h-sr) 14) 1)) - (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14)))) -) - -(define-hardware - (name h-szbit) - (comment "Floating point transfer size bit") - (attrs (ISA media,compact) VIRTUAL) - (type register BI) - (get () (and (srl (reg h-sr) 13) 1)) - (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13)))) -) - -(define-hardware - (name h-prbit) - (comment "Floating point precision bit") - (attrs (ISA media,compact) VIRTUAL) - (type register BI) - (get () (and (srl (reg h-sr) 12) 1)) - (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12)))) -) - -(define-hardware - (name h-sbit) - (comment "Multiply-accumulate saturation flag") - (attrs (ISA compact) VIRTUAL) - (type register BI) - (get () (and (srl (reg h-sr) 1) 1)) - (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1)))) -) - -(define-hardware - (name h-mbit) - (comment "Divide-step M flag") - (attrs (ISA compact) VIRTUAL) - (type register BI) - (get () (and (srl (reg h-sr) 9) 1)) - (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9)))) -) - -(define-hardware - (name h-qbit) - (comment "Divide-step Q flag") - (attrs (ISA compact) VIRTUAL) - (type register BI) - (get () (and (srl (reg h-sr) 8) 1)) - (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8)))) -) - -(define-pmacro (-build-freg-name n) ((.sym fr n) n)) - -(define-hardware - (name h-fr) - (comment "Single precision floating point registers") - (attrs (ISA media,compact)) - (type register SF (64)) - (indices keyword "" (.map -build-freg-name (.iota 64))) -) - - -(define-pmacro (-build-fpair-name n) ((.sym fp n) n)) - -(define-hardware - (name h-fp) - (comment "Single precision floating point register pairs") - (attrs (ISA media,compact)) - (type register DF (32)) - (indices keyword "" (.map -build-fpair-name (.iota 32))) -) - -(define-pmacro (-build-fvec-name n) ((.sym fv n) n)) - -(define-hardware - (name h-fv) - (comment "Single precision floating point vectors") - (attrs VIRTUAL (ISA media,compact)) - (type register SF (16)) - (indices keyword "" (.map -build-fvec-name (.iota 16))) - ; Mask with $F to ensure 0 <= index < 15. - (get (index) (reg h-fr (mul (and UQI index 15) 4))) - (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval)) -) - -(define-hardware - (name h-fmtx) - (comment "Single precision floating point matrices") - (attrs VIRTUAL (ISA media)) - (type register SF (4)) - (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3))) - ; Mask with $3 to ensure 0 <= index < 4. - (get (index) (reg h-fr (mul (and UQI index 3) 16))) - (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval)) -) - -(define-pmacro (-build-dreg-name n) ((.sym dr n) n)) - -(define-hardware - (name h-dr) - (comment "Double precision floating point registers") - (attrs (ISA media,compact) VIRTUAL) - (type register DF (32)) - (indices keyword "" (.map -build-dreg-name (.iota 64))) - (get (index) - (subword DF - (or - (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32) - (zext DI (subword SI (reg h-fr (add index 1)) 0))) 0)) - (set (index newval) - (sequence () - (set (reg h-fr index) - (subword SF (subword SI newval 0) 0)) - (set (reg h-fr (add index 1)) - (subword SF (subword SI newval 1) 0)))) -) - -(define-hardware - (name h-tr) - (comment "Branch target registers") - (attrs (ISA media)) - (type register DI (8)) - (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7))) -) - -(define-hardware - (name h-endian) - (comment "Current endian mode") - (attrs (ISA compact,media) VIRTUAL) - (type register BI) - (get () (c-call BI "sh64_endian")) - (set (newval) (error "cannot alter target byte order mid-program")) -) - -(define-hardware - (name h-ism) - (comment "Current instruction set mode") - (attrs (ISA compact,media)) - (type register BI) - (get () (raw-reg h-ism)) - (set (newval) (error "cannot set ism directly")) -) - - -; Operands. - -(dnop endian "Endian mode" ((ISA compact,media)) h-endian f-nil) -(dnop ism "Instruction set mode" ((ISA compact,media)) h-ism f-nil) - -; Universally useful macros. - -; A pmacro for use in semantic bodies of unimplemented insns. -(define-pmacro (unimp mnemonic) (nop)) - -; Join 2 ints together in natural bit order. -(define-pmacro (-join-si s1 s0) - (or (sll (zext DI s1) 32) - (zext DI s0))) - -; Join 4 half-ints together in natural bit order. -(define-pmacro (-join-hi h3 h2 h1 h0) - (or (sll (zext DI h3) 48) - (or (sll (zext DI h2) 32) - (or (sll (zext DI h1) 16) - (zext DI h0))))) - -; Join 8 quarter-ints together in natural bit order. -(define-pmacro (-join-qi b7 b6 b5 b4 b3 b2 b1 b0) - (or (sll (zext DI b7) 56) - (or (sll (zext DI b6) 48) - (or (sll (zext DI b5) 40) - (or (sll (zext DI b4) 32) - (or (sll (zext DI b3) 24) - (or (sll (zext DI b2) 16) - (or (sll (zext DI b1) 8) - (zext DI b0))))))))) - - -; Include the two instruction set descriptions from their respective -; source files. - -(if (keep-isa? (compact)) - (include "sh64-compact.cpu")) - -(if (keep-isa? (media)) - (include "sh64-media.cpu")) diff --git a/binutils-2.24/cpu/sh.opc b/binutils-2.24/cpu/sh.opc deleted file mode 100644 index 364fcccf..00000000 --- a/binutils-2.24/cpu/sh.opc +++ /dev/null @@ -1,77 +0,0 @@ -/* SHmedia opcode support. -*- C -*- - - Copyright 2000, 2005, 2007, 2009 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; developed under contract from Hitachi - Semiconductor (America) Inc. - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* This file is an addendum to sh-media.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h" */ - -/* -- opc.h */ - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* Override disassembly hashing - there are variable bits in the top - byte of these instructions. */ -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE) - -/* -- asm.c */ - -static const char * -parse_fsd (CGEN_CPU_DESC cd, - const char ** strp, - int opindex, - long * valuep) -{ - abort (); -} - -/* -- dis.c */ - -static void -print_likely (CGEN_CPU_DESC cd, - void * dis_info, - long value, - unsigned int attrs, - bfd_vma pc, - int length) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - (*info->fprintf_func) (info->stream, (value) ? "/l" : "/u"); -} - -/* -- */ diff --git a/binutils-2.24/cpu/sh64-compact.cpu b/binutils-2.24/cpu/sh64-compact.cpu deleted file mode 100644 index 5b1b8633..00000000 --- a/binutils-2.24/cpu/sh64-compact.cpu +++ /dev/null @@ -1,1748 +0,0 @@ -; Hitachi SHcompact instruction set description. -*- Scheme -*- -; -; Copyright 2000, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Hitachi -; Semiconductor (America) Inc. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; dshcf -- define-normal-sh-compact-field - -(define-pmacro (dshcf xname xcomment ignored xstart xlength) - (dnf xname xcomment ((ISA compact)) xstart xlength)) - -; dshcop -- define-normal-sh-compact-operand - -(define-pmacro (dshcop xname xcomment ignored xhardware xfield) - (dnop xname xcomment ((ISA compact)) xhardware xfield)) - - -; SHcompact-specific attributes. - -(define-attr - (for insn) - (type boolean) - (name ILLSLOT) - (comment "instruction may not appear in a delay slot") -) - -(define-attr - (for insn) - (type boolean) - (name FP-INSN) - (comment "floating point instruction") -) - -(define-keyword - (name frc-names) - (attrs (ISA compact)) - (print-name h-frc) - (values (fr0 0) (fr1 1) (fr2 2) (fr3 3) (fr4 4) (fr5 5) - (fr6 6) (fr7 7) (fr8 8) (fr9 9) (fr10 10) (fr11 11) - (fr12 12) (fr13 13) (fr14 14) (fr15 15)) -) - -(define-keyword - (name drc-names) - (attrs (ISA compact)) - (print-name h-drc) - (values (dr0 0) (dr2 2) (dr4 4) (dr6 6) (dr8 8) (dr10 10) (dr12 12) (dr14 14)) -) - -(define-keyword - (name xf-names) - (attrs (ISA compact)) - (print-name h-xf) - (values (xf0 0) (xf1 1) (xf2 2) (xf3 3) (xf4 4) (xf5 5) - (xf6 6) (xf7 7) (xf8 8) (xf9 9) (xf10 10) (xf11 11) - (xf12 12) (xf13 13) (xf14 14) (xf15 15)) -) - -; Hardware specific to the SHcompact mode. - -(define-pmacro (front) (mul 16 frbit)) -(define-pmacro (back) (mul 16 (not frbit))) - -(define-hardware - (name h-frc) - (comment "Single precision floating point registers") - (attrs VIRTUAL (ISA compact)) - (indices extern-keyword frc-names) - (type register SF (16)) - (get (index) (reg h-fr (add (front) index))) - (set (index newval) (set (reg h-fr (add (front) index)) newval)) -) - -(define-hardware - (name h-drc) - (comment "Double precision floating point registers") - (attrs VIRTUAL (ISA compact)) - (indices extern-keyword drc-names) - (type register DF (8)) - (get (index) (reg h-dr (add (front) index))) - (set (index newval) (set (reg h-dr (add (front) index)) newval)) -) - -(define-hardware - (name h-xf) - (comment "Extended single precision floating point registers") - (attrs VIRTUAL (ISA compact)) - (indices extern-keyword xf-names) - (type register SF (16)) - (get (index) (reg h-fr (add (back) index))) - (set (index newval) (set (reg h-fr (add (back) index)) newval)) -) - -(define-hardware - (name h-xd) - (comment "Extended double precision floating point registers") - (attrs VIRTUAL (ISA compact)) - (indices extern-keyword frc-names) - (type register DF (8)) - (get (index) (reg h-dr (add (back) index))) - (set (index newval) (set (reg h-dr (add (back) index)) newval)) -) - -(define-hardware - (name h-fvc) - (comment "Single precision floating point vectors") - (attrs VIRTUAL (ISA compact)) - (indices keyword "" ((fv0 0) (fv4 4) (fv8 8) (fv12 12))) - (type register SF (4)) - (get (index) (reg h-fr (add (front) index))) - (set (index newval) (set (reg h-fr (add (front) index)) newval)) -) - -(define-hardware - (name h-fpccr) - (comment "SHcompact floating point status/control register") - (attrs VIRTUAL (ISA compact)) - (type register SI) - (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21))) - (set (newvalue) (sequence () - (set (reg h-fpscr) newvalue) - (set prbit (and (srl newvalue 19) 1)) - (set szbit (and (srl newvalue 20) 1)) - (set frbit (and (srl newvalue 21) 1)))) -) - -(define-hardware - (name h-gbr) - (comment "Global base register") - (attrs VIRTUAL (ISA compact)) - (type register SI) - (get () (subword SI (raw-reg h-gr 16) 1)) - (set (newval) (set (raw-reg h-gr 16) (ext DI newval))) -) - -(define-hardware - (name h-pr) - (comment "Procedure link register") - (attrs VIRTUAL (ISA compact)) - (type register SI) - (get () (subword SI (raw-reg h-gr 18) 1)) - (set (newval) (set (raw-reg h-gr 18) (ext DI newval))) -) - -(define-hardware - (name h-macl) - (comment "Multiple-accumulate low register") - (attrs VIRTUAL (ISA compact)) - (type register SI) - (get () (subword SI (raw-reg h-gr 17) 1)) - (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval))) -) - -(define-hardware - (name h-mach) - (comment "Multiply-accumulate high register") - (attrs VIRTUAL (ISA compact)) - (type register SI) - (get () (subword SI (raw-reg h-gr 17) 0)) - (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1)))) -) - -(define-hardware - (name h-tbit) - (comment "Condition code flag") - (attrs VIRTUAL (ISA compact)) - (type register BI) - (get () (and BI (raw-reg h-gr 19) 1)) - (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval)))) -) - - -(dshcf f-op4 "Opcode (4 bits)" () 15 4) -(dshcf f-op8 "Opcode (8 bits)" () 15 8) -(dshcf f-op16 "Opcode (16 bits)" () 15 16) - -(dshcf f-sub4 "Sub opcode (4 bits)" () 3 4) -(dshcf f-sub8 "Sub opcode (8 bits)" () 7 8) -(dshcf f-sub10 "Sub opcode (10 bits)" () 9 10) - -(dshcf f-rn "Register selector n" () 11 4) -(dshcf f-rm "Register selector m" () 7 4) - -(dshcf f-8-1 "One bit at bit 8" () 8 1) - -(df f-disp8 "Displacement (8 bits)" ((ISA compact) PCREL-ADDR) 7 8 INT - ((value pc) (sra SI value 1)) - ((value pc) (add SI (sll SI value 1) (add pc 4)))) - -(df f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT - ((value pc) (sra SI value 1)) - ((value pc) (add SI (sll SI value 1) (add pc 4)))) - -(dshcf f-imm8 "Immediate (8 bits)" () 7 8) -(dshcf f-imm4 "Immediate (4 bits)" () 3 4) - -(df f-imm4x2 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT - ((value pc) (srl SI value 1)) - ((value pc) (sll SI value 1))) - -(df f-imm4x4 "Immediate (4 bits)" ((ISA compact)) 3 4 UINT - ((value pc) (srl SI value 2)) - ((value pc) (sll SI value 2))) - -(df f-imm8x2 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT - ((value pc) (sra SI value 1)) - ((value pc) (sll SI value 1))) - -(df f-imm8x4 "Immediate (8 bits)" ((ISA compact)) 7 8 UINT - ((value pc) (sra SI value 2)) - ((value pc) (sll SI value 2))) - -(df f-dn "Double selector n" ((ISA compact)) 11 3 UINT - ((value pc) (srl SI value 1)) - ((value pc) (sll SI value 1))) - -(df f-dm "Double selector m" ((ISA compact)) 7 3 UINT - ((value pc) (srl SI value 1)) - ((value pc) (sll SI value 1))) - -(df f-vn "Vector selector n" ((ISA compact)) 11 2 UINT - ((value pc) (srl SI value 2)) - ((value pc) (sll SI value 2))) - -(df f-vm "Vector selector m" ((ISA compact)) 9 2 UINT - ((value pc) (srl SI value 2)) - ((value pc) (sll SI value 2))) - -(df f-xn "Extended selector n" ((ISA compact)) 11 3 UINT - ((value pc) (srl SI value 1)) - ((value pc) (add SI (sll SI value 1) 1))) - -(df f-xm "Extended selector m" ((ISA compact)) 7 3 UINT - ((value pc) (srl SI value 1)) - ((value pc) (add SI (sll SI value 1) 1))) - - -; Operands. - -(dshcop rm "Left general purpose register" () h-grc f-rm) -(dshcop rn "Right general purpose register" () h-grc f-rn) -(dshcop r0 "Register 0" () h-grc 0) - -(dshcop frn "Single precision register" () h-frc f-rn) -(dshcop frm "Single precision register" () h-frc f-rm) - -(dshcop fvn "Left floating point vector" () h-fvc f-vn) -(dshcop fvm "Right floating point vector" () h-fvc f-vm) - -(dshcop drn "Left double precision register" () h-drc f-dn) -(dshcop drm "Right double precision register" () h-drc f-dm) - -(dshcop imm4 "Immediate value (4 bits)" () h-sint f-imm4) -(dshcop imm8 "Immediate value (8 bits)" () h-sint f-imm8) -(dshcop uimm8 "Immediate value (8 bits unsigned)" () h-uint f-imm8) - -(dshcop imm4x2 "Immediate value (4 bits, 2x scale)" () h-uint f-imm4x2) -(dshcop imm4x4 "Immediate value (4 bits, 4x scale)" () h-uint f-imm4x4) -(dshcop imm8x2 "Immediate value (8 bits, 2x scale)" () h-uint f-imm8x2) -(dshcop imm8x4 "Immediate value (8 bits, 4x scale)" () h-uint f-imm8x4) - -(dshcop disp8 "Displacement (8 bits)" () h-iaddr f-disp8) -(dshcop disp12 "Displacement (12 bits)" () h-iaddr f-disp12) - -(dshcop rm64 "Register m (64 bits)" () h-gr f-rm) -(dshcop rn64 "Register n (64 bits)" () h-gr f-rn) - -(dshcop gbr "Global base register" () h-gbr f-nil) -(dshcop pr "Procedure link register" () h-pr f-nil) - -(dshcop fpscr "Floating point status/control register" () h-fpccr f-nil) - -(dshcop tbit "Condition code flag" () h-tbit f-nil) -(dshcop sbit "Multiply-accumulate saturation flag" () h-sbit f-nil) -(dshcop mbit "Divide-step M flag" () h-mbit f-nil) -(dshcop qbit "Divide-step Q flag" () h-qbit f-nil) -(dshcop fpul "Floating point ???" () h-fr 32) - -(dshcop frbit "Floating point register bank bit" () h-frbit f-nil) -(dshcop szbit "Floating point transfer size bit" () h-szbit f-nil) -(dshcop prbit "Floating point precision bit" () h-prbit f-nil) - -(dshcop macl "Multiply-accumulate low register" () h-macl f-nil) -(dshcop mach "Multiply-accumulate high register" () h-mach f-nil) - - -(define-operand (name fsdm) (comment "bar") - (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd"))) - -(define-operand (name fsdn) (comment "bar") - (attrs (ISA compact)) (type h-frc) (index f-rn)) - - -; Cover macro to dni to indicate these are all SHcompact instructions. -; dshmi: define-normal-sh-compact-insn - -(define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics) - (define-insn - (name (.sym xname -compact)) - (comment xcomment) - (.splice attrs (.unsplice xattrs) (ISA compact)) - (syntax xsyntax) - (format xformat) - (semantics xsemantics))) - -(define-pmacro (dr operand) (reg h-dr (index-of operand))) -(define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1)))) - -(dshci add "Add" - () - "add $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 12)) - (set rn (add rn rm))) - -(dshci addi "Add immediate" - () - "add #$imm8, $rn" - (+ (f-op4 7) rn imm8) - (set rn (add rn (ext SI (and QI imm8 255))))) - -(dshci addc "Add with carry" - () - "addc $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 14)) - (sequence ((BI flag)) - (set flag (add-cflag rn rm tbit)) - (set rn (addc rn rm tbit)) - (set tbit flag))) - -(dshci addv "Add with overflow" - () - "addv $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 15)) - (sequence ((BI t)) - (set t (add-oflag rn rm 0)) - (set rn (add rn rm)) - (set tbit t))) - -(dshci and "Bitwise AND" - () - "and $rm64, $rn64" - (+ (f-op4 2) rn64 rm64 (f-sub4 9)) - (set rn64 (and rm64 rn64))) - -(dshci andi "Bitwise AND immediate" - () - "and #$uimm8, r0" - (+ (f-op8 #xc9) uimm8) - (set r0 (and r0 (zext DI uimm8)))) - -(dshci andb "Bitwise AND memory byte" - () - "and.b #$imm8, @(r0, gbr)" - (+ (f-op8 #xcd) imm8) - (sequence ((DI addr) (UQI data)) - (set addr (add r0 gbr)) - (set data (and (mem UQI addr) imm8)) - (set (mem UQI addr) data))) - -(dshci bf "Conditional branch" - () - "bf $disp8" - (+ (f-op8 #x8b) disp8) - (if (not tbit) - (set pc disp8))) - -(dshci bfs "Conditional branch with delay slot" - () - "bf/s $disp8" - (+ (f-op8 #x8f) disp8) - (if (not tbit) - (delay 1 (set pc disp8)))) - -(dshci bra "Branch" - () - "bra $disp12" - (+ (f-op4 10) disp12) - (delay 1 (set pc disp12))) - -(dshci braf "Branch far" - () - "braf $rn" - (+ (f-op4 0) rn (f-sub8 35)) - (delay 1 (set pc (add (ext DI rn) (add pc 4))))) - -(dshci brk "Breakpoint" - () - "brk" - (+ (f-op16 59)) - (c-call "sh64_break" pc)) - -(dshci bsr "Branch to subroutine" - () - "bsr $disp12" - (+ (f-op4 11) disp12) - (delay 1 (sequence () - (set pr (add pc 4)) - (set pc disp12)))) - -(dshci bsrf "Branch to far subroutine" - () - "bsrf $rn" - (+ (f-op4 0) rn (f-sub8 3)) - (delay 1 (sequence () - (set pr (add pc 4)) - (set pc (add (ext DI rn) (add pc 4)))))) - -(dshci bt "Conditional branch" - () - "bt $disp8" - (+ (f-op8 #x89) disp8) - (if tbit - (set pc disp8))) - -(dshci bts "Conditional branch with delay slot" - () - "bt/s $disp8" - (+ (f-op8 #x8d) disp8) - (if tbit - (delay 1 (set pc disp8)))) - -(dshci clrmac "Clear MACL and MACH" - () - "clrmac" - (+ (f-op16 40)) - (sequence () - (set macl 0) - (set mach 0))) - -(dshci clrs "Clear S-bit" - () - "clrs" - (+ (f-op16 72)) - (set sbit 0)) - -(dshci clrt "Clear T-bit" - () - "clrt" - (+ (f-op16 8)) - (set tbit 0)) - -(dshci cmpeq "Compare if equal" - () - "cmp/eq $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 0)) - (set tbit (eq rm rn))) - -(dshci cmpeqi "Compare if equal (immediate)" - () - "cmp/eq #$imm8, r0" - (+ (f-op8 #x88) imm8) - (set tbit (eq r0 (ext SI (and QI imm8 255))))) - -(dshci cmpge "Compare if greater than or equal" - () - "cmp/ge $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 3)) - (set tbit (ge rn rm))) - -(dshci cmpgt "Compare if greater than" - () - "cmp/gt $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 7)) - (set tbit (gt rn rm))) - -(dshci cmphi "Compare if greater than (unsigned)" - () - "cmp/hi $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 6)) - (set tbit (gtu rn rm))) - -(dshci cmphs "Compare if greater than or equal (unsigned)" - () - "cmp/hs $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 2)) - (set tbit (geu rn rm))) - -(dshci cmppl "Compare if greater than zero" - () - "cmp/pl $rn" - (+ (f-op4 4) rn (f-sub8 21)) - (set tbit (gt rn 0))) - -(dshci cmppz "Compare if greater than or equal zero" - () - "cmp/pz $rn" - (+ (f-op4 4) rn (f-sub8 17)) - (set tbit (ge rn 0))) - -(dshci cmpstr "Compare bytes" - () - "cmp/str $rm, $rn" - (+ (f-op4 2) rn rm (f-sub4 12)) - (sequence ((BI t) (SI temp)) - (set temp (xor rm rn)) - (set t (eq (and temp #xff000000) 0)) - (set t (or (eq (and temp #xff0000) 0) t)) - (set t (or (eq (and temp #xff00) 0) t)) - (set t (or (eq (and temp #xff) 0) t)) - (set tbit (if BI (gtu t 0) 1 0)))) - -(dshci div0s "Initialise divide-step state for signed division" - () - "div0s $rm, $rn" - (+ (f-op4 2) rn rm (f-sub4 7)) - (sequence () - (set qbit (srl rn 31)) - (set mbit (srl rm 31)) - (set tbit (if BI (eq (srl rm 31) (srl rn 31)) 0 1)))) - -(dshci div0u "Initialise divide-step state for unsigned division" - () - "div0u" - (+ (f-op16 25)) - (sequence () - (set tbit 0) - (set qbit 0) - (set mbit 0))) - -(dshci div1 "Divide step" - () - "div1 $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 4)) - (sequence ((BI oldq) (SI tmp0) (UQI tmp1)) - (set oldq qbit) - (set qbit (srl rn 31)) - (set rn (or (sll rn 1) (zext SI tbit))) - (if (not oldq) - (if (not mbit) - (sequence () - (set tmp0 rn) - (set rn (sub rn rm)) - (set tmp1 (gtu rn tmp0)) - (if (not qbit) - (set qbit (if BI tmp1 1 0)) - (set qbit (if BI (eq tmp1 0) 1 0)))) - (sequence () - (set tmp0 rn) - (set rn (add rn rm)) - (set tmp1 (ltu rn tmp0)) - (if (not qbit) - (set qbit (if BI (eq tmp1 0) 1 0)) - (set qbit (if BI tmp1 1 0))))) - (if (not mbit) - (sequence () - (set tmp0 rn) - (set rn (add rm rn)) - (set tmp1 (ltu rn tmp0)) - (if (not qbit) - (set qbit (if BI tmp1 1 0)) - (set qbit (if BI (eq tmp1 0) 1 0)))) - (sequence () - (set tmp0 rn) - (set rn (sub rn rm)) - (set tmp1 (gtu rn tmp0)) - (if (not qbit) - (set qbit (if BI (eq tmp1 0) 1 0)) - (set qbit (if BI tmp1 1 0)))))) - (set tbit (if BI (eq qbit mbit) 1 0)))) - -(dshci dmulsl "Multiply long (signed)" - () - "dmuls.l $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 13)) - (sequence ((DI result)) - (set result (mul (ext DI rm) (ext DI rn))) - (set mach (subword SI result 0)) - (set macl (subword SI result 1)))) - -(dshci dmulul "Multiply long (unsigned)" - () - "dmulu.l $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 5)) - (sequence ((DI result)) - (set result (mul (zext DI rm) (zext DI rn))) - (set mach (subword SI result 0)) - (set macl (subword SI result 1)))) - -(dshci dt "Decrement and set" - () - "dt $rn" - (+ (f-op4 4) rn (f-sub8 16)) - (sequence () - (set rn (sub rn 1)) - (set tbit (eq rn 0)))) - -(dshci extsb "Sign extend byte" - () - "exts.b $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 14)) - (set rn (ext SI (subword QI rm 3)))) - -(dshci extsw "Sign extend word" - () - "exts.w $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 15)) - (set rn (ext SI (subword HI rm 1)))) - -(dshci extub "Zero extend byte" - () - "extu.b $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 12)) - (set rn (zext SI (subword QI rm 3)))) - -(dshci extuw "Zero etxend word" - () - "extu.w $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 13)) - (set rn (zext SI (subword HI rm 1)))) - -(dshci fabs "Floating point absolute" - (FP-INSN) - "fabs $fsdn" - (+ (f-op4 15) fsdn (f-sub8 #x5d)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_fabsd" (dr fsdn))) - (set fsdn (c-call SF "sh64_fabss" fsdn)))) - -(dshci fadd "Floating point add" - (FP-INSN) - "fadd $fsdm, $fsdn" - (+ (f-op4 15) fsdn fsdm (f-sub4 0)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_faddd" (dr fsdm) (dr fsdn))) - (set fsdn (c-call SF "sh64_fadds" fsdm fsdn)))) - -(dshci fcmpeq "Floating point compare equal" - (FP-INSN) - "fcmp/eq $fsdm, $fsdn" - (+ (f-op4 15) fsdn fsdm (f-sub4 4)) - (if prbit - (set tbit (c-call BI "sh64_fcmpeqd" (dr fsdm) (dr fsdn))) - (set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn)))) - -(dshci fcmpgt "Floating point compare greater than" - (FP-INSN) - "fcmp/gt $fsdm, $fsdn" - (+ (f-op4 15) fsdn fsdm (f-sub4 5)) - (if prbit - (set tbit (c-call BI "sh64_fcmpgtd" (dr fsdn) (dr fsdm))) - (set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm)))) - -(dshci fcnvds "Floating point convert (double to single)" - (FP-INSN) - "fcnvds $drn, fpul" - (+ (f-op4 15) drn (f-8-1 10) (f-sub8 #xbd)) - (set fpul (c-call SF "sh64_fcnvds" drn))) - -(dshci fcnvsd "Floating point convert (single to double)" - (FP-INSN) - "fcnvsd fpul, $drn" - (+ (f-op4 15) drn (f-8-1 0) (f-sub8 #xad)) - (set drn (c-call DF "sh64_fcnvsd" fpul))) - -(dshci fdiv "Floating point divide" - (FP-INSN) - "fdiv $fsdm, $fsdn" - (+ (f-op4 15) fsdn fsdm (f-sub4 3)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_fdivd" (dr fsdn) (dr fsdm))) - (set fsdn (c-call SF "sh64_fdivs" fsdn fsdm)))) - -(dshci fipr "Floating point inner product" - (FP-INSN) - "fipr $fvm, $fvn" - (+ (f-op4 15) fvn fvm (f-sub8 #xed)) - (sequence ((QI m) (QI n) (SF res)) - (set m (index-of fvm)) - (set n (index-of fvn)) - (set res (c-call SF "sh64_fmuls" fvm fvn)) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 1)) (reg h-frc (add n 1))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 2)) (reg h-frc (add n 2))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 3)) (reg h-frc (add n 3))))) - (set (reg h-frc (add n 3)) res))) - -(dshci flds "Floating point load status register" - (FP-INSN) - "flds $frn" - (+ (f-op4 15) frn (f-sub8 #x1d)) - (set fpul frn)) - -(dshci fldi0 "Floating point load immediate 0.0" - (FP-INSN) - "fldi0 $frn" - (+ (f-op4 15) frn (f-sub8 #x8d)) - (set frn (c-call SF "sh64_fldi0"))) - -(dshci fldi1 "Floating point load immediate 1.0" - (FP-INSN) - "fldi1 $frn" - (+ (f-op4 15) frn (f-sub8 #x9d)) - (set frn (c-call SF "sh64_fldi1"))) - -(dshci float "Floating point integer conversion" - (FP-INSN) - "float fpul, $fsdn" - (+ (f-op4 15) fsdn (f-sub8 #x2d)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_floatld" fpul)) - (set fsdn (c-call SF "sh64_floatls" fpul)))) - -(dshci fmac "Floating point multiply and accumulate" - (FP-INSN) - "fmac fr0, $frm, $frn" - (+ (f-op4 15) frn frm (f-sub4 14)) - (set frn (c-call SF "sh64_fmacs" (reg h-frc 0) frm frn))) - -(define-pmacro (even x) (eq (and x 1) 0)) -(define-pmacro (odd x) (eq (and x 1) 1)) -(define-pmacro (extd x) (odd (index-of x))) - -(dshci fmov1 "Floating point move (register to register)" - (FP-INSN) - "fmov $frm, $frn" - (+ (f-op4 15) frn frm (f-sub4 12)) - (if (not szbit) - ; single precision operation - (set frn frm) - ; double or extended operation - (if (extd frm) - (if (extd frn) - (set (xd frn) (xd frm)) - (set (dr frn) (xd frm))) - (if (extd frn) - (set (xd frn) (dr frm)) - (set (dr frn) (dr frm)))))) - -(dshci fmov2 "Floating point load" - (FP-INSN) - "fmov @$rm, $frn" - (+ (f-op4 15) frn rm (f-sub4 8)) - (if (not szbit) - ; single precision operation - (set frn (mem SF rm)) - ; double or extended operation - (if (extd frn) - (set (xd frn) (mem DF rm)) - (set (dr frn) (mem DF rm))))) - -(dshci fmov3 "Floating point load (post-increment)" - (FP-INSN) - "fmov @${rm}+, frn" - (+ (f-op4 15) frn rm (f-sub4 9)) - (if (not szbit) - ; single precision operation - (sequence () - (set frn (mem SF rm)) - (set rm (add rm 4))) - ; double or extended operation - (sequence () - (if (extd frn) - (set (xd frn) (mem DF rm)) - (set (dr frn) (mem DF rm))) - (set rm (add rm 8))))) - -(dshci fmov4 "Floating point load (register/register indirect)" - (FP-INSN) - "fmov @(r0, $rm), $frn" - (+ (f-op4 15) frn rm (f-sub4 6)) - (if (not szbit) - ; single precision operation - (set frn (mem SF (add r0 rm))) - ; double or extended operation - (if (extd frn) - (set (xd frn) (mem DF (add r0 rm))) - (set (dr frn) (mem DF (add r0 rm)))))) - -(dshci fmov5 "Floating point store" - (FP-INSN) - "fmov $frm, @$rn" - (+ (f-op4 15) rn frm (f-sub4 10)) - (if (not szbit) - ; single precision operation - (set (mem SF rn) frm) - ; double or extended operation - (if (extd frm) - (set (mem DF rn) (xd frm)) - (set (mem DF rn) (dr frm))))) - -(dshci fmov6 "Floating point store (pre-decrement)" - (FP-INSN) - "fmov $frm, @-$rn" - (+ (f-op4 15) rn frm (f-sub4 11)) - (if (not szbit) - ; single precision operation - (sequence () - (set rn (sub rn 4)) - (set (mem SF rn) frm)) - ; double or extended operation - (sequence () - (set rn (sub rn 8)) - (if (extd frm) - (set (mem DF rn) (xd frm)) - (set (mem DF rn) (dr frm)))))) - -(dshci fmov7 "Floating point store (register/register indirect)" - (FP-INSN) - "fmov $frm, @(r0, $rn)" - (+ (f-op4 15) rn frm (f-sub4 7)) - (if (not szbit) - ; single precision operation - (set (mem SF (add r0 rn)) frm) - ; double or extended operation - (if (extd frm) - (set (mem DF (add r0 rn)) (xd frm)) - (set (mem DF (add r0 rn)) (dr frm))))) - -(dshci fmul "Floating point multiply" - (FP-INSN) - "fmul $fsdm, $fsdn" - (+ (f-op4 15) fsdn fsdm (f-sub4 2)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_fmuld" (dr fsdm) (dr fsdn))) - (set fsdn (c-call SF "sh64_fmuls" fsdm fsdn)))) - -(dshci fneg "Floating point negate" - (FP-INSN) - "fneg $fsdn" - (+ (f-op4 15) fsdn (f-sub8 #x4d)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_fnegd" (dr fsdn))) - (set fsdn (c-call SF "sh64_fnegs" fsdn)))) - -(dshci frchg "Toggle floating point register banks" - (FP-INSN) - "frchg" - (+ (f-op16 #xfbfd)) - (set frbit (not frbit))) - -(dshci fschg "Set size of floating point transfers" - (FP-INSN) - "fschg" - (+ (f-op16 #xf3fd)) - (set szbit (not szbit))) - -(dshci fsqrt "Floating point square root" - (FP-INSN) - "fsqrt $fsdn" - (+ (f-op4 15) fsdn (f-sub8 #x6d)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_fsqrtd" (dr fsdn))) - (set fsdn (c-call SF "sh64_fsqrts" fsdn)))) - -(dshci fsts "Floating point store status register" - (FP-INSN) - "fsts fpul, $frn" - (+ (f-op4 15) frn (f-sub8 13)) - (set frn fpul)) - -(dshci fsub "Floating point subtract" - (FP-INSN) - "fsub $fsdm, $fsdn" - (+ (f-op4 15) fsdn fsdm (f-sub4 1)) - (if prbit - (set (dr fsdn) (c-call DF "sh64_fsubd" (dr fsdn) (dr fsdm))) - (set fsdn (c-call SF "sh64_fsubs" fsdn fsdm)))) - -(dshci ftrc "Floating point truncate" - (FP-INSN) - "ftrc $fsdn, fpul" - (+ (f-op4 15) fsdn (f-sub8 #x3d)) - (set fpul (if SF prbit - (c-call SF "sh64_ftrcdl" (dr fsdn)) - (c-call SF "sh64_ftrcsl" fsdn)))) - -(dshci ftrv "Floating point transform vector" - (FP-INSN) - "ftrv xmtrx, $fvn" - (+ (f-op4 15) fvn (f-sub10 #x1fd)) - (sequence ((QI n) (SF res)) - (set n (index-of fvn)) - (set res (c-call SF "sh64_fmuls" (reg h-xf 0) (reg h-frc n))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 4) (reg h-frc (add n 1))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 8) (reg h-frc (add n 2))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 12) (reg h-frc (add n 3))))) - (set (reg h-frc n) res) - (set res (c-call SF "sh64_fmuls" (reg h-xf 1) (reg h-frc n))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 5) (reg h-frc (add n 1))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 9) (reg h-frc (add n 2))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 13) (reg h-frc (add n 3))))) - (set (reg h-frc (add n 1)) res) - (set res (c-call SF "sh64_fmuls" (reg h-xf 2) (reg h-frc n))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 6) (reg h-frc (add n 1))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 10) (reg h-frc (add n 2))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 14) (reg h-frc (add n 3))))) - (set (reg h-frc (add n 2)) res) - (set res (c-call SF "sh64_fmuls" (reg h-xf 3) (reg h-frc n))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 7) (reg h-frc (add n 1))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 11) (reg h-frc (add n 2))))) - (set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 15) (reg h-frc (add n 3))))) - (set (reg h-frc (add n 3)) res))) - -(dshci jmp "Jump" - () - "jmp @$rn" - (+ (f-op4 4) rn (f-sub8 43)) - (delay 1 (set pc rn))) - -(dshci jsr "Jump to subroutine" - () - "jsr @$rn" - (+ (f-op4 4) rn (f-sub8 11)) - (delay 1 (sequence () - (set pr (add pc 4)) - (set pc rn)))) - -(dshci ldc "Load control register (GBR)" - () - "ldc $rn, gbr" - (+ (f-op4 4) rn (f-sub8 30)) - (set gbr rn)) - -(dshci ldcl "Load control register (GBR)" - () - "ldc.l @${rn}+, gbr" - (+ (f-op4 4) rn (f-sub8 39)) - (sequence () - (set gbr (mem SI rn)) - (set rn (add rn 4)))) - -(dshci lds-fpscr "Load status register (FPSCR)" - () - "lds $rn, fpscr" - (+ (f-op4 4) rn (f-sub8 106)) - (set fpscr rn)) - -(dshci ldsl-fpscr "Load status register (FPSCR)" - () - "lds.l @${rn}+, fpscr" - (+ (f-op4 4) rn (f-sub8 102)) - (sequence () - (set fpscr (mem SI rn)) - (set rn (add rn 4)))) - -(dshci lds-fpul "Load status register (FPUL)" - () - "lds $rn, fpul" - (+ (f-op4 4) rn (f-sub8 90)) - ; Use subword to convert rn's mode. - (set fpul (subword SF rn 0))) - -(dshci ldsl-fpul "Load status register (FPUL)" - () - "lds.l @${rn}+, fpul" - (+ (f-op4 4) rn (f-sub8 86)) - (sequence () - (set fpul (mem SF rn)) - (set rn (add rn 4)))) - -(dshci lds-mach "Load status register (MACH)" - () - "lds $rn, mach" - (+ (f-op4 4) rn (f-sub8 10)) - (set mach rn)) - -(dshci ldsl-mach "Load status register (MACH), post-increment" - () - "lds.l @${rn}+, mach" - (+ (f-op4 4) rn (f-sub8 6)) - (sequence () - (set mach (mem SI rn)) - (set rn (add rn 4)))) - -(dshci lds-macl "Load status register (MACL)" - () - "lds $rn, macl" - (+ (f-op4 4) rn (f-sub8 26)) - (set macl rn)) - -(dshci ldsl-macl "Load status register (MACL), post-increment" - () - "lds.l @${rn}+, macl" - (+ (f-op4 4) rn (f-sub8 22)) - (sequence () - (set macl (mem SI rn)) - (set rn (add rn 4)))) - -(dshci lds-pr "Load status register (PR)" - () - "lds $rn, pr" - (+ (f-op4 4) rn (f-sub8 42)) - (set pr rn)) - -(dshci ldsl-pr "Load status register (PR), post-increment" - () - "lds.l @${rn}+, pr" - (+ (f-op4 4) rn (f-sub8 38)) - (sequence () - (set pr (mem SI rn)) - (set rn (add rn 4)))) - -(dshci macl "Multiply and accumulate (long)" - () - "mac.l @${rm}+, @${rn}+" - (+ (f-op4 0) rn rm (f-sub4 15)) - (sequence ((DI tmpry) (DI mac) (DI result) (SI x) (SI y)) - (set x (mem SI rn)) - (set rn (add rn 4)) - (if (eq (index-of rn) (index-of rm)) - (sequence () - (set rn (add rn 4)) - (set rm (add rm 4)))) - (set y (mem SI rm)) - (set rm (add rm 4)) - (set tmpry (mul (zext DI x) (zext DI y))) - (set mac (or DI (sll (zext DI mach) 32) (zext DI macl))) - (set result (add mac tmpry)) - (sequence () - (if sbit - (sequence ((SI min) (SI max)) - (set max (srl (inv DI 0) 16)) - ; Preserve bit 48 for sign. - (set min (srl (inv DI 0) 15)) - (if (gt result max) - (set result max) - (if (lt result min) - (set result min))))) - (set mach (subword SI result 0)) - (set macl (subword SI result 1))))) - -(dshci macw "Multiply and accumulate (word)" - () - "mac.w @${rm}+, @${rn}+" - (+ (f-op4 4) rn rm (f-sub4 15)) - (sequence ((SI tmpry) (DI mac) (DI result) (HI x) (HI y)) - (set x (mem HI rn)) - (set rn (add rn 2)) - (if (eq (index-of rn) (index-of rm)) - (sequence () - (set rn (add rn 2)) - (set rm (add rm 2)))) - (set y (mem HI rm)) - (set rm (add rm 2)) - (set tmpry (mul (zext SI x) (zext SI y))) - (if sbit - (sequence () - (if (add-oflag tmpry macl 0) - (set mach 1)) - (set macl (add tmpry macl))) - (sequence () - (set mac (or DI (sll (zext DI mach) 32) (zext DI macl))) - (set result (add mac (ext DI tmpry))) - (set mach (subword SI result 0)) - (set macl (subword SI result 1)))))) - -(dshci mov "Move" - () - "mov $rm64, $rn64" - (+ (f-op4 6) rn64 rm64 (f-sub4 3)) - (set rn64 rm64)) - -(dshci movi "Move immediate" - () - "mov #$imm8, $rn" - (+ (f-op4 14) rn imm8) - (set rn (ext DI (and QI imm8 255)))) - -(dshci movb1 "Store byte to memory (register indirect w/ zero displacement)" - () - "mov.b $rm, @$rn" - (+ (f-op4 2) rn rm (f-sub4 0)) - (set (mem UQI rn) (subword UQI rm 3))) - -(dshci movb2 "Store byte to memory (register indirect w/ pre-decrement)" - () - "mov.b $rm, @-$rn" - (+ (f-op4 2) rn rm (f-sub4 4)) - (sequence ((DI addr)) - (set addr (sub rn 1)) - (set (mem UQI addr) (subword UQI rm 3)) - (set rn addr))) - -(dshci movb3 "Store byte to memory (register/register indirect)" - () - "mov.b $rm, @(r0,$rn)" - (+ (f-op4 0) rn rm (f-sub4 4)) - (set (mem UQI (add r0 rn)) (subword UQI rm 3))) - -(dshci movb4 "Store byte to memory (GBR-relative w/ displacement)" - () - "mov.b r0, @($imm8, gbr)" - (+ (f-op8 #xc0) imm8) - (sequence ((DI addr)) - (set addr (add gbr imm8)) - (set (mem UQI addr) (subword UQI r0 3)))) - -(dshci movb5 "Store byte to memory (register indirect w/ displacement)" - () - "mov.b r0, @($imm4, $rm)" - (+ (f-op8 #x80) rm imm4) - (sequence ((DI addr)) - (set addr (add rm imm4)) - (set (mem UQI addr) (subword UQI r0 3)))) - -(dshci movb6 "Load byte from memory (register indirect w/ zero displacement)" - () - "mov.b @$rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 0)) - (set rn (ext SI (mem QI rm)))) - -(dshci movb7 "Load byte from memory (register indirect w/ post-increment)" - () - "mov.b @${rm}+, $rn" - (+ (f-op4 6) rn rm (f-sub4 4)) - (sequence ((QI data)) - (set data (mem QI rm)) - (if (eq (index-of rm) (index-of rn)) - (set rm (ext SI data)) - (set rm (add rm 1))) - (set rn (ext SI data)))) - -(dshci movb8 "Load byte from memory (register/register indirect)" - () - "mov.b @(r0, $rm), $rn" - (+ (f-op4 0) rn rm (f-sub4 12)) - (set rn (ext SI (mem QI (add r0 rm))))) - -(dshci movb9 "Load byte from memory (GBR-relative with displacement)" - () - "mov.b @($imm8, gbr), r0" - (+ (f-op8 #xc4) imm8) - (set r0 (ext SI (mem QI (add gbr imm8))))) - -(dshci movb10 "Load byte from memory (register indirect w/ displacement)" - () - "mov.b @($imm4, $rm), r0" - (+ (f-op8 #x84) rm imm4) - (set r0 (ext SI (mem QI (add rm imm4))))) - -(dshci movl1 "Store long word to memory (register indirect w/ zero displacement)" - () - "mov.l $rm, @$rn" - (+ (f-op4 2) rn rm (f-sub4 2)) - (set (mem SI rn) rm)) - -(dshci movl2 "Store long word to memory (register indirect w/ pre-decrement)" - () - "mov.l $rm, @-$rn" - (+ (f-op4 2) rn rm (f-sub4 6)) - (sequence ((SI addr)) - (set addr (sub rn 4)) - (set (mem SI addr) rm) - (set rn addr))) - -(dshci movl3 "Store long word to memory (register/register indirect)" - () - "mov.l $rm, @(r0, $rn)" - (+ (f-op4 0) rn rm (f-sub4 6)) - (set (mem SI (add r0 rn)) rm)) - -(dshci movl4 "Store long word to memory (GBR-relative w/ displacement)" - () - "mov.l r0, @($imm8x4, gbr)" - (+ (f-op8 #xc2) imm8x4) - (set (mem SI (add gbr imm8x4)) r0)) - -(dshci movl5 "Store long word to memory (register indirect w/ displacement)" - () - "mov.l $rm, @($imm4x4, $rn)" - (+ (f-op4 1) rn rm imm4x4) - (set (mem SI (add rn imm4x4)) rm)) - -(dshci movl6 "Load long word to memory (register indirect w/ zero displacement)" - () - "mov.l @$rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 2)) - (set rn (mem SI rm))) - -(dshci movl7 "Load long word from memory (register indirect w/ post-increment)" - () - "mov.l @${rm}+, $rn" - (+ (f-op4 6) rn rm (f-sub4 6)) - (sequence () - (set rn (mem SI rm)) - (if (eq (index-of rm) (index-of rn)) - (set rm rn) - (set rm (add rm 4))))) - -(dshci movl8 "Load long word from memory (register/register indirect)" - () - "mov.l @(r0, $rm), $rn" - (+ (f-op4 0) rn rm (f-sub4 14)) - (set rn (mem SI (add r0 rm)))) - -(dshci movl9 "Load long word from memory (GBR-relative w/ displacement)" - () - "mov.l @($imm8x4, gbr), r0" - (+ (f-op8 #xc6) imm8x4) - (set r0 (mem SI (add gbr imm8x4)))) - -(dshci movl10 "Load long word from memory (PC-relative w/ displacement)" - (ILLSLOT) - "mov.l @($imm8x4, pc), $rn" - (+ (f-op4 13) rn imm8x4) - (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3)))))) - -(dshci movl11 "Load long word from memory (register indirect w/ displacement)" - () - "mov.l @($imm4x4, $rm), $rn" - (+ (f-op4 5) rn rm imm4x4) - (set rn (mem SI (add rm imm4x4)))) - -(dshci movw1 "Store word to memory (register indirect w/ zero displacement)" - () - "mov.w $rm, @$rn" - (+ (f-op4 2) rn rm (f-sub4 1)) - (set (mem HI rn) (subword HI rm 1))) - -(dshci movw2 "Store word to memory (register indirect w/ pre-decrement)" - () - "mov.w $rm, @-$rn" - (+ (f-op4 2) rn rm (f-sub4 5)) - (sequence ((DI addr)) - (set addr (sub rn 2)) - (set (mem HI addr) (subword HI rm 1)) - (set rn addr))) - -(dshci movw3 "Store word to memory (register/register indirect)" - () - "mov.w $rm, @(r0, $rn)" - (+ (f-op4 0) rn rm (f-sub4 5)) - (set (mem HI (add r0 rn)) (subword HI rm 1))) - -(dshci movw4 "Store word to memory (GBR-relative w/ displacement)" - () - "mov.w r0, @($imm8x2, gbr)" - (+ (f-op8 #xc1) imm8x2) - (set (mem HI (add gbr imm8x2)) (subword HI r0 1))) - -(dshci movw5 "Store word to memory (register indirect w/ displacement)" - () - "mov.w r0, @($imm4x2, $rn)" - (+ (f-op8 #x81) rn imm4x2) - (set (mem HI (add rn imm4x2)) (subword HI r0 1))) - -(dshci movw6 "Load word from memory (register indirect w/ zero displacement)" - () - "mov.w @$rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 1)) - (set rn (ext SI (mem HI rm)))) - -(dshci movw7 "Load word from memory (register indirect w/ post-increment)" - () - "mov.w @${rm}+, $rn" - (+ (f-op4 6) rn rm (f-sub4 5)) - (sequence ((HI data)) - (set data (mem HI rm)) - (if (eq (index-of rm) (index-of rn)) - (set rm (ext SI data)) - (set rm (add rm 2))) - (set rn (ext SI data)))) - -(dshci movw8 "Load word from memory (register/register indirect)" - () - "mov.w @(r0, $rm), $rn" - (+ (f-op4 0) rn rm (f-sub4 13)) - (set rn (ext SI (mem HI (add r0 rm))))) - -(dshci movw9 "Load word from memory (GBR-relative w/ displacement)" - () - "mov.w @($imm8x2, gbr), r0" - (+ (f-op8 #xc5) imm8x2) - (set r0 (ext SI (mem HI (add gbr imm8x2))))) - -(dshci movw10 "Load word from memory (PC-relative w/ displacement)" - (ILLSLOT) - "mov.w @($imm8x2, pc), $rn" - (+ (f-op4 9) rn imm8x2) - (set rn (ext SI (mem HI (add (add pc 4) imm8x2))))) - -(dshci movw11 "Load word from memory (register indirect w/ displacement)" - () - "mov.w @($imm4x2, $rm), r0" - (+ (f-op8 #x85) rm imm4x2) - (set r0 (ext SI (mem HI (add rm imm4x2))))) - -(dshci mova "Move effective address" - (ILLSLOT) - "mova @($imm8x4, pc), r0" - (+ (f-op8 #xc7) imm8x4) - (set r0 (add (and (add pc 4) (inv 3)) imm8x4))) - -(dshci movcal "Move with cache block allocation" - () - "movca.l r0, @$rn" - (+ (f-op4 0) rn (f-sub8 #xc3)) - (set (mem SI rn) r0)) - -(dshci movt "Move t-bit" - () - "movt $rn" - (+ (f-op4 0) rn (f-sub8 41)) - (set rn (zext SI tbit))) - -(dshci mull "Multiply" - () - "mul.l $rm, $rn" - (+ (f-op4 0) rn rm (f-sub4 7)) - (set macl (mul rm rn))) - -(dshci mulsw "Multiply words (signed)" - () - "muls.w $rm, $rn" - (+ (f-op4 2) rn rm (f-sub4 15)) - (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1))))) - -(dshci muluw "Multiply words (unsigned)" - () - "mulu.w $rm, $rn" - (+ (f-op4 2) rn rm (f-sub4 14)) - (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))) - -(dshci neg "Negate" - () - "neg $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 11)) - (set rn (neg rm))) - -(dshci negc "Negate with carry" - () - "negc $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 10)) - (sequence ((BI flag)) - (set flag (sub-cflag 0 rm tbit)) - (set rn (subc 0 rm tbit)) - (set tbit flag))) - -(dshci nop "No operation" - () - "nop" - (+ (f-op16 9)) - (nop)) - -(dshci not "Bitwise NOT" - () - "not $rm64, $rn64" - (+ (f-op4 6) rn64 rm64 (f-sub4 7)) - (set rn64 (inv rm64))) - -(dshci ocbi "Invalidate operand cache block" - () - "ocbi @$rn" - (+ (f-op4 0) rn (f-sub8 147)) - (unimp "ocbi")) - -(dshci ocbp "Purge operand cache block" - () - "ocbp @$rn" - (+ (f-op4 0) rn (f-sub8 163)) - (unimp "ocbp")) - -(dshci ocbwb "Write back operand cache block" - () - "ocbwb @$rn" - (+ (f-op4 0) rn (f-sub8 179)) - (unimp "ocbwb")) - -(dshci or "Bitwise OR" - () - "or $rm64, $rn64" - (+ (f-op4 2) rn64 rm64 (f-sub4 11)) - (set rn64 (or rm64 rn64))) - -(dshci ori "Bitwise OR immediate" - () - "or #$uimm8, r0" - (+ (f-op8 #xcb) uimm8) - (set r0 (or r0 (zext DI uimm8)))) - -(dshci orb "Bitwise OR immediate" - () - "or.b #$imm8, @(r0, gbr)" - (+ (f-op8 #xcf) imm8) - (sequence ((DI addr) (UQI data)) - (set addr (add r0 gbr)) - (set data (or (mem UQI addr) imm8)) - (set (mem UQI addr) data))) - -(dshci pref "Prefetch data" - () - "pref @$rn" - (+ (f-op4 0) rn (f-sub8 131)) - (unimp "pref")) - -(dshci rotcl "Rotate with carry left" - () - "rotcl $rn" - (+ (f-op4 4) rn (f-sub8 36)) - (sequence ((BI temp)) - (set temp (srl rn 31)) - (set rn (or (sll rn 1) tbit)) - (set tbit (if BI temp 1 0)))) - -(dshci rotcr "Rotate with carry right" - () - "rotcr $rn" - (+ (f-op4 4) rn (f-sub8 37)) - (sequence ((BI lsbit) (SI temp)) - (set lsbit (if BI (eq (and rn 1) 0) 0 1)) - (set temp tbit) - (set rn (or (srl rn 1) (sll temp 31))) - (set tbit (if BI lsbit 1 0)))) - -(dshci rotl "Rotate left" - () - "rotl $rn" - (+ (f-op4 4) rn (f-sub8 4)) - (sequence ((BI temp)) - (set temp (srl rn 31)) - (set rn (or (sll rn 1) temp)) - (set tbit (if BI temp 1 0)))) - -(dshci rotr "Rotate right" - () - "rotr $rn" - (+ (f-op4 4) rn (f-sub8 5)) - (sequence ((BI lsbit) (SI temp)) - (set lsbit (if BI (eq (and rn 1) 0) 0 1)) - (set temp lsbit) - (set rn (or (srl rn 1) (sll temp 31))) - (set tbit (if BI lsbit 1 0)))) - -(dshci rts "Return from subroutine" - () - "rts" - (+ (f-op16 11)) - (delay 1 (set pc pr))) - -(dshci sets "Set S-bit" - () - "sets" - (+ (f-op16 88)) - (set sbit 1)) - -(dshci sett "Set T-bit" - () - "sett" - (+ (f-op16 24)) - (set tbit 1)) - -(dshci shad "Shift arithmetic dynamic" - () - "shad $rm, $rn" - (+ (f-op4 4) rn rm (f-sub4 12)) - (sequence ((QI shamt)) - (set shamt (and QI rm 31)) - (if (ge rm 0) - (set rn (sll rn shamt)) - (if (ne shamt 0) - (set rn (sra rn (sub 32 shamt))) - (if (lt rn 0) - (set rn (neg 1)) - (set rn 0)))))) - -(dshci shal "Shift left arithmetic one bit" - () - "shal $rn" - (+ (f-op4 4) rn (f-sub8 32)) - (sequence ((BI t)) - (set t (srl rn 31)) - (set rn (sll rn 1)) - (set tbit (if BI t 1 0)))) - -(dshci shar "Shift right arithmetic one bit" - () - "shar $rn" - (+ (f-op4 4) rn (f-sub8 33)) - (sequence ((BI t)) - (set t (and rn 1)) - (set rn (sra rn 1)) - (set tbit (if BI t 1 0)))) - -(dshci shld "Shift logical dynamic" - () - "shld $rm, $rn" - (+ (f-op4 4) rn rm (f-sub4 13)) - (sequence ((QI shamt)) - (set shamt (and QI rm 31)) - (if (ge rm 0) - (set rn (sll rn shamt)) - (if (ne shamt 0) - (set rn (srl rn (sub 32 shamt))) - (set rn 0))))) - -(dshci shll "Shift left logical one bit" - () - "shll $rn" - (+ (f-op4 4) rn (f-sub8 0)) - (sequence ((BI t)) - (set t (srl rn 31)) - (set rn (sll rn 1)) - (set tbit (if BI t 1 0)))) - -(dshci shll2 "Shift left logical two bits" - () - "shll2 $rn" - (+ (f-op4 4) rn (f-sub8 8)) - (set rn (sll rn 2))) - -(dshci shll8 "Shift left logical eight bits" - () - "shll8 $rn" - (+ (f-op4 4) rn (f-sub8 24)) - (set rn (sll rn 8))) - -(dshci shll16 "Shift left logical sixteen bits" - () - "shll16 $rn" - (+ (f-op4 4) rn (f-sub8 40)) - (set rn (sll rn 16))) - -(dshci shlr "Shift right logical one bit" - () - "shlr $rn" - (+ (f-op4 4) rn (f-sub8 1)) - (sequence ((BI t)) - (set t (and rn 1)) - (set rn (srl rn 1)) - (set tbit (if BI t 1 0)))) - -(dshci shlr2 "Shift right logical two bits" - () - "shlr2 $rn" - (+ (f-op4 4) rn (f-sub8 9)) - (set rn (srl rn 2))) - -(dshci shlr8 "Shift right logical eight bits" - () - "shlr8 $rn" - (+ (f-op4 4) rn (f-sub8 25)) - (set rn (srl rn 8))) - -(dshci shlr16 "Shift right logical sixteen bits" - () - "shlr16 $rn" - (+ (f-op4 4) rn (f-sub8 41)) - (set rn (srl rn 16))) - -(dshci stc-gbr "Store control register (GBR)" - () - "stc gbr, $rn" - (+ (f-op4 0) rn (f-sub8 18)) - (set rn gbr)) - -(dshci stcl-gbr "Store control register (GBR)" - () - "stc.l gbr, @-$rn" - (+ (f-op4 4) rn (f-sub8 19)) - (sequence ((DI addr)) - (set addr (sub rn 4)) - (set (mem SI addr) gbr) - (set rn addr))) - -(dshci sts-fpscr "Store status register (FPSCR)" - () - "sts fpscr, $rn" - (+ (f-op4 0) rn (f-sub8 106)) - (set rn fpscr)) - -(dshci stsl-fpscr "Store status register (FPSCR)" - () - "sts.l fpscr, @-$rn" - (+ (f-op4 4) rn (f-sub8 98)) - (sequence ((DI addr)) - (set addr (sub rn 4)) - (set (mem SI addr) fpscr) - (set rn addr))) - -(dshci sts-fpul "Store status register (FPUL)" - () - "sts fpul, $rn" - (+ (f-op4 0) rn (f-sub8 90)) - (set rn (subword SI fpul 0))) - -(dshci stsl-fpul "Store status register (FPUL)" - () - "sts.l fpul, @-$rn" - (+ (f-op4 4) rn (f-sub8 82)) - (sequence ((DI addr)) - (set addr (sub rn 4)) - (set (mem SF addr) fpul) - (set rn addr))) - -(dshci sts-mach "Store status register (MACH)" - () - "sts mach, $rn" - (+ (f-op4 0) rn (f-sub8 10)) - (set rn mach)) - -(dshci stsl-mach "Store status register (MACH)" - () - "sts.l mach, @-$rn" - (+ (f-op4 4) rn (f-sub8 2)) - (sequence ((DI addr)) - (set addr (sub rn 4)) - (set (mem SI addr) mach) - (set rn addr))) - -(dshci sts-macl "Store status register (MACL)" - () - "sts macl, $rn" - (+ (f-op4 0) rn (f-sub8 26)) - (set rn macl)) - -(dshci stsl-macl "Store status register (MACL)" - () - "sts.l macl, @-$rn" - (+ (f-op4 4) rn (f-sub8 18)) - (sequence ((DI addr)) - (set addr (sub rn 4)) - (set (mem SI addr) macl) - (set rn addr))) - -(dshci sts-pr "Store status register (PR)" - () - "sts pr, $rn" - (+ (f-op4 0) rn (f-sub8 42)) - (set rn pr)) - -(dshci stsl-pr "Store status register (PR)" - () - "sts.l pr, @-$rn" - (+ (f-op4 4) rn (f-sub8 34)) - (sequence ((DI addr)) - (set addr (sub rn 4)) - (set (mem SI addr) pr) - (set rn addr))) - -(dshci sub "Subtract" - () - "sub $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 8)) - (set rn (sub rn rm))) - -(dshci subc "Subtract and detect carry" - () - "subc $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 10)) - (sequence ((BI flag)) - (set flag (sub-cflag rn rm tbit)) - (set rn (subc rn rm tbit)) - (set tbit flag))) - -(dshci subv "Subtract and detect overflow" - () - "subv $rm, $rn" - (+ (f-op4 3) rn rm (f-sub4 11)) - (sequence ((BI t)) - (set t (sub-oflag rn rm 0)) - (set rn (sub rn rm)) - (set tbit (if BI t 1 0)))) - -(dshci swapb "Swap bytes" - () - "swap.b $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 8)) - (sequence ((UHI top-half) (UQI byte1) (UQI byte0)) - (set top-half (subword HI rm 0)) - (set byte1 (subword QI rm 2)) - (set byte0 (subword QI rm 3)) - (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1))))) - -(dshci swapw "Swap words" - () - "swap.w $rm, $rn" - (+ (f-op4 6) rn rm (f-sub4 9)) - (set rn (or (srl rm 16) (sll rm 16)))) - -(dshci tasb "Test and set byte" - () - "tas.b @$rn" - (+ (f-op4 4) rn (f-sub8 27)) - (sequence ((UQI byte)) - (set byte (mem UQI rn)) - (set tbit (if BI (eq byte 0) 1 0)) - (set byte (or byte 128)) - (set (mem UQI rn) byte))) - -(dshci trapa "Trap" - (ILLSLOT) - "trapa #$uimm8" - (+ (f-op8 #xc3) uimm8) - (c-call "sh64_compact_trapa" uimm8 pc)) - -(dshci tst "Test and set t-bit" - () - "tst $rm, $rn" - (+ (f-op4 2) rn rm (f-sub4 8)) - (set tbit (if BI (eq (and rm rn) 0) 1 0))) - -(dshci tsti "Test and set t-bit immediate" - () - "tst #$uimm8, r0" - (+ (f-op8 #xc8) uimm8) - (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0))) - -(dshci tstb "Test and set t-bit immedate with memory byte" - () - "tst.b #$imm8, @(r0, gbr)" - (+ (f-op8 #xcc) imm8) - (sequence ((DI addr)) - (set addr (add r0 gbr)) - (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0)))) - -(dshci xor "Exclusive OR" - () - "xor $rm64, $rn64" - (+ (f-op4 2) rn64 rm64 (f-sub4 10)) - (set rn64 (xor rn64 rm64))) - -(dshci xori "Exclusive OR immediate" - () - "xor #$uimm8, r0" - (+ (f-op8 #xca) uimm8) - (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8)))) - -(dshci xorb "Exclusive OR immediate with memory byte" - () - "xor.b #$imm8, @(r0, gbr)" - (+ (f-op8 #xce) imm8) - (sequence ((DI addr) (UQI data)) - (set addr (add r0 gbr)) - (set data (xor (mem UQI addr) imm8)) - (set (mem UQI addr) data))) - -(dshci xtrct "Extract" - () - "xtrct $rm, $rn" - (+ (f-op4 2) rn rm (f-sub4 13)) - (set rn (or (sll rm 16) (srl rn 16)))) diff --git a/binutils-2.24/cpu/sh64-media.cpu b/binutils-2.24/cpu/sh64-media.cpu deleted file mode 100644 index 80dd74a8..00000000 --- a/binutils-2.24/cpu/sh64-media.cpu +++ /dev/null @@ -1,1733 +0,0 @@ -; Hitachi SHmedia instruction set description. -*- Scheme -*- -; -; Copyright 2000, 2001, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; developed under contract from Hitachi -; Semiconductor (America) Inc. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - - -; dshmf -- define-normal-sh-media-field - -(define-pmacro (dshmf xname xcomment ignored xstart xlength) - (dnf xname xcomment ((ISA media)) xstart xlength)) - -; dshmop -- define-normal-sh-media-operand - -(define-pmacro (dshmop xname xcomment ignored xhardware xfield) - (dnop xname xcomment ((ISA media)) xhardware xfield)) - -; dnshmi -- define-normal-sh-media-insn - -(define-pmacro (dshmi xname xcomment xattrs xsyntax xformat xsemantics) - (define-insn - (name xname) - (comment xcomment) - (.splice attrs (.unsplice xattrs) (ISA media)) - (syntax xsyntax) - (format xformat) - (semantics xsemantics))) - -; Saturation functions. -; Force a value `i' into words `n' bits wide. -; See Hitachi SH-5 CPU core, volume 2, p. 25 for details. - -; saturate -- signed saturatation function - -(define-pmacro (saturate mode n i) - (if mode (lt i (neg mode (sll mode 1 (sub n 1)))) - (neg (sll mode 1 (sub n 1))) - (if mode (lt i (sll mode 1 (sub n 1))) - i - (sub mode (sll mode 1 (sub n 1)) 1)))) - -; usaturate -- unsigned saturation function - -(define-pmacro (usaturate mode n i) - (if mode (lt i (const mode 0)) - (const mode 0) - (if mode (lt i (sll mode 1 n)) - i - (sub mode (sll mode 1 n) 1)))) - - -; Ifields. - -(dshmf f-op "Opcode" () 31 6) -(dshmf f-ext "Extension opcode" () 19 4) -(dshmf f-rsvd "Reserved" (RESERVED) 3 4) - -(dshmf f-left "Left register" () 25 6) -(dshmf f-right "Right register" () 15 6) -(dshmf f-dest "Destination register" () 9 6) - -(define-multi-ifield - (name f-left-right) - (comment "Left and right matched register pair") - (attrs (ISA media)) - (mode UINT) - (subfields f-left f-right) - (insert (sequence () - (set (ifield f-left) - (and (ifield f-left-right) 63)) - (set (ifield f-right) - (and (ifield f-left-right) 63)))) - (extract (set (ifield f-left-right) (ifield f-left))) -) - -(dshmf f-tra "Target register" () 6 3) -(dshmf f-trb "Target register" () 22 3) -(dshmf f-likely "Likely bit" () 9 1) -(dshmf f-25 "Three unused bits at bit 25" () 25 3) -(dshmf f-8-2 "Two unused bits at bit 8" () 8 2) - -(df f-imm6 "Immediate value (6 bits)" ((ISA media)) 15 6 INT #f #f) -(df f-imm10 "Immediate value (10 bits)" ((ISA media)) 19 10 INT #f #f) -(df f-imm16 "Immediate value (16 bits)" ((ISA media)) 25 16 INT #f #f) - -(dshmf f-uimm6 "Immediate value (6 bits)" () 15 6) -(dshmf f-uimm16 "Immediate value (16 bits)" () 25 16) - -; Various displacement fields. -; The 10 bit field, for example, has different scaling for displacements. - -(df f-disp6 "Displacement (6 bits)" ((ISA media)) 15 6 INT #f #f) - -(df f-disp6x32 "Displacement (6 bits)" ((ISA media)) 15 6 INT - ((value pc) (sra SI value 5)) - ((value pc) (sll SI value 5))) - -(df f-disp10 "Displacement (10 bits)" ((ISA media)) 19 10 INT #f #f) - -(df f-disp10x8 "Displacement (10 bits)" ((ISA media)) 19 10 INT - ((value pc) (sra SI value 3)) - ((value pc) (sll SI value 3))) - -(df f-disp10x4 "Displacement (10 bits)" ((ISA media)) 19 10 INT - ((value pc) (sra SI value 2)) - ((value pc) (sll SI value 2))) - -(df f-disp10x2 "Displacement (10 bits)" ((ISA media)) 19 10 INT - ((value pc) (sra SI value 1)) - ((value pc) (sll SI value 1))) - -(df f-disp16 "Displacement (16 bits)" ((ISA media) PCREL-ADDR) 25 16 INT - ((value pc) (sra DI value 2)) - ((value pc) (add DI (sll DI value 2) pc))) - - -; Operands. - -(dshmop rm "Left general purpose reg" () h-gr f-left) -(dshmop rn "Right general purpose reg" () h-gr f-right) -(dshmop rd "Destination general purpose reg" () h-gr f-dest) - -(dshmop frg "Left single precision register" () h-fr f-left) -(dshmop frh "Right single precision register" () h-fr f-right) -(dshmop frf "Destination single precision reg" () h-fr f-dest) -(dshmop frgh "Single precision register pair" () h-fr f-left-right) - -(dshmop fpf "Pair of single precision registers" () h-fp f-dest) - -(dshmop fvg "Left single precision vector" () h-fv f-left) -(dshmop fvh "Right single precision vector" () h-fv f-right) -(dshmop fvf "Destination single precision vector" () h-fv f-dest) -(dshmop mtrxg "Left single precision matrix" () h-fmtx f-left) - -(dshmop drg "Left double precision register" () h-dr f-left) -(dshmop drh "Right double precision register" () h-dr f-right) -(dshmop drf "Destination double precision reg" () h-dr f-dest) -(dshmop drgh "Double precision register pair" () h-dr f-left-right) - -(dshmop fpscr "Floating point status register" () h-fpscr f-nil) -(dshmop crj "Control register j" () h-cr f-dest) -(dshmop crk "Control register k" () h-cr f-left) - -(dshmop tra "Target register a" () h-tr f-tra) -(dshmop trb "Target register b" () h-tr f-trb) - -(dshmop disp6 "Displacement (6 bits)" () h-sint f-disp6) -(dshmop disp6x32 "Displacement (6 bits, scale 32)" () h-sint f-disp6x32) -(dshmop disp10 "Displacement (10 bits)" () h-sint f-disp10) -(dshmop disp10x2 "Displacement (10 bits, scale 2)" () h-sint f-disp10x2) -(dshmop disp10x4 "Displacement (10 bits, scale 4)" () h-sint f-disp10x4) -(dshmop disp10x8 "Displacement (10 bits, scale 8)" () h-sint f-disp10x8) -(dshmop disp16 "Displacement (16 bits)" () h-sint f-disp16) - -(dshmop imm6 "Immediate (6 bits)" () h-sint f-imm6) -(dshmop imm10 "Immediate (10 bits)" () h-sint f-imm10) -(dshmop imm16 "Immediate (16 bits)" () h-sint f-imm16) -(dshmop uimm6 "Immediate (6 bits)" () h-uint f-uimm6) -(dshmop uimm16 "Unsigned immediate (16 bits)" () h-uint f-uimm16) - -; FIXME: provide these parse/print functions in `sh-media.opc'. - -(define-operand (name likely) (comment "Likely branch?") (attrs (ISA media)) - (type h-uint) (index f-likely) (handlers (parse "likely") (print "likely"))) - - -; Instructions. - -(dshmi add "Add" - () - "add $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 9) rn rd (f-rsvd 0)) - (set rd (add rm rn))) - -(dshmi addl "Add long" - () - "add.l $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 8) rn rd (f-rsvd 0)) - (set rd (add (subword SI rm 1) (subword SI rn 1)))) - -(dshmi addi "Add immediate" - () - "addi $rm, $disp10, $rd" - (+ (f-op 52) rm disp10 rd (f-rsvd 0)) - (set rd (add rm (ext DI disp10)))) - -(dshmi addil "Add immediate long" - () - "addi.l $rm, $disp10, $rd" - (+ (f-op 53) rm disp10 rd (f-rsvd 0)) - (set rd (ext DI (add (ext SI disp10) (subword SI rm 1))))) - -(dshmi addzl "Add zero extended long" - () - "addz.l $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 12) rn rd (f-rsvd 0)) - (set rd (zext DI (add (subword SI rm 1) (subword SI rn 1))))) - -(dshmi alloco "Allocate operand cache block" - () - "alloco $rm, $disp6x32" - (+ (f-op 56) rm (f-ext 4) disp6x32 (f-dest 63) (f-rsvd 0)) - (unimp "alloco")) - -(dshmi and "AND" - () - "and $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 11) rn rd (f-rsvd 0)) - (set rd (and rm rn))) - -(dshmi andc "AND complement" - () - "andc $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 15) rn rd (f-rsvd 0)) - (set rd (and rm (inv rn)))) - -(dshmi andi "AND immediate" - () - "andi $rm, $disp10, $rd" - (+ (f-op 54) rm disp10 rd (f-rsvd 0)) - (set rd (and rm (ext DI disp10)))) - -(dshmi beq "Branch if equal" - () - "beq$likely $rm, $rn, $tra" - (+ (f-op 25) rm (f-ext 1) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (eq rm rn) - (set pc tra))) - -(dshmi beqi "Branch if equal immediate" - () - "beqi$likely $rm, $imm6, $tra" - (+ (f-op 57) rm (f-ext 1) imm6 likely (f-8-2 0) tra (f-rsvd 0)) - (if (eq rm (ext DI imm6)) - (set pc tra))) - -(dshmi bge "Branch if greater than or equal" - () - "bge$likely $rm, $rn, $tra" - (+ (f-op 25) rm (f-ext 3) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (ge rm rn) - (set pc tra))) - -(dshmi bgeu "Branch if greater than or equal (unsigned comparison)" - () - "bgeu$likely $rm, $rn, $tra" - (+ (f-op 25) rm (f-ext 11) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (geu rm rn) - (set pc tra))) - -(dshmi bgt "Branch greater than" - () - "bgt$likely $rm, $rn, $tra" - (+ (f-op 25) rm (f-ext 7) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (gt rm rn) - (set pc tra))) - -(dshmi bgtu "Branch greater than (unsigned comparison)" - () - "bgtu$likely $rm, $rn, $tra" - (+ (f-op 25) rm (f-ext 15) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (gtu rm rn) - (set pc tra))) - -(dshmi blink "Branch and link" - () - "blink $trb, $rd" - (+ (f-op 17) (f-25 0) trb (f-ext 1) (f-right 63) rd (f-rsvd 0)) - (sequence () - (set rd (or (add pc 4) 1)) - (set pc trb))) - -(dshmi bne "Branch if not equal" - () - "bne$likely $rm, $rn, $tra" - (+ (f-op 25) rm (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (ne rm rn) - (set pc tra))) - -(dshmi bnei "Branch if not equal immediate" - () - "bnei$likely $rm, $imm6, $tra" - (+ (f-op 57) rm (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0)) - (if (ne rm (ext DI imm6)) - (set pc tra))) - -(dshmi brk "Breakpoint instruction" - () - "brk" - (+ (f-op 27) (f-left 63) (f-ext 5) (f-right 63) (f-dest 63) (f-rsvd 0)) - (c-call "sh64_break" pc)) - -(define-pmacro (-byterev-step) - (sequence () - (set result (or (sll result 8) (and source 255))) - (set source (srl source 8))) -) - -(dshmi byterev "Byte reverse" - () - "byterev $rm, $rd" - (+ (f-op 0) rm (f-ext 15) (f-right 63) rd (f-rsvd 0)) - (sequence ((DI source) (DI result)) - (set source rm) - (set result 0) - (-byterev-step) - (-byterev-step) - (-byterev-step) - (-byterev-step) - (-byterev-step) - (-byterev-step) - (-byterev-step) - (-byterev-step) - (set rd result))) - -(dshmi cmpeq "Compare equal" - () - "cmpeq $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 1) rn rd (f-rsvd 0)) - (set rd (if DI (eq rm rn) 1 0))) - -(dshmi cmpgt "Compare greater than" - () - "cmpgt $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 3) rn rd (f-rsvd 0)) - (set rd (if DI (gt rm rn) 1 0))) - -(dshmi cmpgtu "Compare greater than (unsigned comparison)" - () - "cmpgtu $rm,$rn, $rd" - (+ (f-op 0) rm (f-ext 7) rn rd (f-rsvd 0)) - (set rd (if DI (gtu rm rn) 1 0))) - -(dshmi cmveq "Conditional move if equal to zero" - () - "cmveq $rm, $rn, $rd" - (+ (f-op 8) rm (f-ext 1) rn rd (f-rsvd 0)) - (if (eq rm 0) - (set rd rn))) - -(dshmi cmvne "Conditional move if not equal to zero" - () - "cmvne $rm, $rn, $rd" - (+ (f-op 8) rm (f-ext 5) rn rd (f-rsvd 0)) - (if (ne rm 0) - (set rd rn))) - -(dshmi fabsd "Floating point absolute (double)" - () - "fabs.d $drgh, $drf" - (+ (f-op 6) drgh (f-ext 1) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_fabsd" drgh))) - -(dshmi fabss "Floating point absolute (single)" - () - "fabs.s $frgh, $frf" - (+ (f-op 6) frgh (f-ext 0) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fabss" frgh))) - -(dshmi faddd "Floating point add (double)" - () - "fadd.d $drg, $drh, $drf" - (+ (f-op 13) drg (f-ext 1) drh drf (f-rsvd 0)) - (set drf (c-call DF "sh64_faddd" drg drh))) - -(dshmi fadds "Floating point add (single)" - () - "fadd.s $frg, $frh, $frf" - (+ (f-op 13) frg (f-ext 0) frh frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fadds" frg frh))) - -(dshmi fcmpeqd "Floating point compare if equal (double)" - () - "fcmpeq.d $drg, $drh, $rd" - (+ (f-op 12) drg (f-ext 9) drh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpeqd" drg drh)))) - -(dshmi fcmpeqs "Floating point compare if equal (single)" - () - "fcmpeq.s $frg, $frh, $rd" - (+ (f-op 12) frg (f-ext 8) frh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpeqs" frg frh)))) - -(dshmi fcmpged "Floating compare compare if greater than or equal (double)" - () - "fcmpge.d $drg, $drh, $rd" - (+ (f-op 12) drg (f-ext 15) drh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpged" drg drh)))) - -(dshmi fcmpges "Floating point compare if greater than or equal (single)" - () - "fcmpge.s $frg, $frh, $rd" - (+ (f-op 12) frg (f-ext 14) frh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpges" frg frh)))) - -(dshmi fcmpgtd "Floating point compare if greater than (double)" - () - "fcmpgt.d $drg, $drh, $rd" - (+ (f-op 12) drg (f-ext 13) drh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpgtd" drg drh)))) - -(dshmi fcmpgts "Floating point compare if greater than (single)" - () - "fcmpgt.s $frg, $frh, $rd" - (+ (f-op 12) frg (f-ext 12) frh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpgts" frg frh)))) - -(dshmi fcmpund "Floating point unordered comparison (double)" - () - "fcmpun.d $drg, $drh, $rd" - (+ (f-op 12) drg (f-ext 11) drh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpund" drg drh)))) - -(dshmi fcmpuns "Floating point unordered comparison (single)" - () - "fcmpun.s $frg, $frh, $rd" - (+ (f-op 12) frg (f-ext 10) frh rd (f-rsvd 0)) - (set rd (zext DI (c-call BI "sh64_fcmpuns" frg frh)))) - -(dshmi fcnvds "Floating point coversion (double to single)" - () - "fcnv.ds $drgh, $frf" - (+ (f-op 14) drgh (f-ext 7) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fcnvds" drgh))) - -(dshmi fcnvsd "Floating point conversion (single to double)" - () - "fcnv.sd $frgh, $drf" - (+ (f-op 14) frgh (f-ext 6) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_fcnvsd" frgh))) - -(dshmi fdivd "Floating point divide (double)" - () - "fdiv.d $drg, $drh, $drf" - (+ (f-op 13) drg (f-ext 5) drh drf (f-rsvd 0)) - (set drf (c-call DF "sh64_fdivd" drg drh))) - -(dshmi fdivs "Floating point divide (single)" - () - "fdiv.s $frg, $frh, $frf" - (+ (f-op 13) frg (f-ext 4) frh frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fdivs" frg frh))) - -(dshmi fgetscr "Floating point get from FPSCR" - () - "fgetscr $frf" - (+ (f-op 7) (f-left 63) (f-ext 2) (f-right 63) frf (f-rsvd 0)) - (unimp "fputscr")) - ; FIXME: this should work! - ; (set frf fpscr)) - -(dshmi fiprs "Floating point inner product (single)" - () - "fipr.s $fvg, $fvh, $frf" - (+ (f-op 5) fvg (f-ext 6) fvh frf (f-rsvd 0)) - (sequence ((UQI g) (UQI h) (SF temp)) - (set g (index-of fvg)) - (set h (index-of fvh)) - (set temp (c-call SF "sh64_fmuls" (reg h-fr g) (reg h-fr h))) - (set temp (c-call SF "sh64_fadds" temp - (c-call SF "sh64_fmuls" (reg h-fr (add g 1)) (reg h-fr (add h 1))))) - (set temp (c-call SF "sh64_fadds" temp - (c-call SF "sh64_fmuls" (reg h-fr (add g 2)) (reg h-fr (add h 2))))) - (set temp (c-call SF "sh64_fadds" temp - (c-call SF "sh64_fmuls" (reg h-fr (add g 3)) (reg h-fr (add h 3))))) - (set frf temp))) - -(dshmi fldd "Floating point load (double)" - () - "fld.d $rm, $disp10x8, $drf" - (+ (f-op 39) rm disp10x8 drf (f-rsvd 0)) - (set drf (mem DF (add rm disp10x8)))) - -(dshmi fldp "Floating point load (pair of singles)" - () - "fld.p $rm, $disp10x8, $fpf" - (+ (f-op 38) rm disp10x8 fpf (f-rsvd 0)) - (sequence ((QI f)) - (set f (index-of fpf)) - (set (reg h-fr f) (mem SF (add rm disp10x8))) - (set (reg h-fr (add f 1)) (mem SF (add rm (add disp10x8 4)))))) - -(dshmi flds "Floating point load (single)" - () - "fld.s $rm, $disp10x4, $frf" - (+ (f-op 37) rm disp10x4 frf (f-rsvd 0)) - (set frf (mem SF (add rm disp10x4)))) - -(dshmi fldxd "Floating point extended load (double)" - () - "fldx.d $rm, $rn, $drf" - (+ (f-op 7) rm (f-ext 9) rn frf (f-rsvd 0)) - (set drf (mem DF (add rm rn)))) - -(dshmi fldxp "Floating point extended load (pair of singles)" - () - "fldx.p $rm, $rn, $fpf" - (+ (f-op 7) rm (f-ext 13) rn fpf (f-rsvd 0)) - (sequence ((QI f)) - (set f (index-of fpf)) - (set (reg h-fr f) (mem SF (add rm rn))) - (set (reg h-fr (add f 1)) (mem SF (add rm (add rn 4)))))) - -(dshmi fldxs "Floating point extended load (single)" - () - "fldx.s $rm, $rn, $frf" - (+ (f-op 7) rm (f-ext 8) rn frf (f-rsvd 0)) - (set frf (mem SF (add rm rn)))) - -(dshmi floatld "Floating point conversion (long to double)" - () - "float.ld $frgh, $drf" - (+ (f-op 14) frgh (f-ext 14) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_floatld" frgh))) - -(dshmi floatls "Floating point conversion (long to single)" - () - "float.ls $frgh, $frf" - (+ (f-op 14) frgh (f-ext 12) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_floatls" frgh))) - -(dshmi floatqd "Floating point conversion (quad to double)" - () - "float.qd $drgh, $drf" - (+ (f-op 14) drgh (f-ext 13) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_floatqd" drgh))) - -(dshmi floatqs "Floating point conversion (quad to single)" - () - "float.qs $drgh, $frf" - (+ (f-op 14) drgh (f-ext 15) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_floatqs" drgh))) - -(dshmi fmacs "Floating point multiply and accumulate (single)" - () - "fmac.s $frg, $frh, $frf" - (+ (f-op 13) frg (f-ext 14) frh frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fadds" frf (c-call SF "sh64_fmuls" frg frh)))) - -(dshmi fmovd "Floating point move double" - () - "fmov.d $drgh, $drf" - (+ (f-op 14) drgh (f-ext 1) drf (f-rsvd 0)) - (set drf drgh)) - -(dshmi fmovdq "Floating point move (double to quad integer)" - () - "fmov.dq $drgh, $rd" - (+ (f-op 12) drgh (f-ext 1) rd (f-rsvd 0)) - (set rd (subword DI drgh 0))) - -(dshmi fmovls "Floating point move (lower to single)" - () - "fmov.ls $rm, $frf" - (+ (f-op 7) rm (f-ext 0) (f-right 63) frf (f-rsvd 0)) - (set frf (subword SF (subword SI rm 1) 0))) - -(dshmi fmovqd "Floating point move (quad to double)" - () - "fmov.qd $rm, $drf" - (+ (f-op 7) rm (f-ext 1) (f-right 63) frf (f-rsvd 0)) - (set drf (subword DF rm 0))) - -(dshmi fmovs "Floating point move (single)" - () - "fmov.s $frgh, $frf" - (+ (f-op 14) frgh (f-ext 0) frf (f-rsvd 0)) - (set frf frgh)) - -(dshmi fmovsl "Floating point move (single to lower)" - () - "fmov.sl $frgh, $rd" - (+ (f-op 12) frgh (f-ext 0) rd (f-rsvd 0)) - (set rd (ext DI (subword SI frgh 1)))) - -(dshmi fmuld "Floating point multiply (double)" - () - "fmul.d $drg, $drh, $drf" - (+ (f-op 13) drg (f-ext 7) drh drf (f-rsvd 0)) - (set drf (c-call DF "sh64_fmuld" drg drh))) - -(dshmi fmuls "Floating point multiply (single)" - () - "fmul.s $frg, $frh, $frf" - (+ (f-op 13) frg (f-ext 6) frh frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fmuls" frg frh))) - -(dshmi fnegd "Floating point negate (double)" - () - "fneg.d $drgh, $drf" - (+ (f-op 6) drgh (f-ext 3) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_fnegd" drgh))) - -(dshmi fnegs "Floating point negate (single)" - () - "fneg.s $frgh, $frf" - (+ (f-op 6) frgh (f-ext 2) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fnegs" frgh))) - -(dshmi fputscr "Floating point put to FPSCR" - () - "fputscr $frgh" - (+ (f-op 12) frgh (f-ext 2) (f-dest 63) (f-rsvd 0)) - (unimp "fputscr")) - ; FIXME: this should work! - ; (set fpscr (subword SI frgh 0))) - -(dshmi fsqrtd "Floating point square root (double)" - () - "fsqrt.d $drgh, $drf" - (+ (f-op 14) drgh (f-ext 5) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_fsqrtd" drgh))) - -(dshmi fsqrts "Floating point squart root (single)" - () - "fsqrt.s $frgh, $frf" - (+ (f-op 14) frgh (f-ext 4) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fsqrts" frgh))) - -(dshmi fstd "Floating point store (double)" - () - "fst.d $rm, $disp10x8, $drf" - (+ (f-op 47) rm disp10x8 drf (f-rsvd 0)) - (set (mem DF (add rm disp10x8)) drf)) - -(dshmi fstp "Floating point store (pair of singles)" - () - "fst.p $rm, $disp10x8, $fpf" - (+ (f-op 46) rm disp10x8 fpf (f-rsvd 0)) - (sequence ((QI f)) - (set f (index-of fpf)) - (set (mem SF (add rm disp10x8)) (reg h-fr f)) - (set (mem SF (add rm (add disp10x8 4))) (reg h-fr (add f 1))))) - -(dshmi fsts "Floating point store (single)" - () - "fst.s $rm, $disp10x4, $frf" - (+ (f-op 45) rm disp10x4 frf (f-rsvd 0)) - (set (mem SF (add rm disp10x4)) frf)) - -(dshmi fstxd "Floating point extended store (double)" - () - "fstx.d $rm, $rn, $drf" - (+ (f-op 15) rm (f-ext 9) rn drf (f-rsvd 0)) - (set (mem DF (add rm rn)) drf)) - -(dshmi fstxp "Floating point extended store (pair of singles)" - () - "fstx.p $rm, $rn, $fpf" - (+ (f-op 15) rm (f-ext 13) rn fpf (f-rsvd 0)) - (sequence ((QI f)) - (set f (index-of fpf)) - (set (mem SF (add rm rn)) (reg h-fr f)) - (set (mem SF (add rm (add rn 4))) (reg h-fr (add f 1))))) - -(dshmi fstxs "Floating point extended store (single)" - () - "fstx.s $rm, $rn, $frf" - (+ (f-op 15) rm (f-ext 8) rn frf (f-rsvd 0)) - (set (mem SF (add rm rn)) frf)) - -(dshmi fsubd "Floating point subtract (double)" - () - "fsub.d $drg, $drh, $drf" - (+ (f-op 13) frg (f-ext 3) frh frf (f-rsvd 0)) - (set drf (c-call DF "sh64_fsubd" drg drh))) - -(dshmi fsubs "Floating point subtract (single)" - () - "fsub.s $frg, $frh, $frf" - (+ (f-op 13) frg (f-ext 2) frh frf (f-rsvd 0)) - (set frf (c-call SF "sh64_fsubs" frg frh))) - -(dshmi ftrcdl "Floating point conversion (double to long)" - () - "ftrc.dl $drgh, $frf" - (+ (f-op 14) drgh (f-ext 11) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_ftrcdl" drgh))) - -(dshmi ftrcsl "Floating point conversion (single to long)" - () - "ftrc.sl $frgh, $frf" - (+ (f-op 14) frgh (f-ext 8) frf (f-rsvd 0)) - (set frf (c-call SF "sh64_ftrcsl" frgh))) - -(dshmi ftrcdq "Floating point conversion (double to quad)" - () - "ftrc.dq $drgh, $drf" - (+ (f-op 14) drgh (f-ext 9) frf (f-rsvd 0)) - (set drf (c-call DF "sh64_ftrcdq" drgh))) - -(dshmi ftrcsq "Floating point conversion (single to quad)" - () - "ftrc.sq $frgh, $drf" - (+ (f-op 14) frgh (f-ext 10) drf (f-rsvd 0)) - (set drf (c-call DF "sh64_ftrcsq" frgh))) - -(dshmi ftrvs "Floating point matrix multiply" - () - "ftrv.s $mtrxg, $fvh, $fvf" - (+ (f-op 5) mtrxg (f-ext 14) fvh fvf (f-rsvd 0)) - (c-call "sh64_ftrvs" (index-of mtrxg) (index-of fvh) (index-of fvf))) - -(dshmi getcfg "Get configuration register" - () - "getcfg $rm, $disp6, $rd" - (+ (f-op 48) rm (f-ext 15) disp6 rd (f-rsvd 0)) - (unimp "getcfg")) - -(dshmi getcon "Get control register" - () - "getcon $crk, $rd" - (+ (f-op 9) crk (f-ext 15) (f-right 63) rd (f-rsvd 0)) - (set rd crk)) - -(dshmi gettr "Get target register" - () - "gettr $trb, $rd" - (+ (f-op 17) (f-25 0) trb (f-ext 5) (f-right 63) rd (f-rsvd 0)) - (set rd trb)) - -(dshmi icbi "Invalidate instruction cache block" - () - "icbi $rm, $disp6x32" - (+ (f-op 56) rm (f-ext 5) disp6x32 (f-dest 63) (f-rsvd 0)) - (unimp "icbi")) - -(dshmi ldb "Load byte" - () - "ld.b $rm, $disp10, $rd" - (+ (f-op 32) rm disp10 rd (f-rsvd 0)) - (set rd (ext DI (mem QI (add rm (ext DI disp10)))))) - -(dshmi ldl "Load long word" - () - "ld.l $rm, $disp10x4, $rd" - (+ (f-op 34) rm disp10x4 rd (f-rsvd 0)) - (set rd (ext DI (mem SI (add rm (ext DI disp10x4)))))) - -(dshmi ldq "Load quad word" - () - "ld.q $rm, $disp10x8, $rd" - (+ (f-op 35) rm disp10x8 rd (f-rsvd 0)) - (set rd (mem DI (add rm (ext DI disp10x8))))) - -(dshmi ldub "Load unsigned byte" - () - "ld.ub $rm, $disp10, $rd" - (+ (f-op 36) rm disp10 rd (f-rsvd 0)) - (set rd (zext DI (mem QI (add rm (ext DI disp10)))))) - -(dshmi lduw "Load unsigned word" - () - "ld.uw $rm, $disp10x2, $rd" - (+ (f-op 44) rm disp10 rd (f-rsvd 0)) - (set rd (zext DI (mem HI (add rm (ext DI disp10x2)))))) - -(dshmi ldw "Load word" - () - "ld.w $rm, $disp10x2, $rd" - (+ (f-op 33) rm disp10 rd (f-rsvd 0)) - (set rd (ext DI (mem HI (add rm (ext DI disp10x2)))))) - -(dshmi ldhil "Load high part (long word)" - () - "ldhi.l $rm, $disp6, $rd" - (+ (f-op 48) rm (f-ext 6) disp6 rd (f-rsvd 0)) - ; FIXME. - (unimp "ldhil")) - -(dshmi ldhiq "Load high part (quad word)" - () - "ldhi.q $rm, $disp6, $rd" - (+ (f-op 48) rm (f-ext 7) disp6 rd (f-rsvd 0)) - ; FIXME. - (unimp "ldhiq")) - -(dshmi ldlol "Load low part (long word)" - () - "ldlo.l $rm, $disp6, $rd" - (+ (f-op 48) rm (f-ext 2) disp6 rd (f-rsvd 0)) - ; FIXME. - (unimp "ldlol")) - -(dshmi ldloq "Load low part (quad word)" - () - "ldlo.q $rm, $disp6, $rd" - (+ (f-op 48) rm (f-ext 3) disp6 rd (f-rsvd 0)) - ; FIXME; - (unimp "ldloq")) - -(dshmi ldxb "Load byte (extended displacement)" - () - "ldx.b $rm, $rn, $rd" - (+ (f-op 16) rm (f-ext 0) rn rd (f-rsvd 0)) - (set rd (ext DI (mem QI (add rm rn))))) - -(dshmi ldxl "Load long word (extended displacement)" - () - "ldx.l $rm, $rn, $rd" - (+ (f-op 16) rm (f-ext 2) rn rd (f-rsvd 0)) - (set rd (ext DI (mem SI (add rm rn))))) - -(dshmi ldxq "Load quad word (extended displacement)" - () - "ldx.q $rm, $rn, $rd" - (+ (f-op 16) rm (f-ext 3) rn rd (f-rsvd 0)) - (set rd (mem DI (add rm rn)))) - -(dshmi ldxub "Load unsigned byte (extended displacement)" - () - "ldx.ub $rm, $rn, $rd" - (+ (f-op 16) rm (f-ext 4) rn rd (f-rsvd 0)) - (set rd (zext DI (mem UQI (add rm rn))))) - -(dshmi ldxuw "Load unsigned word (extended displacement)" - () - "ldx.uw $rm, $rn, $rd" - (+ (f-op 16) rm (f-ext 5) rn rd (f-rsvd 0)) - (set rd (zext DI (mem UHI (add rm rn))))) - -(dshmi ldxw "Load word (extended displacement)" - () - "ldx.w $rm, $rn, $rd" - (+ (f-op 16) rm (f-ext 1) rn rd (f-rsvd 0)) - (set rd (ext DI (mem HI (add rm rn))))) - - -; Macros to facilitate multimedia instructions. - -(define-pmacro (slice-byte expr) - (sequence ((QI result7) (QI result6) (QI result5) (QI result4) - (QI result3) (QI result2) (QI result1) (QI result0)) - (set result0 (expr (subword QI rm 7) (subword QI rn 7))) - (set result1 (expr (subword QI rm 6) (subword QI rn 6))) - (set result2 (expr (subword QI rm 5) (subword QI rn 5))) - (set result3 (expr (subword QI rm 4) (subword QI rn 4))) - (set result4 (expr (subword QI rm 3) (subword QI rn 3))) - (set result5 (expr (subword QI rm 2) (subword QI rn 2))) - (set result6 (expr (subword QI rm 1) (subword QI rn 1))) - (set result7 (expr (subword QI rm 0) (subword QI rn 0))) - (set rd (-join-qi result7 result6 result5 result4 result3 result2 - result1 result0)))) - -(define-pmacro (slice-word expr) - (sequence ((HI result3) (HI result2) (HI result1) (HI result0)) - (set result0 (expr (subword HI rm 3) (subword HI rn 3))) - (set result1 (expr (subword HI rm 2) (subword HI rn 2))) - (set result2 (expr (subword HI rm 1) (subword HI rn 1))) - (set result3 (expr (subword HI rm 0) (subword HI rn 0))) - (set rd (-join-hi result3 result2 result1 result0)))) - -(define-pmacro (slice-word-unop expr) - (sequence ((HI result3) (HI result2) (HI result1) (HI result0)) - (set result0 (expr (subword HI rm 3))) - (set result1 (expr (subword HI rm 2))) - (set result2 (expr (subword HI rm 1))) - (set result3 (expr (subword HI rm 0))) - (set rd (-join-hi result3 result2 result1 result0)))) - -(define-pmacro (slice-long expr) - (sequence ((SI result1) (SI result0)) - (set result0 (expr (subword SI rm 1) (subword SI rn 1))) - (set result1 (expr (subword SI rm 0) (subword SI rn 0))) - (set rd (-join-si result1 result0)))) - -(define-pmacro (slice-long-unop expr) - (sequence ((SI result1) (SI result0)) - (set result0 (expr (subword SI rm 1))) - (set result1 (expr (subword SI rm 0))) - (set rd (-join-si result1 result0)))) - -; Multimedia instructions. - -(dshmi mabsl "Multimedia absolute value (long word)" - () - "mabs.l $rm, $rd" - (+ (f-op 10) rm (f-ext 10) (f-right 63) rd (f-rsvd 0)) - (slice-long-unop abs)) - -(dshmi mabsw "Multimedia absolute value (word)" - () - "mabs.w $rm, $rd" - (+ (f-op 10) rm (f-ext 9) (f-right 63) rd (f-rsvd 0)) - (slice-word-unop abs)) - -(dshmi maddl "Multimedia add (long word)" - () - "madd.l $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 2) rn rd (f-rsvd 0)) - (slice-long add)) - -(dshmi maddw "Multimedia add (word)" - () - "madd.w $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 1) rn rd (f-rsvd 0)) - (slice-word add)) - -(define-pmacro (-maddsl arg1 arg2) (saturate SI 32 (add arg1 arg2))) -(dshmi maddsl "Multimedia add (saturating, long word)" - () - "madds.l $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 6) rn rd (f-rsvd 0)) - (slice-long -maddsl)) - -(define-pmacro (-maddsub arg1 arg2) (usaturate QI 8 (add arg1 arg2))) -(dshmi maddsub "Multimedia add (saturating, unsigned byte)" - () - "madds.ub $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 4) rn rd (f-rsvd 0)) - (slice-byte -maddsub)) - -(define-pmacro (-maddsw arg1 arg2) (saturate HI 16 (add arg1 arg2))) -(dshmi maddsw "Multimedia add (saturating, word)" - () - "madds.w $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 5) rn rd (f-rsvd 0)) - (slice-word -maddsw)) - -(define-pmacro (-mcmpeq mode arg1 arg2) - (if mode (eq arg1 arg2) (inv mode 0) (const mode 0))) - -(define-pmacro (-mcmpeqb arg1 arg2) (-mcmpeq QI arg1 arg2)) -(dshmi mcmpeqb "Multimedia compare equal (byte)" - () - "mcmpeq.b $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 0) rn rd (f-rsvd 0)) - (slice-byte -mcmpeqb)) - -(define-pmacro (-mcmpeql arg1 arg2) (-mcmpeq SI arg1 arg2)) -(dshmi mcmpeql "Multimedia compare equal (long word)" - () - "mcmpeq.l $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 2) rn rd (f-rsvd 0)) - (slice-long -mcmpeql)) - -(define-pmacro (-mcmpeqw arg1 arg2) (-mcmpeq HI arg1 arg2)) -(dshmi mcmpeqw "Multimedia compare equal (word)" - () - "mcmpeq.w $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 1) rn rd (f-rsvd 0)) - (slice-word -mcmpeqw)) - -(define-pmacro (-mcmpgt mode arg1 arg2) - (if mode (gt arg1 arg2) (inv mode 0) (const mode 0))) -(define-pmacro (-mcmpgtu mode arg1 arg2) - (if mode (gtu arg1 arg2) (inv mode 0) (const mode 0))) - -(define-pmacro (-mcmpgtl arg1 arg2) (-mcmpgt SI arg1 arg2)) -(dshmi mcmpgtl "Multimedia compare greater than (long word)" - () - "mcmpgt.l $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 6) rn rd (f-rsvd 0)) - (slice-long -mcmpgtl)) - -(define-pmacro (-mcmpgtub arg1 arg2) (-mcmpgtu QI arg1 arg2)) -(dshmi mcmpgtub "Multimediate compare unsigned greater than (byte)" - () - "mcmpgt.ub $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 4) rn rd (f-rsvd 0)) - (slice-byte -mcmpgtub)) - -(define-pmacro (-mcmpgtw arg1 arg2) (-mcmpgt HI arg1 arg2)) -(dshmi mcmpgtw "Multimedia compare greater than (word)" - () - "mcmpgt.w $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 5) rn rd (f-rsvd 0)) - (slice-word -mcmpgtw)) - -(dshmi mcmv "Multimedia conditional move" - () - "mcmv $rm, $rn, $rd" - (+ (f-op 18) rm (f-ext 3) rn rd (f-rsvd 0)) - (set rd (or (and rm rn) (and rd (inv rn))))) - -(dshmi mcnvslw "Multimedia convert/saturate (long to word)" - () - "mcnvs.lw $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 13) rn rd (f-rsvd 0)) - (sequence ((HI result3) (HI result2) (HI result1) (HI result0)) - (set result0 (saturate HI 16 (subword SI rm 0))) - (set result1 (saturate HI 16 (subword SI rm 1))) - (set result2 (saturate HI 16 (subword SI rn 0))) - (set result3 (saturate HI 16 (subword SI rn 1))) - (set rd (-join-hi result3 result2 result1 result0)))) - -(dshmi mcnvswb "Multimedia convert/saturate (word to byte)" - () - "mcnvs.wb $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 8) rn rd (f-rsvd 0)) - (sequence ((QI result7) (QI result6) (QI result5) (QI result4) - (QI result3) (QI result2) (QI result1) (QI result0)) - (set result0 (saturate QI 8 (subword HI rm 0))) - (set result1 (saturate QI 8 (subword HI rm 1))) - (set result2 (saturate QI 8 (subword HI rm 2))) - (set result3 (saturate QI 8 (subword HI rm 3))) - (set result4 (saturate QI 8 (subword HI rn 0))) - (set result5 (saturate QI 8 (subword HI rn 1))) - (set result6 (saturate QI 8 (subword HI rn 2))) - (set result7 (saturate QI 8 (subword HI rn 3))) - (set rd (-join-qi result7 result6 result5 result4 - result3 result2 result1 result0)))) - -(dshmi mcnvswub "Multimedia convert/saturate (word to unsigned byte)" - () - "mcnvs.wub $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 12) rn rd (f-rsvd 0)) - (sequence ((QI result7) (QI result6) (QI result5) (QI result4) - (QI result3) (QI result2) (QI result1) (QI result0)) - (set result0 (usaturate QI 8 (subword HI rm 0))) - (set result1 (usaturate QI 8 (subword HI rm 1))) - (set result2 (usaturate QI 8 (subword HI rm 2))) - (set result3 (usaturate QI 8 (subword HI rm 3))) - (set result4 (usaturate QI 8 (subword HI rn 0))) - (set result5 (usaturate QI 8 (subword HI rn 1))) - (set result6 (usaturate QI 8 (subword HI rn 2))) - (set result7 (usaturate QI 8 (subword HI rn 3))) - (set rd (-join-qi result7 result6 result5 result4 result3 - result2 result1 result0)))) - -; mexter -- generate an mexterN instruction, where: -; op = primary opcode -; extop = extended opcode - -(define-pmacro (make-mextr n op extop) - (dshmi (.sym mextr n) - (.str "Multimedia extract 64-bit slice (from byte " n ")") - () - (.str "mextr" n " $rm, $rn, $rd") - (+ (f-op op) rm (f-ext extop) rn rd (f-rsvd 0)) - (sequence ((QI count) (DI mask) (DI rhs)) - (set count (mul QI 8 (sub QI 8 n))) - (set mask (sll DI (inv 0) count)) - (set rhs (srl (and rm mask) count)) - (set count (mul QI 8 n)) - (set mask (srl DI (inv 0) count)) - (set rd (or DI rhs (sll DI (and rn mask) count)))))) - -(make-mextr 1 10 7) -(make-mextr 2 10 11) -(make-mextr 3 10 15) -(make-mextr 4 11 3) -(make-mextr 5 11 7) -(make-mextr 6 11 11) -(make-mextr 7 11 15) - -(dshmi mmacfxwl "Multimedia fractional multiply (word to long)" - () - "mmacfx.wl $rm, $rn, $rd" - (+ (f-op 18) rm (f-ext 1) rn rd (f-rsvd 0)) - (sequence ((SI temp) (SI result1) (SI result0)) - (set result0 (subword SI rd 0)) - (set result1 (subword SI rd 1)) - (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0)))) - (set temp (saturate SI 32 (sll temp 1))) - (set result0 (saturate SI 32 (add result0 temp))) - (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))) - (set temp (saturate SI 32 (sll temp 1))) - (set result1 (saturate SI 32 (add result1 temp))) - (set rd (-join-si result1 result0)))) - -(dshmi mmacnfx.wl "Multimedia fractional multiple (word to long)" - () - "mmacnfx.wl $rm, $rn, $rd" - (+ (f-op 18) rn (f-ext 5) rn rd (f-rsvd 0)) - (sequence ((SI temp) (SI result1) (SI result0)) - (set result0 (subword SI rd 0)) - (set result1 (subword SI rd 1)) - (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0)))) - (set temp (saturate SI 32 (sll temp 1))) - (set result0 (saturate SI 32 (sub result0 temp))) - (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))) - (set temp (saturate SI 32 (sll temp 1))) - (set result1 (saturate SI 32 (sub result1 temp))) - (set rd (-join-si result1 result0)))) - -(dshmi mmull "Multimedia multiply (long word)" - () - "mmul.l $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 2) rn rd (f-rsvd 0)) - (slice-long mul)) - -(dshmi mmulw "Multimedia multiply (word)" - () - "mmul.w $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 1) rn rd (f-rsvd 0)) - (slice-word mul)) - -(dshmi mmulfxl "Multimedia fractional multiply (long word)" - () - "mmulfx.l $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 6) rn rd (f-rsvd 0)) - (sequence ((DI temp) (SI result0) (SI result1)) - (set temp (mul (zext DI (subword SI rm 0)) (zext DI (subword SI rn 0)))) - (set result0 (saturate SI 32 (sra temp 31))) - (set temp (mul (zext DI (subword SI rm 1)) (zext DI (subword SI rn 1)))) - (set result1 (saturate SI 32 (sra temp 31))) - (set rd (-join-si result1 result0)))) - -(dshmi mmulfxw "Multimedia fractional multiply (word)" - () - "mmulfx.w $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 5) rn rd (f-rsvd 0)) - (sequence ((SI temp) (HI result0) (HI result1) (HI result2) (HI result3)) - (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0)))) - (set result0 (saturate HI 16 (sra temp 15))) - (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))) - (set result1 (saturate HI 16 (sra temp 15))) - (set temp (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2)))) - (set result2 (saturate HI 16 (sra temp 15))) - (set temp (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3)))) - (set result3 (saturate HI 16 (sra temp 15))) - (set rd (-join-hi result3 result2 result1 result0)))) - -(dshmi mmulfxrpw "Multimedia fractional multiply round positive (word op)" - () - "mmulfxrp.w $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 9) rn rd (f-rsvd 0)) - (sequence ((SI temp) (HI result0) (HI result1) (HI result2) (HI result3) (HI c)) - (set c (sll 1 14)) - (set temp (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0)))) - (set result0 (saturate HI 16 (sra (add temp c) 15))) - (set temp (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))) - (set result1 (saturate HI 16 (sra (add temp c) 15))) - (set temp (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2)))) - (set result2 (saturate HI 16 (sra (add temp c) 15))) - (set temp (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3)))) - (set result3 (saturate HI 16 (sra (add temp c) 15))) - (set rd (-join-hi result3 result2 result1 result0)))) - -(dshmi mmulhiwl "Multimedia multiply higher halves (word to long)" - () - "mmulhi.wl $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 14) rn rd (f-rsvd 0)) - (sequence ((SI result1) (SI result0)) - (set result0 (mul (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2)))) - (set result1 (mul (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3)))) - (set rd (-join-si result1 result0)))) - -(dshmi mmullowl "Multimedia multiply lower halves (word to long)" - () - "mmullo.wl $rm, $rn, $rd" - (+ (f-op 19) rm (f-ext 10) rn rd (f-rsvd 0)) - (sequence ((SI result1) (SI result0)) - (set result0 (mul (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0)))) - (set result1 (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))) - (set rd (-join-si result1 result0)))) - -(dshmi mmulsumwq "Multimedia multiply and accumulate (word to quad)" - () - "mmulsum.wq $rm, $rn, $rd" - (+ (f-op 18) rm (f-ext 9) rn rd (f-rsvd 0)) - (sequence ((DI acc)) - (set acc (mul SI (zext SI (subword HI rm 0)) (zext SI (subword HI rn 0)))) - (set acc (add acc (mul SI (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1))))) - (set acc (add acc (mul SI (zext SI (subword HI rm 2)) (zext SI (subword HI rn 2))))) - (set acc (add acc (mul SI (zext SI (subword HI rm 3)) (zext SI (subword HI rn 3))))) - (set rd (add rd acc)))) - -(dshmi movi "Move immediate" - () - "movi $imm16, $rd" - (+ (f-op 51) imm16 rd (f-rsvd 0)) - (set rd (ext DI imm16))) - -(dshmi mpermw "Multimedia permutate word" - () - "mperm.w $rm, $rn, $rd" - (+ (f-op 10) rm (f-ext 13) rn rd (f-rsvd 0)) - (sequence ((QI control) (HI result3) (HI result2) (HI result1) (HI result0)) - (set control (and QI rn #x3f)) - (set result0 (subword HI rm (sub 3 (and control 3)))) - (set result1 (subword HI rm (sub 3 (and (srl control 2) 3)))) - (set result2 (subword HI rm (sub 3 (and (srl control 4) 3)))) - (set result3 (subword HI rm (sub 3 (and (srl control 6) 3)))) - (set rd (-join-hi result3 result2 result1 result0)))) - -(dshmi msadubq "Multimedia absolute difference (byte)" - () - "msad.ubq $rm, $rn, $rd" - (+ (f-op 18) rm (f-ext 0) rn rd (f-rsvd 0)) - (sequence ((DI acc)) - (set acc (abs DI (sub (subword QI rm 0) (subword QI rn 1)))) - (set acc (add DI acc (abs (sub (subword QI rm 1) (subword QI rn 1))))) - (set acc (add DI acc (abs (sub (subword QI rm 2) (subword QI rn 2))))) - (set acc (add DI acc (abs (sub (subword QI rm 3) (subword QI rn 3))))) - (set acc (add DI acc (abs (sub (subword QI rm 4) (subword QI rn 4))))) - (set acc (add DI acc (abs (sub (subword QI rm 5) (subword QI rn 5))))) - (set acc (add DI acc (abs (sub (subword QI rm 6) (subword QI rn 6))))) - (set acc (add DI acc (abs (sub (subword QI rm 7) (subword QI rn 7))))) - (set rd (add rd acc)))) - -(define-pmacro (-mshaldsl arg) (saturate SI 32 (sll arg (and rn 31)))) -(dshmi mshaldsl "Multimedia saturating arithmetic left shift (long word)" - () - "mshalds.l $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 6) rn rd (f-rsvd 0)) - (slice-long-unop -mshaldsl)) - -(define-pmacro (-mshaldsw arg) (saturate HI 16 (sll arg (and rn 15)))) -(dshmi mshaldsw "Multimedia saturating arithmetic left shift (word)" - () - "mshalds.w $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 5) rn rd (f-rsvd 0)) - (slice-word-unop -mshaldsw)) - -(define-pmacro (-mshardl arg) (sra arg (and rn 31))) -(dshmi mshardl "Multimedia arithmetic right shift (long)" - () - "mshard.l $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 10) rn rd (f-rsvd 0)) - (slice-long-unop -mshardl)) - -(define-pmacro (-mshardw arg) (sra arg (and rn 15))) -(dshmi mshardw "Multimedia arithmetic right shift (word)" - () - "mshard.w $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 9) rn rd (f-rsvd 0)) - (slice-word-unop -mshardw)) - -(dshmi mshardsq "Multimedia saturating arithmetic right shift (quad word)" - () - "mshards.q $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 11) rn rd (f-rsvd 0)) - (set rd (saturate DI 16 (sra rm (and rn 63))))) - -(dshmi mshfhib "Multimedia shuffle higher-half (byte)" - () - "mshfhi.b $rm, $rn, $rd" - (+ (f-op 11) rm (f-ext 4) rn rd (f-rsvd 0)) - (sequence ((QI result7) (QI result6) (QI result5) (QI result4) - (QI result3) (QI result2) (QI result1) (QI result0)) - (set result0 (subword QI rm 4)) - (set result1 (subword QI rn 4)) - (set result2 (subword QI rm 5)) - (set result3 (subword QI rn 5)) - (set result4 (subword QI rm 6)) - (set result5 (subword QI rn 6)) - (set result6 (subword QI rm 7)) - (set result7 (subword QI rn 7)) - (set rd (-join-qi result7 result6 result5 result4 result3 - result2 result1 result0)))) - -(dshmi mshfhil "Multimedia shuffle higher-half (long)" - () - "mshfhi.l $rm, $rn, $rd" - (+ (f-op 11) rm (f-ext 6) rn rd (f-rsvd 0)) - (sequence ((SI result1) (SI result0)) - (set result0 (subword SI rm 1)) - (set result1 (subword SI rn 1)) - (set rd (-join-si result1 result0)))) - -(dshmi mshfhiw "Multimedia shuffle higher-half (word)" - () - "mshfhi.w $rm, $rn, $rd" - (+ (f-op 11) rm (f-ext 5) rn rd (f-rsvd 0)) - (sequence ((HI result3) (HI result2) (HI result1) (HI result0)) - (set result0 (subword HI rm 2)) - (set result1 (subword HI rn 2)) - (set result2 (subword HI rm 3)) - (set result3 (subword HI rn 3)) - (set rd (-join-hi result3 result2 result1 result0)))) - -(dshmi mshflob "Multimedia shuffle lower-half (byte)" - () - "mshflo.b $rm, $rn, $rd" - (+ (f-op 11) rm (f-ext 0) rn rd (f-rsvd 0)) - (sequence ((QI result7) (QI result6) (QI result5) (QI result4) - (QI result3) (QI result2) (QI result1) (QI result0)) - (set result0 (subword QI rm 0)) - (set result1 (subword QI rn 0)) - (set result2 (subword QI rm 1)) - (set result3 (subword QI rn 1)) - (set result4 (subword QI rm 2)) - (set result5 (subword QI rn 2)) - (set result6 (subword QI rm 3)) - (set result7 (subword QI rn 3)) - (set rd (-join-qi result7 result6 result5 result4 result3 - result2 result1 result0)))) - -(dshmi mshflol "Multimedia shuffle lower-half (long)" - () - "mshflo.l $rm, $rn, $rd" - (+ (f-op 11) rm (f-ext 2) rn rd (f-rsvd 0)) - (sequence ((SI result1) (SI result0)) - (set result0 (subword SI rm 0)) - (set result1 (subword SI rn 0)) - (set rd (-join-si result1 result0)))) - -(dshmi mshflow "Multimedia shuffle lower-half (word)" - () - "mshflo.w $rm, $rn, $rd" - (+ (f-op 11) rm (f-ext 1) rn rd (f-rsvd 0)) - (sequence ((HI result3) (HI result2) (HI result1) (HI result0)) - (set result0 (subword HI rm 0)) - (set result1 (subword HI rn 0)) - (set result2 (subword HI rm 1)) - (set result3 (subword HI rn 1)) - (set rd (-join-hi result3 result2 result1 result0)))) - -(define-pmacro (-mshlldl arg) (sll arg (and rn 31))) -(dshmi mshlldl "Multimedia logical left shift (long word)" - () - "mshlld.l $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 2) rn rd (f-rsvd 0)) - (slice-long-unop -mshlldl)) - -(define-pmacro (-mshlldw arg) (sll arg (and rn 15))) -(dshmi mshlldw "Multimedia logical left shift (word)" - () - "mshlld.w $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 1) rn rd (f-rsvd 0)) - (slice-word-unop -mshlldw)) - -(define-pmacro (-mshlrdl arg) (srl arg (and rn 31))) -(dshmi mshlrdl "Multimedia logical right shift (long word)" - () - "mshlrd.l $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 14) rn rd (f-rsvd 0)) - (slice-long-unop -mshlrdl)) - -(define-pmacro (-mshlrdw arg) (srl arg (and rn 15))) -(dshmi mshlrdw "Multimedia logical right shift (word)" - () - "mshlrd.w $rm, $rn, $rd" - (+ (f-op 3) rm (f-ext 13) rn rd (f-rsvd 0)) - (slice-word-unop -mshlrdw)) - -(dshmi msubl "Multimedia subtract (long word)" - () - "msub.l $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 10) rn rd (f-rsvd 0)) - (slice-long sub)) - -(dshmi msubw "Multimedia add (word)" - () - "msub.w $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 9) rn rd (f-rsvd 0)) - (slice-word sub)) - -(define-pmacro (-msubsl arg1 arg2) (saturate SI 32 (sub arg1 arg2))) -(dshmi msubsl "Multimedia subtract (saturating long)" - () - "msubs.l $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 14) rn rd (f-rsvd 0)) - (slice-long -msubsl)) - -(define-pmacro (-msubsub arg1 arg2) (usaturate QI 8 (sub arg1 arg2))) -(dshmi msubsub "Multimedia subtract (saturating byte)" - () - "msubs.ub $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 12) rn rd (f-rsvd 0)) - (slice-byte -msubsub)) - -(define-pmacro (-msubsw arg1 arg2) (saturate HI 16 (sub arg1 arg2))) -(dshmi msubsw "Multimedia subtract (saturating word)" - () - "msubs.w $rm, $rn, $rd" - (+ (f-op 2) rm (f-ext 13) rn rd (f-rsvd 0)) - (slice-byte -msubsw)) - -(dshmi mulsl "Multiply signed long" - () - "muls.l $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 14) rn rd (f-rsvd 0)) - (set rd (mul (ext DI (subword SI rm 1)) (ext DI (subword SI rn 1))))) - -(dshmi mulul "Multiply unsigned long" - () - "mulu.l $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 14) rn rd (f-rsvd 0)) - (set rd (mul (zext DI (subword SI rm 1)) (zext DI (subword SI rn 1))))) - -(dshmi nop "No operation" - () - "nop" - (+ (f-op 27) (f-left 63) (f-ext 0) (f-right 63) (f-dest 63) (f-rsvd 0)) - (nop)) - -(dshmi nsb "Number of consecutive sign bits" - () - "nsb $rm, $rd" - (+ (f-op 0) rm (f-ext 13) (f-right 63) rd (f-rsvd 0)) - ; Semantics requires a loop construct, so punt to C. - (set rd (c-call DI "sh64_nsb" rm))) - -(dshmi ocbi "Invalidate operand cache block" - () - "ocbi $rm, $disp6x32" - (+ (f-op 56) rm (f-ext 9) disp6x32 (f-dest 63) (f-rsvd 0)) - (unimp "ocbi")) - -(dshmi ocbp "Purge operand cache block" - () - "ocbp $rm, $disp6x32" - (+ (f-op 56) rm (f-ext 8) disp6x32 (f-dest 63) (f-rsvd 0)) - (unimp "ocbp")) - -(dshmi ocbwb "Write-back operand cache block" - () - "ocbwb $rm, $disp6x32" - (+ (f-op 56) rm (f-ext 12) disp6x32 (f-dest 63) (f-rsvd 0)) - (unimp "ocbwb")) - -(dshmi or "OR" - () - "or $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 9) rn rd (f-rsvd 0)) - (set rd (or rm rn))) - -(dshmi ori "OR immediate" - () - "ori $rm, $imm10, $rd" - (+ (f-op 55) rm imm10 rd (f-rsvd 0)) - (set rd (or rm (ext DI imm10)))) - -(dshmi prefi "Prefetch instruction" - () - "prefi $rm, $disp6x32" - (+ (f-op 56) rm (f-ext 1) disp6x32 (f-right 63) (f-rsvd 0)) - (unimp "prefi")) - -(dshmi pta "Prepare target register for SHmedia target" - () - "pta$likely $disp16, $tra" - (+ (f-op 58) disp16 likely (f-8-2 0) tra (f-rsvd 0)) - (set tra (add disp16 1))) - -(dshmi ptabs "Prepare target register with absolute value from register" - () - "ptabs$likely $rn, $tra" - (+ (f-op 26) (f-left 63) (f-ext 1) rn likely (f-8-2 0) tra (f-rsvd 0)) - (set tra rn)) - -(dshmi ptb "Prepare target register for SHcompact target" - () - "ptb$likely $disp16, $tra" - (+ (f-op 59) disp16 likely (f-8-2 0) tra (f-rsvd 0)) - (set tra disp16)) - -(dshmi ptrel "Prepare target register with relative value from register" - () - "ptrel$likely $rn, $tra" - (+ (f-op 26) (f-left 63) (f-ext 5) rn likely (f-8-2 0) tra (f-rsvd 0)) - (set tra (add pc rn))) - -(dshmi putcfg "Put configuration register" - () - "putcfg $rm, $disp6, $rd" - (+ (f-op 56) rm (f-ext 15) disp6 rd (f-rsvd 0)) - (unimp "putcfg")) - -(dshmi putcon "Put control register" - () - "putcon $rm, $crj" - (+ (f-op 27) rm (f-ext 15) (f-right 63) crj (f-rsvd 0)) - (set crj rm)) - -(dshmi rte "Return from exception" - () - "rte" - (+ (f-op 27) (f-left 63) (f-ext 3) (f-right 63) (f-dest 63) (f-rsvd 0)) - (unimp "rte")) - -(dshmi shard "Arithmetic right shift" - () - "shard $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 7) rn rd (f-rsvd 0)) - (set rd (sra rm (and rn 63)))) - -(dshmi shardl "Arithmetic right shift (long word)" - () - "shard.l $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 6) rn rd (f-rsvd 0)) - (set rd (ext DI (sra (subword SI rm 1) (and rn 63))))) - -(dshmi shari "Arithmetic right shift (immediate count)" - () - "shari $rm, $uimm6, $rd" - (+ (f-op 49) rm (f-ext 7) uimm6 rd (f-rsvd 0)) - (set rd (sra rm uimm6))) - -(dshmi sharil "Arithmetic right shift (long word, immediate count)" - () - "shari.l $rm, $uimm6, $rd" - (+ (f-op 49) rm (f-ext 6) uimm6 rd (f-rsvd 0)) - (set rd (ext DI (sra (subword SI rm 1) (and uimm6 63))))) - -(dshmi shlld "Logical left shift" - () - "shlld $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 1) rn rd (f-rsvd 0)) - (set rd (sll rm (and rn 63)))) - -(dshmi shlldl "Logical left shift (long word)" - () - "shlld.l $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 0) rn rd (f-rsvd 0)) - (set rd (ext DI (sll (subword SI rm 1) (and rn 63))))) - -(dshmi shlli "Logical left shift (immediate count)" - () - "shlli $rm, $uimm6, $rd" - (+ (f-op 49) rm (f-ext 1) uimm6 rd (f-rsvd 0)) - (set rd (sll rm uimm6))) - -(dshmi shllil "Logical left shift (long word, immediate count)" - () - "shlli.l $rm, $uimm6, $rd" - (+ (f-op 49) rm (f-ext 0) uimm6 rd (f-rsvd 0)) - (set rd (ext DI (sll (subword SI rm 1) (and uimm6 63))))) - -(dshmi shlrd "Logical right shift" - () - "shlrd $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 3) rn rd (f-rsvd 0)) - (set rd (srl rm (and rn 63)))) - -(dshmi shlrdl "Logical right shift (long word)" - () - "shlrd.l $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 2) rn rd (f-rsvd 0)) - (set rd (ext DI (srl (subword SI rm 1) (and rn 63))))) - -(dshmi shlri "Logical right shift (immediate count)" - () - "shlri $rm, $uimm6, $rd" - (+ (f-op 49) rm (f-ext 3) uimm6 rd (f-rsvd 0)) - (set rd (srl rm uimm6))) - -(dshmi shlril "Logical right shift (long word, immediate count)" - () - "shlri.l $rm, $uimm6, $rd" - (+ (f-op 49) rm (f-ext 2) uimm6 rd (f-rsvd 0)) - (set rd (ext DI (srl (subword SI rm 1) (and uimm6 63))))) - -(dshmi shori "Shift-or immediate" - () - "shori $uimm16, $rd" - (+ (f-op 50) uimm16 rd (f-rsvd 0)) - (set rd (or (sll rd 16) (zext DI uimm16)))) - -(dshmi sleep "Sleep" - () - "sleep" - (+ (f-op 27) (f-left 63) (f-ext 7) (f-right 63) (f-dest 63) (f-rsvd 0)) - (unimp "sleep")) - -(dshmi stb "Store byte" - () - "st.b $rm, $disp10, $rd" - (+ (f-op 40) rm disp10 rd (f-rsvd 0)) - (set (mem UQI (add rm (ext DI disp10))) (and QI rd #xff))) - -(dshmi stl "Store long word" - () - "st.l $rm, $disp10x4, $rd" - (+ (f-op 42) rm disp10x4 rd (f-rsvd 0)) - (set (mem SI (add rm (ext DI disp10x4))) (and SI rd #xffffffff))) - -(dshmi stq "Store quad word" - () - "st.q $rm, $disp10x8, $rd" - (+ (f-op 43) rm disp10x8 rd (f-rsvd 0)) - (set (mem DI (add rm (ext DI disp10x8))) rd)) - -(dshmi stw "Store word" - () - "st.w $rm, $disp10x2, $rd" - (+ (f-op 41) rm disp10x2 rd (f-rsvd 0)) - (set (mem HI (add rm (ext DI disp10x2))) (and HI rd #xffff))) - -(define-pmacro (-sthi-byte) - (sequence () - (set (mem UQI addr) (and QI val #xff)) - (set val (srl val 8)) - (set addr (add addr 1)))) - -(dshmi sthil "Store high part (long word)" - () - "sthi.l $rm, $disp6, $rd" - (+ (f-op 56) rm (f-ext 6) disp6 rd (f-rsvd 0)) - (sequence ((DI addr) (QI bytecount) (DI val)) - (set addr (add rm disp6)) - (set bytecount (add (and addr 3) 1)) - (if endian - (set val rd) - (set val (srl rd (sub 32 (mul 8 bytecount))))) - (set addr (add (sub addr bytecount) 1)) - (if (gt bytecount 3) - (-sthi-byte)) - (if (gt bytecount 2) - (-sthi-byte)) - (if (gt bytecount 1) - (-sthi-byte)) - (if (gt bytecount 0) - (-sthi-byte)))) - -(dshmi sthiq "Store high part (quad word)" - () - "sthi.q $rm, $disp6, $rd" - (+ (f-op 56) rm (f-ext 7) disp6 rd (f-rsvd 0)) - (sequence ((DI addr) (QI bytecount) (DI val)) - (set addr (add rm disp6)) - (set bytecount (add (and addr 7) 1)) - (if endian - (set val rd) - (set val (srl rd (sub 64 (mul 8 bytecount))))) - (set addr (add (sub addr bytecount) 1)) - (if (gt bytecount 7) - (-sthi-byte)) - (if (gt bytecount 6) - (-sthi-byte)) - (if (gt bytecount 5) - (-sthi-byte)) - (if (gt bytecount 4) - (-sthi-byte)) - (if (gt bytecount 3) - (-sthi-byte)) - (if (gt bytecount 2) - (-sthi-byte)) - (if (gt bytecount 1) - (-sthi-byte)) - (if (gt bytecount 0) - (-sthi-byte)))) - -(dshmi stlol "Store low part (long word)" - () - "stlo.l $rm, $disp6, $rd" - (+ (f-op 56) rm (f-ext 2) disp6 rd (f-rsvd 0)) - ; FIXME. - (unimp "stlol")) - -(dshmi stloq "Store low part (quad word)" - () - "stlo.q $rm, $disp6, $rd" - (+ (f-op 56) rm (f-ext 3) disp6 rd (f-rsvd 0)) - ; FIXME. - (unimp "stloq")) - -(dshmi stxb "Store byte (extended displacement)" - () - "stx.b $rm, $rn, $rd" - (+ (f-op 24) rm (f-ext 0) rn rd (f-rsvd 0)) - (set (mem UQI (add rm rn)) (subword QI rd 7))) - -(dshmi stxl "Store long (extended displacement)" - () - "stx.l $rm, $rn, $rd" - (+ (f-op 24) rm (f-ext 2) rn rd (f-rsvd 0)) - (set (mem SI (add rm rn)) (subword SI rd 1))) - -(dshmi stxq "Store quad word (extended displacement)" - () - "stx.q $rm, $rn, $rd" - (+ (f-op 24) rm (f-ext 3) rn rd (f-rsvd 0)) - (set (mem DI (add rm rn)) rd)) - -(dshmi stxw "Store word (extended displacement)" - () - "stx.w $rm, $rn, $rd" - (+ (f-op 24) rm (f-ext 1) rn rd (f-rsvd 0)) - (set (mem HI (add rm rn)) (subword HI rd 3))) - -(dshmi sub "Subtract" - () - "sub $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 11) rn rd (f-rsvd 0)) - (set rd (sub rm rn))) - -(dshmi subl "Subtract long" - () - "sub.l $rm, $rn, $rd" - (+ (f-op 0) rm (f-ext 10) rn rd (f-rsvd 0)) - (set rd (ext DI (sub (subword SI rm 1) (subword SI rn 1))))) - -(dshmi swapq "Swap quad words" - () - "swap.q $rm, $rn, $rd" - (+ (f-op 8) rm (f-ext 3) rn rd (f-rsvd 0)) - (sequence ((DI addr) (DI temp)) - (set addr (add rm rn)) - (set temp (mem DI addr)) - (set (mem DI addr) rd) - (set rd temp))) - -(dshmi synci "Synchronise instruction fetch" - () - "synci" - (+ (f-op 27) (f-left 63) (f-ext 2) (f-right 63) (f-dest 63) (f-rsvd 0)) - (unimp "synci")) - -(dshmi synco "Synchronise data operations" - () - "synco" - (+ (f-op 27) (f-left 63) (f-ext 6) (f-right 63) (f-dest 63) (f-rsvd 0)) - (unimp "synco")) - -(dshmi trapa "Trap" - () - "trapa $rm" - (+ (f-op 27) rm (f-ext 1) (f-right 63) (f-dest 63) (f-rsvd 0)) - (c-call "sh64_trapa" rm pc)) - -(dshmi xor "Exclusive OR" - () - "xor $rm, $rn, $rd" - (+ (f-op 1) rm (f-ext 13) rn rd (f-rsvd 0)) - (set rd (xor rm rn))) - -(dshmi xori "Exclusive OR immediate" - () - "xori $rm, $imm6, $rd" - (+ (f-op 49) rm (f-ext 13) rn rd (f-rsvd 0)) - (set rd (xor rm (ext DI imm6)))) diff --git a/binutils-2.24/cpu/simplify.inc b/binutils-2.24/cpu/simplify.inc deleted file mode 100644 index 808018dc..00000000 --- a/binutils-2.24/cpu/simplify.inc +++ /dev/null @@ -1,218 +0,0 @@ -; Collection of macros, for GNU Binutils .cpu files. -*- Scheme -*- -; -; Copyright 2000, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -; Enums. - -; Define a normal enum without using name/value pairs. -; This is currently the same as define-full-enum but it needn't remain -; that way (it's define-full-enum that would change). - -(define-pmacro (define-normal-enum name comment attrs prefix vals) - "Define a normal enum, fixed number of arguments." - (define-full-enum name comment attrs prefix vals) -) - -; Define a normal insn enum. - -(define-pmacro (define-normal-insn-enum name comment attrs prefix fld vals) - "Define a normal instruction opcode enum." - (define-full-insn-enum name comment attrs prefix fld vals) -) - -; Instruction fields. - -; Normally, fields are unsigned and have no encode/decode needs. - -(define-pmacro (define-normal-ifield name comment attrs start length) - "Define a normal instruction field." - (define-full-ifield name comment attrs start length UINT #f #f) -) - -; For those who don't like typing. - -(define-pmacro (df name comment attrs start length mode encode decode) - "Shorthand form of normal fields requiring mode, encode/decode." - (define-full-ifield name comment attrs start length mode encode decode) -) -(define-pmacro dnf - "Shorthand form of define-normal-ifield." - define-normal-ifield -) - -; Define a normal multi-ifield. - -(define-pmacro (define-normal-multi-ifield name comment attrs - mode subflds insert extract) - "Define a normal multi-part instruction field." - (define-full-multi-ifield name comment attrs mode subflds insert extract) -) - -; For those who don't like typing. - -(define-pmacro dnmf - "Shorthand form of define-normal-multi-ifield." - define-normal-multi-ifield -) - -; Simple multi-ifields: mode is UINT, default insert/extract support, -; default encode/decode support. - -(define-pmacro (dsmf name comment attrs subflds) - "Define a simple multi-part instruction field." - (define-full-multi-ifield name comment attrs UINT subflds #f #f) -) - -; Hardware. - -; Simpler version for most hardware elements. -; Allow special assembler support specification but no semantic-name, -; getter/setter, or layout specs. - -(define-pmacro (define-normal-hardware name comment attrs type - indices values handlers) - "Define a normal hardware element." - (define-full-hardware name comment attrs name type - indices values handlers () () ()) -) - -; For those who don't like typing. - -(define-pmacro dnh - "Shorthand form of define-normal-hardware." - define-normal-hardware -) - -; Simpler version of dnh that leaves out the indices, values, handlers, -; getter/setter, and layout specs. -; This is useful for 1 bit registers. -; ??? While dsh and dnh aren't that distinguishable when perusing a .cpu file, -; they both take a fixed number of positional arguments, and dsh is a proper -; subset of dnh with all arguments in the same positions, so methinks things -; are ok. - -(define-pmacro (define-simple-hardware name comment attrs type) - "Define a simple hardware element (usually a scalar register)." - (define-full-hardware name comment attrs name type () () () () () ()) -) - -(define-pmacro dsh - "Shorthand form of define-simple-hardware." - define-simple-hardware -) - -; Operands. - -; Simpler version for most operands. -; Allow special assembler support specification but no handlers or -; getter/setter specs. - -(define-pmacro (define-normal-operand name comment attrs type index) - "Define a normal operand." - (define-full-operand name comment attrs type DFLT index () () ()) -) - -; For those who don't like typing. - -(define-pmacro dno - "Shorthand form of define-normal-operand." - define-normal-operand -) - -; Deprecated, but still in wide use. - -(define-pmacro dnop - "Shorthand form of define-normal-operand." - define-normal-operand -) - -(define-pmacro (dndo x-name x-mode x-args - x-syntax x-base-ifield x-encoding x-ifield-assertion - x-getter x-setter) - "Define a normal derived operand." - (define-derived-operand - (name x-name) - (mode x-mode) - (args x-args) - (syntax x-syntax) - (base-ifield x-base-ifield) - (encoding x-encoding) - (ifield-assertion x-ifield-assertion) - (getter x-getter) - (setter x-setter) - ) -) - -; Instructions. - -; Define an instruction object, normal version. -; At present all fields must be specified. -; Fields ifield-assertion is absent. - -(define-pmacro (define-normal-insn name comment attrs syntax fmt semantics timing) - "Define a normal instruction." - (define-full-insn name comment attrs syntax fmt () semantics timing) -) - -; To reduce the amount of typing. -; Note that this is the same name as the D'ni in MYST. Oooohhhh..... -; this must be the right way to go. :-) - -(define-pmacro dni - "Shorthand form of define-normal-insn." - define-normal-insn -) - -; Macro instructions. - -; Define a macro-insn object, normal version. -; This only supports expanding to one real insn. - -(define-pmacro (define-normal-macro-insn name comment attrs syntax expansion) - "Define a normal macro instruction." - (define-full-minsn name comment attrs syntax expansion) -) - -; To reduce the amount of typing. - -(define-pmacro dnmi - "Shorthand form of define-normal-macro-insn." - define-normal-macro-insn -) - -; Modes. -; ??? Not currently available for use. -; -; Define Normal Mode -; -;(define-pmacro (define-normal-mode name comment attrs bits bytes -; non-mode-c-type printf-type sem-mode ptr-to host?) -; "Define a normal mode.\n" -; (define-full-mode name comment attrs bits bytes -; non-mode-c-type printf-type sem-mode ptr-to host?) -;) -; -; For those who don't like typing. -;(define-pmacro dnm -; "Shorthand form of define-normal-mode.\n" -; define-normal-mode -;) diff --git a/binutils-2.24/cpu/xc16x.cpu b/binutils-2.24/cpu/xc16x.cpu deleted file mode 100644 index 4903b814..00000000 --- a/binutils-2.24/cpu/xc16x.cpu +++ /dev/null @@ -1,3146 +0,0 @@ -; Infineon XC16X CPU description. -*- Scheme -*- -; -; Copyright 2006, 2007, 2009 Free Software Foundation, Inc. -; -; Contributed by KPIT Cummins Infosystems Ltd.; developed under contract -; from Infineon Systems, GMBH , Germany. -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, 51 Franklin Street - Fifth Floor, Boston, MA -; 02110-1301, USA. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -; define-arch appears first - -(define-arch - (name xc16x) ; name of cpu family - (comment "Infineon XC16X") - (default-alignment aligned) - (insn-lsb0? #t) - (machs xc16x) - (isas xc16x) -) - -; Attributes. -; An attribute to describe which pipeline an insn runs in generally OS. -(define-attr - (for insn) - (type enum) - (name PIPE) - (comment "parallel execution pipeline selection") - (values NONE OS) -) - -; Instruction set parameters. - -(define-isa - (name xc16x) - (default-insn-bitsize 32) - (base-insn-bitsize 32) - (default-insn-word-bitsize 16) - (decode-assist (15 14 13 12)) - ; The XC16X fetches 1 insn at a time. - (liw-insns 1) - (parallel-insns 1) -) - -; Cpu family definitions. - -(define-cpu - ; cpu names must be distinct from the architecture name and machine names. - ; The "b" suffix stands for "base" and is the convention. - ; The "f" suffix stands for "family" and is the convention. - (name xc16xbf) - (comment "Infineon XC16X base family") - (endian little) - (insn-chunk-bitsize 32) - (word-bitsize 16) - (parallel-insns 1) -) - -(define-mach - (name xc16x) - (comment "Infineon XC16X cpu") - (cpu xc16xbf) -) - -; Model descriptions. - -(define-model - (name xc16x) (comment "XC16X") (attrs) - (mach xc16x) - - (pipeline p-mem "" () ((prefetch) (fetch) (decode) (address) (memory) (execute) (writeback))) - - ; `state' is a list of variables for recording model state - (state - ; bit mask of h-gr registers, =1 means value being loaded from memory - (h-gr UINT) - ) - - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () ; state - ((dr INT -1) (sr INT -1)) ; inputs - ((dr INT -1)) ; outputs - () ; profile action (default) - ) - (unit u-cmp "Compare Unit" () - 1 1 ; issue done - () ; state - ((src1 INT -1) (src2 INT -1)) ; inputs - () ; outputs - () ; profile action (default) - ) - (unit u-cti "Jump & Call Unit" () - 1 1 ; issue done - () ; state - ((condbit) (sr INT -1)) ; inputs - ((pc)) ; outputs - () ; profile action (default) - ) - (unit u-mov "Data Movement Unit" () - 1 1 ; issue done - () ;state - ((dr INT -1) (sr INT -1)) ; inputs - ((dr INT -1)) ; output - () ; profile action (default) - ) - ) - -; Instruction fields. -; -; Attributes: -; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) -; ABS-ADDR: absolute address (for reloc and disassembly purposes) -; RELOC: there is a relocation associated with this field (experiment) - -(define-attr - (for ifield operand) - (type boolean) - (name RELOC) - (comment "there is a reloc associated with this field (experiment)") -) - -(dnf f-op1 "op1" () 7 4) -(dnf f-op2 "op2" () 3 4) -(dnf f-condcode "condcode" () 7 4) ;condition code required in other jmps and calls -(dnf f-icondcode "indrct condcode" () 15 4) ;condition code required in other jmpi and calli -(dnf f-rcond "relative-cond" () 7 4) ;condition code required in JMPR -(dnf f-qcond "qbit" () 7 4) ;used in enum of bset/bclear macro -(dnf f-extccode "extended condcode" () 15 5) ;condition code required in other jmpa and calla -(dnf f-r0 "r0" () 9 2) ;required where 2 bit register used(only R0-R3) -(dnf f-r1 "r1" () 15 4) -(dnf f-r2 "r2" () 11 4) -(dnf f-r3 "r3" () 12 4) -(dnf f-r4 "r4" () 11 4) -(dnf f-uimm2 "uimm2" () 13 2) ;used for immediate data,eg in ADD,MOV insns -(dnf f-uimm3 "uimm3" () 10 3) ;used for immediate data,eg in ADD,SUB insns -(dnf f-uimm4 "uimm4" () 15 4) ;used for immediate data,eg in MOV insns -(dnf f-uimm7 "uimm7" (PCREL-ADDR RELOC) 15 7) ;used in TRAP -(dnf f-uimm8 "uimm8" () 23 8) ;used in immediate byte data,eg in ADDB,MOVB insns -(dnf f-uimm16 "uimm16" () 31 16) ;used for immediate word data -(dnf f-memory "memory" () 31 16) ; used for memory operands -(dnf f-memgr8 "memory" () 31 16) ; memory location of gr -(dnf f-rel8 "rel8" (PCREL-ADDR RELOC) 15 8) ;used in JMPR,CALLR -(dnf f-relhi8 "relhi8" (PCREL-ADDR RELOC) 23 8) ;used in JB,JBC,JNB,JNBS -(dnf f-reg8 "reg8" () 15 8) ;required where 8bit gp register used -(dnf f-regmem8 "regmem8" () 15 8) ;required where 8bit register used -(dnf f-regoff8 "regoff8" () 15 8) ;required for offset calc -(dnf f-reghi8 "reghi8" () 23 8) ;required where 8bit register number used -(dnf f-regb8 "regb8" () 15 8) ;required for byte registers RL0,RH0, till RL8,RH8 -(dnf f-seg8 "seg8" () 15 8) ;used as segment number in JMPS,CALLS -(dnf f-segnum8 "segnum8" () 23 8) ;used in EXTS,EXTSR -(dnf f-mask8 "mask8" () 23 8) ;used as mask in BFLDH,BFLDL insns -(dnf f-pagenum "page num" () 25 10);used in EXTP,EXTPR -(dnf f-datahi8 "datahi8" () 31 8) ;used for filling with const data -(dnf f-data8 "data8" () 23 8) ;used for filling with const data -(dnf f-offset16 "address offset16" (ABS-ADDR RELOC) 31 16) ;used in JMPS,JMPA,CALLA,CALLS -(dnf f-op-bit1 "gap of 1 bit" () 11 1) ;used for filling with const data -(dnf f-op-bit2 "gap of 2 bits" () 11 2) ;used for filling with const data -(dnf f-op-bit4 "gap of 4 bits" () 11 4) ;used for filling with const data -(dnf f-op-bit3 "gap of 3 bits" () 10 3) ;used in CALLA, JMPA -(dnf f-op-2bit "gap of 2 bits" () 10 2) ;used in CALLA -(dnf f-op-bitone "gap of 1 bit " () 10 1) ;used in JMPA -(dnf f-op-onebit "gap of 1 bit " () 9 1) ;used in JMPA -(dnf f-op-1bit "gap of 1 bit " () 8 1) ;used in JMPA, CALLA -(dnf f-op-lbit4 "gap of 4 bits" () 15 4) ;used for filling with const data -(dnf f-op-lbit2 "gap of 2 bits" () 15 2) ;used for filling with const data -(dnf f-op-bit8 "gap of 8 bits" () 31 8) ;used for filling with const data -(dnf f-op-bit16 "gap of 16 bits" () 31 16) ;used for filling with const data -(dnf f-qbit "qbit" () 7 4) ;used in bit field of bset/bclear -(dnf f-qlobit "qlobit" () 31 4) ;used for filling with const data -(dnf f-qhibit "qhibit" () 27 4) ;used for filling with const data -(dnf f-qlobit2 "qlobit2" () 27 2) ;used for filling with const data -(dnf f-pof "upof16" () 31 16) ; used for memory operands - -; Enums. -; insn-op1: bits 0-3 -(define-normal-insn-enum insn-op1 "insn format enums" () OP1_ f-op1 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "10" "11" "12" "13" "14" "15") -) - -; insn-op2: bits 4-7 -(define-normal-insn-enum insn-op2 "op2 enums" () OP2_ f-op2 - ("0" "1" "2" "3" "4" "5" "6" "7" - "8" "9" "10" "11" "12" "13" "14" "15") -) - -;/*for bclr/bset*/ -; insn-rcond: bits 0-3 -(define-normal-insn-enum insn-qcond "bit set/clear enums" () QBIT_ f-qcond - (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) - ("11" 11) ("12" 12) ("13" 13) ("14" 14) ("15" 15)) -) -;/************/ -; insn-rcond: bits 0-3 -(define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond - (("UC" 0) ("NET" 1) ("Z" 2) ("NE_NZ" 3) ("V" 4) ("NV" 5) ("N" 6) ("NN" 7) - ("C" 8) ("NC" 9) ("SGT" 10) ("SLE" 11) ("SLT" 12) ("SGE" 13) ("UGT" 14) ("ULE" 15) - ("EQ" 2) ("NE" 3) ("ULT" 8) ("UGE" 9)) -) - - - -; Hardware pieces. -; These entries list the elements of the raw hardware. -; They're also used to provide tables and other elements of the assembly -; language. - -(dnh h-pc "program counter" (PC) (pc) () () ()) - -(define-keyword - (name gr-names) - (enum-prefix H-GR-) - (values (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)) - -) -(define-hardware - (name h-gr) - (comment "general registers") - (attrs PROFILE CACHE-ADDR) - (type register HI (16)) - (indices extern-keyword gr-names) -) - -;; HACK: Various semantics refer to h-cr. -;; This is here to keep things working. -(define-hardware - (name h-cr) - (comment "cr registers") - (attrs PROFILE CACHE-ADDR) - (type register HI (16)) - (indices extern-keyword gr-names) -) - -(define-keyword - (name ext-names) - (enum-prefix H-EXT-) - (values (0x1 0) (0x2 1) (0x3 2) (0x4 3) - ("1" 0) ("2" 1) ("3" 2) ("4" 3)) - -) - -(define-hardware - (name h-ext) - (comment "ext values") - (attrs PROFILE CACHE-ADDR) - (type register HI (8)) - (indices extern-keyword ext-names) -) - -(define-keyword - (name psw-names) - (enum-prefix H-PSW-) - (values ("IEN" 136) ("r0.11" 240) ("r1.11" 241) ("r2.11" 242) ("r3.11" 243) ("r4.11" 244) - ("r5.11" 245) ("r6.11" 246) ("r7.11" 247) ("r8.11" 248) - ("r9.11" 249) ("r10.11" 250) ("r11.11" 251) ("r12.11" 252) - ("r13.11" 253) ("r14.11" 254) ("r15.11" 255)) -) - -(define-hardware - (name h-psw) - (comment "ext values") - (attrs PROFILE CACHE-ADDR) - (type register HI (1)) - (indices extern-keyword psw-names) -) - -(define-keyword - (name grb-names) - (enum-prefix H-GRB-) - (values (rl0 0) (rh0 1) (rl1 2) (rh1 3) (rl2 4) (rh2 5) (rl3 6) (rh3 7) - (rl4 8) (rh4 9) (rl5 10) (rh5 11) (rl6 12) (rh6 13) (rl7 14) (rh7 15)) -) - -(define-hardware - (name h-grb) - (comment "general registers") - (attrs PROFILE CACHE-ADDR) - (type register QI (16)) - (indices extern-keyword grb-names) -) - -(define-keyword - (name conditioncode-names) - (enum-prefix H-CC-) - (values (cc_UC 0) (cc_NET 1) (cc_Z 2) (cc_EQ 2) (cc_NZ 3) (cc_NE 3) (cc_V 4) (cc_NV 5) (cc_N 6) (cc_NN 7) (cc_ULT 8) (cc_UGE 9) - (cc_C 8) (cc_NC 9) (cc_SGT 10) (cc_SLE 11) (cc_SLT 12) (cc_SGE 13) (cc_UGT 14) - (cc_ULE 15)) -) -(define-hardware - (name h-cc) - (comment "condition codes") - (attrs PROFILE CACHE-ADDR) - (type register QI (16)) - (indices extern-keyword conditioncode-names) -) - -(define-keyword - (name extconditioncode-names) - (enum-prefix H-ECC-) - (values(cc_UC 0) (cc_NET 2) (cc_Z 4) (cc_EQ 4) (cc_NZ 6) (cc_NE 6) (cc_V 8) (cc_NV 10) (cc_N 12) (cc_NN 14) (cc_ULT 16) (cc_UGE 18) (cc_C 16) (cc_NC 18) (cc_SGT 20) - (cc_SLE 22) (cc_SLT 24) (cc_SGE 26) (cc_UGT 28) (cc_ULE 30) (cc_nusr0 1) - (cc_nusr1 3) (cc_usr0 5) (cc_usr1 7)) -) -(define-hardware - (name h-ecc) - (comment "extended condition codes") - (attrs PROFILE CACHE-ADDR) - (type register QI (4)) - (indices extern-keyword extconditioncode-names) -) - -(define-keyword - (name grb8-names) - (enum-prefix H-GRB8-) - (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) - (psw 136) (cp 8) (mdl 7) (mdh 6) - (mdc 135) (sp 9) (csp 4) (vecseg 137) - (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) - (zeros 142) (ones 143) (spseg 134) (tfr 214) - (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247) - (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255)) -) - -(define-hardware - (name h-grb8) - (comment "general byte registers") - (attrs PROFILE CACHE-ADDR) - (type register QI (36)) - (indices extern-keyword grb8-names) -) - -(define-keyword - (name r8-names) - (enum-prefix H-R8-) - (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) - (psw 136) (cp 8) (mdl 7) (mdh 6) - (mdc 135) (sp 9) (csp 4) (vecseg 137) - (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) - (zeros 142) (ones 143) (spseg 134) (tfr 214) - (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247) - (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255)) -) - -(define-hardware - (name h-r8) - (comment "registers") - (attrs PROFILE CACHE-ADDR) - (type register HI (36)) - (indices extern-keyword r8-names) -) - -(define-keyword - (name regmem8-names) - (enum-prefix H-REGMEM8-) - (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) - (psw 136) (cp 8) (mdl 7) (mdh 6) - (mdc 135) (sp 9) (csp 4) (vecseg 137) - (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) - (zeros 142) (ones 143) (spseg 134) (tfr 214) - (r0 240) (r1 241) (r2 242) (r3 243) (r4 244) (r5 245) (r6 246) (r7 247) - (r8 248) (r9 249) (r10 250) (r11 251) (r12 252) (r13 253) (r14 254) (r15 255)) -) - -(define-hardware - (name h-regmem8) - (comment "registers") - (attrs ) - (type register HI (16)) - (indices extern-keyword regmem8-names) -) - -(define-keyword - (name regdiv8-names) - (enum-prefix H-REGDIV8-) - (values (r0 0) (r1 17) (r2 34) (r3 51) (r4 68) (r5 85) (r6 102) (r7 119) - (r8 136) (r9 153) (r10 170) (r11 187) (r12 204) (r13 221) (r14 238) (r15 255)) -) - -(define-hardware - (name h-regdiv8) - (comment "division insn registers") - (attrs PROFILE CACHE-ADDR) - (type register HI (16)) - (indices extern-keyword regdiv8-names) -) - -(define-keyword - (name reg0-name) - (enum-prefix H-REG0-) - (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) (0x8 8) (0x9 9) (0xa 10) (0xb 11) - (0xc 12) (0xd 13) (0xe 14) (0xf 15) - ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11) - ("12" 12) ("13" 13) ("14" 14) ("15" 15)) -) - -(define-hardware - (name h-r0) - (comment "for 4-bit data excuding 0") - (attrs PROFILE CACHE-ADDR) - (type register HI (30)) - (indices extern-keyword reg0-name) -) - -(define-keyword - (name reg0-name1) - (enum-prefix H-REG01-) - (values (0x1 1) (0x2 2) (0x3 3) (0x4 4) (0x5 5) (0x6 6) (0x7 7) - ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5) ("6" 6) ("7" 7)) -) - -(define-hardware - (name h-r01) - (comment "for 4-bit data excuding 0") - (attrs PROFILE CACHE-ADDR) - (type register HI (14)) - (indices extern-keyword reg0-name1) -) - -(define-keyword - (name regbmem8-names) - (enum-prefix H-REGBMEM8-) - (values (dpp0 0) (dpp1 1) (dpp2 2) (dpp3 3) - (psw 136) (cp 8) (mdl 7) (mdh 6) - (mdc 135) (sp 9) (csp 4) (vecseg 137) - (stkov 10) (stkun 11) (cpucon1 12) (cpucon2 13) - (zeros 142) (ones 143) (spseg 134) (tfr 214) - (rl0 240) (rh0 241) (rl1 242) (rh1 243) (rl2 244) (rh2 245) (rl3 246) (rh3 247) - (rl4 248) (rh4 249) (rl5 250) (rh5 251) (rl6 252) (rh6 253) (rl7 254) (rh7 255)) -) - -(define-hardware - (name h-regbmem8) - (comment "registers") - (attrs PROFILE CACHE-ADDR) - (type register HI (36)) - (indices extern-keyword regbmem8-names) -) - -(define-keyword - (name memgr8-names) - (enum-prefix H-MEMGR8-) - (values (dpp0 65024) (dpp1 65026) (dpp2 65028) (dpp3 65030) - (psw 65296) (cp 65040) (mdl 65038) (mdh 65036) - (mdc 65294) (sp 65042) (csp 65032) (vecseg 65298) - (stkov 65044) (stkun 65046) (cpucon1 65048) (cpucon2 65050) - (zeros 65308) (ones 65310) (spseg 65292) (tfr 65452) ) -) - -(define-hardware - (name h-memgr8) - (comment "memory location of registers") - (attrs ) - (type register HI (20)) - (indices extern-keyword memgr8-names) -) - -(dsh h-cond "condition bit" () (register BI)) ;any bit from PSW while comparison -; This bit is part of the PSW register -(dsh h-cbit "carry bit" () (register BI)) - -(dsh h-sgtdis "segmentation enable bit" () (register BI)) ;0 means segmentation enabled - -;Instruction operands -; -- layer between the assembler and the raw hardware description -; -- the main means of manipulating instruction fields in the semantic code - -; XC16X specific operand attributes: - -(define-attr - (for operand) - (type boolean) - (name HASH-PREFIX) - (comment "immediates have an optional '#' prefix") -) - -(define-attr - (for operand) - (type boolean) - (name DOT-PREFIX) - (comment "bit addr have an optional '.' prefix") -) - -(define-attr - (for operand) - (type boolean) - (name POF-PREFIX) - (comment "page offset ") -) - -(define-attr - (for operand) - (type boolean) - (name PAG-PREFIX) - (comment "page ") -) - -(define-attr - (for operand) - (type boolean) - (name SOF-PREFIX) - (comment "segment offset selection") -) - -(define-attr - (for operand) - (type boolean) - (name SEG-PREFIX) - (comment "segment") -) - -;; Define an operand that takes a set of handlers. -;; dowh: define-operand-with-handlers -(define-pmacro (dowh x-name x-comment x-attrs x-type x-index x-handlers) - (define-operand (name x-name) (comment x-comment) - (.splice attrs (.unsplice x-attrs)) - (type x-type) (index x-index) - (.splice handlers (.unsplice x-handlers))) -) - -(dnop sr "source register" () h-gr f-r2) -(dnop dr "destination register" () h-gr f-r1) -(dnop dri "destination register" () h-gr f-r4) -(dnop srb "source register" () h-grb f-r2) -(dnop drb "destination register" () h-grb f-r1) -(dnop sr2 "2 bit source register" () h-gr f-r0) -(dnop src1 "source register 1" () h-gr f-r1) -(dnop src2 "source register 2" () h-gr f-r2) -(dnop srdiv "source register 2" () h-regdiv8 f-reg8) -(dnop RegNam "PSW bits" () h-psw f-reg8) -(dnop uimm2 "2 bit unsigned number" (HASH-PREFIX) h-ext f-uimm2) -(dnop uimm3 "3 bit unsigned number" (HASH-PREFIX) h-r01 f-uimm3) -(dnop uimm4 "4 bit unsigned number" (HASH-PREFIX) h-uint f-uimm4) -(dnop uimm7 "7 bit trap number" (HASH-PREFIX) h-uint f-uimm7) -(dnop uimm8 "8 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm8) -(dnop uimm16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-uimm16) -(dowh upof16 "16 bit unsigned immediate" (POF-PREFIX) h-addr f-memory ((print "with_pof_prefix"))) -(dnop reg8 "8 bit word register number" () h-r8 f-reg8) -(dnop regmem8 "8 bit word register number" () h-regmem8 f-regmem8) -(dnop regbmem8 "8 bit byte register number" () h-regbmem8 f-regmem8) -(dnop regoff8 "8 bit word register number" () h-r8 f-regoff8) -(dnop reghi8 "8 bit word register number" () h-r8 f-reghi8) -(dnop regb8 "8 bit byte register number" () h-grb8 f-regb8) -(dnop genreg "8 bit word register number" () h-r8 f-regb8) -(dnop seg "8 bit segment number" () h-uint f-seg8) -(dnop seghi8 "8 bit hi segment number" () h-uint f-segnum8) -(dnop caddr "16 bit address offset" () h-addr f-offset16) -(dnop rel "8 bit signed relative offset" () h-sint f-rel8) -(dnop relhi "hi 8 bit signed relative offset" () h-sint f-relhi8) -(dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) -(dnop bit1 "gap of 1 bit" () h-uint f-op-bit1) -(dnop bit2 "gap of 2 bits" () h-uint f-op-bit2) -(dnop bit4 "gap of 4 bits" () h-uint f-op-bit4) -(dnop lbit4 "gap of 4 bits" () h-uint f-op-lbit4) -(dnop lbit2 "gap of 2 bits" () h-uint f-op-lbit2) -(dnop bit8 "gap of 8 bits" () h-uint f-op-bit8) -(dnop u4 "gap of 4 bits" () h-r0 f-uimm4) -(dnop bitone "field of 1 bit" () h-uint f-op-onebit) -(dnop bit01 "field of 1 bit" () h-uint f-op-1bit) -(dnop cond "condition code" () h-cc f-condcode) -(dnop icond "indirect condition code" () h-cc f-icondcode) -(dnop extcond "extended condition code" () h-ecc f-extccode) -(dnop memory "16 bit memory" () h-addr f-memory) -(dnop memgr8 "16 bit memory" () h-memgr8 f-memgr8) -(dnop cbit "carry bit" (SEM-ONLY) h-cbit f-nil) -(dowh qbit "bit addr" (DOT-PREFIX) h-uint f-qbit ((print "with_dot_prefix"))) -(dowh qlobit "bit addr" (DOT-PREFIX) h-uint f-qlobit ((print "with_dot_prefix"))) -(dowh qhibit "bit addr" (DOT-PREFIX) h-uint f-qhibit ((print "with_dot_prefix"))) -(dnop mask8 "8 bit mask" (HASH-PREFIX) h-uint f-mask8) -(dnop masklo8 "8 bit mask" (HASH-PREFIX) h-uint f-datahi8) -(dnop pagenum "10 bit page number" (HASH-PREFIX) h-uint f-pagenum) -(dnop data8 "8 bit data" (HASH-PREFIX) h-uint f-data8) -(dnop datahi8 "8 bit data" (HASH-PREFIX) h-uint f-datahi8) -(dnop sgtdisbit "segmentation enable bit" (SEM-ONLY) h-sgtdis f-nil) -(dowh upag16 "16 bit unsigned immediate" (PAG-PREFIX) h-uint f-uimm16 ((print "with_pag_prefix"))) -(dnop useg8 "8 bit segment " (SEG-PREFIX) h-uint f-seg8) -(dnop useg16 "16 bit address offset" (SEG-PREFIX) h-uint f-offset16) -(dnop usof16 "16 bit address offset" (SOF-PREFIX) h-uint f-offset16) - -; define hash operator -(define-operand (name hash) (comment "# prefix") (attrs) - (type h-sint) - (index f-nil) - (handlers (parse "hash") (print "hash")) -) - -; define dot operator -(define-operand (name dot) (comment ". prefix") (attrs) - (type h-sint) - (index f-nil) - (handlers (parse "dot") (print "dot")) -) - -; define pof operator -(define-operand (name pof) (comment "pof: prefix") (attrs) - (type h-sint) - (index f-nil) - (handlers (parse "pof") (print "pof")) -) - -; define pag operator -(define-operand (name pag) (comment "pag: prefix") (attrs) - (type h-sint) - (index f-nil) - (handlers (parse "pag") (print "pag")) -) - -; define sof operator -(define-operand (name sof) (comment "sof: prefix") (attrs) - (type h-sint) - (index f-nil) - (handlers (parse "sof") (print "sof")) -) - -; define seg operator -(define-operand (name segm) (comment "seg: prefix") (attrs) - (type h-sint) - (index f-nil) - (handlers (parse "seg") (print "seg")) -) - -; IDOC attribute for instruction documentation. -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MOVE - () "Data Movement") - (ALU - () "Arithmatic & logical") - (CMP - () "Compare") - (JMP - () "Jump & Call") - (MISC - () "Miscellaneous") - (SYSC - () "System control") - ) -) - -; Include the instruction set descriptions from their respective -; source files. - -;Arithmatic insns -;****************************************************************** - -;add/sub register and immediate -(define-pmacro (arithmetic16 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"dir"$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 (mem HI op2))) - () - ) -) -(arithmetic16 addrpof add add OP1_0 OP2_2 reg8 upof16 HI "pof") -(arithmetic16 subrpof sub sub OP1_2 OP2_2 reg8 upof16 HI "pof") -(arithmetic16 addbrpof addb add OP1_0 OP2_3 regb8 upof16 QI "pof") -(arithmetic16 subbrpof subb sub OP1_2 OP2_3 regb8 upof16 QI "pof") -(arithmetic16 addrpag add add OP1_0 OP2_2 reg8 upag16 HI "pag") -(arithmetic16 subrpag sub sub OP1_2 OP2_2 reg8 upag16 HI "pag") -(arithmetic16 addbrpag addb add OP1_0 OP2_3 regb8 upag16 QI "pag") -(arithmetic16 subbrpag subb sub OP1_2 OP2_3 regb8 upag16 QI "pag") - -;add/sub register and immediate -(define-pmacro (arithmetic17 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"dir"$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 (mem HI op2) cbit)) - () - ) -) -(arithmetic17 addcrpof addc addc OP1_1 OP2_2 reg8 upof16 HI "pof") -(arithmetic17 subcrpof subc subc OP1_3 OP2_2 reg8 upof16 HI "pof") -(arithmetic17 addcbrpof addcb addc OP1_1 OP2_3 regb8 upof16 QI "pof") -(arithmetic17 subcbrpof subcb subc OP1_3 OP2_3 regb8 upof16 QI "pof") -(arithmetic17 addcrpag addc addc OP1_1 OP2_2 reg8 upag16 HI "pag") -(arithmetic17 subcrpag subc subc OP1_3 OP2_2 reg8 upag16 HI "pag") -(arithmetic17 addcbrpag addcb addc OP1_1 OP2_3 regb8 upag16 QI "pag") -(arithmetic17 subcbrpag subcb subc OP1_3 OP2_3 regb8 upag16 QI "pag") - -;add/sub register and immediate -(define-pmacro (arithmetic18 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"dir"$"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) (insn1 (mem HI op1) op2 )) - () - ) -) -(arithmetic18 addrpofr add add OP1_0 OP2_4 upof16 reg8 HI "pof") -(arithmetic18 subrpofr sub sub OP1_2 OP2_4 upof16 reg8 HI "pof") -(arithmetic18 addbrpofr addb add OP1_0 OP2_5 upof16 regb8 QI "pof") -(arithmetic18 subbrpofr subb sub OP1_2 OP2_5 upof16 regb8 QI "pof") - -;add/sub register and immediate -(define-pmacro (arithmetic19 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"dir"$"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) (insn1 mode (mem HI op1) op2 cbit)) - () - ) -) -(arithmetic19 addcrpofr addc addc OP1_1 OP2_4 upof16 reg8 HI "pof") -(arithmetic19 subcrpofr subc subc OP1_3 OP2_4 upof16 reg8 HI "pof") -(arithmetic19 addcbrpofr addcb addc OP1_1 OP2_5 upof16 regb8 QI "pof") -(arithmetic19 subcbrpofr subcb subc OP1_3 OP2_5 upof16 regb8 QI "pof") - -;add/sub register and immediate -(define-pmacro (arithmetic20 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic20 addrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pof") -(arithmetic20 subrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pof") -(arithmetic20 addbrhpof add add OP1_0 OP2_6 reg8 uimm16 HI "pag") -(arithmetic20 subbrhpof sub sub OP1_2 OP2_6 reg8 uimm16 HI "pag") - -;add/sub register and immediate -(define-pmacro (arithmetic21 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 (f-op-bit1 0) op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic21 addrhpof3 add add OP1_0 OP2_8 dr uimm3 HI "pof") -(arithmetic21 subrhpof3 sub sub OP1_2 OP2_8 dr uimm3 HI "pof") -(arithmetic21 addbrhpag3 addb add OP1_0 OP2_9 drb uimm3 QI "pag") -(arithmetic21 subbrhpag3 subb sub OP1_2 OP2_9 drb uimm3 QI "pag") -(arithmetic21 addrhpag3 add add OP1_0 OP2_8 dr uimm3 HI "pag") -(arithmetic21 subrhpag3 sub sub OP1_2 OP2_8 dr uimm3 HI "pag") -(arithmetic21 addbrhpof3 addb add OP1_0 OP2_9 drb uimm3 QI "pof") -(arithmetic21 subbrhpof3 subb sub OP1_2 OP2_9 drb uimm3 QI "pof") - -;add/sub register and immediate -(define-pmacro (arithmetic22 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 op2 (f-op-bit8 0)) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic22 addrbhpof addb add OP1_0 OP2_7 regb8 uimm8 QI "pof") -(arithmetic22 subrbhpof subb sub OP1_2 OP2_7 regb8 uimm8 QI "pof") -(arithmetic22 addbrhpag addb add OP1_0 OP2_7 regb8 uimm8 QI "pag") -(arithmetic22 subbrhpag subb sub OP1_2 OP2_7 regb8 uimm8 QI "pag") - -;add/sub register and immediate -(define-pmacro (arithmetic23 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic23 addcrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pof") -(arithmetic23 subcrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pof") -(arithmetic23 addcbrhpof addc addc OP1_1 OP2_6 reg8 uimm16 HI "pag") -(arithmetic23 subcbrhpof subc subc OP1_3 OP2_6 reg8 uimm16 HI "pag") - -;add/sub register and immediate -(define-pmacro (arithmetic24 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 (f-op-bit1 0) op2) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic24 addcrhpof3 addc addc OP1_1 OP2_8 dr uimm3 HI "pof") -(arithmetic24 subcrhpof3 subc subc OP1_3 OP2_8 dr uimm3 HI "pof") -(arithmetic24 addcbrhpag3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pag") -(arithmetic24 subcbrhpag3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pag") -(arithmetic24 addcrhpag3 addc addc OP1_1 OP2_8 dr uimm3 HI "pag") -(arithmetic24 subcrhpag3 subc subc OP1_3 OP2_8 dr uimm3 HI "pag") -(arithmetic24 addcbrhpof3 addcb addc OP1_1 OP2_9 drb uimm3 QI "pof") -(arithmetic24 subcbrhpof3 subcb subc OP1_3 OP2_9 drb uimm3 QI "pof") - -;add/sub register and immediate -(define-pmacro (arithmetic25 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 op2 (f-op-bit8 0)) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic25 addcrbhpof addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pof") -(arithmetic25 subcrbhpof subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pof") -(arithmetic25 addcbrhpag addcb addc OP1_1 OP2_7 regb8 uimm8 QI "pag") -(arithmetic25 subcbrhpag subcb subc OP1_3 OP2_7 regb8 uimm8 QI "pag") - -;add/sub register and immediate -(define-pmacro (arithmetic10 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 (f-op-bit1 0) op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic10 addri add add OP1_0 OP2_8 dr uimm3 HI) -(arithmetic10 subri sub sub OP1_2 OP2_8 dr uimm3 HI) -(arithmetic10 addbri addb add OP1_0 OP2_9 drb uimm3 QI) -(arithmetic10 subbri subb sub OP1_2 OP2_9 drb uimm3 QI) - -;add/sub register and immediate -(define-pmacro (arithmetic11 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic11 addrim add add OP1_0 OP2_6 reg8 uimm16 HI) -(arithmetic11 subrim sub sub OP1_2 OP2_6 reg8 uimm16 HI) - -;add/sub register and immediate -(define-pmacro (arithmetic12 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 op2 (f-op-bit8 0)) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic12 addbrim addb add OP1_0 OP2_7 regb8 uimm8 QI) -(arithmetic12 subbrim subb sub OP1_2 OP2_7 regb8 uimm8 QI) - -;add/sub register and immediate with carry -(define-pmacro (arithmetic13 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 (f-op-bit1 0) op2) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic13 addcri addc addc OP1_1 OP2_8 dr uimm3 HI) -(arithmetic13 subcri subc subc OP1_3 OP2_8 dr uimm3 HI) -(arithmetic13 addcbri addcb addc OP1_1 OP2_9 drb uimm3 QI) -(arithmetic13 subcbri subcb subc OP1_3 OP2_9 drb uimm3 QI) - -;add/sub register and immediate with carry -(define-pmacro (arithmetic14 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic14 addcrim addc addc OP1_1 OP2_6 reg8 uimm16 HI) -(arithmetic14 subcrim subc subc OP1_3 OP2_6 reg8 uimm16 HI) - -;add/sub register and immediate with carry -(define-pmacro (arithmetic15 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 op2 (f-op-bit8 0)) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic15 addcbrim addcb addc OP1_1 OP2_7 regb8 uimm8 QI) -(arithmetic15 subcbrim subcb subc OP1_3 OP2_7 regb8 uimm8 QI) - - -;add/sub registers -(define-pmacro (arithmetic name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(arithmetic addr add add OP1_0 OP2_0 dr sr HI) -(arithmetic subr sub sub OP1_2 OP2_0 dr sr HI) -(arithmetic addbr addb add OP1_0 OP2_1 drb srb QI) -(arithmetic subbr subb sub OP1_2 OP2_1 drb srb QI) - -;add/sub register and indirect memory -(define-pmacro (arithmetic1 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",[$"op2"]") - (+ opc1 opc2 op1 (f-op-bit2 2) op2) - (set mode op1 (insn1 mode op1 (mem HI op2))) - () - ) -) -(arithmetic1 add2 add add OP1_0 OP2_8 dr sr2 HI) -(arithmetic1 sub2 sub sub OP1_2 OP2_8 dr sr2 HI) -(arithmetic1 addb2 addb add OP1_0 OP2_9 drb sr2 QI) -(arithmetic1 subb2 subb sub OP1_2 OP2_9 drb sr2 QI) - -;add/sub register and indirect memory post increment -(define-pmacro (arithmetic2 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",[$"op2"+]") - (+ opc1 opc2 op1 (f-op-bit2 3) op2) - (sequence () - (set mode op1 (insn1 mode op1 (mem HI op2))) - (set HI op2 (add HI op2 (const 2))) - ) - () - ) -) -(arithmetic2 add2i add add OP1_0 OP2_8 dr sr2 HI) -(arithmetic2 sub2i sub sub OP1_2 OP2_8 dr sr2 HI) -(arithmetic2 addb2i addb add OP1_0 OP2_9 drb sr2 QI) -(arithmetic2 subb2i subb sub OP1_2 OP2_9 drb sr2 QI) - -;add/sub registers with carry -(define-pmacro (arithmetic3 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) -(arithmetic3 addcr addc addc OP1_1 OP2_0 dr sr HI) -(arithmetic3 subcr subc subc OP1_3 OP2_0 dr sr HI) -(arithmetic3 addbcr addcb addc OP1_1 OP2_1 drb srb QI) -(arithmetic3 subbcr subcb subc OP1_3 OP2_1 drb srb QI) - - -;add/sub register and indirect memory -(define-pmacro (arithmetic4 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",[$"op2"]") - (+ opc1 opc2 op1 (f-op-bit2 2) op2) - (set mode op1 (insn1 mode op1 (mem HI op2) cbit)) - () - ) -) -(arithmetic4 addcr2 addc addc OP1_1 OP2_8 dr sr2 HI) -(arithmetic4 subcr2 subc subc OP1_3 OP2_8 dr sr2 HI) -(arithmetic4 addbcr2 addcb addc OP1_1 OP2_9 drb sr2 QI) -(arithmetic4 subbcr2 subcb subc OP1_3 OP2_9 drb sr2 QI) - -;add/sub register and indirect memory post increment -(define-pmacro (arithmetic5 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",[$"op2"+]") - (+ opc1 opc2 op1 (f-op-bit2 3) op2) - (sequence () - (set mode op1 (insn1 mode op1 (mem HI op2) cbit)) - (set HI op2 (add HI op2 (const 2))) - ) - () - ) -) -(arithmetic5 addcr2i addc addc OP1_1 OP2_8 dr sr2 HI) -(arithmetic5 subcr2i subc subc OP1_3 OP2_8 dr sr2 HI) -(arithmetic5 addbcr2i addcb addc OP1_1 OP2_9 drb sr2 QI) -(arithmetic5 subbcr2i subcb subc OP1_3 OP2_9 drb sr2 QI) - -;add/sub register and direct memory -(define-pmacro (arithmetic6 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) - -;add/sub register and direct memory -(define-pmacro (arithmetic7 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) (insn1 (mem HI op1) op2)) - () - ) -) -(arithmetic6 addrm2 add add OP1_0 OP2_2 regmem8 memgr8 HI) -(arithmetic7 addrm3 add add OP1_0 OP2_4 memgr8 regmem8 HI) -(arithmetic6 addrm add add OP1_0 OP2_2 reg8 memory HI) -(arithmetic7 addrm1 add add OP1_0 OP2_4 memory reg8 HI) -(arithmetic6 subrm3 sub sub OP1_2 OP2_2 regmem8 memgr8 HI) -(arithmetic7 subrm2 sub sub OP1_2 OP2_4 memgr8 regmem8 HI) -(arithmetic6 subrm1 sub sub OP1_2 OP2_2 reg8 memory HI) -(arithmetic7 subrm sub sub OP1_2 OP2_4 memory reg8 HI) -(arithmetic6 addbrm2 addb add OP1_0 OP2_3 regbmem8 memgr8 QI) -(arithmetic7 addbrm3 addb add OP1_0 OP2_5 memgr8 regbmem8 QI) -(arithmetic6 addbrm addb add OP1_0 OP2_3 regb8 memory QI) -(arithmetic7 addbrm1 addb add OP1_0 OP2_5 memory regb8 QI) -(arithmetic6 subbrm3 subb sub OP1_2 OP2_3 regbmem8 memgr8 QI) -(arithmetic7 subbrm2 subb sub OP1_2 OP2_5 memgr8 regbmem8 QI) -(arithmetic6 subbrm1 subb sub OP1_2 OP2_3 regb8 memory QI) -(arithmetic7 subbrm subb sub OP1_2 OP2_5 memory regb8 QI) - -;add/sub registers with carry -(define-pmacro (arithmetic8 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2 cbit)) - () - ) -) - -;add/sub registers with carry -(define-pmacro (arithmetic9 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) (insn1 (mem HI op1) op2 cbit)) - () - ) -) -(arithmetic8 addcrm2 addc addc OP1_1 OP2_2 regmem8 memgr8 HI) -(arithmetic9 addcrm3 addc addc OP1_1 OP2_4 memgr8 regmem8 HI) -(arithmetic8 addcrm addc addc OP1_1 OP2_2 reg8 memory HI) -(arithmetic9 addcrm1 addc addc OP1_1 OP2_4 memory reg8 HI) -(arithmetic8 subcrm3 subc subc OP1_3 OP2_2 regmem8 memgr8 HI) -(arithmetic9 subcrm2 subc subc OP1_3 OP2_4 memgr8 regmem8 HI) -(arithmetic8 subcrm1 subc subc OP1_3 OP2_2 reg8 memory HI) -(arithmetic9 subcrm subc subc OP1_3 OP2_4 memory reg8 HI) -(arithmetic8 addcbrm2 addcb addc OP1_1 OP2_3 regbmem8 memgr8 QI) -(arithmetic9 addcbrm3 addcb addc OP1_1 OP2_5 memgr8 regbmem8 QI) -(arithmetic8 addcbrm addcb addc OP1_1 OP2_3 regb8 memory QI) -(arithmetic9 addcbrm1 addcb addc OP1_1 OP2_5 memory regb8 QI) -(arithmetic8 subcbrm3 subcb subc OP1_3 OP2_3 regbmem8 memgr8 QI) -(arithmetic9 subcbrm2 subcb subc OP1_3 OP2_5 memgr8 regbmem8 QI) -(arithmetic8 subcbrm1 subcb subc OP1_3 OP2_3 regb8 memory QI) -(arithmetic9 subcbrm subcb subc OP1_3 OP2_5 memory regb8 QI) - -; MUL Rwn,Rwm -(dni muls "signed multiplication" - ((PIPE OS) (IDOC ALU)) - "mul $src1,$src2" - (+ OP1_0 OP2_11 src1 src2) - (nop) ;; FIXME: (reg SI h-md 0) - () -) -; MULU Rwn,Rwm -(dni mulu "unsigned multiplication" - ((PIPE OS) (IDOC ALU)) - "mulu $src1,$src2" - (+ OP1_1 OP2_11 src1 src2) - (nop) ;; FIXME: (reg SI h-md 0) - () -) -; DIV Rwn -(dni div "16-by-16 signed division" - ((PIPE OS) (IDOC ALU)) - "div $srdiv" - (+ OP1_4 OP2_11 srdiv ) - (sequence () - (set HI (reg HI h-cr 6) (div HI (reg HI h-cr 6) srdiv)) - (set HI (reg HI h-cr 7) (mod HI (reg HI h-cr 6) srdiv)) - ) - () -) -; DIVL Rwn -(dni divl "32-by16 signed division" - ((PIPE OS) (IDOC ALU)) - "divl $srdiv" - (+ OP1_6 OP2_11 srdiv ) - (sequence () - (set HI (reg HI h-cr 6) 0) ;; FIXME: (div SI (reg SI h-md 0) srdiv)) - (set HI (reg HI h-cr 7) 0) ;; FIXME: (mod SI (reg SI h-md 0) srdiv)) - ) - () -) -; DIVLU Rwn -(dni divlu "32-by16 unsigned division" - ((PIPE OS) (IDOC ALU)) - "divlu $srdiv" - (+ OP1_7 OP2_11 srdiv ) - (sequence () - (set HI (reg HI h-cr 6) 0) ;; FIXME: (udiv SI (reg SI h-md 0) srdiv)) - (set HI (reg HI h-cr 7) 0) ;; FIXME: (umod SI (reg SI h-md 0) srdiv)) - ) - () -) -; DIVU Rwn -(dni divu "16-by-16 unsigned division" - ((PIPE OS) (IDOC ALU)) - "divu $srdiv" - (+ OP1_5 OP2_11 srdiv ) - (sequence () - (set HI (reg HI h-cr 6) (udiv HI (reg HI h-cr 6) srdiv)) - (set HI (reg HI h-cr 7) (umod HI (reg HI h-cr 6) srdiv)) - ) - () -) - -;Integer one's complement -; CPL Rwn -(dni cpl "Integer Ones complement" - ((PIPE OS) (IDOC MISC)) - "cpl $dr" - (+ OP1_9 OP2_1 dr (f-op-bit4 0)) - (set dr (inv HI dr)) - () -) - -;Bytes one's complement -; CPLB Rbn -(dni cplb "Byte Ones complement" - ((PIPE OS) (IDOC MISC)) - "cplb $drb" - (+ OP1_11 OP2_1 drb (f-op-bit4 0)) - (set drb (inv QI drb)) - () -) -;Integer two's complement -; NEG Rwn -(dni neg "Integer two's complement" - ((PIPE OS) (IDOC MISC)) - "neg $dr" - (+ OP1_8 OP2_1 dr (f-op-bit4 0)) - (set dr (neg HI dr)) - () -) -;Bytes two's complement -; NEGB Rbn -(dni negb "byte twos complement" - ((PIPE OS) (IDOC MISC)) - "negb $drb" - (+ OP1_10 OP2_1 drb (f-op-bit4 0)) - (set drb (neg QI drb)) - () -) - -;**************************************************************** -;logical insn -;**************************************************************** -;and/or/xor registers -(define-pmacro (logical name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "logical" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) - -(logical andr and and OP1_6 OP2_0 dr sr HI) -(logical orr or or OP1_7 OP2_0 dr sr HI) -(logical xorr xor xor OP1_5 OP2_0 dr sr HI) -(logical andbr andb and OP1_6 OP2_1 drb srb QI) -(logical orbr orb or OP1_7 OP2_1 drb srb QI) -(logical xorbr xorb xor OP1_5 OP2_1 drb srb QI) - -;and/or/xor register and immediate -(define-pmacro (logical1 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "logical" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 (f-op-bit1 0) op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(logical1 andri and and OP1_6 OP2_8 dr uimm3 HI) -(logical1 orri or or OP1_7 OP2_8 dr uimm3 HI) -(logical1 xorri xor xor OP1_5 OP2_8 dr uimm3 HI) -(logical1 andbri andb and OP1_6 OP2_9 drb uimm3 QI) -(logical1 orbri orb or OP1_7 OP2_9 drb uimm3 QI) -(logical1 xorbri xorb xor OP1_5 OP2_9 drb uimm3 QI) - -;and/or/xor register and immediate -(define-pmacro (logical2 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "logical" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(logical2 andrim and and OP1_6 OP2_6 reg8 uimm16 HI) -(logical2 orrim or or OP1_7 OP2_6 reg8 uimm16 HI) -(logical2 xorrim xor xor OP1_5 OP2_6 reg8 uimm16 HI) - -;and/or/xor register and immediate -(define-pmacro (logical3 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "logical" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 op2 (f-op-bit8 0)) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(logical3 andbrim andb and OP1_6 OP2_7 regb8 uimm8 QI) -(logical3 orbrim orb or OP1_7 OP2_7 regb8 uimm8 QI) -(logical3 xorbrim xorb xor OP1_5 OP2_7 regb8 uimm8 QI) - -;and/or/xor register and indirect memory -(define-pmacro (logical4 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "logical" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",[$"op2"]") - (+ opc1 opc2 op1 (f-op-bit2 2) op2) - (set mode op1 (insn1 mode op1 (mem HI op2))) - () - ) -) -(logical4 and2 and and OP1_6 OP2_8 dr sr2 HI) -(logical4 or2 or or OP1_7 OP2_8 dr sr2 HI) -(logical4 xor2 xor xor OP1_5 OP2_8 dr sr2 HI) -(logical4 andb2 andb and OP1_6 OP2_9 drb sr2 QI) -(logical4 orb2 orb or OP1_7 OP2_9 drb sr2 QI) -(logical4 xorb2 xorb xor OP1_5 OP2_9 drb sr2 QI) - -;and/or/xor register and indirect memory post increment -(define-pmacro (logical5 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "logical" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",[$"op2"+]") - (+ opc1 opc2 op1 (f-op-bit2 3) op2) - (sequence () - (set mode op1 (insn1 mode op1 (mem HI op2))) - (set HI op2 (add HI op2 (const 2))) - ) - () - ) -) -(logical5 and2i and and OP1_6 OP2_8 dr sr2 HI) -(logical5 or2i or or OP1_7 OP2_8 dr sr2 HI) -(logical5 xor2i xor xor OP1_5 OP2_8 dr sr2 HI) -(logical5 andb2i andb and OP1_6 OP2_9 drb sr2 QI) -(logical5 orb2i orb or OP1_7 OP2_9 drb sr2 QI) -(logical5 xorb2i xorb xor OP1_5 OP2_9 drb sr2 QI) - -;add/sub register and immediate -(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"dir"$"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set (mem HI op1) (insn1 (mem HI op1) op2 )) - () - ) -) -(logical7 andpofr and and OP1_6 OP2_2 reg8 upof16 HI "pof") -(logical7 orpofr or or OP1_7 OP2_2 reg8 upof16 HI "pof") -(logical7 xorpofr xor xor OP1_5 OP2_2 reg8 upof16 HI "pof") -(logical7 andbpofr andb and OP1_6 OP2_3 regb8 upof16 QI "pof") -(logical7 orbpofr orb or OP1_7 OP2_3 regb8 upof16 QI "pof") -(logical7 xorbpofr xorb xor OP1_5 OP2_3 regb8 upof16 QI "pof") - -;add/sub register and immediate -(define-pmacro (logical8 name insn insn1 opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"dir"$"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set (mem HI op1) (insn1 (mem HI op1) op2 )) - () - ) -) -(logical8 andrpofr and and OP1_6 OP2_4 upof16 reg8 HI "pof") -(logical8 orrpofr or or OP1_7 OP2_4 upof16 reg8 HI "pof") -(logical8 xorrpofr xor xor OP1_5 OP2_4 upof16 reg8 HI "pof") -(logical8 andbrpofr andb and OP1_6 OP2_5 upof16 regb8 QI "pof") -(logical8 orbrpofr orb or OP1_7 OP2_5 upof16 regb8 QI "pof") -(logical8 xorbrpofr xorb xor OP1_5 OP2_5 upof16 regb8 QI "pof") - -;and/or/xor register and direct memory -(define-pmacro (logical6 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) - -;and/or/xor register and direct memory -(define-pmacro (logical7 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "arithmetic" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) (insn1 (mem HI op1) op2)) - () - ) -) -(logical6 andrm2 and and OP1_6 OP2_2 regmem8 memgr8 HI) -(logical7 andrm3 and and OP1_6 OP2_4 memgr8 regmem8 HI) -(logical6 andrm and and OP1_6 OP2_2 reg8 memory HI) -(logical7 andrm1 and and OP1_6 OP2_4 memory reg8 HI) -(logical6 orrm3 or or OP1_7 OP2_2 regmem8 memgr8 HI) -(logical7 orrm2 or or OP1_7 OP2_4 memgr8 regmem8 HI) -(logical6 orrm1 or or OP1_7 OP2_2 reg8 memory HI) -(logical7 orrm or or OP1_7 OP2_4 memory reg8 HI) -(logical6 xorrm3 xor xor OP1_5 OP2_2 regmem8 memgr8 HI) -(logical7 xorrm2 xor xor OP1_5 OP2_4 memgr8 regmem8 HI) -(logical6 xorrm1 xor xor OP1_5 OP2_2 reg8 memory HI) -(logical7 xorrm xor xor OP1_5 OP2_4 memory reg8 HI) -(logical6 andbrm2 andb and OP1_6 OP2_3 regbmem8 memgr8 QI) -(logical7 andbrm3 andb and OP1_6 OP2_5 memgr8 regbmem8 QI) -(logical6 andbrm andb and OP1_6 OP2_3 regb8 memory QI) -(logical7 andbrm1 andb and OP1_6 OP2_5 memory regb8 QI) -(logical6 orbrm3 orb or OP1_7 OP2_3 regbmem8 memgr8 QI) -(logical7 orbrm2 orb or OP1_7 OP2_5 memgr8 regbmem8 QI) -(logical6 orbrm1 orb or OP1_7 OP2_3 regb8 memory QI) -(logical7 orbrm orb or OP1_7 OP2_5 memory regb8 QI) -(logical6 xorbrm3 xorb xor OP1_5 OP2_3 regbmem8 memgr8 QI) -(logical7 xorbrm2 xorb xor OP1_5 OP2_5 memgr8 regbmem8 QI) -(logical6 xorbrm1 xorb xor OP1_5 OP2_3 regb8 memory QI) -(logical7 xorbrm xorb xor OP1_5 OP2_5 memory regb8 QI) - -;**************************************************************** -;logical insn -;**************************************************************** -;mov registers -(define-pmacro (move name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "mov registers" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 op2) - () - ) -) -(move movr mov OP1_15 OP2_0 dr sr HI) -(move movrb movb OP1_15 OP2_1 drb srb HI) - -;mov register and immediate -(define-pmacro (move1 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op2 op1) - (set mode op1 op2) - () - ) -) -(move1 movri mov OP1_14 OP2_0 dri u4 HI) -(move1 movbri movb OP1_14 OP2_1 srb u4 QI) - -; MOV Rwn,#data16 -(dni movi "move immediate to register" - ((PIPE OS) (IDOC MOVE)) - "mov $reg8,$hash$uimm16" - (+ OP1_14 OP2_6 reg8 uimm16) - (set HI reg8 uimm16) - () -) - -; MOVB reg,#data8 -(dni movbi "move immediate to register" - ((PIPE OS) (IDOC MOVE)) - "movb $regb8,$hash$uimm8" - (+ OP1_14 OP2_7 regb8 uimm8 (f-op-bit8 0)) - (set QI regb8 uimm8) - () -) - -;move and indirect memory -(define-pmacro (mov2 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",[$"op2"]") - (+ opc1 opc2 op1 op2) - (set mode op1 (mem HI op2)) - () - ) -) -(mov2 movr2 mov OP1_10 OP2_8 dr sr HI) -(mov2 movbr2 movb OP1_10 OP2_9 drb sr QI) - -;move and indirect memory -(define-pmacro (mov3 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [$"op2 "],$"op1) - (+ opc1 opc2 op1 op2) - (set mode op1 (mem HI op2)) - () - ) -) -(mov3 movri2 mov OP1_11 OP2_8 dr sr HI) -(mov3 movbri2 movb OP1_11 OP2_9 drb sr QI) - -;move and indirect memory -(define-pmacro (mov4 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [-$"op2 "],$"op1) - (+ opc1 opc2 op1 op2) - (sequence () - (set op1 (sub op2 (const HI 2))) - (set HI (mem HI op2) op1) - ) - () - ) -) -(mov4 movri3 mov OP1_8 OP2_8 dr sr HI) -(mov4 movbri3 movb OP1_8 OP2_9 drb sr QI) - -;mov register and indirect memory post increment -(define-pmacro (mov5 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",[$"op2"+]") - (+ opc1 opc2 op1 op2) - (sequence () - (set mode op1 (mem HI op2)) - (set HI op2 (add HI op2 (const 2))) - ) - () - ) -) -(mov5 mov2i mov OP1_9 OP2_8 dr sr HI) -(mov5 movb2i movb OP1_9 OP2_9 drb sr HI) - -;mov indirect memory -(define-pmacro (mov6 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [$"op1 "],[$"op2"]") - (+ opc1 opc2 op1 op2) - (set HI (mem HI op1) (mem HI op2)) - () - ) -) -(mov6 mov6i mov OP1_12 OP2_8 dr sr HI) -(mov6 movb6i movb OP1_12 OP2_9 dr sr HI) - -;mov indirect memory -(define-pmacro (mov7 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [$"op1 "+],[$"op2"]") - (+ opc1 opc2 op1 op2) - (sequence () - (set mode (mem mode op1) (mem mode op2)) - (set mode op1 (add mode op1 (const mode 2))) - ) - () - ) -) -(mov7 mov7i mov OP1_13 OP2_8 dr sr HI) -(mov7 movb7i movb OP1_13 OP2_9 dr sr HI) - -;mov indirect memory -(define-pmacro (mov8 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [$"op1 "],[$"op2"+]") - (+ opc1 opc2 op1 op2) - (sequence () - (set mode (mem mode op1) (mem mode op2)) - (set mode op2 (add mode op2 (const mode 2))) - ) - () - ) -) -(mov8 mov8i mov OP1_14 OP2_8 dr sr HI) -(mov8 movb8i movb OP1_14 OP2_9 dr sr HI) - -;mov indirect memory -(define-pmacro (mov9 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",[$"op2"+$hash$"uimm16"]") - (+ opc1 opc2 op1 op2 uimm16) - (sequence ((mode tmp1)) - (set mode tmp1 (add HI op2 uimm16)) - (set mode op1 (mem HI tmp1)) - ) - () - ) -) -(mov9 mov9i mov OP1_13 OP2_4 dr sr HI) -(mov9 movb9i movb OP1_15 OP2_4 drb sr QI) - -;mov indirect memory -(define-pmacro (mov10 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [$"op2"+$hash$"uimm16 "],$"op1) - (+ opc1 opc2 op1 op2 uimm16) - (sequence ((mode tmp1)) - (set mode tmp1 (add HI op1 uimm16)) - (set mode (mem HI tmp1) op1) - ) - () - ) -) -(mov10 mov10i mov OP1_12 OP2_4 dr sr HI) -(mov10 movb10i movb OP1_14 OP2_4 drb sr QI) - -;move and indirect memory -(define-pmacro (mov11 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " [$"op1 "],$"op2) - (+ opc1 opc2 (f-op-lbit4 0) op1 op2) - (set (mem mode op1) (mem HI op2)) - () - ) -) -(mov11 movri11 mov OP1_8 OP2_4 src2 memory HI) -(mov11 movbri11 movb OP1_10 OP2_4 src2 memory HI) - -;move and indirect memory -(define-pmacro (mov12 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op2 ",[$"op1"]") - (+ opc1 opc2 (f-op-lbit4 0) op1 op2) - (set (mem HI op2) (mem mode op1)) - () - ) -) -(mov12 movri12 mov OP1_9 OP2_4 src2 memory HI) -(mov12 movbri12 movb OP1_11 OP2_4 src2 memory HI) - -(define-pmacro (movemem3 name insn opc1 opc2 op1 op2 dir) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 op2) - (set HI op1 op2) - () - ) -) -(movemem3 movehm5 mov OP1_14 OP2_6 regoff8 upof16 "pof") -(movemem3 movehm6 mov OP1_14 OP2_6 regoff8 upag16 "pag") -(movemem3 movehm7 mov OP1_14 OP2_6 regoff8 useg16 "segm") -(movemem3 movehm8 mov OP1_14 OP2_6 regoff8 usof16 "sof") - -(define-pmacro (movemem4 name insn opc1 opc2 op1 op2 dir) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op1 op2 (f-op-bit8 0)) - (set QI op1 op2) - () - ) -) -(movemem4 movehm9 movb OP1_14 OP2_7 regb8 uimm8 "pof") -(movemem4 movehm10 movb OP1_14 OP2_7 regoff8 uimm8 "pag") - -(define-pmacro (movemem name insn opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$"dir"$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (mem HI op2)) - () - ) -) -(movemem movrmp mov OP1_15 OP2_2 regoff8 upof16 HI "pof") -(movemem movrmp1 movb OP1_15 OP2_3 regb8 upof16 QI "pof") -(movemem movrmp2 mov OP1_15 OP2_2 regoff8 upag16 HI "pag") -(movemem movrmp3 movb OP1_15 OP2_3 regb8 upag16 QI "pag") - -(define-pmacro (movemem1 name insn opc1 opc2 op1 op2 dir) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"dir"$"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) op2 ) - () - ) -) -(movemem1 movrmp4 mov OP1_15 OP2_6 upof16 regoff8 "pof") -(movemem1 movrmp5 movb OP1_15 OP2_7 upof16 regb8 "pof") - -(define-pmacro (movemem2 name insn opc1 opc2 op1 op2 mode dir) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$hash$"dir"$"op2) - (+ opc1 opc2 op2 op1) - (set mode op1 op2) - () - ) -) -(movemem2 movehm1 mov OP1_14 OP2_0 dri u4 HI "pof") -(movemem2 movehm2 movb OP1_14 OP2_1 srb u4 QI "pof") -(movemem2 movehm3 mov OP1_14 OP2_0 dri u4 HI "pag") -(movemem2 movehm4 movb OP1_14 OP2_1 srb u4 QI "pag") - -;move register and direct memory -(define-pmacro (move12 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (mem HI op2)) - () - ) -) - -;move register and direct memory -(define-pmacro (move13 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set (mem HI op1) op2) - () - ) -) -(move12 mve12 mov OP1_15 OP2_2 regmem8 memgr8 HI) -(move13 mve13 mov OP1_15 OP2_6 memgr8 regmem8 HI) -(move12 mover12 mov OP1_15 OP2_2 reg8 memory HI) -(move13 mvr13 mov OP1_15 OP2_6 memory reg8 HI) -(move12 mver12 movb OP1_15 OP2_3 regbmem8 memgr8 QI) -(move13 mver13 movb OP1_15 OP2_7 memgr8 regbmem8 QI) -(move12 movr12 movb OP1_15 OP2_3 regb8 memory QI) -(move13 movr13 movb OP1_15 OP2_7 memory regb8 QI) - -; MOVBS Rw,Rb -(dni movbsrr "mov byte register with sign extension to word register" - ((PIPE OS) (IDOC MOVE)) - "movbs $sr,$drb" - (+ OP1_13 OP2_0 drb sr) - (sequence () - (if (and QI drb (const 128)) - (set HI sr (or HI (const HI 65280) drb))) - (set HI sr (and HI (const HI 255) drb)) - ) - () -) - -; MOVBZ Rw,Rb -(dni movbzrr "mov byte register with zero extension to word register" - ((PIPE OS) (IDOC MOVE)) - "movbz $sr,$drb" - (+ OP1_12 OP2_0 drb sr) - (set HI sr (and HI (const HI 255) drb)) - () -) - -; MOVBS reg,POF mem -(dni movbsrpofm "mov memory to byte register" - ((PIPE OS) (IDOC MOVE)) - "movbs $regmem8,$pof$upof16" - (+ OP1_13 OP2_2 regmem8 upof16) - (set QI regmem8 (mem HI upof16)) - () -) - -; MOVBS pof,reg -(dni movbspofmr "mov memory to byte register" - ((PIPE OS) (IDOC MOVE)) - "movbs $pof$upof16,$regbmem8" - (+ OP1_13 OP2_5 upof16 regbmem8 ) - (set QI (mem HI upof16) regbmem8) - () -) - -; MOVBZ reg,POF mem -(dni movbzrpofm "mov memory to byte register" - ((PIPE OS) (IDOC MOVE)) - "movbz $reg8,$pof$upof16" - (+ OP1_12 OP2_2 reg8 upof16) - (set QI reg8 (mem HI upof16)) - () -) - -; MOVBZ pof,reg -(dni movbzpofmr "mov memory to byte register" - ((PIPE OS) (IDOC MOVE)) - "movbz $pof$upof16,$regb8" - (+ OP1_12 OP2_5 upof16 regb8 ) - (set QI (mem HI upof16) regb8) - () -) - -;move register and direct memory -(define-pmacro (move14 name insn opc1 opc2 op1 op2 ) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set HI op1 (and HI (const HI 255) (mem QI op2))) - () - ) -) - -;move register and direct memory -(define-pmacro (move15 name insn opc1 opc2 op1 op2 ) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op2 op1) - (set HI (mem HI op1) (and HI (const HI 255) op2)) - () - ) -) -(move14 movebs14 movbs OP1_13 OP2_2 regmem8 memgr8 ) -(move15 movebs15 movbs OP1_13 OP2_5 memgr8 regbmem8 ) -(move14 moverbs14 movbs OP1_13 OP2_2 reg8 memory ) -(move15 movrbs15 movbs OP1_13 OP2_5 memory regb8 ) -(move14 movebz14 movbz OP1_12 OP2_2 regmem8 memgr8 ) -(move15 movebz15 movbz OP1_12 OP2_5 memgr8 regbmem8 ) -(move14 moverbz14 movbz OP1_12 OP2_2 reg8 memory ) -(move15 movrbz15 movbz OP1_12 OP2_5 memory regb8 ) - - -;mov registers -(define-pmacro (moveb1 name insn opc1 opc2 op1 op2) - (dni name - (.str name "move" ) - ((PIPE OS) (IDOC MOVE)) - (.str insn " $"op2 ",$"op1) - (+ opc1 opc2 op1 op2) - (sequence () - (if (and QI op1 (const 128)) - (set HI op2 (or HI (const HI 65280) op1))) - (set HI op2 (and HI (const HI 255) op1)) - ) - () - ) -) -(moveb1 movrbs movbs OP1_13 OP2_0 drb sr ) -(moveb1 movrbz movbz OP1_12 OP2_0 drb sr ) - - - -;jump and call insns -;****************************************************************** -;Absolute conditional jump -(define-pmacro (jmpabs name insn) - (dni name - (.str name "Absolute conditional jump" ) - ((PIPE OS) (IDOC JMP)) - (.str insn " $extcond,$caddr") - (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone bit01 caddr) - (sequence ((HI tmp1) (HI tmp2)) - (set tmp1 (mem HI caddr)) - (set tmp2 (sub HI pc (mem HI caddr))) - (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32)) - (set bitone (const 1))) - (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32)) - (set bitone (const 0))) - (if (eq extcond (const 1)) ;; FIXME: (ne extcond cc_Z)) - (set bit01 (const 0)) - (set HI pc (mem HI caddr))) - (if (ne extcond (const 1)) ;; FIXME: (eq extcond cc_Z)) - (set bit01 (const 1)) - (set HI pc (add HI pc (const 2)))) - ) - () - ) -) - -(jmpabs jmpa0 jmpa+) -(jmpabs jmpa1 jmpa) - -; JMPA- cc,caddr -(dni jmpa- "Absolute conditional jump" - (COND-CTI (PIPE OS) (IDOC JMP)) - "jmpa- $extcond,$caddr" - (+ OP1_14 OP2_10 extcond (f-op-bitone 0) bitone (f-op-1bit 1) caddr) - (sequence ((HI tmp1) (HI tmp2)) - (set tmp1 (mem HI caddr)) - (set tmp2 (sub HI pc (mem HI caddr))) - (if (gt tmp2 (const 0)) ;; FIXME: (lt tmp2 (const 32)) (eq tmp2 (const 32)) - (set bitone (const 1))) - (if (lt tmp2 (const 0)) ;; FIXME: (eq tmp2 (const 0)) (gt tmp2 (const 32)) - (set bitone (const 0))) - (set HI pc (add HI pc (const 2))) - ) - () -) - -; JMPI cc,[Rwn] -(dni jmpi "Indirect conditional jump" - (COND-CTI (PIPE OS) (IDOC JMP)) - "jmpi $icond,[$sr]" - (+ OP1_9 OP2_12 icond sr) - (sequence () - (if (eq icond (const 1)) - (set HI pc (mem HI sr))) - (set HI pc (add HI pc (const 2))) - ) - () -) - -(define-pmacro (jmprel name insn opc1) - (dni name - (.str name "conditional" ) - (COND-CTI (PIPE OS) (IDOC JMP)) - (.str insn " $cond,$rel") - (+ opc1 OP2_13 rel) - (sequence () - (if (eq cond (const 1)) - (sequence () - (if (lt QI rel (const 0)) - (sequence () - ;; FIXME: (neg QI rel) - ;; FIXME: (add QI rel (const 1)) - ;; FIXME: (mul QI rel (const 2)) - (set HI pc (sub HI pc rel)) - )) - (set HI pc (add HI pc (mul QI rel (const 2)))) - ) - ) - (set HI pc pc) - ) - () - ) -) - -(jmprel jmpr_nenz jmpr COND_NE_NZ ) -(jmprel jmpr_sgt jmpr COND_SGT ) -(jmprel jmpr_z jmpr COND_Z ) -(jmprel jmpr_v jmpr COND_V ) -(jmprel jmpr_nv jmpr COND_NV ) -(jmprel jmpr_n jmpr COND_N ) -(jmprel jmpr_nn jmpr COND_NN ) -(jmprel jmpr_c jmpr COND_C ) -(jmprel jmpr_nc jmpr COND_NC ) -(jmprel jmpr_eq jmpr COND_EQ ) -(jmprel jmpr_ne jmpr COND_NE ) -(jmprel jmpr_ult jmpr COND_ULT ) -(jmprel jmpr_ule jmpr COND_ULE ) -(jmprel jmpr_uge jmpr COND_UGE ) -(jmprel jmpr_ugt jmpr COND_UGT ) -(jmprel jmpr_sle jmpr COND_SLE ) -(jmprel jmpr_sge jmpr COND_SGE ) -(jmprel jmpr_net jmpr COND_NET ) -(jmprel jmpr_uc jmpr COND_UC ) -(jmprel jmpr_slt jmpr COND_SLT ) - - - - -; JMPS seg,caddr -(dni jmpseg "absolute inter-segment jump" - (UNCOND-CTI(PIPE OS) (IDOC JMP)) - "jmps $hash$segm$useg8,$hash$sof$usof16" - (+ OP1_15 OP2_10 seg usof16) - (sequence () - (if (eq BI sgtdisbit (const BI 0)) - (set QI (reg h-cr 10) useg8)) - ;; FIXME: previous indentation suggested this nop was the `else' - ;; clause of the previous `if'. - (nop) - (set HI pc usof16) - ) - () -) - -; JMPS seg,caddr -(dni jmps "absolute inter-segment jump" - (UNCOND-CTI(PIPE OS) (IDOC JMP)) - "jmps $seg,$caddr" - (+ OP1_15 OP2_10 seg caddr) - (sequence () - (if (eq BI sgtdisbit (const BI 0)) - (set QI (reg h-cr 10) seg)) - ;; FIXME: previous indentation suggested this nop was the `else' - ;; clause of the previous `if'. - (nop) - (set HI pc caddr) - ) - () -) - - -;relative jump if bit set -;JB bitaddrQ.q,rel -(dni jb "relative jump if bit set" - ((PIPE OS) (IDOC JMP)) - "jb $genreg$dot$qlobit,$relhi" - (+ OP1_8 OP2_10 genreg relhi qlobit (f-qhibit 0)) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 genreg) - (set HI tmp2 (const 1)) - ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) - (set HI tmp2 (and tmp1 tmp2)) - (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)? - (sequence () - (if (lt QI relhi (const 0)) - (set HI pc (add HI pc (mul QI relhi (const 2))))) - )) - (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? - ) - () -) - -;relative jump if bit set and clear bit -;JBC bitaddrQ.q,rel -(dni jbc "relative jump if bit set and clear bit" - ((PIPE OS) (IDOC JMP)) - "jbc $genreg$dot$qlobit,$relhi" - (+ OP1_10 OP2_10 genreg relhi qlobit (f-qhibit 0)) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 genreg) - (set HI tmp2 (const 1)) - ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) - (set HI tmp2 (and tmp1 tmp2)) - (if (eq tmp2 (const 1)) ;; FIXME: (ne tmp2 0)? - (sequence () - ;; FIXME: The `else' clause has several statements. - (if (lt QI relhi (const 0)) - (set tmp2 (const 1)) - (set tmp1 genreg) - ;; FIXME: (sll tmp2 qlobit) - ;; FIXME: (inv tmp2) - (set HI tmp1 (and tmp1 tmp2)) - (set HI genreg tmp1) - (set HI pc (add HI pc (mul QI relhi (const 2))))) - )) - (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? - ) - () -) - -;relative jump if bit set -;JNB bitaddrQ.q,rel -(dni jnb "relative jump if bit not set" - ((PIPE OS) (IDOC JMP)) - "jnb $genreg$dot$qlobit,$relhi" - (+ OP1_9 OP2_10 genreg relhi qlobit (f-qhibit 0)) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 genreg) - (set HI tmp2 (const 1)) - ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) - (set HI tmp2 (and tmp1 tmp2)) - (if (eq tmp2 (const 0)) ;; FIXME: (ne tmp2 0)? - (sequence () - (if (lt QI relhi (const 0)) - (set HI pc (add HI pc (mul QI relhi (const 2))))) - )) - (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? - ) - () -) - -;relative jump if bit not set and set bit -;JNBS bitaddrQ.q,rel -(dni jnbs "relative jump if bit not set and set bit" - ((PIPE OS) (IDOC JMP)) - "jnbs $genreg$dot$qlobit,$relhi" - (+ OP1_11 OP2_10 genreg relhi qlobit (f-qhibit 0)) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 genreg) - (set HI tmp2 (const 1)) - ;;(sll HI tmp2 qlobit) - FIXME: missing (set ...) - (set HI tmp2 (and tmp1 tmp2)) - (if (eq tmp2 (const 0)) - (sequence () - ;; FIXME: The `else' clause has several statements. - (if (lt QI relhi (const 0)) - (set tmp2 (const 1)) - (set tmp1 reg8) - ;; FIXME: (sll tmp2 qbit) - (set BI tmp1(or tmp1 tmp2)) - (set HI reg8 tmp1) - (set HI pc (add HI pc (mul QI relhi (const 2))))) - )) - (set HI pc (add HI pc (const 4))) ;; FIXME: Is this right? - ) - () -) - - -;Absolute conditional call -(define-pmacro (callabs name insn) - (dni name - (.str name "Absolute conditional call" ) - ((PIPE OS) (IDOC JMP)) - (.str insn " $extcond,$caddr") - (+ OP1_12 OP2_10 extcond (f-op-2bit 0) bit01 caddr) - (sequence () - (if (eq extcond (const 1)) - (set bit01 (const 0)) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (set HI pc (mem HI caddr))) - (if (ne extcond (const 1)) - (set bit01 (const 1)) - (set HI pc (add HI pc (const 2)))) - ) - () - ) -) - -(callabs calla0 calla+) -(callabs calla1 calla) - -; CALLA- cc,caddr -(dni calla- "Absolute conditional call" - (COND-CTI (PIPE OS) (IDOC JMP)) - "calla- $extcond,$caddr" - (+ OP1_12 OP2_10 extcond (f-op-bit3 1) caddr) - (sequence () - (if (eq extcond (const 1)) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (set HI pc (mem HI caddr))) - (set HI pc (add HI pc (const 2))) - ) - () -) - -; CALLI cc,[Rwn] -(dni calli "indirect subroutine call" - (COND-CTI (PIPE OS) (IDOC JMP)) - "calli $icond,[$sr]" - (+ OP1_10 OP2_11 icond sr) - (sequence () - (if (eq icond (const 1)) - (sequence () - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (set HI pc (mem HI sr)) - ) - ) - (set HI pc (add HI pc (const 2))) - ) - () -) - -; CALLR rel -(dni callr "Call subroutine with PC relative signed 8 bit offset" - ( COND-CTI (PIPE OS) (IDOC JMP)) - "callr $rel" - (+ OP1_11 OP2_11 rel) - (sequence () - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (sequence () - (if (lt QI rel (const 0)) - (sequence () - ;; FIXME: (neg QI rel) - ;; FIXME: (add QI rel (const 1)) - ;; FIXME: (mul QI rel (const 2)) - (set HI pc (sub HI pc rel)) - )) - (set HI pc (add HI pc (mul QI rel (const 2)))) - ) - ) - () -) - - -; CALLS seg,caddr -(dni callseg "call inter-segment subroutine" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "calls $hash$segm$useg8,$hash$sof$usof16" - (+ OP1_13 OP2_10 useg8 usof16) - (sequence () - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) (reg h-cr 10)) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (if (eq BI sgtdisbit (const BI 0)) - (set QI (reg h-cr 10) useg8)) - ;; FIXME: previous indentation suggested this nop was the `else' - ;; clause of the previous `if'. - (nop) - (set HI pc usof16) - ) - () -) - -; CALLS seg,caddr -(dni calls "call inter-segment subroutine" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "calls $seg,$caddr" - (+ OP1_13 OP2_10 seg caddr) - (sequence () - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) (reg h-cr 10)) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (if (eq BI sgtdisbit (const BI 0)) - (set QI (reg h-cr 10) seg)) - ;; FIXME: previous indentation suggested this nop was the `else' - ;; clause of the previous `if'. - (nop) - (set HI pc caddr) - ) - () -) - -; PCALL reg,caddr -(dni pcall "push word and call absolute subroutine" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "pcall $reg8,$caddr" - (+ OP1_14 OP2_2 reg8 caddr) - (sequence ((HI tmp1)) - (set HI tmp1 reg8) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) tmp1) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (set HI pc caddr) - ) - () -) - -; TRAP #uimm7 -(dni trap "software trap" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "trap $hash$uimm7" - (+ OP1_9 OP2_11 uimm7 (f-op-1bit 0)) - (sequence () - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) (reg h-cr 4)) - (if (eq BI sgtdisbit (const BI 0)) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) (reg h-cr 10) ) - ) - (nop) - (set HI (reg h-cr 10) (reg h-cr 11)) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) pc) - (set HI pc (mul QI uimm7 (const 4))) - ) - () -) - -;Return insns -; RET -(dni ret "return from subroutine" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "ret" - (+ OP1_12 OP2_11 (f-op-bit8 0)) - (sequence () - (set HI pc (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - ) - () -) - -; RETS -(dni rets "return from inter-segment sunroutine" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "rets" - (+ OP1_13 OP2_11 (f-op-bit8 0)) - (sequence () - (set HI pc (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - (if (eq BI sgtdisbit (const BI 0)) - (set HI (reg h-cr 10) (mem HI (reg h-cr 9))) - ) - (nop) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - ) - () -) - -; RETP reg -(dni retp "return from subroutine and pop word register" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "retp $reg8" - (+ OP1_14 OP2_11 reg8) - (sequence ((HI tmp1)) - (set HI pc (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - (set HI tmp1 (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - (set HI reg8 tmp1) - ) - () -) - -; RETI -(dni reti "return from ISR" - (UNCOND-CTI (PIPE OS) (IDOC JMP)) - "reti" - (+ OP1_15 OP2_11 (f-op-lbit4 8) (f-op-bit4 8)) - (sequence () - (set HI pc (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - (if (eq BI sgtdisbit (const BI 0)) - (sequence () - (set HI (reg h-cr 10) (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - ) - ) - (nop) - (set HI (reg h-cr 4) (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - ) - () -) - -;stack operation insn -;****************************************************************** -; POP reg -(dni pop "restore register from system stack" - ((PIPE OS) (IDOC MISC)) - "pop $reg8" - (+ OP1_15 OP2_12 reg8) - (sequence ((HI tmp1)) - (set HI tmp1 (mem HI (reg h-cr 9))) - (set (reg h-cr 9) (add HI (reg h-cr 9) (const 2))) - (set HI reg8 tmp1) - ) - () -) - -; PUSH reg -(dni push "save register on system stack" - ((PIPE OS) (IDOC MISC)) - "push $reg8" - (+ OP1_14 OP2_12 reg8) - (sequence ((HI tmp1)) - (set HI tmp1 reg8) - (set (reg h-cr 9) (sub HI (reg h-cr 9) (const 2))) - (set HI (mem HI (reg h-cr 9)) tmp1) - ) - () -) - -;context switching insns -; SCXT reg,#data16 -(dni scxti "Push word register on stack and update same with immediate data" - ((PIPE OS) (IDOC MISC)) - "scxt $reg8,$hash$uimm16" - (+ OP1_12 OP2_6 reg8 uimm16) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 reg8) - (set HI tmp2 uimm16) - ;; FIXME: (sub HI (reg HI h-cr 9) (const 2)) - (set HI (reg HI h-cr 9) tmp1) - (set HI reg8 tmp2) - ) - () -) - -; SCXT reg,POF mem -(dni scxtrpofm "mov memory to byte register" - ((PIPE OS) (IDOC MOVE)) - "scxt $reg8,$pof$upof16" - (+ OP1_13 OP2_6 reg8 upof16) - (set QI reg8 (mem HI upof16)) - () -) - -; SCXT regmem8,memgr8 -(dni scxtmg "Push word register on stack and update same with direct memory" - ((PIPE OS) (IDOC MISC)) - "scxt $regmem8,$memgr8" - (+ OP1_13 OP2_6 regmem8 memgr8) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 regmem8) - (set HI tmp2 memgr8) - ;; FIXME: (sub HI (reg HI h-cr 9) (const 2)) - (set HI (reg HI h-cr 9) tmp1) - (set HI regmem8 tmp2) - ) - () -) - -; SCXT reg,mem -(dni scxtm "Push word register on stack and update same with direct memory" - ((PIPE OS) (IDOC MISC)) - "scxt $reg8,$memory" - (+ OP1_13 OP2_6 reg8 memory) - (sequence ((HI tmp1) (HI tmp2)) - (set HI tmp1 reg8) - (set HI tmp2 memory) - ;; FIXME: (sub HI (reg HI h-cr 9) (const 2)) - (set HI (reg HI h-cr 9) tmp1) - (set HI reg8 tmp2) - ) - () -) - -;No operation -; NOP -(dni nop "nop" - ((PIPE OS) (IDOC MISC)) - "nop" - (+ OP1_12 OP2_12 (f-op-bit8 0)) - () - () -) - -;*********system control instructions *********************/ - -(define-pmacro (sysctrl name insn opc1 opc2 op1 op2 op3) - (dni name - (.str name "miscellaneous" ) - ((PIPE OS) (IDOC MISC)) - (.str insn ) - (+ opc1 opc2 (f-op-lbit4 op1) (f-op-bit4 op2) (f-data8 op3) (f-op-bit8 op3)) - () - () - ) -) -(sysctrl srstm srst OP1_11 OP2_7 4 8 183 ) -(sysctrl idlem idle OP1_8 OP2_7 7 8 135) -(sysctrl pwrdnm pwrdn OP1_9 OP2_7 6 8 151) -(sysctrl diswdtm diswdt OP1_10 OP2_5 5 10 165) -(sysctrl enwdtm enwdt OP1_8 OP2_5 7 10 133) -(sysctrl einitm einit OP1_11 OP2_5 4 10 181) -(sysctrl srvwdtm srvwdt OP1_10 OP2_7 5 8 167 ) - -;s/w brk -; SBRK -(dni sbrk "sbrk" - ((PIPE OS) (IDOC MISC)) - "sbrk" - (+ OP1_8 OP2_12 (f-op-bit8 0)) - () - () -) - -; atomic sequence -; ATOMIC #irang2 -(dni atomic "begin atomic sequence" - ((PIPE OS) (IDOC SYSC)) - "atomic $hash$uimm2" - (+ OP1_13 OP2_1 (f-op-lbit2 0) uimm2 (f-op-bit4 0)) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended register sequence -; EXTR #irang2 -(dni extr "begin extended register sequence" - ((PIPE OS) (IDOC SYSC)) - "extr $hash$uimm2" - (+ OP1_13 OP2_1 (f-op-lbit2 2) uimm2 (f-op-bit4 0)) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended page sequence -; EXTP Rw,#irang2 -(dni extp "begin extended page sequence" - ((PIPE OS) (IDOC SYSC)) - "extp $sr,$hash$uimm2" - (+ OP1_13 OP2_12 (f-op-lbit2 1) uimm2 sr) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended page sequence -; EXTP #pag10,#irang2 -(dni extp1 "begin extended page sequence" - ((PIPE OS) (IDOC SYSC)) - "extp $hash$pagenum,$hash$uimm2" - (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0)) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -; EXTP #pag10,#irang2 -(dni extpg1 "begin extended page sequence" - ((PIPE OS) (IDOC SYSC)) - "extp $hash$pag$upag16,$hash$uimm2" - (+ OP1_13 OP2_7 (f-op-lbit2 1) uimm2 (f-op-bit4 0) upag16 ) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended page and register sequence -; EXTPR Rw,#irang2 -(dni extpr "begin extended page and register sequence" - ((PIPE OS) (IDOC SYSC)) - "extpr $sr,$hash$uimm2" - (+ OP1_13 OP2_12 (f-op-lbit2 3) uimm2 sr) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended page and register sequence -; EXTPR #pag10,#irang2 -(dni extpr1 "begin extended page sequence" - ((PIPE OS) (IDOC SYSC)) - "extpr $hash$pagenum,$hash$uimm2" - (+ OP1_13 OP2_7 (f-op-lbit2 3) uimm2 (f-op-bit4 0) pagenum (f-qlobit 0) (f-qlobit2 0)) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended segment sequence -; EXTS Rw,#irang2 -(dni exts "begin extended segment sequence" - ((PIPE OS) (IDOC SYSC)) - "exts $sr,$hash$uimm2" - (+ OP1_13 OP2_12 (f-op-lbit2 0) uimm2 sr) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended segment sequence -; EXTS #seg8,#irang2 -(dni exts1 "begin extended segment sequence" - ((PIPE OS) (IDOC SYSC)) - "exts $hash$seghi8,$hash$uimm2" - (+ OP1_13 OP2_7 (f-op-lbit2 0) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0)) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended segment register sequence -; EXTSR Rwm,#irang2 -(dni extsr "begin extended segment and register sequence" - ((PIPE OS) (IDOC SYSC)) - "extsr $sr,$hash$uimm2" - (+ OP1_13 OP2_12 (f-op-lbit2 2) uimm2 sr) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;extended segment register sequence -; EXTSR #pag10,#irang2 -(dni extsr1 "begin extended segment and register sequence" - ((PIPE OS) (IDOC SYSC)) - "extsr $hash$seghi8,$hash$uimm2" - (+ OP1_13 OP2_7 (f-op-lbit2 2) uimm2 (f-op-bit4 0) seghi8 (f-op-bit8 0)) - (sequence ((HI count)) - (set HI count uimm2) - (cond - ((ne HI count (const 0)) - (sequence () - (set HI pc (add HI pc (const 2))) - (set HI count (sub HI count (const 1))) - )) - ) - (set HI count (const 0)) - ) - () -) - -;prioritize register -;PRIOR Rwn,Rwm -(dni prior "add registers" - ((PIPE OS) (IDOC ALU)) - "prior $dr,$sr" - (+ OP1_2 OP2_11 dr sr) - (sequence ((HI count) (HI tmp1) (HI tmp2)) - (set HI count (const 0)) - (set HI tmp1 sr) - (set HI tmp2 (and tmp1 (const 32768))) - (cond - ((ne HI tmp2 (const 1)) ;;(ne HI sr (const 0)) - FIXME: and? or? - ;;(sll HI tmp1 (const 1)) - FIXME: missing (set ...) - (set HI tmp2 (and tmp1 (const 32768))) - (set HI count (add HI count (const 1))) - ) - ) - (set HI dr count) - ) - () -) - - -;bit instructions -;****************************************************************** -;bit clear -(define-pmacro (bclear name insn opc1) - (dni name - (.str name "bit clear" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $reg8$dot$qbit") - (+ opc1 OP2_14 reg8) - (sequence ((HI tmp1) (HI tmp2)) - (set tmp2 (const 1)) - (set tmp1 reg8) - ;; FIXME: (sll tmp2 qbit) - ;; FIXME: (inv tmp2) - (set BI tmp1(and tmp1 tmp2)) - (set HI reg8 tmp1)) - () - ) -) - -;clear direct bit -(dni bclr18 "bit logical MOVN" - ((PIPE OS) (IDOC ALU)) - "bclr $RegNam" - (+ OP1_11 OP2_14 RegNam) - (sequence ((HI tmp1) (HI tmp2)) - (set tmp2 (const 1)) - (set tmp1 reg8) - ;; FIXME: (sll tmp2 qbit) - ;; FIXME: (inv tmp2) - (set BI tmp1(and tmp1 tmp2)) - (set HI reg8 tmp1)) - () -) - - -(bclear bclr0 bclr QBIT_0 ) -(bclear bclr1 bclr QBIT_1 ) -(bclear bclr2 bclr QBIT_2 ) -(bclear bclr3 bclr QBIT_3 ) -(bclear bclr4 bclr QBIT_4 ) -(bclear bclr5 bclr QBIT_5 ) -(bclear bclr6 bclr QBIT_6 ) -(bclear bclr7 bclr QBIT_7 ) -(bclear bclr8 bclr QBIT_8 ) -(bclear bclr9 bclr QBIT_9 ) -(bclear bclr10 bclr QBIT_10 ) -(bclear bclr11 bclr QBIT_11 ) -(bclear bclr12 bclr QBIT_12 ) -(bclear bclr13 bclr QBIT_13 ) -(bclear bclr14 bclr QBIT_14 ) -(bclear bclr15 bclr QBIT_15 ) - -;set direct bit -(dni bset19 "bit logical MOVN" - ((PIPE OS) (IDOC ALU)) - "bset $RegNam" - (+ OP1_11 OP2_15 RegNam) - (sequence ((HI tmp1) (HI tmp2)) - (set tmp2 (const 1)) - (set tmp1 reg8) - ;; FIXME: (sll tmp2 qbit) - (set BI tmp1(or tmp1 tmp2)) - (set HI reg8 tmp1)) - () -) - -;bit set -(define-pmacro (bitset name insn opc1) - (dni name - (.str name "bit set" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $reg8$dot$qbit") - (+ opc1 OP2_15 reg8) - (sequence ((HI tmp1) (HI tmp2)) - (set tmp2 (const 1)) - (set tmp1 reg8) - ;; FIXME: (sll tmp2 qbit) - (set BI tmp1(or tmp1 tmp2)) - (set HI reg8 tmp1)) - () - ) -) - - -(bitset bset0 bset QBIT_0 ) -(bitset bset1 bset QBIT_1 ) -(bitset bset2 bset QBIT_2 ) -(bitset bset3 bset QBIT_3 ) -(bitset bset4 bset QBIT_4 ) -(bitset bset5 bset QBIT_5 ) -(bitset bset6 bset QBIT_6 ) -(bitset bset7 bset QBIT_7 ) -(bitset bset8 bset QBIT_8 ) -(bitset bset9 bset QBIT_9 ) -(bitset bset10 bset QBIT_10 ) -(bitset bset11 bset QBIT_11 ) -(bitset bset12 bset QBIT_12 ) -(bitset bset13 bset QBIT_13 ) -(bitset bset14 bset QBIT_14 ) -(bitset bset15 bset QBIT_15 ) - -;mov direct bit -;BMOV bitaddrZ.z,bitaddrQ.q -(dni bmov "bit logical MOV" - ((PIPE OS) (IDOC ALU)) - "bmov $reghi8$dot$qhibit,$reg8$dot$qlobit" - (+ OP1_4 OP2_10 reg8 reghi8 qhibit qlobit) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) - (set HI tmp1 reghi8) - (set HI tmp2 reg8) - (set tmp3 (const 1)) - (set tmp4 (const 1)) - ;; FIXME: (sll tmp3 qlobit) - ;; FIXME: (sll tmp4 qhibit) - ;; FIXME: (and tmp1 tmp3) - ;; FIXME: (and tmp2 tmp4) - (set BI tmp1 tmp2) - (set HI reghi8 tmp1) - (set HI reg8 tmp2)) - () -) - -;movn direct bit -;BMOVN bitaddrZ.z,bitaddrQ.q -(dni bmovn "bit logical MOVN" - ((PIPE OS) (IDOC ALU)) - "bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit" - (+ OP1_3 OP2_10 reg8 reghi8 qhibit qlobit) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) - (set HI tmp1 reghi8) - (set HI tmp2 reg8) - (set tmp3 (const 1)) - (set tmp4 (const 1)) - ;; FIXME: (sll tmp3 qlobit) - ;; FIXME: (sll tmp4 qhibit) - ;; FIXME: (and tmp1 tmp3) - ;; FIXME: (and tmp2 tmp4) - ;; FIXME: (inv HI tmp2) - (set BI tmp1 tmp2) - (set HI reghi8 tmp1) - (set HI reg8 tmp2)) - () -) - -;and direct bit -;BAND bitaddrZ.z,bitaddrQ.q -(dni band "bit logical AND" - ((PIPE OS) (IDOC ALU)) - "band $reghi8$dot$qhibit,$reg8$dot$qlobit" - (+ OP1_6 OP2_10 reg8 reghi8 qhibit qlobit) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) - (set HI tmp1 reghi8) - (set HI tmp2 reg8) - (set tmp3 (const 1)) - (set tmp4 (const 1)) - ;; FIXME: (sll tmp3 qlobit) - ;; FIXME: (sll tmp4 qhibit) - ;; FIXME: (and tmp1 tmp3) - ;; FIXME: (and tmp2 tmp4) - (set BI tmp1(and tmp1 tmp2)) - (set HI reghi8 tmp1) - (set HI reg8 tmp2)) - () -) - -;or direct bit -;BOR bitaddrZ.z,bitaddrQ.q -(dni bor "bit logical OR" - ((PIPE OS) (IDOC ALU)) - "bor $reghi8$dot$qhibit,$reg8$dot$qlobit" - (+ OP1_5 OP2_10 reg8 reghi8 qhibit qlobit) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) - (set HI tmp1 reghi8) - (set HI tmp2 reg8) - (set tmp3 (const 1)) - (set tmp4 (const 1)) - ;; FIXME: (sll tmp3 qlobit) - ;; FIXME: (sll tmp4 qhibit) - ;; FIXME: (and tmp1 tmp3) - ;; FIXME: (and tmp2 tmp4) - (set BI tmp1(or tmp1 tmp2)) - (set HI reghi8 tmp1) - (set HI reg8 tmp2)) - () -) - -;xor direct bit -;BXOR bitaddrZ.z,bitaddrQ.q -(dni bxor "bit logical XOR" - ((PIPE OS) (IDOC ALU)) - "bxor $reghi8$dot$qhibit,$reg8$dot$qlobit" - (+ OP1_7 OP2_10 reg8 reghi8 qhibit qlobit) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) - (set HI tmp1 reghi8) - (set HI tmp2 reg8) - (set tmp3 (const 1)) - (set tmp4 (const 1)) - ;; FIXME: (sll tmp3 qlobit) - ;; FIXME: (sll tmp4 qhibit) - ;; FIXME: (and tmp1 tmp3) - ;; FIXME: (and tmp2 tmp4) - (set BI tmp1(xor tmp1 tmp2)) - (set HI reghi8 tmp1) - (set HI reg8 tmp2)) - () -) - -;cmp direct bit to bit -;BCMP bitaddrZ.z,bitaddrQ.q -(dni bcmp "bit to bit compare" - ((PIPE OS) (IDOC ALU)) - "bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit" - (+ OP1_2 OP2_10 reg8 reghi8 qhibit qlobit) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3) (HI tmp4)) - (set HI tmp1 reghi8) - (set HI tmp2 reg8) - (set tmp3 (const 1)) - (set tmp4 (const 1)) - ;; FIXME: (sll tmp3 qlobit) - ;; FIXME: (sll tmp4 qhibit) - ;; FIXME: (and tmp1 tmp3) - ;; FIXME: (and tmp2 tmp4) - (set BI tmp1(xor tmp1 tmp2)) - (set HI reghi8 tmp1) - (set HI reg8 tmp2)) - () -) - -;bit field low byte -;BFLDL op1,op2,op3 -(dni bfldl "bit field low byte" - ((PIPE OS) (IDOC MOVE)) - "bfldl $reg8,$hash$mask8,$hash$datahi8" - (+ OP1_0 OP2_10 reg8 mask8 datahi8) - (sequence ((HI tmp1) (QI tmp2) (QI tmp3)) - (set HI tmp1 reg8) - (set QI tmp2 mask8) - (set QI tmp3 datahi8) - ;; FIXME: (inv QI tmp2) - (set HI tmp1 (and tmp1 tmp2)) - (set HI tmp1 (or tmp1 tmp3)) - (set HI reg8 tmp1) - ) - () -) - -;bit field high byte -;BFLDH op1,op2,op3 -(dni bfldh "bit field high byte" - ((PIPE OS) (IDOC MOVE)) - "bfldh $reg8,$hash$masklo8,$hash$data8" - (+ OP1_1 OP2_10 reg8 masklo8 data8) - (sequence ((HI tmp1) (HI tmp2) (HI tmp3)) - (set HI tmp1 reg8) - (set QI tmp2 masklo8) - (set HI tmp3 data8) - ;; FIXME: (sll tmp2 (const 8)) - ;; FIXME: (inv HI tmp2) - ;; FIXME: (sll tmp3 (const 8)) - (set HI tmp1 (and tmp1 tmp2)) - (set HI tmp1 (or tmp1 tmp3)) - (set HI reg8 tmp1) - ) - () -) - -;/**********compare instructions****************** - -;Compare register -;CMP Rwn,Rwm -(dni cmpr "compare two registers" - ((PIPE OS) (IDOC CMP)) - "cmp $src1,$src2" - (+ OP1_4 OP2_0 src1 src2) - (set condbit (lt HI src1 src2)) - () -) - -;Compare byte register -;CMPB Rbn,Rbm -(dni cmpbr "compare two byte registers" - ((PIPE OS) (IDOC CMP)) - "cmpb $drb,$srb" - (+ OP1_4 OP2_1 drb srb) - (set condbit (lt QI drb srb)) - () -) - -(define-pmacro (cmp1 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op1 (f-op-bit1 0) op2) - (set condbit (lt mode op1 op2)) - () - ) -) -(cmp1 cmpri cmp OP1_4 OP2_8 src1 uimm3 HI) -(cmp1 cmpbri cmpb OP1_4 OP2_9 drb uimm3 QI) - -; CMP Rwn,#data16 -(dni cmpi "compare" - ((PIPE OS) (IDOC CMP)) - "cmp $reg8,$hash$uimm16" - (+ OP1_4 OP2_6 reg8 uimm16) - (set condbit (lt HI reg8 uimm16)) - () -) - -; CMPB reg,#data8 -(dni cmpbi "compare" - ((PIPE OS) (IDOC CMP)) - "cmpb $regb8,$hash$uimm8" - (+ OP1_4 OP2_7 regb8 uimm8 (f-op-bit8 0)) - (set condbit (lt QI regb8 uimm8)) - () -) - -;compare reg and indirect memory -(define-pmacro (cmp2 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",[$"op2"]") - (+ opc1 opc2 op1 (f-op-bit2 2) op2) - (set condbit (lt mode op1 op2)) - () - ) -) -(cmp2 cmpr2 cmp OP1_4 OP2_8 dr sr2 HI) -(cmp2 cmpbr2 cmpb OP1_4 OP2_9 drb sr2 QI) - -;compare register and indirect memory post increment -(define-pmacro (cmp3 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",[$"op2"+]") - (+ opc1 opc2 op1 (f-op-bit2 3) op2) - (sequence () - (set condbit (lt mode op1 op2)) - (set HI op2 (add HI op2 (const 2))) - ) - () - ) -) -(cmp3 cmp2i cmp OP1_4 OP2_8 dr sr2 HI) -(cmp3 cmpb2i cmpb OP1_4 OP2_9 drb sr2 QI) - -;compare register and direct memory -(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",$pof$"op2) - (+ opc1 opc2 op1 op2) - (set condbit (lt HI op1 (mem HI op2))) - () - ) -) -(cmp4 cmp04 cmp OP1_4 OP2_2 reg8 upof16 HI) -(cmp4 cmpb4 cmpb OP1_4 OP2_3 regb8 upof16 QI) - -;compare register and direct memory -(define-pmacro (cmp4 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set condbit (lt HI op1 (mem HI op2))) - () - ) -) -(cmp4 cmp004 cmp OP1_4 OP2_2 regmem8 memgr8 HI) -(cmp4 cmp0004 cmp OP1_4 OP2_2 reg8 memory HI) -(cmp4 cmpb04 cmpb OP1_4 OP2_3 regbmem8 memgr8 QI) -(cmp4 cmpb004 cmpb OP1_4 OP2_3 regb8 memory QI) - -;compare register and immediate -(define-pmacro (cmp5 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op2 op1) - (sequence () - (set condbit (lt HI op1 op2)) - (set mode op1 (sub HI op1 (const 1))) - ) - () - ) -) -(cmp5 cmpd1ri cmpd1 OP1_10 OP2_0 sr uimm4 HI) -(cmp5 cmpd2ri cmpd2 OP1_11 OP2_0 sr uimm4 HI) -(cmp5 cmpi1ri cmpi1 OP1_8 OP2_0 sr uimm4 HI) -(cmp5 cmpi2ri cmpi2 OP1_9 OP2_0 sr uimm4 HI) -(cmp5 cmpd1rim cmpd1 OP1_10 OP2_6 reg8 uimm16 HI) -(cmp5 cmpd2rim cmpd2 OP1_11 OP2_6 reg8 uimm16 HI) -(cmp5 cmpi1rim cmpi1 OP1_8 OP2_6 reg8 uimm16 HI) -(cmp5 cmpi2rim cmpi2 OP1_9 OP2_6 reg8 uimm16 HI) - -;compare register and direct memory -(define-pmacro (cmp6 name insn opc1 opc2 op1 op2 mode ) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",$pof$"op2) - (+ opc1 opc2 op1 op2) - (sequence () - (set condbit (lt HI op1 (mem HI op2))) - (set mode op1 (sub HI op1 (const 1))) - ) - () - ) -) -(cmp6 cmpd1rp cmpd1 OP1_10 OP2_2 reg8 upof16 HI ) -(cmp6 cmpd2rp cmpd2 OP1_11 OP2_2 reg8 upof16 HI ) -(cmp6 cmpi1rp cmpi1 OP1_8 OP2_2 reg8 upof16 HI ) -(cmp6 cmpi2rp cmpi2 OP1_9 OP2_2 reg8 upof16 HI ) - -;compare register and direct memory -(define-pmacro (cmp7 name insn opc1 opc2 op1 op2 mode) - (dni name - (.str name "compare" ) - ((PIPE OS) (IDOC CMP)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (sequence () - (set condbit (lt HI op1 (mem HI op2))) - (set mode op1 (sub HI op1 (const 1))) - ) - () - ) -) -(cmp7 cmpd1rm cmpd1 OP1_10 OP2_2 regmem8 memgr8 HI) -(cmp7 cmpd2rm cmpd2 OP1_11 OP2_2 regmem8 memgr8 HI) -(cmp7 cmpi1rm cmpi1 OP1_8 OP2_2 regmem8 memgr8 HI) -(cmp7 cmpi2rm cmpi2 OP1_9 OP2_2 regmem8 memgr8 HI) -(cmp7 cmpd1rmi cmpd1 OP1_10 OP2_2 reg8 memory HI) -(cmp7 cmpd2rmi cmpd2 OP1_11 OP2_2 reg8 memory HI) -(cmp7 cmpi1rmi cmpi1 OP1_8 OP2_2 reg8 memory HI) -(cmp7 cmpi2rmi cmpi2 OP1_9 OP2_2 reg8 memory HI) - - -;Shift and rotate insns -;**************************************************************** -(define-pmacro (shift name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "shift" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$"op2) - (+ opc1 opc2 op1 op2) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(shift shlr shl sll OP1_4 OP2_12 dr sr HI) -(shift shrr shr srl OP1_6 OP2_12 dr sr HI) -(shift rolr rol rol OP1_0 OP2_12 dr sr HI) -(shift rorr ror ror OP1_2 OP2_12 dr sr HI) -(shift ashrr ashr sra OP1_10 OP2_12 dr sr HI) - -(define-pmacro (shift1 name insn insn1 opc1 opc2 op1 op2 mode) - (dni name - (.str name "shift" ) - ((PIPE OS) (IDOC ALU)) - (.str insn " $"op1 ",$hash$"op2) - (+ opc1 opc2 op2 op1) - (set mode op1 (insn1 mode op1 op2)) - () - ) -) -(shift1 shlri shl sll OP1_5 OP2_12 sr uimm4 HI) -(shift1 shrri shr srl OP1_7 OP2_12 sr uimm4 HI) -(shift1 rolri rol rol OP1_1 OP2_12 sr uimm4 HI) -(shift1 rorri ror ror OP1_3 OP2_12 sr uimm4 HI) -(shift1 ashrri ashr sra OP1_11 OP2_12 sr uimm4 HI) diff --git a/binutils-2.24/cpu/xc16x.opc b/binutils-2.24/cpu/xc16x.opc deleted file mode 100644 index 47b7c690..00000000 --- a/binutils-2.24/cpu/xc16x.opc +++ /dev/null @@ -1,290 +0,0 @@ -/* XC16X opcode support. -*- C -*- - - Copyright 2006, 2007, 2009 Free Software Foundation, Inc. - - Contributed by KPIT Cummins Infosystems Ltd.; developed under contract - from Infineon Systems, GMBH , Germany. - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - - -/* This file is an addendum to xc16x.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h" */ - -/* -- opc.h */ - -#define CGEN_DIS_HASH_SIZE 8 -#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE) - -/* -- */ - -/* -- opc.c */ - -/* -- */ - -/* -- asm.c */ -/* Handle '#' prefixes (i.e. skip over them). */ - -static const char * -parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (**strp == '#') - { - ++*strp; - return NULL; - } - return _("Missing '#' prefix"); -} - -/* Handle '.' prefixes (i.e. skip over them). */ - -static const char * -parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (**strp == '.') - { - ++*strp; - return NULL; - } - return _("Missing '.' prefix"); -} - -/* Handle 'pof:' prefixes (i.e. skip over them). */ - -static const char * -parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (strncasecmp (*strp, "pof:", 4) == 0) - { - *strp += 4; - return NULL; - } - return _("Missing 'pof:' prefix"); -} - -/* Handle 'pag:' prefixes (i.e. skip over them). */ - -static const char * -parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (strncasecmp (*strp, "pag:", 4) == 0) - { - *strp += 4; - return NULL; - } - return _("Missing 'pag:' prefix"); -} - -/* Handle 'sof' prefixes (i.e. skip over them). */ - -static const char * -parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (strncasecmp (*strp, "sof:", 4) == 0) - { - *strp += 4; - return NULL; - } - return _("Missing 'sof:' prefix"); -} - -/* Handle 'seg' prefixes (i.e. skip over them). */ - -static const char * -parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - const char **strp, - int opindex ATTRIBUTE_UNUSED, - long *valuep ATTRIBUTE_UNUSED) -{ - if (strncasecmp (*strp, "seg:", 4) == 0) - { - *strp += 4; - return NULL; - } - return _("Missing 'seg:' prefix"); -} -/* -- */ - -/* -- dis.c */ - -/* Print an operand with a "." prefix. - NOTE: This prints the operand in hex. - ??? This exists to maintain disassembler compatibility with previous - versions. Ideally we'd print the "." in print_dot. */ - -static void -print_with_dot_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "."); - info->fprintf_func (info->stream, "0x%lx", value); -} - -/* Print an operand with a "#pof:" prefix. - NOTE: This prints the operand as an address. - ??? This exists to maintain disassembler compatibility with previous - versions. Ideally we'd print "#pof:" in print_pof. */ - -static void -print_with_pof_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - bfd_vma value, - unsigned attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "#pof:"); - info->fprintf_func (info->stream, "0x%lx", (long) value); -} - -/* Print an operand with a "#pag:" prefix. - NOTE: This prints the operand in hex. - ??? This exists to maintain disassembler compatibility with previous - versions. Ideally we'd print "#pag:" in print_pag. */ - -static void -print_with_pag_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value, - unsigned attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "#pag:"); - info->fprintf_func (info->stream, "0x%lx", value); -} - -/* Print a 'pof:' prefix to an operand. */ - -static void -print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ -} - -/* Print a 'pag:' prefix to an operand. */ - -static void -print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ -} - -/* Print a 'sof:' prefix to an operand. */ - -static void -print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "sof:"); -} - -/* Print a 'seg:' prefix to an operand. */ - -static void -print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "seg:"); -} - -/* Print a '#' prefix to an operand. */ - -static void -print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ - disassemble_info *info = (disassemble_info *) dis_info; - - info->fprintf_func (info->stream, "#"); -} - -/* Print a '.' prefix to an operand. */ - -static void -print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, - void * dis_info ATTRIBUTE_UNUSED, - long value ATTRIBUTE_UNUSED, - unsigned int attrs ATTRIBUTE_UNUSED, - bfd_vma pc ATTRIBUTE_UNUSED, - int length ATTRIBUTE_UNUSED) -{ -} - -/* -- */ diff --git a/binutils-2.24/cpu/xstormy16.cpu b/binutils-2.24/cpu/xstormy16.cpu deleted file mode 100644 index ae7e042c..00000000 --- a/binutils-2.24/cpu/xstormy16.cpu +++ /dev/null @@ -1,1965 +0,0 @@ -; xstormy16 CPU core description. -*- Scheme -*- -; Copyright 2011 Free Software Foundation, Inc. -; -; Contributed by Red Hat Inc; -; -; This file is part of the GNU Binutils. -; -; This program is free software; you can redistribute it and/or modify -; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 3 of the License, or -; (at your option) any later version. -; -; This program is distributed in the hope that it will be useful, -; but WITHOUT ANY WARRANTY; without even the implied warranty of -; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; GNU General Public License for more details. -; -; You should have received a copy of the GNU General Public License -; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -; MA 02110-1301, USA. - -(define-rtl-version 0 8) - -(include "simplify.inc") - -(define-arch - (name xstormy16) - (comment "Xstormy16 architecture") - (insn-lsb0? #f) - (machs xstormy16) - (isas xstormy16) -) - -(define-isa - (name xstormy16) - (comment "Xstormy16 instruction set") - (default-insn-word-bitsize 32) - (default-insn-bitsize 32) - ; FIXME base-insn-bitsize should be 16 too, but at present CGEN has - ; no support for instruction sets with opcode bits past - ; base-insn-bitsize, so we must set it to at least 20. - (base-insn-bitsize 32) -) - -(define-cpu - (name xstormy16) - (comment "Xstormy16 CPU core") - (endian little) - (insn-endian little) - (insn-chunk-bitsize 16) - (word-bitsize 32) -) - -(define-mach - (name xstormy16) - (comment "Xstormy16 CPU core") - (cpu xstormy16) - (isas xstormy16) -) - -(define-model - (name xstormy16) - (comment "Xstormy16 CPU core") - (unit u-exec "Execution Unit" () - 1 1 ; issue done - () () () ()) -) - -; IDOC attribute for instruction documentation. - -(define-attr - (for insn) - (type enum) - (name IDOC) - (comment "insn kind for documentation") - (attrs META) - (values - (MEM - () "Memory") - (ALU - () "ALU") - (FPU - () "FPU") - (BR - () "Branch") - (PRIV - () "Priviledged") - (MISC - () "Miscellaneous") - ) -) - -; Hardware elements. - -(define-hardware - (name h-pc) - (comment "program counter") - (attrs PC) - (type pc) - (set (newval) (c-call "h_pc_set_handler" newval)) -) - -(define-keyword - (name gr-names) - (enum-prefix H-GR-) - (values (r0 0) (r1 1) (r2 2) (r3 3) - (r4 4) (r5 5) (r6 6) (r7 7) - (r8 8) (r9 9) (r10 10) (r11 11) - (r12 12) (r13 13) (r14 14) (r15 15) - (psw 14) (sp 15))) - -(define-keyword - (name gr-Rb-names) - (enum-prefix H-RBJ-) - (values (r8 0) (r9 1) (r10 2) (r11 3) - (r12 4) (r13 5) (r14 6) (r15 7) - (psw 6) (sp 7))) - -(define-hardware - (name h-gr) - (comment "registers") - (type register WI (16)) - (indices extern-keyword gr-names) - (get (index) (and #xFFFF (raw-reg h-gr index))) - (set (index newval) (c-call "h_gr_set_handler" index newval)) -) - -(define-hardware - (name h-Rb) - (comment "Rb registers") - (attrs VIRTUAL) - (type register SI(8)) - (indices extern-keyword gr-Rb-names) - (get (index) (reg h-gr (add index 8))) - (set (index newval) (set (reg h-gr (add index 8)) newval)) -) - -(define-hardware - (name h-Rbj) - (comment "Rbj registers") - (attrs VIRTUAL) - (type register SI(2)) - (indices extern-keyword gr-Rb-names) - (get (index) (reg h-gr (add index 8))) - (set (index newval) (set (reg h-gr (add index 8)) newval)) -) - -(define-hardware - (name h-Rpsw) - (comment "Register number field of the PSW") - (attrs VIRTUAL) - (type register WI) - (get () (and #xF (srl psw 12))) - (set (newval) (set psw (or (and psw #xFFF) - (sll HI newval 12))))) - -(define-pmacro (define-psw-field fnam hnam index) - (define-hardware - (name hnam) - (attrs VIRTUAL) - (type register SI) - (get () (and 1 (srl psw index))) - (set (newval) (set psw (or (and psw (inv (sll HI 1 index))) - (sll HI newval index))))) - ;(dnop fnam "" (SEM-ONLY) hnam f-nil) -) -(define-psw-field psw-z8 h-z8 0) -(dnop psw-z8 "" (SEM-ONLY) h-z8 f-nil) -(define-psw-field psw-z16 h-z16 1) -(dnop psw-z16 "" (SEM-ONLY) h-z16 f-nil) -(define-psw-field psw-cy h-cy 2) -(dnop psw-cy "" (SEM-ONLY) h-cy f-nil) -(define-psw-field psw-hc h-hc 3) -(dnop psw-hc "" (SEM-ONLY) h-hc f-nil) -(define-psw-field psw-ov h-ov 4) -(dnop psw-ov "" (SEM-ONLY) h-ov f-nil) -(define-psw-field psw-pt h-pt 5) -(dnop psw-pt "" (SEM-ONLY) h-pt f-nil) -(define-psw-field psw-s h-s 6) -(dnop psw-s "" (SEM-ONLY) h-s f-nil) - -(define-hardware - (name h-branchcond) - (comment "Condition of a branch instruction") - (type immediate (UINT 4)) - (values keyword "" - (("ge" 0) ("nc" 1) ("lt" 2) ("c" 3) - ("gt" 4) ("hi" 5) ("le" 6) ("ls" 7) - ("pl" 8) ("nv" 9) ("mi" 10) ("v" 11) - ("nz.b" 12) ("nz" 13) ("z.b" 14) ("z" 15))) -) - -(define-hardware - (name h-wordsize) - (comment "Data size") - (type immediate (UINT 1)) - (values keyword "" ((".b" 0) (".w" 1) ("" 1))) -) - - -; Instruction fields, and the corresponding operands. -; Register fields - -(dnf f-Rd "general register destination" () 12 4) -(dnop Rd "general register destination" () h-gr f-Rd) - -(dnf f-Rdm "general register destination" () 13 3) -(dnop Rdm "general register destination" () h-gr f-Rdm) - -(dnf f-Rm "general register for memory" () 4 3) -(dnop Rm "general register for memory" () h-gr f-Rm) - -(dnf f-Rs "general register source" () 8 4) -(dnop Rs "general register source" () h-gr f-Rs) - -(dnf f-Rb "base register" () 17 3) -(dnop Rb "base register" () h-Rb f-Rb) - -(dnf f-Rbj "base register for jump" () 11 1) -(dnop Rbj "base register for jump" () h-Rbj f-Rbj) - -; Main opcodes in 4 bit chunks - -(dnf f-op1 "opcode" () 0 4) -(define-normal-insn-enum insn-op1 "insn op enums" () OP1_ f-op1 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) - -(dnf f-op2 "opcode" () 4 4) -(define-normal-insn-enum insn-op2 "insn op enums" () OP2_ f-op2 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) -(dnop bcond2 "branch condition opcode" () h-branchcond f-op2) - -(dnf f-op2a "opcode" () 4 3) -(define-normal-insn-enum insn-op2a "insn op enums" () OP2A_ f-op2a - ( "0" "2" "4" "6" "8" "A" "C" "E" )) - -(dnf f-op2m "opcode" () 7 1) -(define-normal-insn-enum insn-op2m "insn op enums" () OP2M_ f-op2m - ( "0" "1" )) -(dnop ws2 "word size opcode" () h-wordsize f-op2m) - -(dnf f-op3 "opcode" () 8 4) -(define-normal-insn-enum insn-op3 "insn op enums" () OP3_ f-op3 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) - -(dnf f-op3a "opcode" () 8 2) -(define-normal-insn-enum insn-op3a "insn op enums" () OP3A_ f-op3a - ( "0" "1" "2" "3" )) - -(dnf f-op3b "opcode" () 8 3) -(define-normal-insn-enum insn-op3b "insn op enums" () OP3B_ f-op3b - ( "0" "2" "4" "6" "8" "A" "C" "E" )) - -(dnf f-op4 "opcode" () 12 4) -(define-normal-insn-enum insn-op4 "insn op enums" () OP4_ f-op4 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) - -(dnf f-op4m "opcode" () 12 1) -(define-normal-insn-enum insn-op4m "insn op enums" () OP4M_ f-op4m - ( "0" "1" )) - -(dnf f-op4b "opcode" () 15 1) -(define-normal-insn-enum insn-op4b "insn op enums" () OP4B_ f-op4b - ( "0" "1" )) - -(dnf f-op5 "opcode" () 16 4) -(define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5 - ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" )) -(dnop bcond5 "branch condition opcode" () h-branchcond f-op5) - -(dnf f-op5a "opcode" () 16 1) -(define-normal-insn-enum insn-op5a "insn op enums" () OP5A_ f-op5a - ( "0" "1" )) - -; The whole first word -(dnf f-op "opcode" () 0 16) - -; Immediate fields - -(dnf f-imm2 "2 bit unsigned" () 10 2) -(dnop imm2 "2 bit unsigned immediate" () h-uint f-imm2) - -(dnf f-imm3 "3 bit unsigned" () 4 3) -(dnop imm3 "3 bit unsigned immediate" () h-uint f-imm3) -(dnf f-imm3b "3 bit unsigned for bit tests" () 17 3) -(dnop imm3b "3 bit unsigned immediate for bit tests" () h-uint f-imm3b) - -(dnf f-imm4 "4 bit unsigned" () 8 4) -(define-operand - (name imm4) - (comment "4 bit unsigned immediate") - (attrs) - (type h-uint) - (index f-imm4) - (handlers (parse "small_immediate")) -) - -(dnf f-imm8 "8 bit unsigned" () 8 8) -(dnop imm8 "8 bit unsigned immediate" () h-uint f-imm8) -(define-operand - (name imm8small) - (comment "8 bit unsigned immediate") - (attrs) - (type h-uint) - (index f-imm8) - (handlers (parse "small_immediate")) -) - -(define-ifield - (name f-imm12) - (comment "12 bit signed") - (attrs) - (start 20) - (length 12) - (mode INT) -) -(dnop imm12 "12 bit signed immediate" () h-sint f-imm12) - -(dnf f-imm16 "16 bit" (SIGN-OPT) 16 16) -(define-operand - (name imm16) - (comment "16 bit immediate") - (attrs) - (type h-uint) - (index f-imm16) - (handlers (parse "immediate16")) -) - -(dnf f-lmem8 "8 bit unsigned low memory" (ABS-ADDR) 8 8) -(define-operand - (name lmem8) - (comment "8 bit unsigned immediate low memory") - (attrs) - (type h-uint) - (index f-lmem8) - (handlers (parse "mem8")) -) -(define-ifield - (name f-hmem8) - (comment "8 bit unsigned high memory") - (attrs ABS-ADDR) - (start 8) - (length 8) - (mode UINT) - (encode (value pc) (sub HI value #x7F00)) - (decode (value pc) (add HI value #x7F00)) -) -(define-operand - (name hmem8) - (comment "8 bit unsigned immediate high memory") - (attrs) - (type h-uint) - (index f-hmem8) - (handlers (parse "mem8")) -) - -(define-ifield - (name f-rel8-2) - (comment "8 bit relative address for 2-byte instruction") - (attrs PCREL-ADDR) - (start 8) - (length 8) - (mode INT) - (encode (value pc) (sub SI value (add SI pc 2))) - (decode (value pc) (add SI value (add SI pc 2))) -) -(dnop rel8-2 "8 bit relative address" () h-uint f-rel8-2) - -(define-ifield - (name f-rel8-4) - (comment "8 bit relative address for 4-byte instruction") - (attrs PCREL-ADDR) - (start 8) - (length 8) - (mode INT) - (encode (value pc) (sub SI value (add SI pc 4))) - (decode (value pc) (add SI value (add SI pc 4))) -) -(dnop rel8-4 "8 bit relative address" () h-uint f-rel8-4) - -(define-ifield - (name f-rel12) - (comment "12 bit relative address") - (attrs PCREL-ADDR) - (start 20) - (length 12) - (mode INT) - (encode (value pc) (sub SI value (add SI pc 4))) - (decode (value pc) (add SI value (add SI pc 4))) -) -(dnop rel12 "12 bit relative address" () h-uint f-rel12) - -(define-ifield - (name f-rel12a) - (comment "12 bit relative address") - (attrs PCREL-ADDR) - (start 4) - (length 11) - (mode INT) - (encode (value pc) (sra SI (sub SI value (add SI pc 2)) 1)) - (decode (value pc) (add SI (sll value 1) (add SI pc 2))) -) -(dnop rel12a "12 bit relative address" () h-uint f-rel12a) - -(dnf f-abs24-1 "abs24 low part" () 8 8) -(dnf f-abs24-2 "abs24 high part" () 16 16) -(define-multi-ifield - (name f-abs24) - (comment "Absolute address for jmpf instruction") - (attrs ABS-ADDR) - (mode UINT) - (subfields f-abs24-1 f-abs24-2) - (insert (sequence () - (set (ifield f-abs24-1) (and (ifield f-abs24) #xFF)) - (set (ifield f-abs24-2) (srl (ifield f-abs24) 8)))) - (extract (set (ifield f-abs24) (or (sll (ifield f-abs24-2) 8) f-abs24-1))) -) -(dnop abs24 "24 bit absolute address" () h-uint f-abs24) - -; Names for registers -(dnop psw "program status word" (SEM-ONLY) h-gr 14) -(dnop Rpsw "N0-N3 of the program status word" (SEM-ONLY) h-Rpsw f-nil) -(dnop sp "stack pointer" (SEM-ONLY) h-gr 15) -(dnop R0 "R0" (SEM-ONLY) h-gr 0) -(dnop R1 "R1" (SEM-ONLY) h-gr 1) -(dnop R2 "R2" (SEM-ONLY) h-gr 2) -(dnop R8 "R8" (SEM-ONLY) h-gr 8) - -; Useful macros. - -; THe Z8, Z16, PT, and S flags of the PSW. -(define-pmacro (basic-psw value ws) - (or (or (zflag (and value #xFF)) - (sll HI (zflag HI value) 1)) - (or (sll HI (c-call BI "parity" value) 5) - (sll HI (nflag QI (srl value (mul ws 8))) 6)))) - - -; Update the PSW for destination register Rd, set Rd to value. -(define-pmacro (set-psw Rd index value ws) - (sequence ((HI nvalue)) - (set nvalue value) - (set (reg HI h-gr index) nvalue) - (set psw (or (and psw #x0F9C) - (or (sll index 12) - (basic-psw nvalue ws)))))) - -; Update the PSW for destination register Rd. -(define-pmacro (set-psw-nowrite index value ws) - (sequence ((HI nvalue)) - (set nvalue value) - (set psw (or (and psw #x0F9C) - (or (sll index 12) - (basic-psw nvalue ws)))))) - -; Update the PSW for destination non-register dest, set dest to value. -(define-pmacro (set-mem-psw dest value ws) - (sequence ((HI nvalue)) - (set nvalue value) - (set psw (or (and psw #xFF9C) - (basic-psw nvalue ws))) - (set dest nvalue))) - -; Update the PSW as with set-psw, but also set the carry flag. -(define-pmacro (set-psw-carry Rd index value carry ws) - (sequence ((HI nvalue) (HI newpsw)) - (set nvalue value) - (set newpsw (or (or (and psw #x0F98) - (sll (and carry #x1) 2)) - (or (sll index 12) - (basic-psw nvalue ws)))) - (set (reg HI h-gr index) nvalue) - (set psw newpsw) - )) - -; The all-purpose addition operation. -(define-pmacro (set-psw-add Rd index a b c) - (sequence ((HI value) (HI newpsw)) - (set value (addc a b c)) - (set newpsw (or (or (and psw #x0F80) - (basic-psw value 1)) - (or (or (sll HI (add-oflag HI a b c) 4) - (sll HI (add-cflag HI a b c) 2)) - (or (and (srl HI (addc HI (and a #xF) (and b #xF) c) - 1) #x8) - (sll index 12))))) - (set (reg HI h-gr index) value) - (set psw newpsw) - )) - -; Set the PSW for a subtraction of a-b into Rd, but don't actually -; do the subtract. -(define-pmacro (set-psw-cmp Rd index a b) - (sequence ((HI value)) - (set value (sub a b)) - (set psw (or (or (and psw #x0F80) - (basic-psw value 1)) - (or (or (sll HI (sub-oflag HI a b 0) 4) - (sll HI (sub-cflag HI a b 0) 2)) - (or (and (srl HI (sub HI (and a #xF) (and b #xF)) - 1) #x8) - (sll index 12))))))) - -; Likewise, for subtraction -; (this chip has a borrow for subtraction, rather than -; just using a carry for both). -(define-pmacro (set-psw-sub Rd index a b c) - (sequence ((HI value) (HI newpsw)) - (set value (subc a b c)) - (set newpsw (or (or (and psw #x0F80) - (basic-psw value 1)) - (or (or (sll HI (sub-oflag HI a b c) 4) - (sll HI (sub-cflag HI a b c) 2)) - (or (and (srl HI (subc HI (and a #xF) (and b #xF) c) - 1) #x8) - (sll index 12))))) - (set (reg HI h-gr index) value) - (set psw newpsw) - )) - -; A 17-bit rotate-left operation -(define-pmacro (set-psw-rotate17 Rd index src c rot) - (sequence ((SI tmpfoo)) - (set tmpfoo (or (or (and (sll SI src 15) #x7FFE0000) - src) - (or (sll SI c 31) - (sll SI c 16)))) - (set tmpfoo (rol tmpfoo (and rot #x1F))) - (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1))) - -; A 17-bit rotate-right operation -(define-pmacro (set-psw-rrotate17 Rd index src c rot) - (sequence ((SI tmpfoo)) - (set tmpfoo (or (or (and (sll SI src 17) #xFFFE0000) - src) - (sll SI c 16))) - (set tmpfoo (ror tmpfoo (and rot #x0F))) - (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1))) - - -; Move Operations - -(define-pmacro (alignfix-mem where) - (mem HI (and where #xFFFE))) - -(define-pmacro (set-alignfix-mem where what) - (set (mem HI (and where #xFFFE)) what)) - -(define-pmacro (alignfix-mem-far where) - (mem HI (and where #xFFFFFFFE))) - -(define-pmacro (set-alignfix-mem-far where what) - (set (mem HI (and where #xFFFFFFFE)) what)) - -(dni movlmemimm - "Move immediate to low memory" - () - ("mov$ws2 $lmem8,#$imm16") - (+ OP1_7 OP2A_8 ws2 lmem8 imm16) - (if ws2 - (set-mem-psw (mem HI (and lmem8 #xFFFE)) imm16 ws2) - (set-mem-psw (mem QI lmem8) (and imm16 #xFF) ws2)) - () -) -(dni movhmemimm - "Move immediate to high memory" - () - ("mov$ws2 $hmem8,#$imm16") - (+ OP1_7 OP2A_A ws2 hmem8 imm16) - (if ws2 - (set-mem-psw (mem HI (and hmem8 #xFFFE)) imm16 ws2) - (set-mem-psw (mem QI hmem8) (and imm16 #xFF) ws2)) - () -) - -(dni movlgrmem - "Move low memory to register" - () - ("mov$ws2 $Rm,$lmem8") - (+ OP1_8 Rm ws2 lmem8) - (if ws2 - (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2) - (set-psw Rm (index-of Rm) (mem QI lmem8) ws2)) - () -) -(dni movhgrmem - "Move high memory to register" - () - ("mov$ws2 $Rm,$hmem8") - (+ OP1_A Rm ws2 hmem8) - (if ws2 - (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2) - (set-psw Rm (index-of Rm) (mem QI hmem8) ws2)) - () -) - -(dni movlmemgr - "Move low memory register to byte" - () - ("mov$ws2 $lmem8,$Rm") - (+ OP1_9 Rm ws2 lmem8) - (if ws2 - (set-mem-psw (mem HI (and lmem8 #xFFFE)) Rm ws2) - (set-mem-psw (mem QI lmem8) Rm ws2)) - () -) -(dni movhmemgr - "Move high memory register to byte" - () - ("mov$ws2 $hmem8,$Rm") - (+ OP1_B Rm ws2 hmem8) - (if ws2 - (set-mem-psw (mem HI (and hmem8 #xFFFE)) Rm ws2) - (set-mem-psw (mem QI hmem8) Rm ws2)) - () -) - -(dni movgrgri - "Move memory addressed by register to register" - () - ("mov$ws2 $Rdm,($Rs)") - (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2)) - () -) - -(dni movgrgripostinc - "Move memory addressed by postincrement register to register" - () - ("mov$ws2 $Rdm,($Rs++)") - (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2)) - (set Rs (add Rs (add 1 ws2)))) - () -) - -(dni movgrgripredec - "Move memory addressed by predecrement register to register" - () - ("mov$ws2 $Rdm,(--$Rs)") - (+ OP1_6 OP2A_8 ws2 Rs OP4M_0 Rdm) - (sequence () - (set Rs (sub Rs (add 1 ws2))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))) - () -) - -(dni movgrigr - "Move register to memory addressed by register" - () - ("mov$ws2 ($Rs),$Rdm") - (+ OP1_7 OP2A_2 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem Rs Rdm) - (set (mem QI Rs) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - -(dni movgripostincgr - "Move register to memory addressed by postincrement register" - () - ("mov$ws2 ($Rs++),$Rdm") - (+ OP1_6 OP2A_2 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem Rs Rdm) - (set (mem QI Rs) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movgripredecgr - "Move register to memory addressed by predecrement register" - () - ("mov$ws2 (--$Rs),$Rdm") - (+ OP1_6 OP2A_A ws2 Rs OP4M_0 Rdm) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (if ws2 - (set-alignfix-mem Rs Rdm) - (set (mem QI Rs) Rdm))) - () -) - -(dni movgrgrii - "Move memory addressed by indexed register to register" - () - ("mov$ws2 $Rdm,($Rs,$imm12)") - (+ OP1_7 OP2A_0 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2)) - () -) - -(dni movgrgriipostinc - "Move memory addressed by indexed register postincrement to register" - () - ("mov$ws2 $Rdm,($Rs++,$imm12)") - (+ OP1_6 OP2A_0 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2)) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movgrgriipredec - "Move memory addressed by indexed register predecrement to register" - () - ("mov$ws2 $Rdm,(--$Rs,$imm12)") - (+ OP1_6 OP2A_8 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2))) - () -) - -(dni movgriigr - "Move register to memory addressed by indexed register" - () - ("mov$ws2 ($Rs,$imm12),$Rdm") - (+ OP1_7 OP2A_2 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (if ws2 - (set-alignfix-mem (add Rs imm12) Rdm) - (set (mem QI (add Rs imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - -(dni movgriipostincgr - "Move register to memory addressed by indexed register postincrement" - () - ("mov$ws2 ($Rs++,$imm12),$Rdm") - (+ OP1_6 OP2A_2 ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (if ws2 - (set-alignfix-mem (add Rs imm12) Rdm) - (set (mem QI (add Rs imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movgriipredecgr - "Move register to memory addressed by indexed register predecrement" - () - ("mov$ws2 (--$Rs,$imm12),$Rdm") - (+ OP1_6 OP2A_A ws2 Rs OP4M_1 Rdm OP5_0 imm12) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (if ws2 - (set-alignfix-mem (add Rs imm12) Rdm) - (set (mem QI (add Rs imm12)) Rdm))) - () -) - -(dni movgrgr - "Move general register to general register" - () - ("mov $Rd,$Rs") - (+ OP1_4 OP2_6 Rs Rd) - (set-psw Rd (index-of Rd) Rs 1) - () -) - -(dnmi movimm8 - "Move 8-bit immediate" - () - ("mov Rx,#$imm8") - (emit movwimm8 imm8) -) - -(dni movwimm8 - "Move 8-bit immediate" - () - ("mov.w Rx,#$imm8") - (+ OP1_4 OP2_7 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw imm8 1) - () -) - -(dnmi movgrimm8 - "Move 8-bit immediate to general register" - () - ("mov $Rm,#$imm8small") - (emit movwgrimm8 Rm imm8small) -) - -(dni movwgrimm8 - "Move 8-bit immediate to general register" - () - ("mov.w $Rm,#$imm8small") - (+ OP1_2 Rm OP2M_1 imm8small) - (set-psw Rm (index-of Rm) imm8small 1) - () -) - -(dnmi movgrimm16 - "Move 16-bit immediate to general register" - () - ("mov $Rd,#$imm16") - (emit movwgrimm16 Rd imm16) -) - -(dni movwgrimm16 - "Move 16-bit immediate to general register" - () - ("mov.w $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_3 Rd imm16) - (set-psw Rd (index-of Rd) imm16 1) - () -) - -(dni movlowgr - "Move 8 low bits to general register" - () - ("mov.b $Rd,RxL") - (+ OP1_3 OP2_0 OP3_C Rd) - (set-psw Rd (index-of Rd) (or (and Rd #xFF00) (and (reg HI h-gr Rpsw) #xFF)) 0) - () -) - -(dni movhighgr - "Move 8 high bits to general register" - () - ("mov.b $Rd,RxH") - (+ OP1_3 OP2_0 OP3_D Rd) - (set-psw Rd (index-of Rd) (or (and Rd #x00FF) (and (reg HI h-gr Rpsw) #xFF00)) 1) - () -) - -(dni movfgrgri - "Move far memory addressed by register to register" - () - ("movf$ws2 $Rdm,($Rs)") - (+ OP1_7 OP2A_4 ws2 Rs OP4M_0 Rdm) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (or (sll SI R8 16) Rs)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (or (sll SI R8 16) Rs))) ws2)) - () -) - -(dni movfgrgripostinc - "Move far memory addressed by postincrement register to register" - () - ("movf$ws2 $Rdm,($Rs++)") - (+ OP1_6 OP2A_4 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (join SI HI R8 Rs)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (join SI HI R8 Rs))) ws2)) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movfgrgripredec - "Move far memory addressed by predecrement register to register" - () - ("movf$ws2 $Rdm,(--$Rs)") - (+ OP1_6 OP2A_C ws2 Rs OP4M_0 Rdm) - (sequence () - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (join SI HI R8 Rs)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (join SI HI R8 Rs))) ws2))) - () -) - -(dni movfgrigr - "Move far register to memory addressed by register" - () - ("movf$ws2 ($Rs),$Rdm") - (+ OP1_7 OP2A_6 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem-far (join SI HI R8 Rs) Rdm) - (set (mem QI (join SI HI R8 Rs)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - -(dni movfgripostincgr - "Move far register to memory addressed by postincrement register" - () - ("movf$ws2 ($Rs++),$Rdm") - (+ OP1_6 OP2A_6 ws2 Rs OP4M_0 Rdm) - (sequence () - (if ws2 - (set-alignfix-mem-far (join SI HI R8 Rs) Rdm) - (set (mem QI (join SI HI R8 Rs)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1)))) - () -) - -(dni movfgripredecgr - "Move far register to memory addressed by predecrement register" - () - ("movf$ws2 (--$Rs),$Rdm") - (+ OP1_6 OP2A_E ws2 Rs OP4M_0 Rdm) - (sequence () - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-alignfix-mem-far (join SI HI R8 Rs) Rdm) - (set (mem QI (join SI HI R8 Rs)) Rdm))) - () -) - -(dni movfgrgrii - "Move far memory addressed by indexed register to register" - () - ("movf$ws2 $Rdm,($Rb,$Rs,$imm12)") - (+ OP1_7 OP2A_4 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2)) - () -) - -(dni movfgrgriipostinc - "Move far memory addressed by indexed register postincrement to register" - () - ("movf$ws2 $Rdm,($Rb,$Rs++,$imm12)") - (+ OP1_6 OP2A_4 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2)) - (set Rs (add Rs (add ws2 1))) - ; Note - despite the XStormy16 ISA documentation the - ; addition *is* propogated into the base register. - (if (eq Rs 0) (set Rb (add Rb 1))) - ) - () -) - -(dni movfgrgriipredec - "Move far memory addressed by indexed register predecrement to register" - () - ("movf$ws2 $Rdm,($Rb,--$Rs,$imm12)") - (+ OP1_6 OP2A_C ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - ; Note - despite the XStormy16 ISA documentation the - ; subtraction *is* propogated into the base register. - (if (eq Rs 0) (set Rb (sub Rb 1))) - (set Rs (sub Rs (add ws2 1))) - (if ws2 - (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2) - (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2))) - () -) - -(dni movfgriigr - "Move far register to memory addressed by indexed register" - () - ("movf$ws2 ($Rb,$Rs,$imm12),$Rdm") - (+ OP1_7 OP2A_6 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - (if ws2 - (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) - Rdm) - (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2)) - () -) - - -(dni movfgriipostincgr - "Move far register to memory addressed by indexed register postincrement" - () - ("movf$ws2 ($Rb,$Rs++,$imm12),$Rdm") - (+ OP1_6 OP2A_6 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - (if ws2 - (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) Rdm) - (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (set Rs (add Rs (add ws2 1))) - ; Note - despite the XStormy16 ISA documentation the - ; addition *is* propogated into the base register. - (if (eq Rs 0) (set Rb (add Rb 1))) - ) - () -) - -(dni movfgriipredecgr - "Move far register to memory addressed by indexed register predecrement" - () - ("movf$ws2 ($Rb,--$Rs,$imm12),$Rdm") - (+ OP1_6 OP2A_E ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) - (sequence () - ; Note - despite the XStormy16 ISA documentation the - ; subtraction *is* propogated into the base register. - (if (eq Rs 0) (set Rb (sub Rb 1))) - (set Rs (sub Rs (add ws2 1))) - (set-psw-nowrite (index-of Rdm) Rdm ws2) - (if ws2 - (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) Rdm) - (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm))) - () -) - -(dni maskgrgr - "Mask insert controlled by general register" - () - ("mask $Rd,$Rs") - (+ OP1_3 OP2_3 Rs Rd) - (set-psw Rd (index-of Rd) (or HI (and HI Rd (inv HI Rs)) (and (reg HI h-gr Rpsw) Rs)) 1) - () -) - -(dni maskgrimm16 - "Mask insert controlled by immediate value" - () - ("mask $Rd,#$imm16") - (+ OP1_3 OP2_0 OP3_E Rd imm16) - (set-psw Rd (index-of Rd) (or (and Rd (inv imm16)) (and (reg HI h-gr Rpsw) imm16)) 1) - () -) - -; Push, Pop -(dni pushgr - "Push register" - () - ("push $Rd") - (+ OP1_0 OP2_0 OP3_8 Rd) - (sequence () - (set (mem HI sp) Rd) - (set sp (add sp 2))) - () -) - -(dni popgr - "Pop into a register" - () - ("pop $Rd") - (+ OP1_0 OP2_0 OP3_9 Rd) - (sequence () - (set sp (add sp -2)) - (set Rd (mem HI sp))) - () -) - -; Swap -(dni swpn - "Swap low nibbles" - () - ("swpn $Rd") - (+ OP1_3 OP2_0 OP3_9 Rd) - (set-psw Rd (index-of Rd) (or (or (and (sll Rd 4) #xF0) - (and (srl Rd 4) #x0F)) - (and Rd #xFF00)) 0) - () -) - -(dni swpb - "Swap bytes" - () - ("swpb $Rd") - (+ OP1_3 OP2_0 OP3_8 Rd) - (set-psw Rd (index-of Rd) (or (sll Rd 8) (srl Rd 8)) 1) - () -) - -(dni swpw - "Swap words" - () - ("swpw $Rd,$Rs") - (+ OP1_3 OP2_2 Rs Rd) - (sequence ((HI foo)) - (set foo Rs) - (set Rs Rd) - (set-psw Rd (index-of Rd) foo 1)) - () -) - -; Logical Operations -(dni andgrgr - "AND general register with general register" - () - ("and $Rd,$Rs") - (+ OP1_4 OP2_0 Rs Rd) - (set-psw Rd (index-of Rd) (and Rd Rs) 1) - () -) - -(dni andimm8 - "AND with 8-bit immediate" - () - ("and Rx,#$imm8") - (+ OP1_4 OP2_1 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw (and (reg HI h-gr Rpsw) imm8) 1) - () -) - -(dni andgrimm16 - "AND general register with 16-bit immediate" - () - ("and $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_0 Rd imm16) - (set-psw Rd (index-of Rd) (and Rd imm16) 1) - () -) - -(dni orgrgr - "OR general register with general register" - () - ("or $Rd,$Rs") - (+ OP1_4 OP2_2 Rs Rd) - (set-psw Rd (index-of Rd) (or Rd Rs) 1) - () -) - -(dni orimm8 - "OR with 8-bit immediate" - () - ("or Rx,#$imm8") - (+ OP1_4 OP2_3 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw (or (reg HI h-gr Rpsw) imm8) 1) - () -) - -(dni orgrimm16 - "OR general register with 16-bit immediate" - () - ("or $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_1 Rd imm16) - (set-psw Rd (index-of Rd) (or Rd imm16) 1) - () -) - -(dni xorgrgr - "XOR general register with general register" - () - ("xor $Rd,$Rs") - (+ OP1_4 OP2_4 Rs Rd) - (set-psw Rd (index-of Rd) (xor Rd Rs) 1) - () -) - -(dni xorimm8 - "XOR with 8-bit immediate" - () - ("xor Rx,#$imm8") - (+ OP1_4 OP2_5 imm8) - (set-psw (reg HI h-gr Rpsw) Rpsw (xor (reg HI h-gr Rpsw) imm8) 1) - () -) - -(dni xorgrimm16 - "XOR general register with 16-bit immediate" - () - ("xor $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_2 Rd imm16) - (set-psw Rd (index-of Rd) (xor Rd imm16) 1) - () -) - -(dni notgr - "NOT general register" - () - ("not $Rd") - (+ OP1_3 OP2_0 OP3_B Rd) - (set-psw Rd (index-of Rd) (inv Rd) 1) - () -) - -; Arithmetic operations -(dni addgrgr - "ADD general register to general register" - () - ("add $Rd,$Rs") - (+ OP1_4 OP2_9 Rs Rd) - (set-psw-add Rd (index-of Rd) Rd Rs 0) - () -) - -(dni addgrimm4 - "ADD 4-bit immediate to general register" - () - ("add $Rd,#$imm4") - (+ OP1_5 OP2_1 imm4 Rd) - (set-psw-add Rd (index-of Rd) Rd imm4 0) - () -) - -(dni addimm8 - "ADD 8-bit immediate" - () - ("add Rx,#$imm8") - (+ OP1_5 OP2_9 imm8) - (set-psw-add (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 0) - () -) - -(dni addgrimm16 - "ADD 16-bit immediate to general register" - () - ("add $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_4 Rd imm16) - (set-psw-add Rd (index-of Rd) Rd imm16 0) - () -) - -(dni adcgrgr - "ADD carry and general register to general register" - () - ("adc $Rd,$Rs") - (+ OP1_4 OP2_B Rs Rd) - (set-psw-add Rd (index-of Rd) Rd Rs psw-cy) - () -) - -(dni adcgrimm4 - "ADD carry and 4-bit immediate to general register" - () - ("adc $Rd,#$imm4") - (+ OP1_5 OP2_3 imm4 Rd) - (set-psw-add Rd (index-of Rd) Rd imm4 psw-cy) - () -) - -(dni adcimm8 - "ADD carry and 8-bit immediate" - () - ("adc Rx,#$imm8") - (+ OP1_5 OP2_B imm8) - (set-psw-add (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 psw-cy) - () -) - -(dni adcgrimm16 - "ADD carry and 16-bit immediate to general register" - () - ("adc $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_5 Rd imm16) - (set-psw-add Rd (index-of Rd) Rd imm16 psw-cy) - () -) - -(dni subgrgr - "SUB general register from general register" - () - ("sub $Rd,$Rs") - (+ OP1_4 OP2_D Rs Rd) - (set-psw-sub Rd (index-of Rd) Rd Rs 0) - () -) - -(dni subgrimm4 - "SUB 4-bit immediate from general register" - () - ("sub $Rd,#$imm4") - (+ OP1_5 OP2_5 imm4 Rd) - (set-psw-sub Rd (index-of Rd) Rd imm4 0) - () -) - -(dni subimm8 - "SUB 8-bit immediate" - () - ("sub Rx,#$imm8") - (+ OP1_5 OP2_D imm8) - (set-psw-sub (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 0) - () -) - -(dni subgrimm16 - "SUB 16-bit immediate from general register" - () - ("sub $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_6 Rd imm16) - (set-psw-sub Rd (index-of Rd) Rd imm16 0) - () -) - -(dni sbcgrgr - "SUB carry and general register from general register" - () - ("sbc $Rd,$Rs") - (+ OP1_4 OP2_F Rs Rd) - (set-psw-sub Rd (index-of Rd) Rd Rs psw-cy) - () -) - -(dni sbcgrimm4 - "SUB carry and 4-bit immediate from general register" - () - ("sbc $Rd,#$imm4") - (+ OP1_5 OP2_7 imm4 Rd) - (set-psw-sub Rd (index-of Rd) Rd imm4 psw-cy) - () -) - -(dni sbcgrimm8 - "SUB carry and 8-bit immediate" - () - ("sbc Rx,#$imm8") - (+ OP1_5 OP2_F imm8) - (set-psw-sub (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 psw-cy) - () -) - -(dni sbcgrimm16 - "SUB carry and 16-bit immediate from general register" - () - ("sbc $Rd,#$imm16") - (+ OP1_3 OP2_1 OP3_7 Rd imm16) - (set-psw-sub Rd (index-of Rd) Rd imm16 psw-cy) - () -) - -(dnmi incgr - "Increment general register" - () - ("inc $Rd") - (emit incgrimm2 Rd (imm2 0)) -) - -(dni incgrimm2 - "Increment general register by 2-bit immediate" - () - ("inc $Rd,#$imm2") - (+ OP1_3 OP2_0 OP3A_0 imm2 Rd) - (set-psw Rd (index-of Rd) (add Rd (add imm2 1)) 1) - () -) - -(dnmi decgr - "Decrement general register" - () - ("dec $Rd") - (emit decgrimm2 Rd (imm2 0)) -) - -(dni decgrimm2 - "Decrement general register by 2-bit immediate" - () - ("dec $Rd,#$imm2") - (+ OP1_3 OP2_0 OP3A_1 imm2 Rd) - (set-psw Rd (index-of Rd) (sub Rd (add imm2 1)) 1) - () -) - -; Logical Shift -(dni rrcgrgr - "Rotate right general register by general register" - () - ("rrc $Rd,$Rs") - (+ OP1_3 OP2_8 Rs Rd) - (set-psw-rrotate17 Rd (index-of Rd) Rd psw-cy Rs) - () -) - -(dni rrcgrimm4 - "Rotate right general register by immediate" - () - ("rrc $Rd,#$imm4") - (+ OP1_3 OP2_9 imm4 Rd) - (set-psw-rrotate17 Rd (index-of Rd) Rd psw-cy imm4) - () -) - -(dni rlcgrgr - "Rotate left general register by general register" - () - ("rlc $Rd,$Rs") - (+ OP1_3 OP2_A Rs Rd) - (set-psw-rotate17 Rd (index-of Rd) Rd psw-cy (and Rs #xF)) - () -) - -(dni rlcgrimm4 - "Rotate left general register by immediate" - () - ("rlc $Rd,#$imm4") - (+ OP1_3 OP2_B imm4 Rd) - (set-psw-rotate17 Rd (index-of Rd) Rd psw-cy imm4) - () -) - -(dni shrgrgr - "Shift right general register by general register" - () - ("shr $Rd,$Rs") - (+ OP1_3 OP2_C Rs Rd) - (set-psw-carry Rd (index-of Rd) - (srl Rd (and Rs #xF)) - (and SI (if SI (eq (and Rs #xF) 0) - psw-cy - (srl Rd (sub (and Rs #xF) 1))) - 1) 1) - () -) - -(dni shrgrimm - "Shift right general register by immediate" - () - ("shr $Rd,#$imm4") - (+ OP1_3 OP2_D imm4 Rd) - (set-psw-carry Rd (index-of Rd) - (srl Rd imm4) - (and SI (if SI (eq imm4 0) - psw-cy - (srl Rd (sub imm4 1))) - 1) 1) - () -) - -(dni shlgrgr - "Shift left general register by general register" - () - ("shl $Rd,$Rs") - (+ OP1_3 OP2_E Rs Rd) - (set-psw-carry Rd (index-of Rd) - (sll Rd (and Rs #xF)) - (srl SI (if SI (eq (and Rs #xF) 0) - (sll psw-cy 15) - (sll Rd (sub (and Rs #xF) 1))) - 15) 1) - () -) - -(dni shlgrimm - "Shift left general register by immediate" - () - ("shl $Rd,#$imm4") - (+ OP1_3 OP2_F imm4 Rd) - (set-psw-carry Rd (index-of Rd) - (sll Rd imm4) - (srl SI (if SI (eq imm4 0) - (sll psw-cy 15) - (sll Rd (sub imm4 1))) - 15) 1) - () -) - -(dni asrgrgr - "Arithmetic shift right general register by general register" - () - ("asr $Rd,$Rs") - (+ OP1_3 OP2_6 Rs Rd) - (set-psw-carry Rd (index-of Rd) - (sra HI Rd (and Rs #xF)) - (and SI (if SI (eq (and Rs #xF) 0) - psw-cy - (srl Rd (sub (and Rs #xF) 1))) - 1) 1) - () -) - -(dni asrgrimm - "Arithmetic shift right general register by immediate" - () - ("asr $Rd,#$imm4") - (+ OP1_3 OP2_7 imm4 Rd) - (set-psw-carry Rd (index-of Rd) - (sra HI Rd imm4) - (and SI (if SI (eq imm4 0) - psw-cy - (srl Rd (sub imm4 1))) - 1) 1) - () -) - -; Bitwise operations -(dni set1grimm - "Set bit in general register by immediate" - () - ("set1 $Rd,#$imm4") - (+ OP1_0 OP2_9 imm4 Rd) - (set-psw Rd (index-of Rd) (or Rd (sll 1 imm4)) 1) - () -) - -(dni set1grgr - "Set bit in general register by general register" - () - ("set1 $Rd,$Rs") - (+ OP1_0 OP2_B Rs Rd) - (set-psw Rd (index-of Rd) (or Rd (sll 1 (and Rs #xF))) 1) - () -) - -(dni set1lmemimm - "Set bit in low memory by immediate" - () - ("set1 $lmem8,#$imm3") - (+ OP1_E imm3 OP2M_1 lmem8) - (set-mem-psw (mem QI lmem8) (or (mem QI lmem8) (sll 1 imm3)) 0) - () -) -(dni set1hmemimm - "Set bit in high memory by immediate" - () - ("set1 $hmem8,#$imm3") - (+ OP1_F imm3 OP2M_1 hmem8) - (set-mem-psw (mem QI hmem8) (or (mem QI hmem8) (sll 1 imm3)) 0) - () -) - -(dni clr1grimm - "Clear bit in general register by immediate" - () - ("clr1 $Rd,#$imm4") - (+ OP1_0 OP2_8 imm4 Rd) - (set-psw Rd (index-of Rd) (and Rd (inv (sll 1 imm4))) 1) - () -) - -(dni clr1grgr - "Clear bit in general register by general register" - () - ("clr1 $Rd,$Rs") - (+ OP1_0 OP2_A Rs Rd) - (set-psw Rd (index-of Rd) (and Rd (inv (sll 1 (and Rs #xF)))) 1) - () -) - -(dni clr1lmemimm - "Clear bit in low memory" - () - ("clr1 $lmem8,#$imm3") - (+ OP1_E imm3 OP2M_0 lmem8) - (set-mem-psw (mem QI lmem8) (and (mem QI lmem8) (inv (sll 1 imm3))) 0) - () -) -(dni clr1hmemimm - "Clear bit in high memory" - () - ("clr1 $hmem8,#$imm3") - (+ OP1_F imm3 OP2M_0 hmem8) - (set-mem-psw (mem QI hmem8) (and (mem QI hmem8) (inv (sll 1 imm3))) 0) - () -) - -; Data conversion - -(dni cbwgr - "Sign-extend byte in general register" - () - ("cbw $Rd") - (+ OP1_3 OP2_0 OP3_A Rd) - (set-psw Rd (index-of Rd) (ext HI (trunc QI Rd)) 1) - () -) - -(dni revgr - "Reverse bit pattern in general register" - () - ("rev $Rd") - (+ OP1_3 OP2_0 OP3_F Rd) - (set-psw Rd (index-of Rd) - (or (sll (and Rd #x0001) 15) - (or (sll (and Rd #x0002) 13) - (or (sll (and Rd #x0004) 11) - (or (sll (and Rd #x0008) 9) - (or (sll (and Rd #x0010) 7) - (or (sll (and Rd #x0020) 5) - (or (sll (and Rd #x0040) 3) - (or (sll (and Rd #x0080) 1) - (or (srl (and Rd #x0100) 1) - (or (srl (and Rd #x0200) 3) - (or (srl (and Rd #x0400) 5) - (or (srl (and Rd #x0800) 7) - (or (srl (and Rd #x1000) 9) - (or (srl (and Rd #x2000) 11) - (or (srl (and Rd #x4000) 13) - (srl (and Rd #x8000) 15)))))))))))))))) - 1) - () -) - -; Conditional Branches - -(define-pmacro (cbranch cond dest) - (sequence ((BI tmp)) - (case cond - ((0) (set tmp (not (xor psw-s psw-ov)))) ; ge - ((1) (set tmp (not psw-cy))) ; nc - ((2) (set tmp (xor psw-s psw-ov))) ; lt - ((3) (set tmp psw-cy)) ; c - ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ; gt - ((5) (set tmp (not (or psw-cy psw-z16)))) ; hi - ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ; le - ((7) (set tmp (or psw-cy psw-z16))) ; ls - ((8) (set tmp (not psw-s))) ; pl - ((9) (set tmp (not psw-ov))) ; nv - ((10) (set tmp psw-s)) ; mi - ((11) (set tmp psw-ov)) ; v - ((12) (set tmp (not psw-z8))) ; nz.b - ((13) (set tmp (not psw-z16))) ; nz - ((14) (set tmp psw-z8)) ; z.b - ((15) (set tmp psw-z16))) ; z - (if tmp (set pc dest))) -) - -(dni bccgrgr - "Conditional branch comparing general register with general register" - () - ("b$bcond5 $Rd,$Rs,$rel12") - (+ OP1_0 OP2_D Rs Rd bcond5 rel12) - (sequence () - (set-psw-cmp Rd (index-of Rd) Rd Rs) - (cbranch bcond5 rel12)) - () -) - -; 4 bytes -(dni bccgrimm8 - "Conditional branch comparing general register with 8-bit immediate" - () - ("b$bcond5 $Rm,#$imm8,$rel12") - (+ OP1_2 OP2M_0 Rm imm8 bcond5 rel12) - (sequence () - (set-psw-cmp Rm (index-of Rm) Rm imm8) - (cbranch bcond5 rel12)) - () -) - -; 4 bytes -(dni bccimm16 - "Conditional branch comparing general register with 16-bit immediate" - () - ("b$bcond2 Rx,#$imm16,${rel8-4}") - (+ OP1_C bcond2 rel8-4 imm16) - (sequence () - (set-psw-cmp (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm16) - (cbranch bcond2 rel8-4)) - () -) - -(dni bngrimm4 - "Test bit in general register by immediate and branch if 0" - () - ("bn $Rd,#$imm4,$rel12") - (+ OP1_0 OP2_4 imm4 Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (eq (and Rd (sll 1 imm4)) 0) - (set pc rel12))) - () -) - -(dni bngrgr - "Test bit in general register by general register and branch if 0" - () - ("bn $Rd,$Rs,$rel12") - (+ OP1_0 OP2_6 Rs Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (eq (and Rd (sll 1 Rs)) 0) - (set pc rel12))) - () -) - -(dni bnlmemimm - "Test bit in memory by immediate and branch if 0" - () - ("bn $lmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_C lmem8 OP5A_0 imm3b rel12) - (if (eq (and (mem QI lmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bnhmemimm - "Test bit in memory by immediate and branch if 0" - () - ("bn $hmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_E hmem8 OP5A_0 imm3b rel12) - (if (eq (and (mem QI hmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bpgrimm4 - "Test bit in general register by immediate and branch if 1" - () - ("bp $Rd,#$imm4,$rel12") - (+ OP1_0 OP2_5 imm4 Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (ne (and Rd (sll 1 imm4)) 0) - (set pc rel12))) - () -) - -(dni bpgrgr - "Test bit in general register by general register and branch if 1" - () - ("bp $Rd,$Rs,$rel12") - (+ OP1_0 OP2_7 Rs Rd OP5_0 rel12) - (sequence () - (set Rpsw (index-of Rd)) - (if (ne (and Rd (sll 1 Rs)) 0) - (set pc rel12))) - () -) - -(dni bplmemimm - "Test bit in memory by immediate and branch if 1" - () - ("bp $lmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_D lmem8 OP5A_0 imm3b rel12) - (if (ne (and (mem QI lmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bphmemimm - "Test bit in memory by immediate and branch if 1" - () - ("bp $hmem8,#$imm3b,$rel12") - (+ OP1_7 OP2_F hmem8 OP5A_0 imm3b rel12) - (if (ne (and (mem QI hmem8) (sll 1 imm3b)) 0) - (set pc rel12)) - () -) - -(dni bcc - "Conditional branch on flag registers" - () - ("b$bcond2 ${rel8-2}") - (+ OP1_D bcond2 rel8-2) - (cbranch bcond2 rel8-2) - () -) - -; Unconditional Branching - -(dni bgr - "Branch to register" - () - ("br $Rd") - (+ OP1_0 OP2_0 OP3_2 Rd) - (set pc (add (add pc 2) Rd)) - () -) - -(dni br - "Branch" - () - ("br $rel12a") - (+ OP1_1 rel12a OP4B_0) - (set pc rel12a) - () -) - -(dni jmp - "Jump" - () - ("jmp $Rbj,$Rd") - (+ OP1_0 OP2_0 OP3B_4 Rbj Rd) - (set pc (join SI HI Rbj Rd)) - () -) - -(dni jmpf - "Jump far" - () - ("jmpf $abs24") - (+ OP1_0 OP2_2 abs24) - (set pc abs24) - () -) - -; Call instructions -(define-pmacro (do-call dest ilen) - (sequence () - (set (mem SI sp) (add pc ilen)) - (set sp (add sp 4)) - (set pc dest))) - -(dni callrgr - "Call relative to general register" - () - ("callr $Rd") - (+ OP1_0 OP2_0 OP3_1 Rd) - (do-call (add Rd (add pc 2)) 2) - () -) - -(dni callrimm - "Call relative to immediate address" - () - ("callr $rel12a") - (+ OP1_1 rel12a OP4B_1) - (do-call rel12a 2) - () -) - -(dni callgr - "Call to general registers" - () - ("call $Rbj,$Rd") - (+ OP1_0 OP2_0 OP3B_A Rbj Rd) - (do-call (join SI HI Rbj Rd) 2) - () -) - -(dni callfimm - "Call far to absolute address" - () - ("callf $abs24") - (+ OP1_0 OP2_1 abs24) - (do-call abs24 4) - () -) - -(define-pmacro (do-calli dest ilen) - (sequence () - (set (mem SI sp) (add pc ilen)) - (set (mem HI (add sp 4)) psw) - (set sp (add sp 6)) - (set pc dest))) - -(dni icallrgr - "Call interrupt to general registers pc-relative" - () - ("icallr $Rd") - (+ OP1_0 OP2_0 OP3_3 Rd) - (do-calli (add Rd (add pc 2)) 2) - () -) - -(dni icallgr - "Call interrupt to general registers" - () - ("icall $Rbj,$Rd") - (+ OP1_0 OP2_0 OP3B_6 Rbj Rd) - (do-calli (join SI HI Rbj Rd) 2) - () -) - -(dni icallfimm - "Call interrupt far to absolute address" - () - ("icallf $abs24") - (+ OP1_0 OP2_3 abs24) - (do-calli abs24 4) - () -) - -; Return instructions -(dni iret - "Return from interrupt" - () - ("iret") - (+ (f-op #x0002)) - (sequence () - (set sp (sub sp 6)) - (set pc (mem SI sp)) - (set psw (mem HI (add sp 4)))) - () -) - -(dni ret - "Return" - () - ("ret") - (+ (f-op #x0003)) - (sequence () - (set sp (sub sp 4)) - (set pc (mem SI sp))) - () -) - -; Multiply and Divide instructions - -(dni mul - "Multiply" - () - ("mul") - (+ (f-op #x00D0)) - (sequence ((SI value)) - (set value (mul SI (and SI R0 #xFFFF) (and SI R2 #xFFFF))) - (set psw (or (and psw #xFF9C) - (basic-psw (trunc HI value) 1))) - (set R0 (trunc HI value)) - (set R1 (trunc HI (srl value 16)))) - () -) -(dni div - "Divide" - () - ("div") - (+ (f-op #x00C0)) - (sequence () - (set R1 (umod R0 R2)) - (set-mem-psw R0 (udiv R0 R2) 1)) - () -) -(dni sdiv - "Signed Divide" - () - ("sdiv") - (+ (f-op #x00C8)) - (sequence () - (set R1 (mod HI R0 R2)) - (set-mem-psw R0 (div HI R0 R2) 1)) - () -) -(dni sdivlh - "Divide 32/16" - () - ("sdivlh") - (+ (f-op #x00E8)) - (sequence ((SI value)) - (set value (add SI (sll SI (and SI R1 #xffff) #x10) (and SI R0 #xffff))) - (set R1 (mod SI value (ext SI (trunc HI R2)))) - (set-mem-psw R0 (div SI value (ext SI (trunc HI R2))) 1)) - () -) -(dni divlh - "Divide 32/16" - () - ("divlh") - (+ (f-op #x00E0)) - (sequence ((SI value)) - (set value (add SI (sll SI (and SI R1 #xffff) #x10) (and SI R0 #xffff))) - (set R1 (umod SI value R2)) - (set-mem-psw R0 (udiv SI value R2) 1)) - () -) - -; System Control - -; added per sanyo's req -- eq to nop for the moment, but can -; add function later -(dni reset "reset" () ("reset") (+ (f-op #x000f)) (nop) ()) - -(dni nop "nop" () ("nop") (+ (f-op #x0000)) (nop) ()) - -(dni halt "halt" () ("halt") (+ (f-op #x0008)) (c-call VOID "do_halt") ()) - -(dni hold "hold" () ("hold") (+ (f-op #x000A)) (c-call VOID "do_hold") ()) - -(dni holdx "holdx" () ("holdx") (+ (f-op #x000B)) (c-call VOID "do_holdx") ()) - -(dni brk "brk" () ("brk") (+ (f-op #x0005)) (c-call VOID "do_brk") ()) - -; An instruction for test instrumentation. -; Using a reserved opcode. -(dni syscall - "simulator system call" - () - ("--unused--") - (+ (f-op #x0001)) - (c-call VOID "syscall") - () -) diff --git a/binutils-2.24/cpu/xstormy16.opc b/binutils-2.24/cpu/xstormy16.opc deleted file mode 100644 index 6d2d16c1..00000000 --- a/binutils-2.24/cpu/xstormy16.opc +++ /dev/null @@ -1,168 +0,0 @@ -/* XSTORMY16 opcode support. -*- C -*- - Copyright 2011 Free Software Foundation, Inc. - - Contributed by Red Hat Inc; - - This file is part of the GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* This file is an addendum to xstormy16.cpu. Heavy use of C code isn't - appropriate in .cpu files, so it resides here. This especially applies - to assembly/disassembly where parsing/printing can be quite involved. - Such things aren't really part of the specification of the cpu, per se, - so .cpu files provide the general framework and .opc files handle the - nitty-gritty details as necessary. - - Each section is delimited with start and end markers. - - <arch>-opc.h additions use: "-- opc.h" - <arch>-opc.c additions use: "-- opc.c" - <arch>-asm.c additions use: "-- asm.c" - <arch>-dis.c additions use: "-- dis.c" - <arch>-ibd.h additions use: "-- ibd.h". */ - -/* -- opc.h */ - -/* Allows reason codes to be output when assembler errors occur. */ -#define CGEN_VERBOSE_ASSEMBLER_ERRORS - -/* We can't use the default hash size because many bits are used by - operands. */ -#define CGEN_DIS_HASH_SIZE 1 -#define CGEN_DIS_HASH(buf, value) 0 -/* -- */ - -/* -- asm.c */ - -/* The machine-independent code doesn't know how to disambiguate - mov (foo),r3 - and - mov (r2),r3 - where 'foo' is a label. This helps it out. */ - -static const char * -parse_mem8 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - if (**strp == '(') - { - const char *s = *strp; - - if (s[1] == '-' && s[2] == '-') - return _("Bad register in preincrement"); - - while (ISALNUM (*++s)) - ; - if (s[0] == '+' && s[1] == '+' && (s[2] == ')' || s[2] == ',')) - return _("Bad register in postincrement"); - if (s[0] == ',' || s[0] == ')') - return _("Bad register name"); - } - else if (cgen_parse_keyword (cd, strp, & xstormy16_cgen_opval_gr_names, - (long *) valuep) == NULL) - return _("Label conflicts with register name"); - else if (strncasecmp (*strp, "rx,", 3) == 0 - || strncasecmp (*strp, "rxl,", 3) == 0 - || strncasecmp (*strp, "rxh,", 3) == 0) - return _("Label conflicts with `Rx'"); - else if (**strp == '#') - return _("Bad immediate expression"); - - return cgen_parse_unsigned_integer (cd, strp, opindex, valuep); -} - -/* For the add and subtract instructions, there are two immediate forms, - one for small operands and one for large ones. We want to use - the small one when possible, but we do not want to generate relocs - of the small size. This is somewhat tricky. */ - -static const char * -parse_small_immediate (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - if (**strp == '@') - return _("No relocation for small immediate"); - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - & result, & value); - - if (errmsg) - return errmsg; - - if (result != CGEN_PARSE_OPERAND_RESULT_NUMBER) - return _("Small operand was not an immediate number"); - - *valuep = value; - return NULL; -} - -/* Literal scan be either a normal literal, a @hi() or @lo relocation. */ - -static const char * -parse_immediate16 (CGEN_CPU_DESC cd, - const char **strp, - int opindex, - unsigned long *valuep) -{ - const char *errmsg; - enum cgen_parse_operand_result result; - bfd_reloc_code_real_type code = BFD_RELOC_NONE; - bfd_vma value; - - if (strncmp (*strp, "@hi(", 4) == 0) - { - *strp += 4; - code = BFD_RELOC_HI16; - } - else - if (strncmp (*strp, "@lo(", 4) == 0) - { - *strp += 4; - code = BFD_RELOC_LO16; - } - - if (code == BFD_RELOC_NONE) - errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, valuep); - else - { - errmsg = cgen_parse_address (cd, strp, opindex, code, &result, &value); - if ((errmsg == NULL) && - (result != CGEN_PARSE_OPERAND_RESULT_QUEUED)) - errmsg = _("Operand is not a symbol"); - - *valuep = value; - if ((code == BFD_RELOC_HI16 || code == BFD_RELOC_LO16) - && **strp == ')') - *strp += 1; - else - { - errmsg = _("Syntax error: No trailing ')'"); - return errmsg; - } - } - return errmsg; -} -/* -- */ |