diff options
Diffstat (limited to 'binutils-2.17/gas/testsuite/gas/arm')
158 files changed, 0 insertions, 11608 deletions
diff --git a/binutils-2.17/gas/testsuite/gas/arm/abs12.d b/binutils-2.17/gas/testsuite/gas/arm/abs12.d deleted file mode 100644 index 5d4bb3b3..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/abs12.d +++ /dev/null @@ -1,20 +0,0 @@ -#objdump: -dr -#not-skip: *-vxworks - -.*: file format .* - -Disassembly of section \.text: - -00000000 <\.text>: - 0: e5910000 ldr r0, \[r1\] - 0: R_ARM_ABS12 global - 4: e5910000 ldr r0, \[r1\] - 4: R_ARM_ABS12 global\+0xc - 8: e5910000 ldr r0, \[r1\] - 8: R_ARM_ABS12 global\+0x100000 - c: e5910000 ldr r0, \[r1\] - c: R_ARM_ABS12 \.text\+0x18 - 10: e5910000 ldr r0, \[r1\] - 10: R_ARM_ABS12 \.text\+0x24 - 14: e5910000 ldr r0, \[r1\] - 14: R_ARM_ABS12 \.text\+0x100018 diff --git a/binutils-2.17/gas/testsuite/gas/arm/abs12.s b/binutils-2.17/gas/testsuite/gas/arm/abs12.s deleted file mode 100644 index 9c2faa55..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/abs12.s +++ /dev/null @@ -1,7 +0,0 @@ - ldr r0,[r1,#global] - ldr r0,[r1,#global + 12] - ldr r0,[r1,#global + 0x100000] - ldr r0,[r1,#local] - ldr r0,[r1,#local + 12] - ldr r0,[r1,#local + 0x100000] -local: diff --git a/binutils-2.17/gas/testsuite/gas/arm/adrl.d b/binutils-2.17/gas/testsuite/gas/arm/adrl.d deleted file mode 100644 index ccd4ef71..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/adrl.d +++ /dev/null @@ -1,27 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ADRL - -# Test the `ADRL' pseudo-op - -.*: +file format .*arm.* - -Disassembly of section .text: - ... -0+2000 <.*> e24f0008 sub r0, pc, #8 ; 0x8 -0+2004 <.*> e2400c20 sub r0, r0, #8192 ; 0x2000 -0+2008 <.*> e28f0020 add r0, pc, #32 ; 0x20 -0+200c <.*> e2800c20 add r0, r0, #8192 ; 0x2000 -0+2010 <.*> e24f0018 sub r0, pc, #24 ; 0x18 -0+2014 <.*> e1a00000 nop \(mov r0,r0\) -0+2018 <.*> e28f0008 add r0, pc, #8 ; 0x8 -0+201c <.*> e1a00000 nop \(mov r0,r0\) -0+2020 <.*> 028f0000 addeq r0, pc, #0 ; 0x0 -0+2024 <.*> e1a00000 nop \(mov r0,r0\) -0+2028 <.*> e24f0030 sub r0, pc, #48 ; 0x30 -0+202c <.*> e2400c20 sub r0, r0, #8192 ; 0x2000 -0+2030 <.*> e28f0c21 add r0, pc, #8448 ; 0x2100 -0+2034 <.*> e1a00000 nop \(mov r0,r0\) - ... -0+4030 <.*> e28fec01 add lr, pc, #256 ; 0x100 - ... - ... diff --git a/binutils-2.17/gas/testsuite/gas/arm/adrl.s b/binutils-2.17/gas/testsuite/gas/arm/adrl.s deleted file mode 100644 index 5bb7456f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/adrl.s +++ /dev/null @@ -1,24 +0,0 @@ - @ test ADRL pseudo-op - .text - .global foo -foo: - .align 0 -1: - .space 8192 -2: - adrl r0, 1b - adrl r0, 1f - adrl r0, 2b - adrl r0, 2f - adrEQl r0, 2f -2: - adrl r0, foo - adrl r0, X - .space 8184 -1: - adral lr, X - .space 0x0104 - - .globl X; -X: - .p2align 5,0 diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch4t.d b/binutils-2.17/gas/testsuite/gas/arm/arch4t.d deleted file mode 100644 index 0fdaa8fd..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch4t.d +++ /dev/null @@ -1,36 +0,0 @@ -# name: ARM architecture 4t instructions -# as: -march=armv4t -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]+> e12fff10 ? bx r0 -0+04 <[^>]+> 012fff11 ? bxeq r1 -0+08 <[^>]+> e15f30b8 ? ldrh r3, \[pc, #-8\] ; 0+08 <[^>]+> -0+0c <[^>]+> e1d540f0 ? ldrsh r4, \[r5\] -0+10 <[^>]+> e19140d3 ? ldrsb r4, \[r1, r3\] -0+14 <[^>]+> e1b410f4 ? ldrsh r1, \[r4, r4\]! -0+18 <[^>]+> 011510d3 ? ldreqsb r1, \[r5, -r3\] -0+1c <[^>]+> 109620b7 ? ldrneh r2, \[r6\], r7 -0+20 <[^>]+> 309720f8 ? ldrccsh r2, \[r7\], r8 -0+24 <[^>]+> e1d32fdf ? ldrsb r2, \[r3, #255\] -0+28 <[^>]+> e1541ffa ? ldrsh r1, \[r4, #-250\] -0+2c <[^>]+> e1d51fd0 ? ldrsb r1, \[r5, #240\] -0+30 <[^>]+> e1cf23b0 ? strh r2, \[pc, #48\] ; 0+68 <[^>]+> -0+34 <[^>]+> 11c330b0 ? strneh r3, \[r3\] -0+38 <[^>]+> e328f002 ? msr CPSR_f, #2 ; 0x2 -0+3c <[^>]+> e121f003 ? msr CPSR_c, r3 -0+40 <[^>]+> e122f004 ? msr CPSR_x, r4 -0+44 <[^>]+> e124f005 ? msr CPSR_s, r5 -0+48 <[^>]+> e128f006 ? msr CPSR_f, r6 -0+4c <[^>]+> e129f007 ? msr CPSR_fc, r7 -0+50 <[^>]+> e368f004 ? msr SPSR_f, #4 ; 0x4 -0+54 <[^>]+> e161f008 ? msr SPSR_c, r8 -0+58 <[^>]+> e162f009 ? msr SPSR_x, r9 -0+5c <[^>]+> e164f00a ? msr SPSR_s, sl -0+60 <[^>]+> e168f00b ? msr SPSR_f, fp -0+64 <[^>]+> e169f00c ? msr SPSR_fc, ip -0+68 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+6c <[^>]+> e1a00000 ? nop \(mov r0,r0\) - diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch4t.s b/binutils-2.17/gas/testsuite/gas/arm/arch4t.s deleted file mode 100644 index 984829d8..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch4t.s +++ /dev/null @@ -1,38 +0,0 @@ - .text - .align 0 -l: - bx r0 - bxeq r1 - -foo: - ldrh r3, foo - ldrsh r4, [r5] - ldrsb r4, [r1, r3] - ldrsh r1, [r4, r4]! - ldreqsb r1, [r5, -r3] - ldrneh r2, [r6], r7 - ldrccsh r2, [r7], +r8 - ldrsb r2, [r3, #255] - ldrsh r1, [r4, #-250] - ldrsb r1, [r5, #+240] - - strh r2, bar - strneh r3, [r3] - - msr CPSR_f, #2 - msr CPSR_c, r3 - msr CPSR_x, r4 - msr CPSR_s, r5 - msr CPSR_f, r6 - msr CPSR_all, r7 - - msr SPSR_f, #4 - msr SPSR_c, r8 - msr SPSR_x, r9 - msr SPSR_s, r10 - msr SPSR_f, r11 - msr SPSR_all, r12 -bar: - @ section padding for a.out's benefit - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch5tej.d b/binutils-2.17/gas/testsuite/gas/arm/arch5tej.d deleted file mode 100644 index 49d2cbbe..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch5tej.d +++ /dev/null @@ -1,17 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM Architecture v5TEJ instructions -#as: -march=armv5tej - -# Test the ARM Architecture v5TEJ instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> e12fff20 ? bxj r0 -0+04 <[^>]*> e12fff21 ? bxj r1 -0+08 <[^>]*> e12fff2e ? bxj lr -0+0c <[^>]*> 012fff20 ? bxjeq r0 -0+10 <[^>]*> 412fff20 ? bxjmi r0 -0+14 <[^>]*> 512fff27 ? bxjpl r7 -0+18 <[^>]*> e1200070 ? bkpt 0x0000 -0+1c <[^>]*> e120007a ? bkpt 0x000a diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch5tej.s b/binutils-2.17/gas/testsuite/gas/arm/arch5tej.s deleted file mode 100644 index 4624b7e1..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch5tej.s +++ /dev/null @@ -1,12 +0,0 @@ - .text - .align 0 -label: - bxj r0 - bxj r1 - bxj r14 - bxjeq r0 - bxjmi r0 - bxjpl r7 - - bkpt @ Support for a breakpoint without an argument - bkpt 10 @ is a feature added to GAS. diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch6zk.d b/binutils-2.17/gas/testsuite/gas/arm/arch6zk.d deleted file mode 100644 index e9dee215..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch6zk.d +++ /dev/null @@ -1,32 +0,0 @@ -#name: ARM V6 instructions -#as: -march=armv6zk -#objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> f57ff01f ? clrex -0+004 <[^>]*> e1dc4f9f ? ldrexb r4, \[ip\] -0+008 <[^>]*> 11d4cf9f ? ldrexbne ip, \[r4\] -0+00c <[^>]*> e1bc4f9f ? ldrexd r4, \[ip\] -0+010 <[^>]*> 11b4cf9f ? ldrexdne ip, \[r4\] -0+014 <[^>]*> e1fc4f9f ? ldrexh r4, \[ip\] -0+018 <[^>]*> 11f4cf9f ? ldrexhne ip, \[r4\] -0+01c <[^>]*> e320f080 ? nop \{128\} -0+020 <[^>]*> 1320f07f ? nopne \{127\} -0+024 <[^>]*> e320f004 ? sev -0+028 <[^>]*> e1c74f9c ? strexb r4, ip, \[r7\] -0+02c <[^>]*> 11c8cf94 ? strexbne ip, r4, \[r8\] -0+030 <[^>]*> e1a74f9c ? strexd r4, ip, \[r7\] -0+034 <[^>]*> 11a8cf94 ? strexdne ip, r4, \[r8\] -0+038 <[^>]*> e1e74f9c ? strexh r4, ip, \[r7\] -0+03c <[^>]*> 11e8cf94 ? strexhne ip, r4, \[r8\] -0+040 <[^>]*> e320f002 ? wfe -0+044 <[^>]*> e320f003 ? wfi -0+048 <[^>]*> e320f001 ? yield -0+04c <[^>]*> e16ec371 ? smc 60465 -0+050 <[^>]*> 11613c7e ? smcne 5070 -0+054 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+058 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+05c <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) - diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch6zk.s b/binutils-2.17/gas/testsuite/gas/arm/arch6zk.s deleted file mode 100644 index 93398675..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch6zk.s +++ /dev/null @@ -1,33 +0,0 @@ -.text -.align 0 - -label: - # ARMV6K instructions - clrex - ldrexb r4, [r12] - ldrexbne r12, [r4] - ldrexd r4, [r12] - ldrexdne r12, [r4] - ldrexh r4, [r12] - ldrexhne r12, [r4] - nop {128} - nopne {127} - sev - strexb r4, r12, [r7] - strexbne r12, r4, [r8] - strexd r4, r12, [r7] - strexdne r12, r4, [r8] - strexh r4, r12, [r7] - strexhne r12, r4, [r8] - wfe - wfi - yield - # ARMV6Z instructions - smc 0xec31 - smcne 0x13ce - - # Add three nop instructions to ensure that the - # output is 32-byte aligned as required for arm-aout. - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch7.d b/binutils-2.17/gas/testsuite/gas/arm/arch7.d deleted file mode 100644 index 992948b8..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch7.d +++ /dev/null @@ -1,77 +0,0 @@ -#name: ARM V7 instructions -#as: -march=armv7r -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -#objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> f6d6f008 pli \[r6, r8\] -0+004 <[^>]*> f6d9f007 pli \[r9, r7\] -0+008 <[^>]*> f6d0f101 pli \[r0, r1, lsl #2\] -0+00c <[^>]*> f4d5f000 pli \[r5\] -0+010 <[^>]*> f4d5ffff pli \[r5, #4095\] -0+014 <[^>]*> f455ffff pli \[r5, #-4095\] -0+018 <[^>]*> e320f0f0 dbg #0 -0+01c <[^>]*> e320f0ff dbg #15 -0+020 <[^>]*> f57ff05f dmb sy -0+024 <[^>]*> f57ff05f dmb sy -0+028 <[^>]*> f57ff04f dsb sy -0+02c <[^>]*> f57ff04f dsb sy -0+030 <[^>]*> f57ff047 dsb un -0+034 <[^>]*> f57ff04e dsb st -0+038 <[^>]*> f57ff046 dsb unst -0+03c <[^>]*> f57ff06f isb sy -0+040 <[^>]*> f57ff06f isb sy -0+044 <[^>]*> f916 f008 pli \[r6, r8\] -0+048 <[^>]*> f919 f007 pli \[r9, r7\] -0+04c <[^>]*> f910 f021 pli \[r0, r1, lsl #2\] -0+050 <[^>]*> f995 f000 pli \[r5\] -0+054 <[^>]*> f995 ffff pli \[r5, #4095\] -0+058 <[^>]*> f915 fcff pli \[r5, #-255\] -0+05c <[^>]*> f99f ffff pli \[pc, #4095\] ; 0000105f <[^>]*> -0+060 <[^>]*> f91f ffff pli \[pc, #-4095\] ; fffff065 <[^>]*> -0+064 <[^>]*> f3af 80f0 dbg #0 -0+068 <[^>]*> f3af 80ff dbg #15 -0+06c <[^>]*> f3bf 8f5f dmb sy -0+070 <[^>]*> f3bf 8f5f dmb sy -0+074 <[^>]*> f3bf 8f4f dsb sy -0+078 <[^>]*> f3bf 8f4f dsb sy -0+07c <[^>]*> f3bf 8f47 dsb un -0+080 <[^>]*> f3bf 8f4e dsb st -0+084 <[^>]*> f3bf 8f46 dsb unst -0+088 <[^>]*> f3bf 8f6f isb sy -0+08c <[^>]*> f3bf 8f6f isb sy -0+090 <[^>]*> fb99 f6fc sdiv r6, r9, ip -0+094 <[^>]*> fb96 f9f3 sdiv r9, r6, r3 -0+098 <[^>]*> fbb6 f9f3 udiv r9, r6, r3 -0+09c <[^>]*> fbb9 f6fc udiv r6, r9, ip -# V7M APSR has the same encoding as V7A CPSR_f -0+0a0 <[^>]*> f3ef 8000 mrs r0, (CPSR|APSR) -0+0a4 <[^>]*> f3ef 8001 mrs r0, IAPSR -0+0a8 <[^>]*> f3ef 8002 mrs r0, EAPSR -0+0ac <[^>]*> f3ef 8003 mrs r0, PSR -0+0b0 <[^>]*> f3ef 8005 mrs r0, IPSR -0+0b4 <[^>]*> f3ef 8006 mrs r0, EPSR -0+0b8 <[^>]*> f3ef 8007 mrs r0, IEPSR -0+0bc <[^>]*> f3ef 8008 mrs r0, MSP -0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP -0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK -0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI -0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK -0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK -0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL -0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR), r0 -0+0dc <[^>]*> f380 8801 msr IAPSR, r0 -0+0e0 <[^>]*> f380 8802 msr EAPSR, r0 -0+0e4 <[^>]*> f380 8803 msr PSR, r0 -0+0e8 <[^>]*> f380 8805 msr IPSR, r0 -0+0ec <[^>]*> f380 8806 msr EPSR, r0 -0+0f0 <[^>]*> f380 8807 msr IEPSR, r0 -0+0f4 <[^>]*> f380 8808 msr MSP, r0 -0+0f8 <[^>]*> f380 8809 msr PSP, r0 -0+0fc <[^>]*> f380 8810 msr PRIMASK, r0 -0+100 <[^>]*> f380 8811 msr BASEPRI, r0 -0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0 -0+108 <[^>]*> f380 8813 msr FAULTMASK, r0 -0+10c <[^>]*> f380 8814 msr CONTROL, r0 diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch7.s b/binutils-2.17/gas/testsuite/gas/arm/arch7.s deleted file mode 100644 index 9b30aa27..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch7.s +++ /dev/null @@ -1,79 +0,0 @@ - # ARMV7 instructions - .text - .arch armv7r -label1: - pli [r6, r8] - pli [r9, r7] - pli [r0, r1, lsl #2] - pli [r5] - pli [r5, #4095] - pli [r5, #-4095] - - dbg #0 - dbg #15 - dmb - dmb sy - dsb - dsb sy - dsb un - dsb st - dsb unst - isb - isb sy - .thumb - .thumb_func -label2: - pli [r6, r8] - pli [r9, r7] - pli [r0, r1, lsl #2] - pli [r5] - pli [r5, #4095] - pli [r5, #-255] - pli [pc, #4095] - pli [pc, #-4095] - - dbg #0 - dbg #15 - dmb - dmb sy - dsb - dsb sy - dsb un - dsb st - dsb unst - isb - isb sy - - sdiv r6, r9, r12 - sdiv r9, r6, r3 - udiv r9, r6, r3 - udiv r6, r9, r12 - .arch armv7m - mrs r0, apsr - mrs r0, iapsr - mrs r0, eapsr - mrs r0, psr - mrs r0, ipsr - mrs r0, epsr - mrs r0, iepsr - mrs r0, msp - mrs r0, psp - mrs r0, primask - mrs r0, basepri - mrs r0, basepri_max - mrs r0, faultmask - mrs r0, control - msr apsr, r0 - msr iapsr, r0 - msr eapsr, r0 - msr psr, r0 - msr ipsr, r0 - msr epsr, r0 - msr iepsr, r0 - msr msp, r0 - msr psp, r0 - msr primask, r0 - msr basepri, r0 - msr basepri_max, r0 - msr faultmask, r0 - msr control, r0 diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.d b/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.d deleted file mode 100644 index b7a3336c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.d +++ /dev/null @@ -1,4 +0,0 @@ -#name: Invalid V7M instructions -#as: -march=armv7m -#error-output: arch7m-bad.l - diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.l b/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.l deleted file mode 100644 index c962dacd..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.l +++ /dev/null @@ -1,5 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:5: Error: selected processor does not support 'A' form of this instruction -- `cpsie a' -[^:]*:6: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie i,#0x10' -[^:]*:7: Error: selected processor does not support `cps #0x10' - diff --git a/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.s b/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.s deleted file mode 100644 index 78ff8649..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arch7m-bad.s +++ /dev/null @@ -1,7 +0,0 @@ - .text - .thumb - .thumb_func -label: - cpsie a - cpsie i, #0x10 - cps #0x10 diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6.d b/binutils-2.17/gas/testsuite/gas/arm/archv6.d deleted file mode 100644 index 1dbaad3a..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6.d +++ /dev/null @@ -1,219 +0,0 @@ -#name: ARM V6 instructions -#as: -march=armv6j -#objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> f102000f ? cps #15 -0+004 <[^>]*> f10c00c0 ? cpsid if -0+008 <[^>]*> f10800c0 ? cpsie if -0+00c <[^>]*> e1942f9f ? ldrex r2, \[r4\] -0+010 <[^>]*> 11984f9f ? ldrexne r4, \[r8\] -0+014 <[^>]*> fc4570c3 ? mcrr2 0, 12, r7, r5, cr3 -0+018 <[^>]*> fc5570c3 ? mrrc2 0, 12, r7, r5, cr3 -0+01c <[^>]*> e6852018 ? pkhbt r2, r5, r8 -0+020 <[^>]*> e6852198 ? pkhbt r2, r5, r8, LSL #3 -0+024 <[^>]*> e6852198 ? pkhbt r2, r5, r8, LSL #3 -0+028 <[^>]*> 06852198 ? pkhbteq r2, r5, r8, LSL #3 -0+02c <[^>]*> e6882015 ? pkhbt r2, r8, r5 -0+030 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, ASR #3 -0+034 <[^>]*> e68521d8 ? pkhtb r2, r5, r8, ASR #3 -0+038 <[^>]*> 068521d8 ? pkhtbeq r2, r5, r8, ASR #3 -0+03c <[^>]*> e6242f17 ? qadd16 r2, r4, r7 -0+040 <[^>]*> 16242f17 ? qadd16ne r2, r4, r7 -0+044 <[^>]*> e6242f97 ? qadd8 r2, r4, r7 -0+048 <[^>]*> 16242f97 ? qadd8ne r2, r4, r7 -0+04c <[^>]*> e6242f37 ? qaddsubx r2, r4, r7 -0+050 <[^>]*> 16242f37 ? qaddsubxne r2, r4, r7 -0+054 <[^>]*> e6242f77 ? qsub16 r2, r4, r7 -0+058 <[^>]*> 16242f77 ? qsub16ne r2, r4, r7 -0+05c <[^>]*> e6242ff7 ? qsub8 r2, r4, r7 -0+060 <[^>]*> 16242ff7 ? qsub8ne r2, r4, r7 -0+064 <[^>]*> e6242f57 ? qsubaddx r2, r4, r7 -0+068 <[^>]*> e6242f57 ? qsubaddx r2, r4, r7 -0+06c <[^>]*> e6bf2f34 ? rev r2, r4 -0+070 <[^>]*> e6bf2fb4 ? rev16 r2, r4 -0+074 <[^>]*> 16bf3fb5 ? rev16ne r3, r5 -0+078 <[^>]*> 16bf3f35 ? revne r3, r5 -0+07c <[^>]*> e6ff2fb4 ? revsh r2, r4 -0+080 <[^>]*> 16ff3fb5 ? revshne r3, r5 -0+084 <[^>]*> f8120a00 ? rfeda r2 -0+088 <[^>]*> f9320a00 ? rfedb r2! -0+08c <[^>]*> f8120a00 ? rfeda r2 -0+090 <[^>]*> f9320a00 ? rfedb r2! -0+094 <[^>]*> f9b20a00 ? rfeib r2! -0+098 <[^>]*> f8920a00 ? rfeia r2 -0+09c <[^>]*> f8920a00 ? rfeia r2 -0+0a0 <[^>]*> f9b20a00 ? rfeib r2! -0+0a4 <[^>]*> e6142f17 ? sadd16 r2, r4, r7 -0+0a8 <[^>]*> 16142f17 ? sadd16ne r2, r4, r7 -0+0ac <[^>]*> e6b42075 ? sxtah r2, r4, r5 -0+0b0 <[^>]*> e6b42475 ? sxtah r2, r4, r5, ROR #8 -0+0b4 <[^>]*> 16b42075 ? sxtahne r2, r4, r5 -0+0b8 <[^>]*> 16b42475 ? sxtahne r2, r4, r5, ROR #8 -0+0bc <[^>]*> e6142f97 ? sadd8 r2, r4, r7 -0+0c0 <[^>]*> 16142f97 ? sadd8ne r2, r4, r7 -0+0c4 <[^>]*> e6842075 ? sxtab16 r2, r4, r5 -0+0c8 <[^>]*> e6842475 ? sxtab16 r2, r4, r5, ROR #8 -0+0cc <[^>]*> 16842075 ? sxtab16ne r2, r4, r5 -0+0d0 <[^>]*> 16842475 ? sxtab16ne r2, r4, r5, ROR #8 -0+0d4 <[^>]*> e6a42075 ? sxtab r2, r4, r5 -0+0d8 <[^>]*> e6a42475 ? sxtab r2, r4, r5, ROR #8 -0+0dc <[^>]*> 16a42075 ? sxtabne r2, r4, r5 -0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ROR #8 -0+0e4 <[^>]*> e6142f37 ? saddaddx r2, r4, r7 -0+0e8 <[^>]*> 16142f37 ? saddaddxne r2, r4, r7 -0+0ec <[^>]*> e6821fb3 ? sel r1, r2, r3 -0+0f0 <[^>]*> 16821fb3 ? selne r1, r2, r3 -0+0f4 <[^>]*> f1010200 ? setend be -0+0f8 <[^>]*> f1010000 ? setend le -0+0fc <[^>]*> e6342f17 ? shadd16 r2, r4, r7 -0+100 <[^>]*> 16342f17 ? shadd16ne r2, r4, r7 -0+104 <[^>]*> e6342f97 ? shadd8 r2, r4, r7 -0+108 <[^>]*> 16342f97 ? shadd8ne r2, r4, r7 -0+10c <[^>]*> e6342f37 ? shaddsubx r2, r4, r7 -0+110 <[^>]*> 16342f37 ? shaddsubxne r2, r4, r7 -0+114 <[^>]*> e6342f77 ? shsub16 r2, r4, r7 -0+118 <[^>]*> 16342f77 ? shsub16ne r2, r4, r7 -0+11c <[^>]*> e6342ff7 ? shsub8 r2, r4, r7 -0+120 <[^>]*> 16342ff7 ? shsub8ne r2, r4, r7 -0+124 <[^>]*> e6342f57 ? shsubaddx r2, r4, r7 -0+128 <[^>]*> 16342f57 ? shsubaddxne r2, r4, r7 -0+12c <[^>]*> e7014312 ? smlad r1, r2, r3, r4 -0+130 <[^>]*> d7014312 ? smladle r1, r2, r3, r4 -0+134 <[^>]*> e7014332 ? smladx r1, r2, r3, r4 -0+138 <[^>]*> d7014332 ? smladxle r1, r2, r3, r4 -0+13c <[^>]*> e7421413 ? smlald r1, r2, r3, r4 -0+140 <[^>]*> d7421413 ? smlaldle r1, r2, r3, r4 -0+144 <[^>]*> e7421433 ? smlaldx r1, r2, r3, r4 -0+148 <[^>]*> d7421433 ? smlaldxle r1, r2, r3, r4 -0+14c <[^>]*> e7014352 ? smlsd r1, r2, r3, r4 -0+150 <[^>]*> d7014352 ? smlsdle r1, r2, r3, r4 -0+154 <[^>]*> e7014372 ? smlsdx r1, r2, r3, r4 -0+158 <[^>]*> d7014372 ? smlsdxle r1, r2, r3, r4 -0+15c <[^>]*> e7421453 ? smlsld r1, r2, r3, r4 -0+160 <[^>]*> d7421453 ? smlsldle r1, r2, r3, r4 -0+164 <[^>]*> e7421473 ? smlsldx r1, r2, r3, r4 -0+168 <[^>]*> d7421473 ? smlsldxle r1, r2, r3, r4 -0+16c <[^>]*> e7514312 ? smmla r1, r2, r3, r4 -0+170 <[^>]*> d7514312 ? smmlale r1, r2, r3, r4 -0+174 <[^>]*> e7514332 ? smmlar r1, r2, r3, r4 -0+178 <[^>]*> d7514332 ? smmlarle r1, r2, r3, r4 -0+17c <[^>]*> e75143d2 ? smmls r1, r2, r3, r4 -0+180 <[^>]*> d75143d2 ? smmlsle r1, r2, r3, r4 -0+184 <[^>]*> e75143f2 ? smmlsr r1, r2, r3, r4 -0+188 <[^>]*> d75143f2 ? smmlsrle r1, r2, r3, r4 -0+18c <[^>]*> e751f312 ? smmul r1, r2, r3 -0+190 <[^>]*> d751f312 ? smmulle r1, r2, r3 -0+194 <[^>]*> e751f332 ? smmulr r1, r2, r3 -0+198 <[^>]*> d751f332 ? smmulrle r1, r2, r3 -0+19c <[^>]*> e701f312 ? smuad r1, r2, r3 -0+1a0 <[^>]*> d701f312 ? smuadle r1, r2, r3 -0+1a4 <[^>]*> e701f332 ? smuadx r1, r2, r3 -0+1a8 <[^>]*> d701f332 ? smuadxle r1, r2, r3 -0+1ac <[^>]*> e701f352 ? smusd r1, r2, r3 -0+1b0 <[^>]*> d701f352 ? smusdle r1, r2, r3 -0+1b4 <[^>]*> e701f372 ? smusdx r1, r2, r3 -0+1b8 <[^>]*> d701f372 ? smusdxle r1, r2, r3 -0+1bc <[^>]*> f8cd0510 ? srsia #16 -0+1c0 <[^>]*> f9ed0510 ? srsib #16! -0+1c4 <[^>]*> e6a01012 ? ssat r1, #1, r2 -0+1c8 <[^>]*> e6a01152 ? ssat r1, #1, r2, ASR #2 -0+1cc <[^>]*> e6a01112 ? ssat r1, #1, r2, LSL #2 -0+1d0 <[^>]*> e6a01f31 ? ssat16 r1, #1, r1 -0+1d4 <[^>]*> d6a01f31 ? ssat16le r1, #1, r1 -0+1d8 <[^>]*> e6142f77 ? ssub16 r2, r4, r7 -0+1dc <[^>]*> 16142f77 ? ssub16ne r2, r4, r7 -0+1e0 <[^>]*> e6142ff7 ? ssub8 r2, r4, r7 -0+1e4 <[^>]*> 16142ff7 ? ssub8ne r2, r4, r7 -0+1e8 <[^>]*> e6142f57 ? ssubaddx r2, r4, r7 -0+1ec <[^>]*> 16142f57 ? ssubaddxne r2, r4, r7 -0+1f0 <[^>]*> e1831f92 ? strex r1, r2, \[r3\] -0+1f4 <[^>]*> 11831f92 ? strexne r1, r2, \[r3\] -0+1f8 <[^>]*> e6bf2075 ? sxth r2,r5 -0+1fc <[^>]*> e6bf2475 ? sxth r2,r5, ROR #8 -0+200 <[^>]*> 16bf2075 ? sxthne r2,r5 -0+204 <[^>]*> 16bf2475 ? sxthne r2,r5, ROR #8 -0+208 <[^>]*> e68f2075 ? sxtb16 r2,r5 -0+20c <[^>]*> e68f2475 ? sxtb16 r2,r5, ROR #8 -0+210 <[^>]*> 168f2075 ? sxtb16ne r2,r5 -0+214 <[^>]*> 168f2475 ? sxtb16ne r2,r5, ROR #8 -0+218 <[^>]*> e6af2075 ? sxtb r2,r5 -0+21c <[^>]*> e6af2475 ? sxtb r2,r5, ROR #8 -0+220 <[^>]*> 16af2075 ? sxtbne r2,r5 -0+224 <[^>]*> 16af2475 ? sxtbne r2,r5, ROR #8 -0+228 <[^>]*> e6542f17 ? uadd16 r2, r4, r7 -0+22c <[^>]*> 16542f17 ? uadd16ne r2, r4, r7 -0+230 <[^>]*> e6f32075 ? uxtah r2, r3, r5 -0+234 <[^>]*> e6f32475 ? uxtah r2, r3, r5, ROR #8 -0+238 <[^>]*> 16f32075 ? uxtahne r2, r3, r5 -0+23c <[^>]*> 16f32475 ? uxtahne r2, r3, r5, ROR #8 -0+240 <[^>]*> e6542f97 ? uadd8 r2, r4, r7 -0+244 <[^>]*> 16542f97 ? uadd8ne r2, r4, r7 -0+248 <[^>]*> e6c32075 ? uxtab16 r2, r3, r5 -0+24c <[^>]*> e6c32475 ? uxtab16 r2, r3, r5, ROR #8 -0+250 <[^>]*> 16c32075 ? uxtab16ne r2, r3, r5 -0+254 <[^>]*> 16c32475 ? uxtab16ne r2, r3, r5, ROR #8 -0+258 <[^>]*> e6e32075 ? uxtab r2, r3, r5 -0+25c <[^>]*> e6e32475 ? uxtab r2, r3, r5, ROR #8 -0+260 <[^>]*> 16e32075 ? uxtabne r2, r3, r5 -0+264 <[^>]*> 16e32475 ? uxtabne r2, r3, r5, ROR #8 -0+268 <[^>]*> e6542f37 ? uaddsubx r2, r4, r7 -0+26c <[^>]*> 16542f37 ? uaddsubxne r2, r4, r7 -0+270 <[^>]*> e6742f17 ? uhadd16 r2, r4, r7 -0+274 <[^>]*> 16742f17 ? uhadd16ne r2, r4, r7 -0+278 <[^>]*> e6742f97 ? uhadd8 r2, r4, r7 -0+27c <[^>]*> 16742f97 ? uhadd8ne r2, r4, r7 -0+280 <[^>]*> e6742f37 ? uhaddsubx r2, r4, r7 -0+284 <[^>]*> 16742f37 ? uhaddsubxne r2, r4, r7 -0+288 <[^>]*> e6742f77 ? uhsub16 r2, r4, r7 -0+28c <[^>]*> 16742f77 ? uhsub16ne r2, r4, r7 -0+290 <[^>]*> e6742ff7 ? uhsub8 r2, r4, r7 -0+294 <[^>]*> 16742ff7 ? uhsub8ne r2, r4, r7 -0+298 <[^>]*> e6742f57 ? uhsubaddx r2, r4, r7 -0+29c <[^>]*> 16742f57 ? uhsubaddxne r2, r4, r7 -0+2a0 <[^>]*> e0421493 ? umaal r1, r2, r3, r4 -0+2a4 <[^>]*> d0421493 ? umaalle r1, r2, r3, r4 -0+2a8 <[^>]*> e6642f17 ? uqadd16 r2, r4, r7 -0+2ac <[^>]*> 16642f17 ? uqadd16ne r2, r4, r7 -0+2b0 <[^>]*> e6642f97 ? uqadd8 r2, r4, r7 -0+2b4 <[^>]*> 16642f97 ? uqadd8ne r2, r4, r7 -0+2b8 <[^>]*> e6642f37 ? uqaddsubx r2, r4, r7 -0+2bc <[^>]*> 16642f37 ? uqaddsubxne r2, r4, r7 -0+2c0 <[^>]*> e6642f77 ? uqsub16 r2, r4, r7 -0+2c4 <[^>]*> 16642f77 ? uqsub16ne r2, r4, r7 -0+2c8 <[^>]*> e6642ff7 ? uqsub8 r2, r4, r7 -0+2cc <[^>]*> 16642ff7 ? uqsub8ne r2, r4, r7 -0+2d0 <[^>]*> e6642f57 ? uqsubaddx r2, r4, r7 -0+2d4 <[^>]*> 16642f57 ? uqsubaddxne r2, r4, r7 -0+2d8 <[^>]*> e781f312 ? usad8 r1, r2, r3 -0+2dc <[^>]*> 1781f312 ? usad8ne r1, r2, r3 -0+2e0 <[^>]*> e7814312 ? usada8 r1, r2, r3, r4 -0+2e4 <[^>]*> 17814312 ? usada8ne r1, r2, r3, r4 -0+2e8 <[^>]*> e6ef1012 ? usat r1, #15, r2 -0+2ec <[^>]*> e6ef1252 ? usat r1, #15, r2, ASR #4 -0+2f0 <[^>]*> e6ef1212 ? usat r1, #15, r2, LSL #4 -0+2f4 <[^>]*> e6ef1f32 ? usat16 r1, #15, r2 -0+2f8 <[^>]*> d6ef1f32 ? usat16le r1, #15, r2 -0+2fc <[^>]*> d6ef1012 ? usatle r1, #15, r2 -0+300 <[^>]*> d6ef1252 ? usatle r1, #15, r2, ASR #4 -0+304 <[^>]*> d6ef1212 ? usatle r1, #15, r2, LSL #4 -0+308 <[^>]*> e6542f77 ? usub16 r2, r4, r7 -0+30c <[^>]*> 16542f77 ? usub16ne r2, r4, r7 -0+310 <[^>]*> e6542ff7 ? usub8 r2, r4, r7 -0+314 <[^>]*> 16542ff7 ? usub8ne r2, r4, r7 -0+318 <[^>]*> e6542f57 ? usubaddx r2, r4, r7 -0+31c <[^>]*> 16542f57 ? usubaddxne r2, r4, r7 -0+320 <[^>]*> e6ff2075 ? uxth r2,r5 -0+324 <[^>]*> e6ff2475 ? uxth r2,r5, ROR #8 -0+328 <[^>]*> 16ff2075 ? uxthne r2,r5 -0+32c <[^>]*> 16ff2475 ? uxthne r2,r5, ROR #8 -0+330 <[^>]*> e6cf2075 ? uxtb16 r2,r5 -0+334 <[^>]*> e6cf2475 ? uxtb16 r2,r5, ROR #8 -0+338 <[^>]*> 16cf2075 ? uxtb16ne r2,r5 -0+33c <[^>]*> 16cf2475 ? uxtb16ne r2,r5, ROR #8 -0+340 <[^>]*> e6ef2075 ? uxtb r2,r5 -0+344 <[^>]*> e6ef2475 ? uxtb r2,r5, ROR #8 -0+348 <[^>]*> 16ef2075 ? uxtbne r2,r5 -0+34c <[^>]*> 16ef2475 ? uxtbne r2,r5, ROR #8 diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6.s b/binutils-2.17/gas/testsuite/gas/arm/archv6.s deleted file mode 100644 index 50378b7c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6.s +++ /dev/null @@ -1,216 +0,0 @@ -.text -.align 0 - -label: - cps #15 - cpsid if - cpsie if - ldrex r2, [r4] - ldrexne r4, [r8] - mcrr2 p0, 12, r7, r5, c3 - mrrc2 p0, 12, r7, r5, c3 - pkhbt r2, r5, r8 - pkhbt r2, r5, r8, LSL #3 - pkhbtal r2, r5, r8, LSL #3 - pkhbteq r2, r5, r8, LSL #3 - pkhtb r2, r5, r8 @ Equivalent to pkhbt r2, r8, r5. - pkhtb r2, r5, r8, ASR #3 - pkhtbal r2, r5, r8, ASR #3 - pkhtbeq r2, r5, r8, ASR #3 - qadd16 r2, r4, r7 - qadd16ne r2, r4, r7 - qadd8 r2, r4, r7 - qadd8ne r2, r4, r7 - qaddsubx r2, r4, r7 - qaddsubxne r2, r4, r7 - qsub16 r2, r4, r7 - qsub16ne r2, r4, r7 - qsub8 r2, r4, r7 - qsub8ne r2, r4, r7 - qsubaddx r2, r4, r7 - qsubaddx r2, r4, r7 - rev r2, r4 - rev16 r2, r4 - rev16ne r3, r5 - revne r3, r5 - revsh r2, r4 - revshne r3, r5 - rfeda r2 - rfedb r2! - rfeea r2 - rfeed r2! - rfefa r2! - rfefd r2 - rfeia r2 - rfeib r2! - sadd16 r2, r4, r7 - sadd16ne r2, r4, r7 - sxtah r2, r4, r5 - sxtah r2, r4, r5, ROR #8 - sxtahne r2, r4, r5 - sxtahne r2, r4, r5, ROR #8 - sadd8 r2, r4, r7 - sadd8ne r2, r4, r7 - sxtab16 r2, r4, r5 - sxtab16 r2, r4, r5, ROR #8 - sxtab16ne r2, r4, r5 - sxtab16ne r2, r4, r5, ROR #8 - sxtab r2, r4, r5 - sxtab r2, r4, r5, ROR #8 - sxtabne r2, r4, r5 - sxtabne r2, r4, r5, ROR #8 - saddsubx r2, r4, r7 - saddsubxne r2, r4, r7 - sel r1, r2, r3 - selne r1, r2, r3 - setend be - setend le - shadd16 r2, r4, r7 - shadd16ne r2, r4, r7 - shadd8 r2, r4, r7 - shadd8ne r2, r4, r7 - shaddsubx r2, r4, r7 - shaddsubxne r2, r4, r7 - shsub16 r2, r4, r7 - shsub16ne r2, r4, r7 - shsub8 r2, r4, r7 - shsub8ne r2, r4, r7 - shsubaddx r2, r4, r7 - shsubaddxne r2, r4, r7 - smlad r1,r2,r3,r4 - smladle r1,r2,r3,r4 - smladx r1,r2,r3,r4 - smladxle r1,r2,r3,r4 - smlald r1,r2,r3,r4 - smlaldle r1,r2,r3,r4 - smlaldx r1,r2,r3,r4 - smlaldxle r1,r2,r3,r4 - smlsd r1,r2,r3,r4 - smlsdle r1,r2,r3,r4 - smlsdx r1,r2,r3,r4 - smlsdxle r1,r2,r3,r4 - smlsld r1,r2,r3,r4 - smlsldle r1,r2,r3,r4 - smlsldx r1,r2,r3,r4 - smlsldxle r1,r2,r3,r4 - smmla r1,r2,r3,r4 - smmlale r1,r2,r3,r4 - smmlar r1,r2,r3,r4 - smmlarle r1,r2,r3,r4 - smmls r1,r2,r3,r4 - smmlsle r1,r2,r3,r4 - smmlsr r1,r2,r3,r4 - smmlsrle r1,r2,r3,r4 - smmul r1,r2,r3 - smmulle r1,r2,r3 - smmulr r1,r2,r3 - smmulrle r1,r2,r3 - smuad r1,r2,r3 - smuadle r1,r2,r3 - smuadx r1,r2,r3 - smuadxle r1,r2,r3 - smusd r1,r2,r3 - smusdle r1,r2,r3 - smusdx r1,r2,r3 - smusdxle r1,r2,r3 - srsia #16 - srsib #16! - ssat r1, #1, r2 - ssat r1, #1, r2, ASR #2 - ssat r1, #1, r2, LSL #2 - ssat16 r1, #1, r1 - ssat16le r1, #1, r1 - ssub16 r2, r4, r7 - ssub16ne r2, r4, r7 - ssub8 r2, r4, r7 - ssub8ne r2, r4, r7 - ssubaddx r2, r4, r7 - ssubaddxne r2, r4, r7 - strex r1, r2, [r3] - strexne r1, r2, [r3] - sxth r2, r5 - sxth r2, r5, ROR #8 - sxthne r2, r5 - sxthne r2, r5, ROR #8 - sxtb16 r2, r5 - sxtb16 r2, r5, ROR #8 - sxtb16ne r2, r5 - sxtb16ne r2, r5, ROR #8 - sxtb r2, r5 - sxtb r2, r5, ROR #8 - sxtbne r2, r5 - sxtbne r2, r5, ROR #8 - uadd16 r2, r4, r7 - uadd16ne r2, r4, r7 - uxtah r2, r3, r5 - uxtah r2, r3, r5, ROR #8 - uxtahne r2, r3, r5 - uxtahne r2, r3, r5, ROR #8 - uadd8 r2, r4, r7 - uadd8ne r2, r4, r7 - uxtab16 r2, r3, r5 - uxtab16 r2, r3, r5, ROR #8 - uxtab16ne r2, r3, r5 - uxtab16ne r2, r3, r5, ROR #8 - uxtab r2, r3, r5 - uxtab r2, r3, r5, ROR #8 - uxtabne r2, r3, r5 - uxtabne r2, r3, r5, ROR #8 - uaddsubx r2, r4, r7 - uaddsubxne r2, r4, r7 - uhadd16 r2, r4, r7 - uhadd16ne r2, r4, r7 - uhadd8 r2, r4, r7 - uhadd8ne r2, r4, r7 - uhaddsubx r2, r4, r7 - uhaddsubxne r2, r4, r7 - uhsub16 r2, r4, r7 - uhsub16ne r2, r4, r7 - uhsub8 r2, r4, r7 - uhsub8ne r2, r4, r7 - uhsubaddx r2, r4, r7 - uhsubaddxne r2, r4, r7 - umaal r1, r2, r3, r4 - umaalle r1, r2, r3, r4 - uqadd16 r2, r4, r7 - uqadd16ne r2, r4, r7 - uqadd8 r2, r4, r7 - uqadd8ne r2, r4, r7 - uqaddsubx r2, r4, r7 - uqaddsubxne r2, r4, r7 - uqsub16 r2, r4, r7 - uqsub16ne r2, r4, r7 - uqsub8 r2, r4, r7 - uqsub8ne r2, r4, r7 - uqsubaddx r2, r4, r7 - uqsubaddxne r2, r4, r7 - usad8 r1, r2, r3 - usad8ne r1, r2, r3 - usada8 r1, r2, r3, r4 - usada8ne r1, r2, r3, r4 - usat r1, #15, r2 - usat r1, #15, r2, ASR #4 - usat r1, #15, r2, LSL #4 - usat16 r1, #15, r2 - usat16le r1, #15, r2 - usatle r1, #15, r2 - usatle r1, #15, r2, ASR #4 - usatle r1, #15, r2, LSL #4 - usub16 r2, r4, r7 - usub16ne r2, r4, r7 - usub8 r2, r4, r7 - usub8ne r2, r4, r7 - usubaddx r2, r4, r7 - usubaddxne r2, r4, r7 - uxth r2, r5 - uxth r2, r5, ROR #8 - uxthne r2, r5 - uxthne r2, r5, ROR #8 - uxtb16 r2, r5 - uxtb16 r2, r5, ROR #8 - uxtb16ne r2, r5 - uxtb16ne r2, r5, ROR #8 - uxtb r2, r5 - uxtb r2, r5, ROR #8 - uxtbne r2, r5 - uxtbne r2, r5, ROR #8 diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.d b/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.d deleted file mode 100644 index 9b8e1b90..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: Invalid V6T2 instructions -#as: -march=armv6t2 -#error-output: archv6t2-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.l b/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.l deleted file mode 100644 index 0f00db37..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.l +++ /dev/null @@ -1,40 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:6: Error: r15 not allowed here -- `bfc pc,#0,#1' -[^:]*:7: Error: r15 not allowed here -- `bfi pc,r0,#0,#1' -[^:]*:8: Error: r15 not allowed here -- `movw pc,#0' -[^:]*:9: Error: r15 not allowed here -- `movt pc,#0' -[^:]*:12: Error: immediate value out of range -- `bfc r0,#0,#0' -[^:]*:13: Error: immediate value out of range -- `bfc r0,#32,#0' -[^:]*:14: Error: immediate value out of range -- `bfc r0,#0,#33' -[^:]*:15: Error: immediate value out of range -- `bfc r0,#33,#1' -[^:]*:16: Error: immediate value out of range -- `bfc r0,#32,#1' -[^:]*:17: Error: bit-field extends past end of register -- `bfc r0,#28,#10' -[^:]*:19: Error: immediate value out of range -- `bfi r0,r1,#0,#0' -[^:]*:20: Error: immediate value out of range -- `bfi r0,r1,#32,#0' -[^:]*:21: Error: immediate value out of range -- `bfi r0,r1,#0,#33' -[^:]*:22: Error: immediate value out of range -- `bfi r0,r1,#33,#1' -[^:]*:23: Error: immediate value out of range -- `bfi r0,r1,#32,#1' -[^:]*:24: Error: bit-field extends past end of register -- `bfi r0,r1,#28,#10' -[^:]*:26: Error: immediate value out of range -- `sbfx r0,r1,#0,#0' -[^:]*:27: Error: immediate value out of range -- `sbfx r0,r1,#32,#0' -[^:]*:28: Error: immediate value out of range -- `sbfx r0,r1,#0,#33' -[^:]*:29: Error: immediate value out of range -- `sbfx r0,r1,#33,#1' -[^:]*:30: Error: immediate value out of range -- `sbfx r0,r1,#32,#1' -[^:]*:31: Error: bit-field extends past end of register -- `sbfx r0,r1,#28,#10' -[^:]*:33: Error: immediate value out of range -- `ubfx r0,r1,#0,#0' -[^:]*:34: Error: immediate value out of range -- `ubfx r0,r1,#32,#0' -[^:]*:35: Error: immediate value out of range -- `ubfx r0,r1,#0,#33' -[^:]*:36: Error: immediate value out of range -- `ubfx r0,r1,#33,#1' -[^:]*:37: Error: immediate value out of range -- `ubfx r0,r1,#32,#1' -[^:]*:38: Error: bit-field extends past end of register -- `ubfx r0,r1,#28,#10' -[^:]*:41: Error: immediate value out of range -- `bfi r0,#1,#2,#3' -[^:]*:44: Error: immediate value out of range -- `movt r0,#65537' -[^:]*:45: Error: immediate value out of range -- `movw r0,#65537' -[^:]*:46: Error: immediate value out of range -- `movt r0,#-1' -[^:]*:47: Error: immediate value out of range -- `movw r0,#-1' -[^:]*:50: Warning: destination register same as write-back base -[^:]*:51: Warning: destination register same as write-back base -[^:]*:52: Warning: destination register same as write-back base -[^:]*:53: Warning: source register same as write-back base -[^:]*:59: Error: instruction does not accept this addressing mode -- `ldrex r0,r2' -[^:]*:60: Error: instruction does not accept this addressing mode -- `strex r1,r0,r2' diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.s b/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.s deleted file mode 100644 index af139727..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6t2-bad.s +++ /dev/null @@ -1,61 +0,0 @@ - @ We do not bother testing simple cases, e.g. immediates where - @ registers belong, trailing junk at end of line. - .text -x: - @ pc not allowed - bfc pc,#0,#1 - bfi pc,r0,#0,#1 - movw pc,#0 - movt pc,#0 - - @ bitfield range limits - bfc r0,#0,#0 - bfc r0,#32,#0 - bfc r0,#0,#33 - bfc r0,#33,#1 - bfc r0,#32,#1 - bfc r0,#28,#10 - - bfi r0,r1,#0,#0 - bfi r0,r1,#32,#0 - bfi r0,r1,#0,#33 - bfi r0,r1,#33,#1 - bfi r0,r1,#32,#1 - bfi r0,r1,#28,#10 - - sbfx r0,r1,#0,#0 - sbfx r0,r1,#32,#0 - sbfx r0,r1,#0,#33 - sbfx r0,r1,#33,#1 - sbfx r0,r1,#32,#1 - sbfx r0,r1,#28,#10 - - ubfx r0,r1,#0,#0 - ubfx r0,r1,#32,#0 - ubfx r0,r1,#0,#33 - ubfx r0,r1,#33,#1 - ubfx r0,r1,#32,#1 - ubfx r0,r1,#28,#10 - - @ bfi accepts only #0 in Rm position - bfi r0,#1,#2,#3 - - @ mov16 range limits - movt r0,#65537 - movw r0,#65537 - movt r0,#-1 - movw r0,#-1 - - @ ldsttv4 Rd == Rn (warning) - ldrht r0,[r0] - ldrsbt r0,[r0] - ldrsht r0,[r0] - strht r0,[r0] - - @ Bug reported by user. GAS used to issue an error message - @ "r15 not allowed here" for these two instructions because - @ it thought that the "r2" operand was a PC-relative branch - @ to a label called "r2". - ldrex r0, r2 - strex r1, r0, r2 -
\ No newline at end of file diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6t2.d b/binutils-2.17/gas/testsuite/gas/arm/archv6t2.d deleted file mode 100644 index 8e8b0387..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6t2.d +++ /dev/null @@ -1,51 +0,0 @@ -#name: ARM V6T2 instructions -#as: -march=armv6t2 -#objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]+> e7c00010 bfi r0, r0, #0, #1 -0+04 <[^>]+> 17c00010 bfine r0, r0, #0, #1 -0+08 <[^>]+> e7c09010 bfi r9, r0, #0, #1 -0+0c <[^>]+> e7c00019 bfi r0, r9, #0, #1 -0+10 <[^>]+> e7d10010 bfi r0, r0, #0, #18 -0+14 <[^>]+> e7d10890 bfi r0, r0, #17, #1 -0+18 <[^>]+> e7c0001f bfc r0, #0, #1 -0+1c <[^>]+> e7c0001f bfc r0, #0, #1 -0+20 <[^>]+> 17c0001f bfcne r0, #0, #1 -0+24 <[^>]+> e7c0901f bfc r9, #0, #1 -0+28 <[^>]+> e7d1001f bfc r0, #0, #18 -0+2c <[^>]+> e7d1089f bfc r0, #17, #1 -0+30 <[^>]+> e7a00050 sbfx r0, r0, #0, #1 -0+34 <[^>]+> 17a00050 sbfxne r0, r0, #0, #1 -0+38 <[^>]+> e7e00050 ubfx r0, r0, #0, #1 -0+3c <[^>]+> e7a09050 sbfx r9, r0, #0, #1 -0+40 <[^>]+> e7a00059 sbfx r0, r9, #0, #1 -0+44 <[^>]+> e7a008d0 sbfx r0, r0, #17, #1 -0+48 <[^>]+> e7b10050 sbfx r0, r0, #0, #18 -0+4c <[^>]+> e3ff0f30 rbit r0, r0 -0+50 <[^>]+> 13ff0f30 rbitne r0, r0 -0+54 <[^>]+> e3ff9f30 rbit r9, r0 -0+58 <[^>]+> e3ff0f39 rbit r0, r9 -0+5c <[^>]+> e0600090 mls r0, r0, r0, r0 -0+60 <[^>]+> 10600090 mlsne r0, r0, r0, r0 -0+64 <[^>]+> e0690090 mls r9, r0, r0, r0 -0+68 <[^>]+> e0600099 mls r0, r9, r0, r0 -0+6c <[^>]+> e0600990 mls r0, r0, r9, r0 -0+70 <[^>]+> e0609090 mls r0, r0, r0, r9 -0+74 <[^>]+> e3000000 movw r0, #0 ; 0x0 -0+78 <[^>]+> e3400000 movt r0, #0 ; 0x0 -0+7c <[^>]+> 13000000 movwne r0, #0 ; 0x0 -0+80 <[^>]+> e3009000 movw r9, #0 ; 0x0 -0+84 <[^>]+> e3000999 movw r0, #2457 ; 0x999 -0+88 <[^>]+> e3090000 movw r0, #36864 ; 0x9000 -0+8c <[^>]+> e0f900b0 ldrht r0, \[r9\] -0+90 <[^>]+> e0f900f0 ldrsht r0, \[r9\] -0+94 <[^>]+> e0f900d0 ldrsbt r0, \[r9\] -0+98 <[^>]+> e0e900b0 strht r0, \[r9\] -0+9c <[^>]+> 10f900b0 ldrneht r0, \[r9\] -0+a0 <[^>]+> e0b090b9 ldrht r9, \[r0\], r9 -0+a4 <[^>]+> e03090b9 ldrht r9, \[r0\], -r9 -0+a8 <[^>]+> e0f099b9 ldrht r9, \[r0\], #153 -0+ac <[^>]+> e07099b9 ldrht r9, \[r0\], #-153 diff --git a/binutils-2.17/gas/testsuite/gas/arm/archv6t2.s b/binutils-2.17/gas/testsuite/gas/arm/archv6t2.s deleted file mode 100644 index 292f11cf..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/archv6t2.s +++ /dev/null @@ -1,55 +0,0 @@ - .text -x: - bfi r0, r0, #0, #1 - bfine r0, r0, #0, #1 - - bfi r9, r0, #0, #1 - bfi r0, r9, #0, #1 - bfi r0, r0, #0, #18 - bfi r0, r0, #17, #1 - - bfi r0, #0, #0, #1 - bfc r0, #0, #1 - bfcne r0, #0, #1 - bfc r9, #0, #1 - bfc r0, #0, #18 - bfc r0, #17, #1 - - sbfx r0, r0, #0, #1 - sbfxne r0, r0, #0, #1 - ubfx r0, r0, #0, #1 - sbfx r9, r0, #0, #1 - sbfx r0, r9, #0, #1 - sbfx r0, r0, #17, #1 - sbfx r0, r0, #0, #18 - - rbit r0, r0 - rbitne r0, r0 - rbit r9, r0 - rbit r0, r9 - - mls r0, r0, r0, r0 - mlsne r0, r0, r0, r0 - mls r9, r0, r0, r0 - mls r0, r9, r0, r0 - mls r0, r0, r9, r0 - mls r0, r0, r0, r9 - - movw r0, #0 - movt r0, #0 - movwne r0, #0 - movw r9, #0 - movw r0, #0x0999 - movw r0, #0x9000 - - @ for these, we must avoid write-back warnings - ldrht r0, [r9] - ldrsht r0, [r9] - ldrsbt r0, [r9] - strht r0, [r9] - ldrneht r0, [r9] - - ldrht r9, [r0], r9 - ldrht r9, [r0], -r9 - ldrht r9, [r0], #0x99 - ldrht r9, [r0], #-0x99 diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm.exp b/binutils-2.17/gas/testsuite/gas/arm/arm.exp deleted file mode 100644 index 56aef3b8..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm.exp +++ /dev/null @@ -1,7 +0,0 @@ -# -# Some ARM tests -# - -if {[istarget *arm*-*-*] || [istarget *xscale*-*-*]} { - run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] -} diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.d b/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.d deleted file mode 100644 index 29449b22..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.d +++ /dev/null @@ -1,3 +0,0 @@ -# name: ARM 3 errors -# as: -mcpu=arm3 -# error-output: arm3-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.l b/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.l deleted file mode 100644 index d55a9b61..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.l +++ /dev/null @@ -1,3 +0,0 @@ -.*arm3-bad.s: Assembler messages: -.*arm3-bad.s:4: Error: Rn must not overlap other operands -- `swp r0,r1,\[r0\]' -.*arm3-bad.s:5: Error: Rn must not overlap other operands -- `swp r1,r0,\[r0\]' diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.s b/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.s deleted file mode 100644 index d3415a04..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm3-bad.s +++ /dev/null @@ -1,7 +0,0 @@ - .text - .align 0 -l: - swp r0, r1, [r0] - swp r1, r0, [r0] - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm3.d b/binutils-2.17/gas/testsuite/gas/arm/arm3.d deleted file mode 100644 index 06323b1c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm3.d +++ /dev/null @@ -1,11 +0,0 @@ -# name: ARM 3 instructions -# as: -mcpu=arm3 -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+0 <[^>]*> e1080091 ? swp r0, r1, \[r8\] -0+4 <[^>]*> e1423093 ? swpb r3, r3, \[r2\] -0+8 <[^>]*> a1454091 ? swpgeb r4, r1, \[r5\] -0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm3.s b/binutils-2.17/gas/testsuite/gas/arm/arm3.s deleted file mode 100644 index b3fd794c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm3.s +++ /dev/null @@ -1,7 +0,0 @@ - .text - .align 0 -l: - swp r0, r1, [r8] - swpb r3, r3, [r2] - swpgeb r4, r1, [r5] - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm6.d b/binutils-2.17/gas/testsuite/gas/arm/arm6.d deleted file mode 100644 index 3fc0de81..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm6.d +++ /dev/null @@ -1,19 +0,0 @@ -# name: ARM 6 instructions -# as: -mcpu=arm6 -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]+> e10f8000 ? mrs r8, CPSR -0+04 <[^>]+> e14f2000 ? mrs r2, SPSR -0+08 <[^>]+> e129f001 ? msr CPSR_fc, r1 -0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000 -0+10 <[^>]+> e168f008 ? msr SPSR_f, r8 -0+14 <[^>]+> e169f009 ? msr SPSR_fc, r9 -0+18 <[^>]+> e10f8000 ? mrs r8, CPSR -0+1c <[^>]+> e14f2000 ? mrs r2, SPSR -0+20 <[^>]+> e129f001 ? msr CPSR_fc, r1 -0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000 -0+28 <[^>]+> e168f008 ? msr SPSR_f, r8 -0+2c <[^>]+> e169f009 ? msr SPSR_fc, r9 diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm6.s b/binutils-2.17/gas/testsuite/gas/arm/arm6.s deleted file mode 100644 index 1883ebad..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm6.s +++ /dev/null @@ -1,18 +0,0 @@ - .text - .align 0 -l: - mrs r8, cpsr - mrs r2, spsr - - msr cpsr, r1 - msrne cpsr_flg, #0xf0000000 - msr spsr_flg, r8 - msr spsr_all, r9 - - mrs r8, CPSR - mrs r2, SPSR - - msr CPSR, r1 - msrne CPSR_flg, #0xf0000000 - msr SPSR_flg, r8 - msr SPSR_all, r9 diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm7dm.d b/binutils-2.17/gas/testsuite/gas/arm/arm7dm.d deleted file mode 100644 index ef47ca6c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm7dm.d +++ /dev/null @@ -1,19 +0,0 @@ -# name: ARM 7DM instructions -# as: -mcpu=arm7dm -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]+> e0c10392 ? smull r0, r1, r2, r3 -0+04 <[^>]+> e0810392 ? umull r0, r1, r2, r3 -0+08 <[^>]+> e0e10392 ? smlal r0, r1, r2, r3 -0+0c <[^>]+> e0a10394 ? umlal r0, r1, r4, r3 -0+10 <[^>]+> 10c10493 ? smullne r0, r1, r3, r4 -0+14 <[^>]+> e0d01b99 ? smulls r1, r0, r9, fp -0+18 <[^>]+> 00b92994 ? umlaleqs r2, r9, r4, r9 -0+1c <[^>]+> a0eaee98 ? smlalge lr, sl, r8, lr -0+20 <[^>]+> e322f000 ? msr CPSR_x, #0 ; 0x0 -0+24 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+28 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+2c <[^>]+> e1a00000 ? nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm7dm.s b/binutils-2.17/gas/testsuite/gas/arm/arm7dm.s deleted file mode 100644 index ee62e8c8..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm7dm.s +++ /dev/null @@ -1,20 +0,0 @@ - .text - .align 0 -l: - smull r0, r1, r2, r3 - umull r0, r1, r2, r3 - smlal r0, r1, r2, r3 - umlal r0, r1, r4, r3 - - smullne r0, r1, r3, r4 - smulls r1, r0, r9, r11 - umlaleqs r2, r9, r4, r9 - smlalge r14, r10, r8, r14 - - @ This used to be illegal, but rev 2 of the ARM ARM allows it. - msr CPSR_x, #0 - - @ padding for a.out's sake - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm7t.d b/binutils-2.17/gas/testsuite/gas/arm/arm7t.d deleted file mode 100644 index 17e4e9d4..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm7t.d +++ /dev/null @@ -1,70 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM arm7t -#as: -mcpu=arm7t -EL - -# Test the halfword and signextend memory transfers: - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> e1d100b0 ? ldrh r0, \[r1\] -0+04 <[^>]*> e1f100b0 ? ldrh r0, \[r1\]! -0+08 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] -0+0c <[^>]*> e1b100b2 ? ldrh r0, \[r1, r2\]! -0+10 <[^>]*> e1d100bc ? ldrh r0, \[r1, #12\] -0+14 <[^>]*> e1f100bc ? ldrh r0, \[r1, #12\]! -0+18 <[^>]*> e15100bc ? ldrh r0, \[r1, #-12\] -0+1c <[^>]*> e09100b2 ? ldrh r0, \[r1\], r2 -0+20 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 -0+24 <[^>]*> e1df0bb4 ? ldrh r0, \[pc, #180\] ; 0+e0 <[^>]*> -0+28 <[^>]*> e1df0abc ? ldrh r0, \[pc, #172\] ; 0+dc <[^>]*> -0+2c <[^>]*> e1c100b0 ? strh r0, \[r1\] -0+30 <[^>]*> e1e100b0 ? strh r0, \[r1\]! -0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\] -0+38 <[^>]*> e1a100b2 ? strh r0, \[r1, r2\]! -0+3c <[^>]*> e1c100bc ? strh r0, \[r1, #12\] -0+40 <[^>]*> e1e100bc ? strh r0, \[r1, #12\]! -0+44 <[^>]*> e14100bc ? strh r0, \[r1, #-12\] -0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2 -0+4c <[^>]*> e1cf08b8 ? strh r0, \[pc, #136\] ; 0+dc <[^>]*> -0+50 <[^>]*> e1d100d0 ? ldrsb r0, \[r1\] -0+54 <[^>]*> e1f100d0 ? ldrsb r0, \[r1\]! -0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] -0+5c <[^>]*> e1b100d2 ? ldrsb r0, \[r1, r2\]! -0+60 <[^>]*> e1d100dc ? ldrsb r0, \[r1, #12\] -0+64 <[^>]*> e1f100dc ? ldrsb r0, \[r1, #12\]! -0+68 <[^>]*> e15100dc ? ldrsb r0, \[r1, #-12\] -0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2 -0+70 <[^>]*> e3a000de ? mov r0, #222 ; 0xde -0+74 <[^>]*> e1df06d0 ? ldrsb r0, \[pc, #96\] ; 0+dc <[^>]*> -0+78 <[^>]*> e1d100f0 ? ldrsh r0, \[r1\] -0+7c <[^>]*> e1f100f0 ? ldrsh r0, \[r1\]! -0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] -0+84 <[^>]*> e1b100f2 ? ldrsh r0, \[r1, r2\]! -0+88 <[^>]*> e1d100fc ? ldrsh r0, \[r1, #12\] -0+8c <[^>]*> e1f100fc ? ldrsh r0, \[r1, #12\]! -0+90 <[^>]*> e15100fc ? ldrsh r0, \[r1, #-12\] -0+94 <[^>]*> e09100f2 ? ldrsh r0, \[r1\], r2 -0+98 <[^>]*> e3a00cff ? mov r0, #65280 ; 0xff00 -0+9c <[^>]*> e1df03fc ? ldrsh r0, \[pc, #60\] ; 0+e0 <[^>]*> -0+a0 <[^>]*> e1df03f4 ? ldrsh r0, \[pc, #52\] ; 0+dc <[^>]*> -0+a4 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\] -0+a8 <[^>]*> 119100b2 ? ldrneh r0, \[r1, r2\] -0+ac <[^>]*> 819100b2 ? ldrhih r0, \[r1, r2\] -0+b0 <[^>]*> b19100b2 ? ldrlth r0, \[r1, r2\] -0+b4 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\] -0+b8 <[^>]*> 119100f2 ? ldrnesh r0, \[r1, r2\] -0+bc <[^>]*> 819100f2 ? ldrhish r0, \[r1, r2\] -0+c0 <[^>]*> b19100f2 ? ldrltsh r0, \[r1, r2\] -0+c4 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\] -0+c8 <[^>]*> 119100d2 ? ldrnesb r0, \[r1, r2\] -0+cc <[^>]*> 819100d2 ? ldrhisb r0, \[r1, r2\] -0+d0 <[^>]*> b19100d2 ? ldrltsb r0, \[r1, r2\] -0+d4 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e0 <[^>]*> -0+d8 <[^>]*> e1df00f4 ? ldrsh r0, \[pc, #4\] ; 0+e4 <[^>]*> -0+dc <[^>]*> 00000000 ? andeq r0, r0, r0 -[ ]*dc:.*fred -0+e0 <[^>]*> 0000c0de ? .* -0+e4 <[^>]*> 0000dead ? .* -0+e8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+ec <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/arm7t.s b/binutils-2.17/gas/testsuite/gas/arm/arm7t.s deleted file mode 100644 index 580c3f11..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/arm7t.s +++ /dev/null @@ -1,81 +0,0 @@ - .text - .align 0 - -loadhalfwords: - ldrh r0, [r1] - ldrh r0, [r1]! - ldrh r0, [r1, r2] - ldrh r0, [r1, r2]! - ldrh r0, [r1,#0x0C] - ldrh r0, [r1,#0x0C]! - ldrh r0, [r1,#-0x0C] - ldrh r0, [r1], r2 - ldrh r0, =0xFF00 - ldrh r0, =0xC0DE - ldrh r0, .L2 - -storehalfwords: - strh r0, [r1] - strh r0, [r1]! - strh r0, [r1, r2] - strh r0, [r1, r2]! - strh r0, [r1,#0x0C] - strh r0, [r1,#0x0C]! - strh r0, [r1,#-0x0C] - strh r0, [r1], r2 - strh r0, .L2 - -loadsignedbytes: - ldrsb r0, [r1] - ldrsb r0, [r1]! - ldrsb r0, [r1, r2] - ldrsb r0, [r1, r2]! - ldrsb r0, [r1,#0x0C] - ldrsb r0, [r1,#0x0C]! - ldrsb r0, [r1,#-0x0C] - ldrsb r0, [r1], r2 - ldrsb r0, =0xDE - ldrsb r0, .L2 - -loadsignedhalfwords: - ldrsh r0, [r1] - ldrsh r0, [r1]! - ldrsh r0, [r1, r2] - ldrsh r0, [r1, r2]! - ldrsh r0, [r1, #0x0C] - ldrsh r0, [r1, #0x0C]! - ldrsh r0, [r1, #-0x0C] - ldrsh r0, [r1], r2 - ldrsh r0, =0xFF00 - ldrsh r0, =0xC0DE - ldrsh r0, .L2 - -misc: - ldralh r0, [r1, r2] - ldrneh r0, [r1, r2] - ldrhih r0, [r1, r2] - ldrlth r0, [r1, r2] - - ldralsh r0, [r1, r2] - ldrnesh r0, [r1, r2] - ldrhish r0, [r1, r2] - ldrltsh r0, [r1, r2] - - ldralsb r0, [r1, r2] - ldrnesb r0, [r1, r2] - ldrhisb r0, [r1, r2] - ldrltsb r0, [r1, r2] - - ldrsh r0, =0xC0DE - ldrsh r0, =0xDEAD - - .align -.L2: - .word fred - - .ltorg - - # Add two nop instructions to ensure that the - # output is 32-byte aligned as required for arm-aout. - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.d b/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.d deleted file mode 100644 index f6f1454b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: ARM v1 errors -#as: -mcpu=arm7m -#error-output: armv1-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.l b/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.l deleted file mode 100644 index 423672c5..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.l +++ /dev/null @@ -1,9 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:4: Error: invalid pseudo operation -- `str r0,=0x00ff0000' -[^:]*:5: Error: bad expression -- `ldr r0,{r1}' -[^:]*:6: Error: bad instruction `cmpl r0,r0' -[^:]*:7: Error: selected processor does not support `strh r0,\[r1\]' -[^:]*:8: Warning: writeback of base register is UNPREDICTABLE -[^:]*:9: Warning: writeback of base register when in register list is UNPREDICTABLE -[^:]*:10: Warning: writeback of base register is UNPREDICTABLE -[^:]*:12: Warning: if writeback register is in list, it must be the lowest reg in the list diff --git a/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.s b/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.s deleted file mode 100644 index 7e5f6839..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/armv1-bad.s +++ /dev/null @@ -1,12 +0,0 @@ - .global entry - .text -entry: - str r0, =0x00ff0000 - ldr r0, {r1} - cmpl r0, r0 - strh r0, [r1] - ldmfa r4!, {r8, r9}^ - ldmfa r4!, {r4, r8, r9} - stmfa r4!, {r8, r9}^ - stmdb r4!, {r4, r8, r9} @ This is OK. - stmdb r8!, {r4, r8, r9} diff --git a/binutils-2.17/gas/testsuite/gas/arm/armv1.d b/binutils-2.17/gas/testsuite/gas/arm/armv1.d deleted file mode 100644 index 4e4c9137..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/armv1.d +++ /dev/null @@ -1,73 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM v1 instructions -#as: -mcpu=arm7t - -# Test the ARM v1 instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> e0000000 ? and r0, r0, r0 -0+04 <[^>]*> e0100000 ? ands r0, r0, r0 -0+08 <[^>]*> e0200000 ? eor r0, r0, r0 -0+0c <[^>]*> e0300000 ? eors r0, r0, r0 -0+10 <[^>]*> e0400000 ? sub r0, r0, r0 -0+14 <[^>]*> e0500000 ? subs r0, r0, r0 -0+18 <[^>]*> e0600000 ? rsb r0, r0, r0 -0+1c <[^>]*> e0700000 ? rsbs r0, r0, r0 -0+20 <[^>]*> e0800000 ? add r0, r0, r0 -0+24 <[^>]*> e0900000 ? adds r0, r0, r0 -0+28 <[^>]*> e0a00000 ? adc r0, r0, r0 -0+2c <[^>]*> e0b00000 ? adcs r0, r0, r0 -0+30 <[^>]*> e0c00000 ? sbc r0, r0, r0 -0+34 <[^>]*> e0d00000 ? sbcs r0, r0, r0 -0+38 <[^>]*> e0e00000 ? rsc r0, r0, r0 -0+3c <[^>]*> e0f00000 ? rscs r0, r0, r0 -0+40 <[^>]*> e1800000 ? orr r0, r0, r0 -0+44 <[^>]*> e1900000 ? orrs r0, r0, r0 -0+48 <[^>]*> e1c00000 ? bic r0, r0, r0 -0+4c <[^>]*> e1d00000 ? bics r0, r0, r0 -0+50 <[^>]*> e1100000 ? tst r0, r0 -0+54 <[^>]*> e1100000 ? tst r0, r0 -0+58 <[^>]*> e110f000 ? tstp r0, r0 -0+5c <[^>]*> e1300000 ? teq r0, r0 -0+60 <[^>]*> e1300000 ? teq r0, r0 -0+64 <[^>]*> e130f000 ? teqp r0, r0 -0+68 <[^>]*> e1500000 ? cmp r0, r0 -0+6c <[^>]*> e1500000 ? cmp r0, r0 -0+70 <[^>]*> e150f000 ? cmpp r0, r0 -0+74 <[^>]*> e1700000 ? cmn r0, r0 -0+78 <[^>]*> e1700000 ? cmn r0, r0 -0+7c <[^>]*> e170f000 ? cmnp r0, r0 -0+80 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+84 <[^>]*> e1b00000 ? movs r0, r0 -0+88 <[^>]*> e1e00000 ? mvn r0, r0 -0+8c <[^>]*> e1f00000 ? mvns r0, r0 -0+90 <[^>]*> ef000000 ? (swi|svc) 0x00000000 -0+94 <[^>]*> e5900000 ? ldr r0, \[r0\] -0+98 <[^>]*> e5d00000 ? ldrb r0, \[r0\] -0+9c <[^>]*> e4b10000 ? ldrt r0, \[r1\] -0+a0 <[^>]*> e4f10000 ? ldrbt r0, \[r1\] -0+a4 <[^>]*> e5800000 ? str r0, \[r0\] -0+a8 <[^>]*> e5c00000 ? strb r0, \[r0\] -0+ac <[^>]*> e4a10000 ? strt r0, \[r1\] -0+b0 <[^>]*> e4e10000 ? strbt r0, \[r1\] -0+b4 <[^>]*> e8800001 ? stmia r0, {r0} -0+b8 <[^>]*> e9800001 ? stmib r0, {r0} -0+bc <[^>]*> e8000001 ? stmda r0, {r0} -0+c0 <[^>]*> e9000001 ? stmdb r0, {r0} -0+c4 <[^>]*> e9000001 ? stmdb r0, {r0} -0+c8 <[^>]*> e9800001 ? stmib r0, {r0} -0+cc <[^>]*> e8800001 ? stmia r0, {r0} -0+d0 <[^>]*> e8000001 ? stmda r0, {r0} -0+d4 <[^>]*> e8900001 ? ldmia r0, {r0} -0+d8 <[^>]*> e9900001 ? ldmib r0, {r0} -0+dc <[^>]*> e8100001 ? ldmda r0, {r0} -0+e0 <[^>]*> e9100001 ? ldmdb r0, {r0} -0+e4 <[^>]*> e8900001 ? ldmia r0, {r0} -0+e8 <[^>]*> e8100001 ? ldmda r0, {r0} -0+ec <[^>]*> e9100001 ? ldmdb r0, {r0} -0+f0 <[^>]*> e9900001 ? ldmib r0, {r0} -0+f4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+f8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+fc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/armv1.s b/binutils-2.17/gas/testsuite/gas/arm/armv1.s deleted file mode 100644 index bd83639d..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/armv1.s +++ /dev/null @@ -1,76 +0,0 @@ - .global entry - .text -entry: - and r0, r0, r0 - ands r0, r0, r0 - eor r0, r0, r0 - eors r0, r0, r0 - sub r0, r0, r0 - subs r0, r0, r0 - rsb r0, r0, r0 - rsbs r0, r0, r0 - add r0, r0, r0 - adds r0, r0, r0 - adc r0, r0, r0 - adcs r0, r0, r0 - sbc r0, r0, r0 - sbcs r0, r0, r0 - rsc r0, r0, r0 - rscs r0, r0, r0 - orr r0, r0, r0 - orrs r0, r0, r0 - bic r0, r0, r0 - bics r0, r0, r0 - - tst r0, r0 - tsts r0, r0 - tstp r0, r0 - teq r0, r0 - teqs r0, r0 - teqp r0, r0 - cmp r0, r0 - cmps r0, r0 - cmpp r0, r0 - cmn r0, r0 - cmns r0, r0 - cmnp r0, r0 - - mov r0, r0 - movs r0, r0 - mvn r0, r0 - mvns r0, r0 - - swi #0 - - ldr r0, [r0, #-0] - ldrb r0, [r0, #-0] - ldrt r0, [r1] - ldrbt r0, [r1] - str r0, [r0, #-0] - strb r0, [r0, #-0] - strt r0, [r1] - strbt r0, [r1] - - stmia r0, {r0} - stmib r0, {r0} - stmda r0, {r0} - stmdb r0, {r0} - stmfd r0, {r0} - stmfa r0, {r0} - stmea r0, {r0} - stmed r0, {r0} - - ldmia r0, {r0} - ldmib r0, {r0} - ldmda r0, {r0} - ldmdb r0, {r0} - ldmfd r0, {r0} - ldmfa r0, {r0} - ldmea r0, {r0} - ldmed r0, {r0} - - # Add three nop instructions to ensure that the - # output is 32-byte aligned as required for arm-aout. - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/bignum1.d b/binutils-2.17/gas/testsuite/gas/arm/bignum1.d deleted file mode 100644 index cef2036c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/bignum1.d +++ /dev/null @@ -1,12 +0,0 @@ -# name: bignums -# as: -# objdump: --full-contents -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* - -.*: +file format .*arm.* - -Contents of section .data: - 0000 [08]0000000 000000[08]0 11111111 11111111 \.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\. -# Ignore .ARM.attributes section -#... diff --git a/binutils-2.17/gas/testsuite/gas/arm/bignum1.s b/binutils-2.17/gas/testsuite/gas/arm/bignum1.s deleted file mode 100644 index 2b9d7364..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/bignum1.s +++ /dev/null @@ -1,3 +0,0 @@ - .data - .8byte -9223372036854775808 - .8byte 1229782938247303441 diff --git a/binutils-2.17/gas/testsuite/gas/arm/blx-local.d b/binutils-2.17/gas/testsuite/gas/arm/blx-local.d deleted file mode 100644 index e187536b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/blx-local.d +++ /dev/null @@ -1,15 +0,0 @@ -#name: Local BLX instructions -#objdump: -dr --prefix-addresses --show-raw-insn -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -#as: - -# Test assembler resolution of blx instructions. - -.*: +file format .*arm.* - -Disassembly of section .text: - -0+00 <[^>]*> fa000000 blx 00+8 <foo> -0+04 <[^>]*> fbffffff blx 00+a <foo2> -0+08 <[^>]*> 46c0 nop \(mov r8, r8\) -0+0a <[^>]*> 46c0 nop \(mov r8, r8\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/blx-local.s b/binutils-2.17/gas/testsuite/gas/arm/blx-local.s deleted file mode 100644 index c85a562d..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/blx-local.s +++ /dev/null @@ -1,16 +0,0 @@ - .text - .arch armv5t - .arm -one: - blx foo - blx foo2 - - .thumb - .type foo, %function - .thumb_func -foo: - nop - .type foo2, %function - .thumb_func -foo2: - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/copro.d b/binutils-2.17/gas/testsuite/gas/arm/copro.d deleted file mode 100644 index 5f5dd110..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/copro.d +++ /dev/null @@ -1,41 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn --architecture=armv5te -#name: ARM CoProcessor Instructions -#as: -march=armv5te -EL - -# Test the standard ARM co-processor instructions: - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> ee421103 dvfs f1, f2, f3 -0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5 -0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\] -0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] -0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]! -0+014 <[^>]*> 5cf31710 ldcpll 7, cr1, \[r3\], #64 -0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] -0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\] -0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] -0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]! -0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48 -0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] -0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\} -0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\} -0+038 <[^>]*> ee21f711 mcr 7, 1, pc, cr1, cr1, \{0\} -0+03c <[^>]*> be228519 mcrlt 5, 1, r8, cr2, cr9, \{0\} -0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\} -0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\} -0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\} -0+04c <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\} -0+050 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\} -0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\} -0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\} -0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\} -0+060 <[^>]*> ecd88bff ldcl 11, cr8, \[r8\], \{255\} -0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\} -0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4 -0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5 -0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15 -0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14 -0+078 <[^>]*> e1a00000 nop \(mov r0,r0\) -0+07c <[^>]*> e1a00000 nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/copro.s b/binutils-2.17/gas/testsuite/gas/arm/copro.s deleted file mode 100644 index 334b000f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/copro.s +++ /dev/null @@ -1,45 +0,0 @@ -.text -.align 0 - cdp p1, 4, cr1, cr2, cr3 - cdpeq 4, 3, c1, c4, cr5, 5 - - ldc 5, cr9, [r3] - ldcl 1, cr14, [r1, #32] - ldcmi 0, cr0, [r2, #1020]! - ldcpll p7, c1, [r3], #64 - ldc p0, c8, foo -foo: - - stc 5, cr0, [r3] - stcl 3, cr15, [r0, #8] - stceq p4, cr12, [r2, #100]! - stccc p6, c8, [r4], #48 - stc p1, c7, bar -bar: - - mrc 2, 3, r5, c1, c2 - mrcge p4, 5, r15, cr1, cr2, 7 - - mcr p7, 1, r15, cr1, cr1 - mcrlt 5, 1, r8, cr2, cr9, 0 - - @ The following patterns test Addressing Mode 5 "Unindexed" - - ldc 3, c7, [r0], {0} - stc p14, c6, [r1], {1} - ldc2 5, c5, [r2], {2} - stc2 p6, c4, [r3], {3} - ldcl 7, c3, [r4], {4} - stcl p8, c2, [r5], {5} - ldc2l 9, c1, [r6], {6} - stc2l p10, c0, [r7], {7} - ldcl 11, c8, [r8], {255} - stcl p12, c9, [r9], {254} - mrrc 13, 0, r7, r0, cr4 - mcrr p14, 0, r7, r0, cr5 - mrrc 15, 15, r7, r0, cr15 - mcrr p14, 15, r7, r0, cr14 - - # Extra instructions to allow for code alignment in arm-aout target. - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/eabi_attr_1.d b/binutils-2.17/gas/testsuite/gas/arm/eabi_attr_1.d deleted file mode 100644 index 0e97addb..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/eabi_attr_1.d +++ /dev/null @@ -1,13 +0,0 @@ -# as: -meabi=4 -# readelf: -A -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -Attribute Section: aeabi -File Attributes - Tag_CPU_name: "ARM1136JF-S" - Tag_CPU_arch: v6 - Tag_ARM_ISA_use: Yes - Tag_ABI_VFP_args: VFP registers - Tag_compatibility: flag = 3, vendor = GNU - Tag_unknown_128: 1234 \(0x4d2\) - Tag_unknown_129: "bar" diff --git a/binutils-2.17/gas/testsuite/gas/arm/eabi_attr_1.s b/binutils-2.17/gas/testsuite/gas/arm/eabi_attr_1.s deleted file mode 100644 index 3375acdb..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/eabi_attr_1.s +++ /dev/null @@ -1,9 +0,0 @@ -.text -.cpu arm1136jf-s -foo: -bx lr -.eabi_attribute 32, 3, "GNU" -.eabi_attribute 28, 1 -.eabi_attribute 128, 1234 -.eabi_attribute 129, "bar" - diff --git a/binutils-2.17/gas/testsuite/gas/arm/el_segundo.d b/binutils-2.17/gas/testsuite/gas/arm/el_segundo.d deleted file mode 100644 index 064c51f4..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/el_segundo.d +++ /dev/null @@ -1,34 +0,0 @@ -# name: El Segundo instructions -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section \.text: -0+00 <[^>]+> c1003281 smlabbgt r0, r1, r2, r3 -0+04 <[^>]+> e1003281 smlabb r0, r1, r2, r3 -0+08 <[^>]+> e10032a1 smlatb r0, r1, r2, r3 -0+0c <[^>]+> e10032c1 smlabt r0, r1, r2, r3 -0+10 <[^>]+> e10032e1 smlatt r0, r1, r2, r3 -0+14 <[^>]+> c1203281 smlawbgt r0, r1, r2, r3 -0+18 <[^>]+> e1203281 smlawb r0, r1, r2, r3 -0+1c <[^>]+> e12032c1 smlawt r0, r1, r2, r3 -0+20 <[^>]+> c1410382 smlalbbgt r0, r1, r2, r3 -0+24 <[^>]+> e1410382 smlalbb r0, r1, r2, r3 -0+28 <[^>]+> e14103a2 smlaltb r0, r1, r2, r3 -0+2c <[^>]+> e14103c2 smlalbt r0, r1, r2, r3 -0+30 <[^>]+> e14103e2 smlaltt r0, r1, r2, r3 -0+34 <[^>]+> c1600281 smulbbgt r0, r1, r2 -0+38 <[^>]+> e1600281 smulbb r0, r1, r2 -0+3c <[^>]+> e16002a1 smultb r0, r1, r2 -0+40 <[^>]+> e16002c1 smulbt r0, r1, r2 -0+44 <[^>]+> e16002e1 smultt r0, r1, r2 -0+48 <[^>]+> c12002a1 smulwbgt r0, r1, r2 -0+4c <[^>]+> e12002a1 smulwb r0, r1, r2 -0+50 <[^>]+> e12002e1 smulwt r0, r1, r2 -0+54 <[^>]+> c1020051 qaddgt r0, r1, r2 -0+58 <[^>]+> e1020051 qadd r0, r1, r2 -0+5c <[^>]+> e1420051 qdadd r0, r1, r2 -0+60 <[^>]+> e1220051 qsub r0, r1, r2 -0+64 <[^>]+> e1620051 qdsub r0, r1, r2 -0+68 <[^>]+> e1220051 qsub r0, r1, r2 -0+6c <[^>]+> e1a00000 nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/el_segundo.s b/binutils-2.17/gas/testsuite/gas/arm/el_segundo.s deleted file mode 100644 index 2111b5e7..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/el_segundo.s +++ /dev/null @@ -1,43 +0,0 @@ -# el_segundo.s -# -# Tests that we generate the right code for v5e instructions. - .text - .global main - .align 0 -main: - smlabbgt r0,r1,r2,r3 - smlabb r0,r1,r2,r3 - smlatb r0,r1,r2,r3 - smlabt r0,r1,r2,r3 - smlatt r0,r1,r2,r3 - - smlawbgt r0,r1,r2,r3 - smlawb r0,r1,r2,r3 - smlawt r0,r1,r2,r3 - - smlalbbgt r0,r1,r2,r3 - smlalbb r0,r1,r2,r3 - smlaltb r0,r1,r2,r3 - smlalbt r0,r1,r2,r3 - smlaltt r0,r1,r2,r3 - - smulbbgt r0,r1,r2 - smulbb r0,r1,r2 - smultb r0,r1,r2 - smulbt r0,r1,r2 - smultt r0,r1,r2 - - smulwbgt r0,r1,r2 - smulwb r0,r1,r2 - smulwt r0,r1,r2 - - qaddgt r0,r1,r2 - qadd r0,r1,r2 - - qdadd r0,r1,r2 - qsub r0,r1,r2 - qdsub r0,r1,r2 - qsub r0,r1,r2 - - @ padding for a.out's sake - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/float.d b/binutils-2.17/gas/testsuite/gas/arm/float.d deleted file mode 100644 index c9754b20..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/float.d +++ /dev/null @@ -1,131 +0,0 @@ -# name: Core floating point instructions -# as: -mcpu=arm7tdmi -mfpu=fpa -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]+> ee088101 ? mvfe f0, f1 -0+004 <[^>]+> 0e08b105 ? mvfeqe f3, f5 -0+008 <[^>]+> 0e00c189 ? mvfeqd f4, #1\.0 -0+00c <[^>]+> ee00c107 ? mvfs f4, f7 -0+010 <[^>]+> ee008121 ? mvfsp f0, f1 -0+014 <[^>]+> ee00b1c4 ? mvfdm f3, f4 -0+018 <[^>]+> ee08f167 ? mvfez f7, f7 -0+01c <[^>]+> ee09010a ? adfe f0, f1, #2\.0 -0+020 <[^>]+> 0e0a110e ? adfeqe f1, f2, #0\.5 -0+024 <[^>]+> ee043145 ? adfsm f3, f4, f5 -0+028 <[^>]+> ee20018a ? sufd f0, f0, #2\.0 -0+02c <[^>]+> ee22110f ? sufs f1, f2, #10\.0 -0+030 <[^>]+> 1e2c3165 ? sufneez f3, f4, f5 -0+034 <[^>]+> ee311108 ? rsfs f1, f1, #0\.0 -0+038 <[^>]+> ee3031ad ? rsfdp f3, f0, #5\.0 -0+03c <[^>]+> de367180 ? rsfled f7, f6, f0 -0+040 <[^>]+> ee100180 ? mufd f0, f0, f0 -0+044 <[^>]+> ee1a116b ? mufez f1, f2, #3\.0 -0+048 <[^>]+> ee10010c ? mufs f0, f0, #4\.0 -0+04c <[^>]+> ee400189 ? dvfd f0, f0, #1\.0 -0+050 <[^>]+> ee49016f ? dvfez f0, f1, #10\.0 -0+054 <[^>]+> 4e443145 ? dvfmism f3, f4, f5 -0+058 <[^>]+> ee59010f ? rdfe f0, f1, #10\.0 -0+05c <[^>]+> ee573109 ? rdfs f3, f7, #1\.0 -0+060 <[^>]+> 3e5441a3 ? rdfccdp f4, f4, f3 -0+064 <[^>]+> ee620183 ? powd f0, f2, f3 -0+068 <[^>]+> ee63110f ? pows f1, f3, #10\.0 -0+06c <[^>]+> 2e6f4169 ? powcsez f4, f7, #1\.0 -0+070 <[^>]+> ee767107 ? rpws f7, f6, f7 -0+074 <[^>]+> 0e710182 ? rpweqd f0, f1, f2 -0+078 <[^>]+> ee7a2143 ? rpwem f2, f2, f3 -0+07c <[^>]+> ee82118b ? rmfd f1, f2, #3\.0 -0+080 <[^>]+> 6e843104 ? rmfvss f3, f4, f4 -0+084 <[^>]+> ee8f4120 ? rmfep f4, f7, f0 -0+088 <[^>]+> ee910102 ? fmls f0, f1, f2 -0+08c <[^>]+> 0e931105 ? fmleqs f1, f3, f5 -0+090 <[^>]+> 5e964160 ? fmlplsz f4, f6, f0 -0+094 <[^>]+> eea3110f ? fdvs f1, f3, #10\.0 -0+098 <[^>]+> eea10122 ? fdvsp f0, f1, f2 -0+09c <[^>]+> 2ea44144 ? fdvcssm f4, f4, f4 -0+0a0 <[^>]+> eeb11109 ? frds f1, f1, #1\.0 -0+0a4 <[^>]+> ceb12100 ? frdgts f2, f1, f0 -0+0a8 <[^>]+> ceb44165 ? frdgtsz f4, f4, f5 -0+0ac <[^>]+> eec10182 ? pold f0, f1, f2 -0+0b0 <[^>]+> eec6416b ? polsz f4, f6, #3\.0 -0+0b4 <[^>]+> 0ece5107 ? poleqe f5, f6, f7 -0+0b8 <[^>]+> ee108101 ? mnfs f0, f1 -0+0bc <[^>]+> ee10818b ? mnfd f0, #3\.0 -0+0c0 <[^>]+> ee18816c ? mnfez f0, #4\.0 -0+0c4 <[^>]+> 0e188165 ? mnfeqez f0, f5 -0+0c8 <[^>]+> ee108124 ? mnfsp f0, f4 -0+0cc <[^>]+> ee1091c7 ? mnfdm f1, f7 -0+0d0 <[^>]+> ee208181 ? absd f0, f1 -0+0d4 <[^>]+> ee20912b ? abssp f1, #3\.0 -0+0d8 <[^>]+> 0e28c105 ? abseqe f4, f5 -0+0dc <[^>]+> ee309102 ? rnds f1, f2 -0+0e0 <[^>]+> ee30b184 ? rndd f3, f4 -0+0e4 <[^>]+> 0e38e16c ? rndeqez f6, #4\.0 -0+0e8 <[^>]+> ee40d105 ? sqts f5, f5 -0+0ec <[^>]+> ee40e1a6 ? sqtdp f6, f6 -0+0f0 <[^>]+> 5e48f166 ? sqtplez f7, f6 -0+0f4 <[^>]+> ee50810f ? logs f0, #10\.0 -0+0f8 <[^>]+> ee58810f ? loge f0, #10\.0 -0+0fc <[^>]+> 1e5081e1 ? lognedz f0, f1 -0+100 <[^>]+> ee689102 ? lgne f1, f2 -0+104 <[^>]+> ee6091e3 ? lgndz f1, f3 -0+108 <[^>]+> 7e60b104 ? lgnvcs f3, f4 -0+10c <[^>]+> ee709103 ? exps f1, f3 -0+110 <[^>]+> ee78b14f ? expem f3, #10\.0 -0+114 <[^>]+> 5e70e187 ? exppld f6, f7 -0+118 <[^>]+> ee808181 ? sind f0, f1 -0+11c <[^>]+> ee809142 ? sinsm f1, f2 -0+120 <[^>]+> ce88c10d ? singte f4, #5\.0 -0+124 <[^>]+> ee909183 ? cosd f1, f3 -0+128 <[^>]+> ee98c145 ? cosem f4, f5 -0+12c <[^>]+> 1e90e1a1 ? cosnedp f6, f1 -0+130 <[^>]+> eea89105 ? tane f1, f5 -0+134 <[^>]+> eea0c167 ? tansz f4, f7 -0+138 <[^>]+> aea091ec ? tangedz f1, #4\.0 -0+13c <[^>]+> eeb8c105 ? asne f4, f5 -0+140 <[^>]+> eeb0e12e ? asnsp f6, #0\.5 -0+144 <[^>]+> 4eb0d1e5 ? asnmidz f5, f5 -0+148 <[^>]+> eec0d106 ? acss f5, f6 -0+14c <[^>]+> eec0e180 ? acsd f6, f0 -0+150 <[^>]+> 2ec8914e ? acscsem f1, #0\.5 -0+154 <[^>]+> eed88105 ? atne f0, f5 -0+158 <[^>]+> eed0916d ? atnsz f1, #5\.0 -0+15c <[^>]+> bed0b182 ? atnltd f3, f2 -0+160 <[^>]+> eee8d104 ? urde f5, f4 -0+164 <[^>]+> eef8e105 ? nrme f6, f5 -0+168 <[^>]+> 5ef0f1e5 ? nrmpldz f7, f5 -0+16c <[^>]+> ee008130 ? fltsp f0, r8 -0+170 <[^>]+> ee090110 ? flte f1, r0 -0+174 <[^>]+> 0e0571f0 ? flteqdz f5, r7 -0+178 <[^>]+> ee100111 ? fix r0, f1 -0+17c <[^>]+> ee101177 ? fixz r1, f7 -0+180 <[^>]+> 2e105155 ? fixcsm r5, f5 -0+184 <[^>]+> ee400110 ? wfc r0 -0+188 <[^>]+> ee201110 ? wfs r1 -0+18c <[^>]+> 0e302110 ? rfseq r2 -0+190 <[^>]+> ee504110 ? rfc r4 -0+194 <[^>]+> ee90f119 ? cmf f0, #1\.0 -0+198 <[^>]+> ee91f112 ? cmf f1, f2 -0+19c <[^>]+> 0e90f111 ? cmfeq f0, f1 -0+1a0 <[^>]+> eeb0f11b ? cnf f0, #3\.0 -0+1a4 <[^>]+> eeb1f11e ? cnf f1, #0\.5 -0+1a8 <[^>]+> 6eb3f114 ? cnfvs f3, f4 -0+1ac <[^>]+> eed0f111 ? cmfe f0, f1 -0+1b0 <[^>]+> 0ed1f112 ? cmfeeq f1, f2 -0+1b4 <[^>]+> 0ed3f11d ? cmfeeq f3, #5\.0 -0+1b8 <[^>]+> eef1f113 ? cnfe f1, f3 -0+1bc <[^>]+> 0ef3f114 ? cnfeeq f3, f4 -0+1c0 <[^>]+> 0ef4f117 ? cnfeeq f4, f7 -0+1c4 <[^>]+> eef4f11d ? cnfe f4, #5\.0 -0+1c8 <[^>]+> ed900200 ? lfm f0, 4, \[r0\] -0+1cc <[^>]+> ed900200 ? lfm f0, 4, \[r0\] -0+1d0 <[^>]+> ed911210 ? lfm f1, 4, \[r1, #64\] -0+1d4 <[^>]+> edae22ff ? sfm f2, 4, \[lr, #1020\]! -0+1d8 <[^>]+> 0c68f2ff ? sfmeq f7, 3, \[r8\], #-1020 -0+1dc <[^>]+> eddf6200 ? lfm f6, 2, \[pc\] -0+1e0 <[^>]+> eca8f203 ? sfm f7, 1, \[r8\], #12 -0+1e4 <[^>]+> 0d16520c ? lfmeq f5, 4, \[r6, #-48\] -0+1e8 <[^>]+> 1d42c209 ? sfmne f4, 3, \[r2, #-36\] -0+1ec <[^>]+> 1d62c209 ? sfmne f4, 3, \[r2, #-36\]! diff --git a/binutils-2.17/gas/testsuite/gas/arm/float.s b/binutils-2.17/gas/testsuite/gas/arm/float.s deleted file mode 100644 index 437d298d..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/float.s +++ /dev/null @@ -1,163 +0,0 @@ - .text - .align 0 -l: - mvfe f0, f1 - mvfeqe f3, f5 - mvfeqd f4, #1.0 - mvfs f4, f7 - mvfsp f0, f1 - mvfdm f3, f4 - mvfez f7, f7 - - adfe f0, f1, #2.0 - adfeqe f1, f2, #0.5 - adfsm f3, f4, f5 - - sufd f0, f0, #2.0 - sufs f1, f2, #10.0 - sufneez f3, f4, f5 - - rsfs f1, f1, #0.0 - rsfdp f3, f0, #5.0 - rsfled f7, f6, f0 - - mufd f0, f0, f0 - mufez f1, f2, #3.0 - mufals f0, f0, #4.0 - - dvfd f0, f0, #1.0000 - dvfez f0, f1, #10e0 - dvfmism f3, f4, f5 - - rdfe f0, f1, #1.0e1 - rdfs f3, f7, #0f1 - rdfccdp f4, f4, f3 - - powd f0, f2, f3 - pows f1, f3, #0e1e1 - powcsez f4, f7, #1 - - rpws f7, f6, f7 - rpweqd f0, f1, f2 - rpwem f2, f2, f3 - - rmfd f1, f2, #3 - rmfvss f3, f4, f4 - rmfep f4, f7, f0 - - fmls f0, f1, f2 - fmleqs f1, f3, f5 - fmlplsz f4, f6, f0 - - fdvs f1, f3, #10 - fdvsp f0, f1, f2 - fdvhssm f4, f4, f4 - - frds f1, f1, #1.0 - frdgts f2, f1, f0 - frdgtsz f4, f4, f5 - - pold f0, f1, f2 - polsz f4, f6, #3.0 - poleqe f5, f6, f7 - - mnfs f0, f1 - mnfd f0, #3.0 - mnfez f0, #4.0 - mnfeqez f0, f5 - mnfsp f0, f4 - mnfdm f1, f7 - - absd f0, f1 - abssp f1, #3.0 - abseqe f4, f5 - - rnds f1, f2 - rndd f3, f4 - rndeqez f6, #4.0 - - sqts f5, f5 - sqtdp f6, f6 - sqtplez f7, f6 - - logs f0, #10 - loge f0, #0f10 - lognedz f0, f1 - - lgne f1, f2 - lgndz f1, f3 - lgnvcs f3, f4 - - exps f1, f3 - expem f3, #10.0 - exppld f6, f7 - - sind f0, f1 - sinsm f1, f2 - singte f4, #5 - - cosd f1, f3 - cosem f4, f5 - cosnedp f6, f1 - - tane f1, f5 - tansz f4, f7 - tangedz f1, #4.0 - - asne f4, f5 - asnsp f6, #5e-1 - asnmidz f5, f5 - - acss f5, f6 - acsd f6, f0 - acshsem f1, #0.05e1 - - atne f0, f5 - atnsz f1, #5 - atnltd f3, f2 - - urde f5, f4 - nrme f6, f5 - nrmpldz f7, f5 - - fltsp f0, r8 - flte f1, r0 - flteqdz f5, r7 - - fix r0, f1 - fixz r1, f7 - fixcsm r5, f5 - - wfc r0 - wfs r1 - rfseq r2 - rfc r4 - - cmf f0, #1 - cmf f1, f2 - cmfeq f0, f1 - - cnf f0, #3 - cnf f1, #0.5 - cnfvs f3, f4 - - cmfe f0, f1 - cmfeeq f1, f2 - cmfeqe f3, #5.0 - - cnfe f1, f3 - cnfeeq f3, f4 - cnfeqe f4, f7 - cnfale f4, #5.0 - - lfm f0, 4, [r0] - lfm f0, 4, [r0, #0] - lfm f1, 4, [r1, #64] - sfm f2, 4, [r14, #1020]! - sfmeq f7, 3, [r8], #-1020 - - lfmfd f6, 2, [r15] - sfmea f7, 1, [r8]! - lfmeqea f5, 4, [r6] - sfmnefd f4, 3, [r2] - sfmnefd f4, 3, [r2]! diff --git a/binutils-2.17/gas/testsuite/gas/arm/fpa-dyadic.d b/binutils-2.17/gas/testsuite/gas/arm/fpa-dyadic.d deleted file mode 100644 index f603bbff..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/fpa-dyadic.d +++ /dev/null @@ -1,166 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: FPA Dyadic instructions -#as: -mfpu=fpa -mcpu=arm7m - -# Test FPA Dyadic instructions -# This test should work for both big and little-endian assembly. - -.*: *file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> ee000100 ? adfs f0, f0, f0 -0+004 <[^>]*> ee000120 ? adfsp f0, f0, f0 -0+008 <[^>]*> ee000140 ? adfsm f0, f0, f0 -0+00c <[^>]*> ee000160 ? adfsz f0, f0, f0 -0+010 <[^>]*> ee000180 ? adfd f0, f0, f0 -0+014 <[^>]*> ee0001a0 ? adfdp f0, f0, f0 -0+018 <[^>]*> ee0001c0 ? adfdm f0, f0, f0 -0+01c <[^>]*> ee0001e0 ? adfdz f0, f0, f0 -0+020 <[^>]*> ee080100 ? adfe f0, f0, f0 -0+024 <[^>]*> ee080120 ? adfep f0, f0, f0 -0+028 <[^>]*> ee080140 ? adfem f0, f0, f0 -0+02c <[^>]*> ee080160 ? adfez f0, f0, f0 -0+030 <[^>]*> ee200100 ? sufs f0, f0, f0 -0+034 <[^>]*> ee200120 ? sufsp f0, f0, f0 -0+038 <[^>]*> ee200140 ? sufsm f0, f0, f0 -0+03c <[^>]*> ee200160 ? sufsz f0, f0, f0 -0+040 <[^>]*> ee200180 ? sufd f0, f0, f0 -0+044 <[^>]*> ee2001a0 ? sufdp f0, f0, f0 -0+048 <[^>]*> ee2001c0 ? sufdm f0, f0, f0 -0+04c <[^>]*> ee2001e0 ? sufdz f0, f0, f0 -0+050 <[^>]*> ee280100 ? sufe f0, f0, f0 -0+054 <[^>]*> ee280120 ? sufep f0, f0, f0 -0+058 <[^>]*> ee280140 ? sufem f0, f0, f0 -0+05c <[^>]*> ee280160 ? sufez f0, f0, f0 -0+060 <[^>]*> ee300100 ? rsfs f0, f0, f0 -0+064 <[^>]*> ee300120 ? rsfsp f0, f0, f0 -0+068 <[^>]*> ee300140 ? rsfsm f0, f0, f0 -0+06c <[^>]*> ee300160 ? rsfsz f0, f0, f0 -0+070 <[^>]*> ee300180 ? rsfd f0, f0, f0 -0+074 <[^>]*> ee3001a0 ? rsfdp f0, f0, f0 -0+078 <[^>]*> ee3001c0 ? rsfdm f0, f0, f0 -0+07c <[^>]*> ee3001e0 ? rsfdz f0, f0, f0 -0+080 <[^>]*> ee380100 ? rsfe f0, f0, f0 -0+084 <[^>]*> ee380120 ? rsfep f0, f0, f0 -0+088 <[^>]*> ee380140 ? rsfem f0, f0, f0 -0+08c <[^>]*> ee380160 ? rsfez f0, f0, f0 -0+090 <[^>]*> ee100100 ? mufs f0, f0, f0 -0+094 <[^>]*> ee100120 ? mufsp f0, f0, f0 -0+098 <[^>]*> ee100140 ? mufsm f0, f0, f0 -0+09c <[^>]*> ee100160 ? mufsz f0, f0, f0 -0+0a0 <[^>]*> ee100180 ? mufd f0, f0, f0 -0+0a4 <[^>]*> ee1001a0 ? mufdp f0, f0, f0 -0+0a8 <[^>]*> ee1001c0 ? mufdm f0, f0, f0 -0+0ac <[^>]*> ee1001e0 ? mufdz f0, f0, f0 -0+0b0 <[^>]*> ee180100 ? mufe f0, f0, f0 -0+0b4 <[^>]*> ee180120 ? mufep f0, f0, f0 -0+0b8 <[^>]*> ee180140 ? mufem f0, f0, f0 -0+0bc <[^>]*> ee180160 ? mufez f0, f0, f0 -0+0c0 <[^>]*> ee400100 ? dvfs f0, f0, f0 -0+0c4 <[^>]*> ee400120 ? dvfsp f0, f0, f0 -0+0c8 <[^>]*> ee400140 ? dvfsm f0, f0, f0 -0+0cc <[^>]*> ee400160 ? dvfsz f0, f0, f0 -0+0d0 <[^>]*> ee400180 ? dvfd f0, f0, f0 -0+0d4 <[^>]*> ee4001a0 ? dvfdp f0, f0, f0 -0+0d8 <[^>]*> ee4001c0 ? dvfdm f0, f0, f0 -0+0dc <[^>]*> ee4001e0 ? dvfdz f0, f0, f0 -0+0e0 <[^>]*> ee480100 ? dvfe f0, f0, f0 -0+0e4 <[^>]*> ee480120 ? dvfep f0, f0, f0 -0+0e8 <[^>]*> ee480140 ? dvfem f0, f0, f0 -0+0ec <[^>]*> ee480160 ? dvfez f0, f0, f0 -0+0f0 <[^>]*> ee500100 ? rdfs f0, f0, f0 -0+0f4 <[^>]*> ee500120 ? rdfsp f0, f0, f0 -0+0f8 <[^>]*> ee500140 ? rdfsm f0, f0, f0 -0+0fc <[^>]*> ee500160 ? rdfsz f0, f0, f0 -0+100 <[^>]*> ee500180 ? rdfd f0, f0, f0 -0+104 <[^>]*> ee5001a0 ? rdfdp f0, f0, f0 -0+108 <[^>]*> ee5001c0 ? rdfdm f0, f0, f0 -0+10c <[^>]*> ee5001e0 ? rdfdz f0, f0, f0 -0+110 <[^>]*> ee580100 ? rdfe f0, f0, f0 -0+114 <[^>]*> ee580120 ? rdfep f0, f0, f0 -0+118 <[^>]*> ee580140 ? rdfem f0, f0, f0 -0+11c <[^>]*> ee580160 ? rdfez f0, f0, f0 -0+120 <[^>]*> ee600100 ? pows f0, f0, f0 -0+124 <[^>]*> ee600120 ? powsp f0, f0, f0 -0+128 <[^>]*> ee600140 ? powsm f0, f0, f0 -0+12c <[^>]*> ee600160 ? powsz f0, f0, f0 -0+130 <[^>]*> ee600180 ? powd f0, f0, f0 -0+134 <[^>]*> ee6001a0 ? powdp f0, f0, f0 -0+138 <[^>]*> ee6001c0 ? powdm f0, f0, f0 -0+13c <[^>]*> ee6001e0 ? powdz f0, f0, f0 -0+140 <[^>]*> ee680100 ? powe f0, f0, f0 -0+144 <[^>]*> ee680120 ? powep f0, f0, f0 -0+148 <[^>]*> ee680140 ? powem f0, f0, f0 -0+14c <[^>]*> ee680160 ? powez f0, f0, f0 -0+150 <[^>]*> ee700100 ? rpws f0, f0, f0 -0+154 <[^>]*> ee700120 ? rpwsp f0, f0, f0 -0+158 <[^>]*> ee700140 ? rpwsm f0, f0, f0 -0+15c <[^>]*> ee700160 ? rpwsz f0, f0, f0 -0+160 <[^>]*> ee700180 ? rpwd f0, f0, f0 -0+164 <[^>]*> ee7001a0 ? rpwdp f0, f0, f0 -0+168 <[^>]*> ee7001c0 ? rpwdm f0, f0, f0 -0+16c <[^>]*> ee7001e0 ? rpwdz f0, f0, f0 -0+170 <[^>]*> ee780100 ? rpwe f0, f0, f0 -0+174 <[^>]*> ee780120 ? rpwep f0, f0, f0 -0+178 <[^>]*> ee780140 ? rpwem f0, f0, f0 -0+17c <[^>]*> ee780160 ? rpwez f0, f0, f0 -0+180 <[^>]*> ee800100 ? rmfs f0, f0, f0 -0+184 <[^>]*> ee800120 ? rmfsp f0, f0, f0 -0+188 <[^>]*> ee800140 ? rmfsm f0, f0, f0 -0+18c <[^>]*> ee800160 ? rmfsz f0, f0, f0 -0+190 <[^>]*> ee800180 ? rmfd f0, f0, f0 -0+194 <[^>]*> ee8001a0 ? rmfdp f0, f0, f0 -0+198 <[^>]*> ee8001c0 ? rmfdm f0, f0, f0 -0+19c <[^>]*> ee8001e0 ? rmfdz f0, f0, f0 -0+1a0 <[^>]*> ee880100 ? rmfe f0, f0, f0 -0+1a4 <[^>]*> ee880120 ? rmfep f0, f0, f0 -0+1a8 <[^>]*> ee880140 ? rmfem f0, f0, f0 -0+1ac <[^>]*> ee880160 ? rmfez f0, f0, f0 -0+1b0 <[^>]*> ee900100 ? fmls f0, f0, f0 -0+1b4 <[^>]*> ee900120 ? fmlsp f0, f0, f0 -0+1b8 <[^>]*> ee900140 ? fmlsm f0, f0, f0 -0+1bc <[^>]*> ee900160 ? fmlsz f0, f0, f0 -0+1c0 <[^>]*> ee900180 ? fmld f0, f0, f0 -0+1c4 <[^>]*> ee9001a0 ? fmldp f0, f0, f0 -0+1c8 <[^>]*> ee9001c0 ? fmldm f0, f0, f0 -0+1cc <[^>]*> ee9001e0 ? fmldz f0, f0, f0 -0+1d0 <[^>]*> ee980100 ? fmle f0, f0, f0 -0+1d4 <[^>]*> ee980120 ? fmlep f0, f0, f0 -0+1d8 <[^>]*> ee980140 ? fmlem f0, f0, f0 -0+1dc <[^>]*> ee980160 ? fmlez f0, f0, f0 -0+1e0 <[^>]*> eea00100 ? fdvs f0, f0, f0 -0+1e4 <[^>]*> eea00120 ? fdvsp f0, f0, f0 -0+1e8 <[^>]*> eea00140 ? fdvsm f0, f0, f0 -0+1ec <[^>]*> eea00160 ? fdvsz f0, f0, f0 -0+1f0 <[^>]*> eea00180 ? fdvd f0, f0, f0 -0+1f4 <[^>]*> eea001a0 ? fdvdp f0, f0, f0 -0+1f8 <[^>]*> eea001c0 ? fdvdm f0, f0, f0 -0+1fc <[^>]*> eea001e0 ? fdvdz f0, f0, f0 -0+200 <[^>]*> eea80100 ? fdve f0, f0, f0 -0+204 <[^>]*> eea80120 ? fdvep f0, f0, f0 -0+208 <[^>]*> eea80140 ? fdvem f0, f0, f0 -0+20c <[^>]*> eea80160 ? fdvez f0, f0, f0 -0+210 <[^>]*> eeb00100 ? frds f0, f0, f0 -0+214 <[^>]*> eeb00120 ? frdsp f0, f0, f0 -0+218 <[^>]*> eeb00140 ? frdsm f0, f0, f0 -0+21c <[^>]*> eeb00160 ? frdsz f0, f0, f0 -0+220 <[^>]*> eeb00180 ? frdd f0, f0, f0 -0+224 <[^>]*> eeb001a0 ? frddp f0, f0, f0 -0+228 <[^>]*> eeb001c0 ? frddm f0, f0, f0 -0+22c <[^>]*> eeb001e0 ? frddz f0, f0, f0 -0+230 <[^>]*> eeb80100 ? frde f0, f0, f0 -0+234 <[^>]*> eeb80120 ? frdep f0, f0, f0 -0+238 <[^>]*> eeb80140 ? frdem f0, f0, f0 -0+23c <[^>]*> eeb80160 ? frdez f0, f0, f0 -0+240 <[^>]*> eec00100 ? pols f0, f0, f0 -0+244 <[^>]*> eec00120 ? polsp f0, f0, f0 -0+248 <[^>]*> eec00140 ? polsm f0, f0, f0 -0+24c <[^>]*> eec00160 ? polsz f0, f0, f0 -0+250 <[^>]*> eec00180 ? pold f0, f0, f0 -0+254 <[^>]*> eec001a0 ? poldp f0, f0, f0 -0+258 <[^>]*> eec001c0 ? poldm f0, f0, f0 -0+25c <[^>]*> eec001e0 ? poldz f0, f0, f0 -0+260 <[^>]*> eec80100 ? pole f0, f0, f0 -0+264 <[^>]*> eec80120 ? polep f0, f0, f0 -0+268 <[^>]*> eec80140 ? polem f0, f0, f0 -0+26c <[^>]*> eec80160 ? polez f0, f0, f0 diff --git a/binutils-2.17/gas/testsuite/gas/arm/fpa-dyadic.s b/binutils-2.17/gas/testsuite/gas/arm/fpa-dyadic.s deleted file mode 100644 index aebcd2b9..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/fpa-dyadic.s +++ /dev/null @@ -1,172 +0,0 @@ - .text - .globl F -F: - adfs f0, f0, f0 - adfsp f0, f0, f0 - adfsm f0, f0, f0 - adfsz f0, f0, f0 - adfd f0, f0, f0 - adfdp f0, f0, f0 - adfdm f0, f0, f0 - adfdz f0, f0, f0 - adfe f0, f0, f0 - adfep f0, f0, f0 - adfem f0, f0, f0 - adfez f0, f0, f0 - - sufs f0, f0, f0 - sufsp f0, f0, f0 - sufsm f0, f0, f0 - sufsz f0, f0, f0 - sufd f0, f0, f0 - sufdp f0, f0, f0 - sufdm f0, f0, f0 - sufdz f0, f0, f0 - sufe f0, f0, f0 - sufep f0, f0, f0 - sufem f0, f0, f0 - sufez f0, f0, f0 - - rsfs f0, f0, f0 - rsfsp f0, f0, f0 - rsfsm f0, f0, f0 - rsfsz f0, f0, f0 - rsfd f0, f0, f0 - rsfdp f0, f0, f0 - rsfdm f0, f0, f0 - rsfdz f0, f0, f0 - rsfe f0, f0, f0 - rsfep f0, f0, f0 - rsfem f0, f0, f0 - rsfez f0, f0, f0 - - mufs f0, f0, f0 - mufsp f0, f0, f0 - mufsm f0, f0, f0 - mufsz f0, f0, f0 - mufd f0, f0, f0 - mufdp f0, f0, f0 - mufdm f0, f0, f0 - mufdz f0, f0, f0 - mufe f0, f0, f0 - mufep f0, f0, f0 - mufem f0, f0, f0 - mufez f0, f0, f0 - - dvfs f0, f0, f0 - dvfsp f0, f0, f0 - dvfsm f0, f0, f0 - dvfsz f0, f0, f0 - dvfd f0, f0, f0 - dvfdp f0, f0, f0 - dvfdm f0, f0, f0 - dvfdz f0, f0, f0 - dvfe f0, f0, f0 - dvfep f0, f0, f0 - dvfem f0, f0, f0 - dvfez f0, f0, f0 - - rdfs f0, f0, f0 - rdfsp f0, f0, f0 - rdfsm f0, f0, f0 - rdfsz f0, f0, f0 - rdfd f0, f0, f0 - rdfdp f0, f0, f0 - rdfdm f0, f0, f0 - rdfdz f0, f0, f0 - rdfe f0, f0, f0 - rdfep f0, f0, f0 - rdfem f0, f0, f0 - rdfez f0, f0, f0 - - pows f0, f0, f0 - powsp f0, f0, f0 - powsm f0, f0, f0 - powsz f0, f0, f0 - powd f0, f0, f0 - powdp f0, f0, f0 - powdm f0, f0, f0 - powdz f0, f0, f0 - powe f0, f0, f0 - powep f0, f0, f0 - powem f0, f0, f0 - powez f0, f0, f0 - - rpws f0, f0, f0 - rpwsp f0, f0, f0 - rpwsm f0, f0, f0 - rpwsz f0, f0, f0 - rpwd f0, f0, f0 - rpwdp f0, f0, f0 - rpwdm f0, f0, f0 - rpwdz f0, f0, f0 - rpwe f0, f0, f0 - rpwep f0, f0, f0 - rpwem f0, f0, f0 - rpwez f0, f0, f0 - - rmfs f0, f0, f0 - rmfsp f0, f0, f0 - rmfsm f0, f0, f0 - rmfsz f0, f0, f0 - rmfd f0, f0, f0 - rmfdp f0, f0, f0 - rmfdm f0, f0, f0 - rmfdz f0, f0, f0 - rmfe f0, f0, f0 - rmfep f0, f0, f0 - rmfem f0, f0, f0 - rmfez f0, f0, f0 - - fmls f0, f0, f0 - fmlsp f0, f0, f0 - fmlsm f0, f0, f0 - fmlsz f0, f0, f0 - fmld f0, f0, f0 - fmldp f0, f0, f0 - fmldm f0, f0, f0 - fmldz f0, f0, f0 - fmle f0, f0, f0 - fmlep f0, f0, f0 - fmlem f0, f0, f0 - fmlez f0, f0, f0 - - fdvs f0, f0, f0 - fdvsp f0, f0, f0 - fdvsm f0, f0, f0 - fdvsz f0, f0, f0 - fdvd f0, f0, f0 - fdvdp f0, f0, f0 - fdvdm f0, f0, f0 - fdvdz f0, f0, f0 - fdve f0, f0, f0 - fdvep f0, f0, f0 - fdvem f0, f0, f0 - fdvez f0, f0, f0 - - frds f0, f0, f0 - frdsp f0, f0, f0 - frdsm f0, f0, f0 - frdsz f0, f0, f0 - frdd f0, f0, f0 - frddp f0, f0, f0 - frddm f0, f0, f0 - frddz f0, f0, f0 - frde f0, f0, f0 - frdep f0, f0, f0 - frdem f0, f0, f0 - frdez f0, f0, f0 - - pols f0, f0, f0 - polsp f0, f0, f0 - polsm f0, f0, f0 - polsz f0, f0, f0 - pold f0, f0, f0 - poldp f0, f0, f0 - poldm f0, f0, f0 - poldz f0, f0, f0 - pole f0, f0, f0 - polep f0, f0, f0 - polem f0, f0, f0 - polez f0, f0, f0 - diff --git a/binutils-2.17/gas/testsuite/gas/arm/fpa-mem.d b/binutils-2.17/gas/testsuite/gas/arm/fpa-mem.d deleted file mode 100644 index 9b3a6567..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/fpa-mem.d +++ /dev/null @@ -1,34 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: FPA memory insructions -#as: -mfpu=fpa10 -mcpu=arm7m - -# Test FPA memory instructions -# This test should work for both big and little-endian assembly. - -.*: *file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> ed900100 ? ldfs f0, \[r0\] -0+04 <[^>]*> ec300101 ? ldfs f0, \[r0\], #-4 -0+08 <[^>]*> ed908100 ? ldfd f0, \[r0\] -0+0c <[^>]*> ec308101 ? ldfd f0, \[r0\], #-4 -0+10 <[^>]*> edd00100 ? ldfe f0, \[r0\] -0+14 <[^>]*> ec700101 ? ldfe f0, \[r0\], #-4 -0+18 <[^>]*> edd08100 ? ldfp f0, \[r0\] -0+1c <[^>]*> ec708101 ? ldfp f0, \[r0\], #-4 -0+20 <[^>]*> ed800100 ? stfs f0, \[r0\] -0+24 <[^>]*> ec200101 ? stfs f0, \[r0\], #-4 -0+28 <[^>]*> ed808100 ? stfd f0, \[r0\] -0+2c <[^>]*> ec208101 ? stfd f0, \[r0\], #-4 -0+30 <[^>]*> edc00100 ? stfe f0, \[r0\] -0+34 <[^>]*> ec600101 ? stfe f0, \[r0\], #-4 -0+38 <[^>]*> edc08100 ? stfp f0, \[r0\] -0+3c <[^>]*> ec608101 ? stfp f0, \[r0\], #-4 -0+40 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] -0+44 <[^>]*> ed900200 ? lfm f0, 4, \[r0\] -0+48 <[^>]*> ed10020c ? lfm f0, 4, \[r0, #-48\] -0+4c <[^>]*> ed800200 ? sfm f0, 4, \[r0\] -0+50 <[^>]*> ed00020c ? sfm f0, 4, \[r0, #-48\] -0+54 <[^>]*> ed800200 ? sfm f0, 4, \[r0\] -0+58 <[^>]*> 5d800100 ? stfpls f0, \[r0\] -0+5c <[^>]*> 5d800100 ? stfpls f0, \[r0\] diff --git a/binutils-2.17/gas/testsuite/gas/arm/fpa-mem.s b/binutils-2.17/gas/testsuite/gas/arm/fpa-mem.s deleted file mode 100644 index bcb4ae3a..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/fpa-mem.s +++ /dev/null @@ -1,32 +0,0 @@ - .text - .globl F -F: - ldfs f0, [r0] - ldfs f0, [r0], #-4 - ldfd f0, [r0] - ldfd f0, [r0], #-4 - ldfe f0, [r0] - ldfe f0, [r0], #-4 - ldfp f0, [r0] - ldfp f0, [r0], #-4 - - stfs f0, [r0] - stfs f0, [r0], #-4 - stfd f0, [r0] - stfd f0, [r0], #-4 - stfe f0, [r0] - stfe f0, [r0], #-4 - stfp f0, [r0] - stfp f0, [r0], #-4 - lfm f0, 4, [r0] - lfmfd f0, 4, [r0] - lfmea f0, 4, [r0] - sfm f0, 4, [r0] - sfmfd f0, 4, [r0] - sfmea f0, 4, [r0] - - # Test mnemonic that is ambiguous between infix and suffic - # condition codes - stfpls f0, [r0] - .syntax unified - stfpls f0, [r0] diff --git a/binutils-2.17/gas/testsuite/gas/arm/fpa-monadic.d b/binutils-2.17/gas/testsuite/gas/arm/fpa-monadic.d deleted file mode 100644 index a688ee4b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/fpa-monadic.d +++ /dev/null @@ -1,202 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: FPA Monadic instructions -#as: -mfpu=fpa -mcpu=arm7m - -# Test FPA Monadic instructions -# This test should work for both big and little-endian assembly. - -.*: *file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> ee008100 ? mvfs f0, f0 -0+004 <[^>]*> ee008120 ? mvfsp f0, f0 -0+008 <[^>]*> ee008140 ? mvfsm f0, f0 -0+00c <[^>]*> ee008160 ? mvfsz f0, f0 -0+010 <[^>]*> ee008180 ? mvfd f0, f0 -0+014 <[^>]*> ee0081a0 ? mvfdp f0, f0 -0+018 <[^>]*> ee0081c0 ? mvfdm f0, f0 -0+01c <[^>]*> ee0081e0 ? mvfdz f0, f0 -0+020 <[^>]*> ee088100 ? mvfe f0, f0 -0+024 <[^>]*> ee088120 ? mvfep f0, f0 -0+028 <[^>]*> ee088140 ? mvfem f0, f0 -0+02c <[^>]*> ee088160 ? mvfez f0, f0 -0+030 <[^>]*> ee108100 ? mnfs f0, f0 -0+034 <[^>]*> ee108120 ? mnfsp f0, f0 -0+038 <[^>]*> ee108140 ? mnfsm f0, f0 -0+03c <[^>]*> ee108160 ? mnfsz f0, f0 -0+040 <[^>]*> ee108180 ? mnfd f0, f0 -0+044 <[^>]*> ee1081a0 ? mnfdp f0, f0 -0+048 <[^>]*> ee1081c0 ? mnfdm f0, f0 -0+04c <[^>]*> ee1081e0 ? mnfdz f0, f0 -0+050 <[^>]*> ee188100 ? mnfe f0, f0 -0+054 <[^>]*> ee188120 ? mnfep f0, f0 -0+058 <[^>]*> ee188140 ? mnfem f0, f0 -0+05c <[^>]*> ee188160 ? mnfez f0, f0 -0+060 <[^>]*> ee208100 ? abss f0, f0 -0+064 <[^>]*> ee208120 ? abssp f0, f0 -0+068 <[^>]*> ee208140 ? abssm f0, f0 -0+06c <[^>]*> ee208160 ? abssz f0, f0 -0+070 <[^>]*> ee208180 ? absd f0, f0 -0+074 <[^>]*> ee2081a0 ? absdp f0, f0 -0+078 <[^>]*> ee2081c0 ? absdm f0, f0 -0+07c <[^>]*> ee2081e0 ? absdz f0, f0 -0+080 <[^>]*> ee288100 ? abse f0, f0 -0+084 <[^>]*> ee288120 ? absep f0, f0 -0+088 <[^>]*> ee288140 ? absem f0, f0 -0+08c <[^>]*> ee288160 ? absez f0, f0 -0+090 <[^>]*> ee308100 ? rnds f0, f0 -0+094 <[^>]*> ee308120 ? rndsp f0, f0 -0+098 <[^>]*> ee308140 ? rndsm f0, f0 -0+09c <[^>]*> ee308160 ? rndsz f0, f0 -0+0a0 <[^>]*> ee308180 ? rndd f0, f0 -0+0a4 <[^>]*> ee3081a0 ? rnddp f0, f0 -0+0a8 <[^>]*> ee3081c0 ? rnddm f0, f0 -0+0ac <[^>]*> ee3081e0 ? rnddz f0, f0 -0+0b0 <[^>]*> ee388100 ? rnde f0, f0 -0+0b4 <[^>]*> ee388120 ? rndep f0, f0 -0+0b8 <[^>]*> ee388140 ? rndem f0, f0 -0+0bc <[^>]*> ee388160 ? rndez f0, f0 -0+0c0 <[^>]*> ee408100 ? sqts f0, f0 -0+0c4 <[^>]*> ee408120 ? sqtsp f0, f0 -0+0c8 <[^>]*> ee408140 ? sqtsm f0, f0 -0+0cc <[^>]*> ee408160 ? sqtsz f0, f0 -0+0d0 <[^>]*> ee408180 ? sqtd f0, f0 -0+0d4 <[^>]*> ee4081a0 ? sqtdp f0, f0 -0+0d8 <[^>]*> ee4081c0 ? sqtdm f0, f0 -0+0dc <[^>]*> ee4081e0 ? sqtdz f0, f0 -0+0e0 <[^>]*> ee488100 ? sqte f0, f0 -0+0e4 <[^>]*> ee488120 ? sqtep f0, f0 -0+0e8 <[^>]*> ee488140 ? sqtem f0, f0 -0+0ec <[^>]*> ee488160 ? sqtez f0, f0 -0+0f0 <[^>]*> ee508100 ? logs f0, f0 -0+0f4 <[^>]*> ee508120 ? logsp f0, f0 -0+0f8 <[^>]*> ee508140 ? logsm f0, f0 -0+0fc <[^>]*> ee508160 ? logsz f0, f0 -0+100 <[^>]*> ee508180 ? logd f0, f0 -0+104 <[^>]*> ee5081a0 ? logdp f0, f0 -0+108 <[^>]*> ee5081c0 ? logdm f0, f0 -0+10c <[^>]*> ee5081e0 ? logdz f0, f0 -0+110 <[^>]*> ee588100 ? loge f0, f0 -0+114 <[^>]*> ee588120 ? logep f0, f0 -0+118 <[^>]*> ee588140 ? logem f0, f0 -0+11c <[^>]*> ee588160 ? logez f0, f0 -0+120 <[^>]*> ee608100 ? lgns f0, f0 -0+124 <[^>]*> ee608120 ? lgnsp f0, f0 -0+128 <[^>]*> ee608140 ? lgnsm f0, f0 -0+12c <[^>]*> ee608160 ? lgnsz f0, f0 -0+130 <[^>]*> ee608180 ? lgnd f0, f0 -0+134 <[^>]*> ee6081a0 ? lgndp f0, f0 -0+138 <[^>]*> ee6081c0 ? lgndm f0, f0 -0+13c <[^>]*> ee6081e0 ? lgndz f0, f0 -0+140 <[^>]*> ee688100 ? lgne f0, f0 -0+144 <[^>]*> ee688120 ? lgnep f0, f0 -0+148 <[^>]*> ee688140 ? lgnem f0, f0 -0+14c <[^>]*> ee688160 ? lgnez f0, f0 -0+150 <[^>]*> ee708100 ? exps f0, f0 -0+154 <[^>]*> ee708120 ? expsp f0, f0 -0+158 <[^>]*> ee708140 ? expsm f0, f0 -0+15c <[^>]*> ee708160 ? expsz f0, f0 -0+160 <[^>]*> ee708180 ? expd f0, f0 -0+164 <[^>]*> ee7081a0 ? expdp f0, f0 -0+168 <[^>]*> ee7081c0 ? expdm f0, f0 -0+16c <[^>]*> ee7081e0 ? expdz f0, f0 -0+170 <[^>]*> ee788100 ? expe f0, f0 -0+174 <[^>]*> ee788120 ? expep f0, f0 -0+178 <[^>]*> ee788140 ? expem f0, f0 -0+17c <[^>]*> ee7081e0 ? expdz f0, f0 -0+180 <[^>]*> ee808100 ? sins f0, f0 -0+184 <[^>]*> ee808120 ? sinsp f0, f0 -0+188 <[^>]*> ee808140 ? sinsm f0, f0 -0+18c <[^>]*> ee808160 ? sinsz f0, f0 -0+190 <[^>]*> ee808180 ? sind f0, f0 -0+194 <[^>]*> ee8081a0 ? sindp f0, f0 -0+198 <[^>]*> ee8081c0 ? sindm f0, f0 -0+19c <[^>]*> ee8081e0 ? sindz f0, f0 -0+1a0 <[^>]*> ee888100 ? sine f0, f0 -0+1a4 <[^>]*> ee888120 ? sinep f0, f0 -0+1a8 <[^>]*> ee888140 ? sinem f0, f0 -0+1ac <[^>]*> ee888160 ? sinez f0, f0 -0+1b0 <[^>]*> ee908100 ? coss f0, f0 -0+1b4 <[^>]*> ee908120 ? cossp f0, f0 -0+1b8 <[^>]*> ee908140 ? cossm f0, f0 -0+1bc <[^>]*> ee908160 ? cossz f0, f0 -0+1c0 <[^>]*> ee908180 ? cosd f0, f0 -0+1c4 <[^>]*> ee9081a0 ? cosdp f0, f0 -0+1c8 <[^>]*> ee9081c0 ? cosdm f0, f0 -0+1cc <[^>]*> ee9081e0 ? cosdz f0, f0 -0+1d0 <[^>]*> ee988100 ? cose f0, f0 -0+1d4 <[^>]*> ee988120 ? cosep f0, f0 -0+1d8 <[^>]*> ee988140 ? cosem f0, f0 -0+1dc <[^>]*> ee988160 ? cosez f0, f0 -0+1e0 <[^>]*> eea08100 ? tans f0, f0 -0+1e4 <[^>]*> eea08120 ? tansp f0, f0 -0+1e8 <[^>]*> eea08140 ? tansm f0, f0 -0+1ec <[^>]*> eea08160 ? tansz f0, f0 -0+1f0 <[^>]*> eea08180 ? tand f0, f0 -0+1f4 <[^>]*> eea081a0 ? tandp f0, f0 -0+1f8 <[^>]*> eea081c0 ? tandm f0, f0 -0+1fc <[^>]*> eea081e0 ? tandz f0, f0 -0+200 <[^>]*> eea88100 ? tane f0, f0 -0+204 <[^>]*> eea88120 ? tanep f0, f0 -0+208 <[^>]*> eea88140 ? tanem f0, f0 -0+20c <[^>]*> eea88160 ? tanez f0, f0 -0+210 <[^>]*> eeb08100 ? asns f0, f0 -0+214 <[^>]*> eeb08120 ? asnsp f0, f0 -0+218 <[^>]*> eeb08140 ? asnsm f0, f0 -0+21c <[^>]*> eeb08160 ? asnsz f0, f0 -0+220 <[^>]*> eeb08180 ? asnd f0, f0 -0+224 <[^>]*> eeb081a0 ? asndp f0, f0 -0+228 <[^>]*> eeb081c0 ? asndm f0, f0 -0+22c <[^>]*> eeb081e0 ? asndz f0, f0 -0+230 <[^>]*> eeb88100 ? asne f0, f0 -0+234 <[^>]*> eeb88120 ? asnep f0, f0 -0+238 <[^>]*> eeb88140 ? asnem f0, f0 -0+23c <[^>]*> eeb88160 ? asnez f0, f0 -0+240 <[^>]*> eec08100 ? acss f0, f0 -0+244 <[^>]*> eec08120 ? acssp f0, f0 -0+248 <[^>]*> eec08140 ? acssm f0, f0 -0+24c <[^>]*> eec08160 ? acssz f0, f0 -0+250 <[^>]*> eec08180 ? acsd f0, f0 -0+254 <[^>]*> eec081a0 ? acsdp f0, f0 -0+258 <[^>]*> eec081c0 ? acsdm f0, f0 -0+25c <[^>]*> eec081e0 ? acsdz f0, f0 -0+260 <[^>]*> eec88100 ? acse f0, f0 -0+264 <[^>]*> eec88120 ? acsep f0, f0 -0+268 <[^>]*> eec88140 ? acsem f0, f0 -0+26c <[^>]*> eec88160 ? acsez f0, f0 -0+270 <[^>]*> eed08100 ? atns f0, f0 -0+274 <[^>]*> eed08120 ? atnsp f0, f0 -0+278 <[^>]*> eed08140 ? atnsm f0, f0 -0+27c <[^>]*> eed08160 ? atnsz f0, f0 -0+280 <[^>]*> eed08180 ? atnd f0, f0 -0+284 <[^>]*> eed081a0 ? atndp f0, f0 -0+288 <[^>]*> eed081c0 ? atndm f0, f0 -0+28c <[^>]*> eed081e0 ? atndz f0, f0 -0+290 <[^>]*> eed88100 ? atne f0, f0 -0+294 <[^>]*> eed88120 ? atnep f0, f0 -0+298 <[^>]*> eed88140 ? atnem f0, f0 -0+29c <[^>]*> eed88160 ? atnez f0, f0 -0+2a0 <[^>]*> eee08100 ? urds f0, f0 -0+2a4 <[^>]*> eee08120 ? urdsp f0, f0 -0+2a8 <[^>]*> eee08140 ? urdsm f0, f0 -0+2ac <[^>]*> eee08160 ? urdsz f0, f0 -0+2b0 <[^>]*> eee08180 ? urdd f0, f0 -0+2b4 <[^>]*> eee081a0 ? urddp f0, f0 -0+2b8 <[^>]*> eee081c0 ? urddm f0, f0 -0+2bc <[^>]*> eee081e0 ? urddz f0, f0 -0+2c0 <[^>]*> eee88100 ? urde f0, f0 -0+2c4 <[^>]*> eee88120 ? urdep f0, f0 -0+2c8 <[^>]*> eee88140 ? urdem f0, f0 -0+2cc <[^>]*> eee88160 ? urdez f0, f0 -0+2d0 <[^>]*> eef08100 ? nrms f0, f0 -0+2d4 <[^>]*> eef08120 ? nrmsp f0, f0 -0+2d8 <[^>]*> eef08140 ? nrmsm f0, f0 -0+2dc <[^>]*> eef08160 ? nrmsz f0, f0 -0+2e0 <[^>]*> eef08180 ? nrmd f0, f0 -0+2e4 <[^>]*> eef081a0 ? nrmdp f0, f0 -0+2e8 <[^>]*> eef081c0 ? nrmdm f0, f0 -0+2ec <[^>]*> eef081e0 ? nrmdz f0, f0 -0+2f0 <[^>]*> eef88100 ? nrme f0, f0 -0+2f4 <[^>]*> eef88120 ? nrmep f0, f0 -0+2f8 <[^>]*> eef88140 ? nrmem f0, f0 -0+2fc <[^>]*> eef88160 ? nrmez f0, f0 diff --git a/binutils-2.17/gas/testsuite/gas/arm/fpa-monadic.s b/binutils-2.17/gas/testsuite/gas/arm/fpa-monadic.s deleted file mode 100644 index 2af03f4e..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/fpa-monadic.s +++ /dev/null @@ -1,210 +0,0 @@ - .text - .globl F -F: - mvfs f0, f0 - mvfsp f0, f0 - mvfsm f0, f0 - mvfsz f0, f0 - mvfd f0, f0 - mvfdp f0, f0 - mvfdm f0, f0 - mvfdz f0, f0 - mvfe f0, f0 - mvfep f0, f0 - mvfem f0, f0 - mvfez f0, f0 - - mnfs f0, f0 - mnfsp f0, f0 - mnfsm f0, f0 - mnfsz f0, f0 - mnfd f0, f0 - mnfdp f0, f0 - mnfdm f0, f0 - mnfdz f0, f0 - mnfe f0, f0 - mnfep f0, f0 - mnfem f0, f0 - mnfez f0, f0 - - abss f0, f0 - abssp f0, f0 - abssm f0, f0 - abssz f0, f0 - absd f0, f0 - absdp f0, f0 - absdm f0, f0 - absdz f0, f0 - abse f0, f0 - absep f0, f0 - absem f0, f0 - absez f0, f0 - - rnds f0, f0 - rndsp f0, f0 - rndsm f0, f0 - rndsz f0, f0 - rndd f0, f0 - rnddp f0, f0 - rnddm f0, f0 - rnddz f0, f0 - rnde f0, f0 - rndep f0, f0 - rndem f0, f0 - rndez f0, f0 - - sqts f0, f0 - sqtsp f0, f0 - sqtsm f0, f0 - sqtsz f0, f0 - sqtd f0, f0 - sqtdp f0, f0 - sqtdm f0, f0 - sqtdz f0, f0 - sqte f0, f0 - sqtep f0, f0 - sqtem f0, f0 - sqtez f0, f0 - - logs f0, f0 - logsp f0, f0 - logsm f0, f0 - logsz f0, f0 - logd f0, f0 - logdp f0, f0 - logdm f0, f0 - logdz f0, f0 - loge f0, f0 - logep f0, f0 - logem f0, f0 - logez f0, f0 - - lgns f0, f0 - lgnsp f0, f0 - lgnsm f0, f0 - lgnsz f0, f0 - lgnd f0, f0 - lgndp f0, f0 - lgndm f0, f0 - lgndz f0, f0 - lgne f0, f0 - lgnep f0, f0 - lgnem f0, f0 - lgnez f0, f0 - - exps f0, f0 - expsp f0, f0 - expsm f0, f0 - expsz f0, f0 - expd f0, f0 - expdp f0, f0 - expdm f0, f0 - expdz f0, f0 - expe f0, f0 - expep f0, f0 - expem f0, f0 - expdz f0, f0 - - sins f0, f0 - sinsp f0, f0 - sinsm f0, f0 - sinsz f0, f0 - sind f0, f0 - sindp f0, f0 - sindm f0, f0 - sindz f0, f0 - sine f0, f0 - sinep f0, f0 - sinem f0, f0 - sinez f0, f0 - - coss f0, f0 - cossp f0, f0 - cossm f0, f0 - cossz f0, f0 - cosd f0, f0 - cosdp f0, f0 - cosdm f0, f0 - cosdz f0, f0 - cose f0, f0 - cosep f0, f0 - cosem f0, f0 - cosez f0, f0 - - tans f0, f0 - tansp f0, f0 - tansm f0, f0 - tansz f0, f0 - tand f0, f0 - tandp f0, f0 - tandm f0, f0 - tandz f0, f0 - tane f0, f0 - tanep f0, f0 - tanem f0, f0 - tanez f0, f0 - - asns f0, f0 - asnsp f0, f0 - asnsm f0, f0 - asnsz f0, f0 - asnd f0, f0 - asndp f0, f0 - asndm f0, f0 - asndz f0, f0 - asne f0, f0 - asnep f0, f0 - asnem f0, f0 - asnez f0, f0 - - acss f0, f0 - acssp f0, f0 - acssm f0, f0 - acssz f0, f0 - acsd f0, f0 - acsdp f0, f0 - acsdm f0, f0 - acsdz f0, f0 - acse f0, f0 - acsep f0, f0 - acsem f0, f0 - acsez f0, f0 - - atns f0, f0 - atnsp f0, f0 - atnsm f0, f0 - atnsz f0, f0 - atnd f0, f0 - atndp f0, f0 - atndm f0, f0 - atndz f0, f0 - atne f0, f0 - atnep f0, f0 - atnem f0, f0 - atnez f0, f0 - - urds f0, f0 - urdsp f0, f0 - urdsm f0, f0 - urdsz f0, f0 - urdd f0, f0 - urddp f0, f0 - urddm f0, f0 - urddz f0, f0 - urde f0, f0 - urdep f0, f0 - urdem f0, f0 - urdez f0, f0 - - nrms f0, f0 - nrmsp f0, f0 - nrmsm f0, f0 - nrmsz f0, f0 - nrmd f0, f0 - nrmdp f0, f0 - nrmdm f0, f0 - nrmdz f0, f0 - nrme f0, f0 - nrmep f0, f0 - nrmem f0, f0 - nrmez f0, f0 diff --git a/binutils-2.17/gas/testsuite/gas/arm/immed.d b/binutils-2.17/gas/testsuite/gas/arm/immed.d deleted file mode 100644 index 62b7eb72..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/immed.d +++ /dev/null @@ -1,16 +0,0 @@ -# name: immediate expressions -# as: -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+0000 <[^>]+> e3a00000 ? mov r0, #0 ; 0x0 -0+0004 <[^>]+> e3e00003 ? mvn r0, #3 ; 0x3 -0+0008 <[^>]+> e51f0010 ? ldr r0, \[pc, #-16\] ; 0+0 <[^>]+> -0+000c <[^>]+> e51f0014 ? ldr r0, \[pc, #-20\] ; 0+0 <[^>]+> - \.\.\. -0+1010 <[^>]+> e3a00008 ? mov r0, #8 ; 0x8 -0+1014 <[^>]+> e59f00e4 ? ldr r0, \[pc, #228\] ; 0+1100 <[^>]+> -0+1018 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+101c <[^>]+> e1a00000 ? nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/immed.s b/binutils-2.17/gas/testsuite/gas/arm/immed.s deleted file mode 100644 index 400f628f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/immed.s +++ /dev/null @@ -1,15 +0,0 @@ -@ Tests for complex immediate expressions - none of these need -@ relocations - .text -bar: - mov r0, #0 - mov r0, #(. - bar - 8) - ldr r0, bar - ldr r0, [pc, # (bar - . -8)] - .space 4096 - mov r0, #(. - bar - 8) & 0xff - ldr r0, [pc, # (bar - . -8) & 0xff] - - @ section padding for a.out's benefit - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/inst.d b/binutils-2.17/gas/testsuite/gas/arm/inst.d deleted file mode 100644 index fbf27b4a..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/inst.d +++ /dev/null @@ -1,203 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM basic instructions -#as: -mcpu=arm7m -EL -# WinCE has its own version of this test. -#skip: *-wince-* - -# Test the standard ARM instructions: - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 -0+004 <[^>]*> e1a01002 ? mov r1, r2 -0+008 <[^>]*> e1a03184 ? mov r3, r4, lsl #3 -0+00c <[^>]*> e1a05736 ? mov r5, r6, lsr r7 -0+010 <[^>]*> e1a08a59 ? mov r8, r9, asr sl -0+014 <[^>]*> e1a0bd1c ? mov fp, ip, lsl sp -0+018 <[^>]*> e1a0e06f ? mov lr, pc, rrx -0+01c <[^>]*> e1a01002 ? mov r1, r2 -0+020 <[^>]*> 01a02003 ? moveq r2, r3 -0+024 <[^>]*> 11a04005 ? movne r4, r5 -0+028 <[^>]*> b1a06007 ? movlt r6, r7 -0+02c <[^>]*> a1a08009 ? movge r8, r9 -0+030 <[^>]*> d1a0a00b ? movle sl, fp -0+034 <[^>]*> c1a0c00d ? movgt ip, sp -0+038 <[^>]*> 31a01002 ? movcc r1, r2 -0+03c <[^>]*> 21a01003 ? movcs r1, r3 -0+040 <[^>]*> 41a03006 ? movmi r3, r6 -0+044 <[^>]*> 51a07009 ? movpl r7, r9 -0+048 <[^>]*> 61a01008 ? movvs r1, r8 -0+04c <[^>]*> 71a09fa1 ? movvc r9, r1, lsr #31 -0+050 <[^>]*> 81a0800f ? movhi r8, pc -0+054 <[^>]*> 91a0f00e ? movls pc, lr -0+058 <[^>]*> 21a09008 ? movcs r9, r8 -0+05c <[^>]*> 31a01003 ? movcc r1, r3 -0+060 <[^>]*> e1b00008 ? movs r0, r8 -0+064 <[^>]*> 31b00007 ? movccs r0, r7 -0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa -0+06c <[^>]*> e0832004 ? add r2, r3, r4 -0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 -0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1 -0+078 <[^>]*> e201000a ? and r0, r1, #10 ; 0xa -0+07c <[^>]*> e0032004 ? and r2, r3, r4 -0+080 <[^>]*> e0065287 ? and r5, r6, r7, lsl #5 -0+084 <[^>]*> e0021113 ? and r1, r2, r3, lsl r1 -0+088 <[^>]*> e221000a ? eor r0, r1, #10 ; 0xa -0+08c <[^>]*> e0232004 ? eor r2, r3, r4 -0+090 <[^>]*> e0265287 ? eor r5, r6, r7, lsl #5 -0+094 <[^>]*> e0221113 ? eor r1, r2, r3, lsl r1 -0+098 <[^>]*> e241000a ? sub r0, r1, #10 ; 0xa -0+09c <[^>]*> e0432004 ? sub r2, r3, r4 -0+0a0 <[^>]*> e0465287 ? sub r5, r6, r7, lsl #5 -0+0a4 <[^>]*> e0421113 ? sub r1, r2, r3, lsl r1 -0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 ; 0xa -0+0ac <[^>]*> e0a32004 ? adc r2, r3, r4 -0+0b0 <[^>]*> e0a65287 ? adc r5, r6, r7, lsl #5 -0+0b4 <[^>]*> e0a21113 ? adc r1, r2, r3, lsl r1 -0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 ; 0xa -0+0bc <[^>]*> e0c32004 ? sbc r2, r3, r4 -0+0c0 <[^>]*> e0c65287 ? sbc r5, r6, r7, lsl #5 -0+0c4 <[^>]*> e0c21113 ? sbc r1, r2, r3, lsl r1 -0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 ; 0xa -0+0cc <[^>]*> e0632004 ? rsb r2, r3, r4 -0+0d0 <[^>]*> e0665287 ? rsb r5, r6, r7, lsl #5 -0+0d4 <[^>]*> e0621113 ? rsb r1, r2, r3, lsl r1 -0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 ; 0xa -0+0dc <[^>]*> e0e32004 ? rsc r2, r3, r4 -0+0e0 <[^>]*> e0e65287 ? rsc r5, r6, r7, lsl #5 -0+0e4 <[^>]*> e0e21113 ? rsc r1, r2, r3, lsl r1 -0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 ; 0xa -0+0ec <[^>]*> e1832004 ? orr r2, r3, r4 -0+0f0 <[^>]*> e1865287 ? orr r5, r6, r7, lsl #5 -0+0f4 <[^>]*> e1821113 ? orr r1, r2, r3, lsl r1 -0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 ; 0xa -0+0fc <[^>]*> e1c32004 ? bic r2, r3, r4 -0+100 <[^>]*> e1c65287 ? bic r5, r6, r7, lsl #5 -0+104 <[^>]*> e1c21113 ? bic r1, r2, r3, lsl r1 -0+108 <[^>]*> e3e0000a ? mvn r0, #10 ; 0xa -0+10c <[^>]*> e1e02004 ? mvn r2, r4 -0+110 <[^>]*> e1e05287 ? mvn r5, r7, lsl #5 -0+114 <[^>]*> e1e01113 ? mvn r1, r3, lsl r1 -0+118 <[^>]*> e310000a ? tst r0, #10 ; 0xa -0+11c <[^>]*> e1120004 ? tst r2, r4 -0+120 <[^>]*> e1150287 ? tst r5, r7, lsl #5 -0+124 <[^>]*> e1110113 ? tst r1, r3, lsl r1 -0+128 <[^>]*> e330000a ? teq r0, #10 ; 0xa -0+12c <[^>]*> e1320004 ? teq r2, r4 -0+130 <[^>]*> e1350287 ? teq r5, r7, lsl #5 -0+134 <[^>]*> e1310113 ? teq r1, r3, lsl r1 -0+138 <[^>]*> e350000a ? cmp r0, #10 ; 0xa -0+13c <[^>]*> e1520004 ? cmp r2, r4 -0+140 <[^>]*> e1550287 ? cmp r5, r7, lsl #5 -0+144 <[^>]*> e1510113 ? cmp r1, r3, lsl r1 -0+148 <[^>]*> e370000a ? cmn r0, #10 ; 0xa -0+14c <[^>]*> e1720004 ? cmn r2, r4 -0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 -0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 ; 0xa -0+15c <[^>]*> e132f004 ? teqp r2, r4 -0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 ; 0xa -0+16c <[^>]*> e172f004 ? cmnp r2, r4 -0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 ; 0xa -0+17c <[^>]*> e152f004 ? cmpp r2, r4 -0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 ; 0xa -0+18c <[^>]*> e112f004 ? tstp r2, r4 -0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 -0+198 <[^>]*> e0000291 ? mul r0, r1, r2 -0+19c <[^>]*> e0110392 ? muls r1, r2, r3 -0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 -0+1a4 <[^>]*> 90190798 ? mullss r9, r8, r7 -0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp -0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip -0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp -0+1b4 <[^>]*> a034e391 ? mlages r4, r1, r3, lr -0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] -0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] -0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! -0+1c4 <[^>]*> e5922020 ? ldr r2, \[r2, #32\] -0+1c8 <[^>]*> e7932424 ? ldr r2, \[r3, r4, lsr #8\] -0+1cc <[^>]*> 07b54484 ? ldreq r4, \[r5, r4, lsl #9\]! -0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6 -0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3 -0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 -0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> -0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] -0+1e4 <[^>]*> 14f85000 ? ldrnebt r5, \[r8\] -0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] -0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] -0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! -0+1f4 <[^>]*> e5822020 ? str r2, \[r2, #32\] -0+1f8 <[^>]*> e7832424 ? str r2, \[r3, r4, lsr #8\] -0+1fc <[^>]*> 07a54484 ? streq r4, \[r5, r4, lsl #9\]! -0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6 -0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3 -0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8 -0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> -0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] -0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] -0+218 <[^>]*> e8900002 ? ldmia r0, {r1} -0+21c <[^>]*> 09920038 ? ldmeqib r2, {r3, r4, r5} -0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ -0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} -0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} -0+22c <[^>]*> e89201f8 ? ldmia r2, {r3, r4, r5, r6, r7, r8} -0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} -0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ -0+238 <[^>]*> e8800002 ? stmia r0, {r1} -0+23c <[^>]*> 09820038 ? stmeqib r2, {r3, r4, r5} -0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ -0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} -0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} -0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} -0+250 <[^>]*> e8830003 ? stmia r3, {r0, r1} -0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ -0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 -0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 -0+260 <[^>]*> eb...... ? bl 0[0123456789abcdef]+ <[^>]*> -[ ]*260:.*_wombat.* -0+264 <[^>]*> 5b...... ? blpl 0[0123456789abcdef]+ <[^>]*> -[ ]*264:.*ARM.*hohum.* -0+268 <[^>]*> ea...... ? b 0[0123456789abcdef]+ <[^>]*> -[ ]*268:.*_wibble.* -0+26c <[^>]*> da...... ? ble 0[0123456789abcdef]+ <[^>]*> -[ ]*26c:.*testerfunc.* -0+270 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 -0+274 <[^>]*> e1a01002 ? mov r1, r2 -0+278 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+27c <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+280 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+284 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+288 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+28c <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+290 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+294 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+298 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+29c <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2a0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2a4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2a8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ac <[^>]*> e1a01062 ? mov r1, r2, rrx -0+2b0 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 -0+2b4 <[^>]*> e1a01002 ? mov r1, r2 -0+2b8 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+2bc <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+2c0 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+2c4 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+2c8 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+2cc <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+2d0 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+2d4 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+2d8 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+2dc <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2e0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2e4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2e8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ec <[^>]*> e1a01062 ? mov r1, r2, rrx diff --git a/binutils-2.17/gas/testsuite/gas/arm/inst.s b/binutils-2.17/gas/testsuite/gas/arm/inst.s deleted file mode 100644 index ef5f7a79..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/inst.s +++ /dev/null @@ -1,223 +0,0 @@ -@ Test file for ARM/GAS -- basic instructions - -.text -.align - mov r0, #0 - mov r1, r2 - mov r3, r4, lsl #3 - mov r5, r6, lsr r7 - mov r8, r9, asr r10 - mov r11, r12, asl r13 - mov r14, r15, rrx - moval a2, a3 - moveq a3, a4 - movne v1, v2 - movlt v3, v4 - movge v5, v6 - movle v7, v8 - movgt ip, sp - movcc r1, r2 - movcs r1, r3 - movmi r3, r6 - movpl wr, sb - movvs r1, r8 - movvc SB, r1, lsr #31 - movhi r8, pc - movls PC, lr - movhs r9, r8 - movul r1, r3 - movs r0, r8 - movuls r0, WR - - add r0, r1, #10 - add r2, r3, r4 - add r5, r6, r7, asl #5 - add r1, r2, r3, lsl r1 - - and r0, r1, #10 - and r2, r3, r4 - and r5, r6, r7, asl #5 - and r1, r2, r3, lsl r1 - - eor r0, r1, #10 - eor r2, r3, r4 - eor r5, r6, r7, asl #5 - eor r1, r2, r3, lsl r1 - - sub r0, r1, #10 - sub r2, r3, r4 - sub r5, r6, r7, asl #5 - sub r1, r2, r3, lsl r1 - - adc r0, r1, #10 - adc r2, r3, r4 - adc r5, r6, r7, asl #5 - adc r1, r2, r3, lsl r1 - - sbc r0, r1, #10 - sbc r2, r3, r4 - sbc r5, r6, r7, asl #5 - sbc r1, r2, r3, lsl r1 - - rsb r0, r1, #10 - rsb r2, r3, r4 - rsb r5, r6, r7, asl #5 - rsb r1, r2, r3, lsl r1 - - rsc r0, r1, #10 - rsc r2, r3, r4 - rsc r5, r6, r7, asl #5 - rsc r1, r2, r3, lsl r1 - - orr r0, r1, #10 - orr r2, r3, r4 - orr r5, r6, r7, asl #5 - orr r1, r2, r3, lsl r1 - - bic r0, r1, #10 - bic r2, r3, r4 - bic r5, r6, r7, asl #5 - bic r1, r2, r3, lsl r1 - - mvn r0, #10 - mvn r2, r4 - mvn r5, r7, asl #5 - mvn r1, r3, lsl r1 - - tst r0, #10 - tst r2, r4 - tst r5, r7, asl #5 - tst r1, r3, lsl r1 - - teq r0, #10 - teq r2, r4 - teq r5, r7, asl #5 - teq r1, r3, lsl r1 - - cmp r0, #10 - cmp r2, r4 - cmp r5, r7, asl #5 - cmp r1, r3, lsl r1 - - cmn r0, #10 - cmn r2, r4 - cmn r5, r7, asl #5 - cmn r1, r3, lsl r1 - - teqp r0, #10 - teqp r2, r4 - teqp r5, r7, asl #5 - teqp r1, r3, lsl r1 - - cmnp r0, #10 - cmnp r2, r4 - cmnp r5, r7, asl #5 - cmnp r1, r3, lsl r1 - - cmpp r0, #10 - cmpp r2, r4 - cmpp r5, r7, asl #5 - cmpp r1, r3, lsl r1 - - tstp r0, #10 - tstp r2, r4 - tstp r5, r7, asl #5 - tstp r1, r3, lsl r1 - - mul r0, r1, r2 - muls r1, r2, r3 - mulne r0, r1, r0 - mullss r9, r8, r7 - - mla r1, r9, sl, fp - mlas r3, r4, r9, IP - mlalt r9, r8, r7, SP - mlages r4, r1, r3, LR - - ldr r0, [r1] - ldr r1, [r1, r2] - ldr r2, [r3, r4]! - ldr r2, [r2, #32] - ldr r2, [r3, r4, lsr #8] - ldreq r4, [r5, r4, asl #9]! - ldrne r4, [r5], #6 - ldrt r1, [r2], r3 - ldr r2, [r4], r5, lsr #8 -foo: - ldr r0, foo - ldrb r3, [r4] - ldrnebt r5, [r8] - - str r0, [r1] - str r1, [r1, r2] - str r3, [r4, r3]! - str r2, [r2, #32] - str r2, [r3, r4, lsr #8] - streq r4, [r5, r4, asl #9]! - strne r4, [r5], #6 - str r1, [r2], r3 - strt r2, [r4], r5, lsr #8 - str r1, bar -bar: - stralb r1, [r7] - strbt r2, [r0] - - ldmia r0, {r1} - ldmeqib r2, {r3, r4, r5} - ldmalda r3, {r0-r15}^ - ldmdb FP!, {r0-r8, SL} - ldmed r1, {r0, r1, r2}|0xf0 - ldmfd r2, {r3, r4}+{r5, r6, r7, r8} - ldmea r3, 3 - ldmfa r4, {r8, r9}^ - - stmia r0, {r1} - stmeqib r2, {r3, r4, r5} - stmalda r3, {r0-r15}^ - stmdb r11!, {r0-r8, r10} - stmed r1, {r0, r1, r2} - stmfd r2, {r3, r4} - stmea r3, 3 - stmfa r4, {r8, r9}^ - - swi 0x123456 - swihs 0x33 - - bl _wombat - blpl hohum - b _wibble - ble testerfunc - - mov r1, r2, lsl #2 - mov r1, r2, lsl #0 - mov r1, r2, lsl #31 - mov r1, r2, lsl r3 - mov r1, r2, lsr #2 - mov r1, r2, lsr #31 - mov r1, r2, lsr #32 - mov r1, r2, lsr r3 - mov r1, r2, asr #2 - mov r1, r2, asr #31 - mov r1, r2, asr #32 - mov r1, r2, asr r3 - mov r1, r2, ror #2 - mov r1, r2, ror #31 - mov r1, r2, ror r3 - mov r1, r2, rrx - mov r1, r2, LSL #2 - mov r1, r2, LSL #0 - mov r1, r2, LSL #31 - mov r1, r2, LSL r3 - mov r1, r2, LSR #2 - mov r1, r2, LSR #31 - mov r1, r2, LSR #32 - mov r1, r2, LSR r3 - mov r1, r2, ASR #2 - mov r1, r2, ASR #31 - mov r1, r2, ASR #32 - mov r1, r2, ASR r3 - mov r1, r2, ROR #2 - mov r1, r2, ROR #31 - mov r1, r2, ROR r3 - mov r1, r2, RRX -
\ No newline at end of file diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.d b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.d deleted file mode 100644 index 6b44634c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: iWMMXt errors -#as: -mcpu=iwmmxt -#error-output: iwmmxt-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.l b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.l deleted file mode 100644 index 65889380..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.l +++ /dev/null @@ -1,10 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:1: Error: instruction cannot be conditional -- `wldrwgt wcgr0,\[r1\]' -[^:]*:2: Error: iWMMXt data register expected -- `wldrb wcgr0,\[r1\]' -[^:]*:3: Error: iWMMXt data register expected -- `wldrh wcgr0,\[r1\]' -[^:]*:4: Error: iWMMXt data register expected -- `wldrd wcgr0,\[r1\]' -[^:]*:5: Error: instruction cannot be conditional -- `wstrwgt wcgr0,\[r1\]' -[^:]*:6: Error: iWMMXt data register expected -- `wstrb wcgr0,\[r1\]' -[^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]' -[^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]' -[^:]*:9: Error: iWMMXt control register expected -- `tmcr wibble,r1' diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.s b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.s deleted file mode 100644 index 47d8d71f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad.s +++ /dev/null @@ -1,9 +0,0 @@ - wldrwgt wcgr0,[r1] - wldrb wcgr0,[r1] - wldrh wcgr0,[r1] - wldrd wcgr0,[r1] - wstrwgt wcgr0,[r1] - wstrb wcgr0,[r1] - wstrh wcgr0,[r1] - wstrd wcgr0,[r1] - tmcr wibble,r1 diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.d b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.d deleted file mode 100644 index c8587a4c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: iWMMXt CoProcessor offset errors -#as: -mcpu=iwmmxt -#error-output: iwmmxt-bad2.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.l b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.l deleted file mode 100644 index 1a43ebcd..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.l +++ /dev/null @@ -1,7 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:1: Error: co-processor offset out of range -[^:]*:2: Error: co-processor offset out of range -[^:]*:3: Error: co-processor offset out of range -[^:]*:4: Error: co-processor offset out of range -[^:]*:5: Error: co-processor offset out of range -[^:]*:6: Error: co-processor offset out of range diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.s b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.s deleted file mode 100644 index dc559a89..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt-bad2.s +++ /dev/null @@ -1,6 +0,0 @@ - wldrd wr1, [r0, #3] - wstrd wr1, [r0, #0x400] - wstrb wr1, [r0, #0x100] - wstrh wr1, [r0, #0x100] - wldrb wr1, [r0, #-0x100] - wldrh wr1, [r0, #-0x100] diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt.d b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt.d deleted file mode 100644 index 494199d2..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt.d +++ /dev/null @@ -1,171 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -miwmmxt -#name: Intel(r) Wireless MMX(tm) technology instructions -#as: -mcpu=xscale+iwmmxt -EL - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <iwmmxt> ee13f130[ ]+tandcb[ ]+pc -0+04 <[^>]*> de53f130[ ]+tandchle[ ]+pc -0+08 <[^>]*> ae93f130[ ]+tandcwge[ ]+pc -0+0c <[^>]*> be401010[ ]+tbcstblt[ ]+wr0, r1 -0+10 <[^>]*> ee412050[ ]+tbcsth[ ]+wr1, r2 -0+14 <[^>]*> ce423090[ ]+tbcstwgt[ ]+wr2, r3 -0+18 <[^>]*> ee13f177[ ]+textrcb[ ]+pc, #7 -0+1c <[^>]*> 0e53f172[ ]+textrcheq[ ]+pc, #2 -0+20 <[^>]*> ee93f170[ ]+textrcw[ ]+pc, #0 -0+24 <[^>]*> ee13e076[ ]+textrmub[ ]+lr, wr3, #6 -0+28 <[^>]*> 1e14d07d[ ]+textrmsbne[ ]+sp, wr4, #5 -0+2c <[^>]*> ee55c072[ ]+textrmuh[ ]+ip, wr5, #2 -0+30 <[^>]*> ee56b078[ ]+textrmsh[ ]+fp, wr6, #0 -0+34 <[^>]*> 2e97a071[ ]+textrmuwcs[ ]+sl, wr7, #1 -0+38 <[^>]*> 2e989078[ ]+textrmswcs[ ]+r9, wr8, #0 -0+3c <[^>]*> ee698014[ ]+tinsrb[ ]+wr9, r8, #4 -0+40 <[^>]*> 3e6a7050[ ]+tinsrhcc[ ]+wr10, r7, #0 -0+44 <[^>]*> ee6b6091[ ]+tinsrw[ ]+wr11, r6, #1 -0+48 <[^>]*> 3e005110[ ]+tmcrcc[ ]+wcid, r5 -0+4c <[^>]*> ec47600c[ ]+tmcrr[ ]+wr12, r6, r7 -0+50 <[^>]*> 3e2041b5[ ]+tmiacc[ ]+wr13, r5, r4 -0+54 <[^>]*> 4e2821d3[ ]+tmiaphmi[ ]+wr14, r3, r2 -0+58 <[^>]*> ee2c11f0[ ]+tmiabb[ ]+wr15, r0, r1 -0+5c <[^>]*> 5e2d31b2[ ]+tmiabtpl[ ]+wr13, r2, r3 -0+60 <[^>]*> 6e2d5034[ ]+tmiabtvs[ ]+wr1, r4, r5 -0+64 <[^>]*> 7e2f7056[ ]+tmiattvc[ ]+wr2, r6, r7 -0+68 <[^>]*> ee138030[ ]+tmovmskb[ ]+r8, wr3 -0+6c <[^>]*> 8e549030[ ]+tmovmskhhi[ ]+r9, wr4 -0+70 <[^>]*> 9e95a030[ ]+tmovmskwls[ ]+sl, wr5 -0+74 <[^>]*> ee11b110[ ]+tmrc[ ]+fp, wcon -0+78 <[^>]*> ac5dc006[ ]+tmrrcge[ ]+ip, sp, wr6 -0+7c <[^>]*> ee13f150[ ]+torcb[ ]+pc -0+80 <[^>]*> be53f150[ ]+torchlt[ ]+pc -0+84 <[^>]*> ee93f150[ ]+torcw[ ]+pc -0+88 <[^>]*> ee0871c0[ ]+waccb[ ]+wr7, wr8 -0+8c <[^>]*> be4a91c0[ ]+wacchlt[ ]+wr9, wr10 -0+90 <[^>]*> ce8cb1c0[ ]+waccwgt[ ]+wr11, wr12 -0+94 <[^>]*> de0ed18f[ ]+waddble[ ]+wr13, wr14, wr15 -0+98 <[^>]*> ee120184[ ]+waddbus[ ]+wr0, wr2, wr4 -0+9c <[^>]*> ee38618a[ ]+waddbss[ ]+wr6, wr8, wr10 -0+a0 <[^>]*> ee4ec18f[ ]+waddh[ ]+wr12, wr14, wr15 -0+a4 <[^>]*> de5cd18b[ ]+waddhusle[ ]+wr13, wr12, wr11 -0+a8 <[^>]*> 0e79a188[ ]+waddhsseq[ ]+wr10, wr9, wr8 -0+ac <[^>]*> 1e867185[ ]+waddwne[ ]+wr7, wr6, wr5 -0+b0 <[^>]*> ee934182[ ]+waddwus[ ]+wr4, wr3, wr2 -0+b4 <[^>]*> 2eb0118f[ ]+waddwsscs[ ]+wr1, wr0, wr15 -0+b8 <[^>]*> ee553027[ ]+waligni[ ]+wr3, wr5, wr7, #5 -0+bc <[^>]*> 2e8b902d[ ]+walignr0cs[ ]+wr9, wr11, wr13 -0+c0 <[^>]*> ee967025[ ]+walignr1[ ]+wr7, wr6, wr5 -0+c4 <[^>]*> 3ea42028[ ]+walignr2cc[ ]+wr2, wr4, wr8 -0+c8 <[^>]*> 3eb95021[ ]+walignr3cc[ ]+wr5, wr9, wr1 -0+cc <[^>]*> ee283001[ ]+wand[ ]+wr3, wr8, wr1 -0+d0 <[^>]*> ee323006[ ]+wandn[ ]+wr3, wr2, wr6 -0+d4 <[^>]*> ee887009[ ]+wavg2b[ ]+wr7, wr8, wr9 -0+d8 <[^>]*> decba00c[ ]+wavg2hle[ ]+wr10, wr11, wr12 -0+dc <[^>]*> ae9ed00f[ ]+wavg2brge[ ]+wr13, wr14, wr15 -0+e0 <[^>]*> eed1000c[ ]+wavg2hr[ ]+wr0, wr1, wr12 -0+e4 <[^>]*> ee04d065[ ]+wcmpeqb[ ]+wr13, wr4, wr5 -0+e8 <[^>]*> 0e474060[ ]+wcmpeqheq[ ]+wr4, wr7, wr0 -0+ec <[^>]*> be896068[ ]+wcmpeqwlt[ ]+wr6, wr9, wr8 -0+f0 <[^>]*> 3e121063[ ]+wcmpgtubcc[ ]+wr1, wr2, wr3 -0+f4 <[^>]*> ee354066[ ]+wcmpgtsb[ ]+wr4, wr5, wr6 -0+f8 <[^>]*> 3e587069[ ]+wcmpgtuhcc[ ]+wr7, wr8, wr9 -0+fc <[^>]*> ee7ba06d[ ]+wcmpgtsh[ ]+wr10, wr11, wr13 -0+100 <[^>]*> ee942063[ ]+wcmpgtuw[ ]+wr2, wr4, wr3 -0+104 <[^>]*> 8eb65063[ ]+wcmpgtswhi[ ]+wr5, wr6, wr3 -0+108 <[^>]*> ed901024[ ]+wldrb[ ]+wr1, \[r0, #36\] -0+10c <[^>]*> 0df12018[ ]+wldrheq[ ]+wr2, \[r1, #24\]! -0+110 <[^>]*> 1cb23104[ ]+wldrwne[ ]+wr3, \[r2\], #16 -0+114 <[^>]*> 6d534153[ ]+wldrdvs[ ]+wr4, \[r3, #-332\] -0+118 <[^>]*> fdb12105[ ]+wldrw[ ]+wcssf, \[r1, #20\]! -0+11c <[^>]*> ee474109[ ]+wmacu[ ]+wr4, wr7, wr9 -0+120 <[^>]*> 2e6a810e[ ]+wmacscs[ ]+wr8, wr10, wr14 -0+124 <[^>]*> ee5cf10b[ ]+wmacuz[ ]+wr15, wr12, wr11 -0+128 <[^>]*> ee78310a[ ]+wmacsz[ ]+wr3, wr8, wr10 -0+12c <[^>]*> ee8bc107[ ]+wmaddu[ ]+wr12, wr11, wr7 -0+130 <[^>]*> cea3510f[ ]+wmaddsgt[ ]+wr5, wr3, wr15 -0+134 <[^>]*> 2e043165[ ]+wmaxubcs[ ]+wr3, wr4, wr5 -0+138 <[^>]*> ee243165[ ]+wmaxsb[ ]+wr3, wr4, wr5 -0+13c <[^>]*> 5e443165[ ]+wmaxuhpl[ ]+wr3, wr4, wr5 -0+140 <[^>]*> 4e643165[ ]+wmaxshmi[ ]+wr3, wr4, wr5 -0+144 <[^>]*> ae843165[ ]+wmaxuwge[ ]+wr3, wr4, wr5 -0+148 <[^>]*> dea43165[ ]+wmaxswle[ ]+wr3, wr4, wr5 -0+14c <[^>]*> 3e1c416a[ ]+wminubcc[ ]+wr4, wr12, wr10 -0+150 <[^>]*> ee3c416a[ ]+wminsb[ ]+wr4, wr12, wr10 -0+154 <[^>]*> 7e5c416a[ ]+wminuhvc[ ]+wr4, wr12, wr10 -0+158 <[^>]*> ee7c416a[ ]+wminsh[ ]+wr4, wr12, wr10 -0+15c <[^>]*> ee9c416a[ ]+wminuw[ ]+wr4, wr12, wr10 -0+160 <[^>]*> 3ebc416a[ ]+wminswcc[ ]+wr4, wr12, wr10 -0+164 <[^>]*> 0e043004[ ]+woreq[ ]+wr3, wr4, wr4 -0+168 <[^>]*> ee112108[ ]+wmulum[ ]+wr2, wr1, wr8 -0+16c <[^>]*> ee312108[ ]+wmulsm[ ]+wr2, wr1, wr8 -0+170 <[^>]*> ee012108[ ]+wmulul[ ]+wr2, wr1, wr8 -0+174 <[^>]*> de212108[ ]+wmulslle[ ]+wr2, wr1, wr8 -0+178 <[^>]*> 0e08b00e[ ]+woreq[ ]+wr11, wr8, wr14 -0+17c <[^>]*> 0e510083[ ]+wpackhuseq[ ]+wr0, wr1, wr3 -0+180 <[^>]*> ee910083[ ]+wpackwus[ ]+wr0, wr1, wr3 -0+184 <[^>]*> eed10083[ ]+wpackdus[ ]+wr0, wr1, wr3 -0+188 <[^>]*> 8e710083[ ]+wpackhsshi[ ]+wr0, wr1, wr3 -0+18c <[^>]*> eeb10083[ ]+wpackwss[ ]+wr0, wr1, wr3 -0+190 <[^>]*> 0ef10083[ ]+wpackdsseq[ ]+wr0, wr1, wr3 -0+194 <[^>]*> ee754046[ ]+wrorh[ ]+wr4, wr5, wr6 -0+198 <[^>]*> 4eb54046[ ]+wrorwmi[ ]+wr4, wr5, wr6 -0+19c <[^>]*> eef54046[ ]+wrord[ ]+wr4, wr5, wr6 -0+1a0 <[^>]*> ee7a9148[ ]+wrorhg[ ]+wr9, wr10, wcgr0 -0+1a4 <[^>]*> aeba9149[ ]+wrorwgge[ ]+wr9, wr10, wcgr1 -0+1a8 <[^>]*> eefa914a[ ]+wrordg[ ]+wr9, wr10, wcgr2 -0+1ac <[^>]*> ee00212a[ ]+wsadb[ ]+wr2, wr0, wr10 -0+1b0 <[^>]*> ee40212a[ ]+wsadh[ ]+wr2, wr0, wr10 -0+1b4 <[^>]*> ee10212a[ ]+wsadbz[ ]+wr2, wr0, wr10 -0+1b8 <[^>]*> de50212a[ ]+wsadhzle[ ]+wr2, wr0, wr10 -0+1bc <[^>]*> 0ef941eb[ ]+wshufheq[ ]+wr4, wr9, #251 -0+1c0 <[^>]*> ee592044[ ]+wsllh[ ]+wr2, wr9, wr4 -0+1c4 <[^>]*> ee992044[ ]+wsllw[ ]+wr2, wr9, wr4 -0+1c8 <[^>]*> 0ed92044[ ]+wslldeq[ ]+wr2, wr9, wr4 -0+1cc <[^>]*> 0e59214b[ ]+wsllhgeq[ ]+wr2, wr9, wcgr3 -0+1d0 <[^>]*> 7e99214a[ ]+wsllwgvc[ ]+wr2, wr9, wcgr2 -0+1d4 <[^>]*> eed92149[ ]+wslldg[ ]+wr2, wr9, wcgr1 -0+1d8 <[^>]*> ee451047[ ]+wsrah[ ]+wr1, wr5, wr7 -0+1dc <[^>]*> ee851047[ ]+wsraw[ ]+wr1, wr5, wr7 -0+1e0 <[^>]*> 0ec51047[ ]+wsradeq[ ]+wr1, wr5, wr7 -0+1e4 <[^>]*> ee45114b[ ]+wsrahg[ ]+wr1, wr5, wcgr3 -0+1e8 <[^>]*> 4e851148[ ]+wsrawgmi[ ]+wr1, wr5, wcgr0 -0+1ec <[^>]*> eec51149[ ]+wsradg[ ]+wr1, wr5, wcgr1 -0+1f0 <[^>]*> ee651047[ ]+wsrlh[ ]+wr1, wr5, wr7 -0+1f4 <[^>]*> eea51047[ ]+wsrlw[ ]+wr1, wr5, wr7 -0+1f8 <[^>]*> 0ee51047[ ]+wsrldeq[ ]+wr1, wr5, wr7 -0+1fc <[^>]*> ee65114b[ ]+wsrlhg[ ]+wr1, wr5, wcgr3 -0+200 <[^>]*> 4ea51148[ ]+wsrlwgmi[ ]+wr1, wr5, wcgr0 -0+204 <[^>]*> eee51149[ ]+wsrldg[ ]+wr1, wr5, wcgr1 -0+208 <[^>]*> ed8110ff[ ]+wstrb[ ]+wr1, \[r1, #255\] -0+20c <[^>]*> ed6110ff[ ]+wstrh[ ]+wr1, \[r1, #-255\]! -0+210 <[^>]*> eca11101[ ]+wstrw[ ]+wr1, \[r1\], #4 -0+214 <[^>]*> edc111ff[ ]+wstrd[ ]+wr1, \[r1, #1020\] -0+218 <[^>]*> fca1314b[ ]+wstrw[ ]+wcasf, \[r1\], #300 -0+21c <[^>]*> 3e1311ae[ ]+wsubbuscc[ ]+wr1, wr3, wr14 -0+220 <[^>]*> ee5311ae[ ]+wsubhus[ ]+wr1, wr3, wr14 -0+224 <[^>]*> 3e9311ae[ ]+wsubwuscc[ ]+wr1, wr3, wr14 -0+228 <[^>]*> 3e3311ae[ ]+wsubbsscc[ ]+wr1, wr3, wr14 -0+22c <[^>]*> 3e7311ae[ ]+wsubhsscc[ ]+wr1, wr3, wr14 -0+230 <[^>]*> eeb311ae[ ]+wsubwss[ ]+wr1, wr3, wr14 -0+234 <[^>]*> ee0630c0[ ]+wunpckehub[ ]+wr3, wr6 -0+238 <[^>]*> 4e4630c0[ ]+wunpckehuhmi[ ]+wr3, wr6 -0+23c <[^>]*> ee8630c0[ ]+wunpckehuw[ ]+wr3, wr6 -0+240 <[^>]*> ee2630c0[ ]+wunpckehsb[ ]+wr3, wr6 -0+244 <[^>]*> ee6630c0[ ]+wunpckehsh[ ]+wr3, wr6 -0+248 <[^>]*> 0ea630c0[ ]+wunpckehsweq[ ]+wr3, wr6 -0+24c <[^>]*> ee1c50ca[ ]+wunpckihb[ ]+wr5, wr12, wr10 -0+250 <[^>]*> 8e5c50ca[ ]+wunpckihhhi[ ]+wr5, wr12, wr10 -0+254 <[^>]*> ee9c50ca[ ]+wunpckihw[ ]+wr5, wr12, wr10 -0+258 <[^>]*> ee0530e0[ ]+wunpckelub[ ]+wr3, wr5 -0+25c <[^>]*> 1e4530e0[ ]+wunpckeluhne[ ]+wr3, wr5 -0+260 <[^>]*> ee8530e0[ ]+wunpckeluw[ ]+wr3, wr5 -0+264 <[^>]*> ce2530e0[ ]+wunpckelsbgt[ ]+wr3, wr5 -0+268 <[^>]*> ee6530e0[ ]+wunpckelsh[ ]+wr3, wr5 -0+26c <[^>]*> eea530e0[ ]+wunpckelsw[ ]+wr3, wr5 -0+270 <[^>]*> ee1540ea[ ]+wunpckilb[ ]+wr4, wr5, wr10 -0+274 <[^>]*> ee5540ea[ ]+wunpckilh[ ]+wr4, wr5, wr10 -0+278 <[^>]*> 0e9540ea[ ]+wunpckilweq[ ]+wr4, wr5, wr10 -0+27c <[^>]*> 1e143005[ ]+wxorne[ ]+wr3, wr4, wr5 -0+280 <[^>]*> ae377007[ ]+wandnge[ ]+wr7, wr7, wr7 -0+284 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) -0+288 <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) -0+28c <[^>]*> e1a00000[ ]+nop[ ]+\(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt.s b/binutils-2.17/gas/testsuite/gas/arm/iwmmxt.s deleted file mode 100644 index 0ebbad5c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/iwmmxt.s +++ /dev/null @@ -1,209 +0,0 @@ - .text - .global iwmmxt -iwmmxt: - - tandcb r15 - TANDCHLE r15 - TANDCWge r15 - - TBCSTBlt wr0, r1 - tbcsth wr1, r2 - TBCSTWGT wr2, r3 - - textrcb r15, #7 - textrcheq r15, #2 - TEXTRCW r15, #0 - - TEXTRMUB r14, wr3, #6 - textrmsbne r13, wr4, #5 - textrmUH r12, wr5, #2 - textrmSh r11, wr6, #0 - TEXTRMUWcs r10, wr7, #1 - textrmswhs r9, wr8, #0 - - TINSRB wr9, r8, #4 - tinsrhcc wr10, r7, #0 - tinsrw wr11, r6, #1 - - tmcrul wcid, r5 - TMCRR wr12, r6, r7 - tmialo wr13, r5, r4 - tmiaphMI wr14, r3, r2 - - TMIAbb wr15, r0, r1 - TMIAbTpl wr13, r2, r3 - tmiaBtvs wr1, r4, r5 - tmiaTTvc wr2, r6, r7 - - tmovmskB r8, wr3 - TMOVMSKHhi r9, wr4 - tmovmskwls r10, wr5 - - tmrc r11, wcon - TMRRCge r12, r13, wr6 - - torcb r15 - torchlt r15 - TORCW r15 - - waccb wr7, wr8 - WACCHlt wr9, wr10 - WACCWGT wr11, wr12 - - waddble wr13, wr14, wr15 - waddBUS wr0, wr2, wr4 - waddbssal wr6, wr8, wr10 - waddH wr12, wr14, wr15 - WADDHUSLE wr13, wr12, wr11 - WADDHSSeq wr10, wr9, wr8 - WADDWne wr7, wr6, wr5 - waddwus wr4, wr3, wr2 - waddwsscs wr1, wr0, wr15 - - waligni wr3, wr5, wr7, #5 - WALIGNR0hs wr9, wr11, wr13 - walignr1 wr7, wr6, wr5 - walignr2cc wr2, wr4, wr8 - WALIGNR3ul wr5, wr9, wr1 - - wand wr3, wr8, wr1 - wandn wr3, wr2, wr6 - - wavg2b wr7, wr8, wr9 - wavg2hle wr10, wr11, wr12 - wavg2brge wr13, wr14, wr15 - wavg2hr wr0, wr1, wr12 - - wcmpeqb wr13, wr4, wr5 - wcmpeqheq wr4, wr7, wr0 - wcmpeqWlt wr6, wr9, wr8 - - wcmpgtUbul wr1, wr2, wr3 - wcmpgtsb wr4, wr5, wr6 - wcmpgtuhcc wr7, wr8, wr9 - wcmpgtsh wr10, wr11, wr13 - wcmpgtuw wr2, wr4, wr3 - wcmpgtswhi wr5, wr6, wr3 - - wldrb wr1, [r0, #36] - wldrheq wr2, [r1, #24]! - wldrwne wr3, [r2], #16 - wldrdvs wr4, [r3, #-332] - wldrw wcssf, [r1, #20]! - - wmacu wr4, wr7, wr9 - wmacscs wr8, wr10, wr14 - wmacuzal wr15, wr12, wr11 - wmacsz wr3, wr8, wr10 - - wmaddu wr12, wr11, wr7 - wmaddsgt wr5, wr3, wr15 - - wmaxubhs wr3, wr4, wr5 - wmaxsb wr3, wr4, wr5 - wmaxuhpl wr3, wr4, wr5 - wmaxshmi wr3, wr4, wr5 - wmaxuwge wr3, wr4, wr5 - wmaxswle wr3, wr4, wr5 - - wminubul wr4, wr12, wr10 - wminsb wr4, wr12, wr10 - wminuhvc wr4, wr12, wr10 - wminsh wr4, wr12, wr10 - wminuw wr4, wr12, wr10 - wminswcc wr4, wr12, wr10 - - wmoveq wr3, wr4 - - wmulum wr2, wr1, wr8 - wmulsm wr2, wr1, wr8 - wmulul wr2, wr1, wr8 - wmulslle wr2, wr1, wr8 - - woreq wr11, wr8, wr14 - - wpackhuseq wr0, wr1, wr3 - wpackwus wr0, wr1, wr3 - wpackdusal wr0, wr1, wr3 - wpackhsshi wr0, wr1, wr3 - wpackwss wr0, wr1, wr3 - wpackdsseq wr0, wr1, wr3 - - wrorh wr4, wr5, wr6 - wrorwmi wr4, wr5, wr6 - wrord wr4, wr5, wr6 - wrorhg wr9, wr10, wcgr0 - wrorwgge wr9, wr10, wcgr1 - wrordg wr9, wr10, wcgr2 - - wsadb wr2, wr0, wr10 - wsadhal wr2, wr0, wr10 - wsadbz wr2, wr0, wr10 - wsadhzle wr2, wr0, wr10 - - wshufheq wr4, wr9, #251 - - wsllh wr2, wr9, wr4 - wsllw wr2, wr9, wr4 - wslldeq wr2, wr9, wr4 - wsllhgeq wr2, wr9, wcgr3 - wsllwgvc wr2, wr9, wcgr2 - wslldg wr2, wr9, wcgr1 - - wsrah wr1, wr5, wr7 - wsraw wr1, wr5, wr7 - wsradeq wr1, wr5, wr7 - wsrahg wr1, wr5, wcgr3 - wsrawgmi wr1, wr5, wcgr0 - wsradg wr1, wr5, wcgr1 - - wsrlh wr1, wr5, wr7 - wsrlw wr1, wr5, wr7 - wsrldeq wr1, wr5, wr7 - wsrlhg wr1, wr5, wcgr3 - wsrlwgmi wr1, wr5, wcgr0 - wsrldg wr1, wr5, wcgr1 - - wstrb wr1, [r1, #0xFF] - wstrh wr1, [r1, #-0xFF]! - wstrw wr1, [r1], #4 - wstrd wr1, [r1, #0x3FC] - wstrw wcasf, [r1], #300 - - wsubbusul wr1, wr3, wr14 - wsubhus wr1, wr3, wr14 - wsubwusul wr1, wr3, wr14 - wsubbssul wr1, wr3, wr14 - wsubhssul wr1, wr3, wr14 - wsubwss wr1, wr3, wr14 - - wunpckehub wr3, wr6 - wunpckehuhmi wr3, wr6 - wunpckehuw wr3, wr6 - wunpckehsb wr3, wr6 - wunpckehsh wr3, wr6 - wunpckehsweq wr3, wr6 - - wunpckihb wr5, wr12, wr10 - wunpckihhhi wr5, wr12, wr10 - wunpckihw wr5, wr12, wr10 - - wunpckelub wr3, wr5 - wunpckeluhne wr3, wr5 - wunpckeluw wr3, wr5 - wunpckelsbgt wr3, wr5 - wunpckelsh wr3, wr5 - wunpckelsw wr3, wr5 - - wunpckilb wr4, wr5, wr10 - wunpckilh wr4, wr5, wr10 - wunpckilweq wr4, wr5, wr10 - - wxorne wr3, wr4, wr5 - - wzeroge wr7 - - @ a.out-required section size padding - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/ldconst.d b/binutils-2.17/gas/testsuite/gas/arm/ldconst.d deleted file mode 100644 index 6ce123d2..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/ldconst.d +++ /dev/null @@ -1,27 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM ldr with immediate constant -#as: -mcpu=arm7m -EL - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 -0+04 <[^>]*> e3a004ff ? mov r0, #-16777216 ; 0xff000000 -0+08 <[^>]*> e3e00000 ? mvn r0, #0 ; 0x0 -0+0c <[^>]*> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+10 <[^>]*> -0+10 <[^>]*> 0fff0000 ? .* -0+14 <[^>]*> e3a0e000 ? mov lr, #0 ; 0x0 -0+18 <[^>]*> e3a0e8ff ? mov lr, #16711680 ; 0xff0000 -0+1c <[^>]*> e3e0e8ff ? mvn lr, #16711680 ; 0xff0000 -0+20 <[^>]*> e51fe004 ? ldr lr, \[pc, #-4\] ; 0+24 <[^>]*> -0+24 <[^>]*> 00fff000 ? .* -0+28 <[^>]*> 03a00000 ? moveq r0, #0 ; 0x0 -0+2c <[^>]*> 03a00cff ? moveq r0, #65280 ; 0xff00 -0+30 <[^>]*> 03e00cff ? mvneq r0, #65280 ; 0xff00 -0+34 <[^>]*> 051f0004 ? ldreq r0, \[pc, #-4\] ; 0+38 <[^>]*> -0+38 <[^>]*> 000fff00 ? .* -0+3c <[^>]*> 43a0b000 ? movmi fp, #0 ; 0x0 -0+40 <[^>]*> 43a0b0ff ? movmi fp, #255 ; 0xff -0+44 <[^>]*> 43e0b0ff ? mvnmi fp, #255 ; 0xff -0+48 <[^>]*> 451fb004 ? ldrmi fp, \[pc, #-4\] ; 0+4c <[^>]*> -0+4c <[^>]*> 0000fff0 ? .* diff --git a/binutils-2.17/gas/testsuite/gas/arm/ldconst.s b/binutils-2.17/gas/testsuite/gas/arm/ldconst.s deleted file mode 100644 index 1b6aca90..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/ldconst.s +++ /dev/null @@ -1,28 +0,0 @@ -@ Test file for ARM/GAS -- ldr reg, =... expressions. - -.text -.align -foo: - ldr r0, =0 - ldr r0, =0xff000000 - ldr r0, =-1 - ldr r0, =0x0fff0000 - .pool - - ldr r14, =0 - ldr r14, =0x00ff0000 - ldr r14, =0xff00ffff - ldr r14, =0x00fff000 - .pool - - ldreq r0, =0 - ldreq r0, =0x0000ff00 - ldreq r0, =0xffff00ff - ldreq r0, =0x000fff00 - .pool - - ldrmi r11, =0 - ldrmi r11, =0x000000ff - ldrmi r11, =0xffffff00 - ldrmi r11, =0x0000fff0 - .pool diff --git a/binutils-2.17/gas/testsuite/gas/arm/le-fpconst.d b/binutils-2.17/gas/testsuite/gas/arm/le-fpconst.d deleted file mode 100644 index 846da89f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/le-fpconst.d +++ /dev/null @@ -1,11 +0,0 @@ -#objdump: -s --section=.text -#as: -EL -#name: arm little-endian fpconst -# Not all arm targets are bi-endian, so only run this test on ones -# we know that are. FIXME We should probably also key off armeb/armel. -#target: *-*-pe - -.*: +file format .*arm.* - -Contents of section .text: - 0000 cdcc8c3f 00000000 9999f13f 9a999999 .* diff --git a/binutils-2.17/gas/testsuite/gas/arm/le-fpconst.s b/binutils-2.17/gas/testsuite/gas/arm/le-fpconst.s deleted file mode 100644 index 8a3c3d70..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/le-fpconst.s +++ /dev/null @@ -1,8 +0,0 @@ -# Test fp constants. -# These need ARM specific support because 8 byte fp constants in little -# endian mode are represented abnormally. - - .text - .float 1.1 - .float 0 - .double 1.1 diff --git a/binutils-2.17/gas/testsuite/gas/arm/macro1.d b/binutils-2.17/gas/testsuite/gas/arm/macro1.d deleted file mode 100644 index 2384594f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/macro1.d +++ /dev/null @@ -1,12 +0,0 @@ -# name: Macro scrubbing -# as: -# objdump: -dr --prefix-addresses --show-raw-insn - -[^:]+: +file format .*arm.* - -Disassembly of section .text: - -0+0 <[^>]*> e8bd8030 ? ldmia sp!, {r4, r5, pc} -0+4 <[^>]*> e1a00000 ? nop \(mov r0,r0\) -0+8 <[^>]*> e1a00000 ? nop \(mov r0,r0\) -0+c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/macro1.s b/binutils-2.17/gas/testsuite/gas/arm/macro1.s deleted file mode 100644 index e2880e7b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/macro1.s +++ /dev/null @@ -1,12 +0,0 @@ - @ Test that macro expansions are properly scrubbed. - .macro popret regs - ldmia sp!, {\regs, pc} - .endm - .text -l: - popret "r4, r5" - - @ section padding for a.out's sake - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/mapping.d b/binutils-2.17/gas/testsuite/gas/arm/mapping.d deleted file mode 100644 index e6db1a98..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/mapping.d +++ /dev/null @@ -1,22 +0,0 @@ -#objdump: --syms --special-syms -#name: ARM Mapping Symbols -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* - -# Test the generation of ARM ELF Mapping Symbols - -.*: +file format.*arm.* - -SYMBOL TABLE: -0+00 l d .text 0+0 (|.text) -0+00 l d .data 0+0 (|.data) -0+00 l d .bss 0+0 (|.bss) -0+00 l .text 0+0 \$a -0+08 l .text 0+0 \$t -0+00 l .data 0+0 \$d -0+00 l d foo 0+0 (|foo) -0+00 l foo 0+0 \$t -#Maybe section symbol for .ARM.attributes -#... -0+00 g .text 0+0 mapping -0+08 g F .text 0+0 thumb_mapping diff --git a/binutils-2.17/gas/testsuite/gas/arm/mapping.s b/binutils-2.17/gas/testsuite/gas/arm/mapping.s deleted file mode 100644 index c9cee8d4..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/mapping.s +++ /dev/null @@ -1,19 +0,0 @@ - .text - .arm - .global mapping -mapping: - nop - bl mapping - - .global thumb_mapping - .thumb_func -thumb_mapping: - .thumb - nop - bl thumb_mapping - - .data - .word 0x123456 - - .section foo,"ax" - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/maverick.c b/binutils-2.17/gas/testsuite/gas/arm/maverick.c deleted file mode 100644 index e0eb25ec..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/maverick.c +++ /dev/null @@ -1,533 +0,0 @@ -/* Copyright (C) 2000, 2003 Free Software Foundation - Contributed by Alexandre Oliva <aoliva@cygnus.com> - - This file is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* Generator of tests for Maverick. - - See the following file for usage and documentation. */ -#include "../all/test-gen.c" - -/* These are the ARM registers. Some of them have canonical names - other than r##, so we'll use both in the asm input, but only the - canonical names in the expected disassembler output. */ -char *arm_regs[] = - { - /* Canonical names. */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", - /* Alternate names, i.e., those that can be used in the assembler, - * but that will never be emitted by the disassembler. */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" - }; - -/* The various types of registers: ARM's registers, Maverick's - f/d/fx/dx registers, Maverick's accumulators and Maverick's - status register. */ -#define armreg(shift) \ - reg_r (arm_regs, shift, 0xf, mk_get_bits (5u)) -#define mvreg(prefix, shift) \ - reg_p ("mv" prefix, shift, mk_get_bits (4u)) -#define acreg(shift) \ - reg_p ("mvax", shift, mk_get_bits (2u)) -#define dspsc \ - literal ("dspsc"), tick_random - -/* This outputs the condition flag that may follow each ARM insn. - Since the condition 15 is invalid, we use it to check that the - assembler recognizes the absence of a condition as `al'. However, - the disassembler won't ever output `al', so, if we emit it in the - assembler, expect the condition to be omitted in the disassembler - output. */ - -int -arm_cond (func_arg * arg, insn_data * data) -#define arm_cond { arm_cond } -{ - static const char conds[16][3] = - { - "eq", "ne", "cs", "cc", - "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", - "gt", "le", "al", "" - }; - unsigned val = get_bits (4u); - - data->as_in = data->dis_out = strdup (conds[val]); - if (val == 14) - data->dis_out = strdup (""); - data->bits = (val == 15 ? 14 : val) << 28; - return 0; -} - -/* The sign of an offset is actually used to determined whether the - absolute value of the offset should be added or subtracted, so we - must adjust negative values so that they do not overflow: -1024 is - not valid, but -0 is distinct from +0. */ -int -off8s (func_arg * arg, insn_data * data) -#define off8s { off8s } -{ - int val; - char value[9]; - - /* Zero values are problematical. - The assembler performs translations on the addressing modes - for these values, meaning that we cannot just recreate the - disassembler string in the LDST macro without knowing what - value had been generated in off8s. */ - do - { - val = get_bits (9s); - } - while (val == -1 || val == 0); - - val <<= 2; - if (val < 0) - { - val = -4 - val; - sprintf (value, ", #-%i", val); - data->dis_out = strdup (value); - sprintf (value, ", #-%i", val); - data->as_in = strdup (value); - data->bits = val >> 2; - } - else - { - sprintf (value, ", #%i", val); - data->as_in = data->dis_out = strdup (value); - data->bits = (val >> 2) | (1 << 23); - } - - return 0; -} - -/* This function generates a 7-bit signed constant, emitted as - follows: the 4 least-significant bits are stored in the 4 - least-significant bits of the word; the 3 most-significant bits are - stored in bits 7:5, i.e., bit 4 is skipped. */ -int -imm7 (func_arg *arg, insn_data *data) -#define imm7 { imm7 } -{ - int val = get_bits (7s); - char value[6]; - - data->bits = (val & 0x0f) | (2 * (val & 0x70)); - sprintf (value, "#%i", val); - data->as_in = data->dis_out = strdup (value); - return 0; -} - -/* Convenience wrapper to define_insn, that prefixes every insn with - `cf' (so, if you specify command-line arguments, remember that `cf' - must *not* be part of the string), and post-fixes a condition code. - insname and insnvar specify the main insn name and a variant; - they're just concatenated, and insnvar is often empty. word is the - bit pattern that defines the insn, properly shifted, and funcs is a - sequence of funcs that define the operands and the syntax of the - insn. */ -#define mv_insn(insname, insnvar, word, funcs...) \ - define_insn (insname ## insnvar, \ - literal ("cf"), \ - insn_bits (insname, word), \ - arm_cond, \ - tab, \ - ## funcs) - -/* Define a single LDC/STC variant. op is the main insn opcode; ld - stands for load (it should be 0 on stores), dword selects 64-bit - operations, pre should be enabled for pre-increment, and wb, for - write-back. sep1, sep2 and sep3 are syntactical elements ([]!) - that the assembler will use to enable pre and wb. It would - probably have been cleaner to couple the syntactical elements with - the pre/wb bits directly, but it would have required the definition - of more functions. */ -#define LDST(insname, insnvar, op, ld, dword, regname, pre, wb, sep1, sep2, sep3) \ - mv_insn (insname, insnvar, \ - (12 << 24) | (op << 8) | (ld << 20) | (pre << 24) | (dword << 22) | (wb << 21), \ - mvreg (regname, 12), comma, \ - lsqbkt, armreg (16), sep1, off8s, sep2, sep3, \ - tick_random) - -/* Define all variants of an LDR or STR instruction, namely, - pre-indexed without write-back, pre-indexed with write-back and - post-indexed. */ -#define LDSTall(insname, op, ld, dword, regname) \ - LDST (insname, _p, op, ld, dword, regname, 1, 0, nothing, rsqbkt, nothing); \ - LDST (insname, _pw, op, ld, dword, regname, 1, 1, nothing, rsqbkt, literal ("!")); \ - LDST (insname, ,op, ld, dword, regname, 0, 1, rsqbkt, nothing, nothing) - -/* Produce the insn identifiers of all LDST variants of a given insn. - To be used in the initialization of an insn group array. */ -#define insns_LDSTall(insname) \ - insn (insname ## _p), insn (insname ## _pw), insn (insname) - -/* Define a CDP variant that uses two registers, at offsets 12 and 16. - The two opcodes and the co-processor number identify the CDP - insn. */ -#define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \ - mv_insn (insname##var, , \ - (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \ - mvreg (reg1name, 12), comma, mvreg (reg2name, 16)) - -/* Define a 32-bit integer CDP instruction with two operands. */ -#define CDP2fx(insname, opcode1, opcode2) \ - CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx") - -/* Define a 64-bit integer CDP instruction with two operands. */ -#define CDP2dx(insname, opcode1, opcode2) \ - CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx") - -/* Define a float CDP instruction with two operands. */ -#define CDP2f(insname, opcode1, opcode2) \ - CDP2 (insname, s, 4, opcode1, opcode2, "f", "f") - -/* Define a double CDP instruction with two operands. */ -#define CDP2d(insname, opcode1, opcode2) \ - CDP2 (insname, d, 4, opcode1, opcode2, "d", "d") - -/* Define a CDP instruction with two register operands and one 7-bit - signed immediate generated with imm7. */ -#define CDP2_imm7(insname, cpnum, opcode1, reg1name, reg2name) \ - mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8), \ - mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, imm7, \ - tick_random) - -/* Produce the insn identifiers of CDP floating-point or integer insn - pairs (i.e., it appends the suffixes for 32-bit and 64-bit - insns. */ -#define CDPfp_insns(insname) \ - insn (insname ## s), insn (insname ## d) -#define CDPx_insns(insname) \ - insn (insname ## 32), insn (insname ## 64) - -/* Define a CDP instruction with 3 operands, at offsets 12, 16, 0. */ -#define CDP3(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name, reg3name) \ - mv_insn (insname##var, , \ - (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \ - mvreg (reg1name, 12), comma, mvreg (reg2name, 16), comma, \ - mvreg (reg3name, 0), tick_random) - -/* Define a 32-bit integer CDP instruction with three operands. */ -#define CDP3fx(insname, opcode1, opcode2) \ - CDP3 (insname, 32, 5, opcode1, opcode2, "fx", "fx", "fx") - -/* Define a 64-bit integer CDP instruction with three operands. */ -#define CDP3dx(insname, opcode1, opcode2) \ - CDP3 (insname, 64, 5, opcode1, opcode2, "dx", "dx", "dx") - -/* Define a float CDP instruction with three operands. */ -#define CDP3f(insname, opcode1, opcode2) \ - CDP3 (insname, s, 4, opcode1, opcode2, "f", "f", "f") - -/* Define a double CDP instruction with three operands. */ -#define CDP3d(insname, opcode1, opcode2) \ - CDP3 (insname, d, 4, opcode1, opcode2, "d", "d", "d") - -/* Define a CDP instruction with four operands, at offsets 5, 12, 16 - * and 0. Used only for ACC instructions. */ -#define CDP4(insname, opcode1, reg2spec, reg3name, reg4name) \ - mv_insn (insname, , (14 << 24) | ((opcode1) << 20) | (6 << 8), \ - acreg (5), comma, reg2spec, comma, \ - mvreg (reg3name, 16), comma, mvreg (reg4name, 0)) - -/* Define a CDP4 instruction with one accumulator operands. */ -#define CDP41A(insname, opcode1) \ - CDP4 (insname, opcode1, mvreg ("fx", 12), "fx", "fx") - -/* Define a CDP4 instruction with two accumulator operands. */ -#define CDP42A(insname, opcode1) \ - CDP4 (insname, opcode1, acreg (12), "fx", "fx") - -/* Define a MCR or MRC instruction with two register operands. */ -#define MCRC2(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec) \ - mv_insn (insname, , \ - ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \ - ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \ - reg1spec, comma, reg2spec) - -/* Define a move from a DSP register to an ARM register. */ -#define MVDSPARM(insname, cpnum, opcode2, regDSPname) \ - MCRC2 (mv ## insname, cpnum, 0, 0, opcode2, \ - mvreg (regDSPname, 16), armreg (12)) - -/* Define a move from an ARM register to a DSP register. */ -#define MVARMDSP(insname, cpnum, opcode2, regDSPname) \ - MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \ - armreg (12), mvreg (regDSPname, 16)) - -/* Move between coprocessor registers. A two operand CDP insn. */ -#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \ - mv_insn (insname, , \ - ((14 << 24) | ((opcode1) << 20) | \ - (4 << 8) | ((opcode2) << 5)), \ - reg1spec, comma, reg2spec) - -/* Define a move from a DSP register to a DSP accumulator. */ -#define MVDSPACC(insname, opcode2, regDSPname) \ - MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16)) - -/* Define a move from a DSP accumulator to a DSP register. */ -#define MVACCDSP(insname, opcode2, regDSPname) \ - MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16)) - -/* Define move insns between a float DSP register and an ARM - register. */ -#define MVf(nameAD, nameDA, opcode2) \ - MVDSPARM (nameAD, 4, opcode2, "f"); \ - MVARMDSP (nameDA, 4, opcode2, "f") - -/* Define move insns between a double DSP register and an ARM - register. */ -#define MVd(nameAD, nameDA, opcode2) \ - MVDSPARM (nameAD, 4, opcode2, "d"); \ - MVARMDSP (nameDA, 4, opcode2, "d") - -/* Define move insns between a 32-bit integer DSP register and an ARM - register. */ -#define MVfx(nameAD, nameDA, opcode2) \ - MVDSPARM (nameAD, 5, opcode2, "fx"); \ - MVARMDSP (nameDA, 5, opcode2, "fx") - -/* Define move insns between a 64-bit integer DSP register and an ARM - register. */ -#define MVdx(nameAD, nameDA, opcode2) \ - MVDSPARM (nameAD, 5, opcode2, "dx"); \ - MVARMDSP (nameDA, 5, opcode2, "dx") - -/* Define move insns between a 32-bit DSP register and a DSP - accumulator. */ -#define MVfxa(nameFA, nameAF, opcode2) \ - MVDSPACC (nameFA, opcode2, "fx"); \ - MVACCDSP (nameAF, opcode2, "fx") - -/* Define move insns between a 64-bit DSP register and a DSP - accumulator. */ -#define MVdxa(nameDA, nameAD, opcode2) \ - MVDSPACC (nameDA, opcode2, "dx"); \ - MVACCDSP (nameAD, opcode2, "dx") - -/* Produce the insn identifiers for a pair of mv insns. */ -#define insns_MV(name1, name2) \ - insn (mv ## name1), insn (mv ## name2) - -/* Define a MCR or MRC instruction with three register operands. */ -#define MCRC3(insname, cpnum, opcode1, dir, opcode2, reg1spec, reg2spec, reg3spec) \ - mv_insn (insname, , \ - ((14 << 24) | ((opcode1) << 21) | ((dir) << 20)| \ - ((cpnum) << 8) | ((opcode2) << 5) | (1 << 4)), \ - reg1spec, comma, reg2spec, comma, reg3spec, \ - tick_random) - -/* Define all load_store insns. */ -LDSTall (ldrs, 4, 1, 0, "f"); -LDSTall (ldrd, 4, 1, 1, "d"); -LDSTall (ldr32, 5, 1, 0, "fx"); -LDSTall (ldr64, 5, 1, 1, "dx"); -LDSTall (strs, 4, 0, 0, "f"); -LDSTall (strd, 4, 0, 1, "d"); -LDSTall (str32, 5, 0, 0, "fx"); -LDSTall (str64, 5, 0, 1, "dx"); - -/* Create the load_store insn group. */ -func *load_store_insns[] = - { - insns_LDSTall (ldrs), insns_LDSTall (ldrd), - insns_LDSTall (ldr32), insns_LDSTall (ldr64), - insns_LDSTall (strs), insns_LDSTall (strd), - insns_LDSTall (str32), insns_LDSTall (str64), - 0 - }; - -/* Define all move insns. */ -MVf (sr, rs, 2); -MVd (dlr, rdl, 0); -MVd (dhr, rdh, 1); -MVdx (64lr, r64l, 0); -MVdx (64hr, r64h, 1); -MVfxa (al32, 32al, 2); -MVfxa (am32, 32am, 3); -MVfxa (ah32, 32ah, 4); -MVfxa (a32, 32a, 5); -MVdxa (a64, 64a, 6); -MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12)); -MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc); -CDP2 (cpys, , 4, 0, 0, "f", "f"); -CDP2 (cpyd, , 4, 0, 1, "d", "d"); - -/* Create the move insns group. */ -func * move_insns[] = - { - insns_MV (sr, rs), insns_MV (dlr, rdl), insns_MV (dhr, rdh), - insns_MV (64lr, r64l), insns_MV (64hr, r64h), - insns_MV (al32, 32al), insns_MV (am32, 32am), insns_MV (ah32, 32ah), - insns_MV (a32, 32a), insns_MV (a64, 64a), - insn (mvsc32), insn (mv32sc), insn (cpys), insn (cpyd), - 0 - }; - -/* Define all conversion insns. */ -CDP2 (cvtsd, , 4, 0, 3, "d", "f"); -CDP2 (cvtds, , 4, 0, 2, "f", "d"); -CDP2 (cvt32s, , 4, 0, 4, "f", "fx"); -CDP2 (cvt32d, , 4, 0, 5, "d", "fx"); -CDP2 (cvt64s, , 4, 0, 6, "f", "dx"); -CDP2 (cvt64d, , 4, 0, 7, "d", "dx"); -CDP2 (cvts32, , 5, 1, 4, "fx", "f"); -CDP2 (cvtd32, , 5, 1, 5, "fx", "d"); -CDP2 (truncs32, , 5, 1, 6, "fx", "f"); -CDP2 (truncd32, , 5, 1, 7, "fx", "d"); - -/* Create the conv insns group. */ -func * conv_insns[] = - { - insn (cvtsd), insn (cvtds), insn (cvt32s), insn (cvt32d), - insn (cvt64s), insn (cvt64d), insn (cvts32), insn (cvtd32), - insn (truncs32), insn (truncd32), - 0 - }; - -/* Define all shift insns. */ -MCRC3 (rshl32, 5, 0, 0, 2, mvreg ("fx", 16), mvreg ("fx", 0), armreg (12)); -MCRC3 (rshl64, 5, 0, 0, 3, mvreg ("dx", 16), mvreg ("dx", 0), armreg (12)); -CDP2_imm7 (sh32, 5, 0, "fx", "fx"); -CDP2_imm7 (sh64, 5, 2, "dx", "dx"); - -/* Create the shift insns group. */ -func *shift_insns[] = - { - insn (rshl32), insn (rshl64), - insn (sh32), insn (sh64), - 0 - }; - -/* Define all comparison insns. */ -MCRC3 (cmps, 4, 0, 1, 4, armreg (12), mvreg ("f", 16), mvreg ("f", 0)); -MCRC3 (cmpd, 4, 0, 1, 5, armreg (12), mvreg ("d", 16), mvreg ("d", 0)); -MCRC3 (cmp32, 5, 0, 1, 4, armreg (12), mvreg ("fx", 16), mvreg ("fx", 0)); -MCRC3 (cmp64, 5, 0, 1, 5, armreg (12), mvreg ("dx", 16), mvreg ("dx", 0)); - -/* Create the comp insns group. */ -func *comp_insns[] = - { - insn (cmps), insn (cmpd), - insn (cmp32), insn (cmp64), - 0 - }; - -/* Define all floating-point arithmetic insns. */ -CDP2f (abs, 3, 0); -CDP2d (abs, 3, 1); -CDP2f (neg, 3, 2); -CDP2d (neg, 3, 3); -CDP3f (add, 3, 4); -CDP3d (add, 3, 5); -CDP3f (sub, 3, 6); -CDP3d (sub, 3, 7); -CDP3f (mul, 1, 0); -CDP3d (mul, 1, 1); - -/* Create the fp-arith insns group. */ -func *fp_arith_insns[] = - { - CDPfp_insns (abs), CDPfp_insns (neg), - CDPfp_insns (add), CDPfp_insns (sub), CDPfp_insns (mul), - 0 - }; - -/* Define all integer arithmetic insns. */ -CDP2fx (abs, 3, 0); -CDP2dx (abs, 3, 1); -CDP2fx (neg, 3, 2); -CDP2dx (neg, 3, 3); -CDP3fx (add, 3, 4); -CDP3dx (add, 3, 5); -CDP3fx (sub, 3, 6); -CDP3dx (sub, 3, 7); -CDP3fx (mul, 1, 0); -CDP3dx (mul, 1, 1); -CDP3fx (mac, 1, 2); -CDP3fx (msc, 1, 3); - -/* Create the int-arith insns group. */ -func * int_arith_insns[] = - { - CDPx_insns (abs), CDPx_insns (neg), - CDPx_insns (add), CDPx_insns (sub), CDPx_insns (mul), - insn (mac32), insn (msc32), - 0 - }; - -/* Define all accumulator arithmetic insns. */ -CDP41A (madd32, 0); -CDP41A (msub32, 1); -CDP42A (madda32, 2); -CDP42A (msuba32, 3); - -/* Create the acc-arith insns group. */ -func * acc_arith_insns[] = - { - insn (madd32), insn (msub32), - insn (madda32), insn (msuba32), - 0 - }; - -/* Create the set of all groups. */ -group_t groups[] = - { - { "load_store", load_store_insns }, - { "move", move_insns }, - { "conv", conv_insns }, - { "shift", shift_insns }, - { "comp", comp_insns }, - { "fp_arith", fp_arith_insns }, - { "int_arith", int_arith_insns }, - { "acc_arith", acc_arith_insns }, - { 0 } - }; - -int -main (int argc, char *argv[]) -{ - FILE *as_in = stdout, *dis_out = stderr; - - /* Check whether we're filtering insns. */ - if (argc > 1) - skip_list = argv + 1; - - /* Output assembler header. */ - fputs ("\t.text\n" - "\t.align\n", - as_in); - /* Output comments for the testsuite-driver and the initial - disassembler output. */ - fputs ("#objdump: -dr --prefix-address --show-raw-insn\n" - "#name: Maverick\n" - "#as: -mcpu=ep9312\n" - "\n" - "# Test the instructions of the Cirrus Maverick floating point co-processor\n" - "\n" - ".*: +file format.*arm.*\n" - "\n" - "Disassembly of section .text:\n", - dis_out); - - /* Now emit all (selected) insns. */ - output_groups (groups, as_in, dis_out); - - exit (0); -} diff --git a/binutils-2.17/gas/testsuite/gas/arm/maverick.d b/binutils-2.17/gas/testsuite/gas/arm/maverick.d deleted file mode 100644 index 7c41457b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/maverick.d +++ /dev/null @@ -1,477 +0,0 @@ -#objdump: -dr --prefix-address --show-raw-insn -#name: Maverick -#as: -mcpu=ep9312 - -# Test the instructions of the Cirrus Maverick floating point co-processor - -.*: +file format.*arm.* - -Disassembly of section .text: -# load_store: -0*0 <load_store> 0d ?9d ?54 ?ff ? * cfldrseq mvf5, ?\[sp, #1020\] -0*4 <load_store\+0x4> 4d ?9b ?e4 ?49 ? * cfldrsmi mvf14, ?\[fp, #292\] -0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? * cfldrsvc mvf2, ?\[ip, #-956\] -0*c <load_store\+0xc> bd ?1a ?04 ?ff ? * cfldrslt mvf0, ?\[sl, #-1020\] -0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1, #-156\] -0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9, #416\]! -0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0, #-1020\]! -0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1, #-156\]! -0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9, #416\]! -0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? * cfldrsvs mvf11, ?\[r0, #-1020\]! -0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? * cfldrscc mvf12, ?\[r1\], #-156 -0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? * cfldrs mvf13, ?\[r9\], #416 -0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? * cfldrscs mvf9, ?\[r0\], #-1020 -0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? * cfldrsls mvf4, ?\[r1\], #-156 -0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? * cfldrsle mvf7, ?\[r9\], #416 -0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\] -0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\] -0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\] -0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\] -0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? * cfldrdls mvd4, ?\[r1, #-156\] -0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9, #416\]! -0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0, #-1020\]! -0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1, #-156\]! -0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9, #416\]! -0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? * cfldrdcs mvd9, ?\[r0, #-1020\]! -0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? * cfldrdls mvd4, ?\[r1\], #-156 -0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? * cfldrdle mvd7, ?\[r9\], #416 -0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? * cfldrdvs mvd11, ?\[r0\], #-1020 -0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? * cfldrdcc mvd12, ?\[r1\], #-156 -0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? * cfldrd mvd13, ?\[r9\], #416 -0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\] -0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\] -0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\] -0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\] -0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1, #-156\] -0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9, #416\]! -0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0, #-1020\]! -0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1, #-156\]! -0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9, #416\]! -0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? * cfldr32vs mvfx11, ?\[r0, #-1020\]! -0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? * cfldr32cc mvfx12, ?\[r1\], #-156 -0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? * cfldr32 mvfx13, ?\[r9\], #416 -0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? * cfldr32cs mvfx9, ?\[r0\], #-1020 -0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? * cfldr32ls mvfx4, ?\[r1\], #-156 -0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? * cfldr32le mvfx7, ?\[r9\], #416 -0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\] -0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\] -0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\] -0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\] -0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1, #-156\] -0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9, #416\]! -0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0, #-1020\]! -0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1, #-156\]! -0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9, #416\]! -0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? * cfldr64cs mvdx9, ?\[r0, #-1020\]! -0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? * cfldr64ls mvdx4, ?\[r1\], #-156 -0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? * cfldr64le mvdx7, ?\[r9\], #416 -0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? * cfldr64vs mvdx11, ?\[r0\], #-1020 -0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? * cfldr64cc mvdx12, ?\[r1\], #-156 -0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? * cfldr64 mvdx13, ?\[r9\], #416 -0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\] -0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\] -0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\] -0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\] -0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1, #-156\] -0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9, #416\]! -0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0, #-1020\]! -0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1, #-156\]! -0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9, #416\]! -0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? * cfstrsvs mvf11, ?\[r0, #-1020\]! -0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? * cfstrscc mvf12, ?\[r1\], #-156 -0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? * cfstrs mvf13, ?\[r9\], #416 -0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? * cfstrscs mvf9, ?\[r0\], #-1020 -0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? * cfstrsls mvf4, ?\[r1\], #-156 -0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? * cfstrsle mvf7, ?\[r9\], #416 -0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\] -0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\] -0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\] -0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\] -0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? * cfstrdls mvd4, ?\[r1, #-156\] -0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9, #416\]! -0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0, #-1020\]! -0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1, #-156\]! -0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9, #416\]! -0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? * cfstrdcs mvd9, ?\[r0, #-1020\]! -0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? * cfstrdls mvd4, ?\[r1\], #-156 -0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? * cfstrdle mvd7, ?\[r9\], #416 -0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? * cfstrdvs mvd11, ?\[r0\], #-1020 -0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? * cfstrdcc mvd12, ?\[r1\], #-156 -0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? * cfstrd mvd13, ?\[r9\], #416 -0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\] -0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\] -0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\] -0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\] -0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1, #-156\] -0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9, #416\]! -0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0, #-1020\]! -0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1, #-156\]! -0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9, #416\]! -0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? * cfstr32vs mvfx11, ?\[r0, #-1020\]! -0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? * cfstr32cc mvfx12, ?\[r1\], #-156 -0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? * cfstr32 mvfx13, ?\[r9\], #416 -0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? * cfstr32cs mvfx9, ?\[r0\], #-1020 -0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? * cfstr32ls mvfx4, ?\[r1\], #-156 -0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? * cfstr32le mvfx7, ?\[r9\], #416 -0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\] -0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\] -0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\] -0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\] -0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1, #-156\] -0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9, #416\]! -0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0, #-1020\]! -0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1, #-156\]! -0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9, #416\]! -0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? * cfstr64cs mvdx9, ?\[r0, #-1020\]! -0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? * cfstr64ls mvdx4, ?\[r1\], #-156 -0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? * cfstr64le mvdx7, ?\[r9\], #416 -0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? * cfstr64vs mvdx11, ?\[r0\], #-1020 -0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? * cfstr64cc mvdx12, ?\[r1\], #-156 -0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? * cfstr64 mvdx13, ?\[r9\], #416 -# move: -0*1e0 <move> 2e ?09 ?04 ?50 ? * cfmvsrcs mvf9, ?r0 -0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? * cfmvsrpl mvf15, ?r7 -0*1e8 <move\+0x8> 9e ?04 ?14 ?50 ? * cfmvsrls mvf4, ?r1 -0*1ec <move\+0xc> 3e ?08 ?24 ?50 ? * cfmvsrcc mvf8, ?r2 -0*1f0 <move\+0x10> 7e ?02 ?c4 ?50 ? * cfmvsrvc mvf2, ?ip -0*1f4 <move\+0x14> ce ?1b ?94 ?50 ? * cfmvrsgt r9, ?mvf11 -0*1f8 <move\+0x18> 0e ?15 ?a4 ?50 ? * cfmvrseq sl, ?mvf5 -0*1fc <move\+0x1c> ee ?1c ?44 ?50 ? * cfmvrs r4, ?mvf12 -0*200 <move\+0x20> ae ?18 ?b4 ?50 ? * cfmvrsge fp, ?mvf8 -0*204 <move\+0x24> ee ?16 ?54 ?50 ? * cfmvrs r5, ?mvf6 -0*208 <move\+0x28> be ?04 ?94 ?10 ? * cfmvdlrlt mvd4, ?r9 -0*20c <move\+0x2c> 9e ?00 ?a4 ?10 ? * cfmvdlrls mvd0, ?sl -0*210 <move\+0x30> ee ?0a ?44 ?10 ? * cfmvdlr mvd10, ?r4 -0*214 <move\+0x34> 4e ?0e ?b4 ?10 ? * cfmvdlrmi mvd14, ?fp -0*218 <move\+0x38> 8e ?0d ?54 ?10 ? * cfmvdlrhi mvd13, ?r5 -0*21c <move\+0x3c> 2e ?1c ?c4 ?10 ? * cfmvrdlcs ip, ?mvd12 -0*220 <move\+0x40> 6e ?10 ?34 ?10 ? * cfmvrdlvs r3, ?mvd0 -0*224 <move\+0x44> 7e ?1e ?d4 ?10 ? * cfmvrdlvc sp, ?mvd14 -0*228 <move\+0x48> 3e ?1a ?e4 ?10 ? * cfmvrdlcc lr, ?mvd10 -0*22c <move\+0x4c> 1e ?1f ?84 ?10 ? * cfmvrdlne r8, ?mvd15 -0*230 <move\+0x50> de ?06 ?c4 ?30 ? * cfmvdhrle mvd6, ?ip -0*234 <move\+0x54> 4e ?02 ?34 ?30 ? * cfmvdhrmi mvd2, ?r3 -0*238 <move\+0x58> 0e ?05 ?d4 ?30 ? * cfmvdhreq mvd5, ?sp -0*23c <move\+0x5c> ae ?09 ?e4 ?30 ? * cfmvdhrge mvd9, ?lr -0*240 <move\+0x60> ee ?03 ?84 ?30 ? * cfmvdhr mvd3, ?r8 -0*244 <move\+0x64> de ?12 ?54 ?30 ? * cfmvrdhle r5, ?mvd2 -0*248 <move\+0x68> 1e ?16 ?64 ?30 ? * cfmvrdhne r6, ?mvd6 -0*24c <move\+0x6c> be ?17 ?04 ?30 ? * cfmvrdhlt r0, ?mvd7 -0*250 <move\+0x70> 5e ?13 ?74 ?30 ? * cfmvrdhpl r7, ?mvd3 -0*254 <move\+0x74> ce ?11 ?14 ?30 ? * cfmvrdhgt r1, ?mvd1 -0*258 <move\+0x78> 8e ?0f ?55 ?10 ? * cfmv64lrhi mvdx15, ?r5 -0*25c <move\+0x7c> 6e ?0b ?65 ?10 ? * cfmv64lrvs mvdx11, ?r6 -0*260 <move\+0x80> 2e ?09 ?05 ?10 ? * cfmv64lrcs mvdx9, ?r0 -0*264 <move\+0x84> 5e ?0f ?75 ?10 ? * cfmv64lrpl mvdx15, ?r7 -0*268 <move\+0x88> 9e ?04 ?15 ?10 ? * cfmv64lrls mvdx4, ?r1 -0*26c <move\+0x8c> 3e ?1d ?85 ?10 ? * cfmvr64lcc r8, ?mvdx13 -0*270 <move\+0x90> 7e ?11 ?f5 ?10 ? * cfmvr64lvc pc, ?mvdx1 -0*274 <move\+0x94> ce ?1b ?95 ?10 ? * cfmvr64lgt r9, ?mvdx11 -0*278 <move\+0x98> 0e ?15 ?a5 ?10 ? * cfmvr64leq sl, ?mvdx5 -0*27c <move\+0x9c> ee ?1c ?45 ?10 ? * cfmvr64l r4, ?mvdx12 -0*280 <move\+0xa0> ae ?01 ?85 ?30 ? * cfmv64hrge mvdx1, ?r8 -0*284 <move\+0xa4> ee ?0d ?f5 ?30 ? * cfmv64hr mvdx13, ?pc -0*288 <move\+0xa8> be ?04 ?95 ?30 ? * cfmv64hrlt mvdx4, ?r9 -0*28c <move\+0xac> 9e ?00 ?a5 ?30 ? * cfmv64hrls mvdx0, ?sl -0*290 <move\+0xb0> ee ?0a ?45 ?30 ? * cfmv64hr mvdx10, ?r4 -0*294 <move\+0xb4> 4e ?13 ?15 ?30 ? * cfmvr64hmi r1, ?mvdx3 -0*298 <move\+0xb8> 8e ?17 ?25 ?30 ? * cfmvr64hhi r2, ?mvdx7 -0*29c <move\+0xbc> 2e ?1c ?c5 ?30 ? * cfmvr64hcs ip, ?mvdx12 -0*2a0 <move\+0xc0> 6e ?10 ?35 ?30 ? * cfmvr64hvs r3, ?mvdx0 -0*2a4 <move\+0xc4> 7e ?1e ?d5 ?30 ? * cfmvr64hvc sp, ?mvdx14 -0*2a8 <move\+0xc8> 3e ?2a ?04 ?40 ? * cfmval32cc mvax0, ?mvfx10 -0*2ac <move\+0xcc> 1e ?2f ?14 ?40 ? * cfmval32ne mvax1, ?mvfx15 -0*2b0 <move\+0xd0> de ?2b ?04 ?40 ? * cfmval32le mvax0, ?mvfx11 -0*2b4 <move\+0xd4> 4e ?29 ?04 ?40 ? * cfmval32mi mvax0, ?mvfx9 -0*2b8 <move\+0xd8> 0e ?2f ?14 ?40 ? * cfmval32eq mvax1, ?mvfx15 -0*2bc <move\+0xdc> ae ?10 ?94 ?40 ? * cfmv32alge mvfx9, ?mvax0 -0*2c0 <move\+0xe0> ee ?11 ?34 ?40 ? * cfmv32al mvfx3, ?mvax1 -0*2c4 <move\+0xe4> de ?10 ?74 ?40 ? * cfmv32alle mvfx7, ?mvax0 -0*2c8 <move\+0xe8> 1e ?10 ?c4 ?40 ? * cfmv32alne mvfx12, ?mvax0 -0*2cc <move\+0xec> be ?11 ?04 ?40 ? * cfmv32allt mvfx0, ?mvax1 -0*2d0 <move\+0xf0> 5e ?23 ?24 ?60 ? * cfmvam32pl mvax2, ?mvfx3 -0*2d4 <move\+0xf4> ce ?21 ?14 ?60 ? * cfmvam32gt mvax1, ?mvfx1 -0*2d8 <move\+0xf8> 8e ?2d ?34 ?60 ? * cfmvam32hi mvax3, ?mvfx13 -0*2dc <move\+0xfc> 6e ?24 ?34 ?60 ? * cfmvam32vs mvax3, ?mvfx4 -0*2e0 <move\+0x100> 2e ?20 ?14 ?60 ? * cfmvam32cs mvax1, ?mvfx0 -0*2e4 <move\+0x104> 5e ?12 ?f4 ?60 ? * cfmv32ampl mvfx15, ?mvax2 -0*2e8 <move\+0x108> 9e ?11 ?44 ?60 ? * cfmv32amls mvfx4, ?mvax1 -0*2ec <move\+0x10c> 3e ?13 ?84 ?60 ? * cfmv32amcc mvfx8, ?mvax3 -0*2f0 <move\+0x110> 7e ?13 ?24 ?60 ? * cfmv32amvc mvfx2, ?mvax3 -0*2f4 <move\+0x114> ce ?11 ?64 ?60 ? * cfmv32amgt mvfx6, ?mvax1 -0*2f8 <move\+0x118> 0e ?25 ?14 ?80 ? * cfmvah32eq mvax1, ?mvfx5 -0*2fc <move\+0x11c> ee ?2c ?24 ?80 ? * cfmvah32 mvax2, ?mvfx12 -0*300 <move\+0x120> ae ?28 ?34 ?80 ? * cfmvah32ge mvax3, ?mvfx8 -0*304 <move\+0x124> ee ?26 ?24 ?80 ? * cfmvah32 mvax2, ?mvfx6 -0*308 <move\+0x128> be ?22 ?24 ?80 ? * cfmvah32lt mvax2, ?mvfx2 -0*30c <move\+0x12c> 9e ?11 ?04 ?80 ? * cfmv32ahls mvfx0, ?mvax1 -0*310 <move\+0x130> ee ?12 ?a4 ?80 ? * cfmv32ah mvfx10, ?mvax2 -0*314 <move\+0x134> 4e ?13 ?e4 ?80 ? * cfmv32ahmi mvfx14, ?mvax3 -0*318 <move\+0x138> 8e ?12 ?d4 ?80 ? * cfmv32ahhi mvfx13, ?mvax2 -0*31c <move\+0x13c> 2e ?12 ?14 ?80 ? * cfmv32ahcs mvfx1, ?mvax2 -0*320 <move\+0x140> 6e ?20 ?14 ?a0 ? * cfmva32vs mvax1, ?mvfx0 -0*324 <move\+0x144> 7e ?2e ?34 ?a0 ? * cfmva32vc mvax3, ?mvfx14 -0*328 <move\+0x148> 3e ?2a ?04 ?a0 ? * cfmva32cc mvax0, ?mvfx10 -0*32c <move\+0x14c> 1e ?2f ?14 ?a0 ? * cfmva32ne mvax1, ?mvfx15 -0*330 <move\+0x150> de ?2b ?04 ?a0 ? * cfmva32le mvax0, ?mvfx11 -0*334 <move\+0x154> 4e ?11 ?24 ?a0 ? * cfmv32ami mvfx2, ?mvax1 -0*338 <move\+0x158> 0e ?13 ?54 ?a0 ? * cfmv32aeq mvfx5, ?mvax3 -0*33c <move\+0x15c> ae ?10 ?94 ?a0 ? * cfmv32age mvfx9, ?mvax0 -0*340 <move\+0x160> ee ?11 ?34 ?a0 ? * cfmv32a mvfx3, ?mvax1 -0*344 <move\+0x164> de ?10 ?74 ?a0 ? * cfmv32ale mvfx7, ?mvax0 -0*348 <move\+0x168> 1e ?26 ?24 ?c0 ? * cfmva64ne mvax2, ?mvdx6 -0*34c <move\+0x16c> be ?27 ?04 ?c0 ? * cfmva64lt mvax0, ?mvdx7 -0*350 <move\+0x170> 5e ?23 ?24 ?c0 ? * cfmva64pl mvax2, ?mvdx3 -0*354 <move\+0x174> ce ?21 ?14 ?c0 ? * cfmva64gt mvax1, ?mvdx1 -0*358 <move\+0x178> 8e ?2d ?34 ?c0 ? * cfmva64hi mvax3, ?mvdx13 -0*35c <move\+0x17c> 6e ?12 ?b4 ?c0 ? * cfmv64avs mvdx11, ?mvax2 -0*360 <move\+0x180> 2e ?10 ?94 ?c0 ? * cfmv64acs mvdx9, ?mvax0 -0*364 <move\+0x184> 5e ?12 ?f4 ?c0 ? * cfmv64apl mvdx15, ?mvax2 -0*368 <move\+0x188> 9e ?11 ?44 ?c0 ? * cfmv64als mvdx4, ?mvax1 -0*36c <move\+0x18c> 3e ?13 ?84 ?c0 ? * cfmv64acc mvdx8, ?mvax3 -0*370 <move\+0x190> 7e ?20 ?14 ?e0 ? * cfmvsc32vc dspsc, ?mvdx1 -0*374 <move\+0x194> ce ?20 ?b4 ?e0 ? * cfmvsc32gt dspsc, ?mvdx11 -0*378 <move\+0x198> 0e ?20 ?54 ?e0 ? * cfmvsc32eq dspsc, ?mvdx5 -0*37c <move\+0x19c> ee ?20 ?c4 ?e0 ? * cfmvsc32 dspsc, ?mvdx12 -0*380 <move\+0x1a0> ae ?20 ?84 ?e0 ? * cfmvsc32ge dspsc, ?mvdx8 -0*384 <move\+0x1a4> ee ?10 ?d4 ?e0 ? * cfmv32sc mvdx13, ?dspsc -0*388 <move\+0x1a8> be ?10 ?44 ?e0 ? * cfmv32sclt mvdx4, ?dspsc -0*38c <move\+0x1ac> 9e ?10 ?04 ?e0 ? * cfmv32scls mvdx0, ?dspsc -0*390 <move\+0x1b0> ee ?10 ?a4 ?e0 ? * cfmv32sc mvdx10, ?dspsc -0*394 <move\+0x1b4> 4e ?10 ?e4 ?e0 ? * cfmv32scmi mvdx14, ?dspsc -0*398 <move\+0x1b8> 8e ?07 ?d4 ?00 ? * cfcpyshi mvf13, ?mvf7 -0*39c <move\+0x1bc> 2e ?0c ?14 ?00 ? * cfcpyscs mvf1, ?mvf12 -0*3a0 <move\+0x1c0> 6e ?00 ?b4 ?00 ? * cfcpysvs mvf11, ?mvf0 -0*3a4 <move\+0x1c4> 7e ?0e ?54 ?00 ? * cfcpysvc mvf5, ?mvf14 -0*3a8 <move\+0x1c8> 3e ?0a ?c4 ?00 ? * cfcpyscc mvf12, ?mvf10 -0*3ac <move\+0x1cc> 1e ?0f ?84 ?20 ? * cfcpydne mvd8, ?mvd15 -0*3b0 <move\+0x1d0> de ?0b ?64 ?20 ? * cfcpydle mvd6, ?mvd11 -0*3b4 <move\+0x1d4> 4e ?09 ?24 ?20 ? * cfcpydmi mvd2, ?mvd9 -0*3b8 <move\+0x1d8> 0e ?0f ?54 ?20 ? * cfcpydeq mvd5, ?mvd15 -0*3bc <move\+0x1dc> ae ?04 ?94 ?20 ? * cfcpydge mvd9, ?mvd4 -# conv: -0*3c0 <conv> ee ?08 ?34 ?60 ? * cfcvtsd mvd3, ?mvf8 -0*3c4 <conv\+0x4> de ?02 ?74 ?60 ? * cfcvtsdle mvd7, ?mvf2 -0*3c8 <conv\+0x8> 1e ?06 ?c4 ?60 ? * cfcvtsdne mvd12, ?mvf6 -0*3cc <conv\+0xc> be ?07 ?04 ?60 ? * cfcvtsdlt mvd0, ?mvf7 -0*3d0 <conv\+0x10> 5e ?03 ?e4 ?60 ? * cfcvtsdpl mvd14, ?mvf3 -0*3d4 <conv\+0x14> ce ?01 ?a4 ?40 ? * cfcvtdsgt mvf10, ?mvd1 -0*3d8 <conv\+0x18> 8e ?0d ?f4 ?40 ? * cfcvtdshi mvf15, ?mvd13 -0*3dc <conv\+0x1c> 6e ?04 ?b4 ?40 ? * cfcvtdsvs mvf11, ?mvd4 -0*3e0 <conv\+0x20> 2e ?00 ?94 ?40 ? * cfcvtdscs mvf9, ?mvd0 -0*3e4 <conv\+0x24> 5e ?0a ?f4 ?40 ? * cfcvtdspl mvf15, ?mvd10 -0*3e8 <conv\+0x28> 9e ?0e ?44 ?80 ? * cfcvt32sls mvf4, ?mvfx14 -0*3ec <conv\+0x2c> 3e ?0d ?84 ?80 ? * cfcvt32scc mvf8, ?mvfx13 -0*3f0 <conv\+0x30> 7e ?01 ?24 ?80 ? * cfcvt32svc mvf2, ?mvfx1 -0*3f4 <conv\+0x34> ce ?0b ?64 ?80 ? * cfcvt32sgt mvf6, ?mvfx11 -0*3f8 <conv\+0x38> 0e ?05 ?74 ?80 ? * cfcvt32seq mvf7, ?mvfx5 -0*3fc <conv\+0x3c> ee ?0c ?34 ?a0 ? * cfcvt32d mvd3, ?mvfx12 -0*400 <conv\+0x40> ae ?08 ?14 ?a0 ? * cfcvt32dge mvd1, ?mvfx8 -0*404 <conv\+0x44> ee ?06 ?d4 ?a0 ? * cfcvt32d mvd13, ?mvfx6 -0*408 <conv\+0x48> be ?02 ?44 ?a0 ? * cfcvt32dlt mvd4, ?mvfx2 -0*40c <conv\+0x4c> 9e ?05 ?04 ?a0 ? * cfcvt32dls mvd0, ?mvfx5 -0*410 <conv\+0x50> ee ?09 ?a4 ?c0 ? * cfcvt64s mvf10, ?mvdx9 -0*414 <conv\+0x54> 4e ?03 ?e4 ?c0 ? * cfcvt64smi mvf14, ?mvdx3 -0*418 <conv\+0x58> 8e ?07 ?d4 ?c0 ? * cfcvt64shi mvf13, ?mvdx7 -0*41c <conv\+0x5c> 2e ?0c ?14 ?c0 ? * cfcvt64scs mvf1, ?mvdx12 -0*420 <conv\+0x60> 6e ?00 ?b4 ?c0 ? * cfcvt64svs mvf11, ?mvdx0 -0*424 <conv\+0x64> 7e ?0e ?54 ?e0 ? * cfcvt64dvc mvd5, ?mvdx14 -0*428 <conv\+0x68> 3e ?0a ?c4 ?e0 ? * cfcvt64dcc mvd12, ?mvdx10 -0*42c <conv\+0x6c> 1e ?0f ?84 ?e0 ? * cfcvt64dne mvd8, ?mvdx15 -0*430 <conv\+0x70> de ?0b ?64 ?e0 ? * cfcvt64dle mvd6, ?mvdx11 -0*434 <conv\+0x74> 4e ?09 ?24 ?e0 ? * cfcvt64dmi mvd2, ?mvdx9 -0*438 <conv\+0x78> 0e ?1f ?55 ?80 ? * cfcvts32eq mvfx5, ?mvf15 -0*43c <conv\+0x7c> ae ?14 ?95 ?80 ? * cfcvts32ge mvfx9, ?mvf4 -0*440 <conv\+0x80> ee ?18 ?35 ?80 ? * cfcvts32 mvfx3, ?mvf8 -0*444 <conv\+0x84> de ?12 ?75 ?80 ? * cfcvts32le mvfx7, ?mvf2 -0*448 <conv\+0x88> 1e ?16 ?c5 ?80 ? * cfcvts32ne mvfx12, ?mvf6 -0*44c <conv\+0x8c> be ?17 ?05 ?a0 ? * cfcvtd32lt mvfx0, ?mvd7 -0*450 <conv\+0x90> 5e ?13 ?e5 ?a0 ? * cfcvtd32pl mvfx14, ?mvd3 -0*454 <conv\+0x94> ce ?11 ?a5 ?a0 ? * cfcvtd32gt mvfx10, ?mvd1 -0*458 <conv\+0x98> 8e ?1d ?f5 ?a0 ? * cfcvtd32hi mvfx15, ?mvd13 -0*45c <conv\+0x9c> 6e ?14 ?b5 ?a0 ? * cfcvtd32vs mvfx11, ?mvd4 -0*460 <conv\+0xa0> 2e ?10 ?95 ?c0 ? * cftruncs32cs mvfx9, ?mvf0 -0*464 <conv\+0xa4> 5e ?1a ?f5 ?c0 ? * cftruncs32pl mvfx15, ?mvf10 -0*468 <conv\+0xa8> 9e ?1e ?45 ?c0 ? * cftruncs32ls mvfx4, ?mvf14 -0*46c <conv\+0xac> 3e ?1d ?85 ?c0 ? * cftruncs32cc mvfx8, ?mvf13 -0*470 <conv\+0xb0> 7e ?11 ?25 ?c0 ? * cftruncs32vc mvfx2, ?mvf1 -0*474 <conv\+0xb4> ce ?1b ?65 ?e0 ? * cftruncd32gt mvfx6, ?mvd11 -0*478 <conv\+0xb8> 0e ?15 ?75 ?e0 ? * cftruncd32eq mvfx7, ?mvd5 -0*47c <conv\+0xbc> ee ?1c ?35 ?e0 ? * cftruncd32 mvfx3, ?mvd12 -0*480 <conv\+0xc0> ae ?18 ?15 ?e0 ? * cftruncd32ge mvfx1, ?mvd8 -0*484 <conv\+0xc4> ee ?16 ?d5 ?e0 ? * cftruncd32 mvfx13, ?mvd6 -# shift: -0*488 <shift> be ?04 ?35 ?52 ? * cfrshl32lt mvfx4, ?mvfx2, ?r3 -0*48c <shift\+0x4> 5e ?0f ?45 ?5a ? * cfrshl32pl mvfx15, ?mvfx10, ?r4 -0*490 <shift\+0x8> ee ?03 ?25 ?58 ? * cfrshl32 mvfx3, ?mvfx8, ?r2 -0*494 <shift\+0xc> 2e ?01 ?95 ?5c ? * cfrshl32cs mvfx1, ?mvfx12, ?r9 -0*498 <shift\+0x10> 0e ?07 ?75 ?55 ? * cfrshl32eq mvfx7, ?mvfx5, ?r7 -0*49c <shift\+0x14> ce ?0a ?85 ?71 ? * cfrshl64gt mvdx10, ?mvdx1, ?r8 -0*4a0 <shift\+0x18> de ?06 ?65 ?7b ? * cfrshl64le mvdx6, ?mvdx11, ?r6 -0*4a4 <shift\+0x1c> 9e ?00 ?d5 ?75 ? * cfrshl64ls mvdx0, ?mvdx5, ?sp -0*4a8 <shift\+0x20> 9e ?04 ?b5 ?7e ? * cfrshl64ls mvdx4, ?mvdx14, ?fp -0*4ac <shift\+0x24> de ?07 ?c5 ?72 ? * cfrshl64le mvdx7, ?mvdx2, ?ip -0*4b0 <shift\+0x28> 6e ?00 ?b5 ?ef ? * cfsh32vs mvfx11, ?mvfx0, ?#-1 -0*4b4 <shift\+0x2c> ee ?0c ?35 ?28 ? * cfsh32 mvfx3, ?mvfx12, ?#24 -0*4b8 <shift\+0x30> 8e ?0d ?f5 ?41 ? * cfsh32hi mvfx15, ?mvfx13, ?#33 -0*4bc <shift\+0x34> 4e ?09 ?25 ?00 ? * cfsh32mi mvfx2, ?mvfx9, ?#0 -0*4c0 <shift\+0x38> ee ?09 ?a5 ?40 ? * cfsh32 mvfx10, ?mvfx9, ?#32 -0*4c4 <shift\+0x3c> 3e ?2d ?85 ?c1 ? * cfsh64cc mvdx8, ?mvdx13, ?#-31 -0*4c8 <shift\+0x40> 1e ?26 ?c5 ?01 ? * cfsh64ne mvdx12, ?mvdx6, ?#1 -0*4cc <shift\+0x44> 7e ?2e ?55 ?c0 ? * cfsh64vc mvdx5, ?mvdx14, ?#-32 -0*4d0 <shift\+0x48> ae ?28 ?15 ?c5 ? * cfsh64ge mvdx1, ?mvdx8, ?#-27 -0*4d4 <shift\+0x4c> 6e ?24 ?b5 ?eb ? * cfsh64vs mvdx11, ?mvdx4, ?#-5 -# comp: -0*4d8 <comp> 0e ?1f ?a4 ?9a ? * cfcmpseq sl, ?mvf15, ?mvf10 -0*4dc <comp\+0x4> 4e ?13 ?14 ?98 ? * cfcmpsmi r1, ?mvf3, ?mvf8 -0*4e0 <comp\+0x8> 7e ?11 ?f4 ?9c ? * cfcmpsvc pc, ?mvf1, ?mvf12 -0*4e4 <comp\+0xc> be ?17 ?04 ?95 ? * cfcmpslt r0, ?mvf7, ?mvf5 -0*4e8 <comp\+0x10> 3e ?1a ?e4 ?91 ? * cfcmpscc lr, ?mvf10, ?mvf1 -0*4ec <comp\+0x14> ee ?16 ?54 ?bb ? * cfcmpd r5, ?mvd6, ?mvd11 -0*4f0 <comp\+0x18> 2e ?10 ?34 ?b5 ? * cfcmpdcs r3, ?mvd0, ?mvd5 -0*4f4 <comp\+0x1c> ae ?14 ?44 ?be ? * cfcmpdge r4, ?mvd4, ?mvd14 -0*4f8 <comp\+0x20> 8e ?17 ?24 ?b2 ? * cfcmpdhi r2, ?mvd7, ?mvd2 -0*4fc <comp\+0x24> ce ?1b ?94 ?b0 ? * cfcmpdgt r9, ?mvd11, ?mvd0 -0*500 <comp\+0x28> 5e ?13 ?75 ?9c ? * cfcmp32pl r7, ?mvfx3, ?mvfx12 -0*504 <comp\+0x2c> 1e ?1f ?85 ?9d ? * cfcmp32ne r8, ?mvfx15, ?mvfx13 -0*508 <comp\+0x30> be ?12 ?65 ?99 ? * cfcmp32lt r6, ?mvfx2, ?mvfx9 -0*50c <comp\+0x34> 5e ?1a ?d5 ?99 ? * cfcmp32pl sp, ?mvfx10, ?mvfx9 -0*510 <comp\+0x38> ee ?18 ?b5 ?9d ? * cfcmp32 fp, ?mvfx8, ?mvfx13 -0*514 <comp\+0x3c> 2e ?1c ?c5 ?b6 ? * cfcmp64cs ip, ?mvdx12, ?mvdx6 -0*518 <comp\+0x40> 0e ?15 ?a5 ?be ? * cfcmp64eq sl, ?mvdx5, ?mvdx14 -0*51c <comp\+0x44> ce ?11 ?15 ?b8 ? * cfcmp64gt r1, ?mvdx1, ?mvdx8 -0*520 <comp\+0x48> de ?1b ?f5 ?b4 ? * cfcmp64le pc, ?mvdx11, ?mvdx4 -0*524 <comp\+0x4c> 9e ?15 ?05 ?bf ? * cfcmp64ls r0, ?mvdx5, ?mvdx15 -# fp_arith: -0*528 <fp_arith> 9e ?3e ?44 ?00 ? * cfabssls mvf4, ?mvf14 -0*52c <fp_arith\+0x4> 3e ?3d ?84 ?00 ? * cfabsscc mvf8, ?mvf13 -0*530 <fp_arith\+0x8> 7e ?31 ?24 ?00 ? * cfabssvc mvf2, ?mvf1 -0*534 <fp_arith\+0xc> ce ?3b ?64 ?00 ? * cfabssgt mvf6, ?mvf11 -0*538 <fp_arith\+0x10> 0e ?35 ?74 ?00 ? * cfabsseq mvf7, ?mvf5 -0*53c <fp_arith\+0x14> ee ?3c ?34 ?20 ? * cfabsd mvd3, ?mvd12 -0*540 <fp_arith\+0x18> ae ?38 ?14 ?20 ? * cfabsdge mvd1, ?mvd8 -0*544 <fp_arith\+0x1c> ee ?36 ?d4 ?20 ? * cfabsd mvd13, ?mvd6 -0*548 <fp_arith\+0x20> be ?32 ?44 ?20 ? * cfabsdlt mvd4, ?mvd2 -0*54c <fp_arith\+0x24> 9e ?35 ?04 ?20 ? * cfabsdls mvd0, ?mvd5 -0*550 <fp_arith\+0x28> ee ?39 ?a4 ?40 ? * cfnegs mvf10, ?mvf9 -0*554 <fp_arith\+0x2c> 4e ?33 ?e4 ?40 ? * cfnegsmi mvf14, ?mvf3 -0*558 <fp_arith\+0x30> 8e ?37 ?d4 ?40 ? * cfnegshi mvf13, ?mvf7 -0*55c <fp_arith\+0x34> 2e ?3c ?14 ?40 ? * cfnegscs mvf1, ?mvf12 -0*560 <fp_arith\+0x38> 6e ?30 ?b4 ?40 ? * cfnegsvs mvf11, ?mvf0 -0*564 <fp_arith\+0x3c> 7e ?3e ?54 ?60 ? * cfnegdvc mvd5, ?mvd14 -0*568 <fp_arith\+0x40> 3e ?3a ?c4 ?60 ? * cfnegdcc mvd12, ?mvd10 -0*56c <fp_arith\+0x44> 1e ?3f ?84 ?60 ? * cfnegdne mvd8, ?mvd15 -0*570 <fp_arith\+0x48> de ?3b ?64 ?60 ? * cfnegdle mvd6, ?mvd11 -0*574 <fp_arith\+0x4c> 4e ?39 ?24 ?60 ? * cfnegdmi mvd2, ?mvd9 -0*578 <fp_arith\+0x50> 0e ?3f ?54 ?8a ? * cfaddseq mvf5, ?mvf15, ?mvf10 -0*57c <fp_arith\+0x54> 4e ?33 ?e4 ?88 ? * cfaddsmi mvf14, ?mvf3, ?mvf8 -0*580 <fp_arith\+0x58> 7e ?31 ?24 ?8c ? * cfaddsvc mvf2, ?mvf1, ?mvf12 -0*584 <fp_arith\+0x5c> be ?37 ?04 ?85 ? * cfaddslt mvf0, ?mvf7, ?mvf5 -0*588 <fp_arith\+0x60> 3e ?3a ?c4 ?81 ? * cfaddscc mvf12, ?mvf10, ?mvf1 -0*58c <fp_arith\+0x64> ee ?36 ?d4 ?ab ? * cfaddd mvd13, ?mvd6, ?mvd11 -0*590 <fp_arith\+0x68> 2e ?30 ?94 ?a5 ? * cfadddcs mvd9, ?mvd0, ?mvd5 -0*594 <fp_arith\+0x6c> ae ?34 ?94 ?ae ? * cfadddge mvd9, ?mvd4, ?mvd14 -0*598 <fp_arith\+0x70> 8e ?37 ?d4 ?a2 ? * cfadddhi mvd13, ?mvd7, ?mvd2 -0*59c <fp_arith\+0x74> ce ?3b ?64 ?a0 ? * cfadddgt mvd6, ?mvd11, ?mvd0 -0*5a0 <fp_arith\+0x78> 5e ?33 ?e4 ?cc ? * cfsubspl mvf14, ?mvf3, ?mvf12 -0*5a4 <fp_arith\+0x7c> 1e ?3f ?84 ?cd ? * cfsubsne mvf8, ?mvf15, ?mvf13 -0*5a8 <fp_arith\+0x80> be ?32 ?44 ?c9 ? * cfsubslt mvf4, ?mvf2, ?mvf9 -0*5ac <fp_arith\+0x84> 5e ?3a ?f4 ?c9 ? * cfsubspl mvf15, ?mvf10, ?mvf9 -0*5b0 <fp_arith\+0x88> ee ?38 ?34 ?cd ? * cfsubs mvf3, ?mvf8, ?mvf13 -0*5b4 <fp_arith\+0x8c> 2e ?3c ?14 ?e6 ? * cfsubdcs mvd1, ?mvd12, ?mvd6 -0*5b8 <fp_arith\+0x90> 0e ?35 ?74 ?ee ? * cfsubdeq mvd7, ?mvd5, ?mvd14 -0*5bc <fp_arith\+0x94> ce ?31 ?a4 ?e8 ? * cfsubdgt mvd10, ?mvd1, ?mvd8 -0*5c0 <fp_arith\+0x98> de ?3b ?64 ?e4 ? * cfsubdle mvd6, ?mvd11, ?mvd4 -0*5c4 <fp_arith\+0x9c> 9e ?35 ?04 ?ef ? * cfsubdls mvd0, ?mvd5, ?mvd15 -0*5c8 <fp_arith\+0xa0> 9e ?1e ?44 ?03 ? * cfmulsls mvf4, ?mvf14, ?mvf3 -0*5cc <fp_arith\+0xa4> de ?12 ?74 ?01 ? * cfmulsle mvf7, ?mvf2, ?mvf1 -0*5d0 <fp_arith\+0xa8> 6e ?10 ?b4 ?07 ? * cfmulsvs mvf11, ?mvf0, ?mvf7 -0*5d4 <fp_arith\+0xac> ee ?1c ?34 ?0a ? * cfmuls mvf3, ?mvf12, ?mvf10 -0*5d8 <fp_arith\+0xb0> 8e ?1d ?f4 ?06 ? * cfmulshi mvf15, ?mvf13, ?mvf6 -0*5dc <fp_arith\+0xb4> 4e ?19 ?24 ?20 ? * cfmuldmi mvd2, ?mvd9, ?mvd0 -0*5e0 <fp_arith\+0xb8> ee ?19 ?a4 ?24 ? * cfmuld mvd10, ?mvd9, ?mvd4 -0*5e4 <fp_arith\+0xbc> 3e ?1d ?84 ?27 ? * cfmuldcc mvd8, ?mvd13, ?mvd7 -0*5e8 <fp_arith\+0xc0> 1e ?16 ?c4 ?2b ? * cfmuldne mvd12, ?mvd6, ?mvd11 -0*5ec <fp_arith\+0xc4> 7e ?1e ?54 ?23 ? * cfmuldvc mvd5, ?mvd14, ?mvd3 -# int_arith: -0*5f0 <int_arith> ae ?38 ?15 ?00 ? * cfabs32ge mvfx1, ?mvfx8 -0*5f4 <int_arith\+0x4> ee ?36 ?d5 ?00 ? * cfabs32 mvfx13, ?mvfx6 -0*5f8 <int_arith\+0x8> be ?32 ?45 ?00 ? * cfabs32lt mvfx4, ?mvfx2 -0*5fc <int_arith\+0xc> 9e ?35 ?05 ?00 ? * cfabs32ls mvfx0, ?mvfx5 -0*600 <int_arith\+0x10> ee ?39 ?a5 ?00 ? * cfabs32 mvfx10, ?mvfx9 -0*604 <int_arith\+0x14> 4e ?33 ?e5 ?20 ? * cfabs64mi mvdx14, ?mvdx3 -0*608 <int_arith\+0x18> 8e ?37 ?d5 ?20 ? * cfabs64hi mvdx13, ?mvdx7 -0*60c <int_arith\+0x1c> 2e ?3c ?15 ?20 ? * cfabs64cs mvdx1, ?mvdx12 -0*610 <int_arith\+0x20> 6e ?30 ?b5 ?20 ? * cfabs64vs mvdx11, ?mvdx0 -0*614 <int_arith\+0x24> 7e ?3e ?55 ?20 ? * cfabs64vc mvdx5, ?mvdx14 -0*618 <int_arith\+0x28> 3e ?3a ?c5 ?40 ? * cfneg32cc mvfx12, ?mvfx10 -0*61c <int_arith\+0x2c> 1e ?3f ?85 ?40 ? * cfneg32ne mvfx8, ?mvfx15 -0*620 <int_arith\+0x30> de ?3b ?65 ?40 ? * cfneg32le mvfx6, ?mvfx11 -0*624 <int_arith\+0x34> 4e ?39 ?25 ?40 ? * cfneg32mi mvfx2, ?mvfx9 -0*628 <int_arith\+0x38> 0e ?3f ?55 ?40 ? * cfneg32eq mvfx5, ?mvfx15 -0*62c <int_arith\+0x3c> ae ?34 ?95 ?60 ? * cfneg64ge mvdx9, ?mvdx4 -0*630 <int_arith\+0x40> ee ?38 ?35 ?60 ? * cfneg64 mvdx3, ?mvdx8 -0*634 <int_arith\+0x44> de ?32 ?75 ?60 ? * cfneg64le mvdx7, ?mvdx2 -0*638 <int_arith\+0x48> 1e ?36 ?c5 ?60 ? * cfneg64ne mvdx12, ?mvdx6 -0*63c <int_arith\+0x4c> be ?37 ?05 ?60 ? * cfneg64lt mvdx0, ?mvdx7 -0*640 <int_arith\+0x50> 5e ?33 ?e5 ?8c ? * cfadd32pl mvfx14, ?mvfx3, ?mvfx12 -0*644 <int_arith\+0x54> 1e ?3f ?85 ?8d ? * cfadd32ne mvfx8, ?mvfx15, ?mvfx13 -0*648 <int_arith\+0x58> be ?32 ?45 ?89 ? * cfadd32lt mvfx4, ?mvfx2, ?mvfx9 -0*64c <int_arith\+0x5c> 5e ?3a ?f5 ?89 ? * cfadd32pl mvfx15, ?mvfx10, ?mvfx9 -0*650 <int_arith\+0x60> ee ?38 ?35 ?8d ? * cfadd32 mvfx3, ?mvfx8, ?mvfx13 -0*654 <int_arith\+0x64> 2e ?3c ?15 ?a6 ? * cfadd64cs mvdx1, ?mvdx12, ?mvdx6 -0*658 <int_arith\+0x68> 0e ?35 ?75 ?ae ? * cfadd64eq mvdx7, ?mvdx5, ?mvdx14 -0*65c <int_arith\+0x6c> ce ?31 ?a5 ?a8 ? * cfadd64gt mvdx10, ?mvdx1, ?mvdx8 -0*660 <int_arith\+0x70> de ?3b ?65 ?a4 ? * cfadd64le mvdx6, ?mvdx11, ?mvdx4 -0*664 <int_arith\+0x74> 9e ?35 ?05 ?af ? * cfadd64ls mvdx0, ?mvdx5, ?mvdx15 -0*668 <int_arith\+0x78> 9e ?3e ?45 ?c3 ? * cfsub32ls mvfx4, ?mvfx14, ?mvfx3 -0*66c <int_arith\+0x7c> de ?32 ?75 ?c1 ? * cfsub32le mvfx7, ?mvfx2, ?mvfx1 -0*670 <int_arith\+0x80> 6e ?30 ?b5 ?c7 ? * cfsub32vs mvfx11, ?mvfx0, ?mvfx7 -0*674 <int_arith\+0x84> ee ?3c ?35 ?ca ? * cfsub32 mvfx3, ?mvfx12, ?mvfx10 -0*678 <int_arith\+0x88> 8e ?3d ?f5 ?c6 ? * cfsub32hi mvfx15, ?mvfx13, ?mvfx6 -0*67c <int_arith\+0x8c> 4e ?39 ?25 ?e0 ? * cfsub64mi mvdx2, ?mvdx9, ?mvdx0 -0*680 <int_arith\+0x90> ee ?39 ?a5 ?e4 ? * cfsub64 mvdx10, ?mvdx9, ?mvdx4 -0*684 <int_arith\+0x94> 3e ?3d ?85 ?e7 ? * cfsub64cc mvdx8, ?mvdx13, ?mvdx7 -0*688 <int_arith\+0x98> 1e ?36 ?c5 ?eb ? * cfsub64ne mvdx12, ?mvdx6, ?mvdx11 -0*68c <int_arith\+0x9c> 7e ?3e ?55 ?e3 ? * cfsub64vc mvdx5, ?mvdx14, ?mvdx3 -0*690 <int_arith\+0xa0> ae ?18 ?15 ?0f ? * cfmul32ge mvfx1, ?mvfx8, ?mvfx15 -0*694 <int_arith\+0xa4> 6e ?14 ?b5 ?02 ? * cfmul32vs mvfx11, ?mvfx4, ?mvfx2 -0*698 <int_arith\+0xa8> 0e ?1f ?55 ?0a ? * cfmul32eq mvfx5, ?mvfx15, ?mvfx10 -0*69c <int_arith\+0xac> 4e ?13 ?e5 ?08 ? * cfmul32mi mvfx14, ?mvfx3, ?mvfx8 -0*6a0 <int_arith\+0xb0> 7e ?11 ?25 ?0c ? * cfmul32vc mvfx2, ?mvfx1, ?mvfx12 -0*6a4 <int_arith\+0xb4> be ?17 ?05 ?25 ? * cfmul64lt mvdx0, ?mvdx7, ?mvdx5 -0*6a8 <int_arith\+0xb8> 3e ?1a ?c5 ?21 ? * cfmul64cc mvdx12, ?mvdx10, ?mvdx1 -0*6ac <int_arith\+0xbc> ee ?16 ?d5 ?2b ? * cfmul64 mvdx13, ?mvdx6, ?mvdx11 -0*6b0 <int_arith\+0xc0> 2e ?10 ?95 ?25 ? * cfmul64cs mvdx9, ?mvdx0, ?mvdx5 -0*6b4 <int_arith\+0xc4> ae ?14 ?95 ?2e ? * cfmul64ge mvdx9, ?mvdx4, ?mvdx14 -0*6b8 <int_arith\+0xc8> 8e ?17 ?d5 ?42 ? * cfmac32hi mvfx13, ?mvfx7, ?mvfx2 -0*6bc <int_arith\+0xcc> ce ?1b ?65 ?40 ? * cfmac32gt mvfx6, ?mvfx11, ?mvfx0 -0*6c0 <int_arith\+0xd0> 5e ?13 ?e5 ?4c ? * cfmac32pl mvfx14, ?mvfx3, ?mvfx12 -0*6c4 <int_arith\+0xd4> 1e ?1f ?85 ?4d ? * cfmac32ne mvfx8, ?mvfx15, ?mvfx13 -0*6c8 <int_arith\+0xd8> be ?12 ?45 ?49 ? * cfmac32lt mvfx4, ?mvfx2, ?mvfx9 -0*6cc <int_arith\+0xdc> 5e ?1a ?f5 ?69 ? * cfmsc32pl mvfx15, ?mvfx10, ?mvfx9 -0*6d0 <int_arith\+0xe0> ee ?18 ?35 ?6d ? * cfmsc32 mvfx3, ?mvfx8, ?mvfx13 -0*6d4 <int_arith\+0xe4> 2e ?1c ?15 ?66 ? * cfmsc32cs mvfx1, ?mvfx12, ?mvfx6 -0*6d8 <int_arith\+0xe8> 0e ?15 ?75 ?6e ? * cfmsc32eq mvfx7, ?mvfx5, ?mvfx14 -0*6dc <int_arith\+0xec> ce ?11 ?a5 ?68 ? * cfmsc32gt mvfx10, ?mvfx1, ?mvfx8 -# acc_arith: -0*6e0 <acc_arith> de ?04 ?b6 ?02 ? * cfmadd32le mvax0, ?mvfx11, ?mvfx4, ?mvfx2 -0*6e4 <acc_arith\+0x4> 9e ?0f ?56 ?0a ? * cfmadd32ls mvax0, ?mvfx5, ?mvfx15, ?mvfx10 -0*6e8 <acc_arith\+0x8> 9e ?03 ?e6 ?08 ? * cfmadd32ls mvax0, ?mvfx14, ?mvfx3, ?mvfx8 -0*6ec <acc_arith\+0xc> de ?01 ?26 ?4c ? * cfmadd32le mvax2, ?mvfx2, ?mvfx1, ?mvfx12 -0*6f0 <acc_arith\+0x10> 6e ?07 ?06 ?25 ? * cfmadd32vs mvax1, ?mvfx0, ?mvfx7, ?mvfx5 -0*6f4 <acc_arith\+0x14> ee ?1a ?c6 ?41 ? * cfmsub32 mvax2, ?mvfx12, ?mvfx10, ?mvfx1 -0*6f8 <acc_arith\+0x18> 8e ?16 ?d6 ?6b ? * cfmsub32hi mvax3, ?mvfx13, ?mvfx6, ?mvfx11 -0*6fc <acc_arith\+0x1c> 4e ?10 ?96 ?05 ? * cfmsub32mi mvax0, ?mvfx9, ?mvfx0, ?mvfx5 -0*700 <acc_arith\+0x20> ee ?14 ?96 ?4e ? * cfmsub32 mvax2, ?mvfx9, ?mvfx4, ?mvfx14 -0*704 <acc_arith\+0x24> 3e ?17 ?d6 ?22 ? * cfmsub32cc mvax1, ?mvfx13, ?mvfx7, ?mvfx2 -0*708 <acc_arith\+0x28> 1e ?2b ?06 ?40 ? * cfmadda32ne mvax2, ?mvax0, ?mvfx11, ?mvfx0 -0*70c <acc_arith\+0x2c> 7e ?23 ?26 ?6c ? * cfmadda32vc mvax3, ?mvax2, ?mvfx3, ?mvfx12 -0*710 <acc_arith\+0x30> ae ?2f ?16 ?6d ? * cfmadda32ge mvax3, ?mvax1, ?mvfx15, ?mvfx13 -0*714 <acc_arith\+0x34> 6e ?22 ?26 ?69 ? * cfmadda32vs mvax3, ?mvax2, ?mvfx2, ?mvfx9 -0*718 <acc_arith\+0x38> 0e ?2a ?36 ?29 ? * cfmadda32eq mvax1, ?mvax3, ?mvfx10, ?mvfx9 -0*71c <acc_arith\+0x3c> 4e ?38 ?36 ?2d ? * cfmsuba32mi mvax1, ?mvax3, ?mvfx8, ?mvfx13 -0*720 <acc_arith\+0x40> 7e ?3c ?36 ?06 ? * cfmsuba32vc mvax0, ?mvax3, ?mvfx12, ?mvfx6 -0*724 <acc_arith\+0x44> be ?35 ?16 ?0e ? * cfmsuba32lt mvax0, ?mvax1, ?mvfx5, ?mvfx14 -0*728 <acc_arith\+0x48> 3e ?31 ?16 ?08 ? * cfmsuba32cc mvax0, ?mvax1, ?mvfx1, ?mvfx8 -0*72c <acc_arith\+0x4c> ee ?3b ?06 ?44 ? * cfmsuba32 mvax2, ?mvax0, ?mvfx11, ?mvfx4 diff --git a/binutils-2.17/gas/testsuite/gas/arm/maverick.s b/binutils-2.17/gas/testsuite/gas/arm/maverick.s deleted file mode 100644 index e32d36b6..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/maverick.s +++ /dev/null @@ -1,470 +0,0 @@ - .text - .align -load_store: - cfldrseq mvf5, [sp, #1020] - cfldrsmi mvf14, [r11, #292] - cfldrsvc mvf2, [r12, #-956] - cfldrslt mvf0, [sl, #-1020] - cfldrscc mvf12, [r1, #-156] - cfldrs mvf13, [r9, #416]! - cfldrscs mvf9, [r0, #-1020]! - cfldrsls mvf4, [r1, #-156]! - cfldrsle mvf7, [r9, #416]! - cfldrsvs mvf11, [r0, #-1020]! - cfldrscc mvf12, [r1], #-156 - cfldrs mvf13, [r9], #416 - cfldrscs mvf9, [r0], #-1020 - cfldrsls mvf4, [r1], #-156 - cfldrsle mvf7, [r9], #416 - cfldrdvs mvd11, [r0, #-1020] - cfldrdcc mvd12, [r1, #-156] - cfldrd mvd13, [r9, #416] - cfldrdcs mvd9, [r0, #-1020] - cfldrdls mvd4, [r1, #-156] - cfldrdle mvd7, [r9, #416]! - cfldrdvs mvd11, [r0, #-1020]! - cfldrdcc mvd12, [r1, #-156]! - cfldrd mvd13, [r9, #416]! - cfldrdcs mvd9, [r0, #-1020]! - cfldrdls mvd4, [r1], #-156 - cfldrdle mvd7, [r9], #416 - cfldrdvs mvd11, [r0], #-1020 - cfldrdcc mvd12, [r1], #-156 - cfldrd mvd13, [r9], #416 - cfldr32cs mvfx9, [r0, #-1020] - cfldr32ls mvfx4, [r1, #-156] - cfldr32le mvfx7, [r9, #416] - cfldr32vs mvfx11, [r0, #-1020] - cfldr32cc mvfx12, [r1, #-156] - cfldr32 mvfx13, [r9, #416]! - cfldr32cs mvfx9, [r0, #-1020]! - cfldr32ls mvfx4, [r1, #-156]! - cfldr32le mvfx7, [r9, #416]! - cfldr32vs mvfx11, [r0, #-1020]! - cfldr32cc mvfx12, [r1], #-156 - cfldr32 mvfx13, [r9], #416 - cfldr32cs mvfx9, [r0], #-1020 - cfldr32ls mvfx4, [r1], #-156 - cfldr32le mvfx7, [r9], #416 - cfldr64vs mvdx11, [r0, #-1020] - cfldr64cc mvdx12, [r1, #-156] - cfldr64 mvdx13, [r9, #416] - cfldr64cs mvdx9, [r0, #-1020] - cfldr64ls mvdx4, [r1, #-156] - cfldr64le mvdx7, [r9, #416]! - cfldr64vs mvdx11, [r0, #-1020]! - cfldr64cc mvdx12, [r1, #-156]! - cfldr64 mvdx13, [r9, #416]! - cfldr64cs mvdx9, [r0, #-1020]! - cfldr64ls mvdx4, [r1], #-156 - cfldr64le mvdx7, [r9], #416 - cfldr64vs mvdx11, [r0], #-1020 - cfldr64cc mvdx12, [r1], #-156 - cfldr64 mvdx13, [r9], #416 - cfstrscs mvf9, [r0, #-1020] - cfstrsls mvf4, [r1, #-156] - cfstrsle mvf7, [r9, #416] - cfstrsvs mvf11, [r0, #-1020] - cfstrscc mvf12, [r1, #-156] - cfstrs mvf13, [r9, #416]! - cfstrscs mvf9, [r0, #-1020]! - cfstrsls mvf4, [r1, #-156]! - cfstrsle mvf7, [r9, #416]! - cfstrsvs mvf11, [r0, #-1020]! - cfstrscc mvf12, [r1], #-156 - cfstrs mvf13, [r9], #416 - cfstrscs mvf9, [r0], #-1020 - cfstrsls mvf4, [r1], #-156 - cfstrsle mvf7, [r9], #416 - cfstrdvs mvd11, [r0, #-1020] - cfstrdcc mvd12, [r1, #-156] - cfstrd mvd13, [r9, #416] - cfstrdcs mvd9, [r0, #-1020] - cfstrdls mvd4, [r1, #-156] - cfstrdle mvd7, [r9, #416]! - cfstrdvs mvd11, [r0, #-1020]! - cfstrdcc mvd12, [r1, #-156]! - cfstrd mvd13, [r9, #416]! - cfstrdcs mvd9, [r0, #-1020]! - cfstrdls mvd4, [r1], #-156 - cfstrdle mvd7, [r9], #416 - cfstrdvs mvd11, [r0], #-1020 - cfstrdcc mvd12, [r1], #-156 - cfstrd mvd13, [r9], #416 - cfstr32cs mvfx9, [r0, #-1020] - cfstr32ls mvfx4, [r1, #-156] - cfstr32le mvfx7, [r9, #416] - cfstr32vs mvfx11, [r0, #-1020] - cfstr32cc mvfx12, [r1, #-156] - cfstr32 mvfx13, [r9, #416]! - cfstr32cs mvfx9, [r0, #-1020]! - cfstr32ls mvfx4, [r1, #-156]! - cfstr32le mvfx7, [r9, #416]! - cfstr32vs mvfx11, [r0, #-1020]! - cfstr32cc mvfx12, [r1], #-156 - cfstr32 mvfx13, [r9], #416 - cfstr32cs mvfx9, [r0], #-1020 - cfstr32ls mvfx4, [r1], #-156 - cfstr32le mvfx7, [r9], #416 - cfstr64vs mvdx11, [r0, #-1020] - cfstr64cc mvdx12, [r1, #-156] - cfstr64 mvdx13, [r9, #416] - cfstr64cs mvdx9, [r0, #-1020] - cfstr64ls mvdx4, [r1, #-156] - cfstr64le mvdx7, [r9, #416]! - cfstr64vs mvdx11, [r0, #-1020]! - cfstr64cc mvdx12, [r1, #-156]! - cfstr64 mvdx13, [r9, #416]! - cfstr64cs mvdx9, [r0, #-1020]! - cfstr64ls mvdx4, [r1], #-156 - cfstr64le mvdx7, [r9], #416 - cfstr64vs mvdx11, [r0], #-1020 - cfstr64cc mvdx12, [r1], #-156 - cfstr64 mvdx13, [r9], #416 -move: - cfmvsrcs mvf9, r0 - cfmvsrpl mvf15, r7 - cfmvsrls mvf4, r1 - cfmvsrcc mvf8, r2 - cfmvsrvc mvf2, r12 - cfmvrsgt r9, mvf11 - cfmvrseq sl, mvf5 - cfmvrsal r4, mvf12 - cfmvrsge fp, mvf8 - cfmvrs r5, mvf6 - cfmvdlrlt mvd4, r9 - cfmvdlrls mvd0, r10 - cfmvdlr mvd10, r4 - cfmvdlrmi mvd14, r11 - cfmvdlrhi mvd13, r5 - cfmvrdlcs r12, mvd12 - cfmvrdlvs r3, mvd0 - cfmvrdlvc r13, mvd14 - cfmvrdlcc r14, mvd10 - cfmvrdlne r8, mvd15 - cfmvdhrle mvd6, ip - cfmvdhrmi mvd2, r3 - cfmvdhreq mvd5, sp - cfmvdhrge mvd9, lr - cfmvdhral mvd3, r8 - cfmvrdhle r5, mvd2 - cfmvrdhne r6, mvd6 - cfmvrdhlt r0, mvd7 - cfmvrdhpl r7, mvd3 - cfmvrdhgt r1, mvd1 - cfmv64lrhi mvdx15, r5 - cfmv64lrvs mvdx11, r6 - cfmv64lrcs mvdx9, r0 - cfmv64lrpl mvdx15, r7 - cfmv64lrls mvdx4, r1 - cfmvr64lcc r8, mvdx13 - cfmvr64lvc pc, mvdx1 - cfmvr64lgt r9, mvdx11 - cfmvr64leq sl, mvdx5 - cfmvr64lal r4, mvdx12 - cfmv64hrge mvdx1, r8 - cfmv64hr mvdx13, r15 - cfmv64hrlt mvdx4, r9 - cfmv64hrls mvdx0, r10 - cfmv64hr mvdx10, r4 - cfmvr64hmi r1, mvdx3 - cfmvr64hhi r2, mvdx7 - cfmvr64hcs r12, mvdx12 - cfmvr64hvs r3, mvdx0 - cfmvr64hvc r13, mvdx14 - cfmval32cc mvax0, mvfx10 - cfmval32ne mvax1, mvfx15 - cfmval32le mvax0, mvfx11 - cfmval32mi mvax0, mvfx9 - cfmval32eq mvax1, mvfx15 - cfmv32alge mvfx9, mvax0 - cfmv32alal mvfx3, mvax1 - cfmv32alle mvfx7, mvax0 - cfmv32alne mvfx12, mvax0 - cfmv32allt mvfx0, mvax1 - cfmvam32pl mvax2, mvfx3 - cfmvam32gt mvax1, mvfx1 - cfmvam32hi mvax3, mvfx13 - cfmvam32vs mvax3, mvfx4 - cfmvam32cs mvax1, mvfx0 - cfmv32ampl mvfx15, mvax2 - cfmv32amls mvfx4, mvax1 - cfmv32amcc mvfx8, mvax3 - cfmv32amvc mvfx2, mvax3 - cfmv32amgt mvfx6, mvax1 - cfmvah32eq mvax1, mvfx5 - cfmvah32al mvax2, mvfx12 - cfmvah32ge mvax3, mvfx8 - cfmvah32 mvax2, mvfx6 - cfmvah32lt mvax2, mvfx2 - cfmv32ahls mvfx0, mvax1 - cfmv32ah mvfx10, mvax2 - cfmv32ahmi mvfx14, mvax3 - cfmv32ahhi mvfx13, mvax2 - cfmv32ahcs mvfx1, mvax2 - cfmva32vs mvax1, mvfx0 - cfmva32vc mvax3, mvfx14 - cfmva32cc mvax0, mvfx10 - cfmva32ne mvax1, mvfx15 - cfmva32le mvax0, mvfx11 - cfmv32ami mvfx2, mvax1 - cfmv32aeq mvfx5, mvax3 - cfmv32age mvfx9, mvax0 - cfmv32aal mvfx3, mvax1 - cfmv32ale mvfx7, mvax0 - cfmva64ne mvax2, mvdx6 - cfmva64lt mvax0, mvdx7 - cfmva64pl mvax2, mvdx3 - cfmva64gt mvax1, mvdx1 - cfmva64hi mvax3, mvdx13 - cfmv64avs mvdx11, mvax2 - cfmv64acs mvdx9, mvax0 - cfmv64apl mvdx15, mvax2 - cfmv64als mvdx4, mvax1 - cfmv64acc mvdx8, mvax3 - cfmvsc32vc dspsc, mvdx1 - cfmvsc32gt dspsc, mvdx11 - cfmvsc32eq dspsc, mvdx5 - cfmvsc32al dspsc, mvdx12 - cfmvsc32ge dspsc, mvdx8 - cfmv32sc mvdx13, dspsc - cfmv32sclt mvdx4, dspsc - cfmv32scls mvdx0, dspsc - cfmv32sc mvdx10, dspsc - cfmv32scmi mvdx14, dspsc - cfcpyshi mvf13, mvf7 - cfcpyscs mvf1, mvf12 - cfcpysvs mvf11, mvf0 - cfcpysvc mvf5, mvf14 - cfcpyscc mvf12, mvf10 - cfcpydne mvd8, mvd15 - cfcpydle mvd6, mvd11 - cfcpydmi mvd2, mvd9 - cfcpydeq mvd5, mvd15 - cfcpydge mvd9, mvd4 -conv: - cfcvtsdal mvd3, mvf8 - cfcvtsdle mvd7, mvf2 - cfcvtsdne mvd12, mvf6 - cfcvtsdlt mvd0, mvf7 - cfcvtsdpl mvd14, mvf3 - cfcvtdsgt mvf10, mvd1 - cfcvtdshi mvf15, mvd13 - cfcvtdsvs mvf11, mvd4 - cfcvtdscs mvf9, mvd0 - cfcvtdspl mvf15, mvd10 - cfcvt32sls mvf4, mvfx14 - cfcvt32scc mvf8, mvfx13 - cfcvt32svc mvf2, mvfx1 - cfcvt32sgt mvf6, mvfx11 - cfcvt32seq mvf7, mvfx5 - cfcvt32dal mvd3, mvfx12 - cfcvt32dge mvd1, mvfx8 - cfcvt32d mvd13, mvfx6 - cfcvt32dlt mvd4, mvfx2 - cfcvt32dls mvd0, mvfx5 - cfcvt64s mvf10, mvdx9 - cfcvt64smi mvf14, mvdx3 - cfcvt64shi mvf13, mvdx7 - cfcvt64scs mvf1, mvdx12 - cfcvt64svs mvf11, mvdx0 - cfcvt64dvc mvd5, mvdx14 - cfcvt64dcc mvd12, mvdx10 - cfcvt64dne mvd8, mvdx15 - cfcvt64dle mvd6, mvdx11 - cfcvt64dmi mvd2, mvdx9 - cfcvts32eq mvfx5, mvf15 - cfcvts32ge mvfx9, mvf4 - cfcvts32al mvfx3, mvf8 - cfcvts32le mvfx7, mvf2 - cfcvts32ne mvfx12, mvf6 - cfcvtd32lt mvfx0, mvd7 - cfcvtd32pl mvfx14, mvd3 - cfcvtd32gt mvfx10, mvd1 - cfcvtd32hi mvfx15, mvd13 - cfcvtd32vs mvfx11, mvd4 - cftruncs32cs mvfx9, mvf0 - cftruncs32pl mvfx15, mvf10 - cftruncs32ls mvfx4, mvf14 - cftruncs32cc mvfx8, mvf13 - cftruncs32vc mvfx2, mvf1 - cftruncd32gt mvfx6, mvd11 - cftruncd32eq mvfx7, mvd5 - cftruncd32al mvfx3, mvd12 - cftruncd32ge mvfx1, mvd8 - cftruncd32 mvfx13, mvd6 -shift: - cfrshl32lt mvfx4, mvfx2, r3 - cfrshl32pl mvfx15, mvfx10, r4 - cfrshl32al mvfx3, mvfx8, r2 - cfrshl32cs mvfx1, mvfx12, r9 - cfrshl32eq mvfx7, mvfx5, r7 - cfrshl64gt mvdx10, mvdx1, r8 - cfrshl64le mvdx6, mvdx11, r6 - cfrshl64ls mvdx0, mvdx5, sp - cfrshl64ls mvdx4, mvdx14, r11 - cfrshl64le mvdx7, mvdx2, r12 - cfsh32vs mvfx11, mvfx0, #-1 - cfsh32al mvfx3, mvfx12, #24 - cfsh32hi mvfx15, mvfx13, #33 - cfsh32mi mvfx2, mvfx9, #0 - cfsh32 mvfx10, mvfx9, #32 - cfsh64cc mvdx8, mvdx13, #-31 - cfsh64ne mvdx12, mvdx6, #1 - cfsh64vc mvdx5, mvdx14, #-32 - cfsh64ge mvdx1, mvdx8, #-27 - cfsh64vs mvdx11, mvdx4, #-5 -comp: - cfcmpseq r10, mvf15, mvf10 - cfcmpsmi r1, mvf3, mvf8 - cfcmpsvc pc, mvf1, mvf12 - cfcmpslt r0, mvf7, mvf5 - cfcmpscc r14, mvf10, mvf1 - cfcmpd r5, mvd6, mvd11 - cfcmpdcs r3, mvd0, mvd5 - cfcmpdge r4, mvd4, mvd14 - cfcmpdhi r2, mvd7, mvd2 - cfcmpdgt r9, mvd11, mvd0 - cfcmp32pl r7, mvfx3, mvfx12 - cfcmp32ne r8, mvfx15, mvfx13 - cfcmp32lt r6, mvfx2, mvfx9 - cfcmp32pl sp, mvfx10, mvfx9 - cfcmp32al r11, mvfx8, mvfx13 - cfcmp64cs r12, mvdx12, mvdx6 - cfcmp64eq sl, mvdx5, mvdx14 - cfcmp64gt r1, mvdx1, mvdx8 - cfcmp64le r15, mvdx11, mvdx4 - cfcmp64ls r0, mvdx5, mvdx15 -fp_arith: - cfabssls mvf4, mvf14 - cfabsscc mvf8, mvf13 - cfabssvc mvf2, mvf1 - cfabssgt mvf6, mvf11 - cfabsseq mvf7, mvf5 - cfabsdal mvd3, mvd12 - cfabsdge mvd1, mvd8 - cfabsd mvd13, mvd6 - cfabsdlt mvd4, mvd2 - cfabsdls mvd0, mvd5 - cfnegs mvf10, mvf9 - cfnegsmi mvf14, mvf3 - cfnegshi mvf13, mvf7 - cfnegscs mvf1, mvf12 - cfnegsvs mvf11, mvf0 - cfnegdvc mvd5, mvd14 - cfnegdcc mvd12, mvd10 - cfnegdne mvd8, mvd15 - cfnegdle mvd6, mvd11 - cfnegdmi mvd2, mvd9 - cfaddseq mvf5, mvf15, mvf10 - cfaddsmi mvf14, mvf3, mvf8 - cfaddsvc mvf2, mvf1, mvf12 - cfaddslt mvf0, mvf7, mvf5 - cfaddscc mvf12, mvf10, mvf1 - cfaddd mvd13, mvd6, mvd11 - cfadddcs mvd9, mvd0, mvd5 - cfadddge mvd9, mvd4, mvd14 - cfadddhi mvd13, mvd7, mvd2 - cfadddgt mvd6, mvd11, mvd0 - cfsubspl mvf14, mvf3, mvf12 - cfsubsne mvf8, mvf15, mvf13 - cfsubslt mvf4, mvf2, mvf9 - cfsubspl mvf15, mvf10, mvf9 - cfsubsal mvf3, mvf8, mvf13 - cfsubdcs mvd1, mvd12, mvd6 - cfsubdeq mvd7, mvd5, mvd14 - cfsubdgt mvd10, mvd1, mvd8 - cfsubdle mvd6, mvd11, mvd4 - cfsubdls mvd0, mvd5, mvd15 - cfmulsls mvf4, mvf14, mvf3 - cfmulsle mvf7, mvf2, mvf1 - cfmulsvs mvf11, mvf0, mvf7 - cfmulsal mvf3, mvf12, mvf10 - cfmulshi mvf15, mvf13, mvf6 - cfmuldmi mvd2, mvd9, mvd0 - cfmuld mvd10, mvd9, mvd4 - cfmuldcc mvd8, mvd13, mvd7 - cfmuldne mvd12, mvd6, mvd11 - cfmuldvc mvd5, mvd14, mvd3 -int_arith: - cfabs32ge mvfx1, mvfx8 - cfabs32 mvfx13, mvfx6 - cfabs32lt mvfx4, mvfx2 - cfabs32ls mvfx0, mvfx5 - cfabs32 mvfx10, mvfx9 - cfabs64mi mvdx14, mvdx3 - cfabs64hi mvdx13, mvdx7 - cfabs64cs mvdx1, mvdx12 - cfabs64vs mvdx11, mvdx0 - cfabs64vc mvdx5, mvdx14 - cfneg32cc mvfx12, mvfx10 - cfneg32ne mvfx8, mvfx15 - cfneg32le mvfx6, mvfx11 - cfneg32mi mvfx2, mvfx9 - cfneg32eq mvfx5, mvfx15 - cfneg64ge mvdx9, mvdx4 - cfneg64al mvdx3, mvdx8 - cfneg64le mvdx7, mvdx2 - cfneg64ne mvdx12, mvdx6 - cfneg64lt mvdx0, mvdx7 - cfadd32pl mvfx14, mvfx3, mvfx12 - cfadd32ne mvfx8, mvfx15, mvfx13 - cfadd32lt mvfx4, mvfx2, mvfx9 - cfadd32pl mvfx15, mvfx10, mvfx9 - cfadd32al mvfx3, mvfx8, mvfx13 - cfadd64cs mvdx1, mvdx12, mvdx6 - cfadd64eq mvdx7, mvdx5, mvdx14 - cfadd64gt mvdx10, mvdx1, mvdx8 - cfadd64le mvdx6, mvdx11, mvdx4 - cfadd64ls mvdx0, mvdx5, mvdx15 - cfsub32ls mvfx4, mvfx14, mvfx3 - cfsub32le mvfx7, mvfx2, mvfx1 - cfsub32vs mvfx11, mvfx0, mvfx7 - cfsub32al mvfx3, mvfx12, mvfx10 - cfsub32hi mvfx15, mvfx13, mvfx6 - cfsub64mi mvdx2, mvdx9, mvdx0 - cfsub64 mvdx10, mvdx9, mvdx4 - cfsub64cc mvdx8, mvdx13, mvdx7 - cfsub64ne mvdx12, mvdx6, mvdx11 - cfsub64vc mvdx5, mvdx14, mvdx3 - cfmul32ge mvfx1, mvfx8, mvfx15 - cfmul32vs mvfx11, mvfx4, mvfx2 - cfmul32eq mvfx5, mvfx15, mvfx10 - cfmul32mi mvfx14, mvfx3, mvfx8 - cfmul32vc mvfx2, mvfx1, mvfx12 - cfmul64lt mvdx0, mvdx7, mvdx5 - cfmul64cc mvdx12, mvdx10, mvdx1 - cfmul64 mvdx13, mvdx6, mvdx11 - cfmul64cs mvdx9, mvdx0, mvdx5 - cfmul64ge mvdx9, mvdx4, mvdx14 - cfmac32hi mvfx13, mvfx7, mvfx2 - cfmac32gt mvfx6, mvfx11, mvfx0 - cfmac32pl mvfx14, mvfx3, mvfx12 - cfmac32ne mvfx8, mvfx15, mvfx13 - cfmac32lt mvfx4, mvfx2, mvfx9 - cfmsc32pl mvfx15, mvfx10, mvfx9 - cfmsc32al mvfx3, mvfx8, mvfx13 - cfmsc32cs mvfx1, mvfx12, mvfx6 - cfmsc32eq mvfx7, mvfx5, mvfx14 - cfmsc32gt mvfx10, mvfx1, mvfx8 -acc_arith: - cfmadd32le mvax0, mvfx11, mvfx4, mvfx2 - cfmadd32ls mvax0, mvfx5, mvfx15, mvfx10 - cfmadd32ls mvax0, mvfx14, mvfx3, mvfx8 - cfmadd32le mvax2, mvfx2, mvfx1, mvfx12 - cfmadd32vs mvax1, mvfx0, mvfx7, mvfx5 - cfmsub32al mvax2, mvfx12, mvfx10, mvfx1 - cfmsub32hi mvax3, mvfx13, mvfx6, mvfx11 - cfmsub32mi mvax0, mvfx9, mvfx0, mvfx5 - cfmsub32 mvax2, mvfx9, mvfx4, mvfx14 - cfmsub32cc mvax1, mvfx13, mvfx7, mvfx2 - cfmadda32ne mvax2, mvax0, mvfx11, mvfx0 - cfmadda32vc mvax3, mvax2, mvfx3, mvfx12 - cfmadda32ge mvax3, mvax1, mvfx15, mvfx13 - cfmadda32vs mvax3, mvax2, mvfx2, mvfx9 - cfmadda32eq mvax1, mvax3, mvfx10, mvfx9 - cfmsuba32mi mvax1, mvax3, mvfx8, mvfx13 - cfmsuba32vc mvax0, mvax3, mvfx12, mvfx6 - cfmsuba32lt mvax0, mvax1, mvfx5, mvfx14 - cfmsuba32cc mvax0, mvax1, mvfx1, mvfx8 - cfmsuba32 mvax2, mvax0, mvfx11, mvfx4 diff --git a/binutils-2.17/gas/testsuite/gas/arm/nomapping.d b/binutils-2.17/gas/testsuite/gas/arm/nomapping.d deleted file mode 100644 index 76f28334..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/nomapping.d +++ /dev/null @@ -1,8 +0,0 @@ -#nm: -n -#name: ARM Mapping Symbols Ignored -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* - -# Check ARM ELF Mapping Symbols are ignored properly -0+0 t sym1 -0+c t sym2 diff --git a/binutils-2.17/gas/testsuite/gas/arm/nomapping.s b/binutils-2.17/gas/testsuite/gas/arm/nomapping.s deleted file mode 100644 index efe92ae5..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/nomapping.s +++ /dev/null @@ -1,19 +0,0 @@ - .text - .arm -sym1: - nop - .thumb - nop - nop -$a.foo: -$t.foo: -$d.foo: -@ Obsolete mapping symbols generated by armcc. -$m: -$m.foo: -$f: -$f.foo: -$p: -$p.foo: - .word 0 -sym2: diff --git a/binutils-2.17/gas/testsuite/gas/arm/offset.d b/binutils-2.17/gas/testsuite/gas/arm/offset.d deleted file mode 100644 index f6957c07..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/offset.d +++ /dev/null @@ -1,11 +0,0 @@ -# name: OFFSET_IMM regression -# as: -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+0 <[^>]+> e51f0004 ? ldr r0, \[pc, #-4\] ; 0+4 <[^>]+> -0+4 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+8 <[^>]+> e1a00000 ? nop \(mov r0,r0\) -0+c <[^>]+> e1a00000 ? nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/offset.s b/binutils-2.17/gas/testsuite/gas/arm/offset.s deleted file mode 100644 index 53d567de..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/offset.s +++ /dev/null @@ -1,14 +0,0 @@ - @ test that an OFFSET_IMM reloc against a global symbol is - @ still resolved by the assembler, as long as the symbol is in - @ the same section as the reference - .text - .globl l - .globl foo -l: - ldr r0, foo -foo: - nop - - @ pad section for a.out's benefit - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/pic.d b/binutils-2.17/gas/testsuite/gas/arm/pic.d deleted file mode 100644 index f5232a36..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/pic.d +++ /dev/null @@ -1,24 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: PIC -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -# VxWorks needs a special variant of this file. -#skip: *-*-vxworks* - -# Test generation of PIC - -.*: +file format .*arm.* - -Disassembly of section .text: -00+0 <[^>]*> eb...... bl 00+. <[^>]*> - 0: R_ARM_(PC24|CALL) foo.* -00+4 <[^>]*> eb...... bl 0[0123456789abcdef]+ <[^>]*> - 4: R_ARM_PLT32 foo - \.\.\. - 8: R_ARM_ABS32 sym - c: R_ARM_GOT32 sym - 10: R_ARM_GOTOFF32 sym - 14: R_ARM_GOTPC _GLOBAL_OFFSET_TABLE_ - 18: R_ARM_TARGET1 foo2 - 1c: R_ARM_SBREL32 foo3 - 20: R_ARM_TARGET2 foo4 diff --git a/binutils-2.17/gas/testsuite/gas/arm/pic.s b/binutils-2.17/gas/testsuite/gas/arm/pic.s deleted file mode 100644 index 3c3c3293..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/pic.s +++ /dev/null @@ -1,14 +0,0 @@ -@ Test file for ARM ELF PIC - -.text -.align 0 - bl foo - bl foo(PLT) - .word sym - .word sym(GOT) - .word sym(GOTOFF) -1: - .word _GLOBAL_OFFSET_TABLE_ - 1b - .word foo2(TARGET1) - .word foo3(SBREL) - .word foo4(TARGET2) diff --git a/binutils-2.17/gas/testsuite/gas/arm/pic_vxworks.d b/binutils-2.17/gas/testsuite/gas/arm/pic_vxworks.d deleted file mode 100644 index f7db8aa4..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/pic_vxworks.d +++ /dev/null @@ -1,22 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: PIC -#source: pic.s -#not-skip: *-*-vxworks* - -# Test generation of PIC - -.*: +file format .*arm.* - -Disassembly of section .text: -00+0 <[^>]*> eb000000 bl .* - 0: R_ARM_PC24 foo\+0xfffffff8 -00+4 <[^>]*> eb000000 bl .* - 4: R_ARM_PLT32 foo\+0xfffffff8 - \.\.\. - 8: R_ARM_ABS32 sym - c: R_ARM_GOT32 sym - 10: R_ARM_GOTOFF32 sym - 14: R_ARM_GOTPC _GLOBAL_OFFSET_TABLE_ - 18: R_ARM_TARGET1 foo2 - 1c: R_ARM_SBREL32 foo3 - 20: R_ARM_TARGET2 foo4 diff --git a/binutils-2.17/gas/testsuite/gas/arm/r15-bad.d b/binutils-2.17/gas/testsuite/gas/arm/r15-bad.d deleted file mode 100644 index ec7c3055..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/r15-bad.d +++ /dev/null @@ -1,2 +0,0 @@ -#name: Invalid use of r15 errors -#error-output: r15-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/r15-bad.l b/binutils-2.17/gas/testsuite/gas/arm/r15-bad.l deleted file mode 100644 index a172e9e9..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/r15-bad.l +++ /dev/null @@ -1,64 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:5: Error: r15 not allowed here -- `mul r15,r1,r2' -[^:]*:6: Error: r15 not allowed here -- `mul r1,r15,r2' -[^:]*:7: Error: r15 not allowed here -- `mla r15,r2,r3,r4' -[^:]*:8: Error: r15 not allowed here -- `mla r1,r15,r3,r4' -[^:]*:9: Error: r15 not allowed here -- `mla r1,r2,r15,r4' -[^:]*:10: Error: r15 not allowed here -- `mla r1,r2,r3,r15' -[^:]*:11: Error: r15 not allowed here -- `smlabb r15,r2,r3,r4' -[^:]*:12: Error: r15 not allowed here -- `smlabb r1,r15,r3,r4' -[^:]*:13: Error: r15 not allowed here -- `smlabb r1,r2,r15,r4' -[^:]*:14: Error: r15 not allowed here -- `smlabb r1,r2,r3,r15' -[^:]*:15: Error: r15 not allowed here -- `smlalbb r15,r2,r3,r4' -[^:]*:16: Error: r15 not allowed here -- `smlalbb r1,r15,r3,r4' -[^:]*:17: Error: r15 not allowed here -- `smlalbb r1,r2,r15,r4' -[^:]*:18: Error: r15 not allowed here -- `smlalbb r1,r2,r3,r15' -[^:]*:19: Error: r15 not allowed here -- `smulbb r15,r2,r3' -[^:]*:20: Error: r15 not allowed here -- `smulbb r1,r15,r3' -[^:]*:21: Error: r15 not allowed here -- `smulbb r1,r2,r15' -[^:]*:22: Error: r15 not allowed here -- `qadd r15,r2,r3' -[^:]*:23: Error: r15 not allowed here -- `qadd r1,r15,r3' -[^:]*:24: Error: r15 not allowed here -- `qadd r1,r2,r15' -[^:]*:25: Error: r15 not allowed here -- `qadd16 r15,r2,r3' -[^:]*:26: Error: r15 not allowed here -- `qadd16 r1,r15,r3' -[^:]*:27: Error: r15 not allowed here -- `qadd16 r1,r2,r15' -[^:]*:28: Error: r15 not allowed here -- `clz r15,r2' -[^:]*:29: Error: r15 not allowed here -- `clz r1,r15' -[^:]*:30: Error: r15 not allowed here -- `umaal r15,r2,r3,r4' -[^:]*:31: Error: r15 not allowed here -- `umaal r1,r15,r3,r4' -[^:]*:32: Error: r15 not allowed here -- `umaal r1,r2,r15,r4' -[^:]*:33: Error: r15 not allowed here -- `umaal r1,r2,r3,r15' -[^:]*:34: Error: r15 not allowed here -- `strex r15,r2,[[]r3[]]' -[^:]*:35: Error: r15 not allowed here -- `strex r1,r15,[[]r3[]]' -[^:]*:36: Error: instruction does not accept this addressing mode -- `strex r1,r2,[[]r15[]]' -[^:]*:37: Error: r15 not allowed here -- `ssat r15,#1,r2' -[^:]*:38: Error: r15 not allowed here -- `ssat r1,#1,r15' -[^:]*:39: Error: r15 not allowed here -- `ssat16 r15,#1,r2' -[^:]*:40: Error: r15 not allowed here -- `ssat16 r1,#1,r15' -[^:]*:41: Error: r15 not allowed here -- `smmul r15,r2,r3' -[^:]*:42: Error: r15 not allowed here -- `smmul r1,r15,r3' -[^:]*:43: Error: r15 not allowed here -- `smmul r1,r2,r15' -[^:]*:44: Error: r15 not allowed here -- `smlald r15,r2,r3,r4' -[^:]*:45: Error: r15 not allowed here -- `smlald r1,r15,r3,r4' -[^:]*:46: Error: r15 not allowed here -- `smlald r1,r2,r15,r4' -[^:]*:47: Error: r15 not allowed here -- `smlald r1,r2,r3,r15' -[^:]*:48: Error: r15 not allowed here -- `smlad r15,r2,r3,r4' -[^:]*:49: Error: r15 not allowed here -- `smlad r1,r15,r3,r4' -[^:]*:50: Error: r15 not allowed here -- `smlad r1,r2,r15,r4' -[^:]*:51: Error: r15 not allowed here -- `smlad r1,r2,r3,r15' -[^:]*:52: Error: r15 not allowed here -- `sxth r15,r2' -[^:]*:53: Error: r15 not allowed here -- `sxth r1,r15' -[^:]*:54: Error: r15 not allowed here -- `sxtah r15,r2,r3' -[^:]*:55: Error: r15 not allowed here -- `sxtah r1,r15,r3' -[^:]*:56: Error: r15 not allowed here -- `sxtah r1,r2,r15' -[^:]*:57: Error: r15 not allowed here -- `rfeda r15' -[^:]*:58: Error: r15 not allowed here -- `rev r15,r2' -[^:]*:59: Error: r15 not allowed here -- `rev r1,r15' -[^:]*:60: Error: r15 not allowed here -- `pkhtb r15,r2,r3' -[^:]*:61: Error: r15 not allowed here -- `pkhtb r1,r15,r3' -[^:]*:62: Error: r15 not allowed here -- `pkhtb r1,r2,r15' -[^:]*:63: Error: r15 not allowed here -- `ldrex r15,[[]r2[]]' -[^:]*:64: Error: instruction does not accept this addressing mode -- `ldrex r1,[[]r15[]]' -[^:]*:65: Error: r15 not allowed here -- `swp r15,r2,[[]r3[]]' -[^:]*:66: Error: r15 not allowed here -- `swp r1,r15,[[]r3[]]' -[^:]*:67: Error: r15 not allowed here -- `swp r1,r2,[[]r15[]]' diff --git a/binutils-2.17/gas/testsuite/gas/arm/r15-bad.s b/binutils-2.17/gas/testsuite/gas/arm/r15-bad.s deleted file mode 100644 index 59a6ea83..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/r15-bad.s +++ /dev/null @@ -1,68 +0,0 @@ -.text -.align 0 - -label: - mul r15, r1, r2 - mul r1, r15, r2 - mla r15, r2, r3, r4 - mla r1, r15, r3, r4 - mla r1, r2, r15, r4 - mla r1, r2, r3, r15 - smlabb r15, r2, r3, r4 - smlabb r1, r15, r3, r4 - smlabb r1, r2, r15, r4 - smlabb r1, r2, r3, r15 - smlalbb r15, r2, r3, r4 - smlalbb r1, r15, r3, r4 - smlalbb r1, r2, r15, r4 - smlalbb r1, r2, r3, r15 - smulbb r15, r2, r3 - smulbb r1, r15, r3 - smulbb r1, r2, r15 - qadd r15, r2, r3 - qadd r1, r15, r3 - qadd r1, r2, r15 - qadd16 r15, r2, r3 - qadd16 r1, r15, r3 - qadd16 r1, r2, r15 - clz r15, r2 - clz r1, r15 - umaal r15, r2, r3, r4 - umaal r1, r15, r3, r4 - umaal r1, r2, r15, r4 - umaal r1, r2, r3, r15 - strex r15, r2, [r3] - strex r1, r15, [r3] - strex r1, r2, [r15] - ssat r15, #1, r2 - ssat r1, #1, r15 - ssat16 r15, #1, r2 - ssat16 r1, #1, r15 - smmul r15, r2, r3 - smmul r1, r15, r3 - smmul r1, r2, r15 - smlald r15, r2, r3, r4 - smlald r1, r15, r3, r4 - smlald r1, r2, r15, r4 - smlald r1, r2, r3, r15 - smlad r15, r2, r3, r4 - smlad r1, r15, r3, r4 - smlad r1, r2, r15, r4 - smlad r1, r2, r3, r15 - sxth r15, r2 - sxth r1, r15 - sxtah r15, r2, r3 - sxtah r1, r15, r3 - sxtah r1, r2, r15 - rfeda r15 - rev r15, r2 - rev r1, r15 - pkhtb r15, r2, r3 - pkhtb r1, r15, r3 - pkhtb r1, r2, r15 - ldrex r15, [r2] - ldrex r1, [r15] - swp r15, r2, [r3] - swp r1, r15, [r3] - swp r1, r2, [r15] - diff --git a/binutils-2.17/gas/testsuite/gas/arm/reg-alias.d b/binutils-2.17/gas/testsuite/gas/arm/reg-alias.d deleted file mode 100644 index d9b4be29..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/reg-alias.d +++ /dev/null @@ -1,10 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: Case Sensitive Register Aliases - -.*: +file format .*arm.* - -Disassembly of section .text: -0+0 <.*> ee060f10 mcr 15, 0, r0, cr6, cr0, \{0\} -0+4 <.*> e1a00000 nop \(mov r0,r0\) -0+8 <.*> e1a00000 nop \(mov r0,r0\) -0+c <.*> e1a00000 nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/reg-alias.s b/binutils-2.17/gas/testsuite/gas/arm/reg-alias.s deleted file mode 100644 index 5086b8b4..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/reg-alias.s +++ /dev/null @@ -1,14 +0,0 @@ - @ Test case-sensitive register aliases - .text - .global fred -fred: - -MMUPurgeTLBReg .req c6 -MMUCP .req p15 - -MCR MMUCP, 0, a1, MMUPurgeTLBReg, c0, 0 - @ The NOPs are here for ports like arm-aout which will pad - @ the .text section to a 16 byte boundary. - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/req.d b/binutils-2.17/gas/testsuite/gas/arm/req.d deleted file mode 100644 index 41707fff..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/req.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: .req errors -#as: -mcpu=arm7m -#error-output: req.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/req.l b/binutils-2.17/gas/testsuite/gas/arm/req.l deleted file mode 100644 index 165d1d81..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/req.l +++ /dev/null @@ -1,3 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:18: Error: ARM register expected -- `add foo,foo,foo' -[^:]*:21: Warning: ignoring attempt to undefine built-in register 'r0' diff --git a/binutils-2.17/gas/testsuite/gas/arm/req.s b/binutils-2.17/gas/testsuite/gas/arm/req.s deleted file mode 100644 index 341f66d1..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/req.s +++ /dev/null @@ -1,25 +0,0 @@ - .text - .global test_dot_req_and_unreq -test_dot_req_and_unreq: - - # Check that builtin register alias 'r0' works. - add r0, r0, r0 - - # Create an alias for r0. - foo .req r0 - - # Check that it works. - add foo, foo, foo - - # Now remove the alias. - .unreq foo - - # And make sure that it no longer works. - add foo, foo, foo - - # Attempt to remove the builtin alias for r0. - .unreq r0 - - # That is ignored, so this should still work. - add r0, r0, r0 - diff --git a/binutils-2.17/gas/testsuite/gas/arm/svc.d b/binutils-2.17/gas/testsuite/gas/arm/svc.d deleted file mode 100644 index fdeb9302..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/svc.d +++ /dev/null @@ -1,15 +0,0 @@ -# name: SWI/SVC instructions -# objdump: -dr --prefix-addresses --show-raw-insn -# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* - -.*: +file format .*arm.* - -Disassembly of section \.text: -0+000 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+004 <[^>]+> ef876543 (swi|svc) 0x00876543 -0+008 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+00c <[^>]+> ef876543 (swi|svc) 0x00876543 -0+010 <[^>]+> df5a (swi|svc) 90 -0+012 <[^>]+> dfa5 (swi|svc) 165 -0+014 <[^>]+> df5a (swi|svc) 90 -0+016 <[^>]+> dfa5 (swi|svc) 165 diff --git a/binutils-2.17/gas/testsuite/gas/arm/svc.s b/binutils-2.17/gas/testsuite/gas/arm/svc.s deleted file mode 100644 index 734bd75b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/svc.s +++ /dev/null @@ -1,15 +0,0 @@ - .text - .arch armv4t - .syntax unified -foo: - swi 0x123456 - swi 0x876543 - svc 0x123456 - svc 0x876543 - - .thumb -bar: - swi 0x5a - swi 0xa5 - svc 0x5a - svc 0xa5 diff --git a/binutils-2.17/gas/testsuite/gas/arm/t16-bad.d b/binutils-2.17/gas/testsuite/gas/arm/t16-bad.d deleted file mode 100644 index b5603add..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/t16-bad.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: Valid ARM, invalid Thumb -#as: -march=armv6k -#error-output: t16-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/t16-bad.l b/binutils-2.17/gas/testsuite/gas/arm/t16-bad.l deleted file mode 100644 index 7c322609..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/t16-bad.l +++ /dev/null @@ -1,186 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:36: Error: lo register required -- `tst r8,r0' -[^:]*:36: Error: lo register required -- `tst r0,r8' -[^:]*:36: Error: unshifted register required -- `tst r0,#12' -[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl#2' -[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl r3' -[^:]*:37: Error: lo register required -- `cmn r8,r0' -[^:]*:37: Error: lo register required -- `cmn r0,r8' -[^:]*:37: Error: unshifted register required -- `cmn r0,#12' -[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl#2' -[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl r3' -[^:]*:38: Error: lo register required -- `mvn r8,r0' -[^:]*:38: Error: lo register required -- `mvn r0,r8' -[^:]*:38: Error: unshifted register required -- `mvn r0,#12' -[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl#2' -[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl r3' -[^:]*:39: Error: lo register required -- `neg r8,r0' -[^:]*:39: Error: lo register required -- `neg r0,r8' -[^:]*:40: Error: lo register required -- `rev r8,r0' -[^:]*:40: Error: lo register required -- `rev r0,r8' -[^:]*:41: Error: lo register required -- `rev16 r8,r0' -[^:]*:41: Error: lo register required -- `rev16 r0,r8' -[^:]*:42: Error: lo register required -- `revsh r8,r0' -[^:]*:42: Error: lo register required -- `revsh r0,r8' -[^:]*:43: Error: lo register required -- `sxtb r8,r0' -[^:]*:43: Error: lo register required -- `sxtb r0,r8' -[^:]*:43: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8' -[^:]*:44: Error: lo register required -- `sxth r8,r0' -[^:]*:44: Error: lo register required -- `sxth r0,r8' -[^:]*:44: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8' -[^:]*:45: Error: lo register required -- `uxtb r8,r0' -[^:]*:45: Error: lo register required -- `uxtb r0,r8' -[^:]*:45: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8' -[^:]*:46: Error: lo register required -- `uxth r8,r0' -[^:]*:46: Error: lo register required -- `uxth r0,r8' -[^:]*:46: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8' -[^:]*:48: Error: dest must overlap one source register -- `adc r1,r2,r3' -[^:]*:48: Error: lo register required -- `adc r8,r0' -[^:]*:48: Error: lo register required -- `adc r0,r8' -[^:]*:48: Error: unshifted register required -- `adc r0,#12' -[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl#2' -[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl r3' -[^:]*:49: Error: dest must overlap one source register -- `and r1,r2,r3' -[^:]*:49: Error: lo register required -- `and r8,r0' -[^:]*:49: Error: lo register required -- `and r0,r8' -[^:]*:49: Error: unshifted register required -- `and r0,#12' -[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl#2' -[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl r3' -[^:]*:50: Error: dest and source1 must be the same register -- `bic r1,r2,r3' -[^:]*:50: Error: lo register required -- `bic r8,r0' -[^:]*:50: Error: lo register required -- `bic r0,r8' -[^:]*:50: Error: unshifted register required -- `bic r0,#12' -[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl#2' -[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl r3' -[^:]*:51: Error: dest must overlap one source register -- `eor r1,r2,r3' -[^:]*:51: Error: lo register required -- `eor r8,r0' -[^:]*:51: Error: lo register required -- `eor r0,r8' -[^:]*:51: Error: unshifted register required -- `eor r0,#12' -[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl#2' -[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl r3' -[^:]*:52: Error: dest must overlap one source register -- `orr r1,r2,r3' -[^:]*:52: Error: lo register required -- `orr r8,r0' -[^:]*:52: Error: lo register required -- `orr r0,r8' -[^:]*:52: Error: unshifted register required -- `orr r0,#12' -[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl#2' -[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl r3' -[^:]*:53: Error: dest and source1 must be the same register -- `sbc r1,r2,r3' -[^:]*:53: Error: lo register required -- `sbc r8,r0' -[^:]*:53: Error: lo register required -- `sbc r0,r8' -[^:]*:53: Error: unshifted register required -- `sbc r0,#12' -[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl#2' -[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl r3' -[^:]*:54: Error: dest must overlap one source register -- `mul r1,r2,r3' -[^:]*:54: Error: lo register required -- `mul r8,r0' -[^:]*:54: Error: lo register required -- `mul r0,r8' -[^:]*:62: Error: lo register required -- `asr r8,r0,#12' -[^:]*:62: Error: lo register required -- `asr r0,r8,#12' -[^:]*:62: Error: lo register required -- `asr r8,r0' -[^:]*:62: Error: lo register required -- `asr r0,r8' -[^:]*:63: Error: lo register required -- `lsl r8,r0,#12' -[^:]*:63: Error: lo register required -- `lsl r0,r8,#12' -[^:]*:63: Error: lo register required -- `lsl r8,r0' -[^:]*:63: Error: lo register required -- `lsl r0,r8' -[^:]*:64: Error: lo register required -- `lsr r8,r0,#12' -[^:]*:64: Error: lo register required -- `lsr r0,r8,#12' -[^:]*:64: Error: lo register required -- `lsr r8,r0' -[^:]*:64: Error: lo register required -- `lsr r0,r8' -[^:]*:65: Error: lo register required -- `ror r8,r0,#12' -[^:]*:65: Error: lo register required -- `ror r0,r8,#12' -[^:]*:65: Error: lo register required -- `ror r8,r0' -[^:]*:65: Error: lo register required -- `ror r0,r8' -[^:]*:66: Error: ror #imm not supported -- `ror r0,r1,#12' -[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl#2' -[^:]*:70: Error: unshifted register required -- `add r0,r1,lsl r3' -[^:]*:71: Error: lo register required -- `add r8,r0,#1' -[^:]*:72: Error: lo register required -- `add r0,r8,#1' -[^:]*:73: Error: lo register required -- `add r8,#10' -[^:]*:74: Error: dest must overlap one source register -- `add r8,r1,r2' -[^:]*:75: Error: dest must overlap one source register -- `add r1,r8,r2' -[^:]*:76: Error: dest must overlap one source register -- `add r1,r2,r8' -[^:]*:77: Error: lo register required -- `add r8,pc,#4' -[^:]*:78: Error: lo register required -- `add r8,sp,#4' -[^:]*:80: Error: lo register required -- `sub r8,r0' -[^:]*:80: Error: lo register required -- `sub r0,r8' -[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl#2' -[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl r3' -[^:]*:81: Error: lo register required -- `sub r8,r0,#1' -[^:]*:82: Error: lo register required -- `sub r0,r8,#1' -[^:]*:83: Error: lo register required -- `sub r8,#10' -[^:]*:84: Error: lo register required -- `sub r8,r1,r2' -[^:]*:85: Error: lo register required -- `sub r1,r8,r2' -[^:]*:86: Error: lo register required -- `sub r1,r2,r8' -[^:]*:90: Error: only lo regs allowed with immediate -- `cmp r8,#255' -[^:]*:94: Error: only lo regs allowed with immediate -- `mov r8,#255' -[^:]*:106: Error: lo register required -- `ldr r8,\[r0\]' -[^:]*:106: Error: lo register required -- `ldr r0,\[r8\]' -[^:]*:106: Error: lo register required -- `ldr r0,\[r0,r8\]' -[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!' -[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4' -[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]' -[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2' -[^:]*:107: Error: lo register required -- `ldrb r8,\[r0\]' -[^:]*:107: Error: lo register required -- `ldrb r0,\[r8\]' -[^:]*:107: Error: lo register required -- `ldrb r0,\[r0,r8\]' -[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!' -[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4' -[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]' -[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2' -[^:]*:108: Error: lo register required -- `ldrh r8,\[r0\]' -[^:]*:108: Error: lo register required -- `ldrh r0,\[r8\]' -[^:]*:108: Error: lo register required -- `ldrh r0,\[r0,r8\]' -[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!' -[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4' -[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,-r2\]' -[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],r2' -[^:]*:109: Error: lo register required -- `ldrsb r8,\[r0\]' -[^:]*:109: Error: lo register required -- `ldrsb r0,\[r8\]' -[^:]*:109: Error: lo register required -- `ldrsb r0,\[r0,r8\]' -[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!' -[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4' -[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]' -[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2' -[^:]*:110: Error: lo register required -- `ldrsh r8,\[r0\]' -[^:]*:110: Error: lo register required -- `ldrsh r0,\[r8\]' -[^:]*:110: Error: lo register required -- `ldrsh r0,\[r0,r8\]' -[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,#4\]!' -[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],#4' -[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,-r2\]' -[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],r2' -[^:]*:111: Error: lo register required -- `str r8,\[r0\]' -[^:]*:111: Error: lo register required -- `str r0,\[r8\]' -[^:]*:111: Error: lo register required -- `str r0,\[r0,r8\]' -[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,#4\]!' -[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],#4' -[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,-r2\]' -[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],r2' -[^:]*:112: Error: lo register required -- `strb r8,\[r0\]' -[^:]*:112: Error: lo register required -- `strb r0,\[r8\]' -[^:]*:112: Error: lo register required -- `strb r0,\[r0,r8\]' -[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,#4\]!' -[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],#4' -[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,-r2\]' -[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],r2' -[^:]*:113: Error: lo register required -- `strh r8,\[r0\]' -[^:]*:113: Error: lo register required -- `strh r0,\[r8\]' -[^:]*:113: Error: lo register required -- `strh r0,\[r0,r8\]' -[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,#4\]!' -[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],#4' -[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,-r2\]' -[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2' -[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl#1\]' -[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl#1\]' -[^:]*:119: Error: lo register required -- `ldmia r8!,{r1,r2}' -[^:]*:120: Error: lo register required -- `ldmia r7!,{r8}' -[^:]*:121: Warning: this instruction will write back the base register -[^:]*:122: Warning: this instruction will not write back the base register -[^:]*:124: Error: lo register required -- `stmia r8!,{r1,r2}' -[^:]*:125: Error: lo register required -- `stmia r7!,{r8}' -[^:]*:126: Warning: this instruction will write back the base register -[^:]*:127: Warning: value stored for r7 is UNPREDICTABLE -[^:]*:129: Error: invalid register list to push/pop instruction -- `push {r8,r9}' -[^:]*:130: Error: invalid register list to push/pop instruction -- `pop {r8,r9}' -[^:]*:133: Error: immediate value out of range -- `bkpt #257' -[^:]*:134: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie ai,#5' -[^:]*:135: Error: Thumb does not support the 2-argument form of this instruction -- `cpsid ai,#5' -[^:]*:138: Error: Thumb does not support conditional execution diff --git a/binutils-2.17/gas/testsuite/gas/arm/t16-bad.s b/binutils-2.17/gas/testsuite/gas/arm/t16-bad.s deleted file mode 100644 index a80a81ff..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/t16-bad.s +++ /dev/null @@ -1,138 +0,0 @@ - @ Things you can't do with 16-bit Thumb instructions, but you can - @ do with the equivalent ARM instruction. Does not include errors - @ caught by fixup processing (e.g. out-of-range immediates). - - .text - .code 16 - .thumb_func -l: - @ Arithmetic instruction templates - .macro ar2 opc - \opc r8,r0 - \opc r0,r8 - .endm - .macro ar2sh opc - ar2 \opc - \opc r0,#12 - \opc r0,r1,lsl #2 - \opc r0,r1,lsl r3 - .endm - .macro ar2r opc - ar2 \opc - \opc r0,r1,ror #8 - .endm - .macro ar3 opc - \opc r1,r2,r3 - \opc r8,r0 - \opc r0,r8 - .endm - .macro ar3sh opc - ar3 \opc - \opc r0,#12 - \opc r0,r1,lsl #2 - \opc r0,r1,lsl r3 - .endm - - ar2sh tst - ar2sh cmn - ar2sh mvn - ar2 neg - ar2 rev - ar2 rev16 - ar2 revsh - ar2r sxtb - ar2r sxth - ar2r uxtb - ar2r uxth - - ar3sh adc - ar3sh and - ar3sh bic - ar3sh eor - ar3sh orr - ar3sh sbc - ar3 mul - - @ Shift instruction template - .macro shift opc - \opc r8,r0,#12 @ form 1 - \opc r0,r8,#12 - ar2 \opc @ form 2 - .endm - shift asr - shift lsl - shift lsr - shift ror - ror r0,r1,#12 - - @ add/sub/mov/cmp are idiosyncratic - add r0,r1,lsl #2 - add r0,r1,lsl r3 - add r8,r0,#1 @ form 1 - add r0,r8,#1 - add r8,#10 @ form 2 - add r8,r1,r2 @ form 3 - add r1,r8,r2 - add r1,r2,r8 - add r8,pc,#4 @ form 5 - add r8,sp,#4 @ form 6 - - ar3sh sub - sub r8,r0,#1 @ form 1 - sub r0,r8,#1 - sub r8,#10 @ form 2 - sub r8,r1,r2 @ form 3 - sub r1,r8,r2 - sub r1,r2,r8 - - cmp r0,r1,lsl #2 - cmp r0,r1,lsl r3 - cmp r8,#255 - - mov r0,r1,lsl #2 - mov r0,r1,lsl r3 - mov r8,#255 - - @ Load/store template - .macro ldst opc - \opc r8,[r0] - \opc r0,[r8] - \opc r0,[r0,r8] - \opc r0,[r1,#4]! - \opc r0,[r1],#4 - \opc r0,[r1,-r2] - \opc r0,[r1],r2 - .endm - ldst ldr - ldst ldrb - ldst ldrh - ldst ldrsb - ldst ldrsh - ldst str - ldst strb - ldst strh - - ldr r0,[r1,r2,lsl #1] - str r0,[r1,r2,lsl #1] - - @ Load/store multiple - ldmia r8!,{r1,r2} - ldmia r7!,{r8} - ldmia r7,{r1,r2} - ldmia r7!,{r1,r7} - - stmia r8!,{r1,r2} - stmia r7!,{r8} - stmia r7,{r1,r2} - stmia r7!,{r1,r7} - - push {r8,r9} - pop {r8,r9} - - @ Miscellaneous - bkpt #257 - cpsie ai,#5 - cpsid ai,#5 - - @ Conditional suffixes - addeq r0,r1,r2 diff --git a/binutils-2.17/gas/testsuite/gas/arm/tcompat.d b/binutils-2.17/gas/testsuite/gas/arm/tcompat.d deleted file mode 100644 index 47e9d89d..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tcompat.d +++ /dev/null @@ -1,50 +0,0 @@ -#name: ARM Thumb-compat pseudos -#objdump: -dr --prefix-addresses --show-raw-insn -#as: - -# Test the ARM pseudo instructions that exist for Thumb source compatibility - -.*: +file format .*arm.* - -Disassembly of section .text: - -0+00 <[^>]*> 91a00000 ? movls r0, r0 -0+04 <[^>]*> e1a09000 ? mov r9, r0 -0+08 <[^>]*> e1a00009 ? mov r0, r9 -0+0c <[^>]*> e1a0c00e ? mov ip, lr -0+10 <[^>]*> 91b09019 ? movlss r9, r9, lsl r0 -0+14 <[^>]*> 91a00910 ? movls r0, r0, lsl r9 -0+18 <[^>]*> e1b00880 ? movs r0, r0, lsl #17 -0+1c <[^>]*> e1a00889 ? mov r0, r9, lsl #17 -0+20 <[^>]*> 91b09039 ? movlss r9, r9, lsr r0 -0+24 <[^>]*> 91a00930 ? movls r0, r0, lsr r9 -0+28 <[^>]*> e1b008a0 ? movs r0, r0, lsr #17 -0+2c <[^>]*> e1a008a9 ? mov r0, r9, lsr #17 -0+30 <[^>]*> 91b09059 ? movlss r9, r9, asr r0 -0+34 <[^>]*> 91a00950 ? movls r0, r0, asr r9 -0+38 <[^>]*> e1b008c0 ? movs r0, r0, asr #17 -0+3c <[^>]*> e1a008c9 ? mov r0, r9, asr #17 -0+40 <[^>]*> 91b09079 ? movlss r9, r9, ror r0 -0+44 <[^>]*> 91a00970 ? movls r0, r0, ror r9 -0+48 <[^>]*> e1b008e0 ? movs r0, r0, ror #17 -0+4c <[^>]*> e1a008e9 ? mov r0, r9, ror #17 -0+50 <[^>]*> e2690000 ? rsb r0, r9, #0 ; 0x0 -0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0 ; 0x0 -0+58 <[^>]*> 92600000 ? rsbls r0, r0, #0 ; 0x0 -0+5c <[^>]*> 92799000 ? rsblss r9, r9, #0 ; 0x0 -0+60 <[^>]*> e92d000e ? stmdb sp!, {r1, r2, r3} -0+64 <[^>]*> 992d8154 ? stmlsdb sp!, {r2, r4, r6, r8, pc} -0+68 <[^>]*> e8bd000e ? ldmia sp!, {r1, r2, r3} -0+6c <[^>]*> 98bd8154 ? ldmlsia sp!, {r2, r4, r6, r8, pc} -0+70 <[^>]*> e0000001 ? and r0, r0, r1 -0+74 <[^>]*> e0200001 ? eor r0, r0, r1 -0+78 <[^>]*> e0400001 ? sub r0, r0, r1 -0+7c <[^>]*> e0600001 ? rsb r0, r0, r1 -0+80 <[^>]*> e0800001 ? add r0, r0, r1 -0+84 <[^>]*> e0a00001 ? adc r0, r0, r1 -0+88 <[^>]*> e0c00001 ? sbc r0, r0, r1 -0+8c <[^>]*> e0e00001 ? rsc r0, r0, r1 -0+90 <[^>]*> e1800001 ? orr r0, r0, r1 -0+94 <[^>]*> e1c00001 ? bic r0, r0, r1 -0+98 <[^>]*> e0000091 ? mul r0, r1, r0 -0+9c <[^>]*> e1a00000 ? nop \(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/tcompat.s b/binutils-2.17/gas/testsuite/gas/arm/tcompat.s deleted file mode 100644 index c0042e8f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tcompat.s +++ /dev/null @@ -1,45 +0,0 @@ - @ ARM instructions defined for source compatibility with Thumb. - .macro shift op opls ops oplss - \oplss r9,r0 - \opls r0,r0,r9 - \ops r0,#17 - \op r0,r9,#17 - .endm - .text - .global l -l: - cpyls r0,r0 - cpy r9,r0 - cpy r0,r9 - cpy ip,lr - - shift lsl lslls lsls lsllss - shift lsr lsrls lsrs lsrlss - shift asr asrls asrs asrlss - shift ror rorls rors rorlss - - neg r0,r9 - negs r9,r0 - negls r0,r0 - neglss r9,r9 - - push {r1,r2,r3} - pushls {r2,r4,r6,r8,pc} - pop {r1,r2,r3} - popls {r2,r4,r6,r8,pc} - - @ Two-argument forms of ARM arithmetic instructions. - and r0,r1 - eor r0,r1 - sub r0,r1 - rsb r0,r1 - - add r0,r1 - adc r0,r1 - sbc r0,r1 - rsc r0,r1 - - orr r0,r1 - bic r0,r1 - mul r0,r1 - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/tcompat2.d b/binutils-2.17/gas/testsuite/gas/arm/tcompat2.d deleted file mode 100644 index ba39db1f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tcompat2.d +++ /dev/null @@ -1,26 +0,0 @@ -#name: Thumb ARM-compat pseudos -#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb -#as: - -# Test the Thumb pseudo instructions that exist for ARM source compatibility - -.*: +file format .*arm.* - -Disassembly of section .text: - -0+00 <[^>]*> 4148 * adcs r0, r1 -0+02 <[^>]*> 4148 * adcs r0, r1 -0+04 <[^>]*> 4008 * ands r0, r1 -0+06 <[^>]*> 4008 * ands r0, r1 -0+08 <[^>]*> 4048 * eors r0, r1 -0+0a <[^>]*> 4048 * eors r0, r1 -0+0c <[^>]*> 4348 * muls r0, r1 -0+0e <[^>]*> 4348 * muls r0, r1 -0+10 <[^>]*> 4308 * orrs r0, r1 -0+12 <[^>]*> 4308 * orrs r0, r1 -0+14 <[^>]*> 4388 * bics r0, r1 -0+16 <[^>]*> 4188 * sbcs r0, r1 -0+18 <[^>]*> 46c0 * nop \(mov r8, r8\) -0+1a <[^>]*> 46c0 * nop \(mov r8, r8\) -0+1c <[^>]*> 46c0 * nop \(mov r8, r8\) -0+1e <[^>]*> 46c0 * nop \(mov r8, r8\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/tcompat2.s b/binutils-2.17/gas/testsuite/gas/arm/tcompat2.s deleted file mode 100644 index b034ce2f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tcompat2.s +++ /dev/null @@ -1,32 +0,0 @@ - @ Three-argument forms of Thumb arithmetic instructions. - @ Commutative instructions allow either the second or third - @ operand to equal the first. - - .text - .global m - .thumb_func -m: - adc r0,r0,r1 - adc r0,r1,r0 - - and r0,r0,r1 - and r0,r1,r0 - - eor r0,r0,r1 - eor r0,r1,r0 - - mul r0,r0,r1 - mul r0,r1,r0 - - orr r0,r0,r1 - orr r0,r1,r0 - - bic r0,r0,r1 - - sbc r0,r0,r1 - - @ section padding for a.out's sake - nop - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb.d b/binutils-2.17/gas/testsuite/gas/arm/thumb.d deleted file mode 100644 index d3f815a2..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb.d +++ /dev/null @@ -1,164 +0,0 @@ -# name: Thumb instructions -# as: -mcpu=arm7t -# objdump: -dr --prefix-addresses --show-raw-insn -# The arm-aout and arm-pe ports do not support Thumb branch relocations. -# not-target: *-*-*aout* *-*-pe - -.*: +file format .*arm.* - -Disassembly of section \.text: -0+000 <[^>]+> 00ca lsls r2, r1, #3 -0+002 <[^>]+> 0fe3 lsrs r3, r4, #31 -0+004 <[^>]+> 1147 asrs r7, r0, #5 -0+006 <[^>]+> 0011 lsls r1, r2, #0 -0+008 <[^>]+> 0023 lsls r3, r4, #0 -0+00a <[^>]+> 002c lsls r4, r5, #0 -0+00c <[^>]+> 083e lsrs r6, r7, #32 -0+00e <[^>]+> 1008 asrs r0, r1, #32 -0+010 <[^>]+> 18d1 adds r1, r2, r3 -0+012 <[^>]+> 1ca2 adds r2, r4, #2 -0+014 <[^>]+> 1beb subs r3, r5, r7 -0+016 <[^>]+> 1fe2 subs r2, r4, #7 -0+018 <[^>]+> 24ff movs r4, #255 -0+01a <[^>]+> 2bfa cmp r3, #250 -0+01c <[^>]+> 367b adds r6, #123 -0+01e <[^>]+> 3d80 subs r5, #128 -0+020 <[^>]+> 402b ands r3, r5 -0+022 <[^>]+> 4074 eors r4, r6 -0+024 <[^>]+> 4081 lsls r1, r0 -0+026 <[^>]+> 40da lsrs r2, r3 -0+028 <[^>]+> 4134 asrs r4, r6 -0+02a <[^>]+> 417d adcs r5, r7 -0+02c <[^>]+> 41a0 sbcs r0, r4 -0+02e <[^>]+> 41e1 rors r1, r4 -0+030 <[^>]+> 422a tst r2, r5 -0+032 <[^>]+> 4249 negs r1, r1 -0+034 <[^>]+> 429a cmp r2, r3 -0+036 <[^>]+> 42e1 cmn r1, r4 -0+038 <[^>]+> 4318 orrs r0, r3 -0+03a <[^>]+> 436c muls r4, r5 -0+03c <[^>]+> 43bd bics r5, r7 -0+03e <[^>]+> 43ed mvns r5, r5 -0+040 <[^>]+> 4469 add r1, sp -0+042 <[^>]+> 4494 add ip, r2 -0+044 <[^>]+> 44c9 add r9, r9 -0+046 <[^>]+> 4571 cmp r1, lr -0+048 <[^>]+> 4580 cmp r8, r0 -0+04a <[^>]+> 45f4 cmp ip, lr -0+04c <[^>]+> 4648 mov r0, r9 -0+04e <[^>]+> 46a1 mov r9, r4 -0+050 <[^>]+> 46c0 nop \(mov r8, r8\) -0+052 <[^>]+> 4738 bx r7 -0+054 <[^>]+> 4740 bx r8 -0+056 <[^>]+> 0000 lsls r0, r0, #0 -0+058 <[^>]+> 4778 bx pc -0+05a <[^>]+> 4b20 ldr r3, \[pc, #128\] \(0+0dc <[^>]+>\) -0+05c <[^>]+> 4c02 ldr r4, \[pc, #8\] \(0+068 <[^>]+>\) -0+05e <[^>]+> 5088 str r0, \[r1, r2\] -0+060 <[^>]+> 5511 strb r1, \[r2, r4\] -0+062 <[^>]+> 59f5 ldr r5, \[r6, r7\] -0+064 <[^>]+> 5d62 ldrb r2, \[r4, r5\] - \.\.\. -0+068 <[^>]+> 52d1 strh r1, \[r2, r3\] -0+06a <[^>]+> 5a23 ldrh r3, \[r4, r0\] -0+06c <[^>]+> 57f1 ldrsb r1, \[r6, r7\] -0+06e <[^>]+> 5f42 ldrsh r2, \[r0, r5\] -0+070 <[^>]+> 67db str r3, \[r3, #124\] -0+072 <[^>]+> 6fe1 ldr r1, \[r4, #124\] -0+074 <[^>]+> 682d ldr r5, \[r5, #0\] -0+076 <[^>]+> 77e9 strb r1, \[r5, #31\] -0+078 <[^>]+> 7161 strb r1, \[r4, #5\] -0+07a <[^>]+> 7032 strb r2, \[r6, #0\] -0+07c <[^>]+> 87ec strh r4, \[r5, #62\] -0+07e <[^>]+> 8885 ldrh r5, \[r0, #4\] -0+080 <[^>]+> 8813 ldrh r3, \[r2, #0\] -0+082 <[^>]+> 93ff str r3, \[sp, #1020\] -0+084 <[^>]+> 990b ldr r1, \[sp, #44\] -0+086 <[^>]+> 9a00 ldr r2, \[sp, #0\] -0+088 <[^>]+> a7ff add r7, pc, #1020 \(adr r7,0+488 <[^>]+>\) -0+08a <[^>]+> ac80 add r4, sp, #512 -0+08c <[^>]+> b043 add sp, #268 -0+08e <[^>]+> b09a sub sp, #104 -0+090 <[^>]+> b0c3 sub sp, #268 -0+092 <[^>]+> b01b add sp, #108 -0+094 <[^>]+> b417 push {r0, r1, r2, r4} -0+096 <[^>]+> b5f9 push {r0, r3, r4, r5, r6, r7, lr} -0+098 <[^>]+> bc98 pop {r3, r4, r7} -0+09a <[^>]+> bdff pop {r0, r1, r2, r3, r4, r5, r6, r7, pc} -0+09c <[^>]+> c3f3 stmia r3!, {r0, r1, r4, r5, r6, r7} -0+09e <[^>]+> c8fe ldmia r0!, {r1, r2, r3, r4, r5, r6, r7} -0+0a0 <[^>]+> d0e2 beq.n 0+068 <[^>]+> -0+0a2 <[^>]+> d1e1 bne.n 0+068 <[^>]+> -0+0a4 <[^>]+> d2e0 bcs.n 0+068 <[^>]+> -0+0a6 <[^>]+> d3df bcc.n 0+068 <[^>]+> -0+0a8 <[^>]+> d4de bmi.n 0+068 <[^>]+> -0+0aa <[^>]+> d5dd bpl.n 0+068 <[^>]+> -0+0ac <[^>]+> d6dc bvs.n 0+068 <[^>]+> -0+0ae <[^>]+> d7db bvc.n 0+068 <[^>]+> -0+0b0 <[^>]+> d8da bhi.n 0+068 <[^>]+> -0+0b2 <[^>]+> d9d9 bls.n 0+068 <[^>]+> -0+0b4 <[^>]+> dad8 bge.n 0+068 <[^>]+> -0+0b6 <[^>]+> dcd7 bgt.n 0+068 <[^>]+> -0+0b8 <[^>]+> dbd6 blt.n 0+068 <[^>]+> -0+0ba <[^>]+> dcd5 bgt.n 0+068 <[^>]+> -0+0bc <[^>]+> ddd4 ble.n 0+068 <[^>]+> -0+0be <[^>]+> d8d3 bhi.n 0+068 <[^>]+> -0+0c0 <[^>]+> d3d2 bcc.n 0+068 <[^>]+> -0+0c2 <[^>]+> d3d1 bcc.n 0+068 <[^>]+> -0+0c4 <[^>]+> e7d0 b.n 0+068 <[^>]+> -0+0c6 <[^>]+> 00ac lsls r4, r5, #2 -0+0c8 <[^>]+> 1c9a adds r2, r3, #2 -0+0ca <[^>]+> b07f add sp, #508 -0+0cc <[^>]+> b0ff sub sp, #508 -0+0ce <[^>]+> a8ff add r0, sp, #1020 -0+0d0 <[^>]+> a0ff add r0, pc, #1020 \(adr r0,0+4d0 <[^>]+>\) -0+0d2 <[^>]+> b01a add sp, #104 -0+0d4 <[^>]+> b09a sub sp, #104 -0+0d6 <[^>]+> a81a add r0, sp, #104 -0+0d8 <[^>]+> a01a add r0, pc, #104 \(adr r0,0+144 <[^>]+>\) -0+0da <[^>]+> 3168 adds r1, #104 -0+0dc <[^>]+> 2668 movs r6, #104 -0+0de <[^>]+> 2f68 cmp r7, #104 -0+0e0 <[^>]+> 46c0 nop \(mov r8, r8\) -0+0e2 <[^>]+> 46c0 nop \(mov r8, r8\) -0+0e4 <[^>]+> eafffffe b 0+0e4 <[^>]+> -0+0e8 <[^>]+> ea000011 b 0+134 <[^>]+> -0+0ec <[^>]+> ebfffffc bl 0+0e4 <[^>]+> -0+0f0 <[^>]+> eb00000f bl 0+134 <[^>]+> -0+0f4 <[^>]+> e12fff10 bx r0 -0+0f8 <[^>]+> ef123456 (swi|svc) 0x00123456 -0+0fc <[^>]+> a004 add r0, pc, #16 \(adr r0,0+110 <[^>]+>\) -0+0fe <[^>]+> e77f b.n 0+000 <[^>]+> -0+100 <[^>]+> e018 b.n 0+134 <[^>]+> -0+102 <[^>]+> f7ff ff7d bl 0+000 <[^>]+> -0+106 <[^>]+> f000 f815 bl 0+134 <[^>]+> -0+10a <[^>]+> 4700 bx r0 -0+10c <[^>]+> dfff (swi|svc) 255 - \.\.\. -0+110 <[^>]+> d010 beq.n 0+134 <[^>]+> -0+112 <[^>]+> d10f bne.n 0+134 <[^>]+> -0+114 <[^>]+> d20e bcs.n 0+134 <[^>]+> -0+116 <[^>]+> d30d bcc.n 0+134 <[^>]+> -0+118 <[^>]+> d40c bmi.n 0+134 <[^>]+> -0+11a <[^>]+> d50b bpl.n 0+134 <[^>]+> -0+11c <[^>]+> d60a bvs.n 0+134 <[^>]+> -0+11e <[^>]+> d709 bvc.n 0+134 <[^>]+> -0+120 <[^>]+> d808 bhi.n 0+134 <[^>]+> -0+122 <[^>]+> d907 bls.n 0+134 <[^>]+> -0+124 <[^>]+> da06 bge.n 0+134 <[^>]+> -0+126 <[^>]+> dc05 bgt.n 0+134 <[^>]+> -0+128 <[^>]+> db04 blt.n 0+134 <[^>]+> -0+12a <[^>]+> dc03 bgt.n 0+134 <[^>]+> -0+12c <[^>]+> dd02 ble.n 0+134 <[^>]+> -0+12e <[^>]+> d801 bhi.n 0+134 <[^>]+> -0+130 <[^>]+> d300 bcc.n 0+134 <[^>]+> -0+132 <[^>]+> d3ff bcc.n 0+134 <[^>]+> -0+134 <[^>]+> f000 fc00 bl 0+938 <[^>]+> - \.\.\. -0+938 <[^>]+> f7ff fbfc bl 0+134 <[^>]+> -0+93c <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\) -0+93e <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+944 <[^>]+>\) -0+940 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\) -0+942 <[^>]+> 4801 ldr r0, \[pc, #4\] \(0+948 <[^>]+>\) -0+944 <[^>]+> 46c0 nop \(mov r8, r8\) -0+946 <[^>]+> 46c0 nop \(mov r8, r8\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb.s b/binutils-2.17/gas/testsuite/gas/arm/thumb.s deleted file mode 100644 index d1e43394..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb.s +++ /dev/null @@ -1,202 +0,0 @@ - .text - .code 16 -.foo: - lsl r2, r1, #3 - lsr r3, r4, #31 -wibble/data: - asr r7, r0, #5 - - lsl r1, r2, #0 - lsr r3, r4, #0 - asr r4, r5, #0 - - lsr r6, r7, #32 - asr r0, r1, #32 - - add r1, r2, r3 - add r2, r4, #2 - sub r3, r5, r7 - sub r2, r4, #7 - - mov r4, #255 - cmp r3, #250 - add r6, #123 - sub r5, #128 - - and r3, r5 - eor r4, r6 - lsl r1, r0 - lsr r2, r3 - asr r4, r6 - adc r5, r7 - sbc r0, r4 - ror r1, r4 - tst r2, r5 - neg r1, r1 - cmp r2, r3 - cmn r1, r4 - orr r0, r3 - mul r4, r5 - bic r5, r7 - mvn r5, r5 - - add r1, r13 - add r12, r2 - add r9, r9 - cmp r1, r14 - cmp r8, r0 - cmp r12, r14 - mov r0, r9 - mov r9, r4 - mov r8, r8 - bx r7 - bx r8 - .align 0 - bx pc - - ldr r3, [pc, #128] - ldr r4, bar - - str r0, [r1, r2] - strb r1, [r2, r4] - ldr r5, [r6, r7] - ldrb r2, [r4, r5] - - .align 0 -bar: - strh r1, [r2, r3] - ldrh r3, [r4, r0] - ldsb r1, [r6, r7] - ldsh r2, [r0, r5] - - str r3, [r3, #124] - ldr r1, [r4, #124] - ldr r5, [r5] - strb r1, [r5, #31] - strb r1, [r4, #5] - strb r2, [r6] - - strh r4, [r5, #62] - ldrh r5, [r0, #4] - ldrh r3, [r2] - - str r3, [r13, #1020] - ldr r1, [r13, #44] - ldr r2, [r13] - - add r7, r15, #1020 - add r4, r13, #512 - - add r13, #268 - add r13, #-104 - sub r13, #268 - sub r13, #-108 - - push {r0, r1, r2, r4} - push {r0, r3-r7, lr} - pop {r3, r4, r7} - pop {r0-r7, r15} - - stmia r3!, {r0, r1, r4-r7} - ldmia r0!, {r1-r7} - - beq bar - bne bar - bcs bar - bcc bar - bmi bar - bpl bar - bvs bar - bvc bar - bhi bar - bls bar - bge bar - bgt bar - blt bar - bgt bar - ble bar - bhi bar - blo bar - bul bar - bal bar - -close: - lsl r4, r5, #near - close -near: - add r2, r3, #near - close - - add sp, sp, #127 << 2 - sub sp, sp, #127 << 2 - add r0, sp, #255 << 2 - add r0, pc, #255 << 2 - - add sp, sp, #bar - .foo - sub sp, sp, #bar - .foo - add r0, sp, #bar - .foo - add r0, pc, #bar - .foo - - add r1, #bar - .foo - mov r6, #bar - .foo - cmp r7, #bar - .foo - - nop - nop - - .arm -.localbar: - b .localbar - b .back - bl .localbar - bl .back - - bx r0 - swi 0x123456 - - .thumb - @ The following will be disassembled incorrectly if we do not - @ have a Thumb symbol defined before the first Thumb instruction: -morethumb: - adr r0, forwardonly - - b .foo - b .back - bl .foo - bl .back - - bx r0 - - swi 0xff - .align 0 -forwardonly: - beq .back - bne .back - bcs .back - bcc .back - bmi .back - bpl .back - bvs .back - bvc .back - bhi .back - bls .back - bge .back - bgt .back - blt .back - bgt .back - ble .back - bhi .back - blo .back - bul .back - -.back: - bl .local - .space (1 << 11) @ leave space to force long offsets -.local: - bl .back - - ldr r0, .target - ldr r0, .target - ldr r0, [pc, #4] - ldr r0, [pc, #4] -.target: - nop @ pad for a.out - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_bcond.d b/binutils-2.17/gas/testsuite/gas/arm/thumb2_bcond.d deleted file mode 100644 index 8ab75320..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_bcond.d +++ /dev/null @@ -1,26 +0,0 @@ -# as: -# objdump: -dr --prefix-addresses --show-raw-insn -# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]+> bf18 it ne -0+002 <[^>]+> e7fd b(|ne).n 0+0 <[^>]+> -0+004 <[^>]+> bf38 it cc -0+006 <[^>]+> f7ff bffb b(|cc).w 0+0 <[^>]+> -0+00a <[^>]+> bf28 it cs -0+00c <[^>]+> f7ff fff8 bl(|cs) 0+0 <[^>]+> -0+010 <[^>]+> bfb8 it lt -0+012 <[^>]+> 47a8 blx(|lr) r5 -0+014 <[^>]+> bf08 it eq -0+016 <[^>]+> 4740 bx(|eq) r8 -0+018 <[^>]+> bfc8 it gt -0+01a <[^>]+> e8d4 f001 tbb(|gt) \[r4, r1\] -0+01e <[^>]+> bfb8 it lt -0+020 <[^>]+> df00 svc(|lt) 0 -0+022 <[^>]+> bfdc itt le -0+024 <[^>]+> be00 bkpt 0x0000 -0+026 <[^>]+> bf00 nop -0+028 <[^>]+> bf00 nop -0+02a <[^>]+> bf00 nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_bcond.s b/binutils-2.17/gas/testsuite/gas/arm/thumb2_bcond.s deleted file mode 100644 index 4a066f24..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_bcond.s +++ /dev/null @@ -1,25 +0,0 @@ - .text - .arch armv7 - .thumb - .syntax unified - .thumb_func -thumb2_bcond: - it ne - bne thumb2_bcond - it cc - bcc.w thumb2_bcond - it cs - blcs thumb2_bcond - it lt - blxlt r5 - it eq - bxeq r8 - it gt - tbbgt [r4, r1] - it lt - svclt 0 - itt le - bkpt #0 - nople - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_invert.d b/binutils-2.17/gas/testsuite/gas/arm/thumb2_invert.d deleted file mode 100644 index 3880e5bb..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_invert.d +++ /dev/null @@ -1,16 +0,0 @@ -# as: -march=armv6kt2 -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]+> f517 0f80 cmn.w r7, #4194304 ; 0x400000 -0+004 <[^>]+> f5b8 0f80 cmp.w r8, #4194304 ; 0x400000 -0+008 <[^>]+> f5a4 0980 sub.w r9, r4, #4194304 ; 0x400000 -0+00c <[^>]+> f506 0380 add.w r3, r6, #4194304 ; 0x400000 -0+010 <[^>]+> f160 4500 sbc.w r5, r0, #2147483648 ; 0x80000000 -0+014 <[^>]+> f147 4400 adc.w r4, r7, #2147483648 ; 0x80000000 -0+018 <[^>]+> f022 4600 bic.w r6, r2, #2147483648 ; 0x80000000 -0+01c <[^>]+> f002 4800 and.w r8, r2, #2147483648 ; 0x80000000 -0+020 <[^>]+> f06f 4300 mvn.w r3, #2147483648 ; 0x80000000 -0+024 <[^>]+> f04f 4100 mov.w r1, #2147483648 ; 0x80000000 diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_invert.s b/binutils-2.17/gas/testsuite/gas/arm/thumb2_invert.s deleted file mode 100644 index 38ebcdda..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_invert.s +++ /dev/null @@ -1,14 +0,0 @@ - .text - .thumb - .syntax unified -thumb2_invert: - cmp r7, #0xffc00000 - cmn r8, #0xffc00000 - add r9, r4, #0xffc00000 - sub r3, r6, #0xffc00000 - adc r5, r0, #0x7fffffff - sbc r4, r7, #0x7fffffff - and r6, r2, #0x7fffffff - bic r8, r2, #0x7fffffff - mov r3, 0x7fffffff - mvn r1, 0x7fffffff diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it.d b/binutils-2.17/gas/testsuite/gas/arm/thumb2_it.d deleted file mode 100644 index 30a390bb..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it.d +++ /dev/null @@ -1,62 +0,0 @@ -# name: Mixed 16 and 32-bit Thumb conditional instructions -# as: -march=armv6kt2 -# objdump: -dr --prefix-addresses --show-raw-insn -# Many of these patterns use "(eq|s)". These should be changed to just "eq" -# once the disassembler is fixed. Likewise for "(eq)?" - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]+> bf05 ittet eq -0+002 <[^>]+> 1880 add(eq|s) r0, r0, r2 -0+004 <[^>]+> 4440 add(eq)? r0, r8 -0+006 <[^>]+> 1888 add(ne|s) r0, r1, r2 -0+008 <[^>]+> eb11 0002 adds(eq)?.w r0, r1, r2 -0+00c <[^>]+> 4410 add r0, r2 -0+00e <[^>]+> 4440 add r0, r8 -0+010 <[^>]+> 1880 adds r0, r0, r2 -0+012 <[^>]+> eb10 0008 adds.w r0, r0, r8 -0+016 <[^>]+> 1888 adds r0, r1, r2 -0+018 <[^>]+> bf0a itet eq -0+01a <[^>]+> 4310 orr(eq|s) r0, r2 -0+01c <[^>]+> ea40 0008 orr(ne)?.w r0, r0, r8 -0+020 <[^>]+> ea50 0002 orrs(eq)?.w r0, r0, r2 -0+024 <[^>]+> ea40 0002 orr.w r0, r0, r2 -0+028 <[^>]+> ea40 0008 orr.w r0, r0, r8 -0+02c <[^>]+> 4310 orrs r0, r2 -0+02e <[^>]+> bf01 itttt eq -0+030 <[^>]+> 4090 lsl(eq|s) r0, r2 -0+032 <[^>]+> fa00 f008 lsl(eq)?.w r0, r0, r8 -0+036 <[^>]+> fa01 f002 lsl(eq)?.w r0, r1, r2 -0+03a <[^>]+> fa10 f002 lsls(eq)?.w r0, r0, r2 -0+03e <[^>]+> bf02 ittt eq -0+040 <[^>]+> 0048 lsl(eq|s) r0, r1, #1 -0+042 <[^>]+> ea4f 0048 mov(eq)?.w r0, r8, lsl #1 -0+046 <[^>]+> ea5f 0040 movs(eq)?.w r0, r0, lsl #1 -0+04a <[^>]+> fa00 f002 lsl.w r0, r0, r2 -0+04e <[^>]+> 4090 lsls r0, r2 -0+050 <[^>]+> ea4f 0041 mov.w r0, r1, lsl #1 -0+054 <[^>]+> 0048 lsls r0, r1, #1 -0+056 <[^>]+> bf01 itttt eq -0+058 <[^>]+> 4288 cmp(eq)? r0, r1 -0+05a <[^>]+> 4540 cmp(eq)? r0, r8 -0+05c <[^>]+> 4608 mov(eq)? r0, r1 -0+05e <[^>]+> ea5f 0001 movs(eq)?.w r0, r1 -0+062 <[^>]+> bf08 it eq -0+064 <[^>]+> 4640 mov(eq)? r0, r8 -0+066 <[^>]+> 4608 mov(eq)? r0, r1 -0+068 <[^>]+> 1c08 adds r0, r1, #0 -0+06a <[^>]+> ea5f 0008 movs.w r0, r8 -0+06e <[^>]+> bf01 itttt eq -0+070 <[^>]+> 43c8 mvn(eq|s) r0, r1 -0+072 <[^>]+> ea6f 0008 mvn(eq)?.w r0, r8 -0+076 <[^>]+> ea7f 0001 mvns(eq)?.w r0, r1 -0+07a <[^>]+> 42c8 cmn(eq)? r0, r1 -0+07c <[^>]+> ea6f 0001 mvn.w r0, r1 -0+080 <[^>]+> 43c8 mvns r0, r1 -0+082 <[^>]+> bf02 ittt eq -0+084 <[^>]+> 4248 neg(eq|s) r0, r1 -0+086 <[^>]+> f1c8 0000 rsb(eq)? r0, r8, #0 ; 0x0 -0+08a <[^>]+> f1d1 0000 rsbs(eq)? r0, r1, #0 ; 0x0 -0+08e <[^>]+> f1c1 0000 rsb r0, r1, #0 ; 0x0 -0+092 <[^>]+> 4248 negs r0, r1 diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it.s b/binutils-2.17/gas/testsuite/gas/arm/thumb2_it.s deleted file mode 100644 index c12abb62..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it.s +++ /dev/null @@ -1,64 +0,0 @@ - .text - .thumb - .syntax unified - .thumb_func -foo: - ittet eq - addeq r0, r0, r2 - addeq r0, r0, r8 - addne r0, r1, r2 - addseq r0, r1, r2 - add r0, r0, r2 - add r0, r0, r8 - adds r0, r0, r2 - adds r0, r0, r8 - adds r0, r1, r2 - - itet eq - orreq r0, r0, r2 - orrne r0, r0, r8 - orrseq r0, r0, r2 - orr r0, r0, r2 - orr r0, r0, r8 - orrs r0, r0, r2 - - itttt eq - lsleq r0, r0, r2 - lsleq r0, r0, r8 - lsleq r0, r1, r2 - lslseq r0, r0, r2 - ittt eq - lsleq r0, r1, #1 - lsleq r0, r8, #1 - lslseq r0, r0, #1 - lsl r0, r0, r2 - lsls r0, r0, r2 - lsl r0, r1, #1 - lsls r0, r1, #1 - - itttt eq - cmpeq r0, r1 - cmpeq r0, r8 - moveq r0, r1 - movseq r0, r1 - it eq - moveq r0, r8 - mov r0, r1 - movs r0, r1 - movs r0, r8 - - itttt eq - mvneq r0, r1 - mvneq r0, r8 - mvnseq r0, r1 - cmneq r0, r1 - mvn r0, r1 - mvns r0, r1 - - ittt eq - negeq r0, r1 - negeq r0, r8 - negseq r0, r1 - neg r0, r1 - negs r0, r1 - diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.d b/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.d deleted file mode 100644 index f905c9f5..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.d +++ /dev/null @@ -1,4 +0,0 @@ -#name: Invalid IT instructions -#as: -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -#error-output: thumb2_it_bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.l b/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.l deleted file mode 100644 index e2e96cdd..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.l +++ /dev/null @@ -1,12 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:8: Error: branch must be last instruction in IT block -- `beq foo' -[^:]*:9: Error: branch must be last instruction in IT block -- `bleq foo' -[^:]*:10: Error: branch must be last instruction in IT block -- `blxeq r0' -[^:]*:11: Error: instruction not allowed in IT block -- `cbzeq r0,foo' -[^:]*:13: Error: branch must be last instruction in IT block -- `bxeq r0' -[^:]*:14: Error: branch must be last instruction in IT block -- `tbbeq \[r0,r1\]' -[^:]*:15: Error: instruction not allowed in IT block -- `cpsieeq f' -[^:]*:17: Error: instruction not allowed in IT block -- `cpseq #0x10' -[^:]*:19: Error: instruction is always unconditional -- `bkpteq 0' -[^:]*:20: Error: instruction not allowed in IT block -- `setendeq le' -[^:]*:22: Error: instruction not allowed in IT block -- `iteq eq' diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.s b/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.s deleted file mode 100644 index 6add4fb5..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_it_bad.s +++ /dev/null @@ -1,24 +0,0 @@ - .text - .syntax unified - .arch armv7a - .thumb - .thumb_func -thumb2_it_bad: - itttt eq - beq foo - bleq foo - blxeq r0 - cbzeq r0, foo - ittt eq - bxeq r0 - tbbeq [r0, r1] - cpsieeq f - it eq - cpseq #0x10 - itt eq - bkpteq 0 - setendeq le - it eq - iteq eq - nop -foo: diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_pool.d b/binutils-2.17/gas/testsuite/gas/arm/thumb2_pool.d deleted file mode 100644 index 7bf0c605..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_pool.d +++ /dev/null @@ -1,15 +0,0 @@ -# as: -march=armv6t2 -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]+> 4e04 ldr r6, \[pc, #16\] \(00+14 <[^>]+>\) -0+002 <[^>]+> 4904 ldr r1, \[pc, #16\] \(00+14 <[^>]+>\) -0+004 <[^>]+> f8df 600c ldr\.w r6, \[pc, #12\] ; 00+14 <[^>]+> -0+008 <[^>]+> f8df 9008 ldr\.w r9, \[pc, #8\] ; 00+14 <[^>]+> -0+00c <[^>]+> bf00 nop -0+00e <[^>]+> f8df 5004 ldr\.w r5, \[pc, #4\] ; 00+14 <[^>]+> -0+012 <[^>]+> 4900 ldr r1, \[pc, #0\] \(00+14 <[^>]+>\) -0+014 <[^>]+> (5678|1234) .* -0+016 <[^>]+> (1234|5678) .* diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_pool.s b/binutils-2.17/gas/testsuite/gas/arm/thumb2_pool.s deleted file mode 100644 index 844e77ec..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_pool.s +++ /dev/null @@ -1,13 +0,0 @@ - .text - .thumb - .syntax unified - .thumb_func -thumb2_ldr: - ldr r6, =0x12345678 - ldr.n r1, =0x12345678 - ldr.w r6, =0x12345678 - ldr r9, =0x12345678 - nop - ldr.w r5, =0x12345678 - ldr r1, =0x12345678 - .pool diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_relax.d b/binutils-2.17/gas/testsuite/gas/arm/thumb2_relax.d deleted file mode 100644 index 48cd1f21..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_relax.d +++ /dev/null @@ -1,155 +0,0 @@ -# as: -march=armv6kt2 -# objdump: -dr --prefix-addresses --show-raw-insn - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]+> 7829 ldrb r1, \[r5, #0\] -0+002 <[^>]+> f895 1023 ldrb.w r1, \[r5, #35\] -0+006 <[^>]+> 7fe9 ldrb r1, \[r5, #31\] -0+008 <[^>]+> f895 101f ldrb.w r1, \[r5, #31\] -0+00c <[^>]+> f815 1c1f ldrb.w r1, \[r5, #-31\] -0+010 <[^>]+> f815 1b1f ldrb.w r1, \[r5\], #31 -0+014 <[^>]+> f815 1b1f ldrb.w r1, \[r5\], #31 -0+018 <[^>]+> f815 1f1f ldrb.w r1, \[r5, #31\]! -0+01c <[^>]+> f815 1d1f ldrb.w r1, \[r5, #-31\]! -0+020 <[^>]+> 5d29 ldrb r1, \[r5, r4\] -0+022 <[^>]+> f819 100c ldrb.w r1, \[r9, ip\] -0+026 <[^>]+> f89f 1014 ldrb.w r1, \[pc, #20\] ; 0+03c <[^>]+> -0+02a <[^>]+> f89f 1010 ldrb.w r1, \[pc, #16\] ; 0+03c <[^>]+> -0+02e <[^>]+> f89f 800c ldrb.w r8, \[pc, #12\] ; 0+03c <[^>]+> -0+032 <[^>]+> f89f 100a ldrb.w r1, \[pc, #10\] ; 0+03e <[^>]+> -0+036 <[^>]+> f81f 1038 ldrb.w r1, \[pc, #-56\] ; 0+000 <[^>]+> -0+03a <[^>]+> 0000 lsls r0, r0, #0 -0+03c <[^>]+> bf00 nop -0+03e <[^>]+> f995 1000 ldrsb.w r1, \[r5\] -0+042 <[^>]+> f995 1023 ldrsb.w r1, \[r5, #35\] -0+046 <[^>]+> f995 101f ldrsb.w r1, \[r5, #31\] -0+04a <[^>]+> f995 101f ldrsb.w r1, \[r5, #31\] -0+04e <[^>]+> f915 1c1f ldrsb.w r1, \[r5, #-31\] -0+052 <[^>]+> f915 1b1f ldrsb.w r1, \[r5\], #31 -0+056 <[^>]+> f915 1b1f ldrsb.w r1, \[r5\], #31 -0+05a <[^>]+> f915 1f1f ldrsb.w r1, \[r5, #31\]! -0+05e <[^>]+> f915 1d1f ldrsb.w r1, \[r5, #-31\]! -0+062 <[^>]+> 5729 ldrsb r1, \[r5, r4\] -0+064 <[^>]+> f919 100c ldrsb.w r1, \[r9, ip\] -0+068 <[^>]+> f99f 1010 ldrsb.w r1, \[pc, #16\] ; 0+07c <[^>]+> -0+06c <[^>]+> f99f 100c ldrsb.w r1, \[pc, #12\] ; 0+07c <[^>]+> -0+070 <[^>]+> f99f 8008 ldrsb.w r8, \[pc, #8\] ; 0+07c <[^>]+> -0+074 <[^>]+> f99f 1006 ldrsb.w r1, \[pc, #6\] ; 0+07e <[^>]+> -0+078 <[^>]+> f91f 103e ldrsb.w r1, \[pc, #-62\] ; 0+03e <[^>]+> -0+07c <[^>]+> bf00 nop -0+07e <[^>]+> 8829 ldrh r1, \[r5, #0\] -0+080 <[^>]+> f8b5 1042 ldrh.w r1, \[r5, #66\] -0+084 <[^>]+> 8fe9 ldrh r1, \[r5, #62\] -0+086 <[^>]+> f8b5 103e ldrh.w r1, \[r5, #62\] -0+08a <[^>]+> f835 1c3e ldrh.w r1, \[r5, #-62\] -0+08e <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62 -0+092 <[^>]+> f835 1b3e ldrh.w r1, \[r5\], #62 -0+096 <[^>]+> f835 1f3e ldrh.w r1, \[r5, #62\]! -0+09a <[^>]+> f835 1d3e ldrh.w r1, \[r5, #-62\]! -0+09e <[^>]+> 5b29 ldrh r1, \[r5, r4\] -0+0a0 <[^>]+> f839 100c ldrh.w r1, \[r9, ip\] -0+0a4 <[^>]+> f8bf 1010 ldrh.w r1, \[pc, #16\] ; 0+0b8 <[^>]+> -0+0a8 <[^>]+> f8bf 100c ldrh.w r1, \[pc, #12\] ; 0+0b8 <[^>]+> -0+0ac <[^>]+> f8bf 8008 ldrh.w r8, \[pc, #8\] ; 0+0b8 <[^>]+> -0+0b0 <[^>]+> f8bf 1006 ldrh.w r1, \[pc, #6\] ; 0+0ba <[^>]+> -0+0b4 <[^>]+> f83f 103a ldrh.w r1, \[pc, #-58\] ; 0+07e <[^>]+> -0+0b8 <[^>]+> bf00 nop -0+0ba <[^>]+> f9b5 1000 ldrsh.w r1, \[r5\] -0+0be <[^>]+> f9b5 1042 ldrsh.w r1, \[r5, #66\] -0+0c2 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\] -0+0c6 <[^>]+> f9b5 103e ldrsh.w r1, \[r5, #62\] -0+0ca <[^>]+> f935 1c3e ldrsh.w r1, \[r5, #-62\] -0+0ce <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62 -0+0d2 <[^>]+> f935 1b3e ldrsh.w r1, \[r5\], #62 -0+0d6 <[^>]+> f935 1f3e ldrsh.w r1, \[r5, #62\]! -0+0da <[^>]+> f935 1d3e ldrsh.w r1, \[r5, #-62\]! -0+0de <[^>]+> 5f29 ldrsh r1, \[r5, r4\] -0+0e0 <[^>]+> f939 100c ldrsh.w r1, \[r9, ip\] -0+0e4 <[^>]+> f9bf 1010 ldrsh.w r1, \[pc, #16\] ; 0+0f8 <[^>]+> -0+0e8 <[^>]+> f9bf 100c ldrsh.w r1, \[pc, #12\] ; 0+0f8 <[^>]+> -0+0ec <[^>]+> f9bf 8008 ldrsh.w r8, \[pc, #8\] ; 0+0f8 <[^>]+> -0+0f0 <[^>]+> f9bf 1006 ldrsh.w r1, \[pc, #6\] ; 0+0fa <[^>]+> -0+0f4 <[^>]+> f93f 103e ldrsh.w r1, \[pc, #-62\] ; 0+0ba <[^>]+> -0+0f8 <[^>]+> bf00 nop -0+0fa <[^>]+> 6829 ldr r1, \[r5, #0\] -0+0fc <[^>]+> f8d5 1080 ldr.w r1, \[r5, #128\] -0+100 <[^>]+> 6fe9 ldr r1, \[r5, #124\] -0+102 <[^>]+> f8d5 107c ldr.w r1, \[r5, #124\] -0+106 <[^>]+> f855 1c7c ldr.w r1, \[r5, #-124\] -0+10a <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124 -0+10e <[^>]+> f855 1b7c ldr.w r1, \[r5\], #124 -0+112 <[^>]+> f855 1f7c ldr.w r1, \[r5, #124\]! -0+116 <[^>]+> f855 1d7c ldr.w r1, \[r5, #-124\]! -0+11a <[^>]+> 5929 ldr r1, \[r5, r4\] -0+11c <[^>]+> f859 100c ldr.w r1, \[r9, ip\] -0+120 <[^>]+> 4904 ldr r1, \[pc, #16\] \(0+134 <[^>]+>\) -0+122 <[^>]+> f8df 1010 ldr.w r1, \[pc, #16\] ; 0+134 <[^>]+> -0+126 <[^>]+> f8df 800c ldr.w r8, \[pc, #12\] ; 0+134 <[^>]+> -0+12a <[^>]+> f8df 100a ldr.w r1, \[pc, #10\] ; 0+136 <[^>]+> -0+12e <[^>]+> f85f 1036 ldr.w r1, \[pc, #-54\] ; 0+0fa <[^>]+> -0+132 <[^>]+> 0000 lsls r0, r0, #0 -0+134 <[^>]+> bf00 nop -0+136 <[^>]+> 7029 strb r1, \[r5, #0\] -0+138 <[^>]+> f885 1023 strb.w r1, \[r5, #35\] -0+13c <[^>]+> 77e9 strb r1, \[r5, #31\] -0+13e <[^>]+> f885 101f strb.w r1, \[r5, #31\] -0+142 <[^>]+> f805 1c1f strb.w r1, \[r5, #-31\] -0+146 <[^>]+> f805 1b1f strb.w r1, \[r5\], #31 -0+14a <[^>]+> f805 1b1f strb.w r1, \[r5\], #31 -0+14e <[^>]+> f805 1f1f strb.w r1, \[r5, #31\]! -0+152 <[^>]+> f805 1d1f strb.w r1, \[r5, #-31\]! -0+156 <[^>]+> 5529 strb r1, \[r5, r4\] -0+158 <[^>]+> f809 100c strb.w r1, \[r9, ip\] -0+15c <[^>]+> f88f 1010 strb.w r1, \[pc, #16\] ; 0+170 <[^>]+> -0+160 <[^>]+> f88f 100c strb.w r1, \[pc, #12\] ; 0+170 <[^>]+> -0+164 <[^>]+> f88f 8008 strb.w r8, \[pc, #8\] ; 0+170 <[^>]+> -0+168 <[^>]+> f88f 1006 strb.w r1, \[pc, #6\] ; 0+172 <[^>]+> -0+16c <[^>]+> f80f 103a strb.w r1, \[pc, #-58\] ; 0+136 <[^>]+> -0+170 <[^>]+> bf00 nop -0+172 <[^>]+> 8029 strh r1, \[r5, #0\] -0+174 <[^>]+> f8a5 1042 strh.w r1, \[r5, #66\] -0+178 <[^>]+> 87e9 strh r1, \[r5, #62\] -0+17a <[^>]+> f8a5 103e strh.w r1, \[r5, #62\] -0+17e <[^>]+> f825 1c3e strh.w r1, \[r5, #-62\] -0+182 <[^>]+> f825 1b3e strh.w r1, \[r5\], #62 -0+186 <[^>]+> f825 1b3e strh.w r1, \[r5\], #62 -0+18a <[^>]+> f825 1f3e strh.w r1, \[r5, #62\]! -0+18e <[^>]+> f825 1d3e strh.w r1, \[r5, #-62\]! -0+192 <[^>]+> 5329 strh r1, \[r5, r4\] -0+194 <[^>]+> f829 100c strh.w r1, \[r9, ip\] -0+198 <[^>]+> f8af 1010 strh.w r1, \[pc, #16\] ; 0+1ac <[^>]+> -0+19c <[^>]+> f8af 100c strh.w r1, \[pc, #12\] ; 0+1ac <[^>]+> -0+1a0 <[^>]+> f8af 8008 strh.w r8, \[pc, #8\] ; 0+1ac <[^>]+> -0+1a4 <[^>]+> f8af 1006 strh.w r1, \[pc, #6\] ; 0+1ae <[^>]+> -0+1a8 <[^>]+> f82f 103a strh.w r1, \[pc, #-58\] ; 0+172 <[^>]+> -0+1ac <[^>]+> bf00 nop -0+1ae <[^>]+> 6029 str r1, \[r5, #0\] -0+1b0 <[^>]+> f8c5 1080 str.w r1, \[r5, #128\] -0+1b4 <[^>]+> 67e9 str r1, \[r5, #124\] -0+1b6 <[^>]+> f8c5 107c str.w r1, \[r5, #124\] -0+1ba <[^>]+> f845 1c7c str.w r1, \[r5, #-124\] -0+1be <[^>]+> f845 1b7c str.w r1, \[r5\], #124 -0+1c2 <[^>]+> f845 1b7c str.w r1, \[r5\], #124 -0+1c6 <[^>]+> f845 1f7c str.w r1, \[r5, #124\]! -0+1ca <[^>]+> f845 1d7c str.w r1, \[r5, #-124\]! -0+1ce <[^>]+> 5129 str r1, \[r5, r4\] -0+1d0 <[^>]+> f849 100c str.w r1, \[r9, ip\] -0+1d4 <[^>]+> f8cf 1010 str.w r1, \[pc, #16\] ; 0+1e8 <[^>]+> -0+1d8 <[^>]+> f8cf 100c str.w r1, \[pc, #12\] ; 0+1e8 <[^>]+> -0+1dc <[^>]+> f8cf 8008 str.w r8, \[pc, #8\] ; 0+1e8 <[^>]+> -0+1e0 <[^>]+> f8cf 1006 str.w r1, \[pc, #6\] ; 0+1ea <[^>]+> -0+1e4 <[^>]+> f84f 103a str.w r1, \[pc, #-58\] ; 0+1ae <[^>]+> -0+1e8 <[^>]+> bf00 nop -0+1ea <[^>]+> a104 add r1, pc, #16 \(adr r1,0+1fc <[^>]+>\) -0+1ec <[^>]+> f20f 010c addw r1, pc, #12 ; 0xc -0+1f0 <[^>]+> f20f 0808 addw r8, pc, #8 ; 0x8 -0+1f4 <[^>]+> f20f 0106 addw r1, pc, #6 ; 0x6 -0+1f8 <[^>]+> f2af 0112 subw r1, pc, #18 ; 0x12 -0+1fc <[^>]+> bf00 nop -0+1fe <[^>]+> bf00 nop -0+200 <[^>]+> f20f 0104 addw r1, pc, #4 ; 0x4 -0+204 <[^>]+> f20f 0102 addw r1, pc, #2 ; 0x2 -0+208 <[^>]+> bf00 nop -0+20a <[^>]+> bf00 nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb2_relax.s b/binutils-2.17/gas/testsuite/gas/arm/thumb2_relax.s deleted file mode 100644 index 428e6ff5..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb2_relax.s +++ /dev/null @@ -1,62 +0,0 @@ - .text - .thumb - .syntax unified -thumb2_relax: - .macro ls op w=".w" -1: - \op r1, [r5] - \op r1, [r5, #(far_\op + 4)] - \op r1, [r5, #far_\op] - \op\w r1, [r5, #far_\op] - \op r1, [r5, #-far_\op] - \op r1, [r5], #far_\op - \op r1, [r5], #far_\op - \op r1, [r5, #far_\op]! - \op r1, [r5, #-far_\op]! - \op r1, [r5, r4] - \op r1, [r9, ip] - \op r1, 1f - \op\w r1, 1f - \op r8, 1f - \op r1, 2f - \op r1, 1b - .align 2 -1: - nop -2: - .endm -.equ far_ldrb, 0x1f -.equ far_ldrsb, 0x1f -.equ far_ldrh, 0x3e -.equ far_ldrsh, 0x3e -.equ far_ldr, 0x7c -.equ far_strb, 0x1f -.equ far_strh, 0x3e -.equ far_str, 0x7c - ls ldrb - ls ldrsb - ls ldrh - ls ldrsh - ls ldr - ls strb - ls strh - ls str - .purgem ls -1: - adr r1, 1f - adr.w r1, 1f - adr r8, 1f - adr r1, 2f - adr r1, 1b -.align 2 -1: - nop -2: - nop - @ Relaxation with conflicting alignment requirements. - adr r1, 1f - adr r1, 2f -1: - nop -2: - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb32.d b/binutils-2.17/gas/testsuite/gas/arm/thumb32.d deleted file mode 100644 index 2977779a..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb32.d +++ /dev/null @@ -1,956 +0,0 @@ -# name: 32-bit Thumb instructions -# as: -march=armv6kt2 -# objdump: -dr --prefix-addresses --show-raw-insn -# The arm-aout and arm-pe ports do not support Thumb branch relocations. -# not-target: *-*-*aout* *-*-pe - -.*: +file format .*arm.* - -Disassembly of section .text: -0[0-9a-f]+ <[^>]+> f041 0000 orr\.w r0, r1, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f041 00a5 orr\.w r0, r1, #165 ; 0xa5 -0[0-9a-f]+ <[^>]+> f041 10a5 orr\.w r0, r1, #10813605 ; 0xa500a5 -0[0-9a-f]+ <[^>]+> f041 20a5 orr\.w r0, r1, #2768282880 ; 0xa500a500 -0[0-9a-f]+ <[^>]+> f041 30a5 orr\.w r0, r1, #2779096485 ; 0xa5a5a5a5 -0[0-9a-f]+ <[^>]+> f041 4000 orr\.w r0, r1, #2147483648 ; 0x80000000 -0[0-9a-f]+ <[^>]+> f041 4080 orr\.w r0, r1, #1073741824 ; 0x40000000 -0[0-9a-f]+ <[^>]+> f041 4020 orr\.w r0, r1, #2684354560 ; 0xa0000000 -0[0-9a-f]+ <[^>]+> f041 40a0 orr\.w r0, r1, #1342177280 ; 0x50000000 -0[0-9a-f]+ <[^>]+> f041 5020 orr\.w r0, r1, #671088640 ; 0x28000000 -0[0-9a-f]+ <[^>]+> f041 4014 orr\.w r0, r1, #2483027968 ; 0x94000000 -0[0-9a-f]+ <[^>]+> f041 4094 orr\.w r0, r1, #1241513984 ; 0x4a000000 -0[0-9a-f]+ <[^>]+> f041 4025 orr\.w r0, r1, #2768240640 ; 0xa5000000 -0[0-9a-f]+ <[^>]+> f041 40a5 orr\.w r0, r1, #1384120320 ; 0x52800000 -0[0-9a-f]+ <[^>]+> f041 5025 orr\.w r0, r1, #692060160 ; 0x29400000 -0[0-9a-f]+ <[^>]+> f041 50a5 orr\.w r0, r1, #346030080 ; 0x14a00000 -0[0-9a-f]+ <[^>]+> f041 6025 orr\.w r0, r1, #173015040 ; 0xa500000 -0[0-9a-f]+ <[^>]+> f041 60a5 orr\.w r0, r1, #86507520 ; 0x5280000 -0[0-9a-f]+ <[^>]+> f041 7025 orr\.w r0, r1, #43253760 ; 0x2940000 -0[0-9a-f]+ <[^>]+> f041 70a5 orr\.w r0, r1, #21626880 ; 0x14a0000 -0[0-9a-f]+ <[^>]+> f441 0025 orr\.w r0, r1, #10813440 ; 0xa50000 -0[0-9a-f]+ <[^>]+> f441 00a5 orr\.w r0, r1, #5406720 ; 0x528000 -0[0-9a-f]+ <[^>]+> f441 1025 orr\.w r0, r1, #2703360 ; 0x294000 -0[0-9a-f]+ <[^>]+> f441 10a5 orr\.w r0, r1, #1351680 ; 0x14a000 -0[0-9a-f]+ <[^>]+> f441 2025 orr\.w r0, r1, #675840 ; 0xa5000 -0[0-9a-f]+ <[^>]+> f441 20a5 orr\.w r0, r1, #337920 ; 0x52800 -0[0-9a-f]+ <[^>]+> f441 3025 orr\.w r0, r1, #168960 ; 0x29400 -0[0-9a-f]+ <[^>]+> f441 30a5 orr\.w r0, r1, #84480 ; 0x14a00 -0[0-9a-f]+ <[^>]+> f441 4025 orr\.w r0, r1, #42240 ; 0xa500 -0[0-9a-f]+ <[^>]+> f441 40a5 orr\.w r0, r1, #21120 ; 0x5280 -0[0-9a-f]+ <[^>]+> f441 5025 orr\.w r0, r1, #10560 ; 0x2940 -0[0-9a-f]+ <[^>]+> f441 50a5 orr\.w r0, r1, #5280 ; 0x14a0 -0[0-9a-f]+ <[^>]+> f441 6025 orr\.w r0, r1, #2640 ; 0xa50 -0[0-9a-f]+ <[^>]+> f441 60a5 orr\.w r0, r1, #1320 ; 0x528 -0[0-9a-f]+ <[^>]+> f441 7025 orr\.w r0, r1, #660 ; 0x294 -0[0-9a-f]+ <[^>]+> f441 70a5 orr\.w r0, r1, #330 ; 0x14a -0[0-9a-f]+ <[^>]+> 3000 adds r0, #0 -0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0 -0[0-9a-f]+ <[^>]+> 1c28 adds r0, r5, #0 -0[0-9a-f]+ <[^>]+> 1d50 adds r0, r2, #5 -0[0-9a-f]+ <[^>]+> 3081 adds r0, #129 -0[0-9a-f]+ <[^>]+> 3081 adds r0, #129 -0[0-9a-f]+ <[^>]+> 357e adds r5, #126 -0[0-9a-f]+ <[^>]+> 1800 adds r0, r0, r0 -0[0-9a-f]+ <[^>]+> 1805 adds r5, r0, r0 -0[0-9a-f]+ <[^>]+> 1828 adds r0, r5, r0 -0[0-9a-f]+ <[^>]+> 1940 adds r0, r0, r5 -0[0-9a-f]+ <[^>]+> 18d1 adds r1, r2, r3 -0[0-9a-f]+ <[^>]+> 4480 add r8, r0 -0[0-9a-f]+ <[^>]+> 4440 add r0, r8 -0[0-9a-f]+ <[^>]+> 4440 add r0, r8 -0[0-9a-f]+ <[^>]+> 4440 add r0, r8 -0[0-9a-f]+ <[^>]+> eb00 0800 add\.w r8, r0, r0 -0[0-9a-f]+ <[^>]+> 4401 add r1, r0 -0[0-9a-f]+ <[^>]+> 4408 add r0, r1 -0[0-9a-f]+ <[^>]+> a000 add r0, pc, #0 \(adr r0,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a500 add r5, pc, #0 \(adr r5,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a081 add r0, pc, #516 \(adr r0,[0-9a-f]+ <[^>]+>\) -0[0-9a-f]+ <[^>]+> a800 add r0, sp, #0 -0[0-9a-f]+ <[^>]+> ad00 add r5, sp, #0 -0[0-9a-f]+ <[^>]+> a881 add r0, sp, #516 -0[0-9a-f]+ <[^>]+> b000 add sp, #0 -0[0-9a-f]+ <[^>]+> b000 add sp, #0 -0[0-9a-f]+ <[^>]+> b041 add sp, #260 -0[0-9a-f]+ <[^>]+> f100 0000 add\.w r0, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f110 0000 adds\.w r0, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f100 0900 add\.w r9, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f109 0000 add\.w r0, r9, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f100 0081 add\.w r0, r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f513 3580 adds\.w r5, r3, #65536 ; 0x10000 -0[0-9a-f]+ <[^>]+> f10d 0001 add\.w r0, sp, #1 ; 0x1 -0[0-9a-f]+ <[^>]+> f10d 0900 add\.w r9, sp, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f10d 0d04 add\.w sp, sp, #4 ; 0x4 -0[0-9a-f]+ <[^>]+> eb00 0000 add\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> eb10 0000 adds\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> eb00 0900 add\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> eb09 0000 add\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> eb00 0009 add\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> eb09 080a add\.w r8, r9, sl -0[0-9a-f]+ <[^>]+> eb09 484a add\.w r8, r9, sl, lsl #17 -0[0-9a-f]+ <[^>]+> eb08 081a add\.w r8, r8, sl, lsr #32 -0[0-9a-f]+ <[^>]+> eb08 485a add\.w r8, r8, sl, lsr #17 -0[0-9a-f]+ <[^>]+> eb09 082a add\.w r8, r9, sl, asr #32 -0[0-9a-f]+ <[^>]+> eb09 486a add\.w r8, r9, sl, asr #17 -0[0-9a-f]+ <[^>]+> eb09 083a add\.w r8, r9, sl, rrx -0[0-9a-f]+ <[^>]+> eb09 487a add\.w r8, r9, sl, ror #17 -0[0-9a-f]+ <[^>]+> 3800 subs r0, #0 -0[0-9a-f]+ <[^>]+> 1e05 subs r5, r0, #0 -0[0-9a-f]+ <[^>]+> 1e28 subs r0, r5, #0 -0[0-9a-f]+ <[^>]+> 1f50 subs r0, r2, #5 -0[0-9a-f]+ <[^>]+> 3881 subs r0, #129 -0[0-9a-f]+ <[^>]+> 3d08 subs r5, #8 -0[0-9a-f]+ <[^>]+> 1a00 subs r0, r0, r0 -0[0-9a-f]+ <[^>]+> 1a05 subs r5, r0, r0 -0[0-9a-f]+ <[^>]+> 1a28 subs r0, r5, r0 -0[0-9a-f]+ <[^>]+> 1b40 subs r0, r0, r5 -0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260 -0[0-9a-f]+ <[^>]+> b0c1 sub sp, #260 -0[0-9a-f]+ <[^>]+> ebb8 0800 subs\.w r8, r8, r0 -0[0-9a-f]+ <[^>]+> ebb0 0008 subs\.w r0, r0, r8 -0[0-9a-f]+ <[^>]+> f5b0 7082 subs\.w r0, r0, #260 ; 0x104 -0[0-9a-f]+ <[^>]+> f1b2 0104 subs\.w r1, r2, #4 ; 0x4 -0[0-9a-f]+ <[^>]+> f5b3 3580 subs\.w r5, r3, #65536 ; 0x10000 -0[0-9a-f]+ <[^>]+> f1ad 0104 sub\.w r1, sp, #4 ; 0x4 -0[0-9a-f]+ <[^>]+> f1ad 0900 sub\.w r9, sp, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1ad 0d04 sub\.w sp, sp, #4 ; 0x4 -0[0-9a-f]+ <[^>]+> 4140 adcs r0, r0 -0[0-9a-f]+ <[^>]+> 4145 adcs r5, r0 -0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 -0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 -0[0-9a-f]+ <[^>]+> 4168 adcs r0, r5 -0[0-9a-f]+ <[^>]+> eb45 0000 adc\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> eb41 0002 adc\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> eb40 0900 adc\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> eb49 0000 adc\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> eb40 0009 adc\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> eb50 0000 adcs\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> eb41 4062 adc\.w r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f141 0081 adc\.w r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 4000 ands r0, r0 -0[0-9a-f]+ <[^>]+> 4005 ands r5, r0 -0[0-9a-f]+ <[^>]+> 4028 ands r0, r5 -0[0-9a-f]+ <[^>]+> 4028 ands r0, r5 -0[0-9a-f]+ <[^>]+> 4028 ands r0, r5 -0[0-9a-f]+ <[^>]+> ea05 0000 and\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> ea01 0002 and\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> ea00 0900 and\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> ea09 0000 and\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> ea00 0009 and\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> ea10 0000 ands\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> ea01 4062 and\.w r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f001 0081 and\.w r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 4380 bics r0, r0 -0[0-9a-f]+ <[^>]+> 4385 bics r5, r0 -0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5 -0[0-9a-f]+ <[^>]+> 43a8 bics r0, r5 -0[0-9a-f]+ <[^>]+> ea35 0000 bics\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> ea25 0000 bic\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> ea21 0002 bic\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> ea20 0900 bic\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> ea29 0000 bic\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> ea20 0009 bic\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> ea30 0000 bics\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> ea21 4062 bic\.w r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f021 0081 bic\.w r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 4040 eors r0, r0 -0[0-9a-f]+ <[^>]+> 4045 eors r5, r0 -0[0-9a-f]+ <[^>]+> 4068 eors r0, r5 -0[0-9a-f]+ <[^>]+> 4068 eors r0, r5 -0[0-9a-f]+ <[^>]+> 4068 eors r0, r5 -0[0-9a-f]+ <[^>]+> ea85 0000 eor\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> ea81 0002 eor\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> ea80 0900 eor\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> ea89 0000 eor\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> ea80 0009 eor\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> ea90 0000 eors\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> ea81 4062 eor\.w r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f081 0081 eor\.w r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 4300 orrs r0, r0 -0[0-9a-f]+ <[^>]+> 4305 orrs r5, r0 -0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5 -0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5 -0[0-9a-f]+ <[^>]+> 4328 orrs r0, r5 -0[0-9a-f]+ <[^>]+> ea45 0000 orr\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> ea41 0002 orr\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> ea40 0900 orr\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> ea49 0000 orr\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> ea40 0009 orr\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> ea50 0000 orrs\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> ea41 4062 orr\.w r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f041 0081 orr\.w r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0 -0[0-9a-f]+ <[^>]+> ebd5 0500 rsbs r5, r5, r0 -0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5 -0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5 -0[0-9a-f]+ <[^>]+> ebd5 0000 rsbs r0, r5, r0 -0[0-9a-f]+ <[^>]+> ebc5 0000 rsb r0, r5, r0 -0[0-9a-f]+ <[^>]+> ebc1 0002 rsb r0, r1, r2 -0[0-9a-f]+ <[^>]+> ebc0 0900 rsb r9, r0, r0 -0[0-9a-f]+ <[^>]+> ebc9 0000 rsb r0, r9, r0 -0[0-9a-f]+ <[^>]+> ebc0 0009 rsb r0, r0, r9 -0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0 -0[0-9a-f]+ <[^>]+> ebc1 4062 rsb r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f1c1 0081 rsb r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 4180 sbcs r0, r0 -0[0-9a-f]+ <[^>]+> 4185 sbcs r5, r0 -0[0-9a-f]+ <[^>]+> 41a8 sbcs r0, r5 -0[0-9a-f]+ <[^>]+> 41a8 sbcs r0, r5 -0[0-9a-f]+ <[^>]+> eb75 0000 sbcs\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> eb65 0000 sbc\.w r0, r5, r0 -0[0-9a-f]+ <[^>]+> eb61 0002 sbc\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> eb60 0900 sbc\.w r9, r0, r0 -0[0-9a-f]+ <[^>]+> eb69 0000 sbc\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> eb60 0009 sbc\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> eb70 0000 sbcs\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> eb61 4062 sbc\.w r0, r1, r2, asr #17 -0[0-9a-f]+ <[^>]+> f161 0081 sbc\.w r0, r1, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f36f 0000 bfc r0, #0, #1 -0[0-9a-f]+ <[^>]+> f36f 0900 bfc r9, #0, #1 -0[0-9a-f]+ <[^>]+> f36f 0900 bfc r9, #0, #1 -0[0-9a-f]+ <[^>]+> f36f 5055 bfc r0, #21, #1 -0[0-9a-f]+ <[^>]+> f36f 0011 bfc r0, #0, #18 -0[0-9a-f]+ <[^>]+> f360 0000 bfi r0, r0, #0, #1 -0[0-9a-f]+ <[^>]+> f360 0900 bfi r9, r0, #0, #1 -0[0-9a-f]+ <[^>]+> f369 0000 bfi r0, r9, #0, #1 -0[0-9a-f]+ <[^>]+> f360 5055 bfi r0, r0, #21, #1 -0[0-9a-f]+ <[^>]+> f360 0011 bfi r0, r0, #0, #18 -0[0-9a-f]+ <[^>]+> f340 0000 sbfx r0, r0, #0, #1 -0[0-9a-f]+ <[^>]+> f3c0 0900 ubfx r9, r0, #0, #1 -0[0-9a-f]+ <[^>]+> f349 0000 sbfx r0, r9, #0, #1 -0[0-9a-f]+ <[^>]+> f3c0 5040 ubfx r0, r0, #21, #1 -0[0-9a-f]+ <[^>]+> f340 0011 sbfx r0, r0, #0, #18 -0[0-9a-f]+ <[^>]+> d0fe beq\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d02a beq\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d1fc bne\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d128 bne\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d2fa bcs\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d226 bcs\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d2f8 bcs\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d224 bcs\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d3f6 bcc\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d322 bcc\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d3f4 bcc\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d320 bcc\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d3f2 bcc\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d31e bcc\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d4f0 bmi\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d41c bmi\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d5ee bpl\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d51a bpl\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d6ec bvs\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d618 bvs\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d7ea bvc\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d716 bvc\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d8e8 bhi\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d814 bhi\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d9e6 bls\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d912 bls\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d7e4 bvc\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d710 bvc\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d8e2 bhi\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d80e bhi\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> d9e0 bls\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> d90c bls\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> dade bge\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> da0a bge\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> dbdc blt\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> db08 blt\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> dcda bgt\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> dc06 bgt\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> ddd8 ble\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> dd04 ble\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> e7d6 b\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> e002 b\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> e7d4 b\.n 0+2ca <[^>]+> -0[0-9a-f]+ <[^>]+> e000 b\.n 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> 46c0 nop \(mov r8, r8\) -0[0-9a-f]+ <[^>]+> f43f affe beq\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f000 8058 beq\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f47f affa bne\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f040 8054 bne\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f4bf aff6 bcs\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f080 8050 bcs\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f4bf aff2 bcs\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f080 804c bcs\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f4ff afee bcc\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f0c0 8048 bcc\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f4ff afea bcc\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f0c0 8044 bcc\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f4ff afe6 bcc\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f0c0 8040 bcc\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f53f afe2 bmi\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f100 803c bmi\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f57f afde bpl\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f140 8038 bpl\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f5bf afda bvs\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f180 8034 bvs\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f5ff afd6 bvc\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f1c0 8030 bvc\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f63f afd2 bhi\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f200 802c bhi\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f67f afce bls\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f240 8028 bls\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f5ff afca bvc\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f1c0 8024 bvc\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f63f afc6 bhi\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f200 8020 bhi\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f67f afc2 bls\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f240 801c bls\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f6bf afbe bge\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f280 8018 bge\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f6ff afba blt\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f2c0 8014 blt\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f73f afb6 bgt\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f300 8010 bgt\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f77f afb2 ble\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f340 800c ble\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f7ff bfae b\.w 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f000 b808 b\.w 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f7ff ffaa bl 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f000 f804 bl 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> f7ff efa6 blx 0+324 <[^>]+> -0[0-9a-f]+ <[^>]+> f000 e800 blx 0+3dc <[^>]+> -0[0-9a-f]+ <[^>]+> 4748 bx r9 -0[0-9a-f]+ <[^>]+> 4780 blx r0 -0[0-9a-f]+ <[^>]+> 47c8 blx r9 -0[0-9a-f]+ <[^>]+> f3c0 8f00 bxj r0 -0[0-9a-f]+ <[^>]+> f3c9 8f00 bxj r9 -0[0-9a-f]+ <[^>]+> fab0 f080 clz r0, r0 -0[0-9a-f]+ <[^>]+> fab0 f980 clz r9, r0 -0[0-9a-f]+ <[^>]+> fab9 f089 clz r0, r9 -0[0-9a-f]+ <[^>]+> b661 cpsie f -0[0-9a-f]+ <[^>]+> b672 cpsid i -0[0-9a-f]+ <[^>]+> b664 cpsie a -0[0-9a-f]+ <[^>]+> f3af 8620 cpsid\.w f -0[0-9a-f]+ <[^>]+> f3af 8440 cpsie\.w i -0[0-9a-f]+ <[^>]+> f3af 8680 cpsid\.w a -0[0-9a-f]+ <[^>]+> f3af 8540 cpsie i, #0 -0[0-9a-f]+ <[^>]+> f3af 8751 cpsid i, #17 -0[0-9a-f]+ <[^>]+> f3af 8100 cps #0 -0[0-9a-f]+ <[^>]+> f3af 8111 cps #17 -0[0-9a-f]+ <[^>]+> 4600 mov r0, r0 -0[0-9a-f]+ <[^>]+> 4681 mov r9, r0 -0[0-9a-f]+ <[^>]+> 4648 mov r0, r9 -0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0 -0[0-9a-f]+ <[^>]+> ea4f 0900 mov\.w r9, r0 -0[0-9a-f]+ <[^>]+> ea4f 0009 mov\.w r0, r9 -0[0-9a-f]+ <[^>]+> b910 cbnz r0, 0+432 <[^>]+> -0[0-9a-f]+ <[^>]+> b105 cbz r5, 0+430 <[^>]+> -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf10 yield -0[0-9a-f]+ <[^>]+> bf20 wfe -0[0-9a-f]+ <[^>]+> bf30 wfi -0[0-9a-f]+ <[^>]+> bf40 sev -0[0-9a-f]+ <[^>]+> f3af 8000 nop\.w -0[0-9a-f]+ <[^>]+> f3af 8001 yield\.w -0[0-9a-f]+ <[^>]+> f3af 8002 wfe\.w -0[0-9a-f]+ <[^>]+> f3af 8003 wfi\.w -0[0-9a-f]+ <[^>]+> f3af 9004 sev\.w -0[0-9a-f]+ <[^>]+> bf90 nop \{9\} -0[0-9a-f]+ <[^>]+> f3af 8081 nop\.w \{129\} -0[0-9a-f]+ <[^>]+> bf08 it eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf18 it ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf28 it cs -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf28 it cs -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf38 it cc -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf48 it mi -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf58 it pl -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf68 it vs -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf78 it vc -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf88 it hi -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bfa8 it ge -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bfb8 it lt -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bfc8 it gt -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bfd8 it le -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bfe8 it al -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf04 itt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf0c ite eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf02 ittt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf0a itet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf06 itte eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf0e itee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf01 itttt eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf09 itett eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf05 ittet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf03 ittte eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf07 ittee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf0b itete eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf0d iteet eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf0f iteee eq -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf1c itt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf14 ite ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf1e ittt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf16 itet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf1a itte ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf12 itee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf1f itttt ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf17 itett ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf1b ittet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf1d ittte ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf19 ittee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf15 itete ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf13 iteet ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf11 iteee ne -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> bf00 nop -0[0-9a-f]+ <[^>]+> f895 f000 pld \[r5\] -0[0-9a-f]+ <[^>]+> f895 f330 pld \[r5, #816\] -0[0-9a-f]+ <[^>]+> f815 fc30 pld \[r5, #-48\] -0[0-9a-f]+ <[^>]+> f815 fb30 pld \[r5\], #48 -0[0-9a-f]+ <[^>]+> f815 f930 pld \[r5\], #-48 -0[0-9a-f]+ <[^>]+> f815 ff30 pld \[r5, #48\]! -0[0-9a-f]+ <[^>]+> f815 fd30 pld \[r5, #-48\]! -0[0-9a-f]+ <[^>]+> f815 f004 pld \[r5, r4\] -0[0-9a-f]+ <[^>]+> f819 f00c pld \[r9, ip\] -0[0-9a-f]+ <[^>]+> f89f f006 pld \[pc, #6\] ; 0+5ba <[^>]+> -0[0-9a-f]+ <[^>]+> f81f f02a pld \[pc, #-42\] ; 0+58e <[^>]+> -0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\] -0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\] -0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\] -0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\] -0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\] -0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\] -0[0-9a-f]+ <[^>]+> f815 1e00 ldrbt r1, \[r5\] -0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\] -0[0-9a-f]+ <[^>]+> f915 1e00 ldrsbt r1, \[r5\] -0[0-9a-f]+ <[^>]+> f915 1e30 ldrsbt r1, \[r5, #48\] -0[0-9a-f]+ <[^>]+> f835 1e00 ldrht r1, \[r5\] -0[0-9a-f]+ <[^>]+> f835 1e30 ldrht r1, \[r5, #48\] -0[0-9a-f]+ <[^>]+> f935 1e00 ldrsht r1, \[r5\] -0[0-9a-f]+ <[^>]+> f935 1e30 ldrsht r1, \[r5, #48\] -0[0-9a-f]+ <[^>]+> f855 1e00 ldrt r1, \[r5\] -0[0-9a-f]+ <[^>]+> f855 1e30 ldrt r1, \[r5, #48\] -0[0-9a-f]+ <[^>]+> e8d4 1f4f ldrexb r1, \[r4\] -0[0-9a-f]+ <[^>]+> e8d4 1f5f ldrexh r1, \[r4\] -0[0-9a-f]+ <[^>]+> e854 1f00 ldrex r1, \[r4\] -0[0-9a-f]+ <[^>]+> e8d4 127f ldrexd r1, r2, \[r4\] -0[0-9a-f]+ <[^>]+> e8c4 2f41 strexb r1, r2, \[r4\] -0[0-9a-f]+ <[^>]+> e8c4 2f51 strexh r1, r2, \[r4\] -0[0-9a-f]+ <[^>]+> e844 2100 strex r1, r2, \[r4\] -0[0-9a-f]+ <[^>]+> e8c4 2371 strexd r1, r2, r3, \[r4\] -0[0-9a-f]+ <[^>]+> e854 1f81 ldrex r1, \[r4, #516\] -0[0-9a-f]+ <[^>]+> e844 2181 strex r1, r2, \[r4, #516\] -0[0-9a-f]+ <[^>]+> c80e ldmia r0!, \{r1, r2, r3\} -0[0-9a-f]+ <[^>]+> ca07 ldmia r2!, \{r0, r1, r2\} -0[0-9a-f]+ <[^>]+> e892 0007 ldmia\.w r2, \{r0, r1, r2\} -0[0-9a-f]+ <[^>]+> e899 0007 ldmia\.w r9, \{r0, r1, r2\} -0[0-9a-f]+ <[^>]+> e890 0580 ldmia\.w r0, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> e8b0 0580 ldmia\.w r0!, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> c00e stmia r0!, \{r1, r2, r3\} -0[0-9a-f]+ <[^>]+> c20b stmia r2!, \{r0, r1, r3\} -0[0-9a-f]+ <[^>]+> e8a2 000b stmia\.w r2!, \{r0, r1, r3\} -0[0-9a-f]+ <[^>]+> e889 0007 stmia\.w r9, \{r0, r1, r2\} -0[0-9a-f]+ <[^>]+> e880 0580 stmia\.w r0, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> e8a0 0580 stmia\.w r0!, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> e910 0580 ldmdb r0, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> e900 0580 stmdb r0, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> fb00 0000 mla r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb00 0010 mls r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb00 0900 mla r9, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb09 0000 mla r0, r9, r0, r0 -0[0-9a-f]+ <[^>]+> fb00 0009 mla r0, r0, r9, r0 -0[0-9a-f]+ <[^>]+> fb00 9000 mla r0, r0, r0, r9 -0[0-9a-f]+ <[^>]+> 4200 tst r0, r0 -0[0-9a-f]+ <[^>]+> 4200 tst r0, r0 -0[0-9a-f]+ <[^>]+> 4205 tst r5, r0 -0[0-9a-f]+ <[^>]+> 4228 tst r0, r5 -0[0-9a-f]+ <[^>]+> ea10 4f65 tst\.w r0, r5, asr #17 -0[0-9a-f]+ <[^>]+> ea10 0f00 tst\.w r0, r0 -0[0-9a-f]+ <[^>]+> ea19 0f00 tst\.w r9, r0 -0[0-9a-f]+ <[^>]+> ea10 0f09 tst\.w r0, r9 -0[0-9a-f]+ <[^>]+> f010 0f81 tst\.w r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f015 0f81 tst\.w r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0 -0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0 -0[0-9a-f]+ <[^>]+> ea95 0f00 teq r5, r0 -0[0-9a-f]+ <[^>]+> ea90 0f05 teq r0, r5 -0[0-9a-f]+ <[^>]+> ea90 4f65 teq r0, r5, asr #17 -0[0-9a-f]+ <[^>]+> ea90 0f00 teq r0, r0 -0[0-9a-f]+ <[^>]+> ea99 0f00 teq r9, r0 -0[0-9a-f]+ <[^>]+> ea90 0f09 teq r0, r9 -0[0-9a-f]+ <[^>]+> f090 0f81 teq r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f095 0f81 teq r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0 -0[0-9a-f]+ <[^>]+> 4280 cmp r0, r0 -0[0-9a-f]+ <[^>]+> 4285 cmp r5, r0 -0[0-9a-f]+ <[^>]+> 42a8 cmp r0, r5 -0[0-9a-f]+ <[^>]+> ebb0 4f65 cmp\.w r0, r5, asr #17 -0[0-9a-f]+ <[^>]+> ebb0 0f00 cmp\.w r0, r0 -0[0-9a-f]+ <[^>]+> 4581 cmp r9, r0 -0[0-9a-f]+ <[^>]+> ebb0 0f09 cmp\.w r0, r9 -0[0-9a-f]+ <[^>]+> f1b0 0f81 cmp\.w r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f1b5 0f81 cmp\.w r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0 -0[0-9a-f]+ <[^>]+> 42c0 cmn r0, r0 -0[0-9a-f]+ <[^>]+> 42c5 cmn r5, r0 -0[0-9a-f]+ <[^>]+> 42e8 cmn r0, r5 -0[0-9a-f]+ <[^>]+> eb10 4f65 cmn\.w r0, r5, asr #17 -0[0-9a-f]+ <[^>]+> eb10 0f00 cmn\.w r0, r0 -0[0-9a-f]+ <[^>]+> eb19 0f00 cmn\.w r9, r0 -0[0-9a-f]+ <[^>]+> eb10 0f09 cmn\.w r0, r9 -0[0-9a-f]+ <[^>]+> f110 0f81 cmn\.w r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f115 0f81 cmn\.w r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 1c00 adds r0, r0, #0 -0[0-9a-f]+ <[^>]+> 4600 mov r0, r0 -0[0-9a-f]+ <[^>]+> 1c05 adds r5, r0, #0 -0[0-9a-f]+ <[^>]+> 4628 mov r0, r5 -0[0-9a-f]+ <[^>]+> ea4f 4065 mov\.w r0, r5, asr #17 -0[0-9a-f]+ <[^>]+> ea4f 0000 mov\.w r0, r0 -0[0-9a-f]+ <[^>]+> ea5f 0900 movs\.w r9, r0 -0[0-9a-f]+ <[^>]+> ea5f 0009 movs\.w r0, r9 -0[0-9a-f]+ <[^>]+> f04f 0081 mov\.w r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f04f 0581 mov\.w r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> 43c0 mvns r0, r0 -0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0 -0[0-9a-f]+ <[^>]+> 43c5 mvns r5, r0 -0[0-9a-f]+ <[^>]+> ea6f 0005 mvn\.w r0, r5 -0[0-9a-f]+ <[^>]+> ea6f 4065 mvn\.w r0, r5, asr #17 -0[0-9a-f]+ <[^>]+> ea6f 0000 mvn\.w r0, r0 -0[0-9a-f]+ <[^>]+> ea7f 0900 mvns\.w r9, r0 -0[0-9a-f]+ <[^>]+> ea7f 0009 mvns\.w r0, r9 -0[0-9a-f]+ <[^>]+> f06f 0081 mvn\.w r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f06f 0581 mvn\.w r5, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f240 0000 movw r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f2c0 0000 movt r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f240 0900 movw r9, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f249 0000 movw r0, #36864 ; 0x9000 -0[0-9a-f]+ <[^>]+> f640 0000 movw r0, #2048 ; 0x800 -0[0-9a-f]+ <[^>]+> f240 5000 movw r0, #1280 ; 0x500 -0[0-9a-f]+ <[^>]+> f240 0081 movw r0, #129 ; 0x81 -0[0-9a-f]+ <[^>]+> f64f 70ff movw r0, #65535 ; 0xffff -0[0-9a-f]+ <[^>]+> f3ef 8000 mrs r0, CPSR -0[0-9a-f]+ <[^>]+> f3ff 8000 mrs r0, SPSR -0[0-9a-f]+ <[^>]+> f3ef 8900 mrs r9, CPSR -0[0-9a-f]+ <[^>]+> f3ff 8900 mrs r9, SPSR -0[0-9a-f]+ <[^>]+> f380 8100 msr CPSR_c, r0 -0[0-9a-f]+ <[^>]+> f390 8100 msr SPSR_c, r0 -0[0-9a-f]+ <[^>]+> f389 8100 msr CPSR_c, r9 -0[0-9a-f]+ <[^>]+> f380 8200 msr CPSR_x, r0 -0[0-9a-f]+ <[^>]+> f380 8400 msr CPSR_s, r0 -0[0-9a-f]+ <[^>]+> f380 8800 msr CPSR_f, r0 -0[0-9a-f]+ <[^>]+> fb00 f000 mul\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb09 f000 mul\.w r0, r9, r0 -0[0-9a-f]+ <[^>]+> fb00 f009 mul\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> fb00 f000 mul\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb00 f909 mul\.w r9, r0, r9 -0[0-9a-f]+ <[^>]+> 4345 muls r5, r0 -0[0-9a-f]+ <[^>]+> 4345 muls r5, r0 -0[0-9a-f]+ <[^>]+> 4368 muls r0, r5 -0[0-9a-f]+ <[^>]+> fb80 0100 smull r0, r1, r0, r0 -0[0-9a-f]+ <[^>]+> fba0 0100 umull r0, r1, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 0100 smlal r0, r1, r0, r0 -0[0-9a-f]+ <[^>]+> fbe0 0100 umlal r0, r1, r0, r0 -0[0-9a-f]+ <[^>]+> fb80 9000 smull r9, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb80 0900 smull r0, r9, r0, r0 -0[0-9a-f]+ <[^>]+> fb89 0100 smull r0, r1, r9, r0 -0[0-9a-f]+ <[^>]+> fb80 0109 smull r0, r1, r0, r9 -0[0-9a-f]+ <[^>]+> 4240 negs r0, r0 -0[0-9a-f]+ <[^>]+> 4268 negs r0, r5 -0[0-9a-f]+ <[^>]+> 4245 negs r5, r0 -0[0-9a-f]+ <[^>]+> f1d0 0000 rsbs r0, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d0 0500 rsbs r5, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d5 0000 rsbs r0, r5, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1c9 0000 rsb r0, r9, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1c0 0900 rsb r9, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d9 0000 rsbs r0, r9, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f1d0 0900 rsbs r9, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> eac0 0000 pkhbt r0, r0, r0 -0[0-9a-f]+ <[^>]+> eac0 0900 pkhbt r9, r0, r0 -0[0-9a-f]+ <[^>]+> eac9 0000 pkhbt r0, r9, r0 -0[0-9a-f]+ <[^>]+> eac0 0009 pkhbt r0, r0, r9 -0[0-9a-f]+ <[^>]+> eac0 5000 pkhbt r0, r0, r0, lsl #20 -0[0-9a-f]+ <[^>]+> eac0 00c0 pkhbt r0, r0, r0, lsl #3 -0[0-9a-f]+ <[^>]+> eac2 0103 pkhbt r1, r2, r3 -0[0-9a-f]+ <[^>]+> eac2 4163 pkhtb r1, r2, r3, asr #17 -0[0-9a-f]+ <[^>]+> b401 push \{r0\} -0[0-9a-f]+ <[^>]+> bc01 pop \{r0\} -0[0-9a-f]+ <[^>]+> b502 push \{r1, lr\} -0[0-9a-f]+ <[^>]+> bd02 pop \{r1, pc\} -0[0-9a-f]+ <[^>]+> e92d 1f00 stmdb sp!, \{r8, r9, sl, fp, ip\} -0[0-9a-f]+ <[^>]+> e8bd 1f00 ldmia\.w sp!, \{r8, r9, sl, fp, ip\} -0[0-9a-f]+ <[^>]+> fa92 f113 qadd16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa82 f113 qadd8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f113 qaddsubx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fad2 f113 qsub16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fac2 f113 qsub8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fae2 f113 qsubaddx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa92 f103 sadd16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa82 f103 sadd8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f103 saddsubx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fad2 f103 ssub16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fac2 f103 ssub8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fae2 f103 ssubaddx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa92 f123 shadd16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa82 f123 shadd8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f123 shaddsubx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fad2 f123 shsub16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fac2 f123 shsub8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fae2 f123 shsubaddx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa92 f143 uadd16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa82 f143 uadd8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f143 uaddsubx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fad2 f143 usub16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fac2 f143 usub8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fae2 f143 usubaddx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa92 f163 uhadd16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa82 f163 uhadd8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f163 uhaddsubx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fad2 f163 uhsub16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fac2 f163 uhsub8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fae2 f163 uhsubaddx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa92 f153 uqadd16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa82 f153 uqadd8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f153 uqaddsubx r1, r2, r3 -0[0-9a-f]+ <[^>]+> fad2 f153 uqsub16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fac2 f153 uqsub8 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fae2 f153 uqsubaddx r1, r2, r3 -0[0-9a-f]+ <[^>]+> faa2 f183 sel r1, r2, r3 -0[0-9a-f]+ <[^>]+> ba00 rev r0, r0 -0[0-9a-f]+ <[^>]+> fa90 f080 rev\.w r0, r0 -0[0-9a-f]+ <[^>]+> ba28 rev r0, r5 -0[0-9a-f]+ <[^>]+> ba05 rev r5, r0 -0[0-9a-f]+ <[^>]+> fa99 f089 rev\.w r0, r9 -0[0-9a-f]+ <[^>]+> fa90 f980 rev\.w r9, r0 -0[0-9a-f]+ <[^>]+> ba40 rev16 r0, r0 -0[0-9a-f]+ <[^>]+> fa90 f090 rev16\.w r0, r0 -0[0-9a-f]+ <[^>]+> ba68 rev16 r0, r5 -0[0-9a-f]+ <[^>]+> ba45 rev16 r5, r0 -0[0-9a-f]+ <[^>]+> fa99 f099 rev16\.w r0, r9 -0[0-9a-f]+ <[^>]+> fa90 f990 rev16\.w r9, r0 -0[0-9a-f]+ <[^>]+> bac0 revsh r0, r0 -0[0-9a-f]+ <[^>]+> fa90 f0b0 revsh\.w r0, r0 -0[0-9a-f]+ <[^>]+> bae8 revsh r0, r5 -0[0-9a-f]+ <[^>]+> bac5 revsh r5, r0 -0[0-9a-f]+ <[^>]+> fa99 f0b9 revsh\.w r0, r9 -0[0-9a-f]+ <[^>]+> fa90 f9b0 revsh\.w r9, r0 -0[0-9a-f]+ <[^>]+> fa90 f0a0 rbit r0, r0 -0[0-9a-f]+ <[^>]+> fa90 f0a0 rbit r0, r0 -0[0-9a-f]+ <[^>]+> fa95 f0a0 rbit r0, r5 -0[0-9a-f]+ <[^>]+> fa90 f5a0 rbit r5, r0 -0[0-9a-f]+ <[^>]+> fa99 f0a0 rbit r0, r9 -0[0-9a-f]+ <[^>]+> fa90 f9a0 rbit r9, r0 -0[0-9a-f]+ <[^>]+> 0440 lsls r0, r0, #17 -0[0-9a-f]+ <[^>]+> 0380 lsls r0, r0, #14 -0[0-9a-f]+ <[^>]+> 0445 lsls r5, r0, #17 -0[0-9a-f]+ <[^>]+> 03a8 lsls r0, r5, #14 -0[0-9a-f]+ <[^>]+> 4080 lsls r0, r0 -0[0-9a-f]+ <[^>]+> 40a8 lsls r0, r5 -0[0-9a-f]+ <[^>]+> 40a8 lsls r0, r5 -0[0-9a-f]+ <[^>]+> ea4f 4949 mov\.w r9, r9, lsl #17 -0[0-9a-f]+ <[^>]+> ea4f 3989 mov\.w r9, r9, lsl #14 -0[0-9a-f]+ <[^>]+> ea5f 4049 movs\.w r0, r9, lsl #17 -0[0-9a-f]+ <[^>]+> ea4f 3980 mov\.w r9, r0, lsl #14 -0[0-9a-f]+ <[^>]+> fa00 f000 lsl\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> fa09 f909 lsl\.w r9, r9, r9 -0[0-9a-f]+ <[^>]+> fa19 f900 lsls\.w r9, r9, r0 -0[0-9a-f]+ <[^>]+> fa00 f009 lsl\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> fa00 f005 lsl\.w r0, r0, r5 -0[0-9a-f]+ <[^>]+> fa11 f002 lsls\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> 0c40 lsrs r0, r0, #17 -0[0-9a-f]+ <[^>]+> 0b80 lsrs r0, r0, #14 -0[0-9a-f]+ <[^>]+> 0c45 lsrs r5, r0, #17 -0[0-9a-f]+ <[^>]+> 0ba8 lsrs r0, r5, #14 -0[0-9a-f]+ <[^>]+> 40c0 lsrs r0, r0 -0[0-9a-f]+ <[^>]+> 40e8 lsrs r0, r5 -0[0-9a-f]+ <[^>]+> 40e8 lsrs r0, r5 -0[0-9a-f]+ <[^>]+> ea4f 4959 mov\.w r9, r9, lsr #17 -0[0-9a-f]+ <[^>]+> ea4f 3999 mov\.w r9, r9, lsr #14 -0[0-9a-f]+ <[^>]+> ea5f 4059 movs\.w r0, r9, lsr #17 -0[0-9a-f]+ <[^>]+> ea4f 3990 mov\.w r9, r0, lsr #14 -0[0-9a-f]+ <[^>]+> fa20 f000 lsr\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> fa29 f909 lsr\.w r9, r9, r9 -0[0-9a-f]+ <[^>]+> fa39 f900 lsrs\.w r9, r9, r0 -0[0-9a-f]+ <[^>]+> fa20 f009 lsr\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> fa20 f005 lsr\.w r0, r0, r5 -0[0-9a-f]+ <[^>]+> fa31 f002 lsrs\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> 1440 asrs r0, r0, #17 -0[0-9a-f]+ <[^>]+> 1380 asrs r0, r0, #14 -0[0-9a-f]+ <[^>]+> 1445 asrs r5, r0, #17 -0[0-9a-f]+ <[^>]+> 13a8 asrs r0, r5, #14 -0[0-9a-f]+ <[^>]+> 4100 asrs r0, r0 -0[0-9a-f]+ <[^>]+> 4128 asrs r0, r5 -0[0-9a-f]+ <[^>]+> 4128 asrs r0, r5 -0[0-9a-f]+ <[^>]+> ea4f 4969 mov\.w r9, r9, asr #17 -0[0-9a-f]+ <[^>]+> ea4f 39a9 mov\.w r9, r9, asr #14 -0[0-9a-f]+ <[^>]+> ea5f 4069 movs\.w r0, r9, asr #17 -0[0-9a-f]+ <[^>]+> ea4f 39a0 mov\.w r9, r0, asr #14 -0[0-9a-f]+ <[^>]+> fa40 f000 asr\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> fa49 f909 asr\.w r9, r9, r9 -0[0-9a-f]+ <[^>]+> fa59 f900 asrs\.w r9, r9, r0 -0[0-9a-f]+ <[^>]+> fa40 f009 asr\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> fa40 f005 asr\.w r0, r0, r5 -0[0-9a-f]+ <[^>]+> fa51 f002 asrs\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> ea5f 4070 movs\.w r0, r0, ror #17 -0[0-9a-f]+ <[^>]+> ea5f 30b0 movs\.w r0, r0, ror #14 -0[0-9a-f]+ <[^>]+> ea5f 4570 movs\.w r5, r0, ror #17 -0[0-9a-f]+ <[^>]+> ea5f 30b5 movs\.w r0, r5, ror #14 -0[0-9a-f]+ <[^>]+> 41c0 rors r0, r0 -0[0-9a-f]+ <[^>]+> 41e8 rors r0, r5 -0[0-9a-f]+ <[^>]+> 41e8 rors r0, r5 -0[0-9a-f]+ <[^>]+> ea4f 4979 mov\.w r9, r9, ror #17 -0[0-9a-f]+ <[^>]+> ea4f 39b9 mov\.w r9, r9, ror #14 -0[0-9a-f]+ <[^>]+> ea5f 4079 movs\.w r0, r9, ror #17 -0[0-9a-f]+ <[^>]+> ea4f 39b0 mov\.w r9, r0, ror #14 -0[0-9a-f]+ <[^>]+> fa60 f000 ror\.w r0, r0, r0 -0[0-9a-f]+ <[^>]+> fa69 f909 ror\.w r9, r9, r9 -0[0-9a-f]+ <[^>]+> fa79 f900 rors\.w r9, r9, r0 -0[0-9a-f]+ <[^>]+> fa60 f009 ror\.w r0, r0, r9 -0[0-9a-f]+ <[^>]+> fa60 f005 ror\.w r0, r0, r5 -0[0-9a-f]+ <[^>]+> fa71 f002 rors\.w r0, r1, r2 -0[0-9a-f]+ <[^>]+> f7f0 8000 smc #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f7fd 8bca smc #43981 ; 0xabcd -0[0-9a-f]+ <[^>]+> fb10 0000 smlabb r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 0900 smlabb r9, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb19 0000 smlabb r0, r9, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 0009 smlabb r0, r0, r9, r0 -0[0-9a-f]+ <[^>]+> fb10 9000 smlabb r0, r0, r0, r9 -0[0-9a-f]+ <[^>]+> fb10 0020 smlatb r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 0010 smlabt r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 0030 smlatt r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb30 0000 smlawb r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb30 0010 smlawt r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb20 0000 smlad r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb20 0010 smladx r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb40 0000 smlsd r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb40 0010 smlsdx r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb50 0000 smmla r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb50 0010 smmlar r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb60 0000 smmls r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb60 0010 smmlsr r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb70 0000 usada8 r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 0080 smlalbb r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 9080 smlalbb r9, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 0980 smlalbb r0, r9, r0, r0 -0[0-9a-f]+ <[^>]+> fbc9 0080 smlalbb r0, r0, r9, r0 -0[0-9a-f]+ <[^>]+> fbc0 0089 smlalbb r0, r0, r0, r9 -0[0-9a-f]+ <[^>]+> fbc0 00a0 smlaltb r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 0090 smlalbt r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 00b0 smlaltt r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 00c0 smlald r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbc0 00d0 smlaldx r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbd0 00c0 smlsld r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbd0 00d0 smlsldx r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fbe0 0060 umaal r0, r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 f000 smulbb r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 f900 smulbb r9, r0, r0 -0[0-9a-f]+ <[^>]+> fb19 f000 smulbb r0, r9, r0 -0[0-9a-f]+ <[^>]+> fb10 f009 smulbb r0, r0, r9 -0[0-9a-f]+ <[^>]+> fb10 f020 smultb r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 f010 smulbt r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb10 f030 smultt r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb30 f000 smulwb r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb30 f010 smulwt r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb50 f000 smmul r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb50 f010 smmulr r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb20 f000 smuad r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb20 f010 smuadx r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0 -0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0 -0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0 -0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0 -0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0 -0[0-9a-f]+ <[^>]+> f300 0900 ssat r9, #0, r0 -0[0-9a-f]+ <[^>]+> f300 0011 ssat r0, #17, r0 -0[0-9a-f]+ <[^>]+> f309 0000 ssat r0, #0, r9 -0[0-9a-f]+ <[^>]+> f300 7000 ssat r0, #0, r0, lsl #28 -0[0-9a-f]+ <[^>]+> f320 00c0 ssat r0, #0, r0, asr #3 -0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0 -0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0 -0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0 -0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9 -0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0 -0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0 -0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0 -0[0-9a-f]+ <[^>]+> f380 0900 usat r9, #0, r0 -0[0-9a-f]+ <[^>]+> f380 0011 usat r0, #17, r0 -0[0-9a-f]+ <[^>]+> f389 0000 usat r0, #0, r9 -0[0-9a-f]+ <[^>]+> f380 7000 usat r0, #0, r0, lsl #28 -0[0-9a-f]+ <[^>]+> f3a0 00c0 usat r0, #0, r0, asr #3 -0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0 -0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0 -0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0 -0[0-9a-f]+ <[^>]+> f3a9 0000 usat16 r0, #0, r9 -0[0-9a-f]+ <[^>]+> b240 sxtb r0, r0 -0[0-9a-f]+ <[^>]+> b240 sxtb r0, r0 -0[0-9a-f]+ <[^>]+> b245 sxtb r5, r0 -0[0-9a-f]+ <[^>]+> b268 sxtb r0, r5 -0[0-9a-f]+ <[^>]+> fa4f f182 sxtb\.w r1, r2 -0[0-9a-f]+ <[^>]+> fa4f f192 sxtb\.w r1, r2, ror #8 -0[0-9a-f]+ <[^>]+> fa4f f1a2 sxtb\.w r1, r2, ror #16 -0[0-9a-f]+ <[^>]+> fa4f f1b2 sxtb\.w r1, r2, ror #24 -0[0-9a-f]+ <[^>]+> fa2f f182 sxtb16 r1, r2 -0[0-9a-f]+ <[^>]+> fa2f f889 sxtb16 r8, r9 -0[0-9a-f]+ <[^>]+> b211 sxth r1, r2 -0[0-9a-f]+ <[^>]+> fa0f f889 sxth\.w r8, r9 -0[0-9a-f]+ <[^>]+> b2d1 uxtb r1, r2 -0[0-9a-f]+ <[^>]+> fa5f f889 uxtb\.w r8, r9 -0[0-9a-f]+ <[^>]+> fa3f f182 uxtb16 r1, r2 -0[0-9a-f]+ <[^>]+> fa3f f889 uxtb16 r8, r9 -0[0-9a-f]+ <[^>]+> b291 uxth r1, r2 -0[0-9a-f]+ <[^>]+> fa1f f889 uxth\.w r8, r9 -0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0 -0[0-9a-f]+ <[^>]+> fa40 f080 sxtab r0, r0, r0 -0[0-9a-f]+ <[^>]+> fa40 f990 sxtab r9, r0, r0, ror #8 -0[0-9a-f]+ <[^>]+> fa49 f0a0 sxtab r0, r9, r0, ror #16 -0[0-9a-f]+ <[^>]+> fa40 f0b9 sxtab r0, r0, r9, ror #24 -0[0-9a-f]+ <[^>]+> fa22 f183 sxtab16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa02 f183 sxtah r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa52 f183 uxtab r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa32 f183 uxtab16 r1, r2, r3 -0[0-9a-f]+ <[^>]+> fa12 f183 uxtah r1, r2, r3 -0[0-9a-f]+ <[^>]+> f89f 12aa ldrb\.w r1, \[pc, #682\] ; 0+e02 <[^>]+> -0[0-9a-f]+ <[^>]+> f89f 1155 ldrb\.w r1, \[pc, #341\] ; 0+cb1 <[^>]+> -0[0-9a-f]+ <[^>]+> f81f 12aa ldrb\.w r1, \[pc, #-682\] ; 0+8b6 <[^>]+> -0[0-9a-f]+ <[^>]+> f81f 1155 ldrb\.w r1, \[pc, #-341\] ; 0+a0f <[^>]+> -0[0-9a-f]+ <[^>]+> f99f 12aa ldrsb\.w r1, \[pc, #682\] ; 0+e12 <[^>]+> -0[0-9a-f]+ <[^>]+> f99f 1155 ldrsb\.w r1, \[pc, #341\] ; 0+cc1 <[^>]+> -0[0-9a-f]+ <[^>]+> f91f 12aa ldrsb\.w r1, \[pc, #-682\] ; 0+8c6 <[^>]+> -0[0-9a-f]+ <[^>]+> f91f 1155 ldrsb\.w r1, \[pc, #-341\] ; 0+a1f <[^>]+> -0[0-9a-f]+ <[^>]+> f8bf 12aa ldrh\.w r1, \[pc, #682\] ; 0+e22 <[^>]+> -0[0-9a-f]+ <[^>]+> f8bf 1155 ldrh\.w r1, \[pc, #341\] ; 0+cd1 <[^>]+> -0[0-9a-f]+ <[^>]+> f83f 12aa ldrh\.w r1, \[pc, #-682\] ; 0+8d6 <[^>]+> -0[0-9a-f]+ <[^>]+> f83f 1155 ldrh\.w r1, \[pc, #-341\] ; 0+a2f <[^>]+> -0[0-9a-f]+ <[^>]+> f9bf 12aa ldrsh\.w r1, \[pc, #682\] ; 0+e32 <[^>]+> -0[0-9a-f]+ <[^>]+> f9bf 1155 ldrsh\.w r1, \[pc, #341\] ; 0+ce1 <[^>]+> -0[0-9a-f]+ <[^>]+> f93f 12aa ldrsh\.w r1, \[pc, #-682\] ; 0+8e6 <[^>]+> -0[0-9a-f]+ <[^>]+> f93f 1155 ldrsh\.w r1, \[pc, #-341\] ; 0+a3f <[^>]+> -0[0-9a-f]+ <[^>]+> f8df 12aa ldr\.w r1, \[pc, #682\] ; 0+e42 <[^>]+> -0[0-9a-f]+ <[^>]+> f8df 1155 ldr\.w r1, \[pc, #341\] ; 0+cf1 <[^>]+> -0[0-9a-f]+ <[^>]+> f85f 12aa ldr\.w r1, \[pc, #-682\] ; 0+8f6 <[^>]+> -0[0-9a-f]+ <[^>]+> f85f 1155 ldr\.w r1, \[pc, #-341\] ; 0+a4f <[^>]+> -0[0-9a-f]+ <[^>]+> f200 0900 addw r9, r0, #0 ; 0x0 -0[0-9a-f]+ <[^>]+> f60f 76ff addw r6, pc, #4095 ; 0xfff -0[0-9a-f]+ <[^>]+> f6a9 2685 subw r6, r9, #2693 ; 0xa85 -0[0-9a-f]+ <[^>]+> f2a9 567a subw r6, r9, #1402 ; 0x57a -0[0-9a-f]+ <[^>]+> e8df f006 tbb \[pc, r6\] -0[0-9a-f]+ <[^>]+> e8d0 f009 tbb \[r0, r9\] -0[0-9a-f]+ <[^>]+> e8df f017 tbh \[pc, r7, lsl #1\] -0[0-9a-f]+ <[^>]+> e8d0 f018 tbh \[r0, r8, lsl #1\] -0[0-9a-f]+ <[^>]+> f84d 8d04 str.w r8, \[sp, #-4\]! -0[0-9a-f]+ <[^>]+> f85d 8b04 ldr.w r8, \[sp\], #4 -0[0-9a-f]+ <[^>]+> e930 0580 ldmdb r0!, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> e920 0580 stmdb r0!, \{r7, r8, sl\} -0[0-9a-f]+ <[^>]+> c806 ldmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> c006 stmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} -0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} -0[0-9a-f]+ <[^>]+> bf01 itttt eq -0[0-9a-f]+ <[^>]+> c806 ldmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> c006 stmia r0!, \{r1, r2\} -0[0-9a-f]+ <[^>]+> e890 0300 ldmia.w r0, \{r8, r9\} -0[0-9a-f]+ <[^>]+> e880 0300 stmia.w r0, \{r8, r9\} -0[0-9a-f]+ <[^>]+> bf00 nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumb32.s b/binutils-2.17/gas/testsuite/gas/arm/thumb32.s deleted file mode 100644 index b75a0850..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumb32.s +++ /dev/null @@ -1,771 +0,0 @@ - .text - .thumb - .syntax unified - -encode_thumb32_immediate: - orr r0, r1, #0x00000000 - orr r0, r1, #0x000000a5 - orr r0, r1, #0x00a500a5 - orr r0, r1, #0xa500a500 - orr r0, r1, #0xa5a5a5a5 - - orr r0, r1, #0xa5 << 31 - orr r0, r1, #0xa5 << 30 - orr r0, r1, #0xa5 << 29 - orr r0, r1, #0xa5 << 28 - orr r0, r1, #0xa5 << 27 - orr r0, r1, #0xa5 << 26 - orr r0, r1, #0xa5 << 25 - orr r0, r1, #0xa5 << 24 - orr r0, r1, #0xa5 << 23 - orr r0, r1, #0xa5 << 22 - orr r0, r1, #0xa5 << 21 - orr r0, r1, #0xa5 << 20 - orr r0, r1, #0xa5 << 19 - orr r0, r1, #0xa5 << 18 - orr r0, r1, #0xa5 << 17 - orr r0, r1, #0xa5 << 16 - orr r0, r1, #0xa5 << 15 - orr r0, r1, #0xa5 << 14 - orr r0, r1, #0xa5 << 13 - orr r0, r1, #0xa5 << 12 - orr r0, r1, #0xa5 << 11 - orr r0, r1, #0xa5 << 10 - orr r0, r1, #0xa5 << 9 - orr r0, r1, #0xa5 << 8 - orr r0, r1, #0xa5 << 7 - orr r0, r1, #0xa5 << 6 - orr r0, r1, #0xa5 << 5 - orr r0, r1, #0xa5 << 4 - orr r0, r1, #0xa5 << 3 - orr r0, r1, #0xa5 << 2 - orr r0, r1, #0xa5 << 1 - -add_sub: - @ Should be format 1, Some have equivalent format 2 encodings - adds r0, r0, #0 - adds r5, r0, #0 - adds r0, r5, #0 - adds r0, r2, #5 - - adds r0, #129 @ format 2 - adds r0, r0, #129 - adds r5, #126 - - adds r0, r0, r0 @ format 3 - adds r5, r0, r0 - adds r0, r5, r0 - adds r0, r0, r5 - adds r1, r2, r3 - - add r8, r0 @ format 4 - add r0, r8 - add r0, r8, r0 - add r0, r0, r8 - add r8, r0, r0 @ ... not this one - - add r1, r0 - add r0, r1 - - add r0, pc, #0 @ format 5 - add r5, pc, #0 - add r0, pc, #516 - - add r0, sp, #0 @ format 6 - add r5, sp, #0 - add r0, sp, #516 - - add sp, #0 @ format 7 - add sp, sp, #0 - add sp, #260 - - add.w r0, r0, #0 @ T32 format 1 - adds.w r0, r0, #0 - add.w r9, r0, #0 - add.w r0, r9, #0 - add.w r0, r0, #129 - adds r5, r3, #0x10000 - add r0, sp, #1 - add r9, sp, #0 - add.w sp, sp, #4 - - add.w r0, r0, r0 @ T32 format 2 - adds.w r0, r0, r0 - add.w r9, r0, r0 - add.w r0, r9, r0 - add.w r0, r0, r9 - - add.w r8, r9, r10 - add.w r8, r9, r10, lsl #17 - add.w r8, r8, r10, lsr #32 - add.w r8, r8, r10, lsr #17 - add.w r8, r9, r10, asr #32 - add.w r8, r9, r10, asr #17 - add.w r8, r9, r10, rrx - add.w r8, r9, r10, ror #17 - - subs r0, r0, #0 @ format 1 - subs r5, r0, #0 - subs r0, r5, #0 - subs r0, r2, #5 - - subs r0, r0, #129 - subs r5, #8 - - subs r0, r0, r0 @ format 3 - subs r5, r0, r0 - subs r0, r5, r0 - subs r0, r0, r5 - - sub sp, #260 @ format 4 - sub sp, sp, #260 - - subs r8, r0 @ T32 format 2 - subs r0, r8 - subs r0, #260 @ T32 format 1 - subs.w r1, r2, #4 - subs r5, r3, #0x10000 - sub r1, sp, #4 - sub r9, sp, #0 - sub.w sp, sp, #4 - -arit3: - .macro arit3 op ops opw opsw - \ops r0, r0 - \ops r5, r0 - \ops r0, r5 - \ops r0, r0, r5 - \ops r0, r5, r0 - \op r0, r5, r0 - \op r0, r1, r2 - \op r9, r0, r0 - \op r0, r9, r0 - \op r0, r0, r9 - \opsw r0, r0, r0 - \opw r0, r1, r2, asr #17 - \opw r0, r1, #129 - .endm - - arit3 adc adcs adc.w adcs.w - arit3 and ands and.w ands.w - arit3 bic bics bic.w bics.w - arit3 eor eors eor.w eors.w - arit3 orr orrs orr.w orrs.w - arit3 rsb rsbs rsb.w rsbs.w - arit3 sbc sbcs sbc.w sbcs.w - - .purgem arit3 - -bfc_bfi_bfx: - bfc r0, #0, #1 - bfc r9, #0, #1 - bfi r9, #0, #0, #1 - bfc r0, #21, #1 - bfc r0, #0, #18 - - bfi r0, r0, #0, #1 - bfi r9, r0, #0, #1 - bfi r0, r9, #0, #1 - bfi r0, r0, #21, #1 - bfi r0, r0, #0, #18 - - sbfx r0, r0, #0, #1 - ubfx r9, r0, #0, #1 - sbfx r0, r9, #0, #1 - ubfx r0, r0, #21, #1 - sbfx r0, r0, #0, #18 - - .globl branches -branches: - .macro bra op - \op 1b - \op 1f - .endm -1: - bra beq.n - bra bne.n - bra bcs.n - bra bhs.n - bra bcc.n - bra bul.n - bra blo.n - bra bmi.n - bra bpl.n - bra bvs.n - bra bvc.n - bra bhi.n - bra bls.n - bra bvc.n - bra bhi.n - bra bls.n - bra bge.n - bra blt.n - bra bgt.n - bra ble.n - bra bal.n - bra b.n - @ bl, blx have no short form. - .balign 4 -1: - bra beq.w - bra bne.w - bra bcs.w - bra bhs.w - bra bcc.w - bra bul.w - bra blo.w - bra bmi.w - bra bpl.w - bra bvs.w - bra bvc.w - bra bhi.w - bra bls.w - bra bvc.w - bra bhi.w - bra bls.w - bra bge.w - bra blt.w - bra bgt.w - bra ble.w - bra b.w - bra bl - bra blx - .balign 4 -1: - bx r9 - blx r0 - blx r9 - bxj r0 - bxj r9 - .purgem bra - -clz: - clz r0, r0 - clz r9, r0 - clz r0, r9 - -cps: - cpsie f - cpsid i - cpsie a - cpsid.w f - cpsie.w i - cpsid.w a - cpsie i, #0 - cpsid i, #17 - cps #0 - cps #17 - -cpy: - cpy r0, r0 - cpy r9, r0 - cpy r0, r9 - cpy.w r0, r0 - cpy.w r9, r0 - cpy.w r0, r9 - -czb: - cbnz r0, 2f - cbz r5, 1f - -nop_hint: - nop -1: yield -2: wfe - wfi - sev - - nop.w - yield.w - wfe.w - wfi.w - sev.w - - nop {9} - nop {129} - -it: - .macro nop1 cond ncond a - .ifc \a,t - nop\cond - .else - nop\ncond - .endif - .endm - .macro it0 cond m= - it\m \cond - nop\cond - .endm - .macro it1 cond ncond a m= - it0 \cond \a\m - nop1 \cond \ncond \a - .endm - .macro it2 cond ncond a b m= - it1 \cond \ncond \a \b\m - nop1 \cond \ncond \b - .endm - .macro it3 cond ncond a b c - it2 \cond \ncond \a \b \c - nop1 \cond \ncond \c - .endm - - it0 eq - it0 ne - it0 cs - it0 hs - it0 cc - it0 ul - it0 lo - it0 mi - it0 pl - it0 vs - it0 vc - it0 hi - it0 ge - it0 lt - it0 gt - it0 le - it0 al - it1 eq ne t - it1 eq ne e - it2 eq ne t t - it2 eq ne e t - it2 eq ne t e - it2 eq ne e e - it3 eq ne t t t - it3 eq ne e t t - it3 eq ne t e t - it3 eq ne t t e - it3 eq ne t e e - it3 eq ne e t e - it3 eq ne e e t - it3 eq ne e e e - - it1 ne eq t - it1 ne eq e - it2 ne eq t t - it2 ne eq e t - it2 ne eq t e - it2 ne eq e e - it3 ne eq t t t - it3 ne eq e t t - it3 ne eq t e t - it3 ne eq t t e - it3 ne eq t e e - it3 ne eq e t e - it3 ne eq e e t - it3 ne eq e e e - -ldst: -1: - pld [r5] - pld [r5, #0x330] - pld [r5, #-0x30] - pld [r5], #0x30 - pld [r5], #-0x30 - pld [r5, #0x30]! - pld [r5, #-0x30]! - pld [r5, r4] - pld [r9, ip] - pld 1f - pld 1b -1: - - ldrd r2, r3, [r5] - ldrd r2, [r5, #0x30] - ldrd r2, [r5, #-0x30] - strd r2, r3, [r5] - strd r2, [r5, #0x30] - strd r2, [r5, #-0x30] - - ldrbt r1, [r5] - ldrbt r1, [r5, #0x30] - ldrsbt r1, [r5] - ldrsbt r1, [r5, #0x30] - ldrht r1, [r5] - ldrht r1, [r5, #0x30] - ldrsht r1, [r5] - ldrsht r1, [r5, #0x30] - ldrt r1, [r5] - ldrt r1, [r5, #0x30] - -ldxstx: - ldrexb r1, [r4] - ldrexh r1, [r4] - ldrex r1, [r4] - ldrexd r1, r2, [r4] - - strexb r1, r2, [r4] - strexh r1, r2, [r4] - strex r1, r2, [r4] - strexd r1, r2, r3, [r4] - - ldrex r1, [r4,#516] - strex r1, r2, [r4,#516] - -ldmstm: - ldmia r0!, {r1,r2,r3} - ldmia r2, {r0,r1,r2} - ldmia.w r2, {r0,r1,r2} - ldmia r9, {r0,r1,r2} - ldmia r0, {r7,r8,r10} - ldmia r0!, {r7,r8,r10} - - stmia r0!, {r1,r2,r3} - stmia r2!, {r0,r1,r3} - stmia.w r2!, {r0,r1,r3} - stmia r9, {r0,r1,r2} - stmia r0, {r7,r8,r10} - stmia r0!, {r7,r8,r10} - - ldmdb r0, {r7,r8,r10} - stmdb r0, {r7,r8,r10} - -mlas: - mla r0, r0, r0, r0 - mls r0, r0, r0, r0 - mla r9, r0, r0, r0 - mla r0, r9, r0, r0 - mla r0, r0, r9, r0 - mla r0, r0, r0, r9 - -tst_teq_cmp_cmn_mov_mvn: - .macro mt op ops opw opsw - \ops r0, r0 - \op r0, r0 - \ops r5, r0 - \op r0, r5 - \op r0, r5, asr #17 - \opw r0, r0 - \ops r9, r0 - \opsw r0, r9 - \opw r0, #129 - \opw r5, #129 - .endm - - mt tst tsts tst.w tsts.w - mt teq teqs teq.w teqs.w - mt cmp cmps cmp.w cmps.w - mt cmn cmns cmn.w cmns.w - mt mov movs mov.w movs.w - mt mvn mvns mvn.w mvns.w - .purgem mt - -mov16: - movw r0, #0 - movt r0, #0 - movw r9, #0 - movw r0, #0x9000 - movw r0, #0x0800 - movw r0, #0x0500 - movw r0, #0x0081 - movw r0, #0xffff - -mrs_msr: - mrs r0, CPSR - mrs r0, SPSR - mrs r9, CPSR_all - mrs r9, SPSR_all - - msr CPSR_c, r0 - msr SPSR_c, r0 - msr CPSR_c, r9 - msr CPSR_x, r0 - msr CPSR_s, r0 - msr CPSR_f, r0 - -mul: - mul r0, r0, r0 - mul r0, r9, r0 - mul r0, r0, r9 - mul r0, r0 - mul r9, r0 - muls r5, r0 - muls r5, r0, r5 - muls r0, r5 - -mull: - smull r0, r1, r0, r0 - umull r0, r1, r0, r0 - smlal r0, r1, r0, r0 - umlal r0, r1, r0, r0 - smull r9, r0, r0, r0 - smull r0, r9, r0, r0 - smull r0, r1, r9, r0 - smull r0, r1, r0, r9 - -neg: - negs r0, r0 - negs r0, r5 - negs r5, r0 - negs.w r0, r0 - negs.w r5, r0 - negs.w r0, r5 - - neg r0, r9 - neg r9, r0 - negs r0, r9 - negs r9, r0 - -pkh: - pkhbt r0, r0, r0 - pkhbt r9, r0, r0 - pkhbt r0, r9, r0 - pkhbt r0, r0, r9 - pkhbt r0, r0, r0, lsl #0x14 - pkhbt r0, r0, r0, lsl #3 - pkhtb r1, r2, r3 - pkhtb r1, r2, r3, asr #0x11 - -push_pop: - push {r0} - pop {r0} - push {r1,lr} - pop {r1,pc} - push {r8,r9,r10,r11,r12} - pop {r8,r9,r10,r11,r12} - -qadd: - qadd16 r1, r2, r3 - qadd8 r1, r2, r3 - qaddsubx r1, r2, r3 - qsub16 r1, r2, r3 - qsub8 r1, r2, r3 - qsubaddx r1, r2, r3 - sadd16 r1, r2, r3 - sadd8 r1, r2, r3 - saddsubx r1, r2, r3 - ssub16 r1, r2, r3 - ssub8 r1, r2, r3 - ssubaddx r1, r2, r3 - shadd16 r1, r2, r3 - shadd8 r1, r2, r3 - shaddsubx r1, r2, r3 - shsub16 r1, r2, r3 - shsub8 r1, r2, r3 - shsubaddx r1, r2, r3 - uadd16 r1, r2, r3 - uadd8 r1, r2, r3 - uaddsubx r1, r2, r3 - usub16 r1, r2, r3 - usub8 r1, r2, r3 - usubaddx r1, r2, r3 - uhadd16 r1, r2, r3 - uhadd8 r1, r2, r3 - uhaddsubx r1, r2, r3 - uhsub16 r1, r2, r3 - uhsub8 r1, r2, r3 - uhsubaddx r1, r2, r3 - uqadd16 r1, r2, r3 - uqadd8 r1, r2, r3 - uqaddsubx r1, r2, r3 - uqsub16 r1, r2, r3 - uqsub8 r1, r2, r3 - uqsubaddx r1, r2, r3 - sel r1, r2, r3 - -rbit_rev: - .macro rx op opw - \op r0, r0 - \opw r0, r0 - \op r0, r5 - \op r5, r0 - \op r0, r9 - \op r9, r0 - .endm - - rx rev rev.w - rx rev16 rev16.w - rx revsh revsh.w - rx rbit rbit.w - - .purgem rx - -shift: - .macro sh op ops opw opsw - \ops r0, #17 @ 16-bit format 1 - \ops r0, r0, #14 - \ops r5, r0, #17 - \ops r0, r5, #14 - \ops r0, r0 @ 16-bit format 2 - \ops r0, r5 - \ops r0, r0, r5 - \op r9, #17 @ 32-bit format 1 - \op r9, r9, #14 - \ops r0, r9, #17 - \op r9, r0, #14 - \opw r0, r0, r0 @ 32-bit format 2 - \op r9, r9 - \ops r9, r0 - \op r0, r9 - \op r0, r5 - \ops r0, r1, r2 - .endm - - sh lsl lsls lsl.w lsls.w - sh lsr lsrs lsr.w lsrs.w - sh asr asrs asr.w asrs.w - sh ror rors ror.w rors.w - - .purgem sh - -smc: - smc #0 - smc #0xabcd - -smla: - smlabb r0, r0, r0, r0 - smlabb r9, r0, r0, r0 - smlabb r0, r9, r0, r0 - smlabb r0, r0, r9, r0 - smlabb r0, r0, r0, r9 - - smlatb r0, r0, r0, r0 - smlabt r0, r0, r0, r0 - smlatt r0, r0, r0, r0 - smlawb r0, r0, r0, r0 - smlawt r0, r0, r0, r0 - smlad r0, r0, r0, r0 - smladx r0, r0, r0, r0 - smlsd r0, r0, r0, r0 - smlsdx r0, r0, r0, r0 - smmla r0, r0, r0, r0 - smmlar r0, r0, r0, r0 - smmls r0, r0, r0, r0 - smmlsr r0, r0, r0, r0 - usada8 r0, r0, r0, r0 - -smlal: - smlalbb r0, r0, r0, r0 - smlalbb r9, r0, r0, r0 - smlalbb r0, r9, r0, r0 - smlalbb r0, r0, r9, r0 - smlalbb r0, r0, r0, r9 - - smlaltb r0, r0, r0, r0 - smlalbt r0, r0, r0, r0 - smlaltt r0, r0, r0, r0 - smlald r0, r0, r0, r0 - smlaldx r0, r0, r0, r0 - smlsld r0, r0, r0, r0 - smlsldx r0, r0, r0, r0 - umaal r0, r0, r0, r0 - -smul: - smulbb r0, r0, r0 - smulbb r9, r0, r0 - smulbb r0, r9, r0 - smulbb r0, r0, r9 - - smultb r0, r0, r0 - smulbt r0, r0, r0 - smultt r0, r0, r0 - smulwb r0, r0, r0 - smulwt r0, r0, r0 - smmul r0, r0, r0 - smmulr r0, r0, r0 - smuad r0, r0, r0 - smuadx r0, r0, r0 - smusd r0, r0, r0 - smusdx r0, r0, r0 - usad8 r0, r0, r0 - -sat: - ssat r0, #1, r0 - ssat r0, #1, r0, lsl #0 - ssat r0, #1, r0, asr #0 - ssat r9, #1, r0 - ssat r0, #18, r0 - ssat r0, #1, r9 - ssat r0, #1, r0, lsl #0x1c - ssat r0, #1, r0, asr #0x03 - - ssat16 r0, #1, r0 - ssat16 r9, #1, r0 - ssat16 r0, #10, r0 - ssat16 r0, #1, r9 - - usat r0, #0, r0 - usat r0, #0, r0, lsl #0 - usat r0, #0, r0, asr #0 - usat r9, #0, r0 - usat r0, #17, r0 - usat r0, #0, r9 - usat r0, #0, r0, lsl #0x1c - usat r0, #0, r0, asr #0x03 - - usat16 r0, #0, r0 - usat16 r9, #0, r0 - usat16 r0, #9, r0 - usat16 r0, #0, r9 - -xt: - sxtb r0, r0 - sxtb r0, r0, ror #0 - sxtb r5, r0 - sxtb r0, r5 - sxtb.w r1, r2 - sxtb r1, r2, ror #8 - sxtb r1, r2, ror #16 - sxtb r1, r2, ror #24 - - sxtb16 r1, r2 - sxtb16 r8, r9 - sxth r1, r2 - sxth r8, r9 - uxtb r1, r2 - uxtb r8, r9 - uxtb16 r1, r2 - uxtb16 r8, r9 - uxth r1, r2 - uxth r8, r9 - -xta: - sxtab r0, r0, r0 - sxtab r0, r0, r0, ror #0 - sxtab r9, r0, r0, ror #8 - sxtab r0, r9, r0, ror #16 - sxtab r0, r0, r9, ror #24 - - sxtab16 r1, r2, r3 - sxtah r1, r2, r3 - uxtab r1, r2, r3 - uxtab16 r1, r2, r3 - uxtah r1, r2, r3 - - .macro ldpcimm op - \op r1, [pc, #0x2aa] - \op r1, [pc, #0x155] - \op r1, [pc, #-0x2aa] - \op r1, [pc, #-0x155] - .endm - ldpcimm ldrb - ldpcimm ldrsb - ldpcimm ldrh - ldpcimm ldrsh - ldpcimm ldr - addw r9, r0, #0 - addw r6, pc, #0xfff - subw r6, r9, #0xa85 - subw r6, r9, #0x57a - tbb [pc, r6] - tbb [r0, r9] - tbh [pc, r7, lsl #1] - tbh [r0, r8, lsl #1] - - push {r8} - pop {r8} - - ldmdb r0!, {r7,r8,r10} - stmdb r0!, {r7,r8,r10} - - ldm r0!, {r1, r2} - stm r0!, {r1, r2} - ldm r0, {r8, r9} - stm r0, {r8, r9} - itttt eq - ldmeq r0!, {r1, r2} - stmeq r0!, {r1, r2} - ldmeq r0, {r8, r9} - stmeq r0, {r8, r9} - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumbv6.d b/binutils-2.17/gas/testsuite/gas/arm/thumbv6.d deleted file mode 100644 index 5dc82145..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumbv6.d +++ /dev/null @@ -1,23 +0,0 @@ -#name: THUMB V6 instructions -#as: -march=armv6j -mthumb -#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> b666 * cpsie ai -0+002 <[^>]*> b675 * cpsid af -0+004 <[^>]*> 4623 * mov r3, r4 -0+006 <[^>]*> ba3a * rev r2, r7 -0+008 <[^>]*> ba4d * rev16 r5, r1 -0+00a <[^>]*> baf3 * revsh r3, r6 -0+00c <[^>]*> b658 * setend be -0+00e <[^>]*> b650 * setend le -0+010 <[^>]*> b208 * sxth r0, r1 -0+012 <[^>]*> b251 * sxtb r1, r2 -0+014 <[^>]*> b2a3 * uxth r3, r4 -0+016 <[^>]*> b2f5 * uxtb r5, r6 -0+018 <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) -0+01a <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) -0+01c <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) -0+01e <[^>]*> 46c0 * nop[ ]+\(mov r8, r8\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumbv6.s b/binutils-2.17/gas/testsuite/gas/arm/thumbv6.s deleted file mode 100644 index a4049750..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumbv6.s +++ /dev/null @@ -1,24 +0,0 @@ -.text -.align 0 - -.thumb -label: - cpsie ia - cpsid af - cpy r3, r4 - rev r2, r7 - rev16 r5, r1 - revsh r3, r6 - setend be - setend le - sxth r0, r1 - sxtb r1, r2 - uxth r3, r4 - uxtb r5, r6 - - # Add four nop instructions to ensure that the output is - # 32-byte aligned as required for arm-aout. - nop - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumbv6k.d b/binutils-2.17/gas/testsuite/gas/arm/thumbv6k.d deleted file mode 100644 index 54a1d31c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumbv6k.d +++ /dev/null @@ -1,15 +0,0 @@ -#name: THUMB V6K instructions -#as: -march=armv6k -mthumb -#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> bf10 * yield -0+002 <[^>]*> bf20 * wfe -0+004 <[^>]*> bf30 * wfi -0+006 <[^>]*> bf40 * sev -0+008 <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) -0+00a <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) -0+00c <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) -0+00e <[^>]*> 46c0 * nop[ \t]+\(mov r8, r8\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/thumbv6k.s b/binutils-2.17/gas/testsuite/gas/arm/thumbv6k.s deleted file mode 100644 index 86198432..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/thumbv6k.s +++ /dev/null @@ -1,14 +0,0 @@ - .text - .align 0 - .thumb -label: - yield - wfe - wfi - sev - # arm-aout wants the segment padded to an 16-byte boundary; - # do this explicitly so it's consistent for all object formats. - nop - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/tls.d b/binutils-2.17/gas/testsuite/gas/arm/tls.d deleted file mode 100644 index 5b411092..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tls.d +++ /dev/null @@ -1,25 +0,0 @@ -#objdump: -dr -#name: TLS -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -# VxWorks needs a special variant of this file. -#skip: *-*-vxworks* - -# Test generation of TLS relocations - -.*: +file format .*arm.* - -Disassembly of section .text: - -00+0 <main>: - 0: e1a00000 nop \(mov r0,r0\) - 4: e1a00000 nop \(mov r0,r0\) - 8: e1a0f00e mov pc, lr - c: 00000000 andeq r0, r0, r0 - c: R_ARM_TLS_GD32 a - 10: 00000004 andeq r0, r0, r4 - 10: R_ARM_TLS_LDM32 b - 14: 00000008 andeq r0, r0, r8 - 14: R_ARM_TLS_IE32 c - 18: 00000000 andeq r0, r0, r0 - 18: R_ARM_TLS_LE32 d diff --git a/binutils-2.17/gas/testsuite/gas/arm/tls.s b/binutils-2.17/gas/testsuite/gas/arm/tls.s deleted file mode 100644 index 48722a42..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tls.s +++ /dev/null @@ -1,14 +0,0 @@ - .text - .globl main - .type main, %function -main: - nop -.L2: - nop - mov pc, lr - -.Lpool: - .word a(tlsgd) + (. - .L2 - 8) - .word b(tlsldm) + (. - .L2 - 8) - .word c(gottpoff) + (. - .L2 - 8) - .word d(tpoff) diff --git a/binutils-2.17/gas/testsuite/gas/arm/tls_vxworks.d b/binutils-2.17/gas/testsuite/gas/arm/tls_vxworks.d deleted file mode 100644 index ec80e652..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/tls_vxworks.d +++ /dev/null @@ -1,30 +0,0 @@ -#objdump: -dr -#name: TLS -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -# This is the VxWorks variant of this file. -#source: tls.s -#not-skip: *-*-vxworks* - -# Test generation of TLS relocations - -.*: +file format .*arm.* - -Disassembly of section .text: - -00+0 <main>: - 0: e1a00000 nop \(mov r0,r0\) - 4: e1a00000 nop \(mov r0,r0\) - 8: e1a0f00e mov pc, lr - c: 00000000 andeq r0, r0, r0 - c: R_ARM_TLS_GD32 a -# ??? The addend is appearing in both the RELA field and the -# contents. Shouldn't it be just one? bfd_install_relocation -# appears to write the addend into the contents unconditionally, -# yet somehow this does not happen for the majority of relocations. - 10: 00000004 andeq r0, r0, r4 - 10: R_ARM_TLS_LDM32 b\+0x4 - 14: 00000008 andeq r0, r0, r8 - 14: R_ARM_TLS_IE32 c\+0x8 - 18: 00000000 andeq r0, r0, r0 - 18: R_ARM_TLS_LE32 d diff --git a/binutils-2.17/gas/testsuite/gas/arm/undefined.d b/binutils-2.17/gas/testsuite/gas/arm/undefined.d deleted file mode 100644 index 6a614956..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/undefined.d +++ /dev/null @@ -1,4 +0,0 @@ -#name: Undefined local label error -# COFF and aout based ports use a different naming convention for local labels. -#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -#error-output: undefined.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/undefined.l b/binutils-2.17/gas/testsuite/gas/arm/undefined.l deleted file mode 100644 index 89cfa041..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/undefined.l +++ /dev/null @@ -1,2 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:1: Error: undefined local label `\.Lval' diff --git a/binutils-2.17/gas/testsuite/gas/arm/undefined.s b/binutils-2.17/gas/testsuite/gas/arm/undefined.s deleted file mode 100644 index f7b76d7d..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/undefined.s +++ /dev/null @@ -1 +0,0 @@ - ldr a1, .Lval diff --git a/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.d b/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.d deleted file mode 100644 index ab0bbcdc..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.d +++ /dev/null @@ -1,4 +0,0 @@ -#name: Undefined local label error -# COFF and aout based ports use a different naming convention for local labels. -#not-skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -#error-output: undefined_coff.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.l b/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.l deleted file mode 100644 index 1bd8dcfc..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.l +++ /dev/null @@ -1,2 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:1: Error: undefined local label `Lval' diff --git a/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.s b/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.s deleted file mode 100644 index dd18dad2..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/undefined_coff.s +++ /dev/null @@ -1 +0,0 @@ - ldr a1, Lval diff --git a/binutils-2.17/gas/testsuite/gas/arm/unwind.d b/binutils-2.17/gas/testsuite/gas/arm/unwind.d deleted file mode 100644 index cd4a7c79..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/unwind.d +++ /dev/null @@ -1,42 +0,0 @@ -#objdump: -sr -#name: Unwind table generation -# This test is only valid on ELF based ports. -#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* -# VxWorks needs a special variant of this file. -#skip: *-*-vxworks* - -.*: file format.* - -RELOCATION RECORDS FOR \[.ARM.extab\]: -OFFSET TYPE VALUE -0000000c R_ARM_PREL31 .text - - -RELOCATION RECORDS FOR \[.ARM.exidx\]: -OFFSET TYPE VALUE -00000000 R_ARM_PREL31 .text -00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0 -00000008 R_ARM_PREL31 .text.* -00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1 -0000000c R_ARM_PREL31 .ARM.extab -00000010 R_ARM_PREL31 .text.* -00000014 R_ARM_PREL31 .ARM.extab.* -00000018 R_ARM_PREL31 .text.* -0000001c R_ARM_PREL31 .ARM.extab.* -00000020 R_ARM_PREL31 .text.* -00000028 R_ARM_PREL31 .text.* - - -Contents of section .text: - 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* - 0010 (04200520|20052004) .* -Contents of section .ARM.extab: - 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* - 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* - 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* -Contents of section .ARM.exidx: - 0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000 .* - 0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c) .* - 0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0) .* -# Ignore .ARM.attributes section -#... diff --git a/binutils-2.17/gas/testsuite/gas/arm/unwind.s b/binutils-2.17/gas/testsuite/gas/arm/unwind.s deleted file mode 100644 index 7d0f1269..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/unwind.s +++ /dev/null @@ -1,51 +0,0 @@ -# Test generation of unwind tables - .text -foo: @ Simple function - .fnstart - .save {r4, lr} - mov r0, #0 - .fnend -foo1: @ Typical frame pointer prologue - .fnstart - .movsp ip - @mov ip, sp - .pad #4 - .save {fp, ip, lr} - @stmfd sp!, {fp, ip, lr, pc} - .setfp fp, ip, #4 - @sub fp, ip, #4 - mov r0, #1 - .fnend -foo2: @ Custom personality routine - .fnstart - .save {r1, r4, r6, lr} - @stmfd {r1, r4, r6, lr} - mov r0, #2 - .personality foo - .handlerdata - .word 42 - .fnend -foo3: @ Saving iwmmxt registers - .fnstart - .save {wr11} - .save {wr10} - .save {wr10, wr11} - .save {wr0} - mov r0, #3 - .fnend - .code 16 -foo4: @ Thumb frame pointer - .fnstart - .save {r7, lr} - @push {r7, lr} - .setfp r7, sp - @mov r7, sp - .pad #8 - @sub sp, sp, #8 - mov r0, #4 - .fnend -foo5: @ Save r0-r3 only. - .fnstart - .save {r0, r1, r2, r3} - mov r0, #5 - .fnend diff --git a/binutils-2.17/gas/testsuite/gas/arm/unwind_vxworks.d b/binutils-2.17/gas/testsuite/gas/arm/unwind_vxworks.d deleted file mode 100644 index ccd16a65..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/unwind_vxworks.d +++ /dev/null @@ -1,41 +0,0 @@ -#objdump: -sr -#name: Unwind table generation -# This is the VxWorks variant of this file. -#source: unwind.s -#not-skip: *-*-vxworks* - -.*: file format.* - -RELOCATION RECORDS FOR \[.ARM.extab\]: -OFFSET TYPE VALUE -0000000c R_ARM_PREL31 .text - - -RELOCATION RECORDS FOR \[.ARM.exidx\]: -OFFSET TYPE VALUE -00000000 R_ARM_PREL31 .text -00000000 R_ARM_NONE __aeabi_unwind_cpp_pr0 -00000008 R_ARM_PREL31 .text.*\+0x00000004 -00000008 R_ARM_NONE __aeabi_unwind_cpp_pr1 -0000000c R_ARM_PREL31 .ARM.extab -00000010 R_ARM_PREL31 .text.*\+0x00000008 -00000014 R_ARM_PREL31 .ARM.extab.*\+0x0000000c -00000018 R_ARM_PREL31 .text.*\+0x0000000c -0000001c R_ARM_PREL31 .ARM.extab.*\+0x0000001c -00000020 R_ARM_PREL31 .text.*\+0x00000010 -00000028 R_ARM_PREL31 .text.*\+0x00000012 - - -Contents of section .text: - 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003) .* - 0010 (04200520|20052004) .* -Contents of section .ARM.extab: - 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000 .* - 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600) .* - 0020 (b0b0c1c1|c1c1b0b0) 00000000 .* -Contents of section .ARM.exidx: - 0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000 .* - 0010 00000000 00000000 00000000 00000000 .* - 0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0) .* -# Ignore .ARM.attributes section -#... diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.d b/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.d deleted file mode 100644 index 760c4d5c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: VFP errors -#as: -mfpu=vfp -#error-output: vfp-bad.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.l b/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.l deleted file mode 100644 index 7726e631..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.l +++ /dev/null @@ -1,9 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:4: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8' -[^:]*:5: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!' -[^:]*:6: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8' -[^:]*:7: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!' -[^:]*:8: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8' -[^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!' -[^:]*:10: Error: instruction does not support writeback -- `flds s0,\[r0\],#8' -[^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!' diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.s b/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.s deleted file mode 100644 index ac443717..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad.s +++ /dev/null @@ -1,11 +0,0 @@ - .global entry - .text -entry: - fstd d0, [r0], #8 - fstd d0, [r0, #-8]! - fsts s0, [r0], #8 - fsts s0, [r0, #-8]! - fldd d0, [r0], #8 - fldd d0, [r0, #-8]! - flds s0, [r0], #8 - flds s0, [r0, #-8]! diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.d b/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.d deleted file mode 100644 index 1ef83bab..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.d +++ /dev/null @@ -1,3 +0,0 @@ -#name: Thumb-2 VFP errors -#as: -mfpu=vfp -#error-output: vfp-bad_t2.l diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.l b/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.l deleted file mode 100644 index ecc0640b..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.l +++ /dev/null @@ -1,9 +0,0 @@ -[^:]*: Assembler messages: -[^:]*:7: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8' -[^:]*:8: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!' -[^:]*:9: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8' -[^:]*:10: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!' -[^:]*:11: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8' -[^:]*:12: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!' -[^:]*:13: Error: instruction does not support writeback -- `flds s0,\[r0\],#8' -[^:]*:14: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!' diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.s b/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.s deleted file mode 100644 index 3b904b36..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp-bad_t2.s +++ /dev/null @@ -1,14 +0,0 @@ - .global entry -@ Same as vfp-bad.s, but for Thumb-2 - .syntax unified - .thumb - .text -entry: - fstd d0, [r0], #8 - fstd d0, [r0, #-8]! - fsts s0, [r0], #8 - fsts s0, [r0, #-8]! - fldd d0, [r0], #8 - fldd d0, [r0, #-8]! - flds s0, [r0], #8 - flds s0, [r0, #-8]! diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1.d b/binutils-2.17/gas/testsuite/gas/arm/vfp1.d deleted file mode 100644 index 672b23de..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1.d +++ /dev/null @@ -1,193 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: VFP Double-precision instructions -#as: -mfpu=vfp - -# Test the ARM VFP Double Precision instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> eeb40bc0 fcmped d0, d0 -0+004 <[^>]*> eeb50bc0 fcmpezd d0 -0+008 <[^>]*> eeb40b40 fcmpd d0, d0 -0+00c <[^>]*> eeb50b40 fcmpzd d0 -0+010 <[^>]*> eeb00bc0 fabsd d0, d0 -0+014 <[^>]*> eeb00b40 fcpyd d0, d0 -0+018 <[^>]*> eeb10b40 fnegd d0, d0 -0+01c <[^>]*> eeb10bc0 fsqrtd d0, d0 -0+020 <[^>]*> ee300b00 faddd d0, d0, d0 -0+024 <[^>]*> ee800b00 fdivd d0, d0, d0 -0+028 <[^>]*> ee000b00 fmacd d0, d0, d0 -0+02c <[^>]*> ee100b00 fmscd d0, d0, d0 -0+030 <[^>]*> ee200b00 fmuld d0, d0, d0 -0+034 <[^>]*> ee000b40 fnmacd d0, d0, d0 -0+038 <[^>]*> ee100b40 fnmscd d0, d0, d0 -0+03c <[^>]*> ee200b40 fnmuld d0, d0, d0 -0+040 <[^>]*> ee300b40 fsubd d0, d0, d0 -0+044 <[^>]*> ed900b00 fldd d0, \[r0\] -0+048 <[^>]*> ed800b00 fstd d0, \[r0\] -0+04c <[^>]*> ec900b02 fldmiad r0, {d0} -0+050 <[^>]*> ec900b02 fldmiad r0, {d0} -0+054 <[^>]*> ecb00b02 fldmiad r0!, {d0} -0+058 <[^>]*> ecb00b02 fldmiad r0!, {d0} -0+05c <[^>]*> ed300b02 fldmdbd r0!, {d0} -0+060 <[^>]*> ed300b02 fldmdbd r0!, {d0} -0+064 <[^>]*> ec800b02 fstmiad r0, {d0} -0+068 <[^>]*> ec800b02 fstmiad r0, {d0} -0+06c <[^>]*> eca00b02 fstmiad r0!, {d0} -0+070 <[^>]*> eca00b02 fstmiad r0!, {d0} -0+074 <[^>]*> ed200b02 fstmdbd r0!, {d0} -0+078 <[^>]*> ed200b02 fstmdbd r0!, {d0} -0+07c <[^>]*> eeb80bc0 fsitod d0, s0 -0+080 <[^>]*> eeb80b40 fuitod d0, s0 -0+084 <[^>]*> eebd0b40 ftosid s0, d0 -0+088 <[^>]*> eebd0bc0 ftosizd s0, d0 -0+08c <[^>]*> eebc0b40 ftouid s0, d0 -0+090 <[^>]*> eebc0bc0 ftouizd s0, d0 -0+094 <[^>]*> eeb70ac0 fcvtds d0, s0 -0+098 <[^>]*> eeb70bc0 fcvtsd s0, d0 -0+09c <[^>]*> ee300b10 fmrdh r0, d0 -0+0a0 <[^>]*> ee100b10 fmrdl r0, d0 -0+0a4 <[^>]*> ee200b10 fmdhr d0, r0 -0+0a8 <[^>]*> ee000b10 fmdlr d0, r0 -0+0ac <[^>]*> eeb51b40 fcmpzd d1 -0+0b0 <[^>]*> eeb52b40 fcmpzd d2 -0+0b4 <[^>]*> eeb5fb40 fcmpzd d15 -0+0b8 <[^>]*> eeb40b41 fcmpd d0, d1 -0+0bc <[^>]*> eeb40b42 fcmpd d0, d2 -0+0c0 <[^>]*> eeb40b4f fcmpd d0, d15 -0+0c4 <[^>]*> eeb41b40 fcmpd d1, d0 -0+0c8 <[^>]*> eeb42b40 fcmpd d2, d0 -0+0cc <[^>]*> eeb4fb40 fcmpd d15, d0 -0+0d0 <[^>]*> eeb45b4c fcmpd d5, d12 -0+0d4 <[^>]*> eeb10b41 fnegd d0, d1 -0+0d8 <[^>]*> eeb10b42 fnegd d0, d2 -0+0dc <[^>]*> eeb10b4f fnegd d0, d15 -0+0e0 <[^>]*> eeb11b40 fnegd d1, d0 -0+0e4 <[^>]*> eeb12b40 fnegd d2, d0 -0+0e8 <[^>]*> eeb1fb40 fnegd d15, d0 -0+0ec <[^>]*> eeb1cb45 fnegd d12, d5 -0+0f0 <[^>]*> ee300b01 faddd d0, d0, d1 -0+0f4 <[^>]*> ee300b02 faddd d0, d0, d2 -0+0f8 <[^>]*> ee300b0f faddd d0, d0, d15 -0+0fc <[^>]*> ee310b00 faddd d0, d1, d0 -0+100 <[^>]*> ee320b00 faddd d0, d2, d0 -0+104 <[^>]*> ee3f0b00 faddd d0, d15, d0 -0+108 <[^>]*> ee301b00 faddd d1, d0, d0 -0+10c <[^>]*> ee302b00 faddd d2, d0, d0 -0+110 <[^>]*> ee30fb00 faddd d15, d0, d0 -0+114 <[^>]*> ee39cb05 faddd d12, d9, d5 -0+118 <[^>]*> eeb70ae0 fcvtds d0, s1 -0+11c <[^>]*> eeb70ac1 fcvtds d0, s2 -0+120 <[^>]*> eeb70aef fcvtds d0, s31 -0+124 <[^>]*> eeb71ac0 fcvtds d1, s0 -0+128 <[^>]*> eeb72ac0 fcvtds d2, s0 -0+12c <[^>]*> eeb7fac0 fcvtds d15, s0 -0+130 <[^>]*> eef70bc0 fcvtsd s1, d0 -0+134 <[^>]*> eeb71bc0 fcvtsd s2, d0 -0+138 <[^>]*> eef7fbc0 fcvtsd s31, d0 -0+13c <[^>]*> eeb70bc1 fcvtsd s0, d1 -0+140 <[^>]*> eeb70bc2 fcvtsd s0, d2 -0+144 <[^>]*> eeb70bcf fcvtsd s0, d15 -0+148 <[^>]*> ee301b10 fmrdh r1, d0 -0+14c <[^>]*> ee30eb10 fmrdh lr, d0 -0+150 <[^>]*> ee310b10 fmrdh r0, d1 -0+154 <[^>]*> ee320b10 fmrdh r0, d2 -0+158 <[^>]*> ee3f0b10 fmrdh r0, d15 -0+15c <[^>]*> ee101b10 fmrdl r1, d0 -0+160 <[^>]*> ee10eb10 fmrdl lr, d0 -0+164 <[^>]*> ee110b10 fmrdl r0, d1 -0+168 <[^>]*> ee120b10 fmrdl r0, d2 -0+16c <[^>]*> ee1f0b10 fmrdl r0, d15 -0+170 <[^>]*> ee201b10 fmdhr d0, r1 -0+174 <[^>]*> ee20eb10 fmdhr d0, lr -0+178 <[^>]*> ee210b10 fmdhr d1, r0 -0+17c <[^>]*> ee220b10 fmdhr d2, r0 -0+180 <[^>]*> ee2f0b10 fmdhr d15, r0 -0+184 <[^>]*> ee001b10 fmdlr d0, r1 -0+188 <[^>]*> ee00eb10 fmdlr d0, lr -0+18c <[^>]*> ee010b10 fmdlr d1, r0 -0+190 <[^>]*> ee020b10 fmdlr d2, r0 -0+194 <[^>]*> ee0f0b10 fmdlr d15, r0 -0+198 <[^>]*> ed910b00 fldd d0, \[r1\] -0+19c <[^>]*> ed9e0b00 fldd d0, \[lr\] -0+1a0 <[^>]*> ed900b00 fldd d0, \[r0\] -0+1a4 <[^>]*> ed900bff fldd d0, \[r0, #1020\] -0+1a8 <[^>]*> ed100bff fldd d0, \[r0, #-1020\] -0+1ac <[^>]*> ed901b00 fldd d1, \[r0\] -0+1b0 <[^>]*> ed902b00 fldd d2, \[r0\] -0+1b4 <[^>]*> ed90fb00 fldd d15, \[r0\] -0+1b8 <[^>]*> ed8ccbc9 fstd d12, \[ip, #804\] -0+1bc <[^>]*> ec901b02 fldmiad r0, {d1} -0+1c0 <[^>]*> ec902b02 fldmiad r0, {d2} -0+1c4 <[^>]*> ec90fb02 fldmiad r0, {d15} -0+1c8 <[^>]*> ec900b04 fldmiad r0, {d0-d1} -0+1cc <[^>]*> ec900b06 fldmiad r0, {d0-d2} -0+1d0 <[^>]*> ec900b20 fldmiad r0, {d0-d15} -0+1d4 <[^>]*> ec901b1e fldmiad r0, {d1-d15} -0+1d8 <[^>]*> ec902b1c fldmiad r0, {d2-d15} -0+1dc <[^>]*> ec90eb04 fldmiad r0, {d14-d15} -0+1e0 <[^>]*> ec910b02 fldmiad r1, {d0} -0+1e4 <[^>]*> ec9e0b02 fldmiad lr, {d0} -0+1e8 <[^>]*> eeb50b40 fcmpzd d0 -0+1ec <[^>]*> eeb51b40 fcmpzd d1 -0+1f0 <[^>]*> eeb52b40 fcmpzd d2 -0+1f4 <[^>]*> eeb53b40 fcmpzd d3 -0+1f8 <[^>]*> eeb54b40 fcmpzd d4 -0+1fc <[^>]*> eeb55b40 fcmpzd d5 -0+200 <[^>]*> eeb56b40 fcmpzd d6 -0+204 <[^>]*> eeb57b40 fcmpzd d7 -0+208 <[^>]*> eeb58b40 fcmpzd d8 -0+20c <[^>]*> eeb59b40 fcmpzd d9 -0+210 <[^>]*> eeb5ab40 fcmpzd d10 -0+214 <[^>]*> eeb5bb40 fcmpzd d11 -0+218 <[^>]*> eeb5cb40 fcmpzd d12 -0+21c <[^>]*> eeb5db40 fcmpzd d13 -0+220 <[^>]*> eeb5eb40 fcmpzd d14 -0+224 <[^>]*> eeb5fb40 fcmpzd d15 -0+228 <[^>]*> 0eb41bcf fcmpedeq d1, d15 -0+22c <[^>]*> 0eb52bc0 fcmpezdeq d2 -0+230 <[^>]*> 0eb43b4e fcmpdeq d3, d14 -0+234 <[^>]*> 0eb54b40 fcmpzdeq d4 -0+238 <[^>]*> 0eb05bcd fabsdeq d5, d13 -0+23c <[^>]*> 0eb06b4c fcpydeq d6, d12 -0+240 <[^>]*> 0eb17b4b fnegdeq d7, d11 -0+244 <[^>]*> 0eb18bca fsqrtdeq d8, d10 -0+248 <[^>]*> 0e319b0f fadddeq d9, d1, d15 -0+24c <[^>]*> 0e832b0e fdivdeq d2, d3, d14 -0+250 <[^>]*> 0e0d4b0c fmacdeq d4, d13, d12 -0+254 <[^>]*> 0e165b0b fmscdeq d5, d6, d11 -0+258 <[^>]*> 0e2a7b09 fmuldeq d7, d10, d9 -0+25c <[^>]*> 0e098b4a fnmacdeq d8, d9, d10 -0+260 <[^>]*> 0e167b4b fnmscdeq d7, d6, d11 -0+264 <[^>]*> 0e245b4c fnmuldeq d5, d4, d12 -0+268 <[^>]*> 0e3d3b4e fsubdeq d3, d13, d14 -0+26c <[^>]*> 0d952b00 flddeq d2, \[r5\] -0+270 <[^>]*> 0d8c1b00 fstdeq d1, \[ip\] -0+274 <[^>]*> 0c911b02 fldmiadeq r1, {d1} -0+278 <[^>]*> 0c922b02 fldmiadeq r2, {d2} -0+27c <[^>]*> 0cb33b02 fldmiadeq r3!, {d3} -0+280 <[^>]*> 0cb44b02 fldmiadeq r4!, {d4} -0+284 <[^>]*> 0d355b02 fldmdbdeq r5!, {d5} -0+288 <[^>]*> 0d366b02 fldmdbdeq r6!, {d6} -0+28c <[^>]*> 0c87fb02 fstmiadeq r7, {d15} -0+290 <[^>]*> 0c88eb02 fstmiadeq r8, {d14} -0+294 <[^>]*> 0ca9db02 fstmiadeq r9!, {d13} -0+298 <[^>]*> 0caacb02 fstmiadeq sl!, {d12} -0+29c <[^>]*> 0d2bbb02 fstmdbdeq fp!, {d11} -0+2a0 <[^>]*> 0d2cab02 fstmdbdeq ip!, {d10} -0+2a4 <[^>]*> 0eb8fbe0 fsitodeq d15, s1 -0+2a8 <[^>]*> 0eb81b6f fuitodeq d1, s31 -0+2ac <[^>]*> 0efd0b4f ftosideq s1, d15 -0+2b0 <[^>]*> 0efdfbc2 ftosizdeq s31, d2 -0+2b4 <[^>]*> 0efc7b42 ftouideq s15, d2 -0+2b8 <[^>]*> 0efc5bc3 ftouizdeq s11, d3 -0+2bc <[^>]*> 0eb71ac5 fcvtdseq d1, s10 -0+2c0 <[^>]*> 0ef75bc1 fcvtsdeq s11, d1 -0+2c4 <[^>]*> 0e318b10 fmrdheq r8, d1 -0+2c8 <[^>]*> 0e1f7b10 fmrdleq r7, d15 -0+2cc <[^>]*> 0e21fb10 fmdhreq d1, pc -0+2d0 <[^>]*> 0e0f1b10 fmdlreq d15, r1 -0+2d4 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+2d8 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+2dc <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1.s b/binutils-2.17/gas/testsuite/gas/arm/vfp1.s deleted file mode 100644 index 1a80877c..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1.s +++ /dev/null @@ -1,284 +0,0 @@ -@ VFP Instructions for D variants (Double precision) - .text - .global F -F: - @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use d0/r0 to avoid setting - @ any more bits than necessary. - - @ Comparison operations - - fcmped d0, d0 - fcmpezd d0 - fcmpd d0, d0 - fcmpzd d0 - - @ Monadic data operations - - fabsd d0, d0 - fcpyd d0, d0 - fnegd d0, d0 - fsqrtd d0, d0 - - @ Dyadic data operations - - faddd d0, d0, d0 - fdivd d0, d0, d0 - fmacd d0, d0, d0 - fmscd d0, d0, d0 - fmuld d0, d0, d0 - fnmacd d0, d0, d0 - fnmscd d0, d0, d0 - fnmuld d0, d0, d0 - fsubd d0, d0, d0 - - @ Load/store operations - - fldd d0, [r0] - fstd d0, [r0] - - @ Load/store multiple operations - - fldmiad r0, {d0} - fldmfdd r0, {d0} - fldmiad r0!, {d0} - fldmfdd r0!, {d0} - fldmdbd r0!, {d0} - fldmead r0!, {d0} - - fstmiad r0, {d0} - fstmead r0, {d0} - fstmiad r0!, {d0} - fstmead r0!, {d0} - fstmdbd r0!, {d0} - fstmfdd r0!, {d0} - - @ Conversion operations - - fsitod d0, s0 - fuitod d0, s0 - - ftosid s0, d0 - ftosizd s0, d0 - ftouid s0, d0 - ftouizd s0, d0 - - fcvtds d0, s0 - fcvtsd s0, d0 - - @ ARM from VFP operations - - fmrdh r0, d0 - fmrdl r0, d0 - - @ VFP From ARM operations - - fmdhr d0, r0 - fmdlr d0, r0 - - @ Now we test that the register fields are updated correctly for - @ each class of instruction. - - @ Single register operations (compare-zero): - - fcmpzd d1 - fcmpzd d2 - fcmpzd d15 - - @ Two register comparison operations: - - fcmpd d0, d1 - fcmpd d0, d2 - fcmpd d0, d15 - fcmpd d1, d0 - fcmpd d2, d0 - fcmpd d15, d0 - fcmpd d5, d12 - - @ Two register data operations (monadic) - - fnegd d0, d1 - fnegd d0, d2 - fnegd d0, d15 - fnegd d1, d0 - fnegd d2, d0 - fnegd d15, d0 - fnegd d12, d5 - - @ Three register data operations (dyadic) - - faddd d0, d0, d1 - faddd d0, d0, d2 - faddd d0, d0, d15 - faddd d0, d1, d0 - faddd d0, d2, d0 - faddd d0, d15, d0 - faddd d1, d0, d0 - faddd d2, d0, d0 - faddd d15, d0, d0 - faddd d12, d9, d5 - - @ Conversion operations - - fcvtds d0, s1 - fcvtds d0, s2 - fcvtds d0, s31 - fcvtds d1, s0 - fcvtds d2, s0 - fcvtds d15, s0 - fcvtsd s1, d0 - fcvtsd s2, d0 - fcvtsd s31, d0 - fcvtsd s0, d1 - fcvtsd s0, d2 - fcvtsd s0, d15 - - @ Move to VFP from ARM - - fmrdh r1, d0 - fmrdh r14, d0 - fmrdh r0, d1 - fmrdh r0, d2 - fmrdh r0, d15 - fmrdl r1, d0 - fmrdl r14, d0 - fmrdl r0, d1 - fmrdl r0, d2 - fmrdl r0, d15 - - @ Move to ARM from VFP - - fmdhr d0, r1 - fmdhr d0, r14 - fmdhr d1, r0 - fmdhr d2, r0 - fmdhr d15, r0 - fmdlr d0, r1 - fmdlr d0, r14 - fmdlr d1, r0 - fmdlr d2, r0 - fmdlr d15, r0 - - @ Load/store operations - - fldd d0, [r1] - fldd d0, [r14] - fldd d0, [r0, #0] - fldd d0, [r0, #1020] - fldd d0, [r0, #-1020] - fldd d1, [r0] - fldd d2, [r0] - fldd d15, [r0] - fstd d12, [r12, #804] - - @ Load/store multiple operations - - fldmiad r0, {d1} - fldmiad r0, {d2} - fldmiad r0, {d15} - fldmiad r0, {d0-d1} - fldmiad r0, {d0-d2} - fldmiad r0, {d0-d15} - fldmiad r0, {d1-d15} - fldmiad r0, {d2-d15} - fldmiad r0, {d14-d15} - fldmiad r1, {d0} - fldmiad r14, {d0} - - @ Check that we assemble all the register names correctly - - fcmpzd d0 - fcmpzd d1 - fcmpzd d2 - fcmpzd d3 - fcmpzd d4 - fcmpzd d5 - fcmpzd d6 - fcmpzd d7 - fcmpzd d8 - fcmpzd d9 - fcmpzd d10 - fcmpzd d11 - fcmpzd d12 - fcmpzd d13 - fcmpzd d14 - fcmpzd d15 - - @ Now we check the placement of the conditional execution substring. - @ On VFP this is always at the end of the instruction. - - @ Comparison operations - - fcmpedeq d1, d15 - fcmpezdeq d2 - fcmpdeq d3, d14 - fcmpzdeq d4 - - @ Monadic data operations - - fabsdeq d5, d13 - fcpydeq d6, d12 - fnegdeq d7, d11 - fsqrtdeq d8, d10 - - @ Dyadic data operations - - fadddeq d9, d1, d15 - fdivdeq d2, d3, d14 - fmacdeq d4, d13, d12 - fmscdeq d5, d6, d11 - fmuldeq d7, d10, d9 - fnmacdeq d8, d9, d10 - fnmscdeq d7, d6, d11 - fnmuldeq d5, d4, d12 - fsubdeq d3, d13, d14 - - @ Load/store operations - - flddeq d2, [r5] - fstdeq d1, [r12] - - @ Load/store multiple operations - - fldmiadeq r1, {d1} - fldmfddeq r2, {d2} - fldmiadeq r3!, {d3} - fldmfddeq r4!, {d4} - fldmdbdeq r5!, {d5} - fldmeadeq r6!, {d6} - - fstmiadeq r7, {d15} - fstmeadeq r8, {d14} - fstmiadeq r9!, {d13} - fstmeadeq r10!, {d12} - fstmdbdeq r11!, {d11} - fstmfddeq r12!, {d10} - - @ Conversion operations - - fsitodeq d15, s1 - fuitodeq d1, s31 - - ftosideq s1, d15 - ftosizdeq s31, d2 - ftouideq s15, d2 - ftouizdeq s11, d3 - - fcvtdseq d1, s10 - fcvtsdeq s11, d1 - - @ ARM from VFP operations - - fmrdheq r8, d1 - fmrdleq r7, d15 - - @ VFP From ARM operations - - fmdhreq d1, r15 - fmdlreq d15, r1 - - # Add three nop instructions to ensure that the - # output is 32-byte aligned as required for arm-aout. - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1_t2.d b/binutils-2.17/gas/testsuite/gas/arm/vfp1_t2.d deleted file mode 100644 index 22c4fd6f..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1_t2.d +++ /dev/null @@ -1,205 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: Thumb-2 VFP Double-precision instructions -#as: -mfpu=vfp - -# Test the ARM VFP Double Precision instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> eeb4 0bc0 fcmped d0, d0 -0+004 <[^>]*> eeb5 0bc0 fcmpezd d0 -0+008 <[^>]*> eeb4 0b40 fcmpd d0, d0 -0+00c <[^>]*> eeb5 0b40 fcmpzd d0 -0+010 <[^>]*> eeb0 0bc0 fabsd d0, d0 -0+014 <[^>]*> eeb0 0b40 fcpyd d0, d0 -0+018 <[^>]*> eeb1 0b40 fnegd d0, d0 -0+01c <[^>]*> eeb1 0bc0 fsqrtd d0, d0 -0+020 <[^>]*> ee30 0b00 faddd d0, d0, d0 -0+024 <[^>]*> ee80 0b00 fdivd d0, d0, d0 -0+028 <[^>]*> ee00 0b00 fmacd d0, d0, d0 -0+02c <[^>]*> ee10 0b00 fmscd d0, d0, d0 -0+030 <[^>]*> ee20 0b00 fmuld d0, d0, d0 -0+034 <[^>]*> ee00 0b40 fnmacd d0, d0, d0 -0+038 <[^>]*> ee10 0b40 fnmscd d0, d0, d0 -0+03c <[^>]*> ee20 0b40 fnmuld d0, d0, d0 -0+040 <[^>]*> ee30 0b40 fsubd d0, d0, d0 -0+044 <[^>]*> ed90 0b00 fldd d0, \[r0\] -0+048 <[^>]*> ed80 0b00 fstd d0, \[r0\] -0+04c <[^>]*> ec90 0b02 fldmiad r0, {d0} -0+050 <[^>]*> ec90 0b02 fldmiad r0, {d0} -0+054 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} -0+058 <[^>]*> ecb0 0b02 fldmiad r0!, {d0} -0+05c <[^>]*> ed30 0b02 fldmdbd r0!, {d0} -0+060 <[^>]*> ed30 0b02 fldmdbd r0!, {d0} -0+064 <[^>]*> ec80 0b02 fstmiad r0, {d0} -0+068 <[^>]*> ec80 0b02 fstmiad r0, {d0} -0+06c <[^>]*> eca0 0b02 fstmiad r0!, {d0} -0+070 <[^>]*> eca0 0b02 fstmiad r0!, {d0} -0+074 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} -0+078 <[^>]*> ed20 0b02 fstmdbd r0!, {d0} -0+07c <[^>]*> eeb8 0bc0 fsitod d0, s0 -0+080 <[^>]*> eeb8 0b40 fuitod d0, s0 -0+084 <[^>]*> eebd 0b40 ftosid s0, d0 -0+088 <[^>]*> eebd 0bc0 ftosizd s0, d0 -0+08c <[^>]*> eebc 0b40 ftouid s0, d0 -0+090 <[^>]*> eebc 0bc0 ftouizd s0, d0 -0+094 <[^>]*> eeb7 0ac0 fcvtds d0, s0 -0+098 <[^>]*> eeb7 0bc0 fcvtsd s0, d0 -0+09c <[^>]*> ee30 0b10 fmrdh r0, d0 -0+0a0 <[^>]*> ee10 0b10 fmrdl r0, d0 -0+0a4 <[^>]*> ee20 0b10 fmdhr d0, r0 -0+0a8 <[^>]*> ee00 0b10 fmdlr d0, r0 -0+0ac <[^>]*> eeb5 1b40 fcmpzd d1 -0+0b0 <[^>]*> eeb5 2b40 fcmpzd d2 -0+0b4 <[^>]*> eeb5 fb40 fcmpzd d15 -0+0b8 <[^>]*> eeb4 0b41 fcmpd d0, d1 -0+0bc <[^>]*> eeb4 0b42 fcmpd d0, d2 -0+0c0 <[^>]*> eeb4 0b4f fcmpd d0, d15 -0+0c4 <[^>]*> eeb4 1b40 fcmpd d1, d0 -0+0c8 <[^>]*> eeb4 2b40 fcmpd d2, d0 -0+0cc <[^>]*> eeb4 fb40 fcmpd d15, d0 -0+0d0 <[^>]*> eeb4 5b4c fcmpd d5, d12 -0+0d4 <[^>]*> eeb1 0b41 fnegd d0, d1 -0+0d8 <[^>]*> eeb1 0b42 fnegd d0, d2 -0+0dc <[^>]*> eeb1 0b4f fnegd d0, d15 -0+0e0 <[^>]*> eeb1 1b40 fnegd d1, d0 -0+0e4 <[^>]*> eeb1 2b40 fnegd d2, d0 -0+0e8 <[^>]*> eeb1 fb40 fnegd d15, d0 -0+0ec <[^>]*> eeb1 cb45 fnegd d12, d5 -0+0f0 <[^>]*> ee30 0b01 faddd d0, d0, d1 -0+0f4 <[^>]*> ee30 0b02 faddd d0, d0, d2 -0+0f8 <[^>]*> ee30 0b0f faddd d0, d0, d15 -0+0fc <[^>]*> ee31 0b00 faddd d0, d1, d0 -0+100 <[^>]*> ee32 0b00 faddd d0, d2, d0 -0+104 <[^>]*> ee3f 0b00 faddd d0, d15, d0 -0+108 <[^>]*> ee30 1b00 faddd d1, d0, d0 -0+10c <[^>]*> ee30 2b00 faddd d2, d0, d0 -0+110 <[^>]*> ee30 fb00 faddd d15, d0, d0 -0+114 <[^>]*> ee39 cb05 faddd d12, d9, d5 -0+118 <[^>]*> eeb7 0ae0 fcvtds d0, s1 -0+11c <[^>]*> eeb7 0ac1 fcvtds d0, s2 -0+120 <[^>]*> eeb7 0aef fcvtds d0, s31 -0+124 <[^>]*> eeb7 1ac0 fcvtds d1, s0 -0+128 <[^>]*> eeb7 2ac0 fcvtds d2, s0 -0+12c <[^>]*> eeb7 fac0 fcvtds d15, s0 -0+130 <[^>]*> eef7 0bc0 fcvtsd s1, d0 -0+134 <[^>]*> eeb7 1bc0 fcvtsd s2, d0 -0+138 <[^>]*> eef7 fbc0 fcvtsd s31, d0 -0+13c <[^>]*> eeb7 0bc1 fcvtsd s0, d1 -0+140 <[^>]*> eeb7 0bc2 fcvtsd s0, d2 -0+144 <[^>]*> eeb7 0bcf fcvtsd s0, d15 -0+148 <[^>]*> ee30 1b10 fmrdh r1, d0 -0+14c <[^>]*> ee30 eb10 fmrdh lr, d0 -0+150 <[^>]*> ee31 0b10 fmrdh r0, d1 -0+154 <[^>]*> ee32 0b10 fmrdh r0, d2 -0+158 <[^>]*> ee3f 0b10 fmrdh r0, d15 -0+15c <[^>]*> ee10 1b10 fmrdl r1, d0 -0+160 <[^>]*> ee10 eb10 fmrdl lr, d0 -0+164 <[^>]*> ee11 0b10 fmrdl r0, d1 -0+168 <[^>]*> ee12 0b10 fmrdl r0, d2 -0+16c <[^>]*> ee1f 0b10 fmrdl r0, d15 -0+170 <[^>]*> ee20 1b10 fmdhr d0, r1 -0+174 <[^>]*> ee20 eb10 fmdhr d0, lr -0+178 <[^>]*> ee21 0b10 fmdhr d1, r0 -0+17c <[^>]*> ee22 0b10 fmdhr d2, r0 -0+180 <[^>]*> ee2f 0b10 fmdhr d15, r0 -0+184 <[^>]*> ee00 1b10 fmdlr d0, r1 -0+188 <[^>]*> ee00 eb10 fmdlr d0, lr -0+18c <[^>]*> ee01 0b10 fmdlr d1, r0 -0+190 <[^>]*> ee02 0b10 fmdlr d2, r0 -0+194 <[^>]*> ee0f 0b10 fmdlr d15, r0 -0+198 <[^>]*> ed91 0b00 fldd d0, \[r1\] -0+19c <[^>]*> ed9e 0b00 fldd d0, \[lr\] -0+1a0 <[^>]*> ed90 0b00 fldd d0, \[r0\] -0+1a4 <[^>]*> ed90 0bff fldd d0, \[r0, #1020\] -0+1a8 <[^>]*> ed10 0bff fldd d0, \[r0, #-1020\] -0+1ac <[^>]*> ed90 1b00 fldd d1, \[r0\] -0+1b0 <[^>]*> ed90 2b00 fldd d2, \[r0\] -0+1b4 <[^>]*> ed90 fb00 fldd d15, \[r0\] -0+1b8 <[^>]*> ed8c cbc9 fstd d12, \[ip, #804\] -0+1bc <[^>]*> ec90 1b02 fldmiad r0, {d1} -0+1c0 <[^>]*> ec90 2b02 fldmiad r0, {d2} -0+1c4 <[^>]*> ec90 fb02 fldmiad r0, {d15} -0+1c8 <[^>]*> ec90 0b04 fldmiad r0, {d0-d1} -0+1cc <[^>]*> ec90 0b06 fldmiad r0, {d0-d2} -0+1d0 <[^>]*> ec90 0b20 fldmiad r0, {d0-d15} -0+1d4 <[^>]*> ec90 1b1e fldmiad r0, {d1-d15} -0+1d8 <[^>]*> ec90 2b1c fldmiad r0, {d2-d15} -0+1dc <[^>]*> ec90 eb04 fldmiad r0, {d14-d15} -0+1e0 <[^>]*> ec91 0b02 fldmiad r1, {d0} -0+1e4 <[^>]*> ec9e 0b02 fldmiad lr, {d0} -0+1e8 <[^>]*> eeb5 0b40 fcmpzd d0 -0+1ec <[^>]*> eeb5 1b40 fcmpzd d1 -0+1f0 <[^>]*> eeb5 2b40 fcmpzd d2 -0+1f4 <[^>]*> eeb5 3b40 fcmpzd d3 -0+1f8 <[^>]*> eeb5 4b40 fcmpzd d4 -0+1fc <[^>]*> eeb5 5b40 fcmpzd d5 -0+200 <[^>]*> eeb5 6b40 fcmpzd d6 -0+204 <[^>]*> eeb5 7b40 fcmpzd d7 -0+208 <[^>]*> eeb5 8b40 fcmpzd d8 -0+20c <[^>]*> eeb5 9b40 fcmpzd d9 -0+210 <[^>]*> eeb5 ab40 fcmpzd d10 -0+214 <[^>]*> eeb5 bb40 fcmpzd d11 -0+218 <[^>]*> eeb5 cb40 fcmpzd d12 -0+21c <[^>]*> eeb5 db40 fcmpzd d13 -0+220 <[^>]*> eeb5 eb40 fcmpzd d14 -0+224 <[^>]*> eeb5 fb40 fcmpzd d15 -# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. -0+228 <[^>]*> bf01 itttt eq -0+22a <[^>]*> eeb4 1bcf fcmped(eq|) d1, d15 -0+22e <[^>]*> eeb5 2bc0 fcmpezd(eq|) d2 -0+232 <[^>]*> eeb4 3b4e fcmpd(eq|) d3, d14 -0+236 <[^>]*> eeb5 4b40 fcmpzd(eq|) d4 -0+23a <[^>]*> bf01 itttt eq -0+23c <[^>]*> eeb0 5bcd fabsd(eq|) d5, d13 -0+240 <[^>]*> eeb0 6b4c fcpyd(eq|) d6, d12 -0+244 <[^>]*> eeb1 7b4b fnegd(eq|) d7, d11 -0+248 <[^>]*> eeb1 8bca fsqrtd(eq|) d8, d10 -0+24c <[^>]*> bf01 itttt eq -0+24e <[^>]*> ee31 9b0f faddd(eq|) d9, d1, d15 -0+252 <[^>]*> ee83 2b0e fdivd(eq|) d2, d3, d14 -0+256 <[^>]*> ee0d 4b0c fmacd(eq|) d4, d13, d12 -0+25a <[^>]*> ee16 5b0b fmscd(eq|) d5, d6, d11 -0+25e <[^>]*> bf01 itttt eq -0+260 <[^>]*> ee2a 7b09 fmuld(eq|) d7, d10, d9 -0+264 <[^>]*> ee09 8b4a fnmacd(eq|) d8, d9, d10 -0+268 <[^>]*> ee16 7b4b fnmscd(eq|) d7, d6, d11 -0+26c <[^>]*> ee24 5b4c fnmuld(eq|) d5, d4, d12 -0+270 <[^>]*> bf02 ittt eq -0+272 <[^>]*> ee3d 3b4e fsubd(eq|) d3, d13, d14 -0+276 <[^>]*> ed95 2b00 fldd(eq|) d2, \[r5\] -0+27a <[^>]*> ed8c 1b00 fstd(eq|) d1, \[ip\] -0+27e <[^>]*> bf01 itttt eq -0+280 <[^>]*> ec91 1b02 fldmiad(eq|) r1, {d1} -0+284 <[^>]*> ec92 2b02 fldmiad(eq|) r2, {d2} -0+288 <[^>]*> ecb3 3b02 fldmiad(eq|) r3!, {d3} -0+28c <[^>]*> ecb4 4b02 fldmiad(eq|) r4!, {d4} -0+290 <[^>]*> bf01 itttt eq -0+292 <[^>]*> ed35 5b02 fldmdbd(eq|) r5!, {d5} -0+296 <[^>]*> ed36 6b02 fldmdbd(eq|) r6!, {d6} -0+29a <[^>]*> ec87 fb02 fstmiad(eq|) r7, {d15} -0+29e <[^>]*> ec88 eb02 fstmiad(eq|) r8, {d14} -0+2a2 <[^>]*> bf01 itttt eq -0+2a4 <[^>]*> eca9 db02 fstmiad(eq|) r9!, {d13} -0+2a8 <[^>]*> ecaa cb02 fstmiad(eq|) sl!, {d12} -0+2ac <[^>]*> ed2b bb02 fstmdbd(eq|) fp!, {d11} -0+2b0 <[^>]*> ed2c ab02 fstmdbd(eq|) ip!, {d10} -0+2b4 <[^>]*> bf01 itttt eq -0+2b6 <[^>]*> eeb8 fbe0 fsitod(eq|) d15, s1 -0+2ba <[^>]*> eeb8 1b6f fuitod(eq|) d1, s31 -0+2be <[^>]*> eefd 0b4f ftosid(eq|) s1, d15 -0+2c2 <[^>]*> eefd fbc2 ftosizd(eq|) s31, d2 -0+2c6 <[^>]*> bf01 itttt eq -0+2c8 <[^>]*> eefc 7b42 ftouid(eq|) s15, d2 -0+2cc <[^>]*> eefc 5bc3 ftouizd(eq|) s11, d3 -0+2d0 <[^>]*> eeb7 1ac5 fcvtds(eq|) d1, s10 -0+2d4 <[^>]*> eef7 5bc1 fcvtsd(eq|) s11, d1 -0+2d8 <[^>]*> bf01 itttt eq -0+2da <[^>]*> ee31 8b10 fmrdh(eq|) r8, d1 -0+2de <[^>]*> ee1f 7b10 fmrdl(eq|) r7, d15 -0+2e2 <[^>]*> ee21 fb10 fmdhr(eq|) d1, pc -0+2e6 <[^>]*> ee0f 1b10 fmdlr(eq|) d15, r1 -0+2ea <[^>]*> bf00 nop -0+2ec <[^>]*> bf00 nop -0+2ee <[^>]*> bf00 nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1_t2.s b/binutils-2.17/gas/testsuite/gas/arm/vfp1_t2.s deleted file mode 100644 index dd596cb5..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1_t2.s +++ /dev/null @@ -1,298 +0,0 @@ -@ VFP Instructions for D variants (Double precision) -@ Same as vfp1.s, but for Thumb-2 - .syntax unified - .thumb - .text - .global F -F: - @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use d0/r0 to avoid setting - @ any more bits than necessary. - - @ Comparison operations - - fcmped d0, d0 - fcmpezd d0 - fcmpd d0, d0 - fcmpzd d0 - - @ Monadic data operations - - fabsd d0, d0 - fcpyd d0, d0 - fnegd d0, d0 - fsqrtd d0, d0 - - @ Dyadic data operations - - faddd d0, d0, d0 - fdivd d0, d0, d0 - fmacd d0, d0, d0 - fmscd d0, d0, d0 - fmuld d0, d0, d0 - fnmacd d0, d0, d0 - fnmscd d0, d0, d0 - fnmuld d0, d0, d0 - fsubd d0, d0, d0 - - @ Load/store operations - - fldd d0, [r0] - fstd d0, [r0] - - @ Load/store multiple operations - - fldmiad r0, {d0} - fldmfdd r0, {d0} - fldmiad r0!, {d0} - fldmfdd r0!, {d0} - fldmdbd r0!, {d0} - fldmead r0!, {d0} - - fstmiad r0, {d0} - fstmead r0, {d0} - fstmiad r0!, {d0} - fstmead r0!, {d0} - fstmdbd r0!, {d0} - fstmfdd r0!, {d0} - - @ Conversion operations - - fsitod d0, s0 - fuitod d0, s0 - - ftosid s0, d0 - ftosizd s0, d0 - ftouid s0, d0 - ftouizd s0, d0 - - fcvtds d0, s0 - fcvtsd s0, d0 - - @ ARM from VFP operations - - fmrdh r0, d0 - fmrdl r0, d0 - - @ VFP From ARM operations - - fmdhr d0, r0 - fmdlr d0, r0 - - @ Now we test that the register fields are updated correctly for - @ each class of instruction. - - @ Single register operations (compare-zero): - - fcmpzd d1 - fcmpzd d2 - fcmpzd d15 - - @ Two register comparison operations: - - fcmpd d0, d1 - fcmpd d0, d2 - fcmpd d0, d15 - fcmpd d1, d0 - fcmpd d2, d0 - fcmpd d15, d0 - fcmpd d5, d12 - - @ Two register data operations (monadic) - - fnegd d0, d1 - fnegd d0, d2 - fnegd d0, d15 - fnegd d1, d0 - fnegd d2, d0 - fnegd d15, d0 - fnegd d12, d5 - - @ Three register data operations (dyadic) - - faddd d0, d0, d1 - faddd d0, d0, d2 - faddd d0, d0, d15 - faddd d0, d1, d0 - faddd d0, d2, d0 - faddd d0, d15, d0 - faddd d1, d0, d0 - faddd d2, d0, d0 - faddd d15, d0, d0 - faddd d12, d9, d5 - - @ Conversion operations - - fcvtds d0, s1 - fcvtds d0, s2 - fcvtds d0, s31 - fcvtds d1, s0 - fcvtds d2, s0 - fcvtds d15, s0 - fcvtsd s1, d0 - fcvtsd s2, d0 - fcvtsd s31, d0 - fcvtsd s0, d1 - fcvtsd s0, d2 - fcvtsd s0, d15 - - @ Move to VFP from ARM - - fmrdh r1, d0 - fmrdh r14, d0 - fmrdh r0, d1 - fmrdh r0, d2 - fmrdh r0, d15 - fmrdl r1, d0 - fmrdl r14, d0 - fmrdl r0, d1 - fmrdl r0, d2 - fmrdl r0, d15 - - @ Move to ARM from VFP - - fmdhr d0, r1 - fmdhr d0, r14 - fmdhr d1, r0 - fmdhr d2, r0 - fmdhr d15, r0 - fmdlr d0, r1 - fmdlr d0, r14 - fmdlr d1, r0 - fmdlr d2, r0 - fmdlr d15, r0 - - @ Load/store operations - - fldd d0, [r1] - fldd d0, [r14] - fldd d0, [r0, #0] - fldd d0, [r0, #1020] - fldd d0, [r0, #-1020] - fldd d1, [r0] - fldd d2, [r0] - fldd d15, [r0] - fstd d12, [r12, #804] - - @ Load/store multiple operations - - fldmiad r0, {d1} - fldmiad r0, {d2} - fldmiad r0, {d15} - fldmiad r0, {d0-d1} - fldmiad r0, {d0-d2} - fldmiad r0, {d0-d15} - fldmiad r0, {d1-d15} - fldmiad r0, {d2-d15} - fldmiad r0, {d14-d15} - fldmiad r1, {d0} - fldmiad r14, {d0} - - @ Check that we assemble all the register names correctly - - fcmpzd d0 - fcmpzd d1 - fcmpzd d2 - fcmpzd d3 - fcmpzd d4 - fcmpzd d5 - fcmpzd d6 - fcmpzd d7 - fcmpzd d8 - fcmpzd d9 - fcmpzd d10 - fcmpzd d11 - fcmpzd d12 - fcmpzd d13 - fcmpzd d14 - fcmpzd d15 - - @ Now we check the placement of the conditional execution substring. - @ On VFP this is always at the end of the instruction. - - @ Comparison operations - - itttt eq - fcmpedeq d1, d15 - fcmpezdeq d2 - fcmpdeq d3, d14 - fcmpzdeq d4 - - @ Monadic data operations - - itttt eq - fabsdeq d5, d13 - fcpydeq d6, d12 - fnegdeq d7, d11 - fsqrtdeq d8, d10 - - @ Dyadic data operations - - itttt eq - fadddeq d9, d1, d15 - fdivdeq d2, d3, d14 - fmacdeq d4, d13, d12 - fmscdeq d5, d6, d11 - itttt eq - fmuldeq d7, d10, d9 - fnmacdeq d8, d9, d10 - fnmscdeq d7, d6, d11 - fnmuldeq d5, d4, d12 - ittt eq - fsubdeq d3, d13, d14 - - @ Load/store operations - - flddeq d2, [r5] - fstdeq d1, [r12] - - @ Load/store multiple operations - - itttt eq - fldmiadeq r1, {d1} - fldmfddeq r2, {d2} - fldmiadeq r3!, {d3} - fldmfddeq r4!, {d4} - itttt eq - fldmdbdeq r5!, {d5} - fldmeadeq r6!, {d6} - - fstmiadeq r7, {d15} - fstmeadeq r8, {d14} - itttt eq - fstmiadeq r9!, {d13} - fstmeadeq r10!, {d12} - fstmdbdeq r11!, {d11} - fstmfddeq r12!, {d10} - - @ Conversion operations - - itttt eq - fsitodeq d15, s1 - fuitodeq d1, s31 - - ftosideq s1, d15 - ftosizdeq s31, d2 - itttt eq - ftouideq s15, d2 - ftouizdeq s11, d3 - - fcvtdseq d1, s10 - fcvtsdeq s11, d1 - - @ ARM from VFP operations - - itttt eq - fmrdheq r8, d1 - fmrdleq r7, d15 - - @ VFP From ARM operations - - fmdhreq d1, r15 - fmdlreq d15, r1 - - # Add three nop instructions to ensure that the - # output is 32-byte aligned as required for arm-aout. - nop - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD.d b/binutils-2.17/gas/testsuite/gas/arm/vfp1xD.d deleted file mode 100644 index 096b46c8..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD.d +++ /dev/null @@ -1,241 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: VFP Single-precision instructions -#as: -mfpu=vfpxd - -# Test the ARM VFP Single Precision instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> eef1fa10 fmstat -0+004 <[^>]*> eeb40ac0 fcmpes s0, s0 -0+008 <[^>]*> eeb50ac0 fcmpezs s0 -0+00c <[^>]*> eeb40a40 fcmps s0, s0 -0+010 <[^>]*> eeb50a40 fcmpzs s0 -0+014 <[^>]*> eeb00ac0 fabss s0, s0 -0+018 <[^>]*> eeb00a40 fcpys s0, s0 -0+01c <[^>]*> eeb10a40 fnegs s0, s0 -0+020 <[^>]*> eeb10ac0 fsqrts s0, s0 -0+024 <[^>]*> ee300a00 fadds s0, s0, s0 -0+028 <[^>]*> ee800a00 fdivs s0, s0, s0 -0+02c <[^>]*> ee000a00 fmacs s0, s0, s0 -0+030 <[^>]*> ee100a00 fmscs s0, s0, s0 -0+034 <[^>]*> ee200a00 fmuls s0, s0, s0 -0+038 <[^>]*> ee000a40 fnmacs s0, s0, s0 -0+03c <[^>]*> ee100a40 fnmscs s0, s0, s0 -0+040 <[^>]*> ee200a40 fnmuls s0, s0, s0 -0+044 <[^>]*> ee300a40 fsubs s0, s0, s0 -0+048 <[^>]*> ed900a00 flds s0, \[r0\] -0+04c <[^>]*> ed800a00 fsts s0, \[r0\] -0+050 <[^>]*> ec900a01 fldmias r0, {s0} -0+054 <[^>]*> ec900a01 fldmias r0, {s0} -0+058 <[^>]*> ecb00a01 fldmias r0!, {s0} -0+05c <[^>]*> ecb00a01 fldmias r0!, {s0} -0+060 <[^>]*> ed300a01 fldmdbs r0!, {s0} -0+064 <[^>]*> ed300a01 fldmdbs r0!, {s0} -0+068 <[^>]*> ec900b03 fldmiax r0, {d0} -0+06c <[^>]*> ec900b03 fldmiax r0, {d0} -0+070 <[^>]*> ecb00b03 fldmiax r0!, {d0} -0+074 <[^>]*> ecb00b03 fldmiax r0!, {d0} -0+078 <[^>]*> ed300b03 fldmdbx r0!, {d0} -0+07c <[^>]*> ed300b03 fldmdbx r0!, {d0} -0+080 <[^>]*> ec800a01 fstmias r0, {s0} -0+084 <[^>]*> ec800a01 fstmias r0, {s0} -0+088 <[^>]*> eca00a01 fstmias r0!, {s0} -0+08c <[^>]*> eca00a01 fstmias r0!, {s0} -0+090 <[^>]*> ed200a01 fstmdbs r0!, {s0} -0+094 <[^>]*> ed200a01 fstmdbs r0!, {s0} -0+098 <[^>]*> ec800b03 fstmiax r0, {d0} -0+09c <[^>]*> ec800b03 fstmiax r0, {d0} -0+0a0 <[^>]*> eca00b03 fstmiax r0!, {d0} -0+0a4 <[^>]*> eca00b03 fstmiax r0!, {d0} -0+0a8 <[^>]*> ed200b03 fstmdbx r0!, {d0} -0+0ac <[^>]*> ed200b03 fstmdbx r0!, {d0} -0+0b0 <[^>]*> eeb80ac0 fsitos s0, s0 -0+0b4 <[^>]*> eeb80a40 fuitos s0, s0 -0+0b8 <[^>]*> eebd0a40 ftosis s0, s0 -0+0bc <[^>]*> eebd0ac0 ftosizs s0, s0 -0+0c0 <[^>]*> eebc0a40 ftouis s0, s0 -0+0c4 <[^>]*> eebc0ac0 ftouizs s0, s0 -0+0c8 <[^>]*> ee100a10 fmrs r0, s0 -0+0cc <[^>]*> eef00a10 fmrx r0, fpsid -0+0d0 <[^>]*> eef10a10 fmrx r0, fpscr -0+0d4 <[^>]*> eef80a10 fmrx r0, fpexc -0+0d8 <[^>]*> ee000a10 fmsr s0, r0 -0+0dc <[^>]*> eee00a10 fmxr fpsid, r0 -0+0e0 <[^>]*> eee10a10 fmxr fpscr, r0 -0+0e4 <[^>]*> eee80a10 fmxr fpexc, r0 -0+0e8 <[^>]*> eef50a40 fcmpzs s1 -0+0ec <[^>]*> eeb51a40 fcmpzs s2 -0+0f0 <[^>]*> eef5fa40 fcmpzs s31 -0+0f4 <[^>]*> eeb40a60 fcmps s0, s1 -0+0f8 <[^>]*> eeb40a41 fcmps s0, s2 -0+0fc <[^>]*> eeb40a6f fcmps s0, s31 -0+100 <[^>]*> eef40a40 fcmps s1, s0 -0+104 <[^>]*> eeb41a40 fcmps s2, s0 -0+108 <[^>]*> eef4fa40 fcmps s31, s0 -0+10c <[^>]*> eef4aa46 fcmps s21, s12 -0+110 <[^>]*> eeb10a60 fnegs s0, s1 -0+114 <[^>]*> eeb10a41 fnegs s0, s2 -0+118 <[^>]*> eeb10a6f fnegs s0, s31 -0+11c <[^>]*> eef10a40 fnegs s1, s0 -0+120 <[^>]*> eeb11a40 fnegs s2, s0 -0+124 <[^>]*> eef1fa40 fnegs s31, s0 -0+128 <[^>]*> eeb16a6a fnegs s12, s21 -0+12c <[^>]*> ee300a20 fadds s0, s0, s1 -0+130 <[^>]*> ee300a01 fadds s0, s0, s2 -0+134 <[^>]*> ee300a2f fadds s0, s0, s31 -0+138 <[^>]*> ee300a80 fadds s0, s1, s0 -0+13c <[^>]*> ee310a00 fadds s0, s2, s0 -0+140 <[^>]*> ee3f0a80 fadds s0, s31, s0 -0+144 <[^>]*> ee700a00 fadds s1, s0, s0 -0+148 <[^>]*> ee301a00 fadds s2, s0, s0 -0+14c <[^>]*> ee70fa00 fadds s31, s0, s0 -0+150 <[^>]*> ee3a6aa2 fadds s12, s21, s5 -0+154 <[^>]*> eeb80ae0 fsitos s0, s1 -0+158 <[^>]*> eeb80ac1 fsitos s0, s2 -0+15c <[^>]*> eeb80aef fsitos s0, s31 -0+160 <[^>]*> eef80ac0 fsitos s1, s0 -0+164 <[^>]*> eeb81ac0 fsitos s2, s0 -0+168 <[^>]*> eef8fac0 fsitos s31, s0 -0+16c <[^>]*> eebd0a60 ftosis s0, s1 -0+170 <[^>]*> eebd0a41 ftosis s0, s2 -0+174 <[^>]*> eebd0a6f ftosis s0, s31 -0+178 <[^>]*> eefd0a40 ftosis s1, s0 -0+17c <[^>]*> eebd1a40 ftosis s2, s0 -0+180 <[^>]*> eefdfa40 ftosis s31, s0 -0+184 <[^>]*> ee001a10 fmsr s0, r1 -0+188 <[^>]*> ee007a10 fmsr s0, r7 -0+18c <[^>]*> ee00ea10 fmsr s0, lr -0+190 <[^>]*> ee000a90 fmsr s1, r0 -0+194 <[^>]*> ee010a10 fmsr s2, r0 -0+198 <[^>]*> ee0f0a90 fmsr s31, r0 -0+19c <[^>]*> ee0a7a90 fmsr s21, r7 -0+1a0 <[^>]*> eee01a10 fmxr fpsid, r1 -0+1a4 <[^>]*> eee0ea10 fmxr fpsid, lr -0+1a8 <[^>]*> ee100a90 fmrs r0, s1 -0+1ac <[^>]*> ee110a10 fmrs r0, s2 -0+1b0 <[^>]*> ee1f0a90 fmrs r0, s31 -0+1b4 <[^>]*> ee101a10 fmrs r1, s0 -0+1b8 <[^>]*> ee107a10 fmrs r7, s0 -0+1bc <[^>]*> ee10ea10 fmrs lr, s0 -0+1c0 <[^>]*> ee159a90 fmrs r9, s11 -0+1c4 <[^>]*> eef01a10 fmrx r1, fpsid -0+1c8 <[^>]*> eef0ea10 fmrx lr, fpsid -0+1cc <[^>]*> ed910a00 flds s0, \[r1\] -0+1d0 <[^>]*> ed9e0a00 flds s0, \[lr\] -0+1d4 <[^>]*> ed900a00 flds s0, \[r0\] -0+1d8 <[^>]*> ed900aff flds s0, \[r0, #1020\] -0+1dc <[^>]*> ed100aff flds s0, \[r0, #-1020\] -0+1e0 <[^>]*> edd00a00 flds s1, \[r0\] -0+1e4 <[^>]*> ed901a00 flds s2, \[r0\] -0+1e8 <[^>]*> edd0fa00 flds s31, \[r0\] -0+1ec <[^>]*> edccaac9 fsts s21, \[ip, #804\] -0+1f0 <[^>]*> ecd00a01 fldmias r0, {s1} -0+1f4 <[^>]*> ec901a01 fldmias r0, {s2} -0+1f8 <[^>]*> ecd0fa01 fldmias r0, {s31} -0+1fc <[^>]*> ec900a02 fldmias r0, {s0-s1} -0+200 <[^>]*> ec900a03 fldmias r0, {s0-s2} -0+204 <[^>]*> ec900a20 fldmias r0, {s0-s31} -0+208 <[^>]*> ecd00a1f fldmias r0, {s1-s31} -0+20c <[^>]*> ec901a1e fldmias r0, {s2-s31} -0+210 <[^>]*> ec90fa02 fldmias r0, {s30-s31} -0+214 <[^>]*> ec910a01 fldmias r1, {s0} -0+218 <[^>]*> ec9e0a01 fldmias lr, {s0} -0+21c <[^>]*> ec801b03 fstmiax r0, {d1} -0+220 <[^>]*> ec802b03 fstmiax r0, {d2} -0+224 <[^>]*> ec80fb03 fstmiax r0, {d15} -0+228 <[^>]*> ec800b05 fstmiax r0, {d0-d1} -0+22c <[^>]*> ec800b07 fstmiax r0, {d0-d2} -0+230 <[^>]*> ec800b21 fstmiax r0, {d0-d15} -0+234 <[^>]*> ec801b1f fstmiax r0, {d1-d15} -0+238 <[^>]*> ec802b1d fstmiax r0, {d2-d15} -0+23c <[^>]*> ec80eb05 fstmiax r0, {d14-d15} -0+240 <[^>]*> ec810b03 fstmiax r1, {d0} -0+244 <[^>]*> ec8e0b03 fstmiax lr, {d0} -0+248 <[^>]*> eeb50a40 fcmpzs s0 -0+24c <[^>]*> eef50a40 fcmpzs s1 -0+250 <[^>]*> eeb51a40 fcmpzs s2 -0+254 <[^>]*> eef51a40 fcmpzs s3 -0+258 <[^>]*> eeb52a40 fcmpzs s4 -0+25c <[^>]*> eef52a40 fcmpzs s5 -0+260 <[^>]*> eeb53a40 fcmpzs s6 -0+264 <[^>]*> eef53a40 fcmpzs s7 -0+268 <[^>]*> eeb54a40 fcmpzs s8 -0+26c <[^>]*> eef54a40 fcmpzs s9 -0+270 <[^>]*> eeb55a40 fcmpzs s10 -0+274 <[^>]*> eef55a40 fcmpzs s11 -0+278 <[^>]*> eeb56a40 fcmpzs s12 -0+27c <[^>]*> eef56a40 fcmpzs s13 -0+280 <[^>]*> eeb57a40 fcmpzs s14 -0+284 <[^>]*> eef57a40 fcmpzs s15 -0+288 <[^>]*> eeb58a40 fcmpzs s16 -0+28c <[^>]*> eef58a40 fcmpzs s17 -0+290 <[^>]*> eeb59a40 fcmpzs s18 -0+294 <[^>]*> eef59a40 fcmpzs s19 -0+298 <[^>]*> eeb5aa40 fcmpzs s20 -0+29c <[^>]*> eef5aa40 fcmpzs s21 -0+2a0 <[^>]*> eeb5ba40 fcmpzs s22 -0+2a4 <[^>]*> eef5ba40 fcmpzs s23 -0+2a8 <[^>]*> eeb5ca40 fcmpzs s24 -0+2ac <[^>]*> eef5ca40 fcmpzs s25 -0+2b0 <[^>]*> eeb5da40 fcmpzs s26 -0+2b4 <[^>]*> eef5da40 fcmpzs s27 -0+2b8 <[^>]*> eeb5ea40 fcmpzs s28 -0+2bc <[^>]*> eef5ea40 fcmpzs s29 -0+2c0 <[^>]*> eeb5fa40 fcmpzs s30 -0+2c4 <[^>]*> eef5fa40 fcmpzs s31 -0+2c8 <[^>]*> 0ef1fa10 fmstateq -0+2cc <[^>]*> 0ef41ae3 fcmpeseq s3, s7 -0+2d0 <[^>]*> 0ef52ac0 fcmpezseq s5 -0+2d4 <[^>]*> 0ef40a41 fcmpseq s1, s2 -0+2d8 <[^>]*> 0ef50a40 fcmpzseq s1 -0+2dc <[^>]*> 0ef00ae1 fabsseq s1, s3 -0+2e0 <[^>]*> 0ef0fa69 fcpyseq s31, s19 -0+2e4 <[^>]*> 0eb1aa44 fnegseq s20, s8 -0+2e8 <[^>]*> 0ef12ae3 fsqrtseq s5, s7 -0+2ec <[^>]*> 0e323a82 faddseq s6, s5, s4 -0+2f0 <[^>]*> 0ec11a20 fdivseq s3, s2, s1 -0+2f4 <[^>]*> 0e4ffa2e fmacseq s31, s30, s29 -0+2f8 <[^>]*> 0e1dea8d fmscseq s28, s27, s26 -0+2fc <[^>]*> 0e6cca2b fmulseq s25, s24, s23 -0+300 <[^>]*> 0e0abaca fnmacseq s22, s21, s20 -0+304 <[^>]*> 0e599a68 fnmscseq s19, s18, s17 -0+308 <[^>]*> 0e278ac7 fnmulseq s16, s15, s14 -0+30c <[^>]*> 0e766a65 fsubseq s13, s12, s11 -0+310 <[^>]*> 0d985a00 fldseq s10, \[r8\] -0+314 <[^>]*> 0dc74a00 fstseq s9, \[r7\] -0+318 <[^>]*> 0c914a01 fldmiaseq r1, {s8} -0+31c <[^>]*> 0cd23a01 fldmiaseq r2, {s7} -0+320 <[^>]*> 0cb33a01 fldmiaseq r3!, {s6} -0+324 <[^>]*> 0cf42a01 fldmiaseq r4!, {s5} -0+328 <[^>]*> 0d352a01 fldmdbseq r5!, {s4} -0+32c <[^>]*> 0d761a01 fldmdbseq r6!, {s3} -0+330 <[^>]*> 0c971b03 fldmiaxeq r7, {d1} -0+334 <[^>]*> 0c982b03 fldmiaxeq r8, {d2} -0+338 <[^>]*> 0cb93b03 fldmiaxeq r9!, {d3} -0+33c <[^>]*> 0cba4b03 fldmiaxeq sl!, {d4} -0+340 <[^>]*> 0d3b5b03 fldmdbxeq fp!, {d5} -0+344 <[^>]*> 0d3c6b03 fldmdbxeq ip!, {d6} -0+348 <[^>]*> 0c8d1a01 fstmiaseq sp, {s2} -0+34c <[^>]*> 0cce0a01 fstmiaseq lr, {s1} -0+350 <[^>]*> 0ce1fa01 fstmiaseq r1!, {s31} -0+354 <[^>]*> 0ca2fa01 fstmiaseq r2!, {s30} -0+358 <[^>]*> 0d63ea01 fstmdbseq r3!, {s29} -0+35c <[^>]*> 0d24ea01 fstmdbseq r4!, {s28} -0+360 <[^>]*> 0c857b03 fstmiaxeq r5, {d7} -0+364 <[^>]*> 0c868b03 fstmiaxeq r6, {d8} -0+368 <[^>]*> 0ca79b03 fstmiaxeq r7!, {d9} -0+36c <[^>]*> 0ca8ab03 fstmiaxeq r8!, {d10} -0+370 <[^>]*> 0d29bb03 fstmdbxeq r9!, {d11} -0+374 <[^>]*> 0d2acb03 fstmdbxeq sl!, {d12} -0+378 <[^>]*> 0ef8dac3 fsitoseq s27, s6 -0+37c <[^>]*> 0efdca62 ftosiseq s25, s5 -0+380 <[^>]*> 0efdbac2 ftosizseq s23, s4 -0+384 <[^>]*> 0efcaa61 ftouiseq s21, s3 -0+388 <[^>]*> 0efc9ac1 ftouizseq s19, s2 -0+38c <[^>]*> 0ef88a60 fuitoseq s17, s1 -0+390 <[^>]*> 0e11ba90 fmrseq fp, s3 -0+394 <[^>]*> 0ef09a10 fmrxeq r9, fpsid -0+398 <[^>]*> 0e019a90 fmsreq s3, r9 -0+39c <[^>]*> 0ee08a10 fmxreq fpsid, r8 diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD.s b/binutils-2.17/gas/testsuite/gas/arm/vfp1xD.s deleted file mode 100644 index 82f080f4..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD.s +++ /dev/null @@ -1,339 +0,0 @@ -@ VFP Instructions for v1xD variants (Single precision only) - .text - .global F -F: - @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use s0/r0 to avoid setting - @ any more bits than necessary. - - @ Comparison operations - - fmstat - - fcmpes s0, s0 - fcmpezs s0 - fcmps s0, s0 - fcmpzs s0 - - @ Monadic data operations - - fabss s0, s0 - fcpys s0, s0 - fnegs s0, s0 - fsqrts s0, s0 - - @ Dyadic data operations - - fadds s0, s0, s0 - fdivs s0, s0, s0 - fmacs s0, s0, s0 - fmscs s0, s0, s0 - fmuls s0, s0, s0 - fnmacs s0, s0, s0 - fnmscs s0, s0, s0 - fnmuls s0, s0, s0 - fsubs s0, s0, s0 - - @ Load/store operations - - flds s0, [r0] - fsts s0, [r0] - - @ Load/store multiple operations - - fldmias r0, {s0} - fldmfds r0, {s0} - fldmias r0!, {s0} - fldmfds r0!, {s0} - fldmdbs r0!, {s0} - fldmeas r0!, {s0} - - fldmiax r0, {d0} - fldmfdx r0, {d0} - fldmiax r0!, {d0} - fldmfdx r0!, {d0} - fldmdbx r0!, {d0} - fldmeax r0!, {d0} - - fstmias r0, {s0} - fstmeas r0, {s0} - fstmias r0!, {s0} - fstmeas r0!, {s0} - fstmdbs r0!, {s0} - fstmfds r0!, {s0} - - fstmiax r0, {d0} - fstmeax r0, {d0} - fstmiax r0!, {d0} - fstmeax r0!, {d0} - fstmdbx r0!, {d0} - fstmfdx r0!, {d0} - - @ Conversion operations - - fsitos s0, s0 - fuitos s0, s0 - - ftosis s0, s0 - ftosizs s0, s0 - ftouis s0, s0 - ftouizs s0, s0 - - @ ARM from VFP operations - - fmrs r0, s0 - fmrx r0, fpsid - fmrx r0, fpscr - fmrx r0, fpexc - - @ VFP From ARM operations - - fmsr s0, r0 - fmxr fpsid, r0 - fmxr fpscr, r0 - fmxr fpexc, r0 - - @ Now we test that the register fields are updated correctly for - @ each class of instruction. - - @ Single register operations (compare-zero): - - fcmpzs s1 - fcmpzs s2 - fcmpzs s31 - - @ Two register comparison operations: - - fcmps s0, s1 - fcmps s0, s2 - fcmps s0, s31 - fcmps s1, s0 - fcmps s2, s0 - fcmps s31, s0 - fcmps s21, s12 - - @ Two register data operations (monadic) - - fnegs s0, s1 - fnegs s0, s2 - fnegs s0, s31 - fnegs s1, s0 - fnegs s2, s0 - fnegs s31, s0 - fnegs s12, s21 - - @ Three register data operations (dyadic) - - fadds s0, s0, s1 - fadds s0, s0, s2 - fadds s0, s0, s31 - fadds s0, s1, s0 - fadds s0, s2, s0 - fadds s0, s31, s0 - fadds s1, s0, s0 - fadds s2, s0, s0 - fadds s31, s0, s0 - fadds s12, s21, s5 - - @ Conversion operations - - fsitos s0, s1 - fsitos s0, s2 - fsitos s0, s31 - fsitos s1, s0 - fsitos s2, s0 - fsitos s31, s0 - - ftosis s0, s1 - ftosis s0, s2 - ftosis s0, s31 - ftosis s1, s0 - ftosis s2, s0 - ftosis s31, s0 - - @ Move to VFP from ARM - - fmsr s0, r1 - fmsr s0, r7 - fmsr s0, r14 - fmsr s1, r0 - fmsr s2, r0 - fmsr s31, r0 - fmsr s21, r7 - - fmxr fpsid, r1 - fmxr fpsid, r14 - - @ Move to ARM from VFP - - fmrs r0, s1 - fmrs r0, s2 - fmrs r0, s31 - fmrs r1, s0 - fmrs r7, s0 - fmrs r14, s0 - fmrs r9, s11 - - fmrx r1, fpsid - fmrx r14, fpsid - - @ Load/store operations - - flds s0, [r1] - flds s0, [r14] - flds s0, [r0, #0] - flds s0, [r0, #1020] - flds s0, [r0, #-1020] - flds s1, [r0] - flds s2, [r0] - flds s31, [r0] - fsts s21, [r12, #804] - - @ Load/store multiple operations - - fldmias r0, {s1} - fldmias r0, {s2} - fldmias r0, {s31} - fldmias r0, {s0-s1} - fldmias r0, {s0-s2} - fldmias r0, {s0-s31} - fldmias r0, {s1-s31} - fldmias r0, {s2-s31} - fldmias r0, {s30-s31} - fldmias r1, {s0} - fldmias r14, {s0} - - fstmiax r0, {d1} - fstmiax r0, {d2} - fstmiax r0, {d15} - fstmiax r0, {d0-d1} - fstmiax r0, {d0-d2} - fstmiax r0, {d0-d15} - fstmiax r0, {d1-d15} - fstmiax r0, {d2-d15} - fstmiax r0, {d14-d15} - fstmiax r1, {d0} - fstmiax r14, {d0} - - @ Check that we assemble all the register names correctly - - fcmpzs s0 - fcmpzs s1 - fcmpzs s2 - fcmpzs s3 - fcmpzs s4 - fcmpzs s5 - fcmpzs s6 - fcmpzs s7 - fcmpzs s8 - fcmpzs s9 - fcmpzs s10 - fcmpzs s11 - fcmpzs s12 - fcmpzs s13 - fcmpzs s14 - fcmpzs s15 - fcmpzs s16 - fcmpzs s17 - fcmpzs s18 - fcmpzs s19 - fcmpzs s20 - fcmpzs s21 - fcmpzs s22 - fcmpzs s23 - fcmpzs s24 - fcmpzs s25 - fcmpzs s26 - fcmpzs s27 - fcmpzs s28 - fcmpzs s29 - fcmpzs s30 - fcmpzs s31 - - @ Now we check the placement of the conditional execution substring. - @ On VFP this is always at the end of the instruction. - @ We use different register numbers here to check for correct - @ disassembly - - @ Comparison operations - - fmstateq - - fcmpeseq s3, s7 - fcmpezseq s5 - fcmpseq s1, s2 - fcmpzseq s1 - - @ Monadic data operations - - fabsseq s1, s3 - fcpyseq s31, s19 - fnegseq s20, s8 - fsqrtseq s5, s7 - - @ Dyadic data operations - - faddseq s6, s5, s4 - fdivseq s3, s2, s1 - fmacseq s31, s30, s29 - fmscseq s28, s27, s26 - fmulseq s25, s24, s23 - fnmacseq s22, s21, s20 - fnmscseq s19, s18, s17 - fnmulseq s16, s15, s14 - fsubseq s13, s12, s11 - - @ Load/store operations - - fldseq s10, [r8] - fstseq s9, [r7] - - @ Load/store multiple operations - - fldmiaseq r1, {s8} - fldmfdseq r2, {s7} - fldmiaseq r3!, {s6} - fldmfdseq r4!, {s5} - fldmdbseq r5!, {s4} - fldmeaseq r6!, {s3} - - fldmiaxeq r7, {d1} - fldmfdxeq r8, {d2} - fldmiaxeq r9!, {d3} - fldmfdxeq r10!, {d4} - fldmdbxeq r11!, {d5} - fldmeaxeq r12!, {d6} - - fstmiaseq r13, {s2} - fstmeaseq r14, {s1} - fstmiaseq r1!, {s31} - fstmeaseq r2!, {s30} - fstmdbseq r3!, {s29} - fstmfdseq r4!, {s28} - - fstmiaxeq r5, {d7} - fstmeaxeq r6, {d8} - fstmiaxeq r7!, {d9} - fstmeaxeq r8!, {d10} - fstmdbxeq r9!, {d11} - fstmfdxeq r10!, {d12} - - @ Conversion operations - - fsitoseq s27, s6 - ftosiseq s25, s5 - ftosizseq s23, s4 - ftouiseq s21, s3 - ftouizseq s19, s2 - fuitoseq s17, s1 - - @ ARM from VFP operations - - fmrseq r11, s3 - fmrxeq r9, fpsid - - @ VFP From ARM operations - - fmsreq s3, r9 - fmxreq fpsid, r8 - diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD_t2.d b/binutils-2.17/gas/testsuite/gas/arm/vfp1xD_t2.d deleted file mode 100644 index 327383d0..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD_t2.d +++ /dev/null @@ -1,258 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: Thumb-2 VFP Single-precision instructions -#as: -mfpu=vfpxd - -# Test the ARM VFP Single Precision instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> eef1 fa10 fmstat -0+004 <[^>]*> eeb4 0ac0 fcmpes s0, s0 -0+008 <[^>]*> eeb5 0ac0 fcmpezs s0 -0+00c <[^>]*> eeb4 0a40 fcmps s0, s0 -0+010 <[^>]*> eeb5 0a40 fcmpzs s0 -0+014 <[^>]*> eeb0 0ac0 fabss s0, s0 -0+018 <[^>]*> eeb0 0a40 fcpys s0, s0 -0+01c <[^>]*> eeb1 0a40 fnegs s0, s0 -0+020 <[^>]*> eeb1 0ac0 fsqrts s0, s0 -0+024 <[^>]*> ee30 0a00 fadds s0, s0, s0 -0+028 <[^>]*> ee80 0a00 fdivs s0, s0, s0 -0+02c <[^>]*> ee00 0a00 fmacs s0, s0, s0 -0+030 <[^>]*> ee10 0a00 fmscs s0, s0, s0 -0+034 <[^>]*> ee20 0a00 fmuls s0, s0, s0 -0+038 <[^>]*> ee00 0a40 fnmacs s0, s0, s0 -0+03c <[^>]*> ee10 0a40 fnmscs s0, s0, s0 -0+040 <[^>]*> ee20 0a40 fnmuls s0, s0, s0 -0+044 <[^>]*> ee30 0a40 fsubs s0, s0, s0 -0+048 <[^>]*> ed90 0a00 flds s0, \[r0\] -0+04c <[^>]*> ed80 0a00 fsts s0, \[r0\] -0+050 <[^>]*> ec90 0a01 fldmias r0, {s0} -0+054 <[^>]*> ec90 0a01 fldmias r0, {s0} -0+058 <[^>]*> ecb0 0a01 fldmias r0!, {s0} -0+05c <[^>]*> ecb0 0a01 fldmias r0!, {s0} -0+060 <[^>]*> ed30 0a01 fldmdbs r0!, {s0} -0+064 <[^>]*> ed30 0a01 fldmdbs r0!, {s0} -0+068 <[^>]*> ec90 0b03 fldmiax r0, {d0} -0+06c <[^>]*> ec90 0b03 fldmiax r0, {d0} -0+070 <[^>]*> ecb0 0b03 fldmiax r0!, {d0} -0+074 <[^>]*> ecb0 0b03 fldmiax r0!, {d0} -0+078 <[^>]*> ed30 0b03 fldmdbx r0!, {d0} -0+07c <[^>]*> ed30 0b03 fldmdbx r0!, {d0} -0+080 <[^>]*> ec80 0a01 fstmias r0, {s0} -0+084 <[^>]*> ec80 0a01 fstmias r0, {s0} -0+088 <[^>]*> eca0 0a01 fstmias r0!, {s0} -0+08c <[^>]*> eca0 0a01 fstmias r0!, {s0} -0+090 <[^>]*> ed20 0a01 fstmdbs r0!, {s0} -0+094 <[^>]*> ed20 0a01 fstmdbs r0!, {s0} -0+098 <[^>]*> ec80 0b03 fstmiax r0, {d0} -0+09c <[^>]*> ec80 0b03 fstmiax r0, {d0} -0+0a0 <[^>]*> eca0 0b03 fstmiax r0!, {d0} -0+0a4 <[^>]*> eca0 0b03 fstmiax r0!, {d0} -0+0a8 <[^>]*> ed20 0b03 fstmdbx r0!, {d0} -0+0ac <[^>]*> ed20 0b03 fstmdbx r0!, {d0} -0+0b0 <[^>]*> eeb8 0ac0 fsitos s0, s0 -0+0b4 <[^>]*> eeb8 0a40 fuitos s0, s0 -0+0b8 <[^>]*> eebd 0a40 ftosis s0, s0 -0+0bc <[^>]*> eebd 0ac0 ftosizs s0, s0 -0+0c0 <[^>]*> eebc 0a40 ftouis s0, s0 -0+0c4 <[^>]*> eebc 0ac0 ftouizs s0, s0 -0+0c8 <[^>]*> ee10 0a10 fmrs r0, s0 -0+0cc <[^>]*> eef0 0a10 fmrx r0, fpsid -0+0d0 <[^>]*> eef1 0a10 fmrx r0, fpscr -0+0d4 <[^>]*> eef8 0a10 fmrx r0, fpexc -0+0d8 <[^>]*> ee00 0a10 fmsr s0, r0 -0+0dc <[^>]*> eee0 0a10 fmxr fpsid, r0 -0+0e0 <[^>]*> eee1 0a10 fmxr fpscr, r0 -0+0e4 <[^>]*> eee8 0a10 fmxr fpexc, r0 -0+0e8 <[^>]*> eef5 0a40 fcmpzs s1 -0+0ec <[^>]*> eeb5 1a40 fcmpzs s2 -0+0f0 <[^>]*> eef5 fa40 fcmpzs s31 -0+0f4 <[^>]*> eeb4 0a60 fcmps s0, s1 -0+0f8 <[^>]*> eeb4 0a41 fcmps s0, s2 -0+0fc <[^>]*> eeb4 0a6f fcmps s0, s31 -0+100 <[^>]*> eef4 0a40 fcmps s1, s0 -0+104 <[^>]*> eeb4 1a40 fcmps s2, s0 -0+108 <[^>]*> eef4 fa40 fcmps s31, s0 -0+10c <[^>]*> eef4 aa46 fcmps s21, s12 -0+110 <[^>]*> eeb1 0a60 fnegs s0, s1 -0+114 <[^>]*> eeb1 0a41 fnegs s0, s2 -0+118 <[^>]*> eeb1 0a6f fnegs s0, s31 -0+11c <[^>]*> eef1 0a40 fnegs s1, s0 -0+120 <[^>]*> eeb1 1a40 fnegs s2, s0 -0+124 <[^>]*> eef1 fa40 fnegs s31, s0 -0+128 <[^>]*> eeb1 6a6a fnegs s12, s21 -0+12c <[^>]*> ee30 0a20 fadds s0, s0, s1 -0+130 <[^>]*> ee30 0a01 fadds s0, s0, s2 -0+134 <[^>]*> ee30 0a2f fadds s0, s0, s31 -0+138 <[^>]*> ee30 0a80 fadds s0, s1, s0 -0+13c <[^>]*> ee31 0a00 fadds s0, s2, s0 -0+140 <[^>]*> ee3f 0a80 fadds s0, s31, s0 -0+144 <[^>]*> ee70 0a00 fadds s1, s0, s0 -0+148 <[^>]*> ee30 1a00 fadds s2, s0, s0 -0+14c <[^>]*> ee70 fa00 fadds s31, s0, s0 -0+150 <[^>]*> ee3a 6aa2 fadds s12, s21, s5 -0+154 <[^>]*> eeb8 0ae0 fsitos s0, s1 -0+158 <[^>]*> eeb8 0ac1 fsitos s0, s2 -0+15c <[^>]*> eeb8 0aef fsitos s0, s31 -0+160 <[^>]*> eef8 0ac0 fsitos s1, s0 -0+164 <[^>]*> eeb8 1ac0 fsitos s2, s0 -0+168 <[^>]*> eef8 fac0 fsitos s31, s0 -0+16c <[^>]*> eebd 0a60 ftosis s0, s1 -0+170 <[^>]*> eebd 0a41 ftosis s0, s2 -0+174 <[^>]*> eebd 0a6f ftosis s0, s31 -0+178 <[^>]*> eefd 0a40 ftosis s1, s0 -0+17c <[^>]*> eebd 1a40 ftosis s2, s0 -0+180 <[^>]*> eefd fa40 ftosis s31, s0 -0+184 <[^>]*> ee00 1a10 fmsr s0, r1 -0+188 <[^>]*> ee00 7a10 fmsr s0, r7 -0+18c <[^>]*> ee00 ea10 fmsr s0, lr -0+190 <[^>]*> ee00 0a90 fmsr s1, r0 -0+194 <[^>]*> ee01 0a10 fmsr s2, r0 -0+198 <[^>]*> ee0f 0a90 fmsr s31, r0 -0+19c <[^>]*> ee0a 7a90 fmsr s21, r7 -0+1a0 <[^>]*> eee0 1a10 fmxr fpsid, r1 -0+1a4 <[^>]*> eee0 ea10 fmxr fpsid, lr -0+1a8 <[^>]*> ee10 0a90 fmrs r0, s1 -0+1ac <[^>]*> ee11 0a10 fmrs r0, s2 -0+1b0 <[^>]*> ee1f 0a90 fmrs r0, s31 -0+1b4 <[^>]*> ee10 1a10 fmrs r1, s0 -0+1b8 <[^>]*> ee10 7a10 fmrs r7, s0 -0+1bc <[^>]*> ee10 ea10 fmrs lr, s0 -0+1c0 <[^>]*> ee15 9a90 fmrs r9, s11 -0+1c4 <[^>]*> eef0 1a10 fmrx r1, fpsid -0+1c8 <[^>]*> eef0 ea10 fmrx lr, fpsid -0+1cc <[^>]*> ed91 0a00 flds s0, \[r1\] -0+1d0 <[^>]*> ed9e 0a00 flds s0, \[lr\] -0+1d4 <[^>]*> ed90 0a00 flds s0, \[r0\] -0+1d8 <[^>]*> ed90 0aff flds s0, \[r0, #1020\] -0+1dc <[^>]*> ed10 0aff flds s0, \[r0, #-1020\] -0+1e0 <[^>]*> edd0 0a00 flds s1, \[r0\] -0+1e4 <[^>]*> ed90 1a00 flds s2, \[r0\] -0+1e8 <[^>]*> edd0 fa00 flds s31, \[r0\] -0+1ec <[^>]*> edcc aac9 fsts s21, \[ip, #804\] -0+1f0 <[^>]*> ecd0 0a01 fldmias r0, {s1} -0+1f4 <[^>]*> ec90 1a01 fldmias r0, {s2} -0+1f8 <[^>]*> ecd0 fa01 fldmias r0, {s31} -0+1fc <[^>]*> ec90 0a02 fldmias r0, {s0-s1} -0+200 <[^>]*> ec90 0a03 fldmias r0, {s0-s2} -0+204 <[^>]*> ec90 0a20 fldmias r0, {s0-s31} -0+208 <[^>]*> ecd0 0a1f fldmias r0, {s1-s31} -0+20c <[^>]*> ec90 1a1e fldmias r0, {s2-s31} -0+210 <[^>]*> ec90 fa02 fldmias r0, {s30-s31} -0+214 <[^>]*> ec91 0a01 fldmias r1, {s0} -0+218 <[^>]*> ec9e 0a01 fldmias lr, {s0} -0+21c <[^>]*> ec80 1b03 fstmiax r0, {d1} -0+220 <[^>]*> ec80 2b03 fstmiax r0, {d2} -0+224 <[^>]*> ec80 fb03 fstmiax r0, {d15} -0+228 <[^>]*> ec80 0b05 fstmiax r0, {d0-d1} -0+22c <[^>]*> ec80 0b07 fstmiax r0, {d0-d2} -0+230 <[^>]*> ec80 0b21 fstmiax r0, {d0-d15} -0+234 <[^>]*> ec80 1b1f fstmiax r0, {d1-d15} -0+238 <[^>]*> ec80 2b1d fstmiax r0, {d2-d15} -0+23c <[^>]*> ec80 eb05 fstmiax r0, {d14-d15} -0+240 <[^>]*> ec81 0b03 fstmiax r1, {d0} -0+244 <[^>]*> ec8e 0b03 fstmiax lr, {d0} -0+248 <[^>]*> eeb5 0a40 fcmpzs s0 -0+24c <[^>]*> eef5 0a40 fcmpzs s1 -0+250 <[^>]*> eeb5 1a40 fcmpzs s2 -0+254 <[^>]*> eef5 1a40 fcmpzs s3 -0+258 <[^>]*> eeb5 2a40 fcmpzs s4 -0+25c <[^>]*> eef5 2a40 fcmpzs s5 -0+260 <[^>]*> eeb5 3a40 fcmpzs s6 -0+264 <[^>]*> eef5 3a40 fcmpzs s7 -0+268 <[^>]*> eeb5 4a40 fcmpzs s8 -0+26c <[^>]*> eef5 4a40 fcmpzs s9 -0+270 <[^>]*> eeb5 5a40 fcmpzs s10 -0+274 <[^>]*> eef5 5a40 fcmpzs s11 -0+278 <[^>]*> eeb5 6a40 fcmpzs s12 -0+27c <[^>]*> eef5 6a40 fcmpzs s13 -0+280 <[^>]*> eeb5 7a40 fcmpzs s14 -0+284 <[^>]*> eef5 7a40 fcmpzs s15 -0+288 <[^>]*> eeb5 8a40 fcmpzs s16 -0+28c <[^>]*> eef5 8a40 fcmpzs s17 -0+290 <[^>]*> eeb5 9a40 fcmpzs s18 -0+294 <[^>]*> eef5 9a40 fcmpzs s19 -0+298 <[^>]*> eeb5 aa40 fcmpzs s20 -0+29c <[^>]*> eef5 aa40 fcmpzs s21 -0+2a0 <[^>]*> eeb5 ba40 fcmpzs s22 -0+2a4 <[^>]*> eef5 ba40 fcmpzs s23 -0+2a8 <[^>]*> eeb5 ca40 fcmpzs s24 -0+2ac <[^>]*> eef5 ca40 fcmpzs s25 -0+2b0 <[^>]*> eeb5 da40 fcmpzs s26 -0+2b4 <[^>]*> eef5 da40 fcmpzs s27 -0+2b8 <[^>]*> eeb5 ea40 fcmpzs s28 -0+2bc <[^>]*> eef5 ea40 fcmpzs s29 -0+2c0 <[^>]*> eeb5 fa40 fcmpzs s30 -0+2c4 <[^>]*> eef5 fa40 fcmpzs s31 -# The "(eq|)" should be replaces by "eq" once the disassembler is fixed. -0+2c8 <[^>]*> bf01 itttt eq -0+2ca <[^>]*> eef1 fa10 fmstat(eq|) -0+2ce <[^>]*> eef4 1ae3 fcmpes(eq|) s3, s7 -0+2d2 <[^>]*> eef5 2ac0 fcmpezs(eq|) s5 -0+2d6 <[^>]*> eef4 0a41 fcmps(eq|) s1, s2 -0+2da <[^>]*> bf01 itttt eq -0+2dc <[^>]*> eef5 0a40 fcmpzs(eq|) s1 -0+2e0 <[^>]*> eef0 0ae1 fabss(eq|) s1, s3 -0+2e4 <[^>]*> eef0 fa69 fcpys(eq|) s31, s19 -0+2e8 <[^>]*> eeb1 aa44 fnegs(eq|) s20, s8 -0+2ec <[^>]*> bf01 itttt eq -0+2ee <[^>]*> eef1 2ae3 fsqrts(eq|) s5, s7 -0+2f2 <[^>]*> ee32 3a82 fadds(eq|) s6, s5, s4 -0+2f6 <[^>]*> eec1 1a20 fdivs(eq|) s3, s2, s1 -0+2fa <[^>]*> ee4f fa2e fmacs(eq|) s31, s30, s29 -0+2fe <[^>]*> bf01 itttt eq -0+300 <[^>]*> ee1d ea8d fmscs(eq|) s28, s27, s26 -0+304 <[^>]*> ee6c ca2b fmuls(eq|) s25, s24, s23 -0+308 <[^>]*> ee0a baca fnmacs(eq|) s22, s21, s20 -0+30c <[^>]*> ee59 9a68 fnmscs(eq|) s19, s18, s17 -0+310 <[^>]*> bf01 itttt eq -0+312 <[^>]*> ee27 8ac7 fnmuls(eq|) s16, s15, s14 -0+316 <[^>]*> ee76 6a65 fsubs(eq|) s13, s12, s11 -0+31a <[^>]*> ed98 5a00 flds(eq|) s10, \[r8\] -0+31e <[^>]*> edc7 4a00 fsts(eq|) s9, \[r7\] -0+322 <[^>]*> bf01 itttt eq -0+324 <[^>]*> ec91 4a01 fldmias(eq|) r1, {s8} -0+328 <[^>]*> ecd2 3a01 fldmias(eq|) r2, {s7} -0+32c <[^>]*> ecb3 3a01 fldmias(eq|) r3!, {s6} -0+330 <[^>]*> ecf4 2a01 fldmias(eq|) r4!, {s5} -0+334 <[^>]*> bf01 itttt eq -0+336 <[^>]*> ed35 2a01 fldmdbs(eq|) r5!, {s4} -0+33a <[^>]*> ed76 1a01 fldmdbs(eq|) r6!, {s3} -0+33e <[^>]*> ec97 1b03 fldmiax(eq|) r7, {d1} -0+342 <[^>]*> ec98 2b03 fldmiax(eq|) r8, {d2} -0+346 <[^>]*> bf01 itttt eq -0+348 <[^>]*> ecb9 3b03 fldmiax(eq|) r9!, {d3} -0+34c <[^>]*> ecba 4b03 fldmiax(eq|) sl!, {d4} -0+350 <[^>]*> ed3b 5b03 fldmdbx(eq|) fp!, {d5} -0+354 <[^>]*> ed3c 6b03 fldmdbx(eq|) ip!, {d6} -0+358 <[^>]*> bf01 itttt eq -0+35a <[^>]*> ec8d 1a01 fstmias(eq|) sp, {s2} -0+35e <[^>]*> ecce 0a01 fstmias(eq|) lr, {s1} -0+362 <[^>]*> ece1 fa01 fstmias(eq|) r1!, {s31} -0+366 <[^>]*> eca2 fa01 fstmias(eq|) r2!, {s30} -0+36a <[^>]*> bf01 itttt eq -0+36c <[^>]*> ed63 ea01 fstmdbs(eq|) r3!, {s29} -0+370 <[^>]*> ed24 ea01 fstmdbs(eq|) r4!, {s28} -0+374 <[^>]*> ec85 7b03 fstmiax(eq|) r5, {d7} -0+378 <[^>]*> ec86 8b03 fstmiax(eq|) r6, {d8} -0+37c <[^>]*> bf01 itttt eq -0+37e <[^>]*> eca7 9b03 fstmiax(eq|) r7!, {d9} -0+382 <[^>]*> eca8 ab03 fstmiax(eq|) r8!, {d10} -0+386 <[^>]*> ed29 bb03 fstmdbx(eq|) r9!, {d11} -0+38a <[^>]*> ed2a cb03 fstmdbx(eq|) sl!, {d12} -0+38e <[^>]*> bf01 itttt eq -0+390 <[^>]*> eef8 dac3 fsitos(eq|) s27, s6 -0+394 <[^>]*> eefd ca62 ftosis(eq|) s25, s5 -0+398 <[^>]*> eefd bac2 ftosizs(eq|) s23, s4 -0+39c <[^>]*> eefc aa61 ftouis(eq|) s21, s3 -0+3a0 <[^>]*> bf01 itttt eq -0+3a2 <[^>]*> eefc 9ac1 ftouizs(eq|) s19, s2 -0+3a6 <[^>]*> eef8 8a60 fuitos(eq|) s17, s1 -0+3aa <[^>]*> ee11 ba90 fmrs(eq|) fp, s3 -0+3ae <[^>]*> eef0 9a10 fmrx(eq|) r9, fpsid -0+3b2 <[^>]*> bf04 itt eq -0+3b4 <[^>]*> ee01 9a90 fmsr(eq|) s3, r9 -0+3b8 <[^>]*> eee0 8a10 fmxr(eq|) fpsid, r8 -0+3bc <[^>]*> bf00 nop -0+3be <[^>]*> bf00 nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD_t2.s b/binutils-2.17/gas/testsuite/gas/arm/vfp1xD_t2.s deleted file mode 100644 index f3087a37..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp1xD_t2.s +++ /dev/null @@ -1,359 +0,0 @@ -@ VFP Instructions for v1xD variants (Single precision only) -@ Same as vfp1xD.s, but for Thumb-2 - .syntax unified - .thumb - .text - .global F -F: - @ First we test the basic syntax and bit patterns of the opcodes. - @ Most of these tests deliberatly use s0/r0 to avoid setting - @ any more bits than necessary. - - @ Comparison operations - - fmstat - - fcmpes s0, s0 - fcmpezs s0 - fcmps s0, s0 - fcmpzs s0 - - @ Monadic data operations - - fabss s0, s0 - fcpys s0, s0 - fnegs s0, s0 - fsqrts s0, s0 - - @ Dyadic data operations - - fadds s0, s0, s0 - fdivs s0, s0, s0 - fmacs s0, s0, s0 - fmscs s0, s0, s0 - fmuls s0, s0, s0 - fnmacs s0, s0, s0 - fnmscs s0, s0, s0 - fnmuls s0, s0, s0 - fsubs s0, s0, s0 - - @ Load/store operations - - flds s0, [r0] - fsts s0, [r0] - - @ Load/store multiple operations - - fldmias r0, {s0} - fldmfds r0, {s0} - fldmias r0!, {s0} - fldmfds r0!, {s0} - fldmdbs r0!, {s0} - fldmeas r0!, {s0} - - fldmiax r0, {d0} - fldmfdx r0, {d0} - fldmiax r0!, {d0} - fldmfdx r0!, {d0} - fldmdbx r0!, {d0} - fldmeax r0!, {d0} - - fstmias r0, {s0} - fstmeas r0, {s0} - fstmias r0!, {s0} - fstmeas r0!, {s0} - fstmdbs r0!, {s0} - fstmfds r0!, {s0} - - fstmiax r0, {d0} - fstmeax r0, {d0} - fstmiax r0!, {d0} - fstmeax r0!, {d0} - fstmdbx r0!, {d0} - fstmfdx r0!, {d0} - - @ Conversion operations - - fsitos s0, s0 - fuitos s0, s0 - - ftosis s0, s0 - ftosizs s0, s0 - ftouis s0, s0 - ftouizs s0, s0 - - @ ARM from VFP operations - - fmrs r0, s0 - fmrx r0, fpsid - fmrx r0, fpscr - fmrx r0, fpexc - - @ VFP From ARM operations - - fmsr s0, r0 - fmxr fpsid, r0 - fmxr fpscr, r0 - fmxr fpexc, r0 - - @ Now we test that the register fields are updated correctly for - @ each class of instruction. - - @ Single register operations (compare-zero): - - fcmpzs s1 - fcmpzs s2 - fcmpzs s31 - - @ Two register comparison operations: - - fcmps s0, s1 - fcmps s0, s2 - fcmps s0, s31 - fcmps s1, s0 - fcmps s2, s0 - fcmps s31, s0 - fcmps s21, s12 - - @ Two register data operations (monadic) - - fnegs s0, s1 - fnegs s0, s2 - fnegs s0, s31 - fnegs s1, s0 - fnegs s2, s0 - fnegs s31, s0 - fnegs s12, s21 - - @ Three register data operations (dyadic) - - fadds s0, s0, s1 - fadds s0, s0, s2 - fadds s0, s0, s31 - fadds s0, s1, s0 - fadds s0, s2, s0 - fadds s0, s31, s0 - fadds s1, s0, s0 - fadds s2, s0, s0 - fadds s31, s0, s0 - fadds s12, s21, s5 - - @ Conversion operations - - fsitos s0, s1 - fsitos s0, s2 - fsitos s0, s31 - fsitos s1, s0 - fsitos s2, s0 - fsitos s31, s0 - - ftosis s0, s1 - ftosis s0, s2 - ftosis s0, s31 - ftosis s1, s0 - ftosis s2, s0 - ftosis s31, s0 - - @ Move to VFP from ARM - - fmsr s0, r1 - fmsr s0, r7 - fmsr s0, r14 - fmsr s1, r0 - fmsr s2, r0 - fmsr s31, r0 - fmsr s21, r7 - - fmxr fpsid, r1 - fmxr fpsid, r14 - - @ Move to ARM from VFP - - fmrs r0, s1 - fmrs r0, s2 - fmrs r0, s31 - fmrs r1, s0 - fmrs r7, s0 - fmrs r14, s0 - fmrs r9, s11 - - fmrx r1, fpsid - fmrx r14, fpsid - - @ Load/store operations - - flds s0, [r1] - flds s0, [r14] - flds s0, [r0, #0] - flds s0, [r0, #1020] - flds s0, [r0, #-1020] - flds s1, [r0] - flds s2, [r0] - flds s31, [r0] - fsts s21, [r12, #804] - - @ Load/store multiple operations - - fldmias r0, {s1} - fldmias r0, {s2} - fldmias r0, {s31} - fldmias r0, {s0-s1} - fldmias r0, {s0-s2} - fldmias r0, {s0-s31} - fldmias r0, {s1-s31} - fldmias r0, {s2-s31} - fldmias r0, {s30-s31} - fldmias r1, {s0} - fldmias r14, {s0} - - fstmiax r0, {d1} - fstmiax r0, {d2} - fstmiax r0, {d15} - fstmiax r0, {d0-d1} - fstmiax r0, {d0-d2} - fstmiax r0, {d0-d15} - fstmiax r0, {d1-d15} - fstmiax r0, {d2-d15} - fstmiax r0, {d14-d15} - fstmiax r1, {d0} - fstmiax r14, {d0} - - @ Check that we assemble all the register names correctly - - fcmpzs s0 - fcmpzs s1 - fcmpzs s2 - fcmpzs s3 - fcmpzs s4 - fcmpzs s5 - fcmpzs s6 - fcmpzs s7 - fcmpzs s8 - fcmpzs s9 - fcmpzs s10 - fcmpzs s11 - fcmpzs s12 - fcmpzs s13 - fcmpzs s14 - fcmpzs s15 - fcmpzs s16 - fcmpzs s17 - fcmpzs s18 - fcmpzs s19 - fcmpzs s20 - fcmpzs s21 - fcmpzs s22 - fcmpzs s23 - fcmpzs s24 - fcmpzs s25 - fcmpzs s26 - fcmpzs s27 - fcmpzs s28 - fcmpzs s29 - fcmpzs s30 - fcmpzs s31 - - @ Now we check the placement of the conditional execution substring. - @ On VFP this is always at the end of the instruction. - @ We use different register numbers here to check for correct - @ disassembly - - @ Comparison operations - - itttt eq - fmstateq - - fcmpeseq s3, s7 - fcmpezseq s5 - fcmpseq s1, s2 - itttt eq - fcmpzseq s1 - - @ Monadic data operations - - fabsseq s1, s3 - fcpyseq s31, s19 - fnegseq s20, s8 - itttt eq - fsqrtseq s5, s7 - - @ Dyadic data operations - - faddseq s6, s5, s4 - fdivseq s3, s2, s1 - fmacseq s31, s30, s29 - itttt eq - fmscseq s28, s27, s26 - fmulseq s25, s24, s23 - fnmacseq s22, s21, s20 - fnmscseq s19, s18, s17 - itttt eq - fnmulseq s16, s15, s14 - fsubseq s13, s12, s11 - - @ Load/store operations - - fldseq s10, [r8] - fstseq s9, [r7] - - @ Load/store multiple operations - - itttt eq - fldmiaseq r1, {s8} - fldmfdseq r2, {s7} - fldmiaseq r3!, {s6} - fldmfdseq r4!, {s5} - itttt eq - fldmdbseq r5!, {s4} - fldmeaseq r6!, {s3} - - fldmiaxeq r7, {d1} - fldmfdxeq r8, {d2} - itttt eq - fldmiaxeq r9!, {d3} - fldmfdxeq r10!, {d4} - fldmdbxeq r11!, {d5} - fldmeaxeq r12!, {d6} - - itttt eq - fstmiaseq r13, {s2} - fstmeaseq r14, {s1} - fstmiaseq r1!, {s31} - fstmeaseq r2!, {s30} - itttt eq - fstmdbseq r3!, {s29} - fstmfdseq r4!, {s28} - - fstmiaxeq r5, {d7} - fstmeaxeq r6, {d8} - itttt eq - fstmiaxeq r7!, {d9} - fstmeaxeq r8!, {d10} - fstmdbxeq r9!, {d11} - fstmfdxeq r10!, {d12} - - @ Conversion operations - - itttt eq - fsitoseq s27, s6 - ftosiseq s25, s5 - ftosizseq s23, s4 - ftouiseq s21, s3 - itttt eq - ftouizseq s19, s2 - fuitoseq s17, s1 - - @ ARM from VFP operations - - fmrseq r11, s3 - fmrxeq r9, fpsid - - @ VFP From ARM operations - - itt eq - fmsreq s3, r9 - fmxreq fpsid, r8 - - @ 2 nops to pad to 16-byte boundary - nop - nop diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp2.d b/binutils-2.17/gas/testsuite/gas/arm/vfp2.d deleted file mode 100644 index f9b60960..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp2.d +++ /dev/null @@ -1,17 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: VFP Additional instructions -#as: -mfpu=vfp - -# Test the ARM VFP Double Precision instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> ec4a5b10 fmdrr d0, r5, sl -0+004 <[^>]*> ec5a5b10 fmrrd r5, sl, d0 -0+008 <[^>]*> ec4a5a37 fmsrr r5, sl, {s15, s16} -0+00c <[^>]*> ec5a5a37 fmrrs r5, sl, {s15, s16} -0+010 <[^>]*> ec45ab1f fmdrr d15, sl, r5 -0+014 <[^>]*> ec55ab1f fmrrd sl, r5, d15 -0+018 <[^>]*> ec45aa38 fmsrr sl, r5, {s17, s18} -0+01c <[^>]*> ec55aa38 fmrrs sl, r5, {s17, s18} diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp2.s b/binutils-2.17/gas/testsuite/gas/arm/vfp2.s deleted file mode 100644 index 8a293abb..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp2.s +++ /dev/null @@ -1,18 +0,0 @@ -@ VFP2 Additional instructions - .text - .global F -F: - @ First we test the basic syntax and bit patterns of the opcodes. - @ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise - @ the full register bitpatterns - - fmdrr d0, r5, r10 - fmrrd r5, r10, d0 - fmsrr {s15, s16}, r5, r10 - fmrrs r5, r10, {s15, s16} - - fmdrr d15, r10, r5 - fmrrd r10, r5, d15 - fmsrr {s17, s18}, r10, r5 - fmrrs r10, r5, {s17, s18} - diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp2_t2.d b/binutils-2.17/gas/testsuite/gas/arm/vfp2_t2.d deleted file mode 100644 index bb988e54..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp2_t2.d +++ /dev/null @@ -1,17 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: Thumb-2 VFP Additional instructions -#as: -mfpu=vfp - -# Test the ARM VFP Double Precision instructions - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> ec4a 5b10 fmdrr d0, r5, sl -0+004 <[^>]*> ec5a 5b10 fmrrd r5, sl, d0 -0+008 <[^>]*> ec4a 5a37 fmsrr r5, sl, {s15, s16} -0+00c <[^>]*> ec5a 5a37 fmrrs r5, sl, {s15, s16} -0+010 <[^>]*> ec45 ab1f fmdrr d15, sl, r5 -0+014 <[^>]*> ec55 ab1f fmrrd sl, r5, d15 -0+018 <[^>]*> ec45 aa38 fmsrr sl, r5, {s17, s18} -0+01c <[^>]*> ec55 aa38 fmrrs sl, r5, {s17, s18} diff --git a/binutils-2.17/gas/testsuite/gas/arm/vfp2_t2.s b/binutils-2.17/gas/testsuite/gas/arm/vfp2_t2.s deleted file mode 100644 index ba5551b6..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/vfp2_t2.s +++ /dev/null @@ -1,21 +0,0 @@ -@ VFP2 Additional instructions -@ Same as vfp2.s, but for Thumb-2 - .syntax unified - .thumb - .text - .global F -F: - @ First we test the basic syntax and bit patterns of the opcodes. - @ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise - @ the full register bitpatterns - - fmdrr d0, r5, r10 - fmrrd r5, r10, d0 - fmsrr {s15, s16}, r5, r10 - fmrrs r5, r10, {s15, s16} - - fmdrr d15, r10, r5 - fmrrd r10, r5, d15 - fmsrr {s17, s18}, r10, r5 - fmrrs r10, r5, {s17, s18} - diff --git a/binutils-2.17/gas/testsuite/gas/arm/wince_inst.d b/binutils-2.17/gas/testsuite/gas/arm/wince_inst.d deleted file mode 100644 index a9852e03..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/wince_inst.d +++ /dev/null @@ -1,205 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: ARM basic instructions (WinCE version) -#as: -mcpu=arm7m -EL -#source: inst.s -# inst.d is used for non-WinCE targets. -#not-skip: *-wince-* - -# This file is the same as inst.d except that the BL -# instructions have not had a -8 bias inserted. - -.*: +file format .*arm.* - -Disassembly of section .text: -0+000 <[^>]*> e3a00000 ? mov r0, #0 ; 0x0 -0+004 <[^>]*> e1a01002 ? mov r1, r2 -0+008 <[^>]*> e1a03184 ? mov r3, r4, lsl #3 -0+00c <[^>]*> e1a05736 ? mov r5, r6, lsr r7 -0+010 <[^>]*> e1a08a59 ? mov r8, r9, asr sl -0+014 <[^>]*> e1a0bd1c ? mov fp, ip, lsl sp -0+018 <[^>]*> e1a0e06f ? mov lr, pc, rrx -0+01c <[^>]*> e1a01002 ? mov r1, r2 -0+020 <[^>]*> 01a02003 ? moveq r2, r3 -0+024 <[^>]*> 11a04005 ? movne r4, r5 -0+028 <[^>]*> b1a06007 ? movlt r6, r7 -0+02c <[^>]*> a1a08009 ? movge r8, r9 -0+030 <[^>]*> d1a0a00b ? movle sl, fp -0+034 <[^>]*> c1a0c00d ? movgt ip, sp -0+038 <[^>]*> 31a01002 ? movcc r1, r2 -0+03c <[^>]*> 21a01003 ? movcs r1, r3 -0+040 <[^>]*> 41a03006 ? movmi r3, r6 -0+044 <[^>]*> 51a07009 ? movpl r7, r9 -0+048 <[^>]*> 61a01008 ? movvs r1, r8 -0+04c <[^>]*> 71a09fa1 ? movvc r9, r1, lsr #31 -0+050 <[^>]*> 81a0800f ? movhi r8, pc -0+054 <[^>]*> 91a0f00e ? movls pc, lr -0+058 <[^>]*> 21a09008 ? movcs r9, r8 -0+05c <[^>]*> 31a01003 ? movcc r1, r3 -0+060 <[^>]*> e1b00008 ? movs r0, r8 -0+064 <[^>]*> 31b00007 ? movccs r0, r7 -0+068 <[^>]*> e281000a ? add r0, r1, #10 ; 0xa -0+06c <[^>]*> e0832004 ? add r2, r3, r4 -0+070 <[^>]*> e0865287 ? add r5, r6, r7, lsl #5 -0+074 <[^>]*> e0821113 ? add r1, r2, r3, lsl r1 -0+078 <[^>]*> e201000a ? and r0, r1, #10 ; 0xa -0+07c <[^>]*> e0032004 ? and r2, r3, r4 -0+080 <[^>]*> e0065287 ? and r5, r6, r7, lsl #5 -0+084 <[^>]*> e0021113 ? and r1, r2, r3, lsl r1 -0+088 <[^>]*> e221000a ? eor r0, r1, #10 ; 0xa -0+08c <[^>]*> e0232004 ? eor r2, r3, r4 -0+090 <[^>]*> e0265287 ? eor r5, r6, r7, lsl #5 -0+094 <[^>]*> e0221113 ? eor r1, r2, r3, lsl r1 -0+098 <[^>]*> e241000a ? sub r0, r1, #10 ; 0xa -0+09c <[^>]*> e0432004 ? sub r2, r3, r4 -0+0a0 <[^>]*> e0465287 ? sub r5, r6, r7, lsl #5 -0+0a4 <[^>]*> e0421113 ? sub r1, r2, r3, lsl r1 -0+0a8 <[^>]*> e2a1000a ? adc r0, r1, #10 ; 0xa -0+0ac <[^>]*> e0a32004 ? adc r2, r3, r4 -0+0b0 <[^>]*> e0a65287 ? adc r5, r6, r7, lsl #5 -0+0b4 <[^>]*> e0a21113 ? adc r1, r2, r3, lsl r1 -0+0b8 <[^>]*> e2c1000a ? sbc r0, r1, #10 ; 0xa -0+0bc <[^>]*> e0c32004 ? sbc r2, r3, r4 -0+0c0 <[^>]*> e0c65287 ? sbc r5, r6, r7, lsl #5 -0+0c4 <[^>]*> e0c21113 ? sbc r1, r2, r3, lsl r1 -0+0c8 <[^>]*> e261000a ? rsb r0, r1, #10 ; 0xa -0+0cc <[^>]*> e0632004 ? rsb r2, r3, r4 -0+0d0 <[^>]*> e0665287 ? rsb r5, r6, r7, lsl #5 -0+0d4 <[^>]*> e0621113 ? rsb r1, r2, r3, lsl r1 -0+0d8 <[^>]*> e2e1000a ? rsc r0, r1, #10 ; 0xa -0+0dc <[^>]*> e0e32004 ? rsc r2, r3, r4 -0+0e0 <[^>]*> e0e65287 ? rsc r5, r6, r7, lsl #5 -0+0e4 <[^>]*> e0e21113 ? rsc r1, r2, r3, lsl r1 -0+0e8 <[^>]*> e381000a ? orr r0, r1, #10 ; 0xa -0+0ec <[^>]*> e1832004 ? orr r2, r3, r4 -0+0f0 <[^>]*> e1865287 ? orr r5, r6, r7, lsl #5 -0+0f4 <[^>]*> e1821113 ? orr r1, r2, r3, lsl r1 -0+0f8 <[^>]*> e3c1000a ? bic r0, r1, #10 ; 0xa -0+0fc <[^>]*> e1c32004 ? bic r2, r3, r4 -0+100 <[^>]*> e1c65287 ? bic r5, r6, r7, lsl #5 -0+104 <[^>]*> e1c21113 ? bic r1, r2, r3, lsl r1 -0+108 <[^>]*> e3e0000a ? mvn r0, #10 ; 0xa -0+10c <[^>]*> e1e02004 ? mvn r2, r4 -0+110 <[^>]*> e1e05287 ? mvn r5, r7, lsl #5 -0+114 <[^>]*> e1e01113 ? mvn r1, r3, lsl r1 -0+118 <[^>]*> e310000a ? tst r0, #10 ; 0xa -0+11c <[^>]*> e1120004 ? tst r2, r4 -0+120 <[^>]*> e1150287 ? tst r5, r7, lsl #5 -0+124 <[^>]*> e1110113 ? tst r1, r3, lsl r1 -0+128 <[^>]*> e330000a ? teq r0, #10 ; 0xa -0+12c <[^>]*> e1320004 ? teq r2, r4 -0+130 <[^>]*> e1350287 ? teq r5, r7, lsl #5 -0+134 <[^>]*> e1310113 ? teq r1, r3, lsl r1 -0+138 <[^>]*> e350000a ? cmp r0, #10 ; 0xa -0+13c <[^>]*> e1520004 ? cmp r2, r4 -0+140 <[^>]*> e1550287 ? cmp r5, r7, lsl #5 -0+144 <[^>]*> e1510113 ? cmp r1, r3, lsl r1 -0+148 <[^>]*> e370000a ? cmn r0, #10 ; 0xa -0+14c <[^>]*> e1720004 ? cmn r2, r4 -0+150 <[^>]*> e1750287 ? cmn r5, r7, lsl #5 -0+154 <[^>]*> e1710113 ? cmn r1, r3, lsl r1 -0+158 <[^>]*> e330f00a ? teqp r0, #10 ; 0xa -0+15c <[^>]*> e132f004 ? teqp r2, r4 -0+160 <[^>]*> e135f287 ? teqp r5, r7, lsl #5 -0+164 <[^>]*> e131f113 ? teqp r1, r3, lsl r1 -0+168 <[^>]*> e370f00a ? cmnp r0, #10 ; 0xa -0+16c <[^>]*> e172f004 ? cmnp r2, r4 -0+170 <[^>]*> e175f287 ? cmnp r5, r7, lsl #5 -0+174 <[^>]*> e171f113 ? cmnp r1, r3, lsl r1 -0+178 <[^>]*> e350f00a ? cmpp r0, #10 ; 0xa -0+17c <[^>]*> e152f004 ? cmpp r2, r4 -0+180 <[^>]*> e155f287 ? cmpp r5, r7, lsl #5 -0+184 <[^>]*> e151f113 ? cmpp r1, r3, lsl r1 -0+188 <[^>]*> e310f00a ? tstp r0, #10 ; 0xa -0+18c <[^>]*> e112f004 ? tstp r2, r4 -0+190 <[^>]*> e115f287 ? tstp r5, r7, lsl #5 -0+194 <[^>]*> e111f113 ? tstp r1, r3, lsl r1 -0+198 <[^>]*> e0000291 ? mul r0, r1, r2 -0+19c <[^>]*> e0110392 ? muls r1, r2, r3 -0+1a0 <[^>]*> 10000091 ? mulne r0, r1, r0 -0+1a4 <[^>]*> 90190798 ? mullss r9, r8, r7 -0+1a8 <[^>]*> e021ba99 ? mla r1, r9, sl, fp -0+1ac <[^>]*> e033c994 ? mlas r3, r4, r9, ip -0+1b0 <[^>]*> b029d798 ? mlalt r9, r8, r7, sp -0+1b4 <[^>]*> a034e391 ? mlages r4, r1, r3, lr -0+1b8 <[^>]*> e5910000 ? ldr r0, \[r1\] -0+1bc <[^>]*> e7911002 ? ldr r1, \[r1, r2\] -0+1c0 <[^>]*> e7b32004 ? ldr r2, \[r3, r4\]! -0+1c4 <[^>]*> e5922020 ? ldr r2, \[r2, #32\] -0+1c8 <[^>]*> e7932424 ? ldr r2, \[r3, r4, lsr #8\] -0+1cc <[^>]*> 07b54484 ? ldreq r4, \[r5, r4, lsl #9\]! -0+1d0 <[^>]*> 14954006 ? ldrne r4, \[r5\], #6 -0+1d4 <[^>]*> e6b21003 ? ldrt r1, \[r2\], r3 -0+1d8 <[^>]*> e6942425 ? ldr r2, \[r4\], r5, lsr #8 -0+1dc <[^>]*> e51f0008 ? ldr r0, \[pc, #-8\] ; 0+1dc <[^>]*> -0+1e0 <[^>]*> e5d43000 ? ldrb r3, \[r4\] -0+1e4 <[^>]*> 14f85000 ? ldrnebt r5, \[r8\] -0+1e8 <[^>]*> e5810000 ? str r0, \[r1\] -0+1ec <[^>]*> e7811002 ? str r1, \[r1, r2\] -0+1f0 <[^>]*> e7a43003 ? str r3, \[r4, r3\]! -0+1f4 <[^>]*> e5822020 ? str r2, \[r2, #32\] -0+1f8 <[^>]*> e7832424 ? str r2, \[r3, r4, lsr #8\] -0+1fc <[^>]*> 07a54484 ? streq r4, \[r5, r4, lsl #9\]! -0+200 <[^>]*> 14854006 ? strne r4, \[r5\], #6 -0+204 <[^>]*> e6821003 ? str r1, \[r2\], r3 -0+208 <[^>]*> e6a42425 ? strt r2, \[r4\], r5, lsr #8 -0+20c <[^>]*> e50f1004 ? str r1, \[pc, #-4\] ; 0+210 <[^>]*> -0+210 <[^>]*> e5c71000 ? strb r1, \[r7\] -0+214 <[^>]*> e4e02000 ? strbt r2, \[r0\] -0+218 <[^>]*> e8900002 ? ldmia r0, {r1} -0+21c <[^>]*> 09920038 ? ldmeqib r2, {r3, r4, r5} -0+220 <[^>]*> e853ffff ? ldmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ -0+224 <[^>]*> e93b05ff ? ldmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} -0+228 <[^>]*> e99100f7 ? ldmib r1, {r0, r1, r2, r4, r5, r6, r7} -0+22c <[^>]*> e89201f8 ? ldmia r2, {r3, r4, r5, r6, r7, r8} -0+230 <[^>]*> e9130003 ? ldmdb r3, {r0, r1} -0+234 <[^>]*> e8540300 ? ldmda r4, {r8, r9}\^ -0+238 <[^>]*> e8800002 ? stmia r0, {r1} -0+23c <[^>]*> 09820038 ? stmeqib r2, {r3, r4, r5} -0+240 <[^>]*> e843ffff ? stmda r3, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, sp, lr, pc}\^ -0+244 <[^>]*> e92b05ff ? stmdb fp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, sl} -0+248 <[^>]*> e8010007 ? stmda r1, {r0, r1, r2} -0+24c <[^>]*> e9020018 ? stmdb r2, {r3, r4} -0+250 <[^>]*> e8830003 ? stmia r3, {r0, r1} -0+254 <[^>]*> e9c40300 ? stmib r4, {r8, r9}\^ -0+258 <[^>]*> ef123456 ? (swi|svc) 0x00123456 -0+25c <[^>]*> 2f000033 ? (swi|svc)cs 0x00000033 -0+260 <[^>]*> eb000000 ? bl 0+268 <[^>]*> -[ ]*260:.*_wombat.* -0+264 <[^>]*> 5b000000 ? blpl 0+26c <[^>]*> -[ ]*264:.*ARM.*hohum -0+268 <[^>]*> ea000000 ? b 0+270 <[^>]*> -[ ]*268:.*_wibble.* -0+26c <[^>]*> da000000 ? ble 0+274 <[^>]*> -[ ]*26c:.*testerfunc.* -0+270 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 -0+274 <[^>]*> e1a01002 ? mov r1, r2 -0+278 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+27c <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+280 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+284 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+288 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+28c <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+290 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+294 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+298 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+29c <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2a0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2a4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2a8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ac <[^>]*> e1a01062 ? mov r1, r2, rrx -0+2b0 <[^>]*> e1a01102 ? mov r1, r2, lsl #2 -0+2b4 <[^>]*> e1a01002 ? mov r1, r2 -0+2b8 <[^>]*> e1a01f82 ? mov r1, r2, lsl #31 -0+2bc <[^>]*> e1a01312 ? mov r1, r2, lsl r3 -0+2c0 <[^>]*> e1a01122 ? mov r1, r2, lsr #2 -0+2c4 <[^>]*> e1a01fa2 ? mov r1, r2, lsr #31 -0+2c8 <[^>]*> e1a01022 ? mov r1, r2, lsr #32 -0+2cc <[^>]*> e1a01332 ? mov r1, r2, lsr r3 -0+2d0 <[^>]*> e1a01142 ? mov r1, r2, asr #2 -0+2d4 <[^>]*> e1a01fc2 ? mov r1, r2, asr #31 -0+2d8 <[^>]*> e1a01042 ? mov r1, r2, asr #32 -0+2dc <[^>]*> e1a01352 ? mov r1, r2, asr r3 -0+2e0 <[^>]*> e1a01162 ? mov r1, r2, ror #2 -0+2e4 <[^>]*> e1a01fe2 ? mov r1, r2, ror #31 -0+2e8 <[^>]*> e1a01372 ? mov r1, r2, ror r3 -0+2ec <[^>]*> e1a01062 ? mov r1, r2, rrx diff --git a/binutils-2.17/gas/testsuite/gas/arm/xscale.d b/binutils-2.17/gas/testsuite/gas/arm/xscale.d deleted file mode 100644 index fc38ba14..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/xscale.d +++ /dev/null @@ -1,37 +0,0 @@ -#objdump: -dr --prefix-addresses --show-raw-insn -#name: XScale instructions -#as: -mcpu=xscale -EL - -# Test the XScale instructions: - -.*: +file format .*arm.* - -Disassembly of section .text: -0+00 <foo> ee201010 mia acc0, r0, r1 -0+04 <[^>]*> be20d01e mialt acc0, lr, sp -0+08 <[^>]*> ee284012 miaph acc0, r2, r4 -0+0c <[^>]*> 1e286015 miaphne acc0, r5, r6 -0+10 <[^>]*> ee2c8017 miaBB acc0, r7, r8 -0+14 <[^>]*> ee2da019 miaBT acc0, r9, sl -0+18 <[^>]*> ee2eb01c miaTB acc0, ip, fp -0+1c <[^>]*> ee2f0010 miaTT acc0, r0, r0 -0+20 <[^>]*> ec411000 mar acc0, r1, r1 -0+24 <[^>]*> cc4c2000 margt acc0, r2, ip -0+28 <[^>]*> ec543000 mra r3, r4, acc0 -0+2c <[^>]*> ec585000 mra r5, r8, acc0 -0+30 <[^>]*> f5d0f000 pld \[r0\] -0+34 <[^>]*> f5d1f789 pld \[r1, #1929\] -0+38 <[^>]*> f7d2f003 pld \[r2, r3\] -0+3c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\] -0+40 <[^>]*> e1c100d0 ldrd r0, \[r1\] -0+44 <[^>]*> 01c327d8 ldreqd r2, \[r3, #120\] -0+48 <[^>]*> b10540d6 ldrltd r4, \[r5, -r6\] -0+4c <[^>]*> e16a88f9 strd r8, \[sl, #-137\]! -0+50 <[^>]*> e1ac00fd strd r0, \[ip, sp\]! -0+54 <[^>]*> 30ce21f0 strccd r2, \[lr\], #16 -0+58 <[^>]*> 708640f8 strvcd r4, \[r6\], r8 -0+5c <[^>]*> e5910000 ldr r0, \[r1\] -0+60 <[^>]*> e5832000 str r2, \[r3\] -0+64 <[^>]*> e321f011 msr CPSR_c, #17 ; 0x11 -0+68 <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) -0+6c <[^>]*> e1a00000 ? nop[ ]+\(mov r0,r0\) diff --git a/binutils-2.17/gas/testsuite/gas/arm/xscale.s b/binutils-2.17/gas/testsuite/gas/arm/xscale.s deleted file mode 100644 index 7b58c344..00000000 --- a/binutils-2.17/gas/testsuite/gas/arm/xscale.s +++ /dev/null @@ -1,42 +0,0 @@ - .text - .global foo -foo: - mia acc0, r0, r1 - mialt acc0, r14, r13 - - miaph acc0, r2, r4 - miaphne acc0, r5, r6 - - miaBB acc0, r7, r8 - miaBT acc0, r9, r10 - miaTB acc0, r12, r11 - miaTT acc0, r0, r0 - - mar acc0, r1, r1 - margt acc0, r2, r12 - - mra r3, r4, acc0 - mra r5, r8, acc0 - - pld [r0] - pld [r1, #0x789] - pld [r2, r3] - pld [r4, -r5, lsl #5] - - ldrd r0, [r1] - ldreqd r2, [r3, #0x78] - ldrltd r4, [r5, -r6] - strd r8, [r10,#-0x89]! - strald r0, [r12, +r13]! - strlod r2, [r14], #+0x010 - strvcd r4, [r6], r8 - - ldr r0, [r1] - str r2, [r3] - - msr cpsr_ctl, #0x11 - - # Add two nop instructions to ensure that the - # output is 32-byte aligned as required for arm-aout. - nop - nop |