[2.25] sync to a30720e3e633f275250e26f85ccae5dbdddfb6c6

local patches will be re-applied later

commit a30720e3e633f275250e26f85ccae5dbdddfb6c6
Author: Alan Modra <amodra@gmail.com>
Date:   Wed Nov 19 10:30:16 2014 +1030

    daily update

Change-Id: Ieb2a3f4dd2ecb289ac5305ff08d428b2847494ab

1 files changed, 1364 insertions, 0 deletions

diff --git a/binutils-2.25/opcodes/ChangeLog-2013 b/binutils-2.25/opcodes/ChangeLog-2013
new file mode 100644
index 00000000..8a9d7e6c
--- /dev/null
+++ b/binutils-2.25/opcodes/ChangeLog-2013
@@ -0,0 +1,1364 @@
+2013-12-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+	* nds32-dis.c (sr_map): Add system register table for disassembling.
+	(usr_map): Fix typo.
+	* nds32-asm.c (keyword_sr): Add embedded debug registers.
+
+2013-12-17  Michael Zolotukhin  <michael.v.zolotukhin@gmail.com>
+
+	* i386-dis.c (MOD_FF_REG_3): New.
+	(MOD_FF_REG_5): Likewise.
+	(mod_table): Add MOD_FF_REG_3 and MOD_FF_REG_5.
+	(reg_table): Use MOD_FF_REG_3 and MOD_FF_REG_5.
+
+2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* mips-dis.c: Add mips_cp1_names pointer.
+	(mips_cp1_names_numeric): New array.
+	(mips_cp1_names_mips3264): New array.
+	(mips_arch_choice): Add cp1_names.
+	(mips_arch_choices): Add relevant cp1 register name array to each of
+	the elements.
+	(set_default_mips_dis_options): Add support for setting up the
+	mips_cp1_names pointer.
+	(parse_mips_dis_option): Add support for the cp1-names command line
+	variable.  Also setup the mips_cp1_names pointer.
+	(print_reg): Print out name of the cp1 register.
+
+2013-12-16  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+	* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+	+v and +w.
+	(micromips_opcodes): Reduced element index range for sldi, splati,
+	copy_s, copy_u, insert and insve instructions.
+	* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+	+v and +w.
+	(mips_builtin_opcodes): Reduced element index range for sldi, splati,
+	copy_s, copy_u, insert and insve instructions.
+
+2013-12-13  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* nds32-dis.c (mnemonic_96): Fix typo.
+
+2013-12-13  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+	    Wei-Cheng Wang  <cole945@gmail.com>
+
+	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nds32-asm.c
+	and nds32-dis.c.
+	* Makefile.in: Regenerate.
+	* configure.in: Add case for bfd_nds32_arch.
+	* configure: Regenerate.
+	* disassemble.c (ARCH_nds32): Define.
+	* nds32-asm.c: New file for nds32.
+	* nds32-asm.h: New file for nds32.
+	* nds32-dis.c: New file for nds32.
+	* nds32-opc.h: New file for nds32.
+
+2013-12-05  Nick Clifton  <nickc@redhat.com>
+
+	* s390-mkopc.c (dumpTable): Provide a format string to printf so
+	that compiling with -Werror=format-security does not produce an
+	error.
+
+2013-11-20  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (aarch64_pstatefields): Update.
+
+2013-11-19  Catherine Moore  <clm@codesourcery.com>
+
+	* micromips-opc.c (LM): Define.
+	(micromips_opcodes): Add LM to load instructions.
+	* mips-opc.c (prefe): Add LM attribute.
+
+2013-11-18  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	Revert
+
+	2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (CPENT): New define.
+	(F_READONLY, F_WRITEONLY): Likewise.
+	(aarch64_sys_regs): Add trace unit registers.
+	(aarch64_sys_reg_readonly_p): New function.
+	(aarch64_sys_reg_writeonly_p): Ditto.
+
+2013-11-15  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (CPENT): New define.
+	(F_READONLY, F_WRITEONLY): Likewise.
+	(aarch64_sys_regs): Add trace unit registers.
+	(aarch64_sys_reg_readonly_p): New function.
+	(aarch64_sys_reg_writeonly_p): Ditto.
+
+2013-11-15  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
+	"mtcr".
+
+2013-11-11  Catherine Moore  <clm@codesourcery.com>
+
+	* mips-dis.c (print_insn_mips): Use
+	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
+	(print_insn_micromips): Likewise.
+	* mips-opc.c (LDD): Remove.
+	(CLD): Include INSN_LOAD_MEMORY.
+	(LM): New.
+	(mips_builtin_opcodes): Use LM instead of LDD.
+        Add LM to load instructions.
+
+2013-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/16140
+	* i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
+	* i386-init.h: Regenerated.
+
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (F_DEPRECATED): New macro.
+	(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
+	F_DEPRECATED.
+	(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
+	AARCH64_OPND_SYSREG.
+
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
+	(convert_from_csel): Likewise.
+	* aarch64-opc.c (operand_general_constraint_met_p): Handle
+	AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
+	(aarch64_print_operand): Handle AARCH64_OPND_COND1.
+	* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
+	COND for cinc, cset, cinv, csetm and cneg.
+	(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
+	* aarch64-asm-2.c: Re-generated.
+	* aarch64-dis-2.c: Ditto.
+	* aarch64-opc-2.c: Ditto.
+
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (set_syntax_error): New function.
+	(operand_general_constraint_met_p): Replace set_other_error
+	with set_syntax_error.
+
+2013-10-30  Andreas Arnez  <arnez@linux.vnet.ibm.com>
+
+	* s390-dis.c (init_disasm): Default to full 'zarch' opcode
+	availability even for 31-bit programs.
+
+2013-10-15  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
+
+	* arm-dis.c (neon_opcodes): Adjust print string for vshll.
+
+2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
+
+	* micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
+	+d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
+	+~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+	(MSA): New define.
+	(MSA64): New define.
+	(micromips_opcodes): Add MSA instructions.
+	* mips-dis.c (msa_control_names): New array.
+	(mips_abi_choice): Add ASE_MSA to mips32r2.
+	Remove ASE_MDMX from mips64r2.
+	Add ASE_MSA and ASE_MSA64 to mips64r2.
+	(parse_mips_dis_option): Handle -Mmsa.
+	(print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
+	(print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
+	(print_mips_disassembler_options): Print -Mmsa.
+	* mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
+	+l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+	(MSA): New define.
+	(MSA64): New define.
+	(mips_builtin_op): Add MSA instructions.
+
+2013-10-13  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
+	as the primary name of r30.
+
+2013-10-12  Jan Beulich <jbeulich@suse.com>
+
+	* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
+	default case.
+	(OP_E_register): Move v_bnd_mode alongside m_mode.
+	* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
+	Drop Reg16 and Disp16. Add NoRex64.
+	(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
+	* i386-tbl.h: Re-generate.
+
+2013-10-10  Sean Keys <skeys@ipdatasys.com>
+
+	* xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
+	table.
+	* xgate-dis.c (print_insn): Refactor to work with table change.
+
+2013-10-10  Roland McGrath  <mcgrathr@google.com>
+
+	* i386-dis.c (oappend_maybe_intel): New function.
+	(OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
+	(OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
+	(VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
+
+	* cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
+	possible compiler warnings when the union's initializer is
+	actually meant for the 'preg' enum typed member.
+	* crx-opc.c (REG): Likewise.
+
+	* v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
+	Remove duplicate const qualifier.
+
+2013-10-08  Jan Beulich <jbeulich@suse.com>
+
+	* i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
+	(clflush): Use Anysize instead of Byte|Unspecified.
+	(prefetch*): Likewise.
+	* i386-tbl.h: Re-generate.
+
+2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
+
+	* micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
+
+2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
+	* i386-init.h: Regenerated.
+
+2013-09-30  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
+
+	* i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
+	* i386-init.h: Regenerated.
+
+2013-09-20  Alan Modra  <amodra@gmail.com>
+
+	* configure: Regenerate.
+
+2013-09-17  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
+
+	* s390-opc.txt (clih): Make the immediate unsigned.
+
+2013-09-04  Roland McGrath  <mcgrathr@google.com>
+
+	PR gas/15914
+	* arm-dis.c (arm_opcodes): Add udf.
+	(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
+	(thumb32_opcodes): Add udf.w.
+	(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
+
+2013-09-02  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
+	For the load fp integer instructions only the suppression flag was
+	new with z196 version.
+
+2013-08-28  Nick Clifton  <nickc@redhat.com>
+
+	* aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
+	immediate is not suitable for the 32-bit ABI.
+
+2013-08-23  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
+	replacing NODS.
+
+2013-08-23  Yuri Chornoivan  <yurchor@ukr.net>
+
+	PR binutils/15834
+	* aarch64-asm.c: Fix typos.
+	* aarch64-dis.c: Likewise.
+	* msp430-dis.c: Likewise.
+
+2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
+	macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
+	Use +H rather than +C for the real "dext".
+	* mips-opc.c (mips_builtin_opcodes): Likewise.
+
+2013-08-19  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
+	* micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
+	and OPTIONAL_MAPPED_REG.
+	* mips-opc.c (decode_mips_operand): Likewise.
+	* mips16-opc.c (decode_mips16_operand): Likewise.
+	* mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
+
+2013-08-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
+	(PREFIX_EVEX_0F3A3F): Likewise.
+	* i386-dis-evex.h (evex_table): Updated.
+
+2013-08-06  Jürgen Urban  <JuergenUrban@gmx.de>
+
+	* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
+	VCLIPW.
+
+2013-08-05  Eric Botcazou  <ebotcazou@adacore.com>
+            Konrad Eisele  <konrad@gaisler.com>
+
+	* sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
+	bfd_mach_sparc.
+	* sparc-opc.c (MASK_LEON): Define.
+	(v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
+	(letandleon): New macro.
+	(v9andleon): Likewise.
+	(sparc_opc): Add leon.
+	(umac): Enable for letandleon.
+	(smac): Likewise.
+	(casa): Enable for v9andleon.
+	(cas): Likewise.
+	(casl): Likewise.
+
+2013-08-04  Jürgen Urban  <JuergenUrban@gmx.de>
+	    Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
+	OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
+	(print_vu0_channel): New function.
+	(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
+	(print_insn_args): Handle '#'.
+	(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
+	* mips-opc.c (mips_vu0_channel_mask): New constant.
+	(decode_mips_operand): Handle new VU0 operand types.
+	(VU0, VU0CH): New macros.
+	(mips_builtin_opcodes): Add VU0 opcodes.  Use "+7" rather than "E"
+	for LQC2 and SQC2.  Use "+9" rather than "G" for EE CFC2 and CTC2.
+	Use "+6" rather than "G" for QMFC2 and QMTC2.
+
+2013-08-03  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-formats.h (PCREL): Reorder parameters and update the definition
+	to match new mips_pcrel_operand layout.
+	(JUMP, JALX, BRANCH): Update accordingly.
+	* mips16-opc.c (decode_mips16_operand): Likewise.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* micromips-opc.c (WR_s): Delete.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
+	New macros.
+	(WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
+	(WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
+	(mips_builtin_opcodes): Use the new position-based read-write flags
+	instead of field-based ones.  Use UDI for "udi..." instructions.
+	* mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
+	New macros.
+	(WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
+	(RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
+	(WR_SP, RD_16): New macros.
+	(RD_SP): Redefine as an INSN2_* flag.
+	(MOD_SP): Redefine in terms of RD_SP and WR_SP.
+	(mips16_opcodes): Use the new position-based read-write flags
+	instead of field-based ones.  Use RD_16 for "nop".  Move RD_SP to
+	pinfo2 field.
+	* micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
+	New macros.
+	(WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
+	(WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
+	(WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
+	(RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
+	(micromips_opcodes): Use the new position-based read-write flags
+	instead of field-based ones.
+	* mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
+	(print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
+	of field-based flags.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
+	(WR_SP): Replace with...
+	(MOD_SP): ...this.
+	(mips16_opcodes): Update accordingly.
+	* mips-dis.c (print_insn_mips16): Likewise.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips16-opc.c (mips16_opcodes): Reformat.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
+	for operands that are hard-coded to $0.
+	* micromips-opc.c (micromips_opcodes): Likewise.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
+	for the single-operand forms of JALR and JALR.HB.
+	* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
+	and JALRS.HB.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
+	instructions.  Fix them to use WR_MACC instead of WR_CC and
+	add missing RD_MACCs.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
+
+2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
+
+	* ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
+
+2013-07-26  Sergey Guriev  <sergey.s.guriev@intel.com>
+	    Alexander Ivchenko  <alexander.ivchenko@intel.com>
+	    Maxim Kuznetsov  <maxim.kuznetsov@intel.com>
+	    Sergey Lega  <sergey.s.lega@intel.com>
+	    Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Ilya Tocar  <ilya.tocar@intel.com>
+	    Andrey Turetskiy  <andrey.turetskiy@intel.com>
+	    Ilya Verbin  <ilya.verbin@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis-evex.h: New.
+	* i386-dis.c (OP_Rounding): New.
+	(VPCMP_Fixup): New.
+	(OP_Mask): New.
+	(Rdq): New.
+	(XMxmmq): New.
+	(EXdScalarS): New.
+	(EXymm): New.
+	(EXEvexHalfBcstXmmq): New.
+	(EXxmm_mdq): New.
+	(EXEvexXGscat): New.
+	(EXEvexXNoBcst): New.
+	(VPCMP): New.
+	(EXxEVexR): New.
+	(EXxEVexS): New.
+	(XMask): New.
+	(MaskG): New.
+	(MaskE): New.
+	(MaskR): New.
+	(MaskVex): New.
+	(modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
+	evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
+	evex_rounding_mode, evex_sae_mode, mask_mode.
+	(USE_EVEX_TABLE): New.
+	(EVEX_TABLE): New.
+	(EVEX enum): New.
+	(REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
+	REG_EVEX_0F38C7.
+	(MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
+	MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
+	MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
+	MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
+	MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,  MOD_EVEX_0F38C7_REG_5,
+	MOD_EVEX_0F38C7_REG_6.
+	(PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
+	PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
+	PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
+	PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
+	PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
+	PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
+	PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
+	PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
+	PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
+	PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
+	PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
+	PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
+	PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
+	PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
+	PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
+	PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
+	PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
+	PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
+	PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
+	PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
+	PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
+	PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
+	PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
+	PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
+	PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
+	PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
+	PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
+	PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
+	PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
+	PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
+	PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
+	PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
+	PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
+	PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
+	PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
+	PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
+	PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
+	PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
+	PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
+	PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
+	PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
+	PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
+	PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
+	PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
+	PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
+	PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
+	PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
+	PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
+	PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
+	PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
+	PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
+	PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
+	PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
+	PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
+	PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
+	PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
+	PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
+	PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
+	PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
+	PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
+	PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
+	PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
+	PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
+	PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
+	PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
+	PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
+	PREFIX_EVEX_0F3A00,  PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
+	PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
+	PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
+	PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
+	PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
+	PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
+	PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
+	PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
+	PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
+	PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
+	PREFIX_EVEX_0F3A55.
+	(VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
+	VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
+	VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
+	VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
+	VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
+	VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
+	VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
+	VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
+	VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
+	VEX_W_0F3A32_P_2_LEN_0.
+	(VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
+	EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
+	EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
+	EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
+	EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
+	EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
+	EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
+	EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
+	EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
+	EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
+	EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
+	EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
+	EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
+	EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
+	EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
+	EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
+	EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
+	EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
+	EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
+	EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
+	EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
+	EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
+	EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
+	EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
+	EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
+	EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
+	EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
+	EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
+	EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
+	EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
+	EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
+	EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
+	EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
+	EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
+	EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
+	EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
+	EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
+	EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
+	EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
+	EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
+	EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
+	EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
+	EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
+	EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
+	EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
+	EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
+	EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
+	EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
+	EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
+	EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
+	EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
+	EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
+	EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
+	EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
+	(struct vex): Add fields evex, r, v, mask_register_specifier,
+	zeroing, ll, b.
+	(intel_names_xmm): Add upper 16 registers.
+	(att_names_xmm): Ditto.
+	(intel_names_ymm): Ditto.
+	(att_names_ymm): Ditto.
+	(names_zmm): New.
+	(intel_names_zmm): Ditto.
+	(att_names_zmm): Ditto.
+	(names_mask): Ditto.
+	(intel_names_mask): Ditto.
+	(att_names_mask): Ditto.
+	(names_rounding): Ditto.
+	(names_broadcast): Ditto.
+	(x86_64_table): Add escape to evex-table.
+	(reg_table): Include reg_table evex-entries from
+	i386-dis-evex.h.  Fix prefetchwt1 instruction.
+	(prefix_table): Add entries for new instructions.
+	(vex_table): Ditto.
+	(vex_len_table): Ditto.
+	(vex_w_table): Ditto.
+	(mod_table): Ditto.
+	(get_valid_dis386): Properly handle new instructions.
+	(print_insn): Handle zmm and mask registers, print mask operand.
+	(intel_operand_size): Support EVEX, new modes and sizes.
+	(OP_E_register): Handle new modes.
+	(OP_E_memory): Ditto.
+	(OP_G): Ditto.
+	(OP_XMM): Ditto.
+	(OP_EX): Ditto.
+	(OP_VEX): Ditto.
+	* i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
+	CPU_ANY_AVX_FLAGS.  Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
+	CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
+	(cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
+	CpuAVX512PF and CpuVREX.
+	(operand_type_init): Add OPERAND_TYPE_REGZMM,
+	OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
+	(opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
+	StaticRounding, SAE, Disp8MemShift, NoDefMask.
+	(operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
+	* i386-init.h: Regenerate.
+	* i386-opc.h (CpuAVX512F): New.
+	(CpuAVX512CD): New.
+	(CpuAVX512ER): New.
+	(CpuAVX512PF): New.
+	(CpuVREX): New.
+	(i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
+	cpuavx512pf and cpuvrex fields.
+	(VecSIB): Add VecSIB512.
+	(EVex): New.
+	(Masking): New.
+	(VecESize): New.
+	(Broadcast): New.
+	(StaticRounding): New.
+	(SAE): New.
+	(Disp8MemShift): New.
+	(NoDefMask): New.
+	(i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
+	staticrounding, sae, disp8memshift and nodefmask.
+	(RegZMM): New.
+	(Zmmword): Ditto.
+	(Vec_Disp8): Ditto.
+	(i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
+	fields.
+	(RegVRex): New.
+	* i386-opc.tbl: Add AVX512 instructions.
+	* i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
+	registers, mask registers.
+	* i386-tbl.h: Regenerate.
+
+2013-07-25  Aaro Koskinen  <aaro.koskinen@iki.fi>
+
+	PR gas/15220
+	* mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
+	Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
+
+2013-07-25  Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
+	PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
+	PREFIX_0F3ACC.
+	(prefix_table): Updated.
+	(three_byte_table): Likewise.
+	* i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
+	(cpu_flags): Add CpuSHA.
+	(i386_cpu_flags): Add cpusha.
+	* i386-init.h: Regenerate.
+	* i386-opc.h (CpuSHA): New.
+	(CpuUnused): Restored.
+	(i386_cpu_flags): Add cpusha.
+	* i386-opc.tbl: Add SHA instructions.
+	* i386-tbl.h: Regenerate.
+
+2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
+	    Kirill Yukhin  <kirill.yukhin@intel.com>
+	    Michael Zolotukhin  <michael.v.zolotukhin@intel.com>
+
+	* i386-dis.c (BND_Fixup): New.
+	(Ebnd): New.
+	(Ev_bnd): New.
+	(Gbnd): New.
+	(BND): New.
+	(v_bnd_mode): New.
+	(bnd_mode): New.
+	(MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
+	MOD_0F1B_PREFIX_1.
+	(PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
+	(dis tables): Replace XX with BND for near branch and call
+	instructions.
+	(prefix_table): Add new entries.
+	(mod_table): Likewise.
+	(names_bnd): New.
+	(intel_names_bnd): New.
+	(att_names_bnd): New.
+	(BND_PREFIX): New.
+	(prefix_name): Handle BND_PREFIX.
+	(print_insn): Initialize names_bnd.
+	(intel_operand_size): Handle new modes.
+	(OP_E_register): Likewise.
+	(OP_E_memory): Likewise.
+	(OP_G): Likewise.
+	* i386-gen.c (cpu_flag_init): Add CpuMPX.
+	(cpu_flags): Add CpuMPX.
+	(operand_type_init): Add RegBND.
+	(opcode_modifiers): Add BNDPrefixOk.
+	(operand_types): Add RegBND.
+	* i386-init.h: Regenerate.
+	* i386-opc.h (CpuMPX): New.
+	(CpuUnused): Comment out.
+	(i386_cpu_flags): Add cpumpx.
+	(BNDPrefixOk): New.
+	(i386_opcode_modifier): Add bndprefixok.
+	(RegBND): New.
+	(i386_operand_type): Add regbnd.
+	* i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
+	Add MPX instructions and bnd prefix.
+	* i386-reg.tbl: Add bnd0-bnd3 registers.
+	* i386-tbl.h: Regenerate.
+
+2013-07-17  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
+	ATTRIBUTE_UNUSED.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
+	special rules.
+	* Makefile.in: Regenerate.
+	* mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
+	all fields.  Reformat.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips16-opc.c: Include mips-formats.h.
+	(reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
+	static arrays.
+	(decode_mips16_operand): New function.
+	* mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
+	(print_insn_arg): Handle OP_ENTRY_EXIT list.
+	Abort for OP_SAVE_RESTORE_LIST.
+	(print_mips16_insn_arg): Change interface.  Use mips_operand
+	structures.  Delete GET_OP_S.  Move GET_OP definition to...
+	(print_insn_mips16): ...here.  Call init_print_arg_state.
+	Update the call to print_mips16_insn_arg.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-formats.h: New file.
+	* mips-opc.c: Include mips-formats.h.
+	(reg_0_map): New static array.
+	(decode_mips_operand): New function.
+	* micromips-opc.c: Remove <stdio.h> include.  Include mips-formats.h.
+	(reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
+	(reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
+	(int_c_map): New static arrays.
+	(decode_micromips_operand): New function.
+	* mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
+	(micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
+	(micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
+	(micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
+	(micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
+	(micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
+	(micromips_imm_b_map, micromips_imm_c_map): Delete.
+	(print_reg): New function.
+	(mips_print_arg_state): New structure.
+	(init_print_arg_state, print_insn_arg): New functions.
+	(print_insn_args): Change interface and use mips_operand structures.
+	Delete GET_OP_S.  Move GET_OP definition to...
+	(print_insn_mips): ...here.  Update the call to print_insn_args.
+	(print_insn_micromips): Use print_insn_args.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
+	in macros.
+
+2013-07-14  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
+	ADDA.S, MULA.S and SUBA.S.
+
+2013-07-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/13572
+	* i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
+	* i386-tbl.h: Regenerated.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Remove o(b) macros.  Move LD
+	and SD A(B) macros up.
+	* micromips-opc.c (micromips_opcodes): Likewise.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips16-opc.c: Add entries for argumentless "entry" and "exit"
+	instructions.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
+	MDMX-like instructions.
+	* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
+	printing "Q" operands for INSN_5400 instructions.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
+	"+S" for "cins".
+	* mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
+	Combine cases.
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
+	"jalx".
+	* mips16-opc.c (mips16_opcodes): Likewise.
+	* micromips-opc.c (micromips_opcodes): Likewise.
+	* mips-dis.c (print_insn_args, print_mips16_insn_arg)
+	(print_insn_mips16): Handle "+i".
+	(print_insn_micromips): Likewise.  Conditionally preserve the
+	ISA bit for "a" but not for "+i".
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* micromips-opc.c (WR_mhi): Rename to..
+	(WR_mh): ...this.
+	(micromips_opcodes): Update "movep" entry accordingly.  Replace
+	"mh,mi" with "mh".
+	* mips-dis.c (micromips_to_32_reg_h_map): Rename to...
+	(micromips_to_32_reg_h_map1): ...this.
+	(micromips_to_32_reg_i_map): Rename to...
+	(micromips_to_32_reg_h_map2): ...this.
+	(print_micromips_insn): Remove "mi" case.  Print both registers
+	in the pair for "mh".
+
+2013-07-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
+	* micromips-opc.c (micromips_opcodes): Likewise.
+	* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
+	and "+T" handling.  Check for a "0" suffix when deciding whether to
+	use coprocessor 0 names.  In that case, also check for ",H" selectors.
+
+2013-07-05  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390-opc.c (J12_12, J24_24): New macros.
+	(INSTR_MII_UPI): Rename to INSTR_MII_UPP.
+	(MASK_MII_UPI): Rename to MASK_MII_UPP.
+	* s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
+
+2013-07-04  Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
+
+2013-06-26  Nick Clifton  <nickc@redhat.com>
+
+	* rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
+	field when checking for type 2 nop.
+	* rx-decode.c: Regenerate.
+
+2013-06-25  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
+	and "movep" macros.
+
+2013-06-24  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips-dis.c (is_mips16_plt_tail): New function.
+	(print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
+	word.
+	(is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
+
+2013-06-21  DJ Delorie  <dj@redhat.com>
+
+	* msp430-decode.opc: New.
+	* msp430-decode.c: New/generated.
+	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
+	(MAINTAINER_CLEANFILES): Likewise.
+	Add rule to build msp430-decode.c frommsp430decode.opc
+        using the opc2c program.
+	* Makefile.in: Regenerate.
+	* configure.in: Add msp430-decode.lo to msp430 architecture files.
+	* configure: Regenerate.
+
+2013-06-20  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
+	(SYMTAB_AVAILABLE): Removed.
+	(#include "elf/aarch64.h): Ditto.
+
+2013-06-17  Catherine Moore  <clm@codesourcery.com>
+	    Maciej W. Rozycki  <macro@codesourcery.com>
+	    Chao-Ying Fu  <fu@mips.com>
+
+	* micromips-opc.c (EVA): Define.
+	(TLBINV): Define.
+	(micromips_opcodes): Add EVA opcodes.
+	* mips-dis.c (mips_arch_choices): Update for ASE_EVA.
+	(print_insn_args): Handle EVA offsets.
+	(print_insn_micromips): Likewise.
+	* mips-opc.c (EVA): Define.
+	(TLBINV): Define.
+	(mips_builtin_opcodes): Add EVA opcodes.
+
+2013-06-17  Alan Modra  <amodra@gmail.com>
+
+	* Makefile.am (mips-opc.lo): Add rules to create automatic
+	dependency files.  Pass archdefs.
+	(micromips-opc.lo, mips16-opc.lo): Likewise.
+	* Makefile.in: Regenerate.
+
+2013-06-14  DJ Delorie  <dj@redhat.com>
+
+	* rx-decode.opc (rx_decode_opcode): Bit operations on
+	registers are 32-bit operations, not 8-bit operations.
+	* rx-decode.c: Regenerate.
+
+2013-06-13  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
+
+	* micromips-opc.c (IVIRT): New define.
+	(IVIRT64): New define.
+	(micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+ 	tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
+
+	* mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
+	dmtgc0 to print cp0 names.
+
+2013-06-09  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
+	argument.
+
+2013-06-08  Catherine Moore  <clm@codesourcery.com>
+	    Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* micromips-opc.c (D32, D33, MC): Update definitions.
+ 	(micromips_opcodes):  Initialize ase field.
+	* mips-dis.c (mips_arch_choice): Add ase field.
+	(mips_arch_choices): Initialize ase field.
+	(set_default_mips_dis_options): Declare and setup mips_ase.
+	* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
+	MT32, MC): Update definitions.
+	(mips_builtin_opcodes): Initialize ase field.
+
+2013-05-24  Richard Sandiford  <rsandifo@linux.vnet.ibm.com>
+
+	* s390-opc.txt (flogr): Require a register pair destination.
+
+2013-05-23  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
+
+	* s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
+	instruction format.
+
+2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>
+
+	* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
+
+2013-05-20  Peter Bergner <bergner@vnet.ibm.com>
+
+	* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
+	* ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
+	XLS_MASK, PPCVSX2): New defines.
+	(powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
+	fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
+	mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
+	mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
+	mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
+	vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
+	vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
+	vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
+	vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
+	vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
+	vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
+	vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
+	vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
+	vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
+	xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
+	xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
+	xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
+	xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
+	<lxvx, stxvx>: New extended mnemonics.
+
+2013-05-17  Alan Modra  <amodra@gmail.com>
+
+	* ia64-raw.tbl: Replace non-ASCII char.
+	* ia64-waw.tbl: Likewise.
+	* ia64-asmtab.c: Regenerate.
+
+2013-05-15  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
+
+	* i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
+	* i386-init.h: Regenerated.
+
+2013-05-13  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
+	* aarch64-opc.c (operand_general_constraint_met_p): Relax the range
+	check from [0, 255] to [-128, 255].
+
+2013-05-09  Andrew Pinski  <apinski@cavium.com>
+
+	* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
+	Add INSN_VIRT and INSN_VIRT64 to mips64r2.
+	(parse_mips_dis_option): Handle the virt option.
+	(print_insn_args): Handle "+J".
+	(print_mips_disassembler_options): Print out message about virt64.
+	* mips-opc.c (IVIRT): New define.
+	(IVIRT64): New define.
+	(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
+	tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
+	Move rfe to the bottom as it conflicts with tlbgp.
+
+2013-05-09  Alan Modra  <amodra@gmail.com>
+
+	* ppc-opc.c (extract_vlesi): Properly sign extend.
+	(extract_vlensi): Likewise.  Comment reason for setting invalid.
+
+2013-05-02  Nick Clifton  <nickc@redhat.com>
+
+	* msp430-dis.c: Add support for MSP430X instructions.
+
+2013-04-24  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
+	to "eccinj".
+
+2013-04-17  Wei-chen Wang  <cole945@gmail.com>
+
+	PR binutils/15369
+	* cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
+	of CGEN_CPU_ENDIAN.
+	(hash_insns_list): Likewise.
+
+2013-04-10  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
+	warning workaround.
+
+2013-04-08  Jan Beulich <jbeulich@suse.com>
+
+	* i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
+	* i386-tbl.h: Re-generate.
+
+2013-04-06  David S. Miller  <davem@davemloft.net>
+
+	* sparc-dis.c (compare_opcodes): When encountering multiple aliases
+	of an opcode, prefer the one with F_PREFERRED set.
+	* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
+	lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
+	ops.  Make 64-bit VIS logical ops have "d" suffix in their names,
+	mark existing mnenomics as aliases.  Add "cc" suffix to edge
+	instructions generating condition codes, mark existing mnenomics
+	as aliases.  Add "fp" prefix to VIS compare instructions, mark
+	existing mnenomics as aliases.
+
+2013-04-03  Nick Clifton  <nickc@redhat.com>
+
+	* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
+	destination address by subtracting the operand from the current
+	address.
+	* v850-opc.c (insert_u16_loop): Disallow negative offsets.  Store
+	a positive value in the insn.
+	(extract_u16_loop): Do not negate the returned value.
+	(D16_LOOP): Add V850_INVERSE_PCREL flag.
+
+	(ceilf.sw): Remove duplicate entry.
+	(cvtf.hs): New entry.
+	(cvtf.sh): Likewise.
+	(fmaf.s): Likewise.
+	(fmsf.s): Likewise.
+	(fnmaf.s): Likewise.
+	(fnmsf.s): Likewise.
+	(maddf.s): Restrict to E3V5 architectures.
+	(msubf.s): Likewise.
+	(nmaddf.s): Likewise.
+	(nmsubf.s): Likewise.
+
+2013-03-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (get_sib): Add the sizeflag argument.  Properly
+	check address mode.
+	(print_insn): Pass sizeflag to get_sib.
+
+2013-03-27  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR binutils/15068
+	* tic6x-dis.c: Add support for displaying 16-bit insns.
+
+2013-03-20  Alexis Deruelle  <alexis.deruelle@gmail.com>
+
+	PR gas/15095
+	* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
+	individual msb and lsb halves in src1 & src2 fields.  Discard the
+	src1 (lsb) value and only use src2 (msb), discarding bit 0, to
+	follow what Ti SDK does in that case as any value in the src1
+	field yields the same output with SDK disassembler.
+
+2013-03-12  Michael Eager <eager@eagercon.com>
+
+	* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
+
+2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
+
+2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
+
+2013-03-11  Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
+
+2013-03-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
+	(thumb32_opcodes): Likewise.
+	(print_insn_thumb32): Handle 'S' control char.
+
+2013-03-08  Yann Sionneau  <yann.sionneau@gmail.com>
+
+	* lm32-desc.c: Regenerate.
+
+2013-03-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-reg.tbl (riz): Add RegRex64.
+	* i386-tbl.h: Regenerated.
+
+2013-02-28  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
+	(aarch64_feature_crc): New static.
+	(CRC): New macro.
+	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
+	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
+	* aarch64-asm-2.c: Re-generate.
+	* aarch64-dis-2.c: Ditto.
+	* aarch64-opc-2.c: Ditto.
+
+2013-02-27  Alan Modra  <amodra@gmail.com>
+
+	* rl78-decode.opc (rl78_decode_opcode): Fix typo.
+	* rl78-decode.c: Regenerate.
+
+2013-02-25  Kaushik Phatak  <Kaushik.Phatak@kpitcummins.com>
+
+	* rl78-decode.opc: Fix encoding of DIVWU insn.
+	* rl78-decode.c: Regenerate.
+
+2013-02-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/15159
+	* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
+
+	* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
+	(cpu_flags): Add CpuSMAP.
+
+	* i386-opc.h (CpuSMAP): New.
+	(i386_cpu_flags): Add cpusmap.
+
+	* i386-opc.tbl: Add clac and stac.
+
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2013-02-15  Markos Chandras  <markos.chandras@imgtec.com>
+
+	* metag-dis.c: Initialize outf->bytes_per_chunk to 4
+	which also makes the disassembler output be in little
+	endian like it should be.
+
+2013-02-14  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
+	fields to NULL.
+	(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
+
+2013-02-13  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips-dis.c (is_compressed_mode_p): Only match symbols from the
+	section disassembled.
+
+2013-02-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* arm-dis.c: Update strht pattern.
+
+2013-02-09  Jürgen Urban  <JuergenUrban@gmx.de>
+
+	* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
+	single-float.  Disable ll, lld, sc and scd for EE.  Disable the
+	trunc.w.s macro for EE.
+
+2013-02-06  Sandra Loosemore  <sandra@codesourcery.com>
+            Andrew Jenner <andrew@codesourcery.com>
+
+	Based on patches from Altera Corporation.
+
+	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
+	nios2-opc.c.
+	* Makefile.in: Regenerated.
+	* configure.in: Add case for bfd_nios2_arch.
+	* configure: Regenerated.
+	* disassemble.c (ARCH_nios2): Define.
+	(disassembler): Add case for bfd_arch_nios2.
+	* nios2-dis.c: New file.
+	* nios2-opc.c: New file.
+
+2013-02-04  Alan Modra  <amodra@gmail.com>
+
+	* po/POTFILES.in: Regenerate.
+	* rl78-decode.c: Regenerate.
+	* rx-decode.c: Regenerate.
+
+2013-01-30  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
+	ushll2 with F_HAS_ALIAS.  Add entries for sxtl, sxtl2, uxtl and uxtl2.
+	* aarch64-asm.c (convert_xtl_to_shll): New function.
+	(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
+	calling convert_xtl_to_shll.
+	* aarch64-dis.c (convert_shll_to_xtl): New function.
+	(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
+	calling convert_shll_to_xtl.
+	* aarch64-gen.c: Update copyright year.
+	* aarch64-asm-2.c: Re-generate.
+	* aarch64-dis-2.c: Re-generate.
+	* aarch64-opc-2.c: Re-generate.
+
+2013-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* v850-dis.c: Add support for e3v5 architecture.
+	* v850-opc.c: Likewise.
+
+2013-01-17  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
+	* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
+	* aarch64-opc.c (operand_general_constraint_met_p): For
+	AARCH64_MOD_LSL, move the range check on the shift amount before the
+	alignment check; change to call set_sft_amount_out_of_range_error
+	instead of set_imm_out_of_range_error.
+	* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
+	(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
+	8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
+	SIMD_IMM_SFT.
+
+2013-01-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
+
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2013-01-15  Nick Clifton  <nickc@redhat.com>
+
+	* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
+	values.
+	* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
+
+2013-01-14  Will Newton <will.newton@imgtec.com>
+
+	* metag-dis.c (REG_WIDTH): Increase to 64.
+
+2013-01-10  Peter Bergner <bergner@vnet.ibm.com>
+
+	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
+	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
+	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
+	(SH6): Update.
+	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
+	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
+	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
+	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
+
+2013-01-10  Will Newton <will.newton@imgtec.com>
+
+	* Makefile.am: Add Meta.
+	* configure.in: Add Meta.
+	* disassemble.c: Add Meta support.
+	* metag-dis.c: New file.
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+
+2013-01-07  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
+
+	* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
+	(match_opcode): Rename to cr16_match_opcode.
+
+2013-01-04  Juergen Urban <JuergenUrban@gmx.de>
+
+	* mips-dis.c: Add names for CP0 registers of r5900.
+	* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
+	instructions sq and lq.
+	Add support for MIPS r5900 CPU.
+	Add support for 128 bit MMI (Multimedia Instructions).
+	Add support for EE instructions (Emotion Engine).
+	Disable unsupported floating point instructions (64 bit and
+	undefined compare operations).
+	Enable instructions of MIPS ISA IV which are supported by r5900.
+	Disable 64 bit co processor instructions.
+	Disable 64 bit multiplication and division instructions.
+	Disable instructions for co-processor 2 and 3, because these are
+	not supported (preparation for later VU0 support (Vector Unit)).
+	Disable cvt.w.s because this behaves like trunc.w.s and the
+	correct execution can't be ensured on r5900.
+	Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
+	will confuse less developers and compilers.
+
+2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (aarch64_print_operand): Change to print
+	AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
+	in comment.
+	* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
+	from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
+	OP_MOV_IMM_WIDE.
+
+2013-01-04  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+	* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
+	PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
+
+2013-01-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-gen.c (process_copyright): Update copyright year to 2013.
+
+2013-01-02  Kaushik Phatak  <kaushik.phatak@kpitcummins.com>
+
+	* cr16-dis.c (match_opcode,make_instruction): Remove static
+	declaration.
+	(dwordU,wordU): Moved typedefs to opcode/cr16.h
+	(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
+
+For older changes see ChangeLog-2012
+
+Copyright (C) 2013 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End: