Create an unified binutils source tree for both Android and ChromiumOS.

About source code - The base version of this binutils is newer than that
of aosp/binutils-2.25, it is based on the binutils that is used to build
google products and ChromiumOS. And it contains *all* local Android
patches as well as all patches that are cherry-picked from upstream for
aosp/binutils-2.25 tree (up to Nov. 5 - 932d71b85). You may find the
detailed development history for this binutils tree here -
https://chromium.googlesource.com/chromiumos/third_party/binutils/+log/unification
(This CL is a combination of all the CLs in it. After this CL is
submitted the tree will be identical to
https://chromium.googlesource.com/chromiumos/third_party/binutils/+log/unification
at 2865a3615d80bd5f82d14d7e0484e84dc052596a)

About testing - We tested this binutils for both ChromiumOS and
Android. For android, we tested building N4, N5X, N6, N7, N9 using new
binutils, we also did a full-build of toolchain (by build.py) and built
a N5X image; for ChromiumOS - it passed ChromiumOS toolchain release
tests on all 4 platforms (x86, x86_64, arm32 and arm64).

Change-Id: I2bb2cf579f9458d0a8bc9612331dc7d5043e3d82

16 files changed, 630 insertions, 404 deletions

diff --git a/binutils-2.25/include/ChangeLog b/binutils-2.25/include/ChangeLog
index 43e06f77..0204432c 100644
--- a/binutils-2.25/include/ChangeLog
+++ b/binutils-2.25/include/ChangeLog
@@ -1,11 +1,10 @@
-2014-11-18  Igor Zamyatin  <igor.zamyatin@intel.com>
+2014-10-30  Andrew Pinski  <apinski@cavium.com>
 
-	* bfdlink.h (struct bfd_link_info): Add bndplt.
+	* elf/mips.h (AFL_EXT_OCTEON3): Define.
+	INSN_OCTEON3, CPU_OCTEON3): Define.
 
-2014-10-28  Matthew Fortune  <matthew.fortune@imgtec.com>
+2014-10-22  Matthew Fortune  <matthew.fortune@imgtec.com>
 
-	Apply trunk patches
-	2014-10-22  Matthew Fortune  <matthew.fortune@imgtec.com>
 	* elf/mips.h (AFL_ASE_MASK): Define.
 
 2014-09-26  Max Ostapenko  <m.ostapenko@partner.samsung.com>
diff --git a/binutils-2.25/include/bfdlink.h b/binutils-2.25/include/bfdlink.h
index f3181ba6..125683db 100644
--- a/binutils-2.25/include/bfdlink.h
+++ b/binutils-2.25/include/bfdlink.h
@@ -417,9 +417,6 @@ struct bfd_link_info
   /* TRUE if the linker script contained an explicit PHDRS command.  */
   unsigned int user_phdrs: 1;
 
-  /* TRUE if BND prefix in PLT entries is always generated.  */
-  unsigned int bndplt: 1;
-
   /* Char that may appear as the first char of a symbol, but should be
      skipped (like symbol_leading_char) when looking up symbols in
      wrap_hash.  Used by PowerPC Linux for 'dot' symbols.  */
diff --git a/binutils-2.25/include/dwarf2.def b/binutils-2.25/include/dwarf2.def
index 71a37b30..215d29d6 100644
--- a/binutils-2.25/include/dwarf2.def
+++ b/binutils-2.25/include/dwarf2.def
@@ -202,6 +202,8 @@ DW_FORM (DW_FORM_sec_offset, 0x17)
 DW_FORM (DW_FORM_exprloc, 0x18)
 DW_FORM (DW_FORM_flag_present, 0x19)
 DW_FORM (DW_FORM_ref_sig8, 0x20)
+/* DWARF 5.  */
+DW_FORM (DW_FORM_line_strp, 0x1f)
 /* Extensions for Fission.  See http://gcc.gnu.org/wiki/DebugFission.  */
 DW_FORM (DW_FORM_GNU_addr_index, 0x1f01)
 DW_FORM (DW_FORM_GNU_str_index, 0x1f02)
diff --git a/binutils-2.25/include/dwarf2.h b/binutils-2.25/include/dwarf2.h
index e05955ca..b3030248 100644
--- a/binutils-2.25/include/dwarf2.h
+++ b/binutils-2.25/include/dwarf2.h
@@ -224,7 +224,13 @@ enum dwarf_line_number_ops
     /* DWARF 3.  */
     DW_LNS_set_prologue_end = 10,
     DW_LNS_set_epilogue_begin = 11,
-    DW_LNS_set_isa = 12
+    DW_LNS_set_isa = 12,
+    /* Experimental DWARF 5 extensions.
+       See http://wiki.dwarfstd.org/index.php?title=TwoLevelLineTables.  */
+    DW_LNS_set_address_from_logical = 13, /* Actuals table only.  */
+    DW_LNS_set_subprogram = 13,           /* Logicals table only.  */
+    DW_LNS_inlined_call = 14,             /* Logicals table only.  */
+    DW_LNS_pop_context = 15               /* Logicals table only.  */
   };
 
 /* Line number extended opcodes.  */
@@ -270,6 +276,22 @@ enum dwarf_location_list_entry_type
     DW_LLE_GNU_start_length_entry = 3
   };
 
+/* Type codes for line number program content descriptors (DWARF 5).  */
+
+enum dwarf_line_number_content_type
+  {
+    DW_LNCT_path = 1,
+    DW_LNCT_directory_index = 2,
+    DW_LNCT_timestamp = 3,
+    DW_LNCT_size = 4,
+    DW_LNCT_MD5 = 5,
+    /* Experimental DWARF 5 extensions.
+       See http://wiki.dwarfstd.org/index.php?title=TwoLevelLineTables.  */
+    DW_LNCT_subprogram_name = 6,
+    DW_LNCT_decl_file = 7,
+    DW_LNCT_decl_line = 8
+  };
+
 #define DW_CIE_ID	  0xffffffff
 #define DW64_CIE_ID	  0xffffffffffffffffULL
 #define DW_CIE_VERSION	  1
diff --git a/binutils-2.25/include/elf/ChangeLog b/binutils-2.25/include/elf/ChangeLog
index 17978ba3..d7767f5c 100644
--- a/binutils-2.25/include/elf/ChangeLog
+++ b/binutils-2.25/include/elf/ChangeLog
@@ -1,3 +1,15 @@
+2014-12-25  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* arm.h: New AEABI_FP_number_model_* and AEABI_VFP_args_* enum values.
+
+2014-11-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* x86-64.h (R_X86_64_GOTPLT64): Mark it obsolete.
+
+2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* sparc.h (ELF_SPARC_HWCAP2_VIS3B): Documentation improved.
+
 2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* sparc.h (Tag_GNU_Sparc_HWCAPS2): New object attribute.
diff --git a/binutils-2.25/include/elf/arm.h b/binutils-2.25/include/elf/arm.h
index 34afdfd9..e85536b7 100644
--- a/binutils-2.25/include/elf/arm.h
+++ b/binutils-2.25/include/elf/arm.h
@@ -319,6 +319,23 @@ enum
   Tag_VFP_HP_extension = Tag_FP_HP_extension
 };
 
+/* Values for Tag_ABI_FP_number_model.  */
+enum
+{
+  AEABI_FP_number_model_none = 0,
+  AEABI_FP_number_model_ieee754_number = 1,
+  AEABI_FP_number_model_rtabi = 2,
+  AEABI_FP_number_model_ieee754_all = 3
+};
+
+/* Values for Tag_ABI_VFP_args.  */
+enum
+{
+  AEABI_VFP_args_base = 0,
+  AEABI_VFP_args_vfp = 1,
+  AEABI_VFP_args_toolchain = 2,
+  AEABI_VFP_args_compatible = 3
+};
 #endif
 
 /* The name of the note section used to identify arm variants.  */
diff --git a/binutils-2.25/include/elf/epiphany.h b/binutils-2.25/include/elf/epiphany.h
index 38f973fb..38f973fb 100644..100755
--- a/binutils-2.25/include/elf/epiphany.h
+++ b/binutils-2.25/include/elf/epiphany.h
diff --git a/binutils-2.25/include/elf/mips.h b/binutils-2.25/include/elf/mips.h
index f3589fff..87704e04 100644
--- a/binutils-2.25/include/elf/mips.h
+++ b/binutils-2.25/include/elf/mips.h
@@ -1250,6 +1250,7 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
 #define AFL_EXT_5500         16  /* NEC VR5500 instruction.  */
 #define AFL_EXT_LOONGSON_2E  17  /* ST Microelectronics Loongson 2E.  */
 #define AFL_EXT_LOONGSON_2F  18  /* ST Microelectronics Loongson 2F.  */
+#define AFL_EXT_OCTEON3      19  /* Cavium Networks Octeon3.  */
 
 /* Masks for the flags1 word of an ABI flags structure.  */
 #define AFL_FLAGS1_ODDSPREG   1	 /* Uses odd single-precision registers.  */
diff --git a/binutils-2.25/include/elf/sparc.h b/binutils-2.25/include/elf/sparc.h
index d41ba35b..fd17a24f 100644
--- a/binutils-2.25/include/elf/sparc.h
+++ b/binutils-2.25/include/elf/sparc.h
@@ -237,7 +237,7 @@ enum
 #define ELF_SPARC_HWCAP_CRC32C	0x20000000 /* CRC32C insn */
 
 #define ELF_SPARC_HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
-#define ELF_SPARC_HWCAP2_VIS3B     0x00000002 /* VIS3 present on multiple chips */
+#define ELF_SPARC_HWCAP2_VIS3B     0x00000002 /* Subset of VIS3 present on sparc64 X+ */
 #define ELF_SPARC_HWCAP2_ADP       0x00000004 /* Application Data Protection */
 #define ELF_SPARC_HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
 #define ELF_SPARC_HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
diff --git a/binutils-2.25/include/elf/x86-64.h b/binutils-2.25/include/elf/x86-64.h
index d0dda478..13f87b27 100644
--- a/binutils-2.25/include/elf/x86-64.h
+++ b/binutils-2.25/include/elf/x86-64.h
@@ -58,8 +58,7 @@ START_RELOC_NUMBERS (elf_x86_64_reloc_type)
      						 offset to GOT entry */
      RELOC_NUMBER (R_X86_64_GOTPC64,  29)     /* 64 bit signed pc relative
      						 offset to GOT */
-     RELOC_NUMBER (R_X86_64_GOTPLT64, 30)     /* like GOT64, but indicates
-     						 that PLT entry is needed */
+     RELOC_NUMBER (R_X86_64_GOTPLT64, 30)     /* Obsolete. The same as GOT64. */
      RELOC_NUMBER (R_X86_64_PLTOFF64, 31)     /* 64 bit GOT relative offset
      						 to PLT entry */
      RELOC_NUMBER (R_X86_64_SIZE32,   32)     /* 32-bit symbol size */
diff --git a/binutils-2.25/include/opcode/ChangeLog b/binutils-2.25/include/opcode/ChangeLog
index d378910e..d40c9fd0 100644
--- a/binutils-2.25/include/opcode/ChangeLog
+++ b/binutils-2.25/include/opcode/ChangeLog
@@ -1,3 +1,62 @@
+2014-11-06  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2.h (nios2_find_opcode_hash): Add mach parameter to
+	declaration.  Fix obsolete comment.
+
+2014-10-23  Sandra Loosemore  <sandra@codesourcery.com>
+
+	* nios2.h (enum iw_format_type): New.
+	(struct nios2_opcode): Update comments.  Add size and format fields.
+	(NIOS2_INSN_OPTARG): New.
+	(REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
+	(struct nios2_reg): Add regtype field.
+	(GET_INSN_FIELD, SET_INSN_FIELD): Delete.
+	(IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
+	(IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
+	(IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
+	(IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
+	(IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
+	(IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
+	(IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
+	(IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
+	(IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
+	(IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
+	(IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
+	(OP_MASK_OP, OP_SH_OP): Delete.
+	(OP_MASK_IOP, OP_SH_IOP): Delete.
+	(OP_MASK_IRD, OP_SH_IRD): Delete.
+	(OP_MASK_IRT, OP_SH_IRT): Delete.
+	(OP_MASK_IRS, OP_SH_IRS): Delete.
+	(OP_MASK_ROP, OP_SH_ROP): Delete.
+	(OP_MASK_RRD, OP_SH_RRD): Delete.
+	(OP_MASK_RRT, OP_SH_RRT): Delete.
+	(OP_MASK_RRS, OP_SH_RRS): Delete.
+	(OP_MASK_JOP, OP_SH_JOP): Delete.
+	(OP_MASK_IMM26, OP_SH_IMM26): Delete.
+	(OP_MASK_RCTL, OP_SH_RCTL): Delete.
+	(OP_MASK_IMM5, OP_SH_IMM5): Delete.
+	(OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
+	(OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
+	(OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
+	(OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
+	(OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
+	(OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
+	(OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
+	(OP_MASK_<insn>, OP_MASK): Delete.
+	(GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
+	(GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
+	Include nios2r1.h to define new instruction opcode constants
+	and accessors.
+	(nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
+	(bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
+	(bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
+	(NUMOPCODES, NUMREGISTERS): Delete.
+	* nios2r1.h: New file.
+
+2014-10-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* sparc.h (HWCAP2_VIS3B): Documentation improved.
+
 2014-10-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* sparc.h (sparc_opcode): new field `hwcaps2'.
diff --git a/binutils-2.25/include/opcode/bfin.h b/binutils-2.25/include/opcode/bfin.h
index fafe0d8a..fafe0d8a 100644..100755
--- a/binutils-2.25/include/opcode/bfin.h
+++ b/binutils-2.25/include/opcode/bfin.h
diff --git a/binutils-2.25/include/opcode/mips.h b/binutils-2.25/include/opcode/mips.h
index 28826997..471f6c8b 100644
--- a/binutils-2.25/include/opcode/mips.h
+++ b/binutils-2.25/include/opcode/mips.h
@@ -1216,6 +1216,7 @@ static const unsigned int mips_isa_table[] = {
 #define INSN_OCTEON		  0x00000800
 #define INSN_OCTEONP		  0x00000200
 #define INSN_OCTEON2		  0x00000100
+#define INSN_OCTEON3		  0x00000040
 
 /* MIPS R5900 instruction */
 #define INSN_5900                 0x00004000
@@ -1346,6 +1347,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_OCTEON	6501
 #define CPU_OCTEONP	6601
 #define CPU_OCTEON2	6502
+#define CPU_OCTEON3	6503
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
 
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
@@ -1411,6 +1413,9 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_OCTEON2:
       return (mask & INSN_OCTEON2) != 0;
 
+    case CPU_OCTEON3:
+      return (mask & INSN_OCTEON3) != 0;
+
     case CPU_XLR:
       return (mask & INSN_XLR) != 0;
 
diff --git a/binutils-2.25/include/opcode/nios2.h b/binutils-2.25/include/opcode/nios2.h
index 04beff93..6b4c2f50 100644
--- a/binutils-2.25/include/opcode/nios2.h
+++ b/binutils-2.25/include/opcode/nios2.h
@@ -31,6 +31,15 @@
  * access various opcode fields.
  ****************************************************************************/
 
+/* Instruction encoding formats.  */
+enum iw_format_type {
+  /* R1 formats */
+  iw_i_type,
+  iw_r_type,
+  iw_j_type,
+  iw_custom_type
+};
+
 /* Identify different overflow situations for error messages.  */
 enum overflow_type
 {
@@ -56,12 +65,14 @@ enum overflow_type
      u - a 16-bit unsigned immediate
      o - a 16-bit signed program counter relative offset
      j - a 5-bit unsigned immediate
-     b - a 5-bit break instruction constant
      l - a 8-bit custom instruction constant
      m - a 26-bit unsigned immediate
    Literal ',', '(', and ')' characters may also appear in the args as
    delimiters.
 
+   Note that the args describe the semantics and assembly-language syntax
+   of the operands, not their encoding into the instruction word.
+
    The pinfo field is INSN_MACRO for a macro.  Otherwise, it is a collection
    of bits describing the instruction, notably any relevant hazard
    information.
@@ -84,6 +95,8 @@ struct nios2_opcode
 				   the expected opcode.  */
   unsigned long num_args;	/* The number of arguments the instruction 
 				   takes.  */
+  unsigned size;		/* Size in bytes of the instruction.  */
+  enum iw_format_type format;	/* Instruction format.  */
   unsigned long match;		/* The basic opcode for the instruction.  */
   unsigned long mask;		/* Mask for the opcode field of the 
 				   instruction.  */
@@ -112,398 +125,28 @@ struct nios2_opcode
 #define NIOS2_INSN_ORI		0x00000200
 #define NIOS2_INSN_XORI		0x00000400
 
+#define NIOS2_INSN_OPTARG	0x00000800
+
+/* Register attributes.  */
+#define REG_NORMAL	(1<<0)	/* Normal registers.  */
+#define REG_CONTROL	(1<<1)  /* Control registers.  */
+#define REG_COPROCESSOR	(1<<2)  /* For custom instructions.  */
 
-/* Associates a register name ($6) with a 5-bit index (eg 6).  */
 struct nios2_reg
 {
   const char *name;
   const int index;
+  unsigned long regtype;
 };
 
+/* Pull in the instruction field accessors, opcodes, and masks.  */
+#include "nios2r1.h"
 
-/* These are bit masks and shift counts for accessing the various
-   fields of a Nios II instruction.  */
-
-/* Macros for getting and setting an instruction field.  */
-#define GET_INSN_FIELD(X, i) \
-  (((i) & OP_MASK_##X) >> OP_SH_##X)
-#define SET_INSN_FIELD(X, i, j) \
-  ((i) = (((i) & ~OP_MASK_##X) | (((j) << OP_SH_##X) & OP_MASK_##X)))
-
-/* Instruction field definitions.  */
-#define IW_A_LSB 27
-#define IW_A_MSB 31
-#define IW_A_SZ 5
-#define IW_A_MASK 0x1f
-
-#define IW_B_LSB 22
-#define IW_B_MSB 26
-#define IW_B_SZ 5
-#define IW_B_MASK 0x1f
-
-#define IW_C_LSB 17
-#define IW_C_MSB 21
-#define IW_C_SZ 5
-#define IW_C_MASK 0x1f
-
-#define IW_IMM16_LSB 6
-#define IW_IMM16_MSB 21
-#define IW_IMM16_SZ 16
-#define IW_IMM16_MASK 0xffff
-
-#define IW_IMM26_LSB 6
-#define IW_IMM26_MSB 31
-#define IW_IMM26_SZ 26
-#define IW_IMM26_MASK 0x3ffffff
-
-#define IW_OP_LSB 0
-#define IW_OP_MSB 5
-#define IW_OP_SZ 6
-#define IW_OP_MASK 0x3f
-
-#define IW_OPX_LSB 11
-#define IW_OPX_MSB 16
-#define IW_OPX_SZ 6
-#define IW_OPX_MASK 0x3f
-
-#define IW_SHIFT_IMM5_LSB 6
-#define IW_SHIFT_IMM5_MSB 10
-#define IW_SHIFT_IMM5_SZ 5
-#define IW_SHIFT_IMM5_MASK 0x1f
-
-#define IW_CONTROL_REGNUM_LSB 6
-#define IW_CONTROL_REGNUM_MSB 9
-#define IW_CONTROL_REGNUM_SZ 4
-#define IW_CONTROL_REGNUM_MASK 0xf
-
-/* Operator mask and shift.  */
-#define OP_MASK_OP		(IW_OP_MASK << IW_OP_LSB)
-#define OP_SH_OP		IW_OP_LSB
-
-/* Masks and shifts for I-type instructions.  */
-#define OP_MASK_IOP		(IW_OP_MASK << IW_OP_LSB)
-#define OP_SH_IOP		IW_OP_LSB
-
-#define OP_MASK_IMM16		(IW_IMM16_MASK << IW_IMM16_LSB)
-#define OP_SH_IMM16		IW_IMM16_LSB
-
-#define OP_MASK_IRD		(IW_B_MASK << IW_B_LSB)
-#define OP_SH_IRD		IW_B_LSB /* The same as T for I-type.  */
-
-#define OP_MASK_IRT		(IW_B_MASK << IW_B_LSB)
-#define OP_SH_IRT		IW_B_LSB
-
-#define OP_MASK_IRS		(IW_A_MASK << IW_A_LSB)
-#define OP_SH_IRS		IW_A_LSB
-
-/* Masks and shifts for R-type instructions.  */
-#define OP_MASK_ROP		(IW_OP_MASK << IW_OP_LSB)
-#define OP_SH_ROP		IW_OP_LSB
-
-#define OP_MASK_ROPX		(IW_OPX_MASK << IW_OPX_LSB)
-#define OP_SH_ROPX		IW_OPX_LSB
-
-#define OP_MASK_RRD		(IW_C_MASK << IW_C_LSB)
-#define OP_SH_RRD		IW_C_LSB
-
-#define OP_MASK_RRT		(IW_B_MASK << IW_B_LSB)
-#define OP_SH_RRT		IW_B_LSB
-
-#define OP_MASK_RRS		(IW_A_MASK << IW_A_LSB)
-#define OP_SH_RRS		IW_A_LSB
-
-/* Masks and shifts for J-type instructions.  */
-#define OP_MASK_JOP		(IW_OP_MASK << IW_OP_LSB)
-#define OP_SH_JOP		IW_OP_LSB
-
-#define OP_MASK_IMM26		(IW_IMM26_MASK << IW_IMM26_LSB)
-#define OP_SH_IMM26		IW_IMM26_LSB
-
-/* Masks and shifts for CTL instructions.  */
-#define OP_MASK_RCTL	0x000007c0
-#define OP_SH_RCTL	6
-
-/* Break instruction imm5 field.  */
-#define OP_MASK_TRAP_IMM5 0x000007c0
-#define OP_SH_TRAP_IMM5	  6
-
-/* Instruction imm5 field.  */
-#define OP_MASK_IMM5		(IW_SHIFT_IMM5_MASK << IW_SHIFT_IMM5_LSB)
-#define OP_SH_IMM5		IW_SHIFT_IMM5_LSB
-
-/* Cache operation fields (type j,i(s)).  */
-#define OP_MASK_CACHE_OPX	(IW_B_MASK << IW_B_LSB)
-#define OP_SH_CACHE_OPX		IW_B_LSB
-#define OP_MASK_CACHE_RRS	(IW_A_MASK << IW_A_LSB)
-#define OP_SH_CACHE_RRS		IW_A_LSB
-
-/* Custom instruction masks.  */
-#define OP_MASK_CUSTOM_A	0x00010000
-#define OP_SH_CUSTOM_A		16
-
-#define OP_MASK_CUSTOM_B	0x00008000
-#define OP_SH_CUSTOM_B		15
-
-#define OP_MASK_CUSTOM_C	0x00004000
-#define OP_SH_CUSTOM_C		14
-
-#define OP_MASK_CUSTOM_N	0x00003fc0
-#define OP_SH_CUSTOM_N		6
-#define OP_MAX_CUSTOM_N		255
-
-/* OP instruction values. */
-#define OP_ADDI 4
-#define OP_ANDHI 44
-#define OP_ANDI 12
-#define OP_BEQ 38
-#define OP_BGE 14
-#define OP_BGEU 46
-#define OP_BLT 22
-#define OP_BLTU 54
-#define OP_BNE 30
-#define OP_BR 6
-#define OP_CALL 0
-#define OP_CMPEQI 32
-#define OP_CMPGEI 8
-#define OP_CMPGEUI 40
-#define OP_CMPLTI 16
-#define OP_CMPLTUI 48
-#define OP_CMPNEI 24
-#define OP_CUSTOM 50
-#define OP_FLUSHD 59
-#define OP_FLUSHDA 27
-#define OP_INITD 51
-#define OP_INITDA 19
-#define OP_JMPI 1
-#define OP_LDB 7
-#define OP_LDBIO 39
-#define OP_LDBU 3
-#define OP_LDBUIO 35
-#define OP_LDH 15
-#define OP_LDHIO 47
-#define OP_LDHU 11
-#define OP_LDHUIO 43
-#define OP_LDL 31
-#define OP_LDW 23
-#define OP_LDWIO 55
-#define OP_MULI 36
-#define OP_OPX 58
-#define OP_ORHI 52
-#define OP_ORI 20
-#define OP_RDPRS 56
-#define OP_STB 5
-#define OP_STBIO 37
-#define OP_STC 29
-#define OP_STH 13
-#define OP_STHIO 45
-#define OP_STW 21
-#define OP_STWIO 53
-#define OP_XORHI 60
-#define OP_XORI 28
-
-/* OPX instruction values.  */
-#define OPX_ADD 49
-#define OPX_AND 14
-#define OPX_BREAK 52
-#define OPX_BRET 9
-#define OPX_CALLR 29
-#define OPX_CMPEQ 32
-#define OPX_CMPGE 8
-#define OPX_CMPGEU 40
-#define OPX_CMPLT 16
-#define OPX_CMPLTU 48
-#define OPX_CMPNE 24
-#define OPX_CRST 62
-#define OPX_DIV 37
-#define OPX_DIVU 36
-#define OPX_ERET 1
-#define OPX_FLUSHI 12
-#define OPX_FLUSHP 4
-#define OPX_HBREAK 53
-#define OPX_INITI 41
-#define OPX_INTR 61
-#define OPX_JMP 13
-#define OPX_MUL 39
-#define OPX_MULXSS 31
-#define OPX_MULXSU 23
-#define OPX_MULXUU 7
-#define OPX_NEXTPC 28
-#define OPX_NOR 6
-#define OPX_OR 22
-#define OPX_RDCTL 38
-#define OPX_RET 5
-#define OPX_ROL 3
-#define OPX_ROLI 2
-#define OPX_ROR 11
-#define OPX_SLL 19
-#define OPX_SLLI 18
-#define OPX_SRA 59
-#define OPX_SRAI 58
-#define OPX_SRL 27
-#define OPX_SRLI 26
-#define OPX_SUB 57
-#define OPX_SYNC 54
-#define OPX_TRAP 45
-#define OPX_WRCTL 46
-#define OPX_WRPRS 20
-#define OPX_XOR 30
-
-/* The following macros define the opcode matches for each
-   instruction code & OP_MASK_INST == OP_MATCH_INST.  */
-
-/* OP instruction matches.  */
-#define OP_MATCH_ADDI		OP_ADDI
-#define OP_MATCH_ANDHI		OP_ANDHI
-#define OP_MATCH_ANDI		OP_ANDI
-#define OP_MATCH_BEQ		OP_BEQ
-#define OP_MATCH_BGE		OP_BGE
-#define OP_MATCH_BGEU		OP_BGEU
-#define OP_MATCH_BLT		OP_BLT
-#define OP_MATCH_BLTU		OP_BLTU
-#define OP_MATCH_BNE		OP_BNE
-#define OP_MATCH_BR		OP_BR
-#define OP_MATCH_FLUSHD		OP_FLUSHD
-#define OP_MATCH_FLUSHDA	OP_FLUSHDA
-#define OP_MATCH_INITD		OP_INITD
-#define OP_MATCH_INITDA		OP_INITDA
-#define OP_MATCH_CALL		OP_CALL
-#define OP_MATCH_CMPEQI		OP_CMPEQI
-#define OP_MATCH_CMPGEI		OP_CMPGEI
-#define OP_MATCH_CMPGEUI	OP_CMPGEUI
-#define OP_MATCH_CMPLTI		OP_CMPLTI
-#define OP_MATCH_CMPLTUI	OP_CMPLTUI
-#define OP_MATCH_CMPNEI		OP_CMPNEI
-#define OP_MATCH_JMPI		OP_JMPI
-#define OP_MATCH_LDB		OP_LDB
-#define OP_MATCH_LDBIO		OP_LDBIO
-#define OP_MATCH_LDBU		OP_LDBU
-#define OP_MATCH_LDBUIO		OP_LDBUIO
-#define OP_MATCH_LDH		OP_LDH
-#define OP_MATCH_LDHIO		OP_LDHIO
-#define OP_MATCH_LDHU		OP_LDHU
-#define OP_MATCH_LDHUIO		OP_LDHUIO
-#define OP_MATCH_LDL		OP_LDL
-#define OP_MATCH_LDW		OP_LDW
-#define OP_MATCH_LDWIO		OP_LDWIO
-#define OP_MATCH_MULI		OP_MULI
-#define OP_MATCH_OPX		OP_OPX
-#define OP_MATCH_ORHI		OP_ORHI
-#define OP_MATCH_ORI		OP_ORI
-#define OP_MATCH_RDPRS		OP_RDPRS
-#define OP_MATCH_STB		OP_STB
-#define OP_MATCH_STBIO		OP_STBIO
-#define OP_MATCH_STC		OP_STC
-#define OP_MATCH_STH		OP_STH
-#define OP_MATCH_STHIO		OP_STHIO
-#define OP_MATCH_STW		OP_STW
-#define OP_MATCH_STWIO		OP_STWIO
-#define OP_MATCH_CUSTOM		OP_CUSTOM
-#define OP_MATCH_XORHI		OP_XORHI
-#define OP_MATCH_XORI		OP_XORI
-#define OP_MATCH_OPX		OP_OPX
-
-/* OPX instruction values.  */
-#define OPX_MATCH(code) ((code << IW_OPX_LSB) | OP_OPX)
-
-#define OP_MATCH_ADD		OPX_MATCH (OPX_ADD)
-#define OP_MATCH_AND		OPX_MATCH (OPX_AND)
-#define OP_MATCH_BREAK		((0x1e << 17) | OPX_MATCH (OPX_BREAK))
-#define OP_MATCH_BRET		(0xf0000000 | OPX_MATCH (OPX_BRET))
-#define OP_MATCH_CALLR		((0x1f << 17) | OPX_MATCH (OPX_CALLR))
-#define OP_MATCH_CMPEQ		OPX_MATCH (OPX_CMPEQ)
-#define OP_MATCH_CMPGE		OPX_MATCH (OPX_CMPGE)
-#define OP_MATCH_CMPGEU		OPX_MATCH (OPX_CMPGEU)
-#define OP_MATCH_CMPLT		OPX_MATCH (OPX_CMPLT)
-#define OP_MATCH_CMPLTU		OPX_MATCH (OPX_CMPLTU)
-#define OP_MATCH_CMPNE		OPX_MATCH (OPX_CMPNE)
-#define OP_MATCH_DIV		OPX_MATCH (OPX_DIV)
-#define OP_MATCH_DIVU		OPX_MATCH (OPX_DIVU)
-#define OP_MATCH_JMP		OPX_MATCH (OPX_JMP)
-#define OP_MATCH_MUL		OPX_MATCH (OPX_MUL)
-#define OP_MATCH_MULXSS		OPX_MATCH (OPX_MULXSS)
-#define OP_MATCH_MULXSU		OPX_MATCH (OPX_MULXSU)
-#define OP_MATCH_MULXUU		OPX_MATCH (OPX_MULXUU)
-#define OP_MATCH_NEXTPC		OPX_MATCH (OPX_NEXTPC)
-#define OP_MATCH_NOR		OPX_MATCH (OPX_NOR)
-#define OP_MATCH_OR		OPX_MATCH (OPX_OR)
-#define OP_MATCH_RDCTL		OPX_MATCH (OPX_RDCTL)
-#define OP_MATCH_RET		(0xf8000000 | OPX_MATCH (OPX_RET))
-#define OP_MATCH_ROL		OPX_MATCH (OPX_ROL)
-#define OP_MATCH_ROLI		OPX_MATCH (OPX_ROLI)
-#define OP_MATCH_ROR		OPX_MATCH (OPX_ROR)
-#define OP_MATCH_SLL		OPX_MATCH (OPX_SLL)
-#define OP_MATCH_SLLI		OPX_MATCH (OPX_SLLI)
-#define OP_MATCH_SRA		OPX_MATCH (OPX_SRA)
-#define OP_MATCH_SRAI		OPX_MATCH (OPX_SRAI)
-#define OP_MATCH_SRL		OPX_MATCH (OPX_SRL)
-#define OP_MATCH_SRLI		OPX_MATCH (OPX_SRLI)
-#define OP_MATCH_SUB		OPX_MATCH (OPX_SUB)
-#define OP_MATCH_SYNC		OPX_MATCH (OPX_SYNC)
-#define OP_MATCH_TRAP		((0x1d << 17) | OPX_MATCH (OPX_TRAP))
-#define OP_MATCH_ERET		(0xef800000 | OPX_MATCH (OPX_ERET))
-#define OP_MATCH_WRCTL		OPX_MATCH (OPX_WRCTL)
-#define OP_MATCH_WRPRS		OPX_MATCH (OPX_WRPRS)
-#define OP_MATCH_XOR		OPX_MATCH (OPX_XOR)
-#define OP_MATCH_FLUSHI		OPX_MATCH (OPX_FLUSHI)
-#define OP_MATCH_FLUSHP		OPX_MATCH (OPX_FLUSHP)
-#define OP_MATCH_INITI		OPX_MATCH (OPX_INITI)
-
-/* Some unusual op masks.  */
-#define OP_MASK_BREAK		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
-				  | OP_MASK_ROPX | OP_MASK_OP) \
-				 & 0xfffff03f)
-#define OP_MASK_CALLR		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
-				  | OP_MASK_OP))
-#define OP_MASK_JMP		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
-				  | OP_MASK_OP))
-#define OP_MASK_SYNC		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
-				  | OP_MASK_OP))
-#define OP_MASK_TRAP		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_RRD \
-				  | OP_MASK_ROPX | OP_MASK_OP) \
-				 & 0xfffff83f)
-#define OP_MASK_WRCTL		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
-				  | OP_MASK_OP))	/*& 0xfffff83f */
-#define OP_MASK_NEXTPC		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
-				  | OP_MASK_OP))
-#define OP_MASK_FLUSHI		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
-				  | OP_MASK_OP))
-#define OP_MASK_INITI		((OP_MASK_RRT | OP_MASK_RRD | OP_MASK_ROPX \
-				  | OP_MASK_OP))
-
-#define OP_MASK_ROLI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
-#define OP_MASK_SLLI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
-#define OP_MASK_SRAI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
-#define OP_MASK_SRLI		((OP_MASK_RRT | OP_MASK_ROPX | OP_MASK_OP))
-#define OP_MASK_RDCTL		((OP_MASK_RRS | OP_MASK_RRT | OP_MASK_ROPX \
-				  | OP_MASK_OP))	/*& 0xfffff83f */
-
-#ifndef OP_MASK
-#define OP_MASK				0xffffffff
-#endif
-
-/* These convenience macros to extract instruction fields are used by GDB.  */
-#define GET_IW_A(Iw) \
-    (((Iw) >> IW_A_LSB) & IW_A_MASK)
-#define GET_IW_B(Iw) \
-    (((Iw) >> IW_B_LSB) & IW_B_MASK)
-#define GET_IW_C(Iw) \
-    (((Iw) >> IW_C_LSB) & IW_C_MASK)
-#define GET_IW_CONTROL_REGNUM(Iw) \
-    (((Iw) >> IW_CONTROL_REGNUM_LSB) & IW_CONTROL_REGNUM_MASK)
-#define GET_IW_IMM16(Iw) \
-    (((Iw) >> IW_IMM16_LSB) & IW_IMM16_MASK)
-#define GET_IW_IMM26(Iw) \
-    (((Iw) >> IW_IMM26_LSB) & IW_IMM26_MASK)
-#define GET_IW_OP(Iw) \
-    (((Iw) >> IW_OP_LSB) & IW_OP_MASK)
-#define GET_IW_OPX(Iw) \
-    (((Iw) >> IW_OPX_LSB) & IW_OPX_MASK)
-
-/* These are the data structures we use to hold the instruction information.  */
-extern const struct nios2_opcode nios2_builtin_opcodes[];
-extern const int bfd_nios2_num_builtin_opcodes;
+/* These are the data structures used to hold the instruction information.  */
+extern const struct nios2_opcode nios2_r1_opcodes[];
+extern const int nios2_num_r1_opcodes;
 extern struct nios2_opcode *nios2_opcodes;
-extern int bfd_nios2_num_opcodes;
+extern int nios2_num_opcodes;
 
 /* These are the data structures used to hold the register information.  */
 extern const struct nios2_reg nios2_builtin_regs[];
@@ -511,12 +154,8 @@ extern struct nios2_reg *nios2_regs;
 extern const int nios2_num_builtin_regs;
 extern int nios2_num_regs;
 
-/* Machine-independent macro for number of opcodes.  */
-#define NUMOPCODES bfd_nios2_num_opcodes
-#define NUMREGISTERS nios2_num_regs;
-
-/* This is made extern so that the assembler can use it to find out
-   what instruction caused an error.  */
-extern const struct nios2_opcode *nios2_find_opcode_hash (unsigned long);
+/* Return the opcode descriptor for a single instruction.  */
+extern const struct nios2_opcode *
+nios2_find_opcode_hash (unsigned long, unsigned long);
 
 #endif /* _NIOS2_H */
diff --git a/binutils-2.25/include/opcode/nios2r1.h b/binutils-2.25/include/opcode/nios2r1.h
new file mode 100644
index 00000000..32a517d8
--- /dev/null
+++ b/binutils-2.25/include/opcode/nios2r1.h
@@ -0,0 +1,474 @@
+/* Nios II R1 opcode list for GAS, the GNU assembler.
+   Copyright (C) 2013-2014 Free Software Foundation, Inc.
+   Contributed by Mentor Graphics, Inc.
+
+   This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
+
+   GAS/GDB is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS/GDB is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS or GDB; see the file COPYING3.  If not, write to
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+#ifndef _NIOS2R1_H_
+#define _NIOS2R1_H_
+
+/* R1 fields.  */
+#define IW_R1_OP_LSB 0 
+#define IW_R1_OP_SIZE 6 
+#define IW_R1_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R1_OP_SIZE)) 
+#define IW_R1_OP_SHIFTED_MASK (IW_R1_OP_UNSHIFTED_MASK << IW_R1_OP_LSB) 
+#define GET_IW_R1_OP(W) (((W) >> IW_R1_OP_LSB) & IW_R1_OP_UNSHIFTED_MASK) 
+#define SET_IW_R1_OP(V) (((V) & IW_R1_OP_UNSHIFTED_MASK) << IW_R1_OP_LSB) 
+
+#define IW_I_A_LSB 27 
+#define IW_I_A_SIZE 5 
+#define IW_I_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_A_SIZE)) 
+#define IW_I_A_SHIFTED_MASK (IW_I_A_UNSHIFTED_MASK << IW_I_A_LSB) 
+#define GET_IW_I_A(W) (((W) >> IW_I_A_LSB) & IW_I_A_UNSHIFTED_MASK) 
+#define SET_IW_I_A(V) (((V) & IW_I_A_UNSHIFTED_MASK) << IW_I_A_LSB) 
+
+#define IW_I_B_LSB 22 
+#define IW_I_B_SIZE 5 
+#define IW_I_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_B_SIZE)) 
+#define IW_I_B_SHIFTED_MASK (IW_I_B_UNSHIFTED_MASK << IW_I_B_LSB) 
+#define GET_IW_I_B(W) (((W) >> IW_I_B_LSB) & IW_I_B_UNSHIFTED_MASK) 
+#define SET_IW_I_B(V) (((V) & IW_I_B_UNSHIFTED_MASK) << IW_I_B_LSB) 
+
+#define IW_I_IMM16_LSB 6 
+#define IW_I_IMM16_SIZE 16 
+#define IW_I_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_IMM16_SIZE)) 
+#define IW_I_IMM16_SHIFTED_MASK (IW_I_IMM16_UNSHIFTED_MASK << IW_I_IMM16_LSB) 
+#define GET_IW_I_IMM16(W) (((W) >> IW_I_IMM16_LSB) & IW_I_IMM16_UNSHIFTED_MASK) 
+#define SET_IW_I_IMM16(V) (((V) & IW_I_IMM16_UNSHIFTED_MASK) << IW_I_IMM16_LSB) 
+
+#define IW_R_A_LSB 27 
+#define IW_R_A_SIZE 5 
+#define IW_R_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_A_SIZE)) 
+#define IW_R_A_SHIFTED_MASK (IW_R_A_UNSHIFTED_MASK << IW_R_A_LSB) 
+#define GET_IW_R_A(W) (((W) >> IW_R_A_LSB) & IW_R_A_UNSHIFTED_MASK) 
+#define SET_IW_R_A(V) (((V) & IW_R_A_UNSHIFTED_MASK) << IW_R_A_LSB) 
+
+#define IW_R_B_LSB 22 
+#define IW_R_B_SIZE 5 
+#define IW_R_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_B_SIZE)) 
+#define IW_R_B_SHIFTED_MASK (IW_R_B_UNSHIFTED_MASK << IW_R_B_LSB) 
+#define GET_IW_R_B(W) (((W) >> IW_R_B_LSB) & IW_R_B_UNSHIFTED_MASK) 
+#define SET_IW_R_B(V) (((V) & IW_R_B_UNSHIFTED_MASK) << IW_R_B_LSB) 
+
+#define IW_R_C_LSB 17 
+#define IW_R_C_SIZE 5 
+#define IW_R_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_C_SIZE)) 
+#define IW_R_C_SHIFTED_MASK (IW_R_C_UNSHIFTED_MASK << IW_R_C_LSB) 
+#define GET_IW_R_C(W) (((W) >> IW_R_C_LSB) & IW_R_C_UNSHIFTED_MASK) 
+#define SET_IW_R_C(V) (((V) & IW_R_C_UNSHIFTED_MASK) << IW_R_C_LSB) 
+
+#define IW_R_OPX_LSB 11 
+#define IW_R_OPX_SIZE 6 
+#define IW_R_OPX_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_OPX_SIZE)) 
+#define IW_R_OPX_SHIFTED_MASK (IW_R_OPX_UNSHIFTED_MASK << IW_R_OPX_LSB) 
+#define GET_IW_R_OPX(W) (((W) >> IW_R_OPX_LSB) & IW_R_OPX_UNSHIFTED_MASK) 
+#define SET_IW_R_OPX(V) (((V) & IW_R_OPX_UNSHIFTED_MASK) << IW_R_OPX_LSB) 
+
+#define IW_R_IMM5_LSB 6 
+#define IW_R_IMM5_SIZE 5 
+#define IW_R_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_IMM5_SIZE)) 
+#define IW_R_IMM5_SHIFTED_MASK (IW_R_IMM5_UNSHIFTED_MASK << IW_R_IMM5_LSB) 
+#define GET_IW_R_IMM5(W) (((W) >> IW_R_IMM5_LSB) & IW_R_IMM5_UNSHIFTED_MASK) 
+#define SET_IW_R_IMM5(V) (((V) & IW_R_IMM5_UNSHIFTED_MASK) << IW_R_IMM5_LSB) 
+
+#define IW_J_IMM26_LSB 6 
+#define IW_J_IMM26_SIZE 26 
+#define IW_J_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_J_IMM26_SIZE)) 
+#define IW_J_IMM26_SHIFTED_MASK (IW_J_IMM26_UNSHIFTED_MASK << IW_J_IMM26_LSB) 
+#define GET_IW_J_IMM26(W) (((W) >> IW_J_IMM26_LSB) & IW_J_IMM26_UNSHIFTED_MASK) 
+#define SET_IW_J_IMM26(V) (((V) & IW_J_IMM26_UNSHIFTED_MASK) << IW_J_IMM26_LSB) 
+
+#define IW_CUSTOM_A_LSB 27 
+#define IW_CUSTOM_A_SIZE 5 
+#define IW_CUSTOM_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_A_SIZE)) 
+#define IW_CUSTOM_A_SHIFTED_MASK (IW_CUSTOM_A_UNSHIFTED_MASK << IW_CUSTOM_A_LSB) 
+#define GET_IW_CUSTOM_A(W) (((W) >> IW_CUSTOM_A_LSB) & IW_CUSTOM_A_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_A(V) (((V) & IW_CUSTOM_A_UNSHIFTED_MASK) << IW_CUSTOM_A_LSB) 
+
+#define IW_CUSTOM_B_LSB 22 
+#define IW_CUSTOM_B_SIZE 5 
+#define IW_CUSTOM_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_B_SIZE)) 
+#define IW_CUSTOM_B_SHIFTED_MASK (IW_CUSTOM_B_UNSHIFTED_MASK << IW_CUSTOM_B_LSB) 
+#define GET_IW_CUSTOM_B(W) (((W) >> IW_CUSTOM_B_LSB) & IW_CUSTOM_B_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_B(V) (((V) & IW_CUSTOM_B_UNSHIFTED_MASK) << IW_CUSTOM_B_LSB) 
+
+#define IW_CUSTOM_C_LSB 17 
+#define IW_CUSTOM_C_SIZE 5 
+#define IW_CUSTOM_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_C_SIZE)) 
+#define IW_CUSTOM_C_SHIFTED_MASK (IW_CUSTOM_C_UNSHIFTED_MASK << IW_CUSTOM_C_LSB) 
+#define GET_IW_CUSTOM_C(W) (((W) >> IW_CUSTOM_C_LSB) & IW_CUSTOM_C_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_C(V) (((V) & IW_CUSTOM_C_UNSHIFTED_MASK) << IW_CUSTOM_C_LSB) 
+
+#define IW_CUSTOM_READA_LSB 16 
+#define IW_CUSTOM_READA_SIZE 1 
+#define IW_CUSTOM_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READA_SIZE)) 
+#define IW_CUSTOM_READA_SHIFTED_MASK (IW_CUSTOM_READA_UNSHIFTED_MASK << IW_CUSTOM_READA_LSB) 
+#define GET_IW_CUSTOM_READA(W) (((W) >> IW_CUSTOM_READA_LSB) & IW_CUSTOM_READA_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_READA(V) (((V) & IW_CUSTOM_READA_UNSHIFTED_MASK) << IW_CUSTOM_READA_LSB) 
+
+#define IW_CUSTOM_READB_LSB 15 
+#define IW_CUSTOM_READB_SIZE 1 
+#define IW_CUSTOM_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READB_SIZE)) 
+#define IW_CUSTOM_READB_SHIFTED_MASK (IW_CUSTOM_READB_UNSHIFTED_MASK << IW_CUSTOM_READB_LSB) 
+#define GET_IW_CUSTOM_READB(W) (((W) >> IW_CUSTOM_READB_LSB) & IW_CUSTOM_READB_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_READB(V) (((V) & IW_CUSTOM_READB_UNSHIFTED_MASK) << IW_CUSTOM_READB_LSB) 
+
+#define IW_CUSTOM_READC_LSB 14 
+#define IW_CUSTOM_READC_SIZE 1 
+#define IW_CUSTOM_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READC_SIZE)) 
+#define IW_CUSTOM_READC_SHIFTED_MASK (IW_CUSTOM_READC_UNSHIFTED_MASK << IW_CUSTOM_READC_LSB) 
+#define GET_IW_CUSTOM_READC(W) (((W) >> IW_CUSTOM_READC_LSB) & IW_CUSTOM_READC_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_READC(V) (((V) & IW_CUSTOM_READC_UNSHIFTED_MASK) << IW_CUSTOM_READC_LSB) 
+
+#define IW_CUSTOM_N_LSB 6 
+#define IW_CUSTOM_N_SIZE 8 
+#define IW_CUSTOM_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_N_SIZE)) 
+#define IW_CUSTOM_N_SHIFTED_MASK (IW_CUSTOM_N_UNSHIFTED_MASK << IW_CUSTOM_N_LSB) 
+#define GET_IW_CUSTOM_N(W) (((W) >> IW_CUSTOM_N_LSB) & IW_CUSTOM_N_UNSHIFTED_MASK) 
+#define SET_IW_CUSTOM_N(V) (((V) & IW_CUSTOM_N_UNSHIFTED_MASK) << IW_CUSTOM_N_LSB) 
+
+/* R1 opcodes.  */
+#define R1_OP_CALL 0
+#define R1_OP_JMPI 1
+#define R1_OP_LDBU 3
+#define R1_OP_ADDI 4
+#define R1_OP_STB 5
+#define R1_OP_BR 6
+#define R1_OP_LDB 7
+#define R1_OP_CMPGEI 8
+#define R1_OP_LDHU 11
+#define R1_OP_ANDI 12
+#define R1_OP_STH 13
+#define R1_OP_BGE 14
+#define R1_OP_LDH 15
+#define R1_OP_CMPLTI 16
+#define R1_OP_INITDA 19
+#define R1_OP_ORI 20
+#define R1_OP_STW 21
+#define R1_OP_BLT 22
+#define R1_OP_LDW 23
+#define R1_OP_CMPNEI 24
+#define R1_OP_FLUSHDA 27
+#define R1_OP_XORI 28
+#define R1_OP_BNE 30
+#define R1_OP_CMPEQI 32
+#define R1_OP_LDBUIO 35
+#define R1_OP_MULI 36
+#define R1_OP_STBIO 37
+#define R1_OP_BEQ 38
+#define R1_OP_LDBIO 39
+#define R1_OP_CMPGEUI 40
+#define R1_OP_LDHUIO 43
+#define R1_OP_ANDHI 44
+#define R1_OP_STHIO 45
+#define R1_OP_BGEU 46
+#define R1_OP_LDHIO 47
+#define R1_OP_CMPLTUI 48
+#define R1_OP_CUSTOM 50
+#define R1_OP_INITD 51
+#define R1_OP_ORHI 52
+#define R1_OP_STWIO 53
+#define R1_OP_BLTU 54
+#define R1_OP_LDWIO 55
+#define R1_OP_RDPRS 56
+#define R1_OP_OPX 58
+#define R1_OP_FLUSHD 59
+#define R1_OP_XORHI 60
+
+#define R1_OPX_ERET 1
+#define R1_OPX_ROLI 2
+#define R1_OPX_ROL 3
+#define R1_OPX_FLUSHP 4
+#define R1_OPX_RET 5
+#define R1_OPX_NOR 6
+#define R1_OPX_MULXUU 7
+#define R1_OPX_CMPGE 8
+#define R1_OPX_BRET 9
+#define R1_OPX_ROR 11
+#define R1_OPX_FLUSHI 12
+#define R1_OPX_JMP 13
+#define R1_OPX_AND 14
+#define R1_OPX_CMPLT 16
+#define R1_OPX_SLLI 18
+#define R1_OPX_SLL 19
+#define R1_OPX_WRPRS 20
+#define R1_OPX_OR 22
+#define R1_OPX_MULXSU 23
+#define R1_OPX_CMPNE 24
+#define R1_OPX_SRLI 26
+#define R1_OPX_SRL 27
+#define R1_OPX_NEXTPC 28
+#define R1_OPX_CALLR 29
+#define R1_OPX_XOR 30
+#define R1_OPX_MULXSS 31
+#define R1_OPX_CMPEQ 32
+#define R1_OPX_DIVU 36
+#define R1_OPX_DIV 37
+#define R1_OPX_RDCTL 38
+#define R1_OPX_MUL 39
+#define R1_OPX_CMPGEU 40
+#define R1_OPX_INITI 41
+#define R1_OPX_TRAP 45
+#define R1_OPX_WRCTL 46
+#define R1_OPX_CMPLTU 48
+#define R1_OPX_ADD 49
+#define R1_OPX_BREAK 52
+#define R1_OPX_SYNC 54
+#define R1_OPX_SUB 57
+#define R1_OPX_SRAI 58
+#define R1_OPX_SRA 59
+
+/* Some convenience macros for R1 encodings, for use in instruction tables.
+   MATCH_R1_OPX0(NAME) and MASK_R1_OPX0 are used for R-type instructions
+   with 3 register operands and constant 0 in the immediate field.
+   The general forms are MATCH_R1_OPX(NAME, A, B, C) where the arguments specify
+   constant values and MASK_R1_OPX(A, B, C, N) where the arguments are booleans
+   that are true if the field should be included in the mask.
+ */
+#define MATCH_R1_OP(NAME) \
+  (SET_IW_R1_OP (R1_OP_##NAME))
+#define MASK_R1_OP \
+  IW_R1_OP_SHIFTED_MASK
+
+#define MATCH_R1_OPX0(NAME) \
+  (SET_IW_R1_OP (R1_OP_OPX) | SET_IW_R_OPX (R1_OPX_##NAME))
+#define MASK_R1_OPX0 \
+  (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK | IW_R_IMM5_SHIFTED_MASK)
+
+#define MATCH_R1_OPX(NAME, A, B, C)				\
+  (MATCH_R1_OPX0 (NAME) | SET_IW_R_A (A) | SET_IW_R_B (B) | SET_IW_R_C (C))
+#define MASK_R1_OPX(A, B, C, N)				\
+  (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK	\
+   | (A ? IW_R_A_SHIFTED_MASK : 0)			\
+   | (B ? IW_R_B_SHIFTED_MASK : 0)			\
+   | (C ? IW_R_C_SHIFTED_MASK : 0)			\
+   | (N ? IW_R_IMM5_SHIFTED_MASK : 0))
+
+/* And here's the match/mask macros for the R1 instruction set.  */
+#define MATCH_R1_ADD	MATCH_R1_OPX0 (ADD)
+#define MASK_R1_ADD	MASK_R1_OPX0
+#define MATCH_R1_ADDI	MATCH_R1_OP (ADDI)
+#define MASK_R1_ADDI	MASK_R1_OP
+#define MATCH_R1_AND	MATCH_R1_OPX0 (AND)
+#define MASK_R1_AND	MASK_R1_OPX0
+#define MATCH_R1_ANDHI	MATCH_R1_OP (ANDHI)
+#define MASK_R1_ANDHI	MASK_R1_OP
+#define MATCH_R1_ANDI	MATCH_R1_OP (ANDI)
+#define MASK_R1_ANDI	MASK_R1_OP
+#define MATCH_R1_BEQ	MATCH_R1_OP (BEQ)
+#define MASK_R1_BEQ	MASK_R1_OP
+#define MATCH_R1_BGE	MATCH_R1_OP (BGE)
+#define MASK_R1_BGE	MASK_R1_OP
+#define MATCH_R1_BGEU	MATCH_R1_OP (BGEU)
+#define MASK_R1_BGEU	MASK_R1_OP
+#define MATCH_R1_BGT	MATCH_R1_OP (BLT)
+#define MASK_R1_BGT	MASK_R1_OP
+#define MATCH_R1_BGTU	MATCH_R1_OP (BLTU)
+#define MASK_R1_BGTU	MASK_R1_OP
+#define MATCH_R1_BLE	MATCH_R1_OP (BGE)
+#define MASK_R1_BLE	MASK_R1_OP
+#define MATCH_R1_BLEU	MATCH_R1_OP (BGEU)
+#define MASK_R1_BLEU	MASK_R1_OP
+#define MATCH_R1_BLT	MATCH_R1_OP (BLT)
+#define MASK_R1_BLT	MASK_R1_OP
+#define MATCH_R1_BLTU	MATCH_R1_OP (BLTU)
+#define MASK_R1_BLTU	MASK_R1_OP
+#define MATCH_R1_BNE	MATCH_R1_OP (BNE)
+#define MASK_R1_BNE	MASK_R1_OP
+#define MATCH_R1_BR	MATCH_R1_OP (BR)
+#define MASK_R1_BR	MASK_R1_OP | IW_I_A_SHIFTED_MASK | IW_I_B_SHIFTED_MASK
+#define MATCH_R1_BREAK	MATCH_R1_OPX (BREAK, 0, 0, 0x1e)
+#define MASK_R1_BREAK	MASK_R1_OPX (1, 1, 1, 0)
+#define MATCH_R1_BRET	MATCH_R1_OPX (BRET, 0x1e, 0, 0)
+#define MASK_R1_BRET	MASK_R1_OPX (1, 1, 1, 1)
+#define MATCH_R1_CALL	MATCH_R1_OP (CALL)
+#define MASK_R1_CALL	MASK_R1_OP
+#define MATCH_R1_CALLR	MATCH_R1_OPX (CALLR, 0, 0, 0x1f)
+#define MASK_R1_CALLR	MASK_R1_OPX (0, 1, 1, 1)
+#define MATCH_R1_CMPEQ	MATCH_R1_OPX0 (CMPEQ)
+#define MASK_R1_CMPEQ	MASK_R1_OPX0
+#define MATCH_R1_CMPEQI	MATCH_R1_OP (CMPEQI)
+#define MASK_R1_CMPEQI	MASK_R1_OP
+#define MATCH_R1_CMPGE	MATCH_R1_OPX0 (CMPGE)
+#define MASK_R1_CMPGE	MASK_R1_OPX0
+#define MATCH_R1_CMPGEI	MATCH_R1_OP (CMPGEI)
+#define MASK_R1_CMPGEI	MASK_R1_OP
+#define MATCH_R1_CMPGEU	MATCH_R1_OPX0 (CMPGEU)
+#define MASK_R1_CMPGEU	MASK_R1_OPX0
+#define MATCH_R1_CMPGEUI	MATCH_R1_OP (CMPGEUI)
+#define MASK_R1_CMPGEUI	MASK_R1_OP
+#define MATCH_R1_CMPGT	MATCH_R1_OPX0 (CMPLT)
+#define MASK_R1_CMPGT	MASK_R1_OPX0
+#define MATCH_R1_CMPGTI	MATCH_R1_OP (CMPGEI)
+#define MASK_R1_CMPGTI	MASK_R1_OP
+#define MATCH_R1_CMPGTU	MATCH_R1_OPX0 (CMPLTU)
+#define MASK_R1_CMPGTU	MASK_R1_OPX0
+#define MATCH_R1_CMPGTUI	MATCH_R1_OP (CMPGEUI)
+#define MASK_R1_CMPGTUI	MASK_R1_OP
+#define MATCH_R1_CMPLE	MATCH_R1_OPX0 (CMPGE)
+#define MASK_R1_CMPLE	MASK_R1_OPX0
+#define MATCH_R1_CMPLEI	MATCH_R1_OP (CMPLTI)
+#define MASK_R1_CMPLEI	MASK_R1_OP
+#define MATCH_R1_CMPLEU	MATCH_R1_OPX0 (CMPGEU)
+#define MASK_R1_CMPLEU	MASK_R1_OPX0
+#define MATCH_R1_CMPLEUI	MATCH_R1_OP (CMPLTUI)
+#define MASK_R1_CMPLEUI	MASK_R1_OP
+#define MATCH_R1_CMPLT	MATCH_R1_OPX0 (CMPLT)
+#define MASK_R1_CMPLT	MASK_R1_OPX0
+#define MATCH_R1_CMPLTI	MATCH_R1_OP (CMPLTI)
+#define MASK_R1_CMPLTI	MASK_R1_OP
+#define MATCH_R1_CMPLTU	MATCH_R1_OPX0 (CMPLTU)
+#define MASK_R1_CMPLTU	MASK_R1_OPX0
+#define MATCH_R1_CMPLTUI	MATCH_R1_OP (CMPLTUI)
+#define MASK_R1_CMPLTUI	MASK_R1_OP
+#define MATCH_R1_CMPNE	MATCH_R1_OPX0 (CMPNE)
+#define MASK_R1_CMPNE	MASK_R1_OPX0
+#define MATCH_R1_CMPNEI	MATCH_R1_OP (CMPNEI)
+#define MASK_R1_CMPNEI	MASK_R1_OP
+#define MATCH_R1_CUSTOM	MATCH_R1_OP (CUSTOM)
+#define MASK_R1_CUSTOM	MASK_R1_OP
+#define MATCH_R1_DIV	MATCH_R1_OPX0 (DIV)
+#define MASK_R1_DIV	MASK_R1_OPX0
+#define MATCH_R1_DIVU	MATCH_R1_OPX0 (DIVU)
+#define MASK_R1_DIVU	MASK_R1_OPX0
+#define MATCH_R1_ERET	MATCH_R1_OPX (ERET, 0x1d, 0x1e, 0)
+#define MASK_R1_ERET	MASK_R1_OPX (1, 1, 1, 1)
+#define MATCH_R1_FLUSHD	MATCH_R1_OP (FLUSHD) | SET_IW_I_B (0)
+#define MASK_R1_FLUSHD	MASK_R1_OP | IW_I_B_SHIFTED_MASK
+#define MATCH_R1_FLUSHDA	MATCH_R1_OP (FLUSHDA) | SET_IW_I_B (0)
+#define MASK_R1_FLUSHDA	MASK_R1_OP | IW_I_B_SHIFTED_MASK
+#define MATCH_R1_FLUSHI	MATCH_R1_OPX (FLUSHI, 0, 0, 0)
+#define MASK_R1_FLUSHI	MASK_R1_OPX (0, 1, 1, 1)
+#define MATCH_R1_FLUSHP	MATCH_R1_OPX (FLUSHP, 0, 0, 0)
+#define MASK_R1_FLUSHP	MASK_R1_OPX (1, 1, 1, 1)
+#define MATCH_R1_INITD	MATCH_R1_OP (INITD) | SET_IW_I_B (0)
+#define MASK_R1_INITD	MASK_R1_OP | IW_I_B_SHIFTED_MASK
+#define MATCH_R1_INITDA	MATCH_R1_OP (INITDA) | SET_IW_I_B (0)
+#define MASK_R1_INITDA	MASK_R1_OP | IW_I_B_SHIFTED_MASK
+#define MATCH_R1_INITI	MATCH_R1_OPX (INITI, 0, 0, 0)
+#define MASK_R1_INITI	MASK_R1_OPX (0, 1, 1, 1)
+#define MATCH_R1_JMP	MATCH_R1_OPX (JMP, 0, 0, 0)
+#define MASK_R1_JMP	MASK_R1_OPX (0, 1, 1, 1)
+#define MATCH_R1_JMPI	MATCH_R1_OP (JMPI)
+#define MASK_R1_JMPI	MASK_R1_OP
+#define MATCH_R1_LDB	MATCH_R1_OP (LDB)
+#define MASK_R1_LDB	MASK_R1_OP
+#define MATCH_R1_LDBIO	MATCH_R1_OP (LDBIO)
+#define MASK_R1_LDBIO	MASK_R1_OP
+#define MATCH_R1_LDBU	MATCH_R1_OP (LDBU)
+#define MASK_R1_LDBU	MASK_R1_OP
+#define MATCH_R1_LDBUIO	MATCH_R1_OP (LDBUIO)
+#define MASK_R1_LDBUIO	MASK_R1_OP
+#define MATCH_R1_LDH	MATCH_R1_OP (LDH)
+#define MASK_R1_LDH	MASK_R1_OP
+#define MATCH_R1_LDHIO	MATCH_R1_OP (LDHIO)
+#define MASK_R1_LDHIO	MASK_R1_OP
+#define MATCH_R1_LDHU	MATCH_R1_OP (LDHU)
+#define MASK_R1_LDHU	MASK_R1_OP
+#define MATCH_R1_LDHUIO	MATCH_R1_OP (LDHUIO)
+#define MASK_R1_LDHUIO	MASK_R1_OP
+#define MATCH_R1_LDW	MATCH_R1_OP (LDW)
+#define MASK_R1_LDW	MASK_R1_OP
+#define MATCH_R1_LDWIO	MATCH_R1_OP (LDWIO)
+#define MASK_R1_LDWIO	MASK_R1_OP
+#define MATCH_R1_MOV	MATCH_R1_OPX (ADD, 0, 0, 0)
+#define MASK_R1_MOV	MASK_R1_OPX (0, 1, 0, 1)
+#define MATCH_R1_MOVHI	MATCH_R1_OP (ORHI) | SET_IW_I_A (0)
+#define MASK_R1_MOVHI	MASK_R1_OP | IW_I_A_SHIFTED_MASK
+#define MATCH_R1_MOVI	MATCH_R1_OP (ADDI) | SET_IW_I_A (0)
+#define MASK_R1_MOVI	MASK_R1_OP | IW_I_A_SHIFTED_MASK
+#define MATCH_R1_MOVUI	MATCH_R1_OP (ORI) | SET_IW_I_A (0)
+#define MASK_R1_MOVUI	MASK_R1_OP | IW_I_A_SHIFTED_MASK
+#define MATCH_R1_MUL	MATCH_R1_OPX0 (MUL)
+#define MASK_R1_MUL	MASK_R1_OPX0
+#define MATCH_R1_MULI	MATCH_R1_OP (MULI)
+#define MASK_R1_MULI	MASK_R1_OP
+#define MATCH_R1_MULXSS	MATCH_R1_OPX0 (MULXSS)
+#define MASK_R1_MULXSS	MASK_R1_OPX0
+#define MATCH_R1_MULXSU	MATCH_R1_OPX0 (MULXSU)
+#define MASK_R1_MULXSU	MASK_R1_OPX0
+#define MATCH_R1_MULXUU	MATCH_R1_OPX0 (MULXUU)
+#define MASK_R1_MULXUU	MASK_R1_OPX0
+#define MATCH_R1_NEXTPC	MATCH_R1_OPX (NEXTPC, 0, 0, 0)
+#define MASK_R1_NEXTPC	MASK_R1_OPX (1, 1, 0, 1)
+#define MATCH_R1_NOP	MATCH_R1_OPX (ADD, 0, 0, 0)
+#define MASK_R1_NOP	MASK_R1_OPX (1, 1, 1, 1)
+#define MATCH_R1_NOR	MATCH_R1_OPX0 (NOR)
+#define MASK_R1_NOR	MASK_R1_OPX0
+#define MATCH_R1_OR	MATCH_R1_OPX0 (OR)
+#define MASK_R1_OR	MASK_R1_OPX0
+#define MATCH_R1_ORHI	MATCH_R1_OP (ORHI)
+#define MASK_R1_ORHI	MASK_R1_OP
+#define MATCH_R1_ORI	MATCH_R1_OP (ORI)
+#define MASK_R1_ORI	MASK_R1_OP
+#define MATCH_R1_RDCTL	MATCH_R1_OPX (RDCTL, 0, 0, 0)
+#define MASK_R1_RDCTL	MASK_R1_OPX (1, 1, 0, 0)
+#define MATCH_R1_RDPRS	MATCH_R1_OP (RDPRS)
+#define MASK_R1_RDPRS	MASK_R1_OP
+#define MATCH_R1_RET	MATCH_R1_OPX (RET, 0x1f, 0, 0)
+#define MASK_R1_RET	MASK_R1_OPX (1, 1, 1, 1)
+#define MATCH_R1_ROL	MATCH_R1_OPX0 (ROL)
+#define MASK_R1_ROL	MASK_R1_OPX0
+#define MATCH_R1_ROLI	MATCH_R1_OPX (ROLI, 0, 0, 0)
+#define MASK_R1_ROLI	MASK_R1_OPX (0, 1, 0, 0)
+#define MATCH_R1_ROR	MATCH_R1_OPX0 (ROR)
+#define MASK_R1_ROR	MASK_R1_OPX0
+#define MATCH_R1_SLL	MATCH_R1_OPX0 (SLL)
+#define MASK_R1_SLL	MASK_R1_OPX0
+#define MATCH_R1_SLLI	MATCH_R1_OPX (SLLI, 0, 0, 0)
+#define MASK_R1_SLLI	MASK_R1_OPX (0, 1, 0, 0)
+#define MATCH_R1_SRA	MATCH_R1_OPX0 (SRA)
+#define MASK_R1_SRA	MASK_R1_OPX0
+#define MATCH_R1_SRAI	MATCH_R1_OPX (SRAI, 0, 0, 0)
+#define MASK_R1_SRAI	MASK_R1_OPX (0, 1, 0, 0)
+#define MATCH_R1_SRL	MATCH_R1_OPX0 (SRL)
+#define MASK_R1_SRL	MASK_R1_OPX0
+#define MATCH_R1_SRLI	MATCH_R1_OPX (SRLI, 0, 0, 0)
+#define MASK_R1_SRLI	MASK_R1_OPX (0, 1, 0, 0)
+#define MATCH_R1_STB	MATCH_R1_OP (STB)
+#define MASK_R1_STB	MASK_R1_OP
+#define MATCH_R1_STBIO	MATCH_R1_OP (STBIO)
+#define MASK_R1_STBIO	MASK_R1_OP
+#define MATCH_R1_STH	MATCH_R1_OP (STH)
+#define MASK_R1_STH	MASK_R1_OP
+#define MATCH_R1_STHIO	MATCH_R1_OP (STHIO)
+#define MASK_R1_STHIO	MASK_R1_OP
+#define MATCH_R1_STW	MATCH_R1_OP (STW)
+#define MASK_R1_STW	MASK_R1_OP
+#define MATCH_R1_STWIO	MATCH_R1_OP (STWIO)
+#define MASK_R1_STWIO	MASK_R1_OP
+#define MATCH_R1_SUB	MATCH_R1_OPX0 (SUB)
+#define MASK_R1_SUB	MASK_R1_OPX0
+#define MATCH_R1_SUBI	MATCH_R1_OP (ADDI)
+#define MASK_R1_SUBI	MASK_R1_OP
+#define MATCH_R1_SYNC	MATCH_R1_OPX (SYNC, 0, 0, 0)
+#define MASK_R1_SYNC	MASK_R1_OPX (1, 1, 1, 1)
+#define MATCH_R1_TRAP	MATCH_R1_OPX (TRAP, 0, 0, 0x1d)
+#define MASK_R1_TRAP	MASK_R1_OPX (1, 1, 1, 0)
+#define MATCH_R1_WRCTL	MATCH_R1_OPX (WRCTL, 0, 0, 0)
+#define MASK_R1_WRCTL	MASK_R1_OPX (0, 1, 1, 0)
+#define MATCH_R1_WRPRS	MATCH_R1_OPX (WRPRS, 0, 0, 0)
+#define MASK_R1_WRPRS	MASK_R1_OPX (0, 1, 0, 1)
+#define MATCH_R1_XOR	MATCH_R1_OPX0 (XOR)
+#define MASK_R1_XOR	MASK_R1_OPX0
+#define MATCH_R1_XORHI	MATCH_R1_OP (XORHI)
+#define MASK_R1_XORHI	MASK_R1_OP
+#define MATCH_R1_XORI	MATCH_R1_OP (XORI)
+#define MASK_R1_XORI	MASK_R1_OP
+
+#endif /* _NIOS2R1_H */
diff --git a/binutils-2.25/include/opcode/sparc.h b/binutils-2.25/include/opcode/sparc.h
index cf4ff1c6..463b9c18 100644
--- a/binutils-2.25/include/opcode/sparc.h
+++ b/binutils-2.25/include/opcode/sparc.h
@@ -151,7 +151,7 @@ typedef struct sparc_opcode
 #define HWCAP_CRC32C	0x20000000 /* CRC32C insn */
 
 #define HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
-#define HWCAP2_VIS3B     0x00000002 /* VIS3 present on multiple chips */
+#define HWCAP2_VIS3B     0x00000002 /* Subset of VIS3 present on sparc64 X+.  */
 #define HWCAP2_ADP       0x00000004 /* Application Data Protection */
 #define HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
 #define HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */