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author | Andrew Hsieh <andrewhsieh@google.com> | 2014-12-09 17:57:18 +0800 |
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committer | Andrew Hsieh <andrewhsieh@google.com> | 2014-12-09 19:50:14 +0800 |
commit | 5e8c1cf25beccac1d22d10dc866912394f42771b (patch) | |
tree | ee16b70f804484dc8e434e647e699ab50da2620f /binutils-2.25/gas/testsuite/gas/arm/thumb2_vpool.s | |
parent | 8eebd7953384e6662ca926b003f2cdda8ccd3ee5 (diff) | |
download | toolchain_binutils-5e8c1cf25beccac1d22d10dc866912394f42771b.tar.gz toolchain_binutils-5e8c1cf25beccac1d22d10dc866912394f42771b.tar.bz2 toolchain_binutils-5e8c1cf25beccac1d22d10dc866912394f42771b.zip |
[2.25] sync to a30720e3e633f275250e26f85ccae5dbdddfb6c6
local patches will be re-applied later
commit a30720e3e633f275250e26f85ccae5dbdddfb6c6
Author: Alan Modra <amodra@gmail.com>
Date: Wed Nov 19 10:30:16 2014 +1030
daily update
Change-Id: Ieb2a3f4dd2ecb289ac5305ff08d428b2847494ab
Diffstat (limited to 'binutils-2.25/gas/testsuite/gas/arm/thumb2_vpool.s')
-rw-r--r-- | binutils-2.25/gas/testsuite/gas/arm/thumb2_vpool.s | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/binutils-2.25/gas/testsuite/gas/arm/thumb2_vpool.s b/binutils-2.25/gas/testsuite/gas/arm/thumb2_vpool.s new file mode 100644 index 00000000..efbbc77e --- /dev/null +++ b/binutils-2.25/gas/testsuite/gas/arm/thumb2_vpool.s @@ -0,0 +1,95 @@ + .text + .fpu neon + .thumb + .syntax unified + .thumb_func +thumb2_ldr: + .macro vlxr regtype const + .irp regindex, 0, 14, 28, 31 + vldr \regtype\regindex, \const + .endr + .endm + # Thumb-2 support vldr literal pool also. + vlxr s "=0" + vlxr s "=0xff000000" + vlxr s "=-1" + vlxr s "=0x0fff0000" + .pool + + vlxr s "=0" + vlxr s "=0x00ff0000" + vlxr s "=0xff00ffff" + vlxr s "=0x00fff000" + .pool + + vlxr d "=0" + vlxr d "=0xca000000" + vlxr d "=-1" + vlxr d "=0x0fff0000" + .pool + + vlxr d "=0" + vlxr d "=0x00ff0000" + vlxr d "=0xff0000ff" + vlxr d "=0x00fff000" + .pool + + vlxr d "=0" + vlxr d "=0xff00000000000000" + vlxr d "=-1" + vlxr d "=0x0fff000000000000" + .pool + + vlxr d "=0" + vlxr d "=0x00ff00000000000" + vlxr d "=0xff00ffff0000000" + vlxr d "=0xff00ffff0000000" + .pool + + # pool should be aligned to 8-byte. + .p2align 3 + vldr d1, =0x0000fff000000000 + .pool + + # no error when code is align already. + .p2align 3 + add r0, r1, #0 + vldr d1, =0x0000fff000000000 + .pool + + .p2align 3 + vldr d1, =0x0000fff000000000 + vldr s2, =0xff000000 + # padding A + vldr d3, =0x0000fff000000001 + # reuse padding slot A + vldr s4, =0xff000001 + # reuse d3 + vldr d5, =0x0000fff000000001 + # new 8-byte entry + vldr d6, =0x0000fff000000002 + # new 8-byte entry + vldr d7, =0x0000fff000000003 + # new 4-byte entry + vldr s8, =0xff000002 + # padding B + vldr d9, =0x0000fff000000004 + # reuse padding slot B + vldr s10, =0xff000003 + # new 8-byte entry + vldr d11, =0x0000fff000000005 + # new 4 entry + vldr s12, =0xff000004 + # new 4 entry + vldr s13, =0xff000005 + # reuse value of s4 in pool + vldr s14, =0xff000001 + # reuse high part of d1 in pool + vldr s15, =0x0000fff0 + # 8-byte entry reuse two 4-byte entries. + # d16 reuse s12, s13 + vldr d16, =0xff000005ff000004 + # d17 should not reuse high part of d11 and s12. + # because the it's align 8-byte aligned. + vldr d17, =0xff0000040000fff0 + .pool |