diff options
author | Jing Yu <jingyu@google.com> | 2009-11-05 16:55:30 -0800 |
---|---|---|
committer | Jing Yu <jingyu@google.com> | 2009-11-05 16:55:30 -0800 |
commit | 2cafa61b4b039e5ac3b876fc44a05c61d66df4d4 (patch) | |
tree | 1caaaacd28e00e283dbacd6726db52cbf2d5d909 /binutils-2.17/gas/testsuite/gas/arc/st.d | |
parent | 8d401cf711539af5a2f78d12447341d774892618 (diff) | |
download | toolchain_binutils-2cafa61b4b039e5ac3b876fc44a05c61d66df4d4.tar.gz toolchain_binutils-2cafa61b4b039e5ac3b876fc44a05c61d66df4d4.tar.bz2 toolchain_binutils-2cafa61b4b039e5ac3b876fc44a05c61d66df4d4.zip |
check in binutils sources for prebuilt toolchains in Eclair.
Diffstat (limited to 'binutils-2.17/gas/testsuite/gas/arc/st.d')
-rw-r--r-- | binutils-2.17/gas/testsuite/gas/arc/st.d | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/binutils-2.17/gas/testsuite/gas/arc/st.d b/binutils-2.17/gas/testsuite/gas/arc/st.d new file mode 100644 index 00000000..813f1aa3 --- /dev/null +++ b/binutils-2.17/gas/testsuite/gas/arc/st.d @@ -0,0 +1,42 @@ +#as: -EL +#objdump: -dr -EL + +.*: +file format elf32-.*arc + +Disassembly of section .text: + +00000000 <.text>: + 0: 00 02 01 10 10010200 st r1,\[r2\] + 4: 0e 02 01 10 1001020e st r1,\[r2,14\] + 8: 00 02 41 10 10410200 stb r1,\[r2\] + c: 0e 82 01 11 1101820e st.a r1,\[r3,14\] + 10: 02 02 81 11 11810202 stw.a r1,\[r2,2\] + 14: 00 02 1f 10 101f0200 st r1,\[0x384\] + 18: 84 03 00 00 + 1c: 00 7e 41 10 10417e00 stb 0,\[r2\] + 20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\] + 24: 50 7e 1f 10 101f7e50 st 80,\[0x2ee\] + 28: 9e 02 00 00 + 2c: 00 04 1f 10 101f0400 st r2,\[0\] + 30: 00 00 00 00 + 30: R_ARC_32 foo + 34: 02 02 01 14 14010202 st.di r1,\[r2,2\] + 38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\] + 3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\] + 40: 04 7c 06 10 10067c04 st 80,\[r12,4\] + 44: 50 00 00 00 + 44: R_ARC_32 .text + 48: 04 7c 06 10 10067c04 st 20,\[r12,4\] + 4c: 14 00 00 00 + 4c: R_ARC_B26 .text + 50: 00 02 01 12 12010200 sr r1,\[r2\] + 54: 0e 82 1f 12 121f820e sr r1,\[0xe\] + 58: 00 fc 00 12 1200fc00 sr 0x3e8,\[r1\] + 5c: e8 03 00 00 + 60: 64 7e 01 12 12017e64 sr 100,\[r2\] + 64: 00 02 1f 12 121f0200 sr r1,\[0x2710\] + 68: 10 27 00 00 + 6c: 64 7e 1f 12 121f7e64 sr 100,\[0x2710\] + 70: 10 27 00 00 + 74: 64 fc 1f 12 121ffc64 sr 0x2710,\[0x64\] + 78: 10 27 00 00 |