aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/reg_srcs/r200
blob: c29ac434ac9c81ae10141613d6d994ce63324d23 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
r200 0x3294
0x1434 SRC_Y_X
0x1438 DST_Y_X
0x143C DST_HEIGHT_WIDTH
0x146C DP_GUI_MASTER_CNTL
0x1474 BRUSH_Y_X
0x1478 DP_BRUSH_BKGD_CLR
0x147C DP_BRUSH_FRGD_CLR
0x1480 BRUSH_DATA0
0x1484 BRUSH_DATA1
0x1598 DST_WIDTH_HEIGHT
0x15C0 CLR_CMP_CNTL
0x15C4 CLR_CMP_CLR_SRC
0x15C8 CLR_CMP_CLR_DST
0x15CC CLR_CMP_MSK
0x15D8 DP_SRC_FRGD_CLR
0x15DC DP_SRC_BKGD_CLR
0x1600 DST_LINE_START
0x1604 DST_LINE_END
0x1608 DST_LINE_PATCOUNT
0x16C0 DP_CNTL
0x16CC DP_WRITE_MSK
0x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
0x16E8 DEFAULT_SC_BOTTOM_RIGHT
0x16EC SC_TOP_LEFT
0x16F0 SC_BOTTOM_RIGHT
0x16F4 SRC_SC_BOTTOM_RIGHT
0x1714 DSTCACHE_CTLSTAT
0x1720 WAIT_UNTIL
0x172C RBBM_GUICNTL
0x1c14 PP_MISC
0x1c18 PP_FOG_COLOR
0x1c1c RE_SOLID_COLOR
0x1c20 RB3D_BLENDCNTL
0x1c4c SE_CNTL
0x1c50 RE_CNTL
0x1cc8 RE_STIPPLE_ADDR
0x1ccc RE_STIPPLE_DATA
0x1cd0 RE_LINE_PATTERN
0x1cd4 RE_LINE_STATE
0x1cd8 RE_SCISSOR_TL_0
0x1cdc RE_SCISSOR_BR_0
0x1ce0 RE_SCISSOR_TL_1
0x1ce4 RE_SCISSOR_BR_1
0x1ce8 RE_SCISSOR_TL_2
0x1cec RE_SCISSOR_BR_2
0x1d60 RB3D_DEPTHXY_OFFSET
0x1d7c RB3D_STENCILREFMASK
0x1d80 RB3D_ROPCNTL
0x1d84 RB3D_PLANEMASK
0x1d98 VAP_VPORT_XSCALE
0x1d9c VAP_VPORT_XOFFSET
0x1da0 VAP_VPORT_YSCALE
0x1da4 VAP_VPORT_YOFFSET
0x1da8 VAP_VPORT_ZSCALE
0x1dac VAP_VPORT_ZOFFSET
0x1db0 SE_ZBIAS_FACTOR
0x1db4 SE_ZBIAS_CONSTANT
0x1db8 SE_LINE_WIDTH
0x2080 SE_VAP_CNTL
0x2090 SE_TCL_OUTPUT_VTX_FMT_0
0x2094 SE_TCL_OUTPUT_VTX_FMT_1
0x20b0 SE_VTE_CNTL
0x2140 SE_CNTL_STATUS
0x2180 SE_VTX_STATE_CNTL
0x2200 SE_TCL_VECTOR_INDX_REG
0x2204 SE_TCL_VECTOR_DATA_REG
0x2208 SE_TCL_SCALAR_INDX_REG
0x220c SE_TCL_SCALAR_DATA_REG
0x2230 SE_TCL_MATRIX_SEL_0
0x2234 SE_TCL_MATRIX_SEL_1
0x2238 SE_TCL_MATRIX_SEL_2
0x223c SE_TCL_MATRIX_SEL_3
0x2240 SE_TCL_MATRIX_SEL_4
0x2250 SE_TCL_OUTPUT_VTX_COMP_SEL
0x2254 SE_TCL_INPUT_VTX_VECTOR_ADDR_0
0x2258 SE_TCL_INPUT_VTX_VECTOR_ADDR_1
0x225c SE_TCL_INPUT_VTX_VECTOR_ADDR_2
0x2260 SE_TCL_INPUT_VTX_VECTOR_ADDR_3
0x2268 SE_TCL_LIGHT_MODEL_CTL_0
0x226c SE_TCL_LIGHT_MODEL_CTL_1
0x2270 SE_TCL_PER_LIGHT_CTL_0
0x2274 SE_TCL_PER_LIGHT_CTL_1
0x2278 SE_TCL_PER_LIGHT_CTL_2
0x227c SE_TCL_PER_LIGHT_CTL_3
0x2284 VAP_PVS_STATE_FLUSH_REG
0x22a8 SE_TCL_TEX_PROC_CTL_2
0x22ac SE_TCL_TEX_PROC_CTL_3
0x22b0 SE_TCL_TEX_PROC_CTL_0
0x22b4 SE_TCL_TEX_PROC_CTL_1
0x22b8 SE_TCL_TEX_CYL_WRAP_CTL
0x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
0x22c4 SE_TCL_POINT_SPRITE_CNTL
0x22d0 SE_PVS_CNTL
0x22d4 SE_PVS_CONST_CNTL
0x2648 RE_POINTSIZE
0x26c0 RE_TOP_LEFT
0x26c4 RE_MISC
0x26f0 RE_AUX_SCISSOR_CNTL
0x2c14 PP_BORDER_COLOR_0
0x2c34 PP_BORDER_COLOR_1
0x2c54 PP_BORDER_COLOR_2
0x2c74 PP_BORDER_COLOR_3
0x2c94 PP_BORDER_COLOR_4
0x2cb4 PP_BORDER_COLOR_5
0x2cc4 PP_CNTL_X
0x2cf8 PP_TRI_PERF
0x2cfc PP_PERF_CNTL
0x2d9c PP_TAM_DEBUG3
0x2ee0 PP_TFACTOR_0
0x2ee4 PP_TFACTOR_1
0x2ee8 PP_TFACTOR_2
0x2eec PP_TFACTOR_3
0x2ef0 PP_TFACTOR_4
0x2ef4 PP_TFACTOR_5
0x2ef8 PP_TFACTOR_6
0x2efc PP_TFACTOR_7
0x2f00 PP_TXCBLEND_0
0x2f04 PP_TXCBLEND2_0
0x2f08 PP_TXABLEND_0
0x2f0c PP_TXABLEND2_0
0x2f10 PP_TXCBLEND_1
0x2f14 PP_TXCBLEND2_1
0x2f18 PP_TXABLEND_1
0x2f1c PP_TXABLEND2_1
0x2f20 PP_TXCBLEND_2
0x2f24 PP_TXCBLEND2_2
0x2f28 PP_TXABLEND_2
0x2f2c PP_TXABLEND2_2
0x2f30 PP_TXCBLEND_3
0x2f34 PP_TXCBLEND2_3
0x2f38 PP_TXABLEND_3
0x2f3c PP_TXABLEND2_3
0x2f40 PP_TXCBLEND_4
0x2f44 PP_TXCBLEND2_4
0x2f48 PP_TXABLEND_4
0x2f4c PP_TXABLEND2_4
0x2f50 PP_TXCBLEND_5
0x2f54 PP_TXCBLEND2_5
0x2f58 PP_TXABLEND_5
0x2f5c PP_TXABLEND2_5
0x2f60 PP_TXCBLEND_6
0x2f64 PP_TXCBLEND2_6
0x2f68 PP_TXABLEND_6
0x2f6c PP_TXABLEND2_6
0x2f70 PP_TXCBLEND_7
0x2f74 PP_TXCBLEND2_7
0x2f78 PP_TXABLEND_7
0x2f7c PP_TXABLEND2_7
0x2f80 PP_TXCBLEND_8
0x2f84 PP_TXCBLEND2_8
0x2f88 PP_TXABLEND_8
0x2f8c PP_TXABLEND2_8
0x2f90 PP_TXCBLEND_9
0x2f94 PP_TXCBLEND2_9
0x2f98 PP_TXABLEND_9
0x2f9c PP_TXABLEND2_9
0x2fa0 PP_TXCBLEND_10
0x2fa4 PP_TXCBLEND2_10
0x2fa8 PP_TXABLEND_10
0x2fac PP_TXABLEND2_10
0x2fb0 PP_TXCBLEND_11
0x2fb4 PP_TXCBLEND2_11
0x2fb8 PP_TXABLEND_11
0x2fbc PP_TXABLEND2_11
0x2fc0 PP_TXCBLEND_12
0x2fc4 PP_TXCBLEND2_12
0x2fc8 PP_TXABLEND_12
0x2fcc PP_TXABLEND2_12
0x2fd0 PP_TXCBLEND_13
0x2fd4 PP_TXCBLEND2_13
0x2fd8 PP_TXABLEND_13
0x2fdc PP_TXABLEND2_13
0x2fe0 PP_TXCBLEND_14
0x2fe4 PP_TXCBLEND2_14
0x2fe8 PP_TXABLEND_14
0x2fec PP_TXABLEND2_14
0x2ff0 PP_TXCBLEND_15
0x2ff4 PP_TXCBLEND2_15
0x2ff8 PP_TXABLEND_15
0x2ffc PP_TXABLEND2_15
0x3218 RB3D_BLENCOLOR
0x321c RB3D_ABLENDCNTL
0x3220 RB3D_CBLENDCNTL
0x3290 RB3D_ZPASS_DATA