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| author | Mike Turquette <mturquette@ti.com> | 2012-05-17 18:11:31 +0300 |
|---|---|---|
| committer | Dmytro Kedrovskyi <x0169235@ti.com> | 2012-06-18 22:19:14 +0300 |
| commit | 2ff36dce16113cb5857d11440492cb7e84018d08 (patch) | |
| tree | 8699790af546810d961bf2832135bc0e21e97806 | |
| parent | b789b578ccdd13b85cdb1b679ab1fce30b0bdfd8 (diff) | |
| download | kernel_samsung_espresso10-2ff36dce16113cb5857d11440492cb7e84018d08.tar.gz kernel_samsung_espresso10-2ff36dce16113cb5857d11440492cb7e84018d08.tar.bz2 kernel_samsung_espresso10-2ff36dce16113cb5857d11440492cb7e84018d08.zip | |
OMAP4: DPLL cascading: SR: handle SRCLKLENGTH
In DPLL cascading mode SYS_CLK is gated. This impacts many IP, including
the SmartReflex AVS modules. To compensate for loss of SYS_CLK the
SR_xxx_SYSCLK clocks derived from the PRM use the 32K timer as a clock
source. As such the SRCLKLENGTH value needs to be updated for this
change in frequency. In DPLL cascading the rate of this clock should be
12.288MHz.
This patch implements three distinct changes:
1) add a 12.288MHz option to the existing sr_set_clk_length function
and give it the ability to detect whether we are in DPLL cascading
mode or not.
2) Remove optimizations in sr_configure_errgen and sr_configure_minmax to
skip sr_set_clk_length re-calibration if the clk_length parameter exists.
The assumption was that this value would never change after initial
calibration at boot; that assumption fails in light of DPLL cascading
scenario.
[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]
Change-Id: Ie657459e53838067139a4dd7316a6adc1f5e7259
Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
| -rw-r--r-- | arch/arm/mach-omap2/smartreflex.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c index c2d85c14b5e..b8374d40e77 100644 --- a/arch/arm/mach-omap2/smartreflex.c +++ b/arch/arm/mach-omap2/smartreflex.c @@ -27,6 +27,10 @@ #include <plat/common.h> +#ifdef CONFIG_OMAP4_DPLL_CASCADING +#include <mach/omap4-common.h> +#endif + #include "pm.h" #include "dvfs.h" #include "smartreflex.h" @@ -256,10 +260,20 @@ static void sr_set_clk_length(struct omap_sr *sr) __func__); return; } - sys_clk_speed = clk_get_rate(sys_ck); +#ifdef CONFIG_OMAP4_DPLL_CASCADING + if (omap4_is_in_dpll_cascading()) + sys_clk_speed = 12288000; + else +#endif + sys_clk_speed = clk_get_rate(sys_ck); clk_put(sys_ck); switch (sys_clk_speed) { +#ifdef CONFIG_OMAP4_DPLL_CASCADING + case 12288000: + sr->clk_length = 0x3d; + break; +#endif case 12000000: sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK; break; @@ -558,7 +572,9 @@ int sr_configure_errgen(struct voltagedomain *voltdm) return -EINVAL; } +#ifndef CONFIG_OMAP4_DPLL_CASCADING if (!sr->clk_length) +#endif sr_set_clk_length(sr); senp_en = sr->senp_mod; @@ -671,7 +687,9 @@ int sr_configure_minmax(struct voltagedomain *voltdm) return -EINVAL; } +#ifndef CONFIG_OMAP4_DPLL_CASCADING if (!sr->clk_length) +#endif sr_set_clk_length(sr); senp_en = sr->senp_mod; |