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author | Tejun Heo <tj@kernel.org> | 2011-05-24 09:59:36 +0200 |
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committer | Tejun Heo <tj@kernel.org> | 2011-05-24 09:59:36 +0200 |
commit | 6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0 (patch) | |
tree | c9d7fc50a2e2147a5ca07e3096e7eeb916ad2da9 /arch/m32r/platforms/oaks32r/setup.c | |
parent | 0415b00d175e0d8945e6785aad21b5f157976ce0 (diff) | |
parent | 6ea0c34dac89611126455537552cffe6c7e832ad (diff) | |
download | kernel_samsung_crespo-6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0.tar.gz kernel_samsung_crespo-6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0.tar.bz2 kernel_samsung_crespo-6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0.zip |
Merge branch 'fixes-2.6.39' into for-2.6.40
Diffstat (limited to 'arch/m32r/platforms/oaks32r/setup.c')
-rw-r--r-- | arch/m32r/platforms/oaks32r/setup.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c index 19a02db7b81..83b46b067a1 100644 --- a/arch/m32r/platforms/oaks32r/setup.c +++ b/arch/m32r/platforms/oaks32r/setup.c @@ -74,39 +74,39 @@ void __init init_IRQ(void) #ifdef CONFIG_NE2000 /* INT3 : LAN controller (RTL8019AS) */ - set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; disable_oaks32r_irq(M32R_IRQ_INT3); #endif /* CONFIG_M32R_NE2000 */ /* MFT2 : system timer */ - set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; disable_oaks32r_irq(M32R_IRQ_MFT2); #ifdef CONFIG_SERIAL_M32R_SIO /* SIO0_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_R); /* SIO0_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO0_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO0_S); /* SIO1_R : uart receive data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_R].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_R); /* SIO1_S : uart send data */ - set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, + irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, handle_level_irq); icu_data[M32R_IRQ_SIO1_S].icucr = 0; disable_oaks32r_irq(M32R_IRQ_SIO1_S); |