diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 17 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.h | 11 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp | 4 |
5 files changed, 36 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 4df3f7e0c8..38e300068d 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -4749,7 +4749,9 @@ fs_visitor::assign_fs_binding_table_offsets() prog_data->binding_table.render_target_start = next_binding_table_offset; next_binding_table_offset += MAX2(key->nr_color_regions, 1); - assign_common_binding_table_offsets(next_binding_table_offset); + brw_assign_common_binding_table_offsets(MESA_SHADER_FRAGMENT, devinfo, + shader_prog, prog, stage_prog_data, + next_binding_table_offset); } void @@ -4763,7 +4765,9 @@ fs_visitor::assign_cs_binding_table_offsets() prog_data->binding_table.work_groups_start = next_binding_table_offset; next_binding_table_offset++; - assign_common_binding_table_offsets(next_binding_table_offset); + brw_assign_common_binding_table_offsets(MESA_SHADER_COMPUTE, devinfo, + shader_prog, prog, stage_prog_data, + next_binding_table_offset); } void @@ -4979,7 +4983,9 @@ fs_visitor::run_vs(gl_clip_plane *clip_planes) { assert(stage == MESA_SHADER_VERTEX); - assign_common_binding_table_offsets(0); + brw_assign_common_binding_table_offsets(MESA_SHADER_VERTEX, devinfo, + shader_prog, prog, stage_prog_data, + 0); setup_vs_payload(); if (shader_time_index >= 0) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index 58b9d66fe5..1f335a39fe 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -1352,16 +1352,25 @@ backend_shader::invalidate_cfg() * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES. */ void -backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset) +brw_assign_common_binding_table_offsets(gl_shader_stage stage, + const struct brw_device_info *devinfo, + const struct gl_shader_program *shader_prog, + const struct gl_program *prog, + struct brw_stage_prog_data *stage_prog_data, + uint32_t next_binding_table_offset) { + const struct gl_shader *shader = NULL; int num_textures = _mesa_fls(prog->SamplersUsed); + if (shader_prog) + shader = shader_prog->_LinkedShaders[stage]; + stage_prog_data->binding_table.texture_start = next_binding_table_offset; next_binding_table_offset += num_textures; if (shader) { stage_prog_data->binding_table.ubo_start = next_binding_table_offset; - next_binding_table_offset += shader->base.NumUniformBlocks; + next_binding_table_offset += shader->NumUniformBlocks; } else { stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0; } @@ -1392,9 +1401,9 @@ backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_ stage_prog_data->binding_table.abo_start = 0xd0d0d0d0; } - if (shader && shader->base.NumImages) { + if (shader && shader->NumImages) { stage_prog_data->binding_table.image_start = next_binding_table_offset; - next_binding_table_offset += shader->base.NumImages; + next_binding_table_offset += shader->NumImages; } else { stage_prog_data->binding_table.image_start = 0xd0d0d0d0; } diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index eeb3306dfc..96903321cd 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -24,6 +24,7 @@ #include <stdint.h> #include "brw_reg.h" #include "brw_defines.h" +#include "brw_context.h" #include "main/compiler.h" #include "glsl/ir.h" #include "program/prog_parameter.h" @@ -266,8 +267,6 @@ public: void calculate_cfg(); void invalidate_cfg(); - void assign_common_binding_table_offsets(uint32_t next_binding_table_offset); - virtual void invalidate_live_intervals() = 0; }; @@ -295,6 +294,14 @@ extern "C" { struct brw_compiler * brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo); +void +brw_assign_common_binding_table_offsets(gl_shader_stage stage, + const struct brw_device_info *devinfo, + const struct gl_shader_program *shader_prog, + const struct gl_program *prog, + struct brw_stage_prog_data *stage_prog_data, + uint32_t next_binding_table_offset); + bool brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *shader_prog, struct gl_program *prog); diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 6aaf764a67..d898405544 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1710,7 +1710,8 @@ vec4_vs_visitor::setup_payload(void) void vec4_visitor::assign_binding_table_offsets() { - assign_common_binding_table_offsets(0); + brw_assign_common_binding_table_offsets(stage, devinfo, shader_prog, prog, + stage_prog_data, 0); } src_reg diff --git a/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp b/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp index 6db6d276f7..52190076d2 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/gen6_gs_visitor.cpp @@ -41,7 +41,9 @@ gen6_gs_visitor::assign_binding_table_offsets() /* In gen6 we reserve the first BRW_MAX_SOL_BINDINGS entries for transform * feedback surfaces. */ - assign_common_binding_table_offsets(BRW_MAX_SOL_BINDINGS); + brw_assign_common_binding_table_offsets(MESA_SHADER_GEOMETRY, devinfo, + shader_prog, prog, stage_prog_data, + BRW_MAX_SOL_BINDINGS); } void |