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| author | Kristian Høgsberg <krh@bitplanet.net> | 2014-10-20 23:05:09 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <krh@bitplanet.net> | 2014-12-10 12:29:04 -0800 |
| commit | c5b3878714a75dab40439622050b2ce6f60337c0 (patch) | |
| tree | 869545b0693e5ed463edb206c54cd3f8935f2e31 /src/mesa/drivers/dri/i965/gen8_vs_state.c | |
| parent | d9e29f5d88d2ddd8ee9d10b7d88377a60fd0094f (diff) | |
| download | external_mesa3d-c5b3878714a75dab40439622050b2ce6f60337c0.tar.gz external_mesa3d-c5b3878714a75dab40439622050b2ce6f60337c0.tar.bz2 external_mesa3d-c5b3878714a75dab40439622050b2ce6f60337c0.zip | |
i965: Add new SIMD8 VS prog data flag
This flag signals that we have a SIMD8 VS shader so we can set up the
corresponding state accordingly. This boils down to setting
the BDW+ SIMD8 enable bit in 3DSTATE_VS and making UBO and pull
constant buffers use dword pitch.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen8_vs_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c index b7af466173..b0444e057f 100644 --- a/src/mesa/drivers/dri/i965/gen8_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c @@ -66,8 +66,10 @@ upload_vs_state(struct brw_context *brw) (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); + uint32_t simd8_enable = prog_data->simd8 ? GEN8_VS_SIMD8_ENABLE : 0; OUT_BATCH(((brw->max_vs_threads - 1) << HSW_VS_MAX_THREADS_SHIFT) | GEN6_VS_STATISTICS_ENABLE | + simd8_enable | GEN6_VS_ENABLE); /* _NEW_TRANSFORM */ |