i965: Change mipmap array_spacing_lod0 to array_layout (enum)

We will want to setup gen6 separate stencil and hiz miptrees in a
layout that is similar to array_spacing_lod0. This is needed because
gen6 hiz and stencil only support a single mip-level.

In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz),
the array slices will be packed at each LOD without reserving extra
space for LODs within each array slice.

So, we generalize the name of this field and add comments to indicate
the old and new uses.

Motivation for the gen6 change comes from the PRM:

PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
 "The separate stencil buffer does not support mip mapping, thus the
  storage for LODs other than LOD 0 is not needed."

PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
 "[DevSNB]: The hierarchical depth buffer does not support the LOD
  field, it is assumed by hardware to be zero. A separate
  hierarachical depth buffer is required for each LOD used, and the
  corresponding buffer’s state delivered to hardware each time a new
  depth buffer state with modified LOD is delivered."

v2:
 * Rename array_spacing_lod0 to non_mip_arrays
v3:
 * Instead, replace array_spacing_lod0 with array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 01120afefa..c257cb79c3 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -315,7 +315,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
    uint32_t effective_depth = (tObj->Immutable && tObj->Target != GL_TEXTURE_3D)
                               ? tObj->NumLayers : mt->logical_depth0;
 
-   if (mt->array_spacing_lod0)
+   if (mt->array_layout == ALL_SLICES_AT_EACH_LOD)
       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 
    surf[1] = mt->bo->offset64 + mt->offset; /* reloc */
@@ -508,8 +508,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 
    surf[0] = surftype << BRW_SURFACE_TYPE_SHIFT |
              format << BRW_SURFACE_FORMAT_SHIFT |
-             (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
-                                          : GEN7_SURFACE_ARYSPC_FULL) |
+             (irb->mt->array_layout == ALL_SLICES_AT_EACH_LOD ?
+                 GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL) |
              gen7_surface_tiling_mode(mt->tiling);
 
    if (irb->mt->align_h == 4)