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| author | Francisco Jerez <currojerez@riseup.net> | 2014-12-16 16:11:57 +0200 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2015-01-31 17:01:49 +0200 |
| commit | 11f5d8a5d4fbb861ec161f68593e429cbd65d1cd (patch) | |
| tree | 82973704141d16da0d20061a97602d9de37d5399 /src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | |
| parent | 11a955aef42730ab009490f03c03c54ed07db666 (diff) | |
| download | external_mesa3d-11f5d8a5d4fbb861ec161f68593e429cbd65d1cd.tar.gz external_mesa3d-11f5d8a5d4fbb861ec161f68593e429cbd65d1cd.tar.bz2 external_mesa3d-11f5d8a5d4fbb861ec161f68593e429cbd65d1cd.zip | |
i965: Enable L3 caching of buffer surfaces.
And remove the mocs argument of the emit_buffer_surface_state vtbl hook. Its
semantics vary greatly from one generation to another, so it kind of
encourages the caller to pass 0 which is the only valid setting across
generations. After this commit the hardware-specific code decides what the
best cacheability settings are for buffer surfaces, just like we do for
textures.
This together with some additional changes coming is expected to improve
performance of pull constants, buffer textures, atomic counters and image
objects on Gen7 and up.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 68f81d9a6c..07db678109 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -225,7 +225,6 @@ gen7_emit_buffer_surface_state(struct brw_context *brw, unsigned surface_format, unsigned buffer_size, unsigned pitch, - unsigned mocs, bool rw) { uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, @@ -241,7 +240,7 @@ gen7_emit_buffer_surface_state(struct brw_context *brw, surf[3] = SET_FIELD(((buffer_size - 1) >> 21) & 0x3f, BRW_SURFACE_DEPTH) | (pitch - 1); - surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS); + surf[5] = SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS); if (brw->is_haswell) { surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | @@ -385,7 +384,6 @@ gen7_create_raw_surface(struct brw_context *brw, drm_intel_bo *bo, BRW_SURFACEFORMAT_RAW, size, 1, - 0 /* mocs */, true /* rw */); } |