summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_meta_util.c
diff options
context:
space:
mode:
authorJason Ekstrand <jason.ekstrand@intel.com>2016-07-23 12:13:07 -0700
committerJason Ekstrand <jason.ekstrand@intel.com>2016-08-17 14:46:22 -0700
commitdff74b83e11c508cdc782f696d8166834857e0cc (patch)
tree6e34af664d4bac87bc7fc73a849fda6a37016c32 /src/mesa/drivers/dri/i965/brw_meta_util.c
parent8fccdf85ba329dc4ccd5764e430ae8d9abce0c69 (diff)
downloadexternal_mesa3d-dff74b83e11c508cdc782f696d8166834857e0cc.tar.gz
external_mesa3d-dff74b83e11c508cdc782f696d8166834857e0cc.tar.bz2
external_mesa3d-dff74b83e11c508cdc782f696d8166834857e0cc.zip
i965/meta_util: Convert get_resolve_rect to use ISL
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_meta_util.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_meta_util.c43
1 files changed, 21 insertions, 22 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c
index 77c6b83c26..a81190d98b 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -585,12 +585,11 @@ brw_meta_get_buffer_rect(const struct gl_framebuffer *fb,
}
void
-brw_get_resolve_rect(const struct brw_context *brw,
- const struct intel_mipmap_tree *mt,
- unsigned *x0, unsigned *y0,
- unsigned *x1, unsigned *y1)
+brw_get_ccs_resolve_rect(const struct isl_device *dev,
+ const struct isl_surf *ccs_surf,
+ unsigned *x0, unsigned *y0,
+ unsigned *x1, unsigned *y1)
{
- unsigned x_align, y_align;
unsigned x_scaledown, y_scaledown;
/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
@@ -598,25 +597,25 @@ brw_get_resolve_rect(const struct brw_context *brw,
* A rectangle primitive must be scaled down by the following factors
* with respect to render target being resolved.
*
- * The scaledown factors in the table that follows are related to the
- * alignment size returned by intel_get_non_msrt_mcs_alignment() by a
- * multiplier. For IVB and HSW, we divide by two, for BDW we multiply
- * by 8 and 16. Similar to the fast clear, SKL eases the BDW vertical scaling
- * by a factor of 2.
+ * The scaledown factors in the table that follows are related to the block
+ * size of the CCS format. For IVB and HSW, we divide by two, for BDW we
+ * multiply by 8 and 16. On Sky Lake, we multiply by 8.
*/
-
- intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
- if (brw->gen >= 9) {
- x_scaledown = x_align * 8;
- y_scaledown = y_align * 8;
- } else if (brw->gen >= 8) {
- x_scaledown = x_align * 8;
- y_scaledown = y_align * 16;
+ const struct isl_format_layout *fmtl =
+ isl_format_get_layout(ccs_surf->format);
+ assert(fmtl->txc == ISL_TXC_CCS);
+
+ if (ISL_DEV_GEN(dev) >= 9) {
+ x_scaledown = fmtl->bw * 8;
+ y_scaledown = fmtl->bh * 8;
+ } else if (ISL_DEV_GEN(dev) >= 8) {
+ x_scaledown = fmtl->bw * 8;
+ y_scaledown = fmtl->bh * 16;
} else {
- x_scaledown = x_align / 2;
- y_scaledown = y_align / 2;
+ x_scaledown = fmtl->bw / 2;
+ y_scaledown = fmtl->bh / 2;
}
*x0 = *y0 = 0;
- *x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
- *y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
+ *x1 = ALIGN(ccs_surf->logical_level0_px.width, x_scaledown) / x_scaledown;
+ *y1 = ALIGN(ccs_surf->logical_level0_px.height, y_scaledown) / y_scaledown;
}