blob: adec722805e2ca63ca43ddc6103ee018a29ed874 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
|
//===-- SparcTargetAsmInfo.cpp - Sparc asm properties -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declarations of the SparcTargetAsmInfo properties.
//
//===----------------------------------------------------------------------===//
#include "SparcTargetAsmInfo.h"
#include "llvm/ADT/SmallVector.h"
using namespace llvm;
SparcELFTargetAsmInfo::SparcELFTargetAsmInfo(const TargetMachine &TM)
: ELFTargetAsmInfo(TM) {
Data16bitsDirective = "\t.half\t";
Data32bitsDirective = "\t.word\t";
Data64bitsDirective = 0; // .xword is only supported by V9.
ZeroDirective = "\t.skip\t";
CommentString = "!";
ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
COMMDirectiveTakesAlignment = true;
CStringSection=".rodata.str";
// Sparc normally uses named section for BSS.
BSSSection_ = getNamedSection("\t.bss",
SectionFlags::Writable | SectionFlags::BSS);
}
void SparcELFTargetAsmInfo::getSectionFlags(unsigned Flags,
SmallVectorImpl<char> &Str) const {
if (Flags & SectionFlags::Mergeable)
return ELFTargetAsmInfo::getSectionFlags(Flags, Str);
// FIXME: Inefficient.
std::string Res;
if (!(Flags & SectionFlags::Debug))
Res += ",#alloc";
if (Flags & SectionFlags::Code)
Res += ",#execinstr";
if (Flags & SectionFlags::Writable)
Res += ",#write";
if (Flags & SectionFlags::TLS)
Res += ",#tls";
Str.append(Res.begin(), Res.end());
}
|
