aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86/X86ISelLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
* Swap fp comparison operands and change predicate to allow load folding.Evan Cheng2008-08-281-4/+18
* remove tabs, fix > 80 colsGabor Greif2008-08-281-10/+16
* erect abstraction boundaries for accessing SDValue members, rename Val -> Nod...Gabor Greif2008-08-281-108/+108
* Use resize instead of reserve. Reserve doesn't change size().Rafael Espindola2008-08-281-1/+1
* Split the ATOMIC NodeType's to include the size, e.g.Dale Johannesen2008-08-281-13/+22
* disallow direct access to SDValue::ResNo, provide a getter insteadGabor Greif2008-08-261-3/+3
* If an xmm register is referenced explicitly in an inline asm, make sure to Chris Lattner2008-08-261-49/+61
* Try approach to moving call address load inside of callseq_start. Now it's do...Evan Cheng2008-08-251-2/+2
* Temporarily reverting r55292. It's causing a bootstraping failure:Bill Wendling2008-08-241-7/+2
* Move callseq_start above the call address load to allow load to be folded int...Evan Cheng2008-08-241-2/+7
* If part of the mask is "undef", then ignore it as we don't care what goes int...Bill Wendling2008-08-211-0/+2
* Fix whitespace. No functionality change.Bill Wendling2008-08-211-6/+20
* Fix a number of byval / memcpy / memset related codegen issues.Evan Cheng2008-08-211-44/+46
* Treat floating point ST1 the same as ST0 when lowering for a call resultMon P Wang2008-08-211-1/+2
* Simplify FastISel's constructor argument list, make the FastISelDan Gohman2008-08-201-4/+2
* Add remaining 64-bit atomic patterns for x86-64.Dale Johannesen2008-08-201-0/+32
* Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.Bill Wendling2008-08-201-0/+2
* Instantiate FastISel for X86.Dan Gohman2008-08-191-2/+2
* The X86 target will soon have an implementation of createFastISel.Dan Gohman2008-08-191-0/+8
* Add support for 8 and 16 bit forms of __syncDale Johannesen2008-08-191-13/+90
* Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return ...Evan Cheng2008-08-171-2/+2
* Use correct name for TLS address resolution routine on x86-64Anton Korobeynikov2008-08-161-2/+2
* Also avoid pinsrw and pinsrb with a variable insertelement index.Dan Gohman2008-08-141-1/+2
* Don't try to use the insertps instruction for vectorDan Gohman2008-08-141-1/+1
* Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64.Evan Cheng2008-08-051-2/+3
* Add an assert to catch invalid VECTOR_SHUFFLE mask indices.Dan Gohman2008-08-041-0/+1
* Add atomic sub for other sizesAndrew Lenharth2008-08-031-1/+2
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-565/+565
* Tidy SDNode::use_iterator, and complete the transition to have itDan Gohman2008-07-271-1/+1
* Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmxNate Begeman2008-07-251-15/+23
* Fix PR2485: do all 4-element SSE shuffles in max. of 2 shuffle instructions.Evan Cheng2008-07-231-5/+60
* Factor out SSE 4 wide shuffle lowering code into its own function. No functio...Evan Cheng2008-07-221-104/+106
* Fix PR2574: implement v2f32 scalar_to_vector.Evan Cheng2008-07-221-0/+7
* Add VerifyNode, a place to put sanity checks onDuncan Sands2008-07-211-3/+4
* Fix for first part of PR2562. Generate the "pinsrw" instruction for insertsBill Wendling2008-07-201-0/+2
* SSE codegen for vsetcc nodesNate Begeman2008-07-171-6/+127
* When lowering certain atomics, we need to copy the memoperand from the oldMon P Wang2008-07-171-1/+5
* x86-64 PIC JIT fixes: do not generate the extra load for external GV's.Evan Cheng2008-07-161-7/+3
* Include a frame index in the "fixed stack" pseudo source valueDan Gohman2008-07-111-11/+8
* The frame address on an x86-64 box needs to be offset by -8, not -4.Bill Wendling2008-07-111-1/+1
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-20/+20
* Rather than having a different custom legalizationDuncan Sands2008-07-041-2/+3
* Add a new getMergeValues method that does not needDuncan Sands2008-07-021-12/+12
* Highlight that getMergeValues optimization isDuncan Sands2008-07-011-1/+2
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-2/+4
* Update comments to new-style syntax.Dan Gohman2008-06-301-3/+3
* Rename ISD::LOCATION to ISD::DBG_STOPPOINT to better reflect itsDan Gohman2008-06-301-2/+2
* Revert the SelectionDAG optimization that makesDuncan Sands2008-06-301-52/+27
* - Fix a x86 vector isel bug: illegal transformation of a vector_shuffle into aEvan Cheng2008-06-251-4/+3
* Remove the OrigVT member from AtomicSDNode, as it is redundant withDan Gohman2008-06-251-4/+4