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* Transfer regmasks to MRI.Jakob Stoklund Olesen2012-02-173-13/+7
* Refactor 'handleMove' code in live intervals. Clients of LiveIntervals won't seeLang Hames2012-02-171-211/+245
* Tidy up.Jim Grosbach2012-02-173-5/+6
* Revert r150288, "Allow Post-RA LICM to hoist reserved register reads."Jakob Stoklund Olesen2012-02-171-11/+0
* ... and it's probably best to use the correct alignment, rather than just gue...David Chisnall2012-02-171-1/+1
* It turns out that putting an 8-byte symbol in a 4-byte section makes Solaris ...David Chisnall2012-02-171-3/+3
* Reverse iterator - should be incrementing rather than decrementing.Lang Hames2012-02-171-2/+2
* MachineScheduler shouldn't use/preserve LiveDebugVariables.Lang Hames2012-02-171-4/+0
* Oops - isRegLiveIntoSuccessor is used in non-assert builds now. Remove NDEBUG...Lang Hames2012-02-171-2/+0
* Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ba...Lang Hames2012-02-171-3/+9
* Turn off assertion, conservatively compute liveness for live-in un-allocatabl...Lang Hames2012-02-171-8/+10
* Disable machine copy propagation for now. It's known to be buggy (PR11940) an...Benjamin Kramer2012-02-161-1/+1
* Remove extraneous #include and spelling mistake introduced in r150669.James Molloy2012-02-161-2/+1
* Modify the algorithm when traversing the DAGCombiner's worklist to be O(log N...James Molloy2012-02-161-13/+36
* Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames2012-02-161-9/+3
* MachineCSE shouldn't extend the live ranges of reserved or allocatable regist...Lang Hames2012-02-161-3/+9
* Handle register masks in branch folding.Jakob Stoklund Olesen2012-02-151-0/+8
* Fix library visibility problems with VLIWPacketizer.Andrew Trick2012-02-151-6/+19
* Make LiveIntervals::handleMove() bundle aware.Lang Hames2012-02-152-4/+16
* Use 'getDataNoRel' for the section kind.Bill Wendling2012-02-151-5/+4
* Fix assertion condition.Lang Hames2012-02-151-1/+1
* Modify the code that emits the module flags to use the new module flags accessorBill Wendling2012-02-152-38/+38
* Don't expose DefaultVLIWSchedulerAndrew Trick2012-02-151-1/+1
* Remove overly conservative assert.Lang Hames2012-02-151-1/+0
* Generic "VLIW" packetizer based on a DFA generated from target itinerary.Andrew Trick2012-02-151-0/+147
* Revert r150565 again. Appears to be a stage2 failure with dragonegg.Andrew Trick2012-02-151-6/+8
* Reapply r150565 with the typo fix properly merged.Andrew Trick2012-02-151-8/+6
* reverting r150565. Premature push.Andrew Trick2012-02-151-6/+8
* Move PostRAMachineLICM into MachineLateOptimization. It now runs after PEI!Andrew Trick2012-02-151-8/+6
* Allow CodeGen (llc) command line options to work as expected.Andrew Trick2012-02-151-52/+114
* Added TargetPassConfig::disablePass/substitutePass as a general mechanism to ...Andrew Trick2012-02-151-6/+42
* Don't emit live ranges for physregs live-ins that are dead.Lang Hames2012-02-151-2/+3
* Disentangle moving a machine instr from updating LiveIntervals.Lang Hames2012-02-152-13/+9
* Added hook to let targets custom lower splitting of illegal vectorsPete Cooper2012-02-151-0/+4
* Fix global live range splitting regmask accuracy.Jakob Stoklund Olesen2012-02-141-1/+2
* Fix details in local live range splitting with regmasks.Jakob Stoklund Olesen2012-02-141-6/+16
* Handle regmasks in findRegisterDefOperandIdx().Jakob Stoklund Olesen2012-02-141-0/+4
* Use the proper clobber check in handleLiveInRegister().Jakob Stoklund Olesen2012-02-141-1/+1
* Dump live intervals in numerical order.Jakob Stoklund Olesen2012-02-141-4/+15
* Don't create a new copy of reserved regs - we already have one handy.Lang Hames2012-02-141-4/+2
* Add code to the target lowering object file module to handle module flags.Bill Wendling2012-02-142-0/+64
* Update MachineVerifier to check the new physreg live-in rules.Lang Hames2012-02-141-0/+22
* Tighten physical register invariants: Allocatable physical registers canLang Hames2012-02-141-9/+43
* Fix PR12000. Some vector operations may use scalar operands with typesNadav Rotem2012-02-141-1/+5
* Turn push_back loops into append/insert.Benjamin Kramer2012-02-141-4/+2
* Rename getExceptionAddressRegister() to getExceptionPointerRegister() for con...Lang Hames2012-02-143-3/+3
* Use convenience function for consistency.Lang Hames2012-02-141-2/+1
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-0/+6
* Don't recalculate the size of the vector each time through the loop.Bill Wendling2012-02-131-2/+2
* Add register mask support to ScheduleDAGRRList.Jakob Stoklund Olesen2012-02-131-11/+49