| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add predicates for checking whether targets have free FNEG and FABS operation... | Owen Anderson | 2012-04-02 | 1 | -3/+5 |
| * | Optimizing swizzles of complex shuffles may generate additional complex shuff... | Nadav Rotem | 2012-04-02 | 1 | -1/+9 |
| * | This commit contains a few changes that had to go in together. | Nadav Rotem | 2012-04-01 | 1 | -0/+92 |
| * | Teach CodeGen's version of computeMaskedBits to understand the range metadata. | Rafael Espindola | 2012-03-31 | 2 | -7/+13 |
| * | If we have a VLA that has a "use" in a metadata node that's then used | Bill Wendling | 2012-03-30 | 1 | -1/+12 |
| * | More debug output. | Eric Christopher | 2012-03-28 | 1 | -1/+2 |
| * | fix what looks like a real logic bug, found by PVS-Studio (part of PR12357) | Chris Lattner | 2012-03-27 | 1 | -2/+2 |
| * | Add a debug statement. | Eric Christopher | 2012-03-26 | 1 | -1/+3 |
| * | Add the ability to promote legal integer VAARGs. This is required for the PPC... | Hal Finkel | 2012-03-24 | 1 | -1/+33 |
| * | Source order scheduler should not preschedule nodes with multiple uses. rdar:... | Evan Cheng | 2012-03-22 | 1 | -7/+11 |
| * | Assign node orders to target intrinsics which do not produce results. rdar://... | Evan Cheng | 2012-03-22 | 1 | -0/+6 |
| * | [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271% | Chad Rosier | 2012-03-22 | 1 | -0/+7 |
| * | Checking a build_vector for an all-ones value. | Jim Grosbach | 2012-03-21 | 1 | -5/+14 |
| * | When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add user... | Craig Topper | 2012-03-20 | 1 | -0/+1 |
| * | Do everything up to generating code to try to get a register for | Eric Christopher | 2012-03-20 | 1 | -1/+6 |
| * | Untabify. | Eric Christopher | 2012-03-20 | 1 | -2/+2 |
| * | Add another debugging statement here. | Eric Christopher | 2012-03-20 | 1 | -0/+4 |
| * | Use lookUpRegForValue here instead of duplicating the code. | Eric Christopher | 2012-03-20 | 1 | -9/+2 |
| * | f16 FDIV can now be legalized by promoting to f32 | Pete Cooper | 2012-03-19 | 1 | -1/+2 |
| * | Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala. | Duncan Sands | 2012-03-19 | 1 | -0/+6 |
| * | Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." f... | NAKAMURA Takumi | 2012-03-16 | 1 | -1/+1 |
| * | We actually handle AllocaInst via getRegForValue below just fine. | Eric Christopher | 2012-03-15 | 1 | -1/+1 |
| * | Add some debugging output into fast isel as well. | Eric Christopher | 2012-03-15 | 1 | -2/+6 |
| * | Add another debug statement. | Eric Christopher | 2012-03-15 | 1 | -1/+3 |
| * | When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add... | Nadav Rotem | 2012-03-15 | 1 | -0/+4 |
| * | Add a xform to the DAG combiner. | Bill Wendling | 2012-03-15 | 1 | -0/+17 |
| * | Insert the debugging instructions in one fell-swoop so that it doesn't call the | Bill Wendling | 2012-03-14 | 1 | -7/+8 |
| * | Fortify r152675 a bit. Although I'm not able to come up with a test case that... | Evan Cheng | 2012-03-13 | 1 | -3/+11 |
| * | DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) to | Evan Cheng | 2012-03-13 | 1 | -4/+19 |
| * | Add a return type. | Bill Wendling | 2012-03-13 | 1 | -1/+1 |
| * | Inline the d'tor and add an anchor instead. | Bill Wendling | 2012-03-13 | 1 | -1/+1 |
| * | Refactor the SelectionDAG's 'dump' methods into their own .cpp file. | Bill Wendling | 2012-03-13 | 3 | -633/+632 |
| * | llvm::SwitchInst | Stepan Dyatkovskiy | 2012-03-11 | 1 | -1/+1 |
| * | Give dagcombiner's worklist some inline capacity. | Benjamin Kramer | 2012-03-10 | 1 | -3/+2 |
| * | Use uint16_t to store instruction implicit uses and defs. Reduces static data. | Craig Topper | 2012-03-08 | 2 | -8/+8 |
| * | Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012: | Stepan Dyatkovskiy | 2012-03-08 | 1 | -4/+4 |
| * | misched preparation: rename core scheduler methods for consistency. | Andrew Trick | 2012-03-07 | 6 | -37/+37 |
| * | misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. | Andrew Trick | 2012-03-07 | 3 | -14/+22 |
| * | misched preparation: modularize schedule emission. | Andrew Trick | 2012-03-07 | 2 | -3/+51 |
| * | misched preparation: modularize schedule printing. | Andrew Trick | 2012-03-07 | 3 | -0/+17 |
| * | misched preparation: modularize schedule verification. | Andrew Trick | 2012-03-07 | 5 | -3/+22 |
| * | whitespace | Andrew Trick | 2012-03-07 | 1 | -5/+5 |
| * | Cleanup in preparation for misched: Move DAG visualization logic. | Andrew Trick | 2012-03-07 | 2 | -0/+7 |
| * | whitespace | Andrew Trick | 2012-03-07 | 1 | -3/+3 |
| * | Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ... | Andrew Trick | 2012-03-07 | 1 | -1/+1 |
| * | Extend r148086 to check for [r +/- reg] address mode. This fixes queens perfo... | Evan Cheng | 2012-03-06 | 1 | -4/+7 |
| * | Make it possible for a target to mark FSUB as Expand. This requires providin... | Owen Anderson | 2012-03-06 | 2 | -16/+39 |
| * | Fix warnings about adding a bool to a string. | Bill Wendling | 2012-03-05 | 1 | -2/+2 |
| * | Use uint16_t to store register overlaps to reduce static data. | Craig Topper | 2012-03-04 | 2 | -2/+2 |
| * | Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ... | James Molloy | 2012-03-01 | 1 | -2/+4 |
