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* Update aosp/master LLVM with patches for fp16Pirama Arumuga Nainar2015-05-261-1/+2
| | | | | | | | | | Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363, r235530, r235609, r235610, r237004 r235191 has a required bug-fix and the rest are all related to fp16. Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6 (cherry picked from commit a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68)
* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-185-77/+82
| | | | | Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-098-81/+195
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-2315-1070/+357
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-0216-320/+648
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* am 281cc67b: Merge "Bring in fixes for Cortex-A53 errata + build updates."Stephen Hines2014-10-171-0/+9
|\ | | | | | | | | * commit '281cc67b6ac794b1eb8232e6efca366d870dad43': Bring in fixes for Cortex-A53 errata + build updates.
| * Bring in fixes for Cortex-A53 errata + build updates.Stephen Hines2014-10-171-0/+9
| | | | | | | | | | | | Bug: 18034609 Change-Id: I2cf0094eb9df801a84274ff29018431d75da89dd
| * Update LLVM for rebase to r212749.Stephen Hines2014-07-219-31/+122
| | | | | | | | | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* | Undefined fseeko/ftello for Windows builds.Stephen Hines2014-09-301-0/+11
| | | | | | | | | | | | | | | | | | | | Bug: 14416410 These are "defined" when building under mingw, so they can't be used as identifiers in LLVM. Once we fix this in upstream, we can pull the patch back and revert this one. Change-Id: Ib576a9617ca685ab3625a2d2d66f652bcb7f2c3e
* | Update LLVM for rebase to r212749.Stephen Hines2014-07-259-31/+122
|/ | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-2913-152/+314
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-2414-365/+468
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Merge remote-tracking branch 'upstream/release_34' into merge-20140211Stephen Hines2014-02-1116-67/+375
|\ | | | | | | | | | | | | | | Conflicts: lib/Linker/LinkModules.cpp lib/Support/Unix/Signals.inc Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
| * Merging r195491:Bill Wendling2013-11-251-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195491 | probinson | 2013-11-22 11:11:24 -0800 (Fri, 22 Nov 2013) | 11 lines Teach ISel not to optimize 'optnone' functions (revised). Improvements over r195317: - Set/restore EnableFastISel flag instead of just running FastISel within SelectAllBasicBlocks; the flag is checked in various places, and FastISel won't run properly if those places don't do the right thing. - Test looks for normal ISel versus FastISel behavior, and not something more subtle that doesn't work everywhere. Based on work by Andrea Di Biagio. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195604 91177308-0d34-0410-b5e6-96231b3b80d8
| * Merging r195339:Bill Wendling2013-11-211-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195339 | chapuni | 2013-11-21 02:55:15 -0800 (Thu, 21 Nov 2013) | 5 lines Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions." It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown". FYI, it didn't appear to add either "-O0" or "-fast-isel". ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195375 91177308-0d34-0410-b5e6-96231b3b80d8
| * Merging r195317:Bill Wendling2013-11-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r195317 | probinson | 2013-11-20 22:33:32 -0800 (Wed, 20 Nov 2013) | 4 lines Teach ISel not to optimize 'optnone' functions. Based on work by Andrea Di Biagio. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195321 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-171-0/+17
| | | | | | | | | | | | | | | | Implementing this on bigendian platforms could get strange. I added a target hook, getStackSlotRange, per Jakob's recommendation to make this as explicit as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-151-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add addrspacecast instruction.Matt Arsenault2013-11-151-0/+5
| | | | | | | | | | | | Patch by Michele Scandale! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move the old pass manager infrastructure into a legacy namespace andChandler Carruth2013-11-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | give the files a legacy prefix in the right directory. Use forwarding headers in the old locations to paper over the name change for most clients during the transitional period. No functionality changed here! This is just clearing some space to reduce renaming churn later on with a new system. Even when the new stuff starts to go in, it is going to be hidden behind a flag and off-by-default as it is still WIP and under development. This patch is specifically designed so that very little out-of-tree code has to change. I'm going to work as hard as I can to keep that the case. Only direct forward declarations of the PassManager class are impacted by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194324 91177308-0d34-0410-b5e6-96231b3b80d8
| * [Stackmap] Materialize the jump address within the patchpoint noop slide.Juergen Ributzka2013-11-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the jump address materialization inside the noop slide. This enables patching of the materialization itself or its complete removal. This patch also adds the ability to define scratch registers that can be used safely by the code called from the patchpoint intrinsic. At least one scratch register is required, because that one is used for the materialization of the jump address. This patch depends on D2009. Differential Revision: http://llvm-reviews.chandlerc.com/D2074 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
| * [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.Juergen Ributzka2013-11-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea of the AnyReg Calling Convention is to provide the call arguments in registers, but not to force them to be placed in a paticular order into a specified set of registers. Instead it is up tp the register allocator to assign any register as it sees fit. The same applies to the return value (if applicable). Differential Revision: http://llvm-reviews.chandlerc.com/D2009 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194293 91177308-0d34-0410-b5e6-96231b3b80d8
| * Convert comments to documentation comments (// -> ///)Dmitri Gribenko2013-11-051-9/+10
| | | | | | | | | | | | | | Patch by MathOnNapkins git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194093 91177308-0d34-0410-b5e6-96231b3b80d8
| * Convert calls to __sinpi and __cospi into __sincospi_stretBob Wilson2013-11-031-0/+12
| | | | | | | | | | | | | | | | | | | | This adds an SimplifyLibCalls case which converts the special __sinpi and __cospi (float & double variants) into a __sincospi_stret where appropriate to remove duplicated work. Patch by Tim Northover git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193943 91177308-0d34-0410-b5e6-96231b3b80d8
| * Lower stackmap intrinsics directly to their target opcode in the DAG builder.Andrew Trick2013-10-313-1/+28
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193769 91177308-0d34-0410-b5e6-96231b3b80d8
| * Update commentMatt Arsenault2013-10-291-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193651 91177308-0d34-0410-b5e6-96231b3b80d8
| * Workaround MSVC 32-bit miscompile of getCondCodeAction.Matt Arsenault2013-10-291-15/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use 32-bit types for the array instead of 64. This should generally be better anyway. In optimized + assert builds, I saw a failure when a cond code / type combination that is never set was loading a non-zero value and hitting the != Promote assert. It turns out when loading the 64-bit value to do the shift, the assembly loads the 2 32-bit halves from non-consecutive addresses. The address the second half of the loaded uint64_t doesn't include the offset of the array in the struct. Instead of being offset + 4, it's just + 4. I'm not entirely sure why this wasn't observed before. setCondCodeAction isn't heavily used by the in-tree targets, and not with the higher valued vector SimpleValueTypes. Only PPC is using one of the > 32 valued types, and that is probably never used by anyone on a 32-bit MSVC compiled host. I ran into this when upgrading LLVM versions, so I guess the value loaded from the nonsense address happened to work out before. No test since I'm not really sure if / how it can be reproduced with the current in tree targets, and it's not supposed to change anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193650 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move getSymbol to TargetLoweringObjectFile.Rafael Espindola2013-10-292-8/+5
| | | | | | | | | | | | This allows constructing a Mangler with just a TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193630 91177308-0d34-0410-b5e6-96231b3b80d8
| * SelectionDAG: Pass along the original argument/element type in ISD::InputArgTom Stellard2013-10-231-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some targets, it is useful to be able to look at the original type of an argument without having to dig through the original IR. This also fixes a bug in SelectionDAGBuilder where InputArg.PartOffset was not taking into account the offset of structure elements. Patch by: Justin Holewinski Tom Stellard: - Changed the type of ArgVT to EVT, so it can store non-simple types like v3i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193214 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unused TargetLowering field.Matt Arsenault2013-10-211-4/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193113 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-211-3/+7
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193112 91177308-0d34-0410-b5e6-96231b3b80d8
| * [projects/test-suite] White space and long line fixes.Jack Carter2013-10-171-10/+14
| | | | | | | | | | | | | | No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192863 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix the ExecutionDepsFix pass to handle AVX instructions.Andrew Trick2013-10-141-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass is needed to break false dependencies. Without it, unlucky register assignment can result in wild (5x) swings in performance. This pass was trying to handle AVX but not getting it right. AVX doesn't have partial register defs, it has unused register reads in which the high bits of a source operand are copied into the unused bits of the dest. Fixing this requires conservative liveness analysis. This is awkard because the pass already has its own pseudo-liveness. However, proper liveness is expensive, and we would like to use a generic utility to compute it. The fix only invokes liveness on-demand. It is rare to detect a case that needs undef-read dependence breaking, but when it happens, it can be needed many times within a very large block. I think the existing heuristic which uses a register window of 16 is too conservative for loop-carried false dependencies. If the loop is a reduction. The out-of-order engine may be able to execute several loop iterations in parallel. However, I'll leave this tuning exercise for next time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192635 91177308-0d34-0410-b5e6-96231b3b80d8
| * [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-111-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
| * [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-111-29/+0
| | | | | | | | | | | | on ubuntu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
| * [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-111-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
| * test commitSriram Murali2013-10-101-2/+4
| | | | | | | | | | | | | | | | - fix comments on vector type legalization git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192389 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix grammar / missing wordsMatt Arsenault2013-10-101-2/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192380 91177308-0d34-0410-b5e6-96231b3b80d8
| * IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
| * Even more spelling fixes for "instruction".Robert Wilhelm2013-09-281-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191611 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added temp flag -misched-bench for staging in default changes.Andrew Trick2013-09-261-0/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191423 91177308-0d34-0410-b5e6-96231b3b80d8
| * Mark the x86 machine model as incomplete. PR17367.Andrew Trick2013-09-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | Ideally, the machinel model is added at the time the instructions are defined. But many instructions in X86InstrSSE.td still need a model. Without this workaround the scheduler asserts because x86 already has itinerary classes for these instructions, indicating they should be modeled by the scheduler. Since we use the new machine model for other instructions, it expects a new machine model for these too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191391 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added MachineSchedPolicy.Andrew Trick2013-09-061-0/+11
| | | | | | | | | | | | | | | | Allow subtargets to customize the generic scheduling strategy. This is convenient for targets that don't need to add new heuristics by specializing the strategy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190176 91177308-0d34-0410-b5e6-96231b3b80d8
| * mi-sched: Load clustering is a bit to expensive to enable unconditionally.Andrew Trick2013-09-041-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189990 91177308-0d34-0410-b5e6-96231b3b80d8
| * Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add useAA() to TargetSubtargetInfoHal Finkel2013-08-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | There are several optional (off-by-default) features in CodeGen that can make use of alias analysis. These features are important for generating code for some kinds of cores (for example the (in-order) PPC A2 core). This adds a useAA() function to TargetSubtargetInfo to allow these features to be enabled by default on a per-subtarget basis. Here is the first use of this function: To control the default of the -enable-aa-sched-mi feature. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189563 91177308-0d34-0410-b5e6-96231b3b80d8
| * SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
| * PrintVRegOrUnitAndrew Trick2013-08-231-0/+16
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189124 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add an OtherPreserved field to the CalleeSaved TableGen class.Jakob Stoklund Olesen2013-08-231-0/+6
| | | | | | | | | | | | | | | | | | | | This field specifies registers that are preserved across function calls, but that should not be included in the generates SaveList array. This can be used ot generate regmasks for architectures that save registers through other means, like SPARC's register windows. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
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