aboutsummaryrefslogtreecommitdiffstats
path: root/include/llvm/MC/MCRegisterInfo.h
Commit message (Collapse)AuthorAgeFilesLines
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-0/+72
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-5/+8
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-4/+4
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-6/+9
| | | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-311-0/+18
| | | | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-281-24/+71
| | | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182783 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor fix to comment from my previous commit.Chad Rosier2013-05-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182536 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify the logic described in the comment.Chad Rosier2013-05-221-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182534 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the IncludeSelf parameter to the MCSubRegIterator and MCSuperRegIteratorChad Rosier2013-05-221-5/+13
| | | | | | | | constructors. No functional change. Part of rdar://12906217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182490 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing assertion, the null register has no register units.Jakob Stoklund Olesen2012-12-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170916 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some DOxygen comments.Jim Grosbach2012-12-201-26/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170628 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-0/+8
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
* Add isSubRegisterEq() and isSuperRegisterEq().Jim Grosbach2012-12-191-4/+14
| | | | | | | isSub and isSuper return false if RegA == RegB. Add variants which also include the identity function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170609 91177308-0d34-0410-b5e6-96231b3b80d8
* Move isSubRegister() and isSuperRegister to MCRegisterInfo.Jim Grosbach2012-12-191-0/+17
| | | | | | | | These were defined on TargetRegisterInfo, but they don't use any information that's not available in MCRegisterInfo, so sink them down to be available at the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170608 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen2012-11-291-7/+11
| | | | | | Use this type for arrays of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
* MCRegisterClass should be returned by const ref, not by value.Lang Hames2012-10-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166822 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-111-0/+7
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
* Give MCRegisterInfo an implementation file.Jakob Stoklund Olesen2012-07-271-55/+3
| | | | | | | | Move some functions from MCRegisterInfo.h that don't need to be inline. This shrinks llc by 8K. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160865 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the large XXXSubRegTable constant arrays.Jakob Stoklund Olesen2012-07-271-13/+32
| | | | | | | | | | | These tables were indexed by [register][subreg index] which made them, very large and sparse. Replace them with lists of sub-register indexes that match the existing lists of sub-registers. MCRI::getSubReg() becomes a very short linear search, like getSubRegIndex() already was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160843 91177308-0d34-0410-b5e6-96231b3b80d8
* Differentially encode all MC register lists.Jakob Stoklund Olesen2012-07-251-34/+20
| | | | | | | This simplifies MCRegisterInfo and shrinks the target descriptions a bit more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160758 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the old register list functions from MCRegisterInfo.Jakob Stoklund Olesen2012-06-011-36/+0
| | | | | | | | | | These functions exposed the layout of the underlying data tables as null-terminated uint16_t arrays. Use the new MCSubRegIterator, MCSuperRegIterator, and MCRegAliasIterator classes instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157855 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen2012-06-011-6/+10
| | | | | | | | | | | | | No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit register unit root tables.Jakob Stoklund Olesen2012-05-311-1/+46
| | | | | | | | | | Each register unit has one or two root registers. The full set of registers containing a given register unit can be computed as the union of the root registers and their super-registers. Provide an MCRegUnitRootIterator class to enumerate the roots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157753 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MCRegisterInfo::RegListIterator.Jakob Stoklund Olesen2012-05-301-2/+54
| | | | | | | | | | | Also add subclasses MCSubRegIterator, MCSuperRegIterator, and MCRegAliasIterator. These iterators provide an abstract interface to the MCRegisterInfo register lists so the internal representation can be changed without changing all clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157695 91177308-0d34-0410-b5e6-96231b3b80d8
* Make DiffListIterator public to unbreak the gcc buildbots.Jakob Stoklund Olesen2012-05-301-1/+1
| | | | | | Apparently, a friend can't derive from a private class according to gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157654 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit register unit lists for each register.Jakob Stoklund Olesen2012-05-291-1/+103
| | | | | | | | | | | | | | | | Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
* Compress MCRegisterInfo register name tables.Jakob Stoklund Olesen2012-05-251-5/+8
| | | | | | | Store (debugging) register names as offsets into a string table instead of as char pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157449 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen'erate mapping physical registers to encoding values.Jim Grosbach2012-05-151-1/+13
| | | | | | | | | | | Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement DwarfLLVMRegPair::operator< without violating asymmetry.Benjamin Kramer2012-04-041-4/+5
| | | | | | MSVC8 verifies this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154002 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the LLVM<->DWARF register mapping as a sorted table and use binary ↵Benjamin Kramer2012-04-011-26/+52
| | | | | | | | | | | | | | | search to do the lookup. This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated by recent inliner changes but the methods were already enormous with the old inline cost computation. The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table. I didn't implement that optimization yet to avoid potentially changing functionality. There is still some duplication both in tablegen and the generated code that should be cleaned up eventually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply 153764 and 153761 with a fix.Jakob Stoklund Olesen2012-03-301-12/+7
| | | | | | | | | Use an explicit comparator instead of the default. The sets are sorted, but not using the default comparator. Hopefully, this will unbreak the Linux builders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 153764 and 153761. They broke a --enable-optimized --enable-assertionsRafael Espindola2012-03-301-7/+12
| | | | | | --enable-expensive-checks build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8
* Compress register lists by sharing suffixes.Jakob Stoklund Olesen2012-03-301-12/+7
| | | | | | | | TableGen emits lists of sub-registers, super-registers, and overlaps. Put them all in a single table and use a SequenceToOffsetTable to share suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8
* Increase number of allowed registers in register classes to 64k instead of ↵Craig Topper2012-03-061-4/+4
| | | | | | 256. Widen register class ID to 16-bits. Widen register size and alignment to be up to 64k bytes instead of 256 bytes. This partially reverts r152019 to be less restrictive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152100 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r152016 and allow overlap, sub, super register tables to be more than ↵Craig Topper2012-03-061-3/+3
| | | | | | 64k entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152099 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-1/+1
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152045 91177308-0d34-0410-b5e6-96231b3b80d8
* MCRegisterInfo-ize getMatchingSuperReg.Jim Grosbach2012-03-051-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152044 91177308-0d34-0410-b5e6-96231b3b80d8
* Shrink and reorder fields in MCRegisterClass to reduce size of static data.Craig Topper2012-03-051-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152019 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-9/+9
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-5/+5
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer2012-03-011-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach2012-03-011-1/+15
| | | | | | | | Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that ↵Craig Topper2012-02-231-7/+3
| | | | | | were added in r151038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder some members in MCRegisterClass to remove padding on 64-bit builds.Craig Topper2012-02-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
* In generated RegisterInfo files, replace a pointer to the end of an array ↵Craig Topper2012-02-211-3/+4
| | | | | | with just the size of the array to avoid relocations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151041 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge some tables in generated RegisterInfo file. Store indices into larger ↵Craig Topper2012-02-211-9/+21
| | | | | | table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151038 91177308-0d34-0410-b5e6-96231b3b80d8
* Value initialize MCRegisterClasses. Not sure how could miss this during the ↵Benjamin Kramer2012-02-081-12/+1
| | | | | | MCTargetDesc refactor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150076 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149849 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2011-10-271-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143113 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-13 02:31:15 +0000