diff options
Diffstat (limited to 'test/CodeGen/AArch64')
53 files changed, 269 insertions, 269 deletions
diff --git a/test/CodeGen/AArch64/adc.ll b/test/CodeGen/AArch64/adc.ll index 7cb373232a..26fd3e66b7 100644 --- a/test/CodeGen/AArch64/adc.ll +++ b/test/CodeGen/AArch64/adc.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s define i128 @test_simple(i128 %a, i128 %b, i128 %c) { -; CHECK: test_simple: +; CHECK-LABEL: test_simple: %valadd = add i128 %a, %b ; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2 @@ -16,7 +16,7 @@ define i128 @test_simple(i128 %a, i128 %b, i128 %c) { } define i128 @test_imm(i128 %a) { -; CHECK: test_imm: +; CHECK-LABEL: test_imm: %val = add i128 %a, 12 ; CHECK: adds x0, x0, #12 @@ -27,7 +27,7 @@ define i128 @test_imm(i128 %a) { } define i128 @test_shifted(i128 %a, i128 %b) { -; CHECK: test_shifted: +; CHECK-LABEL: test_shifted: %rhs = shl i128 %b, 45 @@ -40,7 +40,7 @@ define i128 @test_shifted(i128 %a, i128 %b) { } define i128 @test_extended(i128 %a, i16 %b) { -; CHECK: test_extended: +; CHECK-LABEL: test_extended: %ext = sext i16 %b to i128 %rhs = shl i128 %ext, 3 diff --git a/test/CodeGen/AArch64/addsub-shifted.ll b/test/CodeGen/AArch64/addsub-shifted.ll index f2c74f6952..269c1e8143 100644 --- a/test/CodeGen/AArch64/addsub-shifted.ll +++ b/test/CodeGen/AArch64/addsub-shifted.ll @@ -4,7 +4,7 @@ @var64 = global i64 0 define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { -; CHECK: test_lsl_arith: +; CHECK-LABEL: test_lsl_arith: %rhs1 = load volatile i32* @var32 %shift1 = shl i32 %rhs1, 18 @@ -73,7 +73,7 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { } define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { -; CHECK: test_lsr_arith: +; CHECK-LABEL: test_lsr_arith: %shift1 = lshr i32 %rhs32, 18 %val1 = add i32 %lhs32, %shift1 @@ -132,7 +132,7 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { } define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { -; CHECK: test_asr_arith: +; CHECK-LABEL: test_asr_arith: %shift1 = ashr i32 %rhs32, 18 %val1 = add i32 %lhs32, %shift1 @@ -191,7 +191,7 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { } define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { -; CHECK: test_cmp: +; CHECK-LABEL: test_cmp: %shift1 = shl i32 %rhs32, 13 %tst1 = icmp uge i32 %lhs32, %shift1 @@ -237,7 +237,7 @@ end: } define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { -; CHECK: test_cmn: +; CHECK-LABEL: test_cmn: %shift1 = shl i32 %rhs32, 13 %val1 = sub i32 0, %shift1 diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll index 5148807163..c0e1cc95f2 100644 --- a/test/CodeGen/AArch64/addsub.ll +++ b/test/CodeGen/AArch64/addsub.ll @@ -76,7 +76,7 @@ define void @sub_med() { } define void @testing() { -; CHECK: testing: +; CHECK-LABEL: testing: %val = load i32* @var_i32 ; CHECK: cmp {{w[0-9]+}}, #4095 diff --git a/test/CodeGen/AArch64/addsub_ext.ll b/test/CodeGen/AArch64/addsub_ext.ll index 2dd16626ea..0bda0f9191 100644 --- a/test/CodeGen/AArch64/addsub_ext.ll +++ b/test/CodeGen/AArch64/addsub_ext.ll @@ -186,4 +186,4 @@ define void @addsub_i32rhs() { ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2 ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll index c62edf6503..a84217f86f 100644 --- a/test/CodeGen/AArch64/alloca.ll +++ b/test/CodeGen/AArch64/alloca.ll @@ -3,7 +3,7 @@ declare void @use_addr(i8*) define void @test_simple_alloca(i64 %n) { -; CHECK: test_simple_alloca: +; CHECK-LABEL: test_simple_alloca: %buf = alloca i8, i64 %n ; Make sure we align the stack change to 16 bytes: @@ -30,7 +30,7 @@ define void @test_simple_alloca(i64 %n) { declare void @use_addr_loc(i8*, i64*) define i64 @test_alloca_with_local(i64 %n) { -; CHECK: test_alloca_with_local: +; CHECK-LABEL: test_alloca_with_local: ; CHECK: sub sp, sp, #32 ; CHECK: stp x29, x30, [sp, #16] @@ -66,7 +66,7 @@ define i64 @test_alloca_with_local(i64 %n) { } define void @test_variadic_alloca(i64 %n, ...) { -; CHECK: test_variadic_alloca: +; CHECK-LABEL: test_variadic_alloca: ; CHECK: sub sp, sp, #208 ; CHECK: stp x29, x30, [sp, #192] @@ -89,7 +89,7 @@ define void @test_variadic_alloca(i64 %n, ...) { } define void @test_alloca_large_frame(i64 %n) { -; CHECK: test_alloca_large_frame: +; CHECK-LABEL: test_alloca_large_frame: ; CHECK: sub sp, sp, #496 ; CHECK: stp x29, x30, [sp, #480] diff --git a/test/CodeGen/AArch64/analyze-branch.ll b/test/CodeGen/AArch64/analyze-branch.ll index e10bbb0f86..36bc2e00d2 100644 --- a/test/CodeGen/AArch64/analyze-branch.ll +++ b/test/CodeGen/AArch64/analyze-branch.ll @@ -11,7 +11,7 @@ declare void @test_false() !1 = metadata !{metadata !"branch_weights", i32 4, i32 64} define void @test_Bcc_fallthrough_taken(i32 %in) nounwind { -; CHECK: test_Bcc_fallthrough_taken: +; CHECK-LABEL: test_Bcc_fallthrough_taken: %tst = icmp eq i32 %in, 42 br i1 %tst, label %true, label %false, !prof !0 @@ -34,7 +34,7 @@ false: } define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind { -; CHECK: test_Bcc_fallthrough_nottaken: +; CHECK-LABEL: test_Bcc_fallthrough_nottaken: %tst = icmp eq i32 %in, 42 br i1 %tst, label %true, label %false, !prof !1 @@ -57,7 +57,7 @@ false: } define void @test_CBZ_fallthrough_taken(i32 %in) nounwind { -; CHECK: test_CBZ_fallthrough_taken: +; CHECK-LABEL: test_CBZ_fallthrough_taken: %tst = icmp eq i32 %in, 0 br i1 %tst, label %true, label %false, !prof !0 @@ -78,7 +78,7 @@ false: } define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind { -; CHECK: test_CBZ_fallthrough_nottaken: +; CHECK-LABEL: test_CBZ_fallthrough_nottaken: %tst = icmp eq i64 %in, 0 br i1 %tst, label %true, label %false, !prof !1 @@ -99,7 +99,7 @@ false: } define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind { -; CHECK: test_CBNZ_fallthrough_taken: +; CHECK-LABEL: test_CBNZ_fallthrough_taken: %tst = icmp ne i32 %in, 0 br i1 %tst, label %true, label %false, !prof !0 @@ -120,7 +120,7 @@ false: } define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind { -; CHECK: test_CBNZ_fallthrough_nottaken: +; CHECK-LABEL: test_CBNZ_fallthrough_nottaken: %tst = icmp ne i64 %in, 0 br i1 %tst, label %true, label %false, !prof !1 @@ -141,7 +141,7 @@ false: } define void @test_TBZ_fallthrough_taken(i32 %in) nounwind { -; CHECK: test_TBZ_fallthrough_taken: +; CHECK-LABEL: test_TBZ_fallthrough_taken: %bit = and i32 %in, 32768 %tst = icmp eq i32 %bit, 0 br i1 %tst, label %true, label %false, !prof !0 @@ -163,7 +163,7 @@ false: } define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind { -; CHECK: test_TBZ_fallthrough_nottaken: +; CHECK-LABEL: test_TBZ_fallthrough_nottaken: %bit = and i64 %in, 32768 %tst = icmp eq i64 %bit, 0 br i1 %tst, label %true, label %false, !prof !1 @@ -186,7 +186,7 @@ false: define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind { -; CHECK: test_TBNZ_fallthrough_taken: +; CHECK-LABEL: test_TBNZ_fallthrough_taken: %bit = and i32 %in, 32768 %tst = icmp ne i32 %bit, 0 br i1 %tst, label %true, label %false, !prof !0 @@ -208,7 +208,7 @@ false: } define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind { -; CHECK: test_TBNZ_fallthrough_nottaken: +; CHECK-LABEL: test_TBNZ_fallthrough_nottaken: %bit = and i64 %in, 32768 %tst = icmp ne i64 %bit, 0 br i1 %tst, label %true, label %false, !prof !1 diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index 5e87f21a21..de84ff46ec 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -6,7 +6,7 @@ @var64 = global i64 0 define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_add_i8: +; CHECK-LABEL: test_atomic_load_add_i8: %old = atomicrmw add i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -26,7 +26,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_add_i16: +; CHECK-LABEL: test_atomic_load_add_i16: %old = atomicrmw add i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -46,7 +46,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_add_i32: +; CHECK-LABEL: test_atomic_load_add_i32: %old = atomicrmw add i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -66,7 +66,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_add_i64: +; CHECK-LABEL: test_atomic_load_add_i64: %old = atomicrmw add i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -86,7 +86,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_sub_i8: +; CHECK-LABEL: test_atomic_load_sub_i8: %old = atomicrmw sub i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -106,7 +106,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_sub_i16: +; CHECK-LABEL: test_atomic_load_sub_i16: %old = atomicrmw sub i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -126,7 +126,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_sub_i32: +; CHECK-LABEL: test_atomic_load_sub_i32: %old = atomicrmw sub i32* @var32, i32 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -146,7 +146,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_sub_i64: +; CHECK-LABEL: test_atomic_load_sub_i64: %old = atomicrmw sub i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -166,7 +166,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_and_i8: +; CHECK-LABEL: test_atomic_load_and_i8: %old = atomicrmw and i8* @var8, i8 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -186,7 +186,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_and_i16: +; CHECK-LABEL: test_atomic_load_and_i16: %old = atomicrmw and i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -206,7 +206,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_and_i32: +; CHECK-LABEL: test_atomic_load_and_i32: %old = atomicrmw and i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -226,7 +226,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_and_i64: +; CHECK-LABEL: test_atomic_load_and_i64: %old = atomicrmw and i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -246,7 +246,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_or_i8: +; CHECK-LABEL: test_atomic_load_or_i8: %old = atomicrmw or i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -266,7 +266,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_or_i16: +; CHECK-LABEL: test_atomic_load_or_i16: %old = atomicrmw or i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -286,7 +286,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_or_i32: +; CHECK-LABEL: test_atomic_load_or_i32: %old = atomicrmw or i32* @var32, i32 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -306,7 +306,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_or_i64: +; CHECK-LABEL: test_atomic_load_or_i64: %old = atomicrmw or i64* @var64, i64 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -326,7 +326,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_xor_i8: +; CHECK-LABEL: test_atomic_load_xor_i8: %old = atomicrmw xor i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -346,7 +346,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_xor_i16: +; CHECK-LABEL: test_atomic_load_xor_i16: %old = atomicrmw xor i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -366,7 +366,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_xor_i32: +; CHECK-LABEL: test_atomic_load_xor_i32: %old = atomicrmw xor i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -386,7 +386,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_xor_i64: +; CHECK-LABEL: test_atomic_load_xor_i64: %old = atomicrmw xor i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -406,7 +406,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i8: +; CHECK-LABEL: test_atomic_load_xchg_i8: %old = atomicrmw xchg i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -425,7 +425,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i16: +; CHECK-LABEL: test_atomic_load_xchg_i16: %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -444,7 +444,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i32: +; CHECK-LABEL: test_atomic_load_xchg_i32: %old = atomicrmw xchg i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -463,7 +463,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i64: +; CHECK-LABEL: test_atomic_load_xchg_i64: %old = atomicrmw xchg i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -483,7 +483,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_min_i8: +; CHECK-LABEL: test_atomic_load_min_i8: %old = atomicrmw min i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -504,7 +504,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_min_i16: +; CHECK-LABEL: test_atomic_load_min_i16: %old = atomicrmw min i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -525,7 +525,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_min_i32: +; CHECK-LABEL: test_atomic_load_min_i32: %old = atomicrmw min i32* @var32, i32 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -546,7 +546,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_min_i64: +; CHECK-LABEL: test_atomic_load_min_i64: %old = atomicrmw min i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -567,7 +567,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_max_i8: +; CHECK-LABEL: test_atomic_load_max_i8: %old = atomicrmw max i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -588,7 +588,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_max_i16: +; CHECK-LABEL: test_atomic_load_max_i16: %old = atomicrmw max i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -609,7 +609,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_max_i32: +; CHECK-LABEL: test_atomic_load_max_i32: %old = atomicrmw max i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -630,7 +630,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_max_i64: +; CHECK-LABEL: test_atomic_load_max_i64: %old = atomicrmw max i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -651,7 +651,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_umin_i8: +; CHECK-LABEL: test_atomic_load_umin_i8: %old = atomicrmw umin i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -672,7 +672,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_umin_i16: +; CHECK-LABEL: test_atomic_load_umin_i16: %old = atomicrmw umin i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -693,7 +693,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_umin_i32: +; CHECK-LABEL: test_atomic_load_umin_i32: %old = atomicrmw umin i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -714,7 +714,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_umin_i64: +; CHECK-LABEL: test_atomic_load_umin_i64: %old = atomicrmw umin i64* @var64, i64 %offset acq_rel ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -735,7 +735,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_umax_i8: +; CHECK-LABEL: test_atomic_load_umax_i8: %old = atomicrmw umax i8* @var8, i8 %offset acq_rel ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -756,7 +756,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_umax_i16: +; CHECK-LABEL: test_atomic_load_umax_i16: %old = atomicrmw umax i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -777,7 +777,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_umax_i32: +; CHECK-LABEL: test_atomic_load_umax_i32: %old = atomicrmw umax i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -798,7 +798,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_umax_i64: +; CHECK-LABEL: test_atomic_load_umax_i64: %old = atomicrmw umax i64* @var64, i64 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -819,7 +819,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { } define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i8: +; CHECK-LABEL: test_atomic_cmpxchg_i8: %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -841,7 +841,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { } define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i16: +; CHECK-LABEL: test_atomic_cmpxchg_i16: %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -863,7 +863,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { } define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i32: +; CHECK-LABEL: test_atomic_cmpxchg_i32: %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -885,7 +885,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { } define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i64: +; CHECK-LABEL: test_atomic_cmpxchg_i64: %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -907,7 +907,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { } define i8 @test_atomic_load_monotonic_i8() nounwind { -; CHECK: test_atomic_load_monotonic_i8: +; CHECK-LABEL: test_atomic_load_monotonic_i8: %val = load atomic i8* @var8 monotonic, align 1 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 @@ -918,7 +918,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind { } define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { -; CHECK: test_atomic_load_monotonic_regoff_i8: +; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* @@ -931,7 +931,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { } define i8 @test_atomic_load_acquire_i8() nounwind { -; CHECK: test_atomic_load_acquire_i8: +; CHECK-LABEL: test_atomic_load_acquire_i8: %val = load atomic i8* @var8 acquire, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -944,7 +944,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind { } define i8 @test_atomic_load_seq_cst_i8() nounwind { -; CHECK: test_atomic_load_seq_cst_i8: +; CHECK-LABEL: test_atomic_load_seq_cst_i8: %val = load atomic i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 @@ -957,7 +957,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind { } define i16 @test_atomic_load_monotonic_i16() nounwind { -; CHECK: test_atomic_load_monotonic_i16: +; CHECK-LABEL: test_atomic_load_monotonic_i16: %val = load atomic i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 @@ -969,7 +969,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind { } define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind { -; CHECK: test_atomic_load_monotonic_regoff_i32: +; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* @@ -982,7 +982,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind } define i64 @test_atomic_load_seq_cst_i64() nounwind { -; CHECK: test_atomic_load_seq_cst_i64: +; CHECK-LABEL: test_atomic_load_seq_cst_i64: %val = load atomic i64* @var64 seq_cst, align 8 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 @@ -995,7 +995,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind { } define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { -; CHECK: test_atomic_store_monotonic_i8: +; CHECK-LABEL: test_atomic_store_monotonic_i8: store atomic i8 %val, i8* @var8 monotonic, align 1 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 ; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8] @@ -1004,7 +1004,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { } define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind { -; CHECK: test_atomic_store_monotonic_regoff_i8: +; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* @@ -1015,7 +1015,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) ret void } define void @test_atomic_store_release_i8(i8 %val) nounwind { -; CHECK: test_atomic_store_release_i8: +; CHECK-LABEL: test_atomic_store_release_i8: store atomic i8 %val, i8* @var8 release, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 @@ -1028,7 +1028,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind { } define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { -; CHECK: test_atomic_store_seq_cst_i8: +; CHECK-LABEL: test_atomic_store_seq_cst_i8: store atomic i8 %val, i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 @@ -1042,7 +1042,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { } define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { -; CHECK: test_atomic_store_monotonic_i16: +; CHECK-LABEL: test_atomic_store_monotonic_i16: store atomic i16 %val, i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 @@ -1053,7 +1053,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { } define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind { -; CHECK: test_atomic_store_monotonic_regoff_i32: +; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* @@ -1067,7 +1067,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va } define void @test_atomic_store_release_i64(i64 %val) nounwind { -; CHECK: test_atomic_store_release_i64: +; CHECK-LABEL: test_atomic_store_release_i64: store atomic i64 %val, i64* @var64 release, align 8 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll index 5343cc793e..1f0b282641 100644 --- a/test/CodeGen/AArch64/basic-pic.ll +++ b/test/CodeGen/AArch64/basic-pic.ll @@ -67,4 +67,4 @@ define void()* @get_func() { ; it can relax it because it knows where get_func is. It can't! ; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func ; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/bitfield-insert-0.ll b/test/CodeGen/AArch64/bitfield-insert-0.ll index d1191f6aaa..37a18b7fb6 100644 --- a/test/CodeGen/AArch64/bitfield-insert-0.ll +++ b/test/CodeGen/AArch64/bitfield-insert-0.ll @@ -16,4 +16,4 @@ define void @test_bfi0(i32* %existing, i32* %new) { store volatile i32 %combined, i32* %existing ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll index 3e871b9a6d..fe2aedb45a 100644 --- a/test/CodeGen/AArch64/bitfield-insert.ll +++ b/test/CodeGen/AArch64/bitfield-insert.ll @@ -25,7 +25,7 @@ entry: } define void @test_whole32(i32* %existing, i32* %new) { -; CHECK: test_whole32: +; CHECK-LABEL: test_whole32: ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5 %oldval = load volatile i32* %existing @@ -42,7 +42,7 @@ define void @test_whole32(i32* %existing, i32* %new) { } define void @test_whole64(i64* %existing, i64* %new) { -; CHECK: test_whole64: +; CHECK-LABEL: test_whole64: ; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14 ; CHECK-NOT: and ; CHECK: ret @@ -61,7 +61,7 @@ define void @test_whole64(i64* %existing, i64* %new) { } define void @test_whole32_from64(i64* %existing, i64* %new) { -; CHECK: test_whole32_from64: +; CHECK-LABEL: test_whole32_from64: ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16 ; CHECK-NOT: and ; CHECK: ret @@ -79,7 +79,7 @@ define void @test_whole32_from64(i64* %existing, i64* %new) { } define void @test_32bit_masked(i32 *%existing, i32 *%new) { -; CHECK: test_32bit_masked: +; CHECK-LABEL: test_32bit_masked: ; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4 ; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff @@ -97,7 +97,7 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) { } define void @test_64bit_masked(i64 *%existing, i64 *%new) { -; CHECK: test_64bit_masked: +; CHECK-LABEL: test_64bit_masked: ; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8 ; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000 @@ -116,7 +116,7 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) { ; Mask is too complicated for literal ANDwwi, make sure other avenues are tried. define void @test_32bit_complexmask(i32 *%existing, i32 *%new) { -; CHECK: test_32bit_complexmask: +; CHECK-LABEL: test_32bit_complexmask: ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4 ; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -135,7 +135,7 @@ define void @test_32bit_complexmask(i32 *%existing, i32 *%new) { ; Neither mask is is a contiguous set of 1s. BFI can't be used define void @test_32bit_badmask(i32 *%existing, i32 *%new) { -; CHECK: test_32bit_badmask: +; CHECK-LABEL: test_32bit_badmask: ; CHECK-NOT: bfi ; CHECK: ret @@ -154,7 +154,7 @@ define void @test_32bit_badmask(i32 *%existing, i32 *%new) { ; Ditto define void @test_64bit_badmask(i64 *%existing, i64 *%new) { -; CHECK: test_64bit_badmask: +; CHECK-LABEL: test_64bit_badmask: ; CHECK-NOT: bfi ; CHECK: ret @@ -174,7 +174,7 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) { ; Bitfield insert where there's a left-over shr needed at the beginning ; (e.g. result of str.bf1 = str.bf2) define void @test_32bit_with_shr(i32* %existing, i32* %new) { -; CHECK: test_32bit_with_shr: +; CHECK-LABEL: test_32bit_with_shr: %oldval = load volatile i32* %existing %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff diff --git a/test/CodeGen/AArch64/bitfield.ll b/test/CodeGen/AArch64/bitfield.ll index 36d337ef05..1c84f5d578 100644 --- a/test/CodeGen/AArch64/bitfield.ll +++ b/test/CodeGen/AArch64/bitfield.ll @@ -5,7 +5,7 @@ @var64 = global i64 0 define void @test_extendb(i8 %var) { -; CHECK: test_extendb: +; CHECK-LABEL: test_extendb: %sxt32 = sext i8 %var to i32 store volatile i32 %sxt32, i32* @var32 @@ -29,7 +29,7 @@ define void @test_extendb(i8 %var) { } define void @test_extendh(i16 %var) { -; CHECK: test_extendh: +; CHECK-LABEL: test_extendh: %sxt32 = sext i16 %var to i32 store volatile i32 %sxt32, i32* @var32 @@ -53,7 +53,7 @@ define void @test_extendh(i16 %var) { } define void @test_extendw(i32 %var) { -; CHECK: test_extendw: +; CHECK-LABEL: test_extendw: %sxt64 = sext i32 %var to i64 store volatile i64 %sxt64, i64* @var64 @@ -66,7 +66,7 @@ define void @test_extendw(i32 %var) { } define void @test_shifts(i32 %val32, i64 %val64) { -; CHECK: test_shifts: +; CHECK-LABEL: test_shifts: %shift1 = ashr i32 %val32, 31 store volatile i32 %shift1, i32* @var32 @@ -114,7 +114,7 @@ define void @test_shifts(i32 %val32, i64 %val64) { ; LLVM can produce in-register extensions taking place entirely with ; 64-bit registers too. define void @test_sext_inreg_64(i64 %in) { -; CHECK: test_sext_inreg_64: +; CHECK-LABEL: test_sext_inreg_64: ; i1 doesn't have an official alias, but crops up and is handled by ; the bitfield ops. @@ -143,7 +143,7 @@ define void @test_sext_inreg_64(i64 %in) { ; These instructions don't actually select to official bitfield ; operations, but it's important that we select them somehow: define void @test_zext_inreg_64(i64 %in) { -; CHECK: test_zext_inreg_64: +; CHECK-LABEL: test_zext_inreg_64: %trunc_i8 = trunc i64 %in to i8 %zext_i8 = zext i8 %trunc_i8 to i64 @@ -164,7 +164,7 @@ define void @test_zext_inreg_64(i64 %in) { } define i64 @test_sext_inreg_from_32(i32 %in) { -; CHECK: test_sext_inreg_from_32: +; CHECK-LABEL: test_sext_inreg_from_32: %small = trunc i32 %in to i1 %ext = sext i1 %small to i64 @@ -178,7 +178,7 @@ define i64 @test_sext_inreg_from_32(i32 %in) { define i32 @test_ubfx32(i32* %addr) { -; CHECK: test_ubfx32: +; CHECK-LABEL: test_ubfx32: ; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3 %fields = load i32* %addr @@ -188,7 +188,7 @@ define i32 @test_ubfx32(i32* %addr) { } define i64 @test_ubfx64(i64* %addr) { -; CHECK: test_ubfx64: +; CHECK-LABEL: test_ubfx64: ; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10 %fields = load i64* %addr @@ -198,7 +198,7 @@ define i64 @test_ubfx64(i64* %addr) { } define i32 @test_sbfx32(i32* %addr) { -; CHECK: test_sbfx32: +; CHECK-LABEL: test_sbfx32: ; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3 %fields = load i32* %addr @@ -208,7 +208,7 @@ define i32 @test_sbfx32(i32* %addr) { } define i64 @test_sbfx64(i64* %addr) { -; CHECK: test_sbfx64: +; CHECK-LABEL: test_sbfx64: ; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63 %fields = load i64* %addr diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll index 5e85057a3c..8cda431b8e 100644 --- a/test/CodeGen/AArch64/blockaddress.ll +++ b/test/CodeGen/AArch64/blockaddress.ll @@ -4,7 +4,7 @@ @addr = global i8* null define void @test_blockaddress() { -; CHECK: test_blockaddress: +; CHECK-LABEL: test_blockaddress: store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr %val = load volatile i8** @addr indirectbr i8* %val, [label %block] diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll index 4213110497..62f4cd58d4 100644 --- a/test/CodeGen/AArch64/compare-branch.ll +++ b/test/CodeGen/AArch64/compare-branch.ll @@ -35,4 +35,4 @@ test5: end: ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll index 3051cf53fd..48c50a134b 100644 --- a/test/CodeGen/AArch64/cond-sel.ll +++ b/test/CodeGen/AArch64/cond-sel.ll @@ -4,7 +4,7 @@ @var64 = global i64 0 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { -; CHECK: test_csel: +; CHECK-LABEL: test_csel: %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, i32 42, i32 52 @@ -26,7 +26,7 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { } define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) { -; CHECK: test_floatcsel: +; CHECK-LABEL: test_floatcsel: %tst1 = fcmp one float %lhs32, %rhs32 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}} @@ -53,7 +53,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) { -; CHECK: test_csinc: +; CHECK-LABEL: test_csinc: ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). %tst1 = icmp ugt i32 %lhs32, %rhs32 @@ -93,7 +93,7 @@ define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) { } define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) { -; CHECK: test_csinv: +; CHECK-LABEL: test_csinv: ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). %tst1 = icmp ugt i32 %lhs32, %rhs32 @@ -133,7 +133,7 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) { } define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) { -; CHECK: test_csneg: +; CHECK-LABEL: test_csneg: ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). %tst1 = icmp ugt i32 %lhs32, %rhs32 @@ -173,7 +173,7 @@ define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) { } define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) { -; CHECK: test_cset: +; CHECK-LABEL: test_cset: ; N.b. code is not optimal here (32-bit csinc would be better) but ; incoming DAG is too complex @@ -194,7 +194,7 @@ define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) { } define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) { -; CHECK: test_csetm: +; CHECK-LABEL: test_csetm: %tst1 = icmp eq i32 %lhs, %rhs %val1 = sext i1 %tst1 to i32 diff --git a/test/CodeGen/AArch64/directcond.ll b/test/CodeGen/AArch64/directcond.ll index f5d57593bf..13f032dbec 100644 --- a/test/CodeGen/AArch64/directcond.ll +++ b/test/CodeGen/AArch64/directcond.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) { -; CHECK: test_select_i32: +; CHECK-LABEL: test_select_i32: %val = select i1 %bit, i32 %a, i32 %b ; CHECK: movz [[ONE:w[0-9]+]], #1 ; CHECK: tst w0, [[ONE]] @@ -11,7 +11,7 @@ define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) { } define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) { -; CHECK: test_select_i64: +; CHECK-LABEL: test_select_i64: %val = select i1 %bit, i64 %a, i64 %b ; CHECK: movz [[ONE:w[0-9]+]], #1 ; CHECK: tst w0, [[ONE]] @@ -21,7 +21,7 @@ define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) { } define float @test_select_float(i1 %bit, float %a, float %b) { -; CHECK: test_select_float: +; CHECK-LABEL: test_select_float: %val = select i1 %bit, float %a, float %b ; CHECK: movz [[ONE:w[0-9]+]], #1 ; CHECK: tst w0, [[ONE]] @@ -31,7 +31,7 @@ define float @test_select_float(i1 %bit, float %a, float %b) { } define double @test_select_double(i1 %bit, double %a, double %b) { -; CHECK: test_select_double: +; CHECK-LABEL: test_select_double: %val = select i1 %bit, double %a, double %b ; CHECK: movz [[ONE:w[0-9]+]], #1 ; CHECK: tst w0, [[ONE]] @@ -41,7 +41,7 @@ define double @test_select_double(i1 %bit, double %a, double %b) { } define i32 @test_brcond(i1 %bit) { -; CHECK: test_brcond: +; CHECK-LABEL: test_brcond: br i1 %bit, label %true, label %false ; CHECK: tbz {{w[0-9]+}}, #0, .LBB diff --git a/test/CodeGen/AArch64/dp-3source.ll b/test/CodeGen/AArch64/dp-3source.ll index c40d3933b4..81d9e15532 100644 --- a/test/CodeGen/AArch64/dp-3source.ll +++ b/test/CodeGen/AArch64/dp-3source.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) { -; CHECK: test_madd32: +; CHECK-LABEL: test_madd32: %mid = mul i32 %val1, %val2 %res = add i32 %val0, %mid ; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -9,7 +9,7 @@ define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) { } define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) { -; CHECK: test_madd64: +; CHECK-LABEL: test_madd64: %mid = mul i64 %val1, %val2 %res = add i64 %val0, %mid ; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} @@ -17,7 +17,7 @@ define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) { } define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) { -; CHECK: test_msub32: +; CHECK-LABEL: test_msub32: %mid = mul i32 %val1, %val2 %res = sub i32 %val0, %mid ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -25,7 +25,7 @@ define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) { } define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) { -; CHECK: test_msub64: +; CHECK-LABEL: test_msub64: %mid = mul i64 %val1, %val2 %res = sub i64 %val0, %mid ; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} @@ -33,7 +33,7 @@ define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) { } define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) { -; CHECK: test_smaddl: +; CHECK-LABEL: test_smaddl: %ext1 = sext i32 %val1 to i64 %ext2 = sext i32 %val2 to i64 %prod = mul i64 %ext1, %ext2 @@ -43,7 +43,7 @@ define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) { } define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) { -; CHECK: test_smsubl: +; CHECK-LABEL: test_smsubl: %ext1 = sext i32 %val1 to i64 %ext2 = sext i32 %val2 to i64 %prod = mul i64 %ext1, %ext2 @@ -53,7 +53,7 @@ define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) { } define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) { -; CHECK: test_umaddl: +; CHECK-LABEL: test_umaddl: %ext1 = zext i32 %val1 to i64 %ext2 = zext i32 %val2 to i64 %prod = mul i64 %ext1, %ext2 @@ -63,7 +63,7 @@ define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) { } define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) { -; CHECK: test_umsubl: +; CHECK-LABEL: test_umsubl: %ext1 = zext i32 %val1 to i64 %ext2 = zext i32 %val2 to i64 %prod = mul i64 %ext1, %ext2 @@ -73,7 +73,7 @@ define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) { } define i64 @test_smulh(i64 %lhs, i64 %rhs) { -; CHECK: test_smulh: +; CHECK-LABEL: test_smulh: %ext1 = sext i64 %lhs to i128 %ext2 = sext i64 %rhs to i128 %res = mul i128 %ext1, %ext2 @@ -84,7 +84,7 @@ define i64 @test_smulh(i64 %lhs, i64 %rhs) { } define i64 @test_umulh(i64 %lhs, i64 %rhs) { -; CHECK: test_umulh: +; CHECK-LABEL: test_umulh: %ext1 = zext i64 %lhs to i128 %ext2 = zext i64 %rhs to i128 %res = mul i128 %ext1, %ext2 @@ -95,21 +95,21 @@ define i64 @test_umulh(i64 %lhs, i64 %rhs) { } define i32 @test_mul32(i32 %lhs, i32 %rhs) { -; CHECK: test_mul32: +; CHECK-LABEL: test_mul32: %res = mul i32 %lhs, %rhs ; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ret i32 %res } define i64 @test_mul64(i64 %lhs, i64 %rhs) { -; CHECK: test_mul64: +; CHECK-LABEL: test_mul64: %res = mul i64 %lhs, %rhs ; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} ret i64 %res } define i32 @test_mneg32(i32 %lhs, i32 %rhs) { -; CHECK: test_mneg32: +; CHECK-LABEL: test_mneg32: %prod = mul i32 %lhs, %rhs %res = sub i32 0, %prod ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -117,7 +117,7 @@ define i32 @test_mneg32(i32 %lhs, i32 %rhs) { } define i64 @test_mneg64(i64 %lhs, i64 %rhs) { -; CHECK: test_mneg64: +; CHECK-LABEL: test_mneg64: %prod = mul i64 %lhs, %rhs %res = sub i64 0, %prod ; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} @@ -125,7 +125,7 @@ define i64 @test_mneg64(i64 %lhs, i64 %rhs) { } define i64 @test_smull(i32 %lhs, i32 %rhs) { -; CHECK: test_smull: +; CHECK-LABEL: test_smull: %ext1 = sext i32 %lhs to i64 %ext2 = sext i32 %rhs to i64 %res = mul i64 %ext1, %ext2 @@ -134,7 +134,7 @@ define i64 @test_smull(i32 %lhs, i32 %rhs) { } define i64 @test_umull(i32 %lhs, i32 %rhs) { -; CHECK: test_umull: +; CHECK-LABEL: test_umull: %ext1 = zext i32 %lhs to i64 %ext2 = zext i32 %rhs to i64 %res = mul i64 %ext1, %ext2 @@ -143,7 +143,7 @@ define i64 @test_umull(i32 %lhs, i32 %rhs) { } define i64 @test_smnegl(i32 %lhs, i32 %rhs) { -; CHECK: test_smnegl: +; CHECK-LABEL: test_smnegl: %ext1 = sext i32 %lhs to i64 %ext2 = sext i32 %rhs to i64 %prod = mul i64 %ext1, %ext2 @@ -153,7 +153,7 @@ define i64 @test_smnegl(i32 %lhs, i32 %rhs) { } define i64 @test_umnegl(i32 %lhs, i32 %rhs) { -; CHECK: test_umnegl: +; CHECK-LABEL: test_umnegl: %ext1 = zext i32 %lhs to i64 %ext2 = zext i32 %rhs to i64 %prod = mul i64 %ext1, %ext2 diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll index 4c740f6b86..a5ebc2f33c 100644 --- a/test/CodeGen/AArch64/dp2.ll +++ b/test/CodeGen/AArch64/dp2.ll @@ -139,7 +139,7 @@ define void @udiv_i32() { ; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2)) ; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions. define i32 @test_lsl32() { -; CHECK: test_lsl32: +; CHECK-LABEL: test_lsl32: %val = load i32* @var32_0 %ret = shl i32 1, %val @@ -149,7 +149,7 @@ define i32 @test_lsl32() { } define i32 @test_lsr32() { -; CHECK: test_lsr32: +; CHECK-LABEL: test_lsr32: %val = load i32* @var32_0 %ret = lshr i32 1, %val @@ -159,7 +159,7 @@ define i32 @test_lsr32() { } define i32 @test_asr32(i32 %in) { -; CHECK: test_asr32: +; CHECK-LABEL: test_asr32: %val = load i32* @var32_0 %ret = ashr i32 %in, %val diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll index bc0acc2533..322b3f4522 100644 --- a/test/CodeGen/AArch64/extern-weak.ll +++ b/test/CodeGen/AArch64/extern-weak.ll @@ -51,4 +51,4 @@ define i32* @wibble() { ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/fcmp.ll b/test/CodeGen/AArch64/fcmp.ll index ad4a903c9b..a9518eabb7 100644 --- a/test/CodeGen/AArch64/fcmp.ll +++ b/test/CodeGen/AArch64/fcmp.ll @@ -3,7 +3,7 @@ declare void @bar(i32) define void @test_float(float %a, float %b) { -; CHECK: test_float: +; CHECK-LABEL: test_float: %tst1 = fcmp oeq float %a, %b br i1 %tst1, label %end, label %t2 @@ -42,7 +42,7 @@ end: } define void @test_double(double %a, double %b) { -; CHECK: test_double: +; CHECK-LABEL: test_double: %tst1 = fcmp oeq double %a, %b br i1 %tst1, label %end, label %t2 diff --git a/test/CodeGen/AArch64/fcvt-fixed.ll b/test/CodeGen/AArch64/fcvt-fixed.ll index 0f7b95b2a4..9d66da4943 100644 --- a/test/CodeGen/AArch64/fcvt-fixed.ll +++ b/test/CodeGen/AArch64/fcvt-fixed.ll @@ -4,7 +4,7 @@ @var64 = global i64 0 define void @test_fcvtzs(float %flt, double %dbl) { -; CHECK: test_fcvtzs: +; CHECK-LABEL: test_fcvtzs: %fix1 = fmul float %flt, 128.0 %cvt1 = fptosi float %fix1 to i32 @@ -50,7 +50,7 @@ define void @test_fcvtzs(float %flt, double %dbl) { } define void @test_fcvtzu(float %flt, double %dbl) { -; CHECK: test_fcvtzu: +; CHECK-LABEL: test_fcvtzu: %fix1 = fmul float %flt, 128.0 %cvt1 = fptoui float %fix1 to i32 @@ -99,7 +99,7 @@ define void @test_fcvtzu(float %flt, double %dbl) { @vardouble = global double 0.0 define void @test_scvtf(i32 %int, i64 %long) { -; CHECK: test_scvtf: +; CHECK-LABEL: test_scvtf: %cvt1 = sitofp i32 %int to float %fix1 = fdiv float %cvt1, 128.0 @@ -145,7 +145,7 @@ define void @test_scvtf(i32 %int, i64 %long) { } define void @test_ucvtf(i32 %int, i64 %long) { -; CHECK: test_ucvtf: +; CHECK-LABEL: test_ucvtf: %cvt1 = uitofp i32 %int to float %fix1 = fdiv float %cvt1, 128.0 diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll index c771d683a9..9afcfc4a8b 100644 --- a/test/CodeGen/AArch64/fcvt-int.ll +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s define i32 @test_floattoi32(float %in) { -; CHECK: test_floattoi32: +; CHECK-LABEL: test_floattoi32: %signed = fptosi float %in to i32 %unsigned = fptoui float %in to i32 @@ -16,7 +16,7 @@ define i32 @test_floattoi32(float %in) { } define i32 @test_doubletoi32(double %in) { -; CHECK: test_doubletoi32: +; CHECK-LABEL: test_doubletoi32: %signed = fptosi double %in to i32 %unsigned = fptoui double %in to i32 @@ -31,7 +31,7 @@ define i32 @test_doubletoi32(double %in) { } define i64 @test_floattoi64(float %in) { -; CHECK: test_floattoi64: +; CHECK-LABEL: test_floattoi64: %signed = fptosi float %in to i64 %unsigned = fptoui float %in to i64 @@ -46,7 +46,7 @@ define i64 @test_floattoi64(float %in) { } define i64 @test_doubletoi64(double %in) { -; CHECK: test_doubletoi64: +; CHECK-LABEL: test_doubletoi64: %signed = fptosi double %in to i64 %unsigned = fptoui double %in to i64 @@ -61,7 +61,7 @@ define i64 @test_doubletoi64(double %in) { } define float @test_i32tofloat(i32 %in) { -; CHECK: test_i32tofloat: +; CHECK-LABEL: test_i32tofloat: %signed = sitofp i32 %in to float %unsigned = uitofp i32 %in to float @@ -75,7 +75,7 @@ define float @test_i32tofloat(i32 %in) { } define double @test_i32todouble(i32 %in) { -; CHECK: test_i32todouble: +; CHECK-LABEL: test_i32todouble: %signed = sitofp i32 %in to double %unsigned = uitofp i32 %in to double @@ -89,7 +89,7 @@ define double @test_i32todouble(i32 %in) { } define float @test_i64tofloat(i64 %in) { -; CHECK: test_i64tofloat: +; CHECK-LABEL: test_i64tofloat: %signed = sitofp i64 %in to float %unsigned = uitofp i64 %in to float @@ -103,7 +103,7 @@ define float @test_i64tofloat(i64 %in) { } define double @test_i64todouble(i64 %in) { -; CHECK: test_i64todouble: +; CHECK-LABEL: test_i64todouble: %signed = sitofp i64 %in to double %unsigned = uitofp i64 %in to double @@ -117,7 +117,7 @@ define double @test_i64todouble(i64 %in) { } define i32 @test_bitcastfloattoi32(float %in) { -; CHECK: test_bitcastfloattoi32: +; CHECK-LABEL: test_bitcastfloattoi32: %res = bitcast float %in to i32 ; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}} @@ -125,7 +125,7 @@ define i32 @test_bitcastfloattoi32(float %in) { } define i64 @test_bitcastdoubletoi64(double %in) { -; CHECK: test_bitcastdoubletoi64: +; CHECK-LABEL: test_bitcastdoubletoi64: %res = bitcast double %in to i64 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}} @@ -133,7 +133,7 @@ define i64 @test_bitcastdoubletoi64(double %in) { } define float @test_bitcasti32tofloat(i32 %in) { -; CHECK: test_bitcasti32tofloat: +; CHECK-LABEL: test_bitcasti32tofloat: %res = bitcast i32 %in to float ; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}} @@ -142,7 +142,7 @@ define float @test_bitcasti32tofloat(i32 %in) { } define double @test_bitcasti64todouble(i64 %in) { -; CHECK: test_bitcasti64todouble: +; CHECK-LABEL: test_bitcasti64todouble: %res = bitcast i64 %in to double ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}} diff --git a/test/CodeGen/AArch64/flags-multiuse.ll b/test/CodeGen/AArch64/flags-multiuse.ll index 940c146f0a..e99c728339 100644 --- a/test/CodeGen/AArch64/flags-multiuse.ll +++ b/test/CodeGen/AArch64/flags-multiuse.ll @@ -9,7 +9,7 @@ declare void @bar() @var = global i32 0 define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) { -; CHECK: test_multiflag: +; CHECK-LABEL: test_multiflag: %test = icmp ne i32 %n, %m ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] diff --git a/test/CodeGen/AArch64/floatdp_2source.ll b/test/CodeGen/AArch64/floatdp_2source.ll index b2256b342a..bb655285ac 100644 --- a/test/CodeGen/AArch64/floatdp_2source.ll +++ b/test/CodeGen/AArch64/floatdp_2source.ll @@ -4,7 +4,7 @@ @vardouble = global double 0.0 define void @testfloat() { -; CHECK: testfloat: +; CHECK-LABEL: testfloat: %val1 = load float* @varfloat %val2 = fadd float %val1, %val1 @@ -32,7 +32,7 @@ define void @testfloat() { } define void @testdouble() { -; CHECK: testdouble: +; CHECK-LABEL: testdouble: %val1 = load double* @vardouble %val2 = fadd double %val1, %val1 diff --git a/test/CodeGen/AArch64/fp-cond-sel.ll b/test/CodeGen/AArch64/fp-cond-sel.ll index 56e8f16f9b..572f42e210 100644 --- a/test/CodeGen/AArch64/fp-cond-sel.ll +++ b/test/CodeGen/AArch64/fp-cond-sel.ll @@ -4,7 +4,7 @@ @vardouble = global double 0.0 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { -; CHECK: test_csel: +; CHECK-LABEL: test_csel: %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, float 0.0, float 1.0 diff --git a/test/CodeGen/AArch64/fp-dp3.ll b/test/CodeGen/AArch64/fp-dp3.ll index f4c00a73d7..09d90727c8 100644 --- a/test/CodeGen/AArch64/fp-dp3.ll +++ b/test/CodeGen/AArch64/fp-dp3.ll @@ -45,7 +45,7 @@ define float @test_fnmsub(float %a, float %b, float %c) { } define double @testd_fmadd(double %a, double %b, double %c) { -; CHECK: testd_fmadd: +; CHECK-LABEL: testd_fmadd: ; CHECK-NOFAST: testd_fmadd: %val = call double @llvm.fma.f64(double %a, double %b, double %c) ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} @@ -54,7 +54,7 @@ define double @testd_fmadd(double %a, double %b, double %c) { } define double @testd_fmsub(double %a, double %b, double %c) { -; CHECK: testd_fmsub: +; CHECK-LABEL: testd_fmsub: ; CHECK-NOFAST: testd_fmsub: %nega = fsub double -0.0, %a %val = call double @llvm.fma.f64(double %nega, double %b, double %c) @@ -64,7 +64,7 @@ define double @testd_fmsub(double %a, double %b, double %c) { } define double @testd_fnmadd(double %a, double %b, double %c) { -; CHECK: testd_fnmadd: +; CHECK-LABEL: testd_fnmadd: ; CHECK-NOFAST: testd_fnmadd: %negc = fsub double -0.0, %c %val = call double @llvm.fma.f64(double %a, double %b, double %negc) @@ -74,7 +74,7 @@ define double @testd_fnmadd(double %a, double %b, double %c) { } define double @testd_fnmsub(double %a, double %b, double %c) { -; CHECK: testd_fnmsub: +; CHECK-LABEL: testd_fnmsub: ; CHECK-NOFAST: testd_fnmsub: %nega = fsub double -0.0, %a %negc = fsub double -0.0, %c diff --git a/test/CodeGen/AArch64/fp128-folding.ll b/test/CodeGen/AArch64/fp128-folding.ll index b5bdcf4f37..b1c560d2b6 100644 --- a/test/CodeGen/AArch64/fp128-folding.ll +++ b/test/CodeGen/AArch64/fp128-folding.ll @@ -5,7 +5,7 @@ declare void @bar(i8*, i8*, i32*) ; which is not supported. define fp128 @test_folding() { -; CHECK: test_folding: +; CHECK-LABEL: test_folding: %l = alloca i32 store i32 42, i32* %l %val = load i32* %l @@ -14,4 +14,4 @@ define fp128 @test_folding() { ; successfully. ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI ret fp128 %fpval -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/fp128.ll b/test/CodeGen/AArch64/fp128.ll index 258d34b8f8..853c03d234 100644 --- a/test/CodeGen/AArch64/fp128.ll +++ b/test/CodeGen/AArch64/fp128.ll @@ -4,7 +4,7 @@ @rhs = global fp128 zeroinitializer define fp128 @test_add() { -; CHECK: test_add: +; CHECK-LABEL: test_add: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -17,7 +17,7 @@ define fp128 @test_add() { } define fp128 @test_sub() { -; CHECK: test_sub: +; CHECK-LABEL: test_sub: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -30,7 +30,7 @@ define fp128 @test_sub() { } define fp128 @test_mul() { -; CHECK: test_mul: +; CHECK-LABEL: test_mul: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -43,7 +43,7 @@ define fp128 @test_mul() { } define fp128 @test_div() { -; CHECK: test_div: +; CHECK-LABEL: test_div: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -59,7 +59,7 @@ define fp128 @test_div() { @var64 = global i64 0 define void @test_fptosi() { -; CHECK: test_fptosi: +; CHECK-LABEL: test_fptosi: %val = load fp128* @lhs %val32 = fptosi fp128 %val to i32 @@ -74,7 +74,7 @@ define void @test_fptosi() { } define void @test_fptoui() { -; CHECK: test_fptoui: +; CHECK-LABEL: test_fptoui: %val = load fp128* @lhs %val32 = fptoui fp128 %val to i32 @@ -89,7 +89,7 @@ define void @test_fptoui() { } define void @test_sitofp() { -; CHECK: test_sitofp: +; CHECK-LABEL: test_sitofp: %src32 = load i32* @var32 %val32 = sitofp i32 %src32 to fp128 @@ -105,7 +105,7 @@ define void @test_sitofp() { } define void @test_uitofp() { -; CHECK: test_uitofp: +; CHECK-LABEL: test_uitofp: %src32 = load i32* @var32 %val32 = uitofp i32 %src32 to fp128 @@ -121,7 +121,7 @@ define void @test_uitofp() { } define i1 @test_setcc1() { -; CHECK: test_setcc1: +; CHECK-LABEL: test_setcc1: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -140,7 +140,7 @@ define i1 @test_setcc1() { } define i1 @test_setcc2() { -; CHECK: test_setcc2: +; CHECK-LABEL: test_setcc2: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -165,7 +165,7 @@ define i1 @test_setcc2() { } define i32 @test_br_cc() { -; CHECK: test_br_cc: +; CHECK-LABEL: test_br_cc: %lhs = load fp128* @lhs %rhs = load fp128* @rhs @@ -202,7 +202,7 @@ iffalse: } define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { -; CHECK: test_select: +; CHECK-LABEL: test_select: %val = select i1 %cond, fp128 %lhs, fp128 %rhs store fp128 %val, fp128* @lhs @@ -222,7 +222,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { @vardouble = global double 0.0 define void @test_round() { -; CHECK: test_round: +; CHECK-LABEL: test_round: %val = load fp128* @lhs @@ -240,7 +240,7 @@ define void @test_round() { } define void @test_extend() { -; CHECK: test_extend: +; CHECK-LABEL: test_extend: %val = load fp128* @lhs @@ -265,7 +265,7 @@ define fp128 @test_neg(fp128 %in) { ; Make sure the weird hex constant below *is* -0.0 ; CHECK-NEXT: fp128 -0 -; CHECK: test_neg: +; CHECK-LABEL: test_neg: ; Could in principle be optimized to fneg which we can't select, this makes ; sure that doesn't happen. diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll index 78fde6a3c3..736710792f 100644 --- a/test/CodeGen/AArch64/func-argpassing.ll +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -186,7 +186,7 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3, declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) define i32 @test_extern() { -; CHECK: test_extern: +; CHECK-LABEL: test_extern: call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0) ; CHECK: bl memcpy ret i32 0 diff --git a/test/CodeGen/AArch64/global-alignment.ll b/test/CodeGen/AArch64/global-alignment.ll index 8ed6e551cd..56e5cba519 100644 --- a/test/CodeGen/AArch64/global-alignment.ll +++ b/test/CodeGen/AArch64/global-alignment.ll @@ -5,7 +5,7 @@ @var32_align64 = global [3 x i32] zeroinitializer, align 8 define i64 @test_align32() { -; CHECK: test_align32: +; CHECK-LABEL: test_align32: %addr = bitcast [3 x i32]* @var32 to i64* ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to @@ -19,7 +19,7 @@ define i64 @test_align32() { } define i64 @test_align64() { -; CHECK: test_align64: +; CHECK-LABEL: test_align64: %addr = bitcast [3 x i64]* @var64 to i64* ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be @@ -33,7 +33,7 @@ define i64 @test_align64() { } define i64 @test_var32_align64() { -; CHECK: test_var32_align64: +; CHECK-LABEL: test_var32_align64: %addr = bitcast [3 x i32]* @var32_align64 to i64* ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to @@ -49,7 +49,7 @@ define i64 @test_var32_align64() { @yet_another_var = external global {i32, i32} define i64 @test_yet_another_var() { -; CHECK: test_yet_another_var: +; CHECK-LABEL: test_yet_another_var: ; @yet_another_var has a preferred alignment of 8, but that's not enough if ; we're going to be linking against other things. Its ABI alignment is only 4 @@ -62,7 +62,7 @@ define i64 @test_yet_another_var() { } define i64()* @test_functions() { -; CHECK: test_functions: +; CHECK-LABEL: test_functions: ret i64()* @test_yet_another_var ; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var ; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var diff --git a/test/CodeGen/AArch64/i128-align.ll b/test/CodeGen/AArch64/i128-align.ll index f019ea0a67..8eeaa2fd96 100644 --- a/test/CodeGen/AArch64/i128-align.ll +++ b/test/CodeGen/AArch64/i128-align.ll @@ -26,4 +26,4 @@ define i64 @check_field() { %diff = sub i64 %endi, %starti ret i64 %diff ; CHECK: movz x0, #16 -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/init-array.ll b/test/CodeGen/AArch64/init-array.ll index d80be8f3a6..3ff1c1a86e 100644 --- a/test/CodeGen/AArch64/init-array.ll +++ b/test/CodeGen/AArch64/init-array.ll @@ -6,4 +6,4 @@ define internal void @_GLOBAL__I_a() section ".text.startup" { @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }] -; CHECK: .section .init_array
\ No newline at end of file +; CHECK: .section .init_array diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badI.ll b/test/CodeGen/AArch64/inline-asm-constraints-badI.ll index c39c57f058..61bbfc2013 100644 --- a/test/CodeGen/AArch64/inline-asm-constraints-badI.ll +++ b/test/CodeGen/AArch64/inline-asm-constraints-badI.ll @@ -4,4 +4,4 @@ define void @foo() { ; Out of range immediate for I. call void asm sideeffect "add x0, x0, $0", "I"(i32 4096) ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badK.ll b/test/CodeGen/AArch64/inline-asm-constraints-badK.ll index 47c5f98bf0..40746e1528 100644 --- a/test/CodeGen/AArch64/inline-asm-constraints-badK.ll +++ b/test/CodeGen/AArch64/inline-asm-constraints-badK.ll @@ -4,4 +4,4 @@ define void @foo() { ; 32-bit bitpattern ending in 1101 can't be produced. call void asm sideeffect "and w0, w0, $0", "K"(i32 13) ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll b/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll index 7a5b99e23b..2c5338191f 100644 --- a/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll +++ b/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll @@ -4,4 +4,4 @@ define void @foo() { ; 32-bit bitpattern ending in 1101 can't be produced. call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296) ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badL.ll b/test/CodeGen/AArch64/inline-asm-constraints-badL.ll index 4f0039865a..d82d5a2ee4 100644 --- a/test/CodeGen/AArch64/inline-asm-constraints-badL.ll +++ b/test/CodeGen/AArch64/inline-asm-constraints-badL.ll @@ -4,4 +4,4 @@ define void @foo() { ; 32-bit bitpattern ending in 1101 can't be produced. call void asm sideeffect "and x0, x0, $0", "L"(i32 13) ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/inline-asm-constraints.ll b/test/CodeGen/AArch64/inline-asm-constraints.ll index c232f3208c..cfa06a4e0b 100644 --- a/test/CodeGen/AArch64/inline-asm-constraints.ll +++ b/test/CodeGen/AArch64/inline-asm-constraints.ll @@ -1,21 +1,21 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s define i64 @test_inline_constraint_r(i64 %base, i32 %offset) { -; CHECK: test_inline_constraint_r: +; CHECK-LABEL: test_inline_constraint_r: %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset) ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw ret i64 %val } define i16 @test_small_reg(i16 %lhs, i16 %rhs) { -; CHECK: test_small_reg: +; CHECK-LABEL: test_small_reg: %val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs) ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth ret i16 %val } define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) { -; CHECK: test_inline_constraint_r_imm: +; CHECK-LABEL: test_inline_constraint_r_imm: %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12) ; CHECK: movz [[FOUR:x[0-9]+]], #4 ; CHECK: movz [[TWELVE:w[0-9]+]], #12 @@ -26,7 +26,7 @@ define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) { ; m is permitted to have a base/offset form. We don't do that ; currently though. define i32 @test_inline_constraint_m(i32 *%ptr) { -; CHECK: test_inline_constraint_m: +; CHECK-LABEL: test_inline_constraint_m: %val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr) ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}] ret i32 %val @@ -36,7 +36,7 @@ define i32 @test_inline_constraint_m(i32 *%ptr) { ; Q should *never* have base/offset form even if given the chance. define i32 @test_inline_constraint_Q(i32 *%ptr) { -; CHECK: test_inline_constraint_Q: +; CHECK-LABEL: test_inline_constraint_Q: %val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1)) ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}] ret i32 %val @@ -45,7 +45,7 @@ define i32 @test_inline_constraint_Q(i32 *%ptr) { @dump = global fp128 zeroinitializer define void @test_inline_constraint_I() { -; CHECK: test_inline_constraint_I: +; CHECK-LABEL: test_inline_constraint_I: call void asm sideeffect "add x0, x0, $0", "I"(i32 0) call void asm sideeffect "add x0, x0, $0", "I"(i64 4095) ; CHECK: add x0, x0, #0 @@ -57,7 +57,7 @@ define void @test_inline_constraint_I() { ; Skip J because it's useless define void @test_inline_constraint_K() { -; CHECK: test_inline_constraint_K: +; CHECK-LABEL: test_inline_constraint_K: call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa call void asm sideeffect "and w0, w0, $0", "K"(i32 65535) ; CHECK: and w0, w0, #-1431655766 @@ -67,7 +67,7 @@ define void @test_inline_constraint_K() { } define void @test_inline_constraint_L() { -; CHECK: test_inline_constraint_L: +; CHECK-LABEL: test_inline_constraint_L: call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa call void asm sideeffect "and x0, x0, $0", "L"(i64 65535) ; CHECK: and x0, x0, #4294967296 @@ -81,7 +81,7 @@ define void @test_inline_constraint_L() { @var = global i32 0 define void @test_inline_constraint_S() { -; CHECK: test_inline_constraint_S: +; CHECK-LABEL: test_inline_constraint_S: call void asm sideeffect "adrp x0, $0", "S"(i32* @var) call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var) call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var) @@ -92,7 +92,7 @@ define void @test_inline_constraint_S() { } define i32 @test_inline_constraint_S_label(i1 %in) { -; CHECK: test_inline_constraint_S_label: +; CHECK-LABEL: test_inline_constraint_S_label: call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc)) ; CHECK: adr x0, .Ltmp{{[0-9]+}} br i1 %in, label %loc, label %loc2 @@ -103,15 +103,15 @@ loc2: } define void @test_inline_constraint_Y() { -; CHECK: test_inline_constraint_Y: +; CHECK-LABEL: test_inline_constraint_Y: call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0) ; CHECK: fcmp s0, #0.0 ret void } define void @test_inline_constraint_Z() { -; CHECK: test_inline_constraint_Z: +; CHECK-LABEL: test_inline_constraint_Z: call void asm sideeffect "cmp w0, $0", "Z"(i32 0) ; CHECK: cmp w0, #0 ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/inline-asm-modifiers.ll b/test/CodeGen/AArch64/inline-asm-modifiers.ll index 3b55945561..d1b21f8c8b 100644 --- a/test/CodeGen/AArch64/inline-asm-modifiers.ll +++ b/test/CodeGen/AArch64/inline-asm-modifiers.ll @@ -9,7 +9,7 @@ @var_tlsle = thread_local(localexec) global i32 0 define void @test_inline_modifier_L() nounwind { -; CHECK: test_inline_modifier_L: +; CHECK-LABEL: test_inline_modifier_L: call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple) call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got) call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd) @@ -34,7 +34,7 @@ define void @test_inline_modifier_L() nounwind { } define void @test_inline_modifier_G() nounwind { -; CHECK: test_inline_modifier_G: +; CHECK-LABEL: test_inline_modifier_G: call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld) call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle) ; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12 @@ -47,7 +47,7 @@ define void @test_inline_modifier_G() nounwind { } define void @test_inline_modifier_A() nounwind { -; CHECK: test_inline_modifier_A: +; CHECK-LABEL: test_inline_modifier_A: call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple) call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got) call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd) @@ -67,7 +67,7 @@ define void @test_inline_modifier_A() nounwind { } define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind { -; CHECK: test_inline_modifier_wx: +; CHECK-LABEL: test_inline_modifier_wx: call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small) call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small) call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small) @@ -91,7 +91,7 @@ define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind { } define void @test_inline_modifier_bhsdq() nounwind { -; CHECK: test_inline_modifier_bhsdq: +; CHECK-LABEL: test_inline_modifier_bhsdq: call float asm sideeffect "ldr ${0:b}, [sp]", "=w"() call float asm sideeffect "ldr ${0:h}, [sp]", "=w"() call float asm sideeffect "ldr ${0:s}, [sp]", "=w"() @@ -117,9 +117,9 @@ define void @test_inline_modifier_bhsdq() nounwind { } define void @test_inline_modifier_c() nounwind { -; CHECK: test_inline_modifier_c: +; CHECK-LABEL: test_inline_modifier_c: call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3) ; CHECK: adr x0, 3 ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/large-frame.ll b/test/CodeGen/AArch64/large-frame.ll index 690b21d310..fde3036aef 100644 --- a/test/CodeGen/AArch64/large-frame.ll +++ b/test/CodeGen/AArch64/large-frame.ll @@ -4,7 +4,7 @@ declare void @use_addr(i8*) @addr = global i8* null define void @test_bigframe() { -; CHECK: test_bigframe: +; CHECK-LABEL: test_bigframe: ; CHECK: .cfi_startproc %var1 = alloca i8, i32 20000000 @@ -50,7 +50,7 @@ define void @test_bigframe() { } define void @test_mediumframe() { -; CHECK: test_mediumframe: +; CHECK-LABEL: test_mediumframe: %var1 = alloca i8, i32 1000000 %var2 = alloca i8, i32 16 %var3 = alloca i8, i32 1000000 @@ -93,7 +93,7 @@ define void @test_mediumframe() { ; If temporary registers are allocated for adjustment, they should *not* clobber ; argument registers. define void @test_tempallocation([8 x i64] %val) nounwind { -; CHECK: test_tempallocation: +; CHECK-LABEL: test_tempallocation: %var = alloca i8, i32 1000000 ; CHECK: sub sp, sp, diff --git a/test/CodeGen/AArch64/logical-imm.ll b/test/CodeGen/AArch64/logical-imm.ll index 5f3f4da0cd..e04bb510eb 100644 --- a/test/CodeGen/AArch64/logical-imm.ll +++ b/test/CodeGen/AArch64/logical-imm.ll @@ -4,7 +4,7 @@ @var64 = global i64 0 define void @test_and(i32 %in32, i64 %in64) { -; CHECK: test_and: +; CHECK-LABEL: test_and: %val0 = and i32 %in32, 2863311530 store volatile i32 %val0, i32* @var32 @@ -26,7 +26,7 @@ define void @test_and(i32 %in32, i64 %in64) { } define void @test_orr(i32 %in32, i64 %in64) { -; CHECK: test_orr: +; CHECK-LABEL: test_orr: %val0 = or i32 %in32, 2863311530 store volatile i32 %val0, i32* @var32 @@ -48,7 +48,7 @@ define void @test_orr(i32 %in32, i64 %in64) { } define void @test_eor(i32 %in32, i64 %in64) { -; CHECK: test_eor: +; CHECK-LABEL: test_eor: %val0 = xor i32 %in32, 2863311530 store volatile i32 %val0, i32* @var32 @@ -70,7 +70,7 @@ define void @test_eor(i32 %in32, i64 %in64) { } define void @test_mov(i32 %in32, i64 %in64) { -; CHECK: test_mov: +; CHECK-LABEL: test_mov: %val0 = add i32 %in32, 2863311530 store i32 %val0, i32* @var32 ; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll index b8a5fb9322..38e37db7b5 100644 --- a/test/CodeGen/AArch64/movw-consts.ll +++ b/test/CodeGen/AArch64/movw-consts.ll @@ -1,50 +1,50 @@ ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s define i64 @test0() { -; CHECK: test0: +; CHECK-LABEL: test0: ; Not produced by move wide instructions, but good to make sure we can return 0 anyway: ; CHECK: mov x0, xzr ret i64 0 } define i64 @test1() { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: movz x0, #1 ret i64 1 } define i64 @test2() { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: movz x0, #65535 ret i64 65535 } define i64 @test3() { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: movz x0, #1, lsl #16 ret i64 65536 } define i64 @test4() { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: movz x0, #65535, lsl #16 ret i64 4294901760 } define i64 @test5() { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: movz x0, #1, lsl #32 ret i64 4294967296 } define i64 @test6() { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: movz x0, #65535, lsl #32 ret i64 281470681743360 } define i64 @test7() { -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: movz x0, #1, lsl #48 ret i64 281474976710656 } @@ -52,19 +52,19 @@ define i64 @test7() { ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one ; couldn't. Useful even for i64 define i64 @test8() { -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: movn w0, #60875 ret i64 4294906420 } define i64 @test9() { -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: movn x0, #0 ret i64 -1 } define i64 @test10() { -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: movn x0, #60875, lsl #16 ret i64 18446744069720047615 } @@ -74,49 +74,49 @@ define i64 @test10() { @var32 = global i32 0 define void @test11() { -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: mov {{w[0-9]+}}, wzr store i32 0, i32* @var32 ret void } define void @test12() { -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: movz {{w[0-9]+}}, #1 store i32 1, i32* @var32 ret void } define void @test13() { -; CHECK: test13: +; CHECK-LABEL: test13: ; CHECK: movz {{w[0-9]+}}, #65535 store i32 65535, i32* @var32 ret void } define void @test14() { -; CHECK: test14: +; CHECK-LABEL: test14: ; CHECK: movz {{w[0-9]+}}, #1, lsl #16 store i32 65536, i32* @var32 ret void } define void @test15() { -; CHECK: test15: +; CHECK-LABEL: test15: ; CHECK: movz {{w[0-9]+}}, #65535, lsl #16 store i32 4294901760, i32* @var32 ret void } define void @test16() { -; CHECK: test16: +; CHECK-LABEL: test16: ; CHECK: movn {{w[0-9]+}}, #0 store i32 -1, i32* @var32 ret void } define i64 @test17() { -; CHECK: test17: +; CHECK-LABEL: test17: ; Mustn't MOVN w0 here. ; CHECK: movn x0, #2 diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll index 77bf691cbc..6ec4b19a12 100644 --- a/test/CodeGen/AArch64/pic-eh-stubs.ll +++ b/test/CodeGen/AArch64/pic-eh-stubs.ll @@ -57,4 +57,4 @@ declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone declare i8* @__cxa_begin_catch(i8*) -declare void @__cxa_end_catch()
\ No newline at end of file +declare void @__cxa_end_catch() diff --git a/test/CodeGen/AArch64/regress-bitcast-formals.ll b/test/CodeGen/AArch64/regress-bitcast-formals.ll index 28dc9a7e25..9655f90d82 100644 --- a/test/CodeGen/AArch64/regress-bitcast-formals.ll +++ b/test/CodeGen/AArch64/regress-bitcast-formals.ll @@ -4,7 +4,7 @@ ; actually capable of that (the test was omitted from LowerFormalArguments). define void @test_bitcast_lower(<2 x i32> %a) { -; CHECK: test_bitcast_lower: +; CHECK-LABEL: test_bitcast_lower: ret void ; CHECK: ret diff --git a/test/CodeGen/AArch64/regress-tail-livereg.ll b/test/CodeGen/AArch64/regress-tail-livereg.ll index 8d5485cae4..32167752cb 100644 --- a/test/CodeGen/AArch64/regress-tail-livereg.ll +++ b/test/CodeGen/AArch64/regress-tail-livereg.ll @@ -16,4 +16,4 @@ define void @foo() { tail call void %func() ; CHECK: br {{x([0-79]|1[0-8])}} ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll index e54552fd8e..ff77fb4e48 100644 --- a/test/CodeGen/AArch64/regress-tblgen-chains.ll +++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll @@ -12,7 +12,7 @@ declare void @bar(i8*) define i64 @test_chains() { -; CHECK: test_chains: +; CHECK-LABEL: test_chains: %locvar = alloca i8 diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll index 9176651d06..0ef981819e 100644 --- a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll +++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll @@ -4,7 +4,7 @@ declare void @bar() define void @test_w29_reserved() { -; CHECK: test_w29_reserved: +; CHECK-LABEL: test_w29_reserved: ; CHECK: .cfi_startproc ; CHECK: .cfi_def_cfa sp, 96 ; CHECK: add x29, sp, #{{[0-9]+}} diff --git a/test/CodeGen/AArch64/setcc-takes-i32.ll b/test/CodeGen/AArch64/setcc-takes-i32.ll index d2eb77ab1b..bd79685d34 100644 --- a/test/CodeGen/AArch64/setcc-takes-i32.ll +++ b/test/CodeGen/AArch64/setcc-takes-i32.ll @@ -12,11 +12,11 @@ declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) define i64 @test_select(i64 %lhs, i64 %rhs) { -; CHECK: test_select: +; CHECK-LABEL: test_select: %res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs) %flag = extractvalue {i64, i1} %res, 1 %retval = select i1 %flag, i64 %lhs, i64 %rhs ret i64 %retval ; CHECK: ret -}
\ No newline at end of file +} diff --git a/test/CodeGen/AArch64/sincos-expansion.ll b/test/CodeGen/AArch64/sincos-expansion.ll index f1b7441118..4cd44494d5 100644 --- a/test/CodeGen/AArch64/sincos-expansion.ll +++ b/test/CodeGen/AArch64/sincos-expansion.ll @@ -32,4 +32,4 @@ declare double @sin(double) readonly declare fp128 @sinl(fp128) readonly declare float @cosf(float) readonly declare double @cos(double) readonly -declare fp128 @cosl(fp128) readonly
\ No newline at end of file +declare fp128 @cosl(fp128) readonly diff --git a/test/CodeGen/AArch64/tls-dynamic-together.ll b/test/CodeGen/AArch64/tls-dynamic-together.ll index bad2298c8a..b5d7d89384 100644 --- a/test/CodeGen/AArch64/tls-dynamic-together.ll +++ b/test/CodeGen/AArch64/tls-dynamic-together.ll @@ -8,7 +8,7 @@ @general_dynamic_var = external thread_local global i32 define i32 @test_generaldynamic() { -; CHECK: test_generaldynamic: +; CHECK-LABEL: test_generaldynamic: %val = load i32* @general_dynamic_var ret i32 %val diff --git a/test/CodeGen/AArch64/tls-dynamics.ll b/test/CodeGen/AArch64/tls-dynamics.ll index cdfd11783c..887d2f8c69 100644 --- a/test/CodeGen/AArch64/tls-dynamics.ll +++ b/test/CodeGen/AArch64/tls-dynamics.ll @@ -4,7 +4,7 @@ @general_dynamic_var = external thread_local global i32 define i32 @test_generaldynamic() { -; CHECK: test_generaldynamic: +; CHECK-LABEL: test_generaldynamic: %val = load i32* @general_dynamic_var ret i32 %val @@ -26,7 +26,7 @@ define i32 @test_generaldynamic() { } define i32* @test_generaldynamic_addr() { -; CHECK: test_generaldynamic_addr: +; CHECK-LABEL: test_generaldynamic_addr: ret i32* @general_dynamic_var @@ -49,7 +49,7 @@ define i32* @test_generaldynamic_addr() { @local_dynamic_var = external thread_local(localdynamic) global i32 define i32 @test_localdynamic() { -; CHECK: test_localdynamic: +; CHECK-LABEL: test_localdynamic: %val = load i32* @local_dynamic_var ret i32 %val @@ -73,7 +73,7 @@ define i32 @test_localdynamic() { } define i32* @test_localdynamic_addr() { -; CHECK: test_localdynamic_addr: +; CHECK-LABEL: test_localdynamic_addr: ret i32* @local_dynamic_var @@ -101,7 +101,7 @@ define i32* @test_localdynamic_addr() { @local_dynamic_var2 = external thread_local(localdynamic) global i32 define i32 @test_localdynamic_deduplicate() { -; CHECK: test_localdynamic_deduplicate: +; CHECK-LABEL: test_localdynamic_deduplicate: %val = load i32* @local_dynamic_var %val2 = load i32* @local_dynamic_var2 diff --git a/test/CodeGen/AArch64/tls-execs.ll b/test/CodeGen/AArch64/tls-execs.ll index a665884227..5bb9e32e99 100644 --- a/test/CodeGen/AArch64/tls-execs.ll +++ b/test/CodeGen/AArch64/tls-execs.ll @@ -4,7 +4,7 @@ @initial_exec_var = external thread_local(initialexec) global i32 define i32 @test_initial_exec() { -; CHECK: test_initial_exec: +; CHECK-LABEL: test_initial_exec: %val = load i32* @initial_exec_var ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var @@ -19,7 +19,7 @@ define i32 @test_initial_exec() { } define i32* @test_initial_exec_addr() { -; CHECK: test_initial_exec_addr: +; CHECK-LABEL: test_initial_exec_addr: ret i32* @initial_exec_var ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var @@ -35,7 +35,7 @@ define i32* @test_initial_exec_addr() { @local_exec_var = thread_local(initialexec) global i32 0 define i32 @test_local_exec() { -; CHECK: test_local_exec: +; CHECK-LABEL: test_local_exec: %val = load i32* @local_exec_var ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var @@ -50,7 +50,7 @@ define i32 @test_local_exec() { } define i32* @test_local_exec_addr() { -; CHECK: test_local_exec_addr: +; CHECK-LABEL: test_local_exec_addr: ret i32* @local_exec_var ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var diff --git a/test/CodeGen/AArch64/tst-br.ll b/test/CodeGen/AArch64/tst-br.ll index 65c1fda49e..154bc08c14 100644 --- a/test/CodeGen/AArch64/tst-br.ll +++ b/test/CodeGen/AArch64/tst-br.ll @@ -7,7 +7,7 @@ @var64 = global i64 0 define i32 @test_tbz() { -; CHECK: test_tbz: +; CHECK-LABEL: test_tbz: %val = load i32* @var32 %val64 = load i64* @var64 diff --git a/test/CodeGen/AArch64/variadic.ll b/test/CodeGen/AArch64/variadic.ll index c5d319eb11..1c7e3bf302 100644 --- a/test/CodeGen/AArch64/variadic.ll +++ b/test/CodeGen/AArch64/variadic.ll @@ -7,7 +7,7 @@ declare void @llvm.va_start(i8*) define void @test_simple(i32 %n, ...) { -; CHECK: test_simple: +; CHECK-LABEL: test_simple: ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] ; CHECK: mov x[[FPRBASE:[0-9]+]], sp ; CHECK: str q7, [x[[FPRBASE]], #112] @@ -37,7 +37,7 @@ define void @test_simple(i32 %n, ...) { } define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { -; CHECK: test_fewargs: +; CHECK-LABEL: test_fewargs: ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] ; CHECK: mov x[[FPRBASE:[0-9]+]], sp ; CHECK: str q7, [x[[FPRBASE]], #96] @@ -67,7 +67,7 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { } define void @test_nospare([8 x i64], [8 x float], ...) { -; CHECK: test_nospare: +; CHECK-LABEL: test_nospare: %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) @@ -81,7 +81,7 @@ define void @test_nospare([8 x i64], [8 x float], ...) { ; If there are non-variadic arguments on the stack (here two i64s) then the ; __stack field should point just past them. define void @test_offsetstack([10 x i64], [3 x float], ...) { -; CHECK: test_offsetstack: +; CHECK-LABEL: test_offsetstack: ; CHECK: sub sp, sp, #80 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp ; CHECK: str q7, [x[[FPRBASE]], #64] @@ -108,7 +108,7 @@ define void @test_offsetstack([10 x i64], [3 x float], ...) { declare void @llvm.va_end(i8*) define void @test_va_end() nounwind { -; CHECK: test_va_end: +; CHECK-LABEL: test_va_end: ; CHECK-NEXT: BB#0 %addr = bitcast %va_list* @var to i8* @@ -123,7 +123,7 @@ declare void @llvm.va_copy(i8* %dest, i8* %src) @second_list = global %va_list zeroinitializer define void @test_va_copy() { -; CHECK: test_va_copy: +; CHECK-LABEL: test_va_copy: %srcaddr = bitcast %va_list* @var to i8* %dstaddr = bitcast %va_list* @second_list to i8* call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr) diff --git a/test/CodeGen/AArch64/zero-reg.ll b/test/CodeGen/AArch64/zero-reg.ll index fef0437ae7..9b1e52770c 100644 --- a/test/CodeGen/AArch64/zero-reg.ll +++ b/test/CodeGen/AArch64/zero-reg.ll @@ -4,7 +4,7 @@ @var64 = global i64 0 define void @test_zr() { -; CHECK: test_zr: +; CHECK-LABEL: test_zr: store i32 0, i32* @var32 ; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32] @@ -16,7 +16,7 @@ define void @test_zr() { } define void @test_sp(i32 %val) { -; CHECK: test_sp: +; CHECK-LABEL: test_sp: ; Important correctness point here is that LLVM doesn't try to use xzr ; as an addressing register: "str w0, [xzr]" is not a valid A64 @@ -28,4 +28,4 @@ define void @test_sp(i32 %val) { ret void ; CHECK: ret -}
\ No newline at end of file +} |