diff options
Diffstat (limited to 'test/CodeGen/AArch64/atomic-ops.ll')
| -rw-r--r-- | test/CodeGen/AArch64/atomic-ops.ll | 474 |
1 files changed, 226 insertions, 248 deletions
diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index 5fe29364ee..58b5d1d078 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -1,5 +1,11 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-REG %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG + + +; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created +; (i.e. reusing a register for status & data in store exclusive). +; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}] +; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}] @var8 = global i8 0 @var16 = global i16 0 @@ -11,20 +17,18 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { %old = atomicrmw add i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: add w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -33,20 +37,18 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { %old = atomicrmw add i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: add w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -55,20 +57,18 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { %old = atomicrmw add i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: add w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -77,15 +77,13 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { %old = atomicrmw add i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-REG: add x[[NEW:[0-9]+]], x{{[0-9]+}}, x0 -; CHECK-REG-NOT: stxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -99,20 +97,18 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { %old = atomicrmw sub i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: sub w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -121,20 +117,18 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { %old = atomicrmw sub i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: sub w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -143,20 +137,18 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { %old = atomicrmw sub i32* @var32, i32 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: sub w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -165,15 +157,13 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { %old = atomicrmw sub i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-REG: sub x[[NEW:[0-9]+]], x{{[0-9]+}}, x0 -; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -187,20 +177,18 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { %old = atomicrmw and i8* @var8, i8 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: and w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -209,20 +197,18 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { %old = atomicrmw and i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: and w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -231,20 +217,18 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { %old = atomicrmw and i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: and w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -253,15 +237,13 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { %old = atomicrmw and i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-REG: and x[[NEW:[0-9]+]], x{{[0-9]+}}, x0 -; CHECK-REG-NOT: stxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -275,20 +257,18 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { %old = atomicrmw or i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: orr w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -297,20 +277,18 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { %old = atomicrmw or i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: orr w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -319,20 +297,18 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { %old = atomicrmw or i32* @var32, i32 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: orr w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -341,15 +317,13 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { %old = atomicrmw or i64* @var64, i64 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-REG: orr x[[NEW:[0-9]+]], x{{[0-9]+}}, x0 -; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -363,20 +337,18 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { %old = atomicrmw xor i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: eor w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -385,20 +357,18 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { %old = atomicrmw xor i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: eor w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -407,20 +377,18 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { %old = atomicrmw xor i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-REG: eor w[[NEW:[0-9]+]], w{{[0-9]+}}, w0 -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -429,15 +397,13 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { %old = atomicrmw xor i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-REG: eor x[[NEW:[0-9]+]], x{{[0-9]+}}, x0 -; CHECK-REG-NOT: stxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -451,18 +417,17 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { %old = atomicrmw xchg i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-REG-NOT: stxrb w0, w0, [x{{[0-9]+}}] ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -471,18 +436,17 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-REG-NOT: stlxrh w0, w0, [x{{[0-9]+}}] ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -491,18 +455,17 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { %old = atomicrmw xchg i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-REG-NOT: stlxr w0, w0, [x{{[0-9]+}}] ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -511,13 +474,12 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { %old = atomicrmw xchg i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-REG-NOT: stxr w0, x0, [x{{[0-9]+}}] ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -532,21 +494,22 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { %old = atomicrmw min i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], sxtb -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, gt -; CHECK-REG-NOT: stxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]] +; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le + ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -555,21 +518,23 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { %old = atomicrmw min i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], sxth -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, gt -; CHECK-REG-NOT: stlxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]] +; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le + + ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -578,21 +543,22 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { %old = atomicrmw min i32* @var32, i32 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]] -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, gt -; CHECK-REG-NOT: stxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le + + ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -601,16 +567,17 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { %old = atomicrmw min i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp x0, x[[OLD]] -; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt -; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, gt -; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp x[[OLD]], x0 +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, le + + ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -624,21 +591,23 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { %old = atomicrmw max i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], sxtb -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lt -; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]] +; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt + + ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -647,21 +616,23 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { %old = atomicrmw max i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], sxth -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lt -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: sxth w[[OLD_EXT:[0-9]+]], w[[OLD]] +; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt + + ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -670,21 +641,22 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { %old = atomicrmw max i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]] -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lt -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt + + ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -693,16 +665,17 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { %old = atomicrmw max i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp x0, x[[OLD]] -; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt -; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, lt -; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp x[[OLD]], x0 +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt + + ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -716,21 +689,22 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { %old = atomicrmw umin i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], uxtb -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, hi -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0, uxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls + + ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -739,21 +713,22 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { %old = atomicrmw umin i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], uxth -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, hi -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0, uxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls + + ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -762,21 +737,22 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { %old = atomicrmw umin i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]] -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, hi -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls + + ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -785,16 +761,17 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { %old = atomicrmw umin i64* @var64, i64 %offset acq_rel ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp x0, x[[OLD]] -; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi -; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, hi -; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp x[[OLD]], x0 +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, ls + + ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -808,21 +785,22 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { %old = atomicrmw umax i8* @var8, i8 %offset acq_rel ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], uxtb -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lo -; CHECK-REG-NOT: stlxrb w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0, uxtb +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi + + ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -831,21 +809,22 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { %old = atomicrmw umax i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]], uxth -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lo -; CHECK-REG-NOT: stxrh w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0, uxth +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi + + ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -854,21 +833,22 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { %old = atomicrmw umax i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp w0, w[[OLD]] -; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-REG: csel w[[NEW:[0-9]+]], w{{[0-9]+}}, w0, lo -; CHECK-REG-NOT: stlxr w[[NEW]], w[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp w[[OLD]], w0 +; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi + + ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } @@ -877,16 +857,17 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { %old = atomicrmw umax i64* @var64, i64 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: cmp x0, x[[OLD]] -; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo -; CHECK-REG: csel x[[NEW:[0-9]+]], x{{[0-9]+}}, x0, lo -; CHECK-REG-NOT: stlxr w[[NEW]], x[[NEW]], [x{{[0-9]+}}] + +; CHECK-NEXT: cmp x[[OLD]], x0 +; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi + + ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 ; CHECK-NOT: dmb @@ -900,21 +881,20 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK-REG-NOT: stxrb w1, w1, [x{{[0-9]+}}] ; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i8 %old } @@ -923,21 +903,20 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK-REG-NOT: stlxrh w1, w1, [x{{[0-9]+}}] ; CHECK: stlxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i16 %old } @@ -946,45 +925,44 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK-REG-NOT: stlxr w1, w1, [x{{[0-9]+}}] ; CHECK: stlxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] +; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]] ret i32 %old } -define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { +define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK-LABEL: test_atomic_cmpxchg_i64: %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp x[[OLD]], x0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK-REG-NOT: stxr w1, x1, [x{{[0-9]+}}] ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] ; CHECK-NOT: dmb -; CHECK: mov x0, x[[OLD]] - ret i64 %old +; CHECK: str x[[OLD]], + store i64 %old, i64* @var64 + ret void } define i8 @test_atomic_load_monotonic_i8() nounwind { @@ -992,7 +970,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind { %val = load atomic i8* @var8 monotonic, align 1 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 -; CHECK: ldrb w0, [x[[HIADDR]], #:lo12:var8] +; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8] ; CHECK-NOT: dmb ret i8 %val @@ -1017,7 +995,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind { ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK-NOT: dmb -; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8 ; CHECK-NOT: dmb ; CHECK: ldarb w0, [x[[ADDR]]] ; CHECK-NOT: dmb @@ -1030,7 +1008,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind { ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 ; CHECK-NOT: dmb -; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8 ; CHECK-NOT: dmb ; CHECK: ldarb w0, [x[[ADDR]]] ; CHECK-NOT: dmb @@ -1043,7 +1021,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind { ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 ; CHECK-NOT: dmb -; CHECK: ldrh w0, [x[[HIADDR]], #:lo12:var16] +; CHECK: ldrh w0, [x[[HIADDR]], {{#?}}:lo12:var16] ; CHECK-NOT: dmb ret i16 %val @@ -1068,7 +1046,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind { ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 ; CHECK-NOT: dmb -; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64 ; CHECK-NOT: dmb ; CHECK: ldar x0, [x[[ADDR]]] ; CHECK-NOT: dmb @@ -1079,7 +1057,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { ; CHECK-LABEL: test_atomic_store_monotonic_i8: store atomic i8 %val, i8* @var8 monotonic, align 1 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 -; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8] +; CHECK: strb w0, [x[[HIADDR]], {{#?}}:lo12:var8] ret void } @@ -1101,7 +1079,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind { ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 ; CHECK-NOT: dmb -; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8 ; CHECK-NOT: dmb ; CHECK: stlrb w0, [x[[ADDR]]] ; CHECK-NOT: dmb @@ -1114,7 +1092,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 ; CHECK-NOT: dmb -; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8 ; CHECK-NOT: dmb ; CHECK: stlrb w0, [x[[ADDR]]] ; CHECK-NOT: dmb @@ -1128,7 +1106,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 ; CHECK-NOT: dmb -; CHECK: strh w0, [x[[HIADDR]], #:lo12:var16] +; CHECK: strh w0, [x[[HIADDR]], {{#?}}:lo12:var16] ; CHECK-NOT: dmb ret void } @@ -1153,7 +1131,7 @@ define void @test_atomic_store_release_i64(i64 %val) nounwind { ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 ; CHECK-NOT: dmb -; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64 ; CHECK-NOT: dmb ; CHECK: stlr x0, [x[[ADDR]]] ; CHECK-NOT: dmb |