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-rw-r--r--lib/CodeGen/AsmPrinter.cpp3
-rw-r--r--lib/CodeGen/IfConversion.cpp3
-rw-r--r--lib/CodeGen/LiveInterval.cpp3
-rw-r--r--lib/CodeGen/RegAllocBigBlock.cpp5
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp19
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp19
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp13
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp2
-rw-r--r--lib/CodeGen/VirtRegMap.cpp3
9 files changed, 44 insertions, 26 deletions
diff --git a/lib/CodeGen/AsmPrinter.cpp b/lib/CodeGen/AsmPrinter.cpp
index b718958f97..7a01a87872 100644
--- a/lib/CodeGen/AsmPrinter.cpp
+++ b/lib/CodeGen/AsmPrinter.cpp
@@ -162,11 +162,12 @@ bool AsmPrinter::doFinalization(Module &M) {
// If the aliasee has external weak linkage it can be referenced only by
// alias itself. In this case it can be not in ExtWeakSymbols list. Emit
// weak reference in such case.
- if (GV->hasExternalWeakLinkage())
+ if (GV->hasExternalWeakLinkage()) {
if (TAI->getWeakRefDirective())
O << TAI->getWeakRefDirective() << Target << "\n";
else
O << "\t.globl\t" << Target << "\n";
+ }
}
}
diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp
index fb53377b98..7d7f33e535 100644
--- a/lib/CodeGen/IfConversion.cpp
+++ b/lib/CodeGen/IfConversion.cpp
@@ -278,9 +278,10 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
: BBI.TrueBB->getNumber()) << ") ";
RetVal = IfConvertSimple(BBI, Kind);
DOUT << (RetVal ? "succeeded!" : "failed!") << "\n";
- if (RetVal)
+ if (RetVal) {
if (isFalse) NumSimpleFalse++;
else NumSimple++;
+ }
break;
}
case ICTriangle:
diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp
index 741c35c43a..48c25a14a3 100644
--- a/lib/CodeGen/LiveInterval.cpp
+++ b/lib/CodeGen/LiveInterval.cpp
@@ -217,7 +217,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
// Otherwise, if this range ends in the middle of, or right next to, another
// interval, merge it into that interval.
- if (it != ranges.end())
+ if (it != ranges.end()) {
if (LR.valno == it->valno) {
if (it->start <= End) {
it = extendIntervalStartTo(it, Start);
@@ -237,6 +237,7 @@ LiveInterval::addRangeFrom(LiveRange LR, iterator From) {
assert(it->start >= End &&
"Cannot overlap two LiveRanges with differing ValID's");
}
+ }
// Otherwise, this is just a new range that doesn't interact with anything.
// Insert it.
diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp
index f29b45eb14..38fb5e6894 100644
--- a/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/lib/CodeGen/RegAllocBigBlock.cpp
@@ -695,7 +695,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Unallocatable register dead, ignore.
continue;
} else {
- assert(!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1 &&
+ assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) &&
"Silently clearing a virtual register?");
}
@@ -832,11 +832,12 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Spill all physical registers holding virtual registers now.
for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
- if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
+ if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) {
if (unsigned VirtReg = PhysRegsUsed[i])
spillVirtReg(MBB, MI, VirtReg, i);
else
removePhysReg(i);
+ }
}
/// runOnMachineFunction - Register allocate the whole function
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 026666c45f..cd57d3ad36 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1996,11 +1996,12 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
- if (SUBC->getValue() == OpSizeInBits)
+ if (SUBC->getValue() == OpSizeInBits) {
if (HasROTL)
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+ }
}
}
@@ -2010,11 +2011,12 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
- if (SUBC->getValue() == OpSizeInBits)
+ if (SUBC->getValue() == OpSizeInBits) {
if (HasROTL)
return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+ }
}
}
@@ -2230,7 +2232,7 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
// the constant which would cause it to be modified for this
// operation.
if (N->getOpcode() == ISD::SRA) {
- uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1;
+ uint64_t BinOpRHSSign = BinOpCst->getValue() >> (MVT::getSizeInBits(VT)-1);
if ((bool)BinOpRHSSign != HighBitSet)
return SDOperand();
}
@@ -2552,7 +2554,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
return SDOperand(N, 0); // Don't revisit N.
// fold selects based on a setcc into other things, such as min/max/abs
- if (N0.getOpcode() == ISD::SETCC)
+ if (N0.getOpcode() == ISD::SETCC) {
// FIXME:
// Check against MVT::Other for SELECT_CC, which is a workaround for targets
// having to say they don't support SELECT_CC on every type the DAG knows
@@ -2562,6 +2564,7 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
N1, N2, N0.getOperand(2));
else
return SimplifySelect(N0, N1, N2);
+ }
return SDOperand();
}
@@ -4013,8 +4016,8 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
if (!((Use->getOpcode() == ISD::LOAD &&
cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
- (Use->getOpcode() == ISD::STORE) &&
- cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
+ (Use->getOpcode() == ISD::STORE &&
+ cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
RealUse = true;
}
if (!RealUse)
@@ -4131,8 +4134,8 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
SDNode *UseUse = *III;
if (!((UseUse->getOpcode() == ISD::LOAD &&
cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
- (UseUse->getOpcode() == ISD::STORE) &&
- cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
+ (UseUse->getOpcode() == ISD::STORE &&
+ cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)))
RealUse = true;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 2cda59758c..17aaa75c9e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1269,15 +1269,18 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
unsigned RScratch = calcMaxScratches(right);
if (LScratch > RScratch)
return true;
- else if (LScratch == RScratch)
+ else if (LScratch == RScratch) {
if (left->Height > right->Height)
return true;
- else if (left->Height == right->Height)
+ else if (left->Height == right->Height) {
if (left->Depth < right->Depth)
return true;
- else if (left->Depth == right->Depth)
+ else if (left->Depth == right->Depth) {
if (left->CycleBound > right->CycleBound)
return true;
+ }
+ }
+ }
}
}
return false;
@@ -1509,15 +1512,19 @@ bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
if (LPriority+LBonus < RPriority+RBonus)
return true;
- else if (LPriority == RPriority)
+ else if (LPriority == RPriority) {
if (left->Depth < right->Depth)
return true;
- else if (left->Depth == right->Depth)
+ else if (left->Depth == right->Depth) {
if (left->NumSuccsLeft > right->NumSuccsLeft)
return true;
- else if (left->NumSuccsLeft == right->NumSuccsLeft)
+ else if (left->NumSuccsLeft == right->NumSuccsLeft) {
if (left->CycleBound > right->CycleBound)
return true;
+ }
+ }
+ }
+
return false;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index eb3729c813..8a2962f0c3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1075,7 +1075,7 @@ SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1,
}
}
}
- if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val))
+ if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) {
// No compile time operations on this type yet.
if (N1C->getValueType(0) == MVT::ppcf128)
@@ -1127,7 +1127,8 @@ SDOperand SelectionDAG::FoldSetCC(MVT::ValueType VT, SDOperand N1,
// Ensure that the constant occurs on the RHS.
return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
}
-
+ }
+
// Could not fold it.
return SDOperand();
}
@@ -2334,20 +2335,22 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
break;
}
case ISD::SELECT:
- if (N1C)
- if (N1C->getValue())
+ if (N1C) {
+ if (N1C->getValue())
return N2; // select true, X, Y -> X
else
return N3; // select false, X, Y -> Y
+ }
if (N2 == N3) return N2; // select C, X, X -> X
break;
case ISD::BRCOND:
- if (N2C)
+ if (N2C) {
if (N2C->getValue()) // Unconditional branch
return getNode(ISD::BR, MVT::Other, N1, N3);
else
return N1; // Never-taken branch
+ }
break;
case ISD::VECTOR_SHUFFLE:
assert(VT == N1.getValueType() && VT == N2.getValueType() &&
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 1ee93d7bba..001c9f6c53 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2602,7 +2602,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
static GlobalVariable *ExtractTypeInfo (Value *V) {
V = IntrinsicInst::StripPointerCasts(V);
GlobalVariable *GV = dyn_cast<GlobalVariable>(V);
- assert (GV || isa<ConstantPointerNull>(V) &&
+ assert ((GV || isa<ConstantPointerNull>(V)) &&
"TypeInfo must be a global variable or NULL");
return GV;
}
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 253d5c16ff..e93bac4987 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -191,7 +191,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
MachineInstr &MI = *MII;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
- if (MO.isRegister() && MO.getReg())
+ if (MO.isRegister() && MO.getReg()) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned VirtReg = MO.getReg();
unsigned PhysReg = VRM.getPhys(VirtReg);
@@ -220,6 +220,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
} else {
MF.getRegInfo().setPhysRegUsed(MO.getReg());
}
+ }
}
DOUT << '\t' << MI;
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-13 17:02:05 +0000