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-rw-r--r--lib/CodeGen/BranchFolding.cpp2
-rw-r--r--lib/CodeGen/DwarfWriter.cpp1
-rw-r--r--lib/CodeGen/ELFWriter.cpp1
-rw-r--r--lib/CodeGen/LiveInterval.cpp1
-rw-r--r--lib/CodeGen/LiveIntervalAnalysis.cpp2
-rw-r--r--lib/CodeGen/LiveVariables.cpp1
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp14
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp1
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp1
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp6
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp2
13 files changed, 6 insertions, 30 deletions
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp
index 0ee7ee2f4b..97587d5012 100644
--- a/lib/CodeGen/BranchFolding.cpp
+++ b/lib/CodeGen/BranchFolding.cpp
@@ -766,7 +766,6 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// Analyze the branch at the end of the pred.
MachineBasicBlock *PredBB = *PI;
MachineFunction::iterator PredFallthrough = PredBB; ++PredFallthrough;
- MachineBasicBlock *PredTBB = 0, *PredFBB = 0;
std::vector<MachineOperand> PredCond;
if (PredBB != MBB && !CanFallThrough(PredBB)) {
MBB->moveAfter(PredBB);
@@ -781,7 +780,6 @@ void BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) {
// Analyze the branch at the end of the block before the succ.
MachineBasicBlock *SuccBB = *SI;
MachineFunction::iterator SuccPrev = SuccBB; --SuccPrev;
- MachineBasicBlock *SuccPrevTBB = 0, *SuccPrevFBB = 0;
std::vector<MachineOperand> SuccPrevCond;
if (SuccBB != MBB && !CanFallThrough(SuccPrev)) {
MBB->moveBefore(SuccBB);
diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp
index 43ea483a36..be51d9ff57 100644
--- a/lib/CodeGen/DwarfWriter.cpp
+++ b/lib/CodeGen/DwarfWriter.cpp
@@ -2132,7 +2132,6 @@ private:
} else {
EmitInt8(DW_CFA_def_cfa);
EOL("DW_CFA_def_cfa");
-
EmitULEB128Bytes(RI->getDwarfRegNum(Src.getRegister()));
EOL("Register");
}
diff --git a/lib/CodeGen/ELFWriter.cpp b/lib/CodeGen/ELFWriter.cpp
index 4f041c2737..5c58dd4fd7 100644
--- a/lib/CodeGen/ELFWriter.cpp
+++ b/lib/CodeGen/ELFWriter.cpp
@@ -113,7 +113,6 @@ void ELFCodeEmitter::startFunction(MachineFunction &F) {
// Add padding zeros to the end of the buffer to make sure that the
// function will start on the correct byte alignment within the section.
- size_t SectionOff = OutBuffer->size();
ELFWriter::align(*OutBuffer, Align);
FnStart = OutBuffer->size();
diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp
index 1834d6c015..8e3f888d00 100644
--- a/lib/CodeGen/LiveInterval.cpp
+++ b/lib/CodeGen/LiveInterval.cpp
@@ -289,7 +289,6 @@ void LiveInterval::join(LiveInterval &Other, int *LHSValNoAssignments,
//
// Also, if one range is a physreg and one is a vreg, we always merge from the
// vreg into the physreg, which leaves the vreg intervals pristine.
- unsigned OtherOffs = 1, ThisOffs = 0;
if ((Other.ranges.size() > ranges.size() &&
MRegisterInfo::isVirtualRegister(reg)) ||
MRegisterInfo::isPhysicalRegister(Other.reg)) {
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index aee2b1f4e0..99f7e4d285 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -184,7 +184,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
(RegRep = rep(srcReg)) == rep(dstReg)) {
// remove from def list
- LiveInterval &interval = getOrCreateInterval(RegRep);
+ getOrCreateInterval(RegRep);
RemoveMachineInstrFromMaps(mii);
mii = mbbi->erase(mii);
++numPeep;
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 5a73131b3e..29686558ad 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -223,7 +223,6 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
for (df_ext_iterator<MachineBasicBlock*> DFI = df_ext_begin(Entry, Visited),
E = df_ext_end(Entry, Visited); DFI != E; ++DFI) {
MachineBasicBlock *MBB = *DFI;
- unsigned BBNum = MBB->getNumber();
// Loop over all of the instructions, processing them.
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a4d3c54e1c..39090edea2 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1041,7 +1041,6 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
MVT::ValueType VT = N1.getValueType();
- unsigned OpSizeInBits = MVT::getSizeInBits(VT);
// fold (and c1, c2) -> c1&c2
if (N0C && N1C)
@@ -1319,7 +1318,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
if (Op.getOpcode() == ISD::AND) {
- if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+ if (isa<ConstantSDNode>(Op.getOperand(1))) {
Mask = Op.getOperand(1);
Op = Op.getOperand(0);
} else {
@@ -1856,9 +1855,6 @@ SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
SDOperand N2 = N->getOperand(2);
SDOperand N3 = N->getOperand(3);
SDOperand N4 = N->getOperand(4);
- ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
// fold select_cc lhs, rhs, x, x, cc -> x
@@ -1900,7 +1896,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
MVT::ValueType VT = N->getValueType(0);
// fold (sext c1) -> c1
- if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
+ if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
// fold (sext (sext x)) -> (sext x)
@@ -1958,7 +1954,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
MVT::ValueType VT = N->getValueType(0);
// fold (zext c1) -> c1
- if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
+ if (isa<ConstantSDNode>(N0))
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
// fold (zext (zext x)) -> (zext x)
// fold (zext (aext x)) -> (zext x)
@@ -3578,7 +3574,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
uint64_t C1 = N1C->getValue();
- if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
+ if (isa<ConstantSDNode>(N0.Val)) {
return DAG.FoldSetCC(VT, N0, N1, Cond);
} else {
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
@@ -3806,7 +3802,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
}
- if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) {
+ if (isa<ConstantFPSDNode>(N0.Val)) {
// Constant fold or commute setcc.
SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
if (O.Val) return O;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index cbb582478d..b1dfc90205 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3690,7 +3690,6 @@ SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
SmallVector<SDOperand, 8> Stores;
unsigned TypeByteSize =
MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
- unsigned VectorSize = MVT::getSizeInBits(VT)/8;
// Store (in the right endianness) the elements to memory.
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
// Ignore undef elements.
@@ -4802,7 +4801,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
- bool UseLibCall = true;
if (HasMULHS || HasMULHU) {
SDOperand LL, LH, RL, RH;
ExpandOp(Node->getOperand(0), LL, LH);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 7704a531af..7befa9c4ca 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -257,7 +257,6 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
// While Available queue is not empty, grab the node with the highest
// priority. If it is not ready put it back. Schedule the node.
std::vector<SUnit*> NotReady;
- SUnit *CurNode = NULL;
while (!AvailableQueue->empty()) {
SUnit *CurNode = AvailableQueue->pop();
while (CurNode && !isReady(CurNode, CurCycle)) {
@@ -373,7 +372,6 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
// While Available queue is not empty, grab the node with the highest
// priority. If it is not ready put it back. Schedule the node.
std::vector<SUnit*> NotReady;
- SUnit *CurNode = NULL;
while (!AvailableQueue->empty()) {
SUnit *CurNode = AvailableQueue->pop();
while (CurNode && !isReady(CurNode, CurCycle)) {
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
index efc828bd52..f48f4447ba 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
@@ -505,7 +505,6 @@ enum {
RSLoadStore = 0x0C000000, // Two load store units
RSBranch = 0x02000000 // One branch unit
};
-static InstrStage CallStage = { CallLatency, RSBranch };
static InstrStage LoadStage = { 5, RSLoadStore };
static InstrStage StoreStage = { 2, RSLoadStore };
static InstrStage IntStage = { 2, RSInteger };
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 16c0718c7d..bfd9a806c3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1956,7 +1956,6 @@ UpdateNodeOperands(SDOperand InN, SDOperand Op1, SDOperand Op2) {
assert(N->getNumOperands() == 2 && "Update with wrong number of operands");
// Check to see if there is no change.
- bool AnyChange = false;
if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1))
return InN; // No operands changed, just return the input node.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 99306050c1..d00b9966ed 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2343,11 +2343,6 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
MVT::Other);
- // Note, we treat inline asms both with and without side-effects as the same.
- // If an inline asm doesn't have side effects and doesn't access memory, we
- // could not choose to not chain it.
- bool hasSideEffects = IA->hasSideEffects();
-
std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
std::vector<MVT::ValueType> ConstraintVTs;
@@ -3124,7 +3119,6 @@ static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
static SDOperand getMemsetStringVal(MVT::ValueType VT,
SelectionDAG &DAG, TargetLowering &TLI,
std::string &Str, unsigned Offset) {
- MVT::ValueType CurVT = VT;
uint64_t Val = 0;
unsigned MSB = getSizeInBits(VT) / 8;
if (TLI.isLittleEndian())
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 129bcd9525..05abe96a59 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -504,7 +504,6 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
}
break;
case ISD::SIGN_EXTEND_INREG: {
- MVT::ValueType VT = Op.getValueType();
MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
@@ -852,7 +851,6 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
}
return;
case ISD::SIGN_EXTEND_INREG: {
- MVT::ValueType VT = Op.getValueType();
MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-13 13:15:43 +0000