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-rw-r--r--lib/CodeGen/LowerSubregs.cpp9
-rw-r--r--lib/CodeGen/MachineRegisterInfo.cpp6
-rw-r--r--lib/CodeGen/PHIElimination.cpp6
-rw-r--r--lib/CodeGen/ScheduleDAGEmit.cpp6
-rw-r--r--lib/CodeGen/SelectionDAG/FastISel.cpp22
-rw-r--r--lib/CodeGen/SelectionDAG/InstrEmitter.cpp8
-rw-r--r--lib/CodeGen/Spiller.cpp12
-rw-r--r--lib/CodeGen/StackSlotColoring.cpp6
-rw-r--r--lib/CodeGen/StrongPHIElimination.cpp8
-rw-r--r--lib/CodeGen/TailDuplication.cpp4
-rw-r--r--lib/CodeGen/TwoAddressInstructionPass.cpp3
-rw-r--r--lib/CodeGen/VirtRegRewriter.cpp9
12 files changed, 59 insertions, 40 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index b4ef648be6..b0348a5b75 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -140,7 +140,8 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
// Insert copy
const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
- bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS,
+ MI->getDebugLoc());
(void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed.
@@ -193,7 +194,8 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
// Insert sub-register copy
const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
- bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
+ MI->getDebugLoc());
(void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed.
@@ -262,7 +264,8 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(TargetOpcode::KILL), DstSubReg);
else {
- bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1,
+ MI->getDebugLoc());
(void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class");
}
diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp
index ea5ca0cad8..ef794d5ae3 100644
--- a/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/lib/CodeGen/MachineRegisterInfo.cpp
@@ -218,7 +218,8 @@ static void EmitLiveInCopy(MachineBasicBlock *MBB,
--Pos;
}
- bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC);
+ bool Emitted = TII.copyRegToReg(*MBB, Pos, VirtReg, PhysReg, RC, RC,
+ DebugLoc());
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
@@ -253,7 +254,8 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
if (LI->second) {
const TargetRegisterClass *RC = getRegClass(LI->second);
bool Emitted = TII.copyRegToReg(*EntryMBB, EntryMBB->begin(),
- LI->second, LI->first, RC, RC);
+ LI->second, LI->first, RC, RC,
+ DebugLoc());
assert(Emitted && "Unable to issue a live-in copy instruction!\n");
(void) Emitted;
}
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 00d2d71431..edbc13f3ff 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -210,7 +210,8 @@ void llvm::PHIElimination::LowerAtomicPHINode(
} else {
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
}
- TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
+ TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC,
+ MPhi->getDebugLoc());
}
// Update live variable information if there is any.
@@ -292,7 +293,8 @@ void llvm::PHIElimination::LowerAtomicPHINode(
// Insert the copy.
if (!reusedIncoming && IncomingReg)
- TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC);
+ TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC,
+ MPhi->getDebugLoc());
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
diff --git a/lib/CodeGen/ScheduleDAGEmit.cpp b/lib/CodeGen/ScheduleDAGEmit.cpp
index 8e034203f4..ee08e1dc0e 100644
--- a/lib/CodeGen/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/ScheduleDAGEmit.cpp
@@ -51,7 +51,8 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
}
}
bool Success = TII->copyRegToReg(*BB, InsertPos, Reg, VRI->second,
- SU->CopyDstRC, SU->CopySrcRC);
+ SU->CopyDstRC, SU->CopySrcRC,
+ DebugLoc());
(void)Success;
assert(Success && "copyRegToReg failed!");
} else {
@@ -62,7 +63,8 @@ void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
bool Success = TII->copyRegToReg(*BB, InsertPos, VRBase, I->getReg(),
- SU->CopyDstRC, SU->CopySrcRC);
+ SU->CopyDstRC, SU->CopySrcRC,
+ DebugLoc());
(void)Success;
assert(Success && "copyRegToReg failed!");
}
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 9cc6f1b5ec..2328ed034d 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -185,7 +185,7 @@ unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) {
else if (Reg != AssignedReg) {
const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
- Reg, RegClass, RegClass);
+ Reg, RegClass, RegClass, DL);
}
return AssignedReg;
}
@@ -413,7 +413,7 @@ bool FastISel::SelectCall(const User *I) {
const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
unsigned ResultReg = createResultReg(RC);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- Reg, RC, RC);
+ Reg, RC, RC, DL);
assert(InsertedCopy && "Can't copy address registers!");
InsertedCopy = InsertedCopy;
UpdateValueMap(I, ResultReg);
@@ -443,7 +443,7 @@ bool FastISel::SelectCall(const User *I) {
const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
unsigned ResultReg = createResultReg(RC);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
- RC, RC);
+ RC, RC, DL);
assert(InsertedCopy && "Can't copy address registers!");
InsertedCopy = InsertedCopy;
@@ -556,7 +556,7 @@ bool FastISel::SelectBitCast(const User *I) {
ResultReg = createResultReg(DstClass);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- Op0, DstClass, SrcClass);
+ Op0, DstClass, SrcClass, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -929,7 +929,7 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
else {
BuildMI(MBB, DL, II).addReg(Op0);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -948,7 +948,7 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
else {
BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -966,7 +966,7 @@ unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
else {
BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -984,7 +984,7 @@ unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
else {
BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -1002,7 +1002,7 @@ unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
else {
BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -1020,7 +1020,7 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
else {
BuildMI(MBB, DL, II).addImm(Imm);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
@@ -1039,7 +1039,7 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
else {
BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
- II.ImplicitDefs[0], RC, RC);
+ II.ImplicitDefs[0], RC, RC, DL);
if (!InsertedCopy)
ResultReg = 0;
}
diff --git a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index c5dae826ff..8f406a8174 100644
--- a/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -143,7 +143,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
// Create the reg, emit the copy.
VRBase = MRI->createVirtualRegister(DstRC);
bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
- DstRC, SrcRC);
+ DstRC, SrcRC, Node->getDebugLoc());
assert(Emitted && "Unable to issue a copy instruction!\n");
(void) Emitted;
@@ -289,7 +289,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
- DstRC, SrcRC);
+ DstRC, SrcRC, Op.getNode()->getDebugLoc());
assert(Emitted && "Unable to issue a copy instruction!\n");
(void) Emitted;
VReg = NewVReg;
@@ -503,7 +503,7 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
// Create the new VReg in the destination class and emit a copy.
unsigned NewVReg = MRI->createVirtualRegister(DstRC);
bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
- DstRC, SrcRC);
+ DstRC, SrcRC, Node->getDebugLoc());
assert(Emitted &&
"Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
(void) Emitted;
@@ -749,7 +749,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
Node->getOperand(1).getValueType());
bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
- DstTRC, SrcTRC);
+ DstTRC, SrcTRC, Node->getDebugLoc());
assert(Emitted && "Unable to issue a copy instruction!\n");
(void) Emitted;
break;
diff --git a/lib/CodeGen/Spiller.cpp b/lib/CodeGen/Spiller.cpp
index bc8b3aea34..735ca316fa 100644
--- a/lib/CodeGen/Spiller.cpp
+++ b/lib/CodeGen/Spiller.cpp
@@ -336,7 +336,8 @@ private:
// Insert a copy at the start of the MBB. The range proceeding the
// copy will be attached to the original LiveInterval.
MachineBasicBlock *defMBB = lis->getMBBFromIndex(newVNI->def);
- tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc);
+ tii->copyRegToReg(*defMBB, defMBB->begin(), newVReg, li->reg, trc, trc,
+ DebugLoc());
MachineInstr *copyMI = defMBB->begin();
copyMI->addRegisterKilled(li->reg, tri);
SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
@@ -389,7 +390,8 @@ private:
if (isTwoAddr && !twoAddrUseIsUndef) {
MachineBasicBlock *defMBB = defInst->getParent();
- tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc);
+ tii->copyRegToReg(*defMBB, defInst, newVReg, li->reg, trc, trc,
+ DebugLoc());
MachineInstr *copyMI = prior(MachineBasicBlock::iterator(defInst));
SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
copyMI->addRegisterKilled(li->reg, tri);
@@ -449,7 +451,8 @@ private:
// reg.
MachineBasicBlock *useMBB = useInst->getParent();
MachineBasicBlock::iterator useItr(useInst);
- tii->copyRegToReg(*useMBB, next(useItr), li->reg, newVReg, trc, trc);
+ tii->copyRegToReg(*useMBB, next(useItr), li->reg, newVReg, trc, trc,
+ DebugLoc());
MachineInstr *copyMI = next(useItr);
copyMI->addRegisterKilled(newVReg, tri);
SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
@@ -486,7 +489,8 @@ private:
assert(oldKillRange != 0 && "No kill range?");
tii->copyRegToReg(*killMBB, killMBB->getFirstTerminator(),
- li->reg, newVReg, trc, trc);
+ li->reg, newVReg, trc, trc,
+ DebugLoc());
MachineInstr *copyMI = prior(killMBB->getFirstTerminator());
copyMI->addRegisterKilled(newVReg, tri);
SlotIndex copyIdx = lis->InsertMachineInstrInMaps(copyMI);
diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp
index 42dfd7fbcb..3643dfb360 100644
--- a/lib/CodeGen/StackSlotColoring.cpp
+++ b/lib/CodeGen/StackSlotColoring.cpp
@@ -607,7 +607,8 @@ StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
DEBUG(MI->dump());
++NumLoadElim;
} else {
- TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC);
+ TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC,
+ MI->getDebugLoc());
++NumRegRepl;
}
@@ -623,7 +624,8 @@ StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
DEBUG(MI->dump());
++NumStoreElim;
} else {
- TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC);
+ TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC,
+ MI->getDebugLoc());
++NumRegRepl;
}
diff --git a/lib/CodeGen/StrongPHIElimination.cpp b/lib/CodeGen/StrongPHIElimination.cpp
index f8f6a55e9d..142398cc16 100644
--- a/lib/CodeGen/StrongPHIElimination.cpp
+++ b/lib/CodeGen/StrongPHIElimination.cpp
@@ -696,7 +696,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
// the Phi defining curr.second
MachineBasicBlock::iterator PI = MRI.getVRegDef(curr.second);
TII->copyRegToReg(*PI->getParent(), PI, t,
- curr.second, RC, RC);
+ curr.second, RC, RC, DebugLoc());
DEBUG(dbgs() << "Inserted copy from " << curr.second << " to " << t
<< "\n");
@@ -713,7 +713,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
// Insert copy from map[curr.first] to curr.second
TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), curr.second,
- map[curr.first], RC, RC);
+ map[curr.first], RC, RC, DebugLoc());
map[curr.first] = curr.second;
DEBUG(dbgs() << "Inserted copy from " << curr.first << " to "
<< curr.second << "\n");
@@ -762,7 +762,7 @@ void StrongPHIElimination::ScheduleCopies(MachineBasicBlock* MBB,
// Insert a copy from dest to a new temporary t at the end of b
unsigned t = MF->getRegInfo().createVirtualRegister(RC);
TII->copyRegToReg(*MBB, MBB->getFirstTerminator(), t,
- curr.second, RC, RC);
+ curr.second, RC, RC, DebugLoc());
map[curr.second] = t;
MachineBasicBlock::iterator TI = MBB->getFirstTerminator();
@@ -961,7 +961,7 @@ bool StrongPHIElimination::runOnMachineFunction(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(I->first);
TII->copyRegToReg(*SI->second, SI->second->getFirstTerminator(),
- I->first, SI->first, RC, RC);
+ I->first, SI->first, RC, RC, DebugLoc());
LI.renumber();
diff --git a/lib/CodeGen/TailDuplication.cpp b/lib/CodeGen/TailDuplication.cpp
index aa6e2b4e87..f2e2a76f00 100644
--- a/lib/CodeGen/TailDuplication.cpp
+++ b/lib/CodeGen/TailDuplication.cpp
@@ -561,7 +561,7 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF,
for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
const TargetRegisterClass *RC = MRI->getRegClass(CopyInfos[i].first);
TII->copyRegToReg(*PredBB, Loc, CopyInfos[i].first,
- CopyInfos[i].second, RC,RC);
+ CopyInfos[i].second, RC,RC, DebugLoc());
MachineInstr *CopyMI = prior(Loc);
Copies.push_back(CopyMI);
}
@@ -620,7 +620,7 @@ TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF,
for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
const TargetRegisterClass *RC = MRI->getRegClass(CopyInfos[i].first);
TII->copyRegToReg(*PrevBB, Loc, CopyInfos[i].first,
- CopyInfos[i].second, RC, RC);
+ CopyInfos[i].second, RC, RC, DebugLoc());
MachineInstr *CopyMI = prior(Loc);
Copies.push_back(CopyMI);
}
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 2b04104520..fde32da9ca 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1048,7 +1048,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
ReMatRegs.set(regB);
++NumReMats;
} else {
- bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
+ bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc,
+ mi->getDebugLoc());
(void)Emitted;
assert(Emitted && "Unable to issue a copy instruction!\n");
}
diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp
index 235db399b2..9b46273455 100644
--- a/lib/CodeGen/VirtRegRewriter.cpp
+++ b/lib/CodeGen/VirtRegRewriter.cpp
@@ -1794,7 +1794,8 @@ bool LocalRewriter::InsertRestores(MachineInstr *MI,
ComputeReloadLoc(MII, MBB->begin(), Phys, TRI, DoReMat, SSorRMId, TII,
*MBB->getParent());
- TII->copyRegToReg(*MBB, InsertLoc, Phys, InReg, RC, RC);
+ TII->copyRegToReg(*MBB, InsertLoc, Phys, InReg, RC, RC,
+ MI->getDebugLoc());
// This invalidates Phys.
Spills.ClobberPhysReg(Phys);
@@ -2139,7 +2140,8 @@ LocalRewriter::RewriteMBB(LiveIntervals *LIs,
ComputeReloadLoc(&MI, MBB->begin(), PhysReg, TRI, DoReMat,
SSorRMId, TII, MF);
- TII->copyRegToReg(*MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC);
+ TII->copyRegToReg(*MBB, InsertLoc, DesignatedReg, PhysReg, RC, RC,
+ MI.getDebugLoc());
MachineInstr *CopyMI = prior(InsertLoc);
CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
@@ -2263,7 +2265,8 @@ LocalRewriter::RewriteMBB(LiveIntervals *LIs,
DEBUG(dbgs() << "Promoted Load To Copy: " << MI);
if (DestReg != InReg) {
const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
- TII->copyRegToReg(*MBB, &MI, DestReg, InReg, RC, RC);
+ TII->copyRegToReg(*MBB, &MI, DestReg, InReg, RC, RC,
+ MI.getDebugLoc());
MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
unsigned SubIdx = DefMO->getSubReg();
// Revisit the copy so we make sure to notice the effects of the
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-18 07:23:45 +0000