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-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp2
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp22
2 files changed, 11 insertions, 13 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d2fe4718da..f05f4445a8 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -318,7 +318,7 @@ static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC) {
/// AddNodeIDValueTypes - Value type lists are intern'd so we can represent them
/// solely with their pointer.
-void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
+static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList) {
ID.AddPointer(VTList.VTs);
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 241ad7e8a9..f79ad0290a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -74,18 +74,16 @@ MachinePassRegistry RegisterScheduler::Registry;
/// ISHeuristic command line option for instruction schedulers.
///
//===---------------------------------------------------------------------===//
-namespace {
- static cl::opt<RegisterScheduler::FunctionPassCtor, false,
- RegisterPassParser<RegisterScheduler> >
- ISHeuristic("pre-RA-sched",
- cl::init(&createDefaultScheduler),
- cl::desc("Instruction schedulers available (before register"
- " allocation):"));
-
- static RegisterScheduler
- defaultListDAGScheduler("default", " Best scheduler for the target",
- createDefaultScheduler);
-} // namespace
+static cl::opt<RegisterScheduler::FunctionPassCtor, false,
+ RegisterPassParser<RegisterScheduler> >
+ISHeuristic("pre-RA-sched",
+ cl::init(&createDefaultScheduler),
+ cl::desc("Instruction schedulers available (before register"
+ " allocation):"));
+
+static RegisterScheduler
+defaultListDAGScheduler("default", " Best scheduler for the target",
+ createDefaultScheduler);
namespace { struct SDISelAsmOperandInfo; }