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-rw-r--r--include/llvm/CodeGen/Passes.h104
-rw-r--r--include/llvm/Target/TargetMachine.h80
2 files changed, 114 insertions, 70 deletions
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 2259ebffc2..082bada1c3 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -26,7 +26,111 @@ namespace llvm {
class TargetLowering;
class TargetRegisterClass;
class raw_ostream;
+}
+namespace llvm {
+
+/// Target-Independent Code Generator Pass Configuration Options.
+///
+/// FIXME: Why are we passing the DisableVerify flags around instead of setting
+/// an options in the target machine, like all the other driver options?
+class TargetPassConfig {
+protected:
+ TargetMachine *TM;
+ PassManagerBase ±
+ bool DisableVerify;
+
+public:
+ TargetPassConfig(TargetMachine *tm, PassManagerBase &pm,
+ bool DisableVerifyFlag)
+ : TM(tm), PM(pm), DisableVerify(DisableVerifyFlag) {}
+
+ virtual ~TargetPassConfig() {}
+
+ /// Get the right type of TargetMachine for this target.
+ template<typename TMC> TMC &getTM() const {
+ return *static_cast<TMC*>(TM);
+ }
+
+ CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
+
+ const TargetLowering *getTargetLowering() const { return TM->getTargetLowering(); }
+
+ /// Add the complete, standard set of LLVM CodeGen passes.
+ /// Fully developed targets will not generally override this.
+ virtual bool addCodeGenPasses(MCContext *&OutContext);
+
+protected:
+ /// Convenient points in the common codegen pass pipeline for inserting
+ /// passes, and major CodeGen stages that some targets may override.
+ ///
+
+ /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
+ /// passes (which are run just before instruction selector).
+ virtual bool addPreISel() {
+ return true;
+ }
+
+ /// addInstSelector - This method should install an instruction selector pass,
+ /// which converts from LLVM code to machine instructions.
+ virtual bool addInstSelector() {
+ return true;
+ }
+
+ /// addPreRegAlloc - This method may be implemented by targets that want to
+ /// run passes immediately before register allocation. This should return
+ /// true if -print-machineinstrs should print after these passes.
+ virtual bool addPreRegAlloc() {
+ return false;
+ }
+
+ /// addPostRegAlloc - This method may be implemented by targets that want
+ /// to run passes after register allocation but before prolog-epilog
+ /// insertion. This should return true if -print-machineinstrs should print
+ /// after these passes.
+ virtual bool addPostRegAlloc() {
+ return false;
+ }
+
+ /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
+ /// on this target. User flag overrides.
+ virtual bool getEnableTailMergeDefault() const { return true; }
+
+ /// addPreSched2 - This method may be implemented by targets that want to
+ /// run passes after prolog-epilog insertion and before the second instruction
+ /// scheduling pass. This should return true if -print-machineinstrs should
+ /// print after these passes.
+ virtual bool addPreSched2() {
+ return false;
+ }
+
+ /// addPreEmitPass - This pass may be implemented by targets that want to run
+ /// passes immediately before machine code is emitted. This should return
+ /// true if -print-machineinstrs should print out the code after the passes.
+ virtual bool addPreEmitPass() {
+ return false;
+ }
+
+ /// Utilities for targets to add passes to the pass manager.
+ ///
+
+ /// Add a target-independent CodeGen pass at this point in the pipeline.
+ void addCommonPass(char &ID);
+
+ /// printNoVerify - Add a pass to dump the machine function, if debugging is
+ /// enabled.
+ ///
+ void printNoVerify(const char *Banner) const;
+
+ /// printAndVerify - Add a pass to dump then verify the machine function, if
+ /// those steps are enabled.
+ ///
+ void printAndVerify(const char *Banner) const;
+};
+} // namespace llvm
+
+/// List of target independent CodeGen pass IDs.
+namespace llvm {
/// createUnreachableBlockEliminationPass - The LLVM code generator does not
/// work well with unreachable basic blocks (what live ranges make sense for a
/// block that cannot be reached?). As such, a code generator should either
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index 61c60c5c73..afb15c0895 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -38,6 +38,7 @@ class TargetInstrInfo;
class TargetIntrinsicInfo;
class TargetJITInfo;
class TargetLowering;
+class TargetPassConfig;
class TargetRegisterInfo;
class TargetSelectionDAGInfo;
class TargetSubtargetInfo;
@@ -200,6 +201,10 @@ public:
/// Default, or Aggressive.
CodeGenOpt::Level getOptLevel() const;
+ void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
+
+ bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
+
/// getAsmVerbosityDefault - Returns the default value of asm verbosity.
///
static bool getAsmVerbosityDefault();
@@ -232,10 +237,6 @@ public:
CGFT_Null // Do not emit any output.
};
- /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
- /// on this target. User flag overrides.
- virtual bool getEnableTailMergeDefault() const { return true; }
-
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
/// generation. This method should return true if emission of this file type
@@ -282,24 +283,12 @@ protected: // Can only create subclasses.
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
- /// printNoVerify - Add a pass to dump the machine function, if debugging is
- /// enabled.
- ///
- void printNoVerify(PassManagerBase &PM, const char *Banner) const;
-
- /// printAndVerify - Add a pass to dump then verify the machine function, if
- /// those steps are enabled.
- ///
- void printAndVerify(PassManagerBase &PM, const char *Banner) const;
-
-private:
- /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
- /// both emitting to assembly files or machine code output.
- ///
- bool addCommonCodeGenPasses(PassManagerBase &,
- bool DisableVerify, MCContext *&OutCtx);
-
public:
+ /// createPassConfig - Create a pass configuration object to be used by
+ /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
+ virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
+ bool DisableVerify);
+
/// addPassesToEmitFile - Add passes to the specified pass manager to get the
/// specified file emitted. Typically this will involve several steps of code
/// generation.
@@ -328,51 +317,6 @@ public:
raw_ostream &OS,
bool DisableVerify = true);
- /// Target-Independent Code Generator Pass Configuration Options.
-
- /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
- /// passes (which are run just before instruction selector).
- virtual bool addPreISel(PassManagerBase &) {
- return true;
- }
-
- /// addInstSelector - This method should install an instruction selector pass,
- /// which converts from LLVM code to machine instructions.
- virtual bool addInstSelector(PassManagerBase &) {
- return true;
- }
-
- /// addPreRegAlloc - This method may be implemented by targets that want to
- /// run passes immediately before register allocation. This should return
- /// true if -print-machineinstrs should print after these passes.
- virtual bool addPreRegAlloc(PassManagerBase &) {
- return false;
- }
-
- /// addPostRegAlloc - This method may be implemented by targets that want
- /// to run passes after register allocation but before prolog-epilog
- /// insertion. This should return true if -print-machineinstrs should print
- /// after these passes.
- virtual bool addPostRegAlloc(PassManagerBase &) {
- return false;
- }
-
- /// addPreSched2 - This method may be implemented by targets that want to
- /// run passes after prolog-epilog insertion and before the second instruction
- /// scheduling pass. This should return true if -print-machineinstrs should
- /// print after these passes.
- virtual bool addPreSched2(PassManagerBase &) {
- return false;
- }
-
- /// addPreEmitPass - This pass may be implemented by targets that want to run
- /// passes immediately before machine code is emitted. This should return
- /// true if -print-machineinstrs should print out the code after the passes.
- virtual bool addPreEmitPass(PassManagerBase &) {
- return false;
- }
-
-
/// addCodeEmitter - This pass should be overridden by the target to add a
/// code emitter, if supported. If this is not supported, 'true' should be
/// returned.
@@ -380,10 +324,6 @@ public:
JITCodeEmitter &) {
return true;
}
-
- /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
- /// on this target. User flag overrides.
- virtual bool getEnableTailMergeDefault() const { return true; }
};
} // End llvm namespace
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-11 22:00:12 +0000