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-rw-r--r--include/llvm/Target/TargetInstrInfo.h12
1 files changed, 7 insertions, 5 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index bb1dfd2b36..5fe9130634 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -395,19 +395,21 @@ public:
/// isPredicable - Returns true if the instruction is already predicated.
///
- virtual bool isPredicated(MachineInstr *MI) const {
+ virtual bool isPredicated(const MachineInstr *MI) const {
return false;
}
/// PredicateInstruction - Convert the instruction into a predicated
/// instruction. It returns true if the operation was successful.
- virtual bool PredicateInstruction(MachineInstr *MI,
- std::vector<MachineOperand> &Pred) const;
+ virtual
+ bool PredicateInstruction(MachineInstr *MI,
+ const std::vector<MachineOperand> &Pred) const;
/// SubsumesPredicate - Returns true if the first specified predicated
/// subsumes the second, e.g. GE subsumes GT.
- virtual bool SubsumesPredicate(std::vector<MachineOperand> &Pred1,
- std::vector<MachineOperand> &Pred2) const {
+ virtual
+ bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
+ const std::vector<MachineOperand> &Pred2) const {
return false;
}