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-rw-r--r--include/llvm/CodeGen/LinkAllCodegenComponents.h14
-rw-r--r--include/llvm/CodeGen/MachinePassRegistry.h44
-rw-r--r--include/llvm/CodeGen/ScheduleDAG.h20
-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h4
4 files changed, 51 insertions, 31 deletions
diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 82b5da9f0b..17212c45f7 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -32,15 +32,15 @@ namespace {
(void) llvm::createLocalRegisterAllocator();
(void) llvm::createLinearScanRegisterAllocator();
- (void) llvm::createBFS_DAGScheduler(NULL, NULL);
- (void) llvm::createSimpleDAGScheduler(NULL, NULL);
- (void) llvm::createNoItinsDAGScheduler(NULL, NULL);
- (void) llvm::createBURRListDAGScheduler(NULL, NULL);
- (void) llvm::createTDRRListDAGScheduler(NULL, NULL);
- (void) llvm::createTDListDAGScheduler(NULL, NULL);
+ (void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createSimpleDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createNoItinsDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
+ (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
}
} ForceCodegenLinking; // Force link by creating a global definition.
}
-#endif \ No newline at end of file
+#endif
diff --git a/include/llvm/CodeGen/MachinePassRegistry.h b/include/llvm/CodeGen/MachinePassRegistry.h
index e8c385d7e4..97ecaae184 100644
--- a/include/llvm/CodeGen/MachinePassRegistry.h
+++ b/include/llvm/CodeGen/MachinePassRegistry.h
@@ -2,10 +2,18 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
+// This file was developed by the James M. Laskey and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the mechanics for machine function pass registries. A
+// function pass registry (MachinePassRegistry) is auto filled by the static
+// constructors of MachinePassRegistryNode. Further there is a command line
+// parser (RegisterPassParser) which listens to each registry for additions
+// and deletions, so that the appropriate command option is updated.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_MACHINEPASSREGISTRY_H
#define LLVM_CODEGEN_MACHINEPASSREGISTRY_H
@@ -14,8 +22,6 @@
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/CommandLine.h"
-#include <iostream>
-
namespace llvm {
@@ -83,7 +89,7 @@ private:
MachinePassRegistryNode<FunctionPassCtor> *List;
// List of registry nodes.
- FunctionPassCtor Cache; // Cached function pass creator.
+ FunctionPassCtor Default; // Default function pass creator.
MachinePassRegistryListener* Listener;// Listener for list adds are removes.
public:
@@ -94,8 +100,8 @@ public:
// Accessors.
//
MachinePassRegistryNode<FunctionPassCtor> *getList() { return List; }
- FunctionPassCtor getCache() { return Cache; }
- void setCache(FunctionPassCtor C) { Cache = C; }
+ FunctionPassCtor getDefault() { return Default; }
+ void setDefault(FunctionPassCtor C) { Default = C; }
void setListener(MachinePassRegistryListener *L) { Listener = L; }
/// Add - Adds a function pass to the registration list.
@@ -113,10 +119,8 @@ public:
for (MachinePassRegistryNode<FunctionPassCtor> **I = &List;
*I; I = (*I)->getNextAddress()) {
if (*I == Node) {
-#if 0 // FIXME: Command opt needs to call a termination routine.
if (Listener) Listener->NotifyRemove(Node->getName(),
Node->getDescription());
-#endif
*I = (*I)->getNext();
break;
}
@@ -166,11 +170,11 @@ public:
static RegisterRegAlloc *getList() {
return (RegisterRegAlloc *)Registry.getList();
}
- static FunctionPassCtor getCache() {
- return Registry.getCache();
+ static FunctionPassCtor getDefault() {
+ return Registry.getDefault();
}
- static void setCache(FunctionPassCtor C) {
- Registry.setCache(C);
+ static void setDefault(FunctionPassCtor C) {
+ Registry.setDefault(C);
}
static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L);
@@ -200,16 +204,19 @@ public:
///
//===----------------------------------------------------------------------===//
+class SelectionDAGISel;
class ScheduleDAG;
class SelectionDAG;
class MachineBasicBlock;
class RegisterScheduler : public
- MachinePassRegistryNode<ScheduleDAG *(*)(SelectionDAG*, MachineBasicBlock*)> {
+ MachinePassRegistryNode<
+ ScheduleDAG *(*)(SelectionDAGISel*, SelectionDAG*, MachineBasicBlock*)> {
public:
- typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAG*, MachineBasicBlock*);
+ typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
+ MachineBasicBlock*);
static MachinePassRegistry<FunctionPassCtor> Registry;
@@ -228,11 +235,11 @@ public:
static RegisterScheduler *getList() {
return (RegisterScheduler *)Registry.getList();
}
- static FunctionPassCtor getCache() {
- return Registry.getCache();
+ static FunctionPassCtor getDefault() {
+ return Registry.getDefault();
}
- static void setCache(FunctionPassCtor C) {
- Registry.setCache(C);
+ static void setDefault(FunctionPassCtor C) {
+ Registry.setDefault(C);
}
static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L);
@@ -267,6 +274,7 @@ class RegisterPassParser : public MachinePassRegistryListener,
public cl::parser<const char *> {
public:
RegisterPassParser() {}
+ ~RegisterPassParser() { RegistryClass::setListener(NULL); }
void initialize(cl::Option &O) {
cl::parser<const char *>::initialize(O);
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 1146c327a6..a1214db8a8 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -26,6 +26,7 @@ namespace llvm {
class MachineInstr;
class MRegisterInfo;
class SelectionDAG;
+ class SelectionDAGISel;
class SSARegMap;
class TargetInstrInfo;
class TargetInstrDescriptor;
@@ -223,31 +224,38 @@ namespace llvm {
/// createBFS_DAGScheduler - This creates a simple breadth first instruction
/// scheduler.
- ScheduleDAG *createBFS_DAGScheduler(SelectionDAG *DAG, MachineBasicBlock *BB);
+ ScheduleDAG *createBFS_DAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
+ MachineBasicBlock *BB);
/// createSimpleDAGScheduler - This creates a simple two pass instruction
/// scheduler using instruction itinerary.
- ScheduleDAG* createSimpleDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createSimpleDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createNoItinsDAGScheduler - This creates a simple two pass instruction
/// scheduler without using instruction itinerary.
- ScheduleDAG* createNoItinsDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createNoItinsDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createBURRListDAGScheduler - This creates a bottom up register usage
/// reduction list scheduler.
- ScheduleDAG* createBURRListDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createTDRRListDAGScheduler - This creates a top down register usage
/// reduction list scheduler.
- ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
/// createTDListDAGScheduler - This creates a top-down list scheduler with
/// a hazard recognizer.
- ScheduleDAG* createTDListDAGScheduler(SelectionDAG *DAG,
+ ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
+ SelectionDAG *DAG,
MachineBasicBlock *BB);
}
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index cd8e5f4989..78179c9e2a 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -67,6 +67,10 @@ public:
/// folded during instruction selection?
virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
+ /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
+ /// to use for this target when scheduling the DAG.
+ virtual HazardRecognizer *CreateTargetHazardRecognizer();
+
/// CaseBlock - This structure is used to communicate between SDLowering and
/// SDISel for the code generation of additional basic blocks needed by multi-
/// case switch statements.
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-14 06:19:36 +0000