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-rw-r--r--include/llvm/CodeGen/AsmPrinter.h6
-rw-r--r--include/llvm/CodeGen/PBQP/HeuristicBase.h14
-rw-r--r--include/llvm/CodeGen/ScheduleDAG.h3
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h2
-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h12
-rw-r--r--include/llvm/CodeGen/ValueTypes.h13
6 files changed, 22 insertions, 28 deletions
diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index 50bb8e4801..8e64ee1c47 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -18,6 +18,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/ErrorHandling.h"
namespace llvm {
class BlockAddress;
@@ -37,7 +38,6 @@ namespace llvm {
class MachineModuleInfo;
class MachineMove;
class MCAsmInfo;
- class MCInst;
class MCContext;
class MCSection;
class MCStreamer;
@@ -49,8 +49,6 @@ namespace llvm {
class TargetLoweringObjectFile;
class TargetData;
class TargetMachine;
- class Twine;
- class Type;
/// AsmPrinter - This class is intended to be used as a driving class for all
/// asm writers.
@@ -254,7 +252,7 @@ namespace llvm {
/// EmitInstruction - Targets should implement this to emit instructions.
virtual void EmitInstruction(const MachineInstr *) {
- assert(0 && "EmitInstruction not implemented");
+ llvm_unreachable("EmitInstruction not implemented");
}
virtual void EmitFunctionEntryLabel();
diff --git a/include/llvm/CodeGen/PBQP/HeuristicBase.h b/include/llvm/CodeGen/PBQP/HeuristicBase.h
index 791c227f0d..3fee18cc42 100644
--- a/include/llvm/CodeGen/PBQP/HeuristicBase.h
+++ b/include/llvm/CodeGen/PBQP/HeuristicBase.h
@@ -157,7 +157,7 @@ namespace PBQP {
case 0: s.applyR0(nItr); break;
case 1: s.applyR1(nItr); break;
case 2: s.applyR2(nItr); break;
- default: assert(false &&
+ default: llvm_unreachable(
"Optimal reductions of degree > 2 nodes is invalid.");
}
@@ -186,7 +186,7 @@ namespace PBQP {
/// \brief Add a node to the heuristic reduce list.
/// @param nItr Node iterator to add to the heuristic reduce list.
void addToHeuristicList(Graph::NodeItr nItr) {
- assert(false && "Must be implemented in derived class.");
+ llvm_unreachable("Must be implemented in derived class.");
}
/// \brief Heuristically reduce one of the nodes in the heuristic
@@ -194,25 +194,25 @@ namespace PBQP {
/// @return True if a reduction takes place, false if the heuristic reduce
/// list is empty.
void heuristicReduce() {
- assert(false && "Must be implemented in derived class.");
+ llvm_unreachable("Must be implemented in derived class.");
}
/// \brief Prepare a change in the costs on the given edge.
/// @param eItr Edge iterator.
void preUpdateEdgeCosts(Graph::EdgeItr eItr) {
- assert(false && "Must be implemented in derived class.");
+ llvm_unreachable("Must be implemented in derived class.");
}
/// \brief Handle the change in the costs on the given edge.
/// @param eItr Edge iterator.
void postUpdateEdgeCostts(Graph::EdgeItr eItr) {
- assert(false && "Must be implemented in derived class.");
+ llvm_unreachable("Must be implemented in derived class.");
}
/// \brief Handle the addition of a new edge into the PBQP graph.
/// @param eItr Edge iterator for the added edge.
void handleAddEdge(Graph::EdgeItr eItr) {
- assert(false && "Must be implemented in derived class.");
+ llvm_unreachable("Must be implemented in derived class.");
}
/// \brief Handle disconnection of an edge from a node.
@@ -223,7 +223,7 @@ namespace PBQP {
/// method allows for the effect to be computed only for the remaining
/// node in the graph.
void handleRemoveEdge(Graph::EdgeItr eItr, Graph::NodeItr nItr) {
- assert(false && "Must be implemented in derived class.");
+ llvm_unreachable("Must be implemented in derived class.");
}
/// \brief Clean up any structures used by HeuristicBase.
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 58a3a9cb59..fdf40c7128 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -128,9 +128,8 @@ namespace llvm {
Other.Contents.Order.isNormalMemory &&
Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
+ default: llvm_unreachable("Invalid dependency kind!");
}
- assert(0 && "Invalid dependency kind!");
- return false;
}
bool operator!=(const SDep &Other) const {
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 8ffca4484d..f921ca20be 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -51,7 +51,7 @@ public:
static void noteHead(SDNode*, SDNode*) {}
static void deleteNode(SDNode *) {
- assert(0 && "ilist_traits<SDNode> shouldn't see a deleteNode call!");
+ llvm_unreachable("ilist_traits<SDNode> shouldn't see a deleteNode call!");
}
private:
static void createNode(const SDNode &);
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index c466175b68..ee3f2319c0 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -240,8 +240,7 @@ public:
/// succeeds or false if it fails. The number is a private implementation
/// detail to the code tblgen produces.
virtual bool CheckPatternPredicate(unsigned PredNo) const {
- assert(0 && "Tblgen should generate the implementation of this!");
- return 0;
+ llvm_unreachable("Tblgen should generate the implementation of this!");
}
/// CheckNodePredicate - This function is generated by tblgen in the target.
@@ -249,20 +248,17 @@ public:
/// false if it fails. The number is a private implementation
/// detail to the code tblgen produces.
virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
- assert(0 && "Tblgen should generate the implementation of this!");
- return 0;
+ llvm_unreachable("Tblgen should generate the implementation of this!");
}
virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
unsigned PatternNo,
SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
- assert(0 && "Tblgen should generate the implementation of this!");
- return false;
+ llvm_unreachable("Tblgen should generate the implementation of this!");
}
virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
- assert(0 && "Tblgen should generate this!");
- return SDValue();
+ llvm_unreachable("Tblgen should generate this!");
}
SDNode *SelectCodeCommon(SDNode *NodeToMatch,
diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index eb0793ed25..d163403145 100644
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -16,10 +16,11 @@
#ifndef LLVM_CODEGEN_VALUETYPES_H
#define LLVM_CODEGEN_VALUETYPES_H
-#include <cassert>
-#include <string>
#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
+#include <cassert>
+#include <string>
namespace llvm {
class Type;
@@ -246,13 +247,13 @@ namespace llvm {
unsigned getSizeInBits() const {
switch (SimpleTy) {
case iPTR:
- assert(0 && "Value type size is target-dependent. Ask TLI.");
+ llvm_unreachable("Value type size is target-dependent. Ask TLI.");
case iPTRAny:
case iAny:
case fAny:
- assert(0 && "Value type is overloaded.");
+ llvm_unreachable("Value type is overloaded.");
default:
- assert(0 && "getSizeInBits called on extended MVT.");
+ llvm_unreachable("getSizeInBits called on extended MVT.");
case i1 : return 1;
case i8 : return 8;
case i16 :
@@ -306,7 +307,7 @@ namespace llvm {
static MVT getFloatingPointVT(unsigned BitWidth) {
switch (BitWidth) {
default:
- assert(false && "Bad bit width!");
+ llvm_unreachable("Bad bit width!");
case 16:
return MVT::f16;
case 32:
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-13 23:07:24 +0000