diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fcopysign.ll | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index e0995aee93..853716b8f6 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2905,7 +2905,7 @@ SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); - if (SrcVT == MVT::f32) { + if (VT == MVT::f32) { Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, DAG.getConstant(0, MVT::i32)); diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index d30e3ebf50..11b96b8570 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -40,5 +40,19 @@ entry: ret double %1 } +; rdar://9059537 +define i32 @test4() ssp { +entry: +; SOFT: test4: +; SOFT: vcvt.f32.f64 s0, +; SOFT: vmov.i32 [[REG4:(d[0-9]+)]], #0x80000000 +; SOFT: vbic [[REG5:(d[0-9]+))], d0, [[REG4]] +; SOFT: vorr d0, [[REG4]], [[REG5]] + %call80 = tail call double @copysign(double 1.000000e+00, double undef) + %conv81 = fptrunc double %call80 to float + %tmp88 = bitcast float %conv81 to i32 + ret i32 %tmp88 +} + declare double @copysign(double, double) nounwind declare float @copysignf(float, float) nounwind |