diff options
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.h | 6 |
2 files changed, 16 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 13f7903402..574c14e00c 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -256,8 +256,8 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI, const TargetInstrDesc &TID, unsigned Binary) { - // FIXME: Assume CC is AL for now. - Binary |= ARMCC::AL << 28; + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << 28; switch (TID.TSFlags & ARMII::FormMask) { default: @@ -376,8 +376,8 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI, const TargetInstrDesc &TID, unsigned Binary) { - // FIXME: Assume CC is AL for now. - Binary |= ARMCC::AL << 28; + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << 28; // Encode S bit if MI modifies CPSR. Binary |= getAddrMode1SBit(MI, TID); @@ -429,8 +429,8 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI, const TargetInstrDesc &TID, unsigned Binary) { - // FIXME: Assume CC is AL for now. - Binary |= ARMCC::AL << 28; + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << 28; // Set first operand Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; @@ -470,8 +470,8 @@ unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI, const TargetInstrDesc &TID, unsigned Binary) { - // FIXME: Assume CC is AL for now. - Binary |= ARMCC::AL << 28; + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << 28; // Set first operand Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; @@ -507,8 +507,8 @@ unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI, unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI, const TargetInstrDesc &TID, unsigned Binary) { - // FIXME: Assume CC is AL for now. - Binary |= ARMCC::AL << 28; + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << 28; // Set first operand Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 0b27bfbcdc..da22521b83 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -217,6 +217,12 @@ public: // Predication support. virtual bool isPredicated(const MachineInstr *MI) const; + ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { + int PIdx = MI->findFirstPredOperandIdx(); + return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() + : ARMCC::AL; + } + virtual bool PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Pred) const; |