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| author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
| commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
| tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/SPARC/inlineasm.ll | |
| parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
| download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip | |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/SPARC/inlineasm.ll')
| -rw-r--r-- | test/CodeGen/SPARC/inlineasm.ll | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/test/CodeGen/SPARC/inlineasm.ll b/test/CodeGen/SPARC/inlineasm.ll new file mode 100644 index 0000000000..2650533b7f --- /dev/null +++ b/test/CodeGen/SPARC/inlineasm.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=sparc <%s | FileCheck %s + +; CHECK-LABEL: test_constraint_r +; CHECK: add %o1, %o0, %o0 +define i32 @test_constraint_r(i32 %a, i32 %b) { +entry: + %0 = tail call i32 asm sideeffect "add $2, $1, $0", "=r,r,r"(i32 %a, i32 %b) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_I +; CHECK: add %o0, 1023, %o0 +define i32 @test_constraint_I(i32 %a) { +entry: + %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 1023) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_I_neg +; CHECK: add %o0, -4096, %o0 +define i32 @test_constraint_I_neg(i32 %a) { +entry: + %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 -4096) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_I_largeimm +; CHECK: sethi 9, [[R0:%[gilo][0-7]]] +; CHECK: or [[R0]], 784, [[R1:%[gilo][0-7]]] +; CHECK: add %o0, [[R1]], %o0 +define i32 @test_constraint_I_largeimm(i32 %a) { +entry: + %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000) + ret i32 %0 +} + +; CHECK-LABEL: test_constraint_reg +; CHECK: ldda [%o1] 43, %g2 +; CHECK: ldda [%o1] 43, %g3 +define void @test_constraint_reg(i32 %s, i32* %ptr) { +entry: + %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43) + %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43) + ret void +} |