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authorStephen Hines <srhines@google.com>2014-12-01 14:51:49 -0800
committerStephen Hines <srhines@google.com>2014-12-02 16:08:10 -0800
commit37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch)
tree8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/ARM/smulw.ll
parentd2327b22152ced7bc46dc629fc908959e8a52d03 (diff)
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Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/ARM/smulw.ll')
-rw-r--r--test/CodeGen/ARM/smulw.ll26
1 files changed, 26 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/smulw.ll b/test/CodeGen/ARM/smulw.ll
new file mode 100644
index 0000000000..8653903eee
--- /dev/null
+++ b/test/CodeGen/ARM/smulw.ll
@@ -0,0 +1,26 @@
+; RUN: llc -mtriple=arm--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
+
+; We cannot codegen the smulw[bt] or smlaw[bt] instructions for these functions,
+; as the top 16 bits of the result would differ
+
+define i32 @f1(i32 %a, i16 %b) {
+; CHECK-LABEL: f1:
+; CHECK: mul
+; CHECK: asr
+ %tmp1 = sext i16 %b to i32
+ %tmp2 = mul i32 %a, %tmp1
+ %tmp3 = ashr i32 %tmp2, 16
+ ret i32 %tmp3
+}
+
+define i32 @f2(i32 %a, i16 %b, i32 %c) {
+; CHECK-LABEL: f2:
+; CHECK: mul
+; CHECK: add{{.*}}, asr #16
+ %tmp1 = sext i16 %b to i32
+ %tmp2 = mul i32 %a, %tmp1
+ %tmp3 = ashr i32 %tmp2, 16
+ %tmp4 = add i32 %tmp3, %c
+ ret i32 %tmp4
+}