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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/CodeGen/ARM/intrinsics-overflow.ll | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/CodeGen/ARM/intrinsics-overflow.ll')
| -rw-r--r-- | test/CodeGen/ARM/intrinsics-overflow.ll | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/intrinsics-overflow.ll b/test/CodeGen/ARM/intrinsics-overflow.ll new file mode 100644 index 0000000000..af3dd9dd41 --- /dev/null +++ b/test/CodeGen/ARM/intrinsics-overflow.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -mtriple=arm-linux -mcpu=generic | FileCheck %s + +define i32 @uadd_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: uadd_overflow: + ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; CHECK: mov r[[R1]], #1 + ; CHECK: cmp r[[R2]], r[[R0]] + ; CHECK: movhs r[[R1]], #0 +} + + +define i32 @sadd_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: sadd_overflow: + ; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]] + ; CHECK: mov r[[R1]], #1 + ; CHECK: cmp r[[R2]], r[[R0]] + ; CHECK: movvc r[[R1]], #0 +} + +define i32 @usub_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: usub_overflow: + ; CHECK: mov r[[R2]], #1 + ; CHECK: cmp r[[R0]], r[[R1]] + ; CHECK: movhs r[[R2]], #0 +} + +define i32 @ssub_overflow(i32 %a, i32 %b) #0 { + %sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) + %1 = extractvalue { i32, i1 } %sadd, 1 + %2 = zext i1 %1 to i32 + ret i32 %2 + + ; CHECK-LABEL: ssub_overflow: + ; CHECK: mov r[[R2]], #1 + ; CHECK: cmp r[[R0]], r[[R1]] + ; CHECK: movvc r[[R2]], #0 +} + +declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1 +declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2 +declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3 +declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4 |