Handle the rest of pseudo instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59275 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 71 insertions, 54 deletions

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 4bbf3018c2..4d87efed8b 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -302,9 +302,10 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
 
   NumEmitted++;  // Keep track of the # of mi's emitted
   switch (MI.getDesc().TSFlags & ARMII::FormMask) {
-  default:
+  default: {
     assert(0 && "Unhandled instruction encoding format!");
     break;
+  }
   case ARMII::Pseudo:
     emitPseudoInstruction(MI);
     break;
@@ -509,6 +510,22 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
   switch (Opcode) {
   default:
     abort(); // FIXME:
+  case TargetInstrInfo::INLINEASM: {
+    const char* Value = MI.getOperand(0).getSymbolName();
+    /* We allow inline assembler nodes with empty bodies - they can
+       implicitly define registers, which is ok for JIT. */
+    assert((Value[0] == 0) && "JIT does not support inline asm!\n");
+    break;
+  }
+  case TargetInstrInfo::DBG_LABEL:
+  case TargetInstrInfo::EH_LABEL:
+    MCE.emitLabel(MI.getOperand(0).getImm());
+    break;
+  case TargetInstrInfo::IMPLICIT_DEF:
+  case TargetInstrInfo::DECLARE:
+  case ARM::DWARF_LOC:
+    // Do nothing.
+    break;
   case ARM::CONSTPOOL_ENTRY:
     emitConstPoolInstruction(MI);
     break;
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index c2d8df31a6..9a1e1c2bb7 100644
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -19,35 +19,35 @@ class Format<bits<5> val> {
   bits<5> Value = val;
 }
 
-def Pseudo        : Format<1>;
-def MulFrm        : Format<2>;
-def BrFrm         : Format<3>;
-def BrMiscFrm     : Format<4>;
-
-def DPFrm         : Format<5>;
-def DPSoRegFrm    : Format<6>;
-
-def LdFrm         : Format<7>;
-def StFrm         : Format<8>;
-def LdMiscFrm     : Format<9>;
-def StMiscFrm     : Format<10>;
-def LdStMulFrm    : Format<11>;
-
-def ArithMiscFrm  : Format<12>;
-def ExtFrm        : Format<13>;
-
-def VFPUnaryFrm   : Format<14>;
-def VFPBinaryFrm  : Format<15>;
-def VFPConv1Frm   : Format<16>;
-def VFPConv2Frm   : Format<17>;
-def VFPConv3Frm   : Format<18>;
-def VFPConv4Frm   : Format<19>;
-def VFPConv5Frm   : Format<20>;
-def VFPLdStFrm    : Format<21>;
-def VFPLdStMulFrm : Format<22>;
-def VFPMiscFrm    : Format<23>;
-
-def ThumbFrm      : Format<24>;
+def Pseudo        : Format<0>;
+def MulFrm        : Format<1>;
+def BrFrm         : Format<2>;
+def BrMiscFrm     : Format<3>;
+
+def DPFrm         : Format<4>;
+def DPSoRegFrm    : Format<5>;
+
+def LdFrm         : Format<6>;
+def StFrm         : Format<7>;
+def LdMiscFrm     : Format<8>;
+def StMiscFrm     : Format<9>;
+def LdStMulFrm    : Format<10>;
+
+def ArithMiscFrm  : Format<11>;
+def ExtFrm        : Format<12>;
+
+def VFPUnaryFrm   : Format<13>;
+def VFPBinaryFrm  : Format<14>;
+def VFPConv1Frm   : Format<15>;
+def VFPConv2Frm   : Format<16>;
+def VFPConv3Frm   : Format<17>;
+def VFPConv4Frm   : Format<18>;
+def VFPConv5Frm   : Format<19>;
+def VFPLdStFrm    : Format<20>;
+def VFPLdStMulFrm : Format<21>;
+def VFPMiscFrm    : Format<22>;
+
+def ThumbFrm      : Format<23>;
 
 // Misc flag for data processing instructions that indicates whether
 // the instruction has a Rn register operand.
diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 476e5fd254..3843860543 100644
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -73,46 +73,46 @@ namespace ARMII {
     FormMask      = 0x1f << FormShift,
 
     // Pseudo instructions
-    Pseudo        = 1  << FormShift,
+    Pseudo        = 0  << FormShift,
 
     // Multiply instructions
-    MulFrm        = 2  << FormShift,
+    MulFrm        = 1  << FormShift,
 
     // Branch instructions
-    BrFrm         = 3  << FormShift,
-    BrMiscFrm     = 4  << FormShift,
+    BrFrm         = 2  << FormShift,
+    BrMiscFrm     = 3  << FormShift,
 
     // Data Processing instructions
-    DPFrm         = 5  << FormShift,
-    DPSoRegFrm    = 6  << FormShift,
+    DPFrm         = 4  << FormShift,
+    DPSoRegFrm    = 5  << FormShift,
 
     // Load and Store
-    LdFrm         = 7  << FormShift,
-    StFrm         = 8  << FormShift,
-    LdMiscFrm     = 9  << FormShift,
-    StMiscFrm     = 10 << FormShift,
-    LdStMulFrm    = 11 << FormShift,
+    LdFrm         = 6  << FormShift,
+    StFrm         = 7  << FormShift,
+    LdMiscFrm     = 8  << FormShift,
+    StMiscFrm     = 9  << FormShift,
+    LdStMulFrm    = 10 << FormShift,
 
     // Miscellaneous arithmetic instructions
-    ArithMiscFrm  = 12 << FormShift,
+    ArithMiscFrm  = 11 << FormShift,
 
     // Extend instructions
-    ExtFrm        = 13 << FormShift,
+    ExtFrm        = 12 << FormShift,
 
     // VFP formats
-    VFPUnaryFrm   = 14 << FormShift,
-    VFPBinaryFrm  = 15 << FormShift,
-    VFPConv1Frm   = 16 << FormShift,
-    VFPConv2Frm   = 17 << FormShift,
-    VFPConv3Frm   = 18 << FormShift,
-    VFPConv4Frm   = 19 << FormShift,
-    VFPConv5Frm   = 20 << FormShift,
-    VFPLdStFrm    = 21 << FormShift,
-    VFPLdStMulFrm = 22 << FormShift,
-    VFPMiscFrm    = 23 << FormShift,
+    VFPUnaryFrm   = 13 << FormShift,
+    VFPBinaryFrm  = 14 << FormShift,
+    VFPConv1Frm   = 15 << FormShift,
+    VFPConv2Frm   = 16 << FormShift,
+    VFPConv3Frm   = 17 << FormShift,
+    VFPConv4Frm   = 18 << FormShift,
+    VFPConv5Frm   = 19 << FormShift,
+    VFPLdStFrm    = 20 << FormShift,
+    VFPLdStMulFrm = 21 << FormShift,
+    VFPMiscFrm    = 22 << FormShift,
 
     // Thumb format
-    ThumbFrm      = 24 << FormShift,
+    ThumbFrm      = 23 << FormShift,
 
     //===------------------------------------------------------------------===//
     // Field shifts - such shifts are used to set field while generating