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authorAndrew Trick <atrick@apple.com>2013-09-25 00:26:16 +0000
committerAndrew Trick <atrick@apple.com>2013-09-25 00:26:16 +0000
commitdfca6eec3171802d6fcb091da01604ef4420fb3b (patch)
treeb98f73a5d345d399923c931a8d1f5d0e7be11f7e /lib
parenta26f4283826894ac00665f9d24fa99cacc5192ab (diff)
downloadexternal_llvm-dfca6eec3171802d6fcb091da01604ef4420fb3b.tar.gz
external_llvm-dfca6eec3171802d6fcb091da01604ef4420fb3b.tar.bz2
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CriticalAntiDepBreaker is no longer needed for armv7 scheduling.
This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMSubtarget.cpp4
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 4589a43ba1..3b34a2bca5 100644
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -282,8 +282,6 @@ bool ARMSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
- Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
- CriticalPathRCs.clear();
- CriticalPathRCs.push_back(&ARM::GPRRegClass);
+ Mode = TargetSubtargetInfo::ANTIDEP_NONE;
return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
}