Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55777 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 4 insertions, 2 deletions

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 51ef25a87c..f46777cd51 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -157,10 +157,10 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
   X86AddressMode AM;
   if (Op1)
     // Address is in register.
-    AM.Base.Reg = Op0;
+    AM.Base.Reg = Op1;
   else
     AM.GV = cast<GlobalValue>(V);
-  addFullAddress(BuildMI(MBB, TII.get(Opc)), AM);
+  addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
   return true;
 }
 
@@ -255,6 +255,8 @@ X86FastISel::TargetSelectInstruction(Instruction *I)  {
   default: break;
   case Instruction::Load:
     return X86SelectLoad(I);
+  case Instruction::Store:
+    return X86SelectStore(I);
   }
 
   return false;