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authorSean Callanan <scallanan@apple.com>2009-09-12 02:25:20 +0000
committerSean Callanan <scallanan@apple.com>2009-09-12 02:25:20 +0000
commit6f8f462ba5ce2c567cff13c77761ea6ccc8d277d (patch)
treeca093502a1536a67e11558f223129d45c5cd2cfb /lib
parentb24222cd7d223b10c2e01e02f535f30453c6e4ca (diff)
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Added CMPS (string comparison) instructions for all
operand widths to the Intel instruction tables, for the purposes of the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81601 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/X86/X86Instr64bit.td2
-rw-r--r--lib/Target/X86/X86InstrInfo.td4
2 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index f165336fdb..353868a407 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -286,6 +286,8 @@ def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
+def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
+
// Fast system-call instructions
def SYSEXIT64 : RI<0x35, RawFrm,
(outs), (ins), "sysexit", []>, TB;
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 8c22bc61e6..fbb5fa938e 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -818,6 +818,10 @@ def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
+def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
+def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
+def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
+
let Defs = [RAX, RDX] in
def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
TB;