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| author | Lang Hames <lhames@gmail.com> | 2012-02-16 02:32:10 +0000 |
|---|---|---|
| committer | Lang Hames <lhames@gmail.com> | 2012-02-16 02:32:10 +0000 |
| commit | 1834df8384354217c59e1c5dd8bc091c11b8ca43 (patch) | |
| tree | b07b39558690dc2a2ef7efb24c1881d0ffded63f /lib | |
| parent | afae28b1c67171a567c6f0274a7dede83ac5d8f1 (diff) | |
| download | external_llvm-1834df8384354217c59e1c5dd8bc091c11b8ca43.tar.gz external_llvm-1834df8384354217c59e1c5dd8bc091c11b8ca43.tar.bz2 external_llvm-1834df8384354217c59e1c5dd8bc091c11b8ca43.zip | |
Oop - r150653 + r150654 broke one of my test cases. Backing out for now...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/MachineCSE.cpp | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 1 |
2 files changed, 4 insertions, 9 deletions
diff --git a/lib/CodeGen/MachineCSE.cpp b/lib/CodeGen/MachineCSE.cpp index 491a22caf0..3031d4588b 100644 --- a/lib/CodeGen/MachineCSE.cpp +++ b/lib/CodeGen/MachineCSE.cpp @@ -63,8 +63,6 @@ namespace { virtual void releaseMemory() { ScopeMap.clear(); Exps.clear(); - AllocatableRegs.clear(); - ReservedRegs.clear(); } private: @@ -78,8 +76,6 @@ namespace { ScopedHTType VNT; SmallVector<MachineInstr*, 64> Exps; unsigned CurrVN; - BitVector AllocatableRegs; - BitVector ReservedRegs; bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB); bool isPhysDefTriviallyDead(unsigned Reg, @@ -240,9 +236,9 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, return false; for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) { - if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i])) - // Avoid extending live range of physical registers if they are - //allocatable or reserved. + if (TRI->isInAllocatableClass(PhysDefs[i])) + // Avoid extending live range of physical registers unless + // they are unallocatable. return false; } CrossMBB = true; @@ -592,7 +588,5 @@ bool MachineCSE::runOnMachineFunction(MachineFunction &MF) { MRI = &MF.getRegInfo(); AA = &getAnalysis<AliasAnalysis>(); DT = &getAnalysis<MachineDominatorTree>(); - AllocatableRegs = TRI->getAllocatableSet(MF); - ReservedRegs = TRI->getReservedRegs(MF); return PerformCSE(DT->getRootNode()); } diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 9c8486c9bc..6a46e63626 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -79,6 +79,7 @@ getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(ARM::SP); Reserved.set(ARM::PC); + Reserved.set(ARM::FPSCR); if (TFI->hasFP(MF)) Reserved.set(FramePtr); if (hasBasePointer(MF)) |