Move some methods out of MachineInstr into MachineOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8

8 files changed, 23 insertions, 25 deletions

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 95f60ed2e6..55a98aa69e 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -216,7 +216,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   int FrameIndex = MI.getOperand(i).getFrameIndex();
 
   // Add the base register of R30 (SP) or R15 (FP).
-  MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30);
+  MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
 
   // Now add the frame object offset to the offset from the virtual frame index.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@@ -233,15 +233,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     //so in this case, we need to use a temporary register, and move the original
     //inst off the SP/FP
     //fix up the old:
-    MI.SetMachineOperandReg(i + 1, Alpha::R28);
-    MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
-                              getLower16(Offset));
+    MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
+    MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
     //insert the new
     MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
       .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
     MBB.insert(II, nMI);
   } else {
-    MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
+    MI.getOperand(i).ChangeToImmediate(Offset);
   }
 }
 
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 53fec20ec1..931921254c 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -155,7 +155,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
   // choose a base register: ( hasFP? framepointer : stack pointer )
   unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
   // Add the base register
-  MI.SetMachineOperandReg(i, BaseRegister);
+  MI.getOperand(i).ChangeToRegister(BaseRegister);
 
   // Now add the frame object offset to the offset from r1.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
@@ -168,7 +168,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
   // XXX: we use 'r22' as another hack+slash temporary register here :(
   if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
     //fix up the old:
-    MI.SetMachineOperandReg(i, IA64::r22);
+    MI.getOperand(i).ChangeToRegister(IA64::r22);
     MI.getOperand(i).setUse(); // mark r22 as being used
                                // (the bundler wants to know this)
     //insert the new
@@ -177,7 +177,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
     MBB.insert(II, nMI);
   } else { // it's big
     //fix up the old:
-    MI.SetMachineOperandReg(i, IA64::r22);
+    MI.getOperand(i).ChangeToRegister(IA64::r22);
     MI.getOperand(i).setUse(); // mark r22 as being used
                                // (the bundler wants to know this)
     MachineInstr* nMI;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 037928fb31..d71f357990 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -136,8 +136,8 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
   // Swap op1/op2
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
-  MI->SetMachineOperandReg(2, Reg1);
-  MI->SetMachineOperandReg(1, Reg2);
+  MI->getOperand(2).setReg(Reg1);
+  MI->getOperand(1).setReg(Reg2);
   
   // Swap the mask around.
   unsigned MB = MI->getOperand(4).getImmedValue();
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 24da5a378f..36cb869abd 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -294,7 +294,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   int FrameIndex = MI.getOperand(i).getFrameIndex();
 
   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
-  MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
 
   // Take into account whether it's an add or mem instruction
   unsigned OffIdx = (i == 2) ? 1 : 2;
@@ -321,8 +321,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
            "No indexed form of load or store available!");
     unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
     MI.setOpcode(NewOpcode);
-    MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
-    MI.SetMachineOperandReg(2, PPC::R0);
+    MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
+    MI.getOperand(2).ChangeToRegister(PPC::R0);
   } else {
     switch (MI.getOpcode()) {
     case PPC::LWA:
@@ -333,7 +333,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
       Offset >>= 2;    // The actual encoded value has the low two bits zero.
       break;
     }
-    MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
+    MI.getOperand(OffIdx).ChangeToImmediate(Offset);
   }
 }
 
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
index 70f203ccca..7073260c4a 100644
--- a/lib/Target/Sparc/FPMover.cpp
+++ b/lib/Target/Sparc/FPMover.cpp
@@ -104,8 +104,8 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
       else
         assert(0 && "Unknown opcode!");
         
-      MI->SetMachineOperandReg(0, EvenDestReg);
-      MI->SetMachineOperandReg(1, EvenSrcReg);
+      MI->getOperand(0).setReg(EvenDestReg);
+      MI->getOperand(1).setReg(EvenSrcReg);
       DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
       // Insert copy for the other half of the double.
       if (DestDReg != SrcDReg) {
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index d72ca74516..88cbc9c769 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -135,8 +135,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   if (Offset >= -4096 && Offset <= 4095) {
     // If the offset is small enough to fit in the immediate field, directly
     // encode it.
-    MI.SetMachineOperandReg(i, SP::I6);
-    MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset);
+    MI.getOperand(i).ChangeToRegister(SP::I6);
+    MI.getOperand(i+1).ChangeToImmediate(Offset);
   } else {
     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to 
     // scavenge a register here instead of reserving G1 all of the time.
@@ -146,9 +146,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     BuildMI(*MI.getParent(), II, SP::ADDrr, 2, 
             SP::G1).addReg(SP::G1).addReg(SP::I6);
     // Insert: G1+%lo(offset) into the user.
-    MI.SetMachineOperandReg(i, SP::G1);
-    MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate,
-                              Offset & ((1 << 10)-1));
+    MI.getOperand(i).ChangeToRegister(SP::G1);
+    MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
   }
 }
 
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 60dd28c90a..6377de8865 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -46,7 +46,7 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
          "This only knows how to commute register operands so far");
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(1).getReg();
-  MI->SetMachineOperandReg(2, Reg1);
-  MI->SetMachineOperandReg(1, Reg2);
+  MI->getOperand(2).setReg(Reg1);
+  MI->getOperand(1).setReg(Reg2);
   return MI;
 }
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 9f4a561d1a..e34b5112a6 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -665,7 +665,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
 
   // This must be part of a four operand memory reference.  Replace the
   // FrameIndex with base register with EBP.  Add add an offset to the offset.
-  MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
 
   // Now add the frame object offset to the offset from EBP.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
@@ -676,7 +676,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
   else
     Offset += 4;  // Skip the saved EBP
 
-  MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
+  MI.getOperand(i+3).ChangeToImmediate(Offset);
 }
 
 void