Codegen pass definition cleanup. No functionality.

Moving toward a uniform style of pass definition to allow easier target configuration.
Globally declare Pass ID.
Globally declare pass initializer.
Use INITIALIZE_PASS consistently.
Add a call to the initializer from CodeGen.cpp.
Remove redundant "createPass" functions and "getPassName" methods.

While cleaning up declarations, cleaned up comments (sorry for large diff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150100 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 20 insertions, 20 deletions

diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp
index 35d18d3a5b..44229ad73f 100644
--- a/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/lib/Target/ARM/ARMTargetMachine.cpp
@@ -170,7 +170,7 @@ bool ARMPassConfig::addPreSched2() {
 
   if (getOptLevel() != CodeGenOpt::None) {
     if (!getARMSubtarget().isThumb1Only())
-      PM.add(createIfConverterPass());
+      addPass(IfConverterID);
   }
   if (getARMSubtarget().isThumb2())
     PM.add(createThumb2ITBlockPass());
@@ -184,7 +184,7 @@ bool ARMPassConfig::addPreEmitPass() {
       PM.add(createThumb2SizeReductionPass());
 
     // Constant island pass work on unbundled instructions.
-    PM.add(createUnpackMachineBundlesPass());
+    addPass(UnpackMachineBundlesID);
   }
 
   PM.add(createARMConstantIslandPass());
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp
index fb55f7d1fe..1f7bdf052c 100644
--- a/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -120,7 +120,7 @@ bool HexagonPassConfig::addPostRegAlloc() {
 
 
 bool HexagonPassConfig::addPreSched2() {
-  PM.add(createIfConverterPass());
+  addPass(IfConverterID);
   return true;
 }
 
diff --git a/lib/Target/PTX/PTXTargetMachine.cpp b/lib/Target/PTX/PTXTargetMachine.cpp
index f96f3e3be0..0432a8bcbd 100644
--- a/lib/Target/PTX/PTXTargetMachine.cpp
+++ b/lib/Target/PTX/PTXTargetMachine.cpp
@@ -280,37 +280,37 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
   printAndVerify("After Instruction Selection");
 
   // Expand pseudo-instructions emitted by ISel.
-  PM.add(createExpandISelPseudosPass());
+  addPass(ExpandISelPseudosID);
 
   // Pre-ra tail duplication.
   if (getOptLevel() != CodeGenOpt::None) {
-    PM.add(createTailDuplicatePass());
+    addPass(TailDuplicateID);
     printAndVerify("After Pre-RegAlloc TailDuplicate");
   }
 
   // Optimize PHIs before DCE: removing dead PHI cycles may make more
   // instructions dead.
   if (getOptLevel() != CodeGenOpt::None)
-    PM.add(createOptimizePHIsPass());
+    addPass(OptimizePHIsID);
 
   // If the target requests it, assign local variables to stack slots relative
   // to one another and simplify frame index references where possible.
-  PM.add(createLocalStackSlotAllocationPass());
+  addPass(LocalStackSlotAllocationID);
 
   if (getOptLevel() != CodeGenOpt::None) {
     // With optimization, dead code should already be eliminated. However
     // there is one known exception: lowered code for arguments that are only
     // used by tail calls, where the tail calls reuse the incoming stack
     // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
-    PM.add(createDeadMachineInstructionElimPass());
+    addPass(DeadMachineInstructionElimID);
     printAndVerify("After codegen DCE pass");
 
-    PM.add(createMachineLICMPass());
-    PM.add(createMachineCSEPass());
-    PM.add(createMachineSinkingPass());
+    addPass(MachineLICMID);
+    addPass(MachineCSEID);
+    addPass(MachineSinkingID);
     printAndVerify("After Machine LICM, CSE and Sinking passes");
 
-    PM.add(createPeepholeOptimizerPass());
+    addPass(PeepholeOptimizerID);
     printAndVerify("After codegen peephole optimization pass");
   }
 
@@ -326,12 +326,12 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
   if (getOptLevel() != CodeGenOpt::None) {
     // FIXME: Re-enable coloring with register when it's capable of adding
     // kill markers.
-    PM.add(createStackSlotColoringPass());
+    addPass(StackSlotColoringID);
 
     // FIXME: Post-RA LICM has asserts that fire on virtual registers.
     // Run post-ra machine LICM to hoist reloads / remats.
     //if (!DisablePostRAMachineLICM)
-    //  PM.add(createMachineLICMPass(false));
+    //  addPass(MachineLICMPass(false));
 
     printAndVerify("After StackSlotColoring and postra Machine LICM");
   }
@@ -340,11 +340,11 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
   if (addPostRegAlloc())
     printAndVerify("After PostRegAlloc passes");
 
-  PM.add(createExpandPostRAPseudosPass());
+  addPass(ExpandPostRAPseudosID);
   printAndVerify("After ExpandPostRAPseudos");
 
   // Insert prolog/epilog code.  Eliminate abstract frame index references...
-  PM.add(createPrologEpilogCodeInserter());
+  addPass(PrologEpilogCodeInserterID);
   printAndVerify("After PrologEpilogCodeInserter");
 
   // Run pre-sched2 passes.
@@ -353,7 +353,7 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
 
   // Second pass scheduler.
   if (getOptLevel() != CodeGenOpt::None) {
-    PM.add(createPostRAScheduler());
+    addPass(PostRASchedulerID);
     printAndVerify("After PostRAScheduler");
   }
 
@@ -365,17 +365,17 @@ bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
 
   // Tail duplication.
   if (getOptLevel() != CodeGenOpt::None) {
-    PM.add(createTailDuplicatePass());
+    addPass(TailDuplicateID);
     printNoVerify("After TailDuplicate");
   }
 
-  PM.add(createGCMachineCodeAnalysisPass());
+  addPass(GCMachineCodeAnalysisID);
 
   //if (PrintGCInfo)
   //  PM.add(createGCInfoPrinter(dbgs()));
 
   if (getOptLevel() != CodeGenOpt::None) {
-    PM.add(createCodePlacementOptPass());
+    addPass(CodePlacementOptID);
     printNoVerify("After CodePlacementOpt");
   }