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authorEvan Cheng <evan.cheng@apple.com>2009-01-20 19:12:24 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-01-20 19:12:24 +0000
commit04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 (patch)
tree83e8495f021a9e995df02cb9df4ed332e369e336 /lib/Target/XCore/XCoreInstrInfo.cpp
parenta913f4fca947c195a675e04ba625fe9e67d1a865 (diff)
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Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.cpp')
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index 545a2852dc..1a16fe01f1 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -49,7 +49,10 @@ static bool isZeroImm(const MachineOperand &op) {
/// leave the source and dest operands in the passed parameters.
///
bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI,
- unsigned &SrcReg, unsigned &DstReg) const {
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SrcSR, unsigned &DstSR) const {
+ SrcSR = DstSR = 0; // No sub-registers.
+
// We look for 4 kinds of patterns here:
// add dst, src, 0
// sub dst, src, 0