The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 10 deletions

diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 0a4d671a4e..8cb0ccf380 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -165,11 +165,6 @@ namespace {
 class ARMMCInstrAnalysis : public MCInstrAnalysis {
 public:
   ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
-  virtual bool isBranch(const MCInst &Inst) const {
-    // Don't flag "bx lr" as a branch.
-    return MCInstrAnalysis::isBranch(Inst) && (Inst.getOpcode() != ARM::BX ||
-           Inst.getOperand(0).getReg() != ARM::LR);
-  }
 
   virtual bool isUnconditionalBranch(const MCInst &Inst) const {
     // BCCs with the "always" predicate are unconditional branches.
@@ -185,11 +180,6 @@ public:
     return MCInstrAnalysis::isConditionalBranch(Inst);
   }
 
-  virtual bool isReturn(const MCInst &Inst) const {
-    // Recognize "bx lr" as return.
-    return Inst.getOpcode() == ARM::BX && Inst.getOperand(0).getReg()==ARM::LR;
-  }
-
   uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
                           uint64_t Size) const {
     // We only handle PCRel branches for now.