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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-02-18 19:45:59 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-02-18 19:45:59 +0000
commit584bf7bb03e4cf1475b26851edcc1ddb66b85028 (patch)
tree8f7aa705e98d2655f8a322fb778e62bf2744d300 /lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
parent6309b3e9bed13e34cf8803509b7f6b642731353a (diff)
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Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp')
-rw-r--r--lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp9
1 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index aace2f9723..1499da00ae 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -397,7 +397,14 @@ void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNum);
- unsigned Mask = Op.getImm();
+ unsigned SpecRegRBit = Op.getImm() >> 4;
+ unsigned Mask = Op.getImm() & 0xf;
+
+ if (SpecRegRBit)
+ O << "spsr";
+ else
+ O << "cpsr";
+
if (Mask) {
O << '_';
if (Mask & 8) O << 'f';