ARM PKH shift ammount operand printing tweaks.

Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 5 deletions

diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index 9d1fdc1feb..4f97def26e 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1498,16 +1498,17 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
       MI.addOperand(MCOperand::CreateImm(Imm));
     } else {
       // Build the constant shift specifier operand.
-      unsigned bits2 = getShiftTypeBits(insn);
       unsigned imm5 = getShiftAmtBits(insn);
-      ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
-      unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
       // The PKHBT/PKHTB instructions have an implied shift type and so just
       // use a plain immediate for the amount.
       if (Opcode == ARM::t2PKHBT || Opcode == ARM::t2PKHTB)
-        MI.addOperand(MCOperand::CreateImm(ShAmt));
-      else
+        MI.addOperand(MCOperand::CreateImm(imm5));
+      else {
+        ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
+        unsigned bits2 = getShiftTypeBits(insn);
+        unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
         MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt)));
+      }
     }
     ++OpIdx;
   }