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authorJohnny Chen <johnny.chen@apple.com>2011-03-25 19:35:37 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-03-25 19:35:37 +0000
commitabeea57639b38b1c3c129a023aecb57eed61355e (patch)
tree5870ee443821863aac4f99524e63987edf9f538c /lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
parentb66a0976127c7eb491ee0dfd1eeaba81b5d4ac76 (diff)
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DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
rdar://problem/9182892 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h')
-rw-r--r--lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index 797968840b..a238306dd1 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1868,7 +1868,7 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
OpInfo[1].RegClass == ARM::GPRRegClassID &&
"Expect >= 3 operands and first two as reg operands");
- bool ThreeReg = (OpInfo[2].RegClass == ARM::GPRRegClassID);
+ bool ThreeReg = (OpInfo[2].RegClass > 0);
bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
@@ -1912,7 +1912,8 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
++OpIdx;
if (ThreeReg) {
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ // This could be an offset register or a TIED_TO register.
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
R2)));
++OpIdx;
}