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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-20 20:32:09 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-20 20:32:09 +0000 |
| commit | a0472dc4205d5f2cc4e9cc5a08c51625573a26ce (patch) | |
| tree | 230801a70a311dd335a2b19c012f598faffd4493 /lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | |
| parent | aeb7de764a99af5565f1a9c04a8439836efa6084 (diff) | |
| download | external_llvm-a0472dc4205d5f2cc4e9cc5a08c51625573a26ce.tar.gz external_llvm-a0472dc4205d5f2cc4e9cc5a08c51625573a26ce.tar.bz2 external_llvm-a0472dc4205d5f2cc4e9cc5a08c51625573a26ce.zip | |
ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 4a790a4ea7..9d1fdc1feb 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1502,7 +1502,12 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned imm5 = getShiftAmtBits(insn); ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift; unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp); - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt))); + // The PKHBT/PKHTB instructions have an implied shift type and so just + // use a plain immediate for the amount. + if (Opcode == ARM::t2PKHBT || Opcode == ARM::t2PKHTB) + MI.addOperand(MCOperand::CreateImm(ShAmt)); + else + MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt))); } ++OpIdx; } |